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<!DOCTYPE allinstrs PUBLIC "-//ARM//DTD allinstrs //EN" "allinstrs.dtd">
<allinstrs id="A64instructiondetails" xreflabel="Instruction Details">
  <title>Instruction Details</title>
  <para>This chapter describes each instruction.</para>
<file type="alphaindex" file="index.xml">
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<alphaindex>
  <toptitle instructionset="AArch32" />
  <iforms title="AArch32 -- Base Instructions (alphabetic order)">
    <iform iformfile="adc_i.xml" heading="ADC, ADCS (immediate)" id="ADC_i">Add with Carry (immediate).</iform>
    <iform iformfile="adc_r.xml" heading="ADC, ADCS (register)" id="ADC_r">Add with Carry (register).</iform>
    <iform iformfile="adc_rr.xml" heading="ADC, ADCS (register-shifted register)" id="ADC_rr">Add with Carry (register-shifted register).</iform>
    <iform iformfile="add_adr.xml" heading="ADD (immediate, to PC)" id="ADD_ADR">Add to PC: an alias of ADR.</iform>
    <iform iformfile="add_i.xml" heading="ADD, ADDS (immediate)" id="ADD_i">Add (immediate).</iform>
    <iform iformfile="add_r.xml" heading="ADD, ADDS (register)" id="ADD_r">Add (register).</iform>
    <iform iformfile="add_rr.xml" heading="ADD, ADDS (register-shifted register)" id="ADD_rr">Add (register-shifted register).</iform>
    <iform iformfile="add_sp_i.xml" heading="ADD, ADDS (SP plus immediate)" id="ADD_SP_i">Add to SP (immediate).</iform>
    <iform iformfile="add_sp_r.xml" heading="ADD, ADDS (SP plus register)" id="ADD_SP_r">Add to SP (register).</iform>
    <iform iformfile="adr.xml" heading="ADR" id="ADR">Form PC-relative address.</iform>
    <iform iformfile="and_i.xml" heading="AND, ANDS (immediate)" id="AND_i">Bitwise AND (immediate).</iform>
    <iform iformfile="and_r.xml" heading="AND, ANDS (register)" id="AND_r">Bitwise AND (register).</iform>
    <iform iformfile="and_rr.xml" heading="AND, ANDS (register-shifted register)" id="AND_rr">Bitwise AND (register-shifted register).</iform>
    <iform iformfile="asr_mov_r.xml" heading="ASR (immediate)" id="ASR_MOV_r">Arithmetic Shift Right (immediate): an alias of MOV, MOVS (register).</iform>
    <iform iformfile="asr_mov_rr.xml" heading="ASR (register)" id="ASR_MOV_rr">Arithmetic Shift Right (register): an alias of MOV, MOVS (register-shifted register).</iform>
    <iform iformfile="asrs_mov_r.xml" heading="ASRS (immediate)" id="ASRS_MOV_r">Arithmetic Shift Right, setting flags (immediate): an alias of MOV, MOVS (register).</iform>
    <iform iformfile="asrs_mov_rr.xml" heading="ASRS (register)" id="ASRS_MOV_rr">Arithmetic Shift Right, setting flags (register): an alias of MOV, MOVS (register-shifted register).</iform>
    <iform iformfile="b.xml" heading="B" id="B">Branch.</iform>
    <iform iformfile="bfc.xml" heading="BFC" id="BFC">Bit Field Clear.</iform>
    <iform iformfile="bfi.xml" heading="BFI" id="BFI">Bit Field Insert.</iform>
    <iform iformfile="bic_i.xml" heading="BIC, BICS (immediate)" id="BIC_i">Bitwise Bit Clear (immediate).</iform>
    <iform iformfile="bic_r.xml" heading="BIC, BICS (register)" id="BIC_r">Bitwise Bit Clear (register).</iform>
    <iform iformfile="bic_rr.xml" heading="BIC, BICS (register-shifted register)" id="BIC_rr">Bitwise Bit Clear (register-shifted register).</iform>
    <iform iformfile="bkpt.xml" heading="BKPT" id="BKPT">Breakpoint.</iform>
    <iform iformfile="bl_i.xml" heading="BL, BLX (immediate)" id="BL_i">Branch with Link and optional Exchange (immediate).</iform>
    <iform iformfile="blx_r.xml" heading="BLX (register)" id="BLX_r">Branch with Link and Exchange (register).</iform>
    <iform iformfile="bx.xml" heading="BX" id="BX">Branch and Exchange.</iform>
    <iform iformfile="bxj.xml" heading="BXJ" id="BXJ">Branch and Exchange, previously Branch and Exchange Jazelle.</iform>
    <iform iformfile="cbnz.xml" heading="CBNZ, CBZ" id="CBNZ">Compare and Branch on Nonzero or Zero.</iform>
    <iform iformfile="clrbhb.xml" heading="CLRBHB" id="CLRBHB">Clear Branch History.</iform>
    <iform iformfile="clrex.xml" heading="CLREX" id="CLREX">Clear-Exclusive.</iform>
    <iform iformfile="clz.xml" heading="CLZ" id="CLZ">Count Leading Zeros.</iform>
    <iform iformfile="cmn_i.xml" heading="CMN (immediate)" id="CMN_i">Compare Negative (immediate).</iform>
    <iform iformfile="cmn_r.xml" heading="CMN (register)" id="CMN_r">Compare Negative (register).</iform>
    <iform iformfile="cmn_rr.xml" heading="CMN (register-shifted register)" id="CMN_rr">Compare Negative (register-shifted register).</iform>
    <iform iformfile="cmp_i.xml" heading="CMP (immediate)" id="CMP_i">Compare (immediate).</iform>
    <iform iformfile="cmp_r.xml" heading="CMP (register)" id="CMP_r">Compare (register).</iform>
    <iform iformfile="cmp_rr.xml" heading="CMP (register-shifted register)" id="CMP_rr">Compare (register-shifted register).</iform>
    <iform iformfile="cps.xml" heading="CPS, CPSID, CPSIE" id="CPS">Change PE State.</iform>
    <iform iformfile="crc32.xml" heading="CRC32" id="CRC32">CRC32.</iform>
    <iform iformfile="crc32c.xml" heading="CRC32C" id="CRC32C">CRC32C.</iform>
    <iform iformfile="csdb.xml" heading="CSDB" id="CSDB">Consumption of Speculative Data Barrier.</iform>
    <iform iformfile="dbg.xml" heading="DBG" id="DBG">Debug hint.</iform>
    <iform iformfile="dcps1.xml" heading="DCPS1" id="DCPS1">Debug Change PE State to EL1.</iform>
    <iform iformfile="dcps2.xml" heading="DCPS2" id="DCPS2">Debug Change PE State to EL2.</iform>
    <iform iformfile="dcps3.xml" heading="DCPS3" id="DCPS3">Debug Change PE State to EL3.</iform>
    <iform iformfile="dmb.xml" heading="DMB" id="DMB">Data Memory Barrier.</iform>
    <iform iformfile="dsb.xml" heading="DSB" id="DSB">Data Synchronization Barrier.</iform>
    <iform iformfile="eor_i.xml" heading="EOR, EORS (immediate)" id="EOR_i">Bitwise Exclusive-OR (immediate).</iform>
    <iform iformfile="eor_r.xml" heading="EOR, EORS (register)" id="EOR_r">Bitwise Exclusive-OR (register).</iform>
    <iform iformfile="eor_rr.xml" heading="EOR, EORS (register-shifted register)" id="EOR_rr">Bitwise Exclusive-OR (register-shifted register).</iform>
    <iform iformfile="eret.xml" heading="ERET" id="ERET">Exception Return.</iform>
    <iform iformfile="esb.xml" heading="ESB" id="ESB">Error Synchronization Barrier.</iform>
    <iform iformfile="hlt.xml" heading="HLT" id="HLT">Halting Breakpoint.</iform>
    <iform iformfile="hvc.xml" heading="HVC" id="HVC">Hypervisor Call.</iform>
    <iform iformfile="isb.xml" heading="ISB" id="ISB">Instruction Synchronization Barrier.</iform>
    <iform iformfile="it.xml" heading="IT" id="IT">If-Then.</iform>
    <iform iformfile="lda.xml" heading="LDA" id="LDA">Load-Acquire Word.</iform>
    <iform iformfile="ldab.xml" heading="LDAB" id="LDAB">Load-Acquire Byte.</iform>
    <iform iformfile="ldaex.xml" heading="LDAEX" id="LDAEX">Load-Acquire Exclusive Word.</iform>
    <iform iformfile="ldaexb.xml" heading="LDAEXB" id="LDAEXB">Load-Acquire Exclusive Byte.</iform>
    <iform iformfile="ldaexd.xml" heading="LDAEXD" id="LDAEXD">Load-Acquire Exclusive Doubleword.</iform>
    <iform iformfile="ldaexh.xml" heading="LDAEXH" id="LDAEXH">Load-Acquire Exclusive Halfword.</iform>
    <iform iformfile="ldah.xml" heading="LDAH" id="LDAH">Load-Acquire Halfword.</iform>
    <iform iformfile="ldc_i.xml" heading="LDC (immediate)" id="LDC_i">Load data to System register (immediate).</iform>
    <iform iformfile="ldc_l.xml" heading="LDC (literal)" id="LDC_l">Load data to System register (literal).</iform>
    <iform iformfile="ldm_e.xml" heading="LDM (exception return)" id="LDM_e">Load Multiple (exception return).</iform>
    <iform iformfile="ldm_u.xml" heading="LDM (User registers)" id="LDM_u">Load Multiple (User registers).</iform>
    <iform iformfile="ldm.xml" heading="LDM, LDMIA, LDMFD" id="LDM">Load Multiple (Increment After, Full Descending).</iform>
    <iform iformfile="ldmda.xml" heading="LDMDA, LDMFA" id="LDMDA">Load Multiple Decrement After (Full Ascending).</iform>
    <iform iformfile="ldmdb.xml" heading="LDMDB, LDMEA" id="LDMDB">Load Multiple Decrement Before (Empty Ascending).</iform>
    <iform iformfile="ldmib.xml" heading="LDMIB, LDMED" id="LDMIB">Load Multiple Increment Before (Empty Descending).</iform>
    <iform iformfile="ldr_i.xml" heading="LDR (immediate)" id="LDR_i">Load Register (immediate).</iform>
    <iform iformfile="ldr_l.xml" heading="LDR (literal)" id="LDR_l">Load Register (literal).</iform>
    <iform iformfile="ldr_r.xml" heading="LDR (register)" id="LDR_r">Load Register (register).</iform>
    <iform iformfile="ldrb_i.xml" heading="LDRB (immediate)" id="LDRB_i">Load Register Byte (immediate).</iform>
    <iform iformfile="ldrb_l.xml" heading="LDRB (literal)" id="LDRB_l">Load Register Byte (literal).</iform>
    <iform iformfile="ldrb_r.xml" heading="LDRB (register)" id="LDRB_r">Load Register Byte (register).</iform>
    <iform iformfile="ldrbt.xml" heading="LDRBT" id="LDRBT">Load Register Byte Unprivileged.</iform>
    <iform iformfile="ldrd_i.xml" heading="LDRD (immediate)" id="LDRD_i">Load Register Dual (immediate).</iform>
    <iform iformfile="ldrd_l.xml" heading="LDRD (literal)" id="LDRD_l">Load Register Dual (literal).</iform>
    <iform iformfile="ldrd_r.xml" heading="LDRD (register)" id="LDRD_r">Load Register Dual (register).</iform>
    <iform iformfile="ldrex.xml" heading="LDREX" id="LDREX">Load Register Exclusive.</iform>
    <iform iformfile="ldrexb.xml" heading="LDREXB" id="LDREXB">Load Register Exclusive Byte.</iform>
    <iform iformfile="ldrexd.xml" heading="LDREXD" id="LDREXD">Load Register Exclusive Doubleword.</iform>
    <iform iformfile="ldrexh.xml" heading="LDREXH" id="LDREXH">Load Register Exclusive Halfword.</iform>
    <iform iformfile="ldrh_i.xml" heading="LDRH (immediate)" id="LDRH_i">Load Register Halfword (immediate).</iform>
    <iform iformfile="ldrh_l.xml" heading="LDRH (literal)" id="LDRH_l">Load Register Halfword (literal).</iform>
    <iform iformfile="ldrh_r.xml" heading="LDRH (register)" id="LDRH_r">Load Register Halfword (register).</iform>
    <iform iformfile="ldrht.xml" heading="LDRHT" id="LDRHT">Load Register Halfword Unprivileged.</iform>
    <iform iformfile="ldrsb_i.xml" heading="LDRSB (immediate)" id="LDRSB_i">Load Register Signed Byte (immediate).</iform>
    <iform iformfile="ldrsb_l.xml" heading="LDRSB (literal)" id="LDRSB_l">Load Register Signed Byte (literal).</iform>
    <iform iformfile="ldrsb_r.xml" heading="LDRSB (register)" id="LDRSB_r">Load Register Signed Byte (register).</iform>
    <iform iformfile="ldrsbt.xml" heading="LDRSBT" id="LDRSBT">Load Register Signed Byte Unprivileged.</iform>
    <iform iformfile="ldrsh_i.xml" heading="LDRSH (immediate)" id="LDRSH_i">Load Register Signed Halfword (immediate).</iform>
    <iform iformfile="ldrsh_l.xml" heading="LDRSH (literal)" id="LDRSH_l">Load Register Signed Halfword (literal).</iform>
    <iform iformfile="ldrsh_r.xml" heading="LDRSH (register)" id="LDRSH_r">Load Register Signed Halfword (register).</iform>
    <iform iformfile="ldrsht.xml" heading="LDRSHT" id="LDRSHT">Load Register Signed Halfword Unprivileged.</iform>
    <iform iformfile="ldrt.xml" heading="LDRT" id="LDRT">Load Register Unprivileged.</iform>
    <iform iformfile="lsl_mov_r.xml" heading="LSL (immediate)" id="LSL_MOV_r">Logical Shift Left (immediate): an alias of MOV, MOVS (register).</iform>
    <iform iformfile="lsl_mov_rr.xml" heading="LSL (register)" id="LSL_MOV_rr">Logical Shift Left (register): an alias of MOV, MOVS (register-shifted register).</iform>
    <iform iformfile="lsls_mov_r.xml" heading="LSLS (immediate)" id="LSLS_MOV_r">Logical Shift Left, setting flags (immediate): an alias of MOV, MOVS (register).</iform>
    <iform iformfile="lsls_mov_rr.xml" heading="LSLS (register)" id="LSLS_MOV_rr">Logical Shift Left, setting flags (register): an alias of MOV, MOVS (register-shifted register).</iform>
    <iform iformfile="lsr_mov_r.xml" heading="LSR (immediate)" id="LSR_MOV_r">Logical Shift Right (immediate): an alias of MOV, MOVS (register).</iform>
    <iform iformfile="lsr_mov_rr.xml" heading="LSR (register)" id="LSR_MOV_rr">Logical Shift Right (register): an alias of MOV, MOVS (register-shifted register).</iform>
    <iform iformfile="lsrs_mov_r.xml" heading="LSRS (immediate)" id="LSRS_MOV_r">Logical Shift Right, setting flags (immediate): an alias of MOV, MOVS (register).</iform>
    <iform iformfile="lsrs_mov_rr.xml" heading="LSRS (register)" id="LSRS_MOV_rr">Logical Shift Right, setting flags (register): an alias of MOV, MOVS (register-shifted register).</iform>
    <iform iformfile="mcr.xml" heading="MCR" id="MCR">Move to System register from general-purpose register or execute a System instruction.</iform>
    <iform iformfile="mcrr.xml" heading="MCRR" id="MCRR">Move to System register from two general-purpose registers.</iform>
    <iform iformfile="mla.xml" heading="MLA, MLAS" id="MLA">Multiply Accumulate.</iform>
    <iform iformfile="mls.xml" heading="MLS" id="MLS">Multiply and Subtract.</iform>
    <iform iformfile="mov_i.xml" heading="MOV, MOVS (immediate)" id="MOV_i">Move (immediate).</iform>
    <iform iformfile="mov_r.xml" heading="MOV, MOVS (register)" id="MOV_r">Move (register).</iform>
    <iform iformfile="mov_rr.xml" heading="MOV, MOVS (register-shifted register)" id="MOV_rr">Move (register-shifted register).</iform>
    <iform iformfile="movt.xml" heading="MOVT" id="MOVT">Move Top.</iform>
    <iform iformfile="mrc.xml" heading="MRC" id="MRC">Move to general-purpose register from System register.</iform>
    <iform iformfile="mrrc.xml" heading="MRRC" id="MRRC">Move to two general-purpose registers from System register.</iform>
    <iform iformfile="mrs.xml" heading="MRS" id="MRS">Move Special register to general-purpose register.</iform>
    <iform iformfile="mrs_br.xml" heading="MRS (Banked register)" id="MRS_br">Move Banked or Special register to general-purpose register.</iform>
    <iform iformfile="msr_br.xml" heading="MSR (Banked register)" id="MSR_br">Move general-purpose register to Banked or Special register.</iform>
    <iform iformfile="msr_i.xml" heading="MSR (immediate)" id="MSR_i">Move immediate value to Special register.</iform>
    <iform iformfile="msr_r.xml" heading="MSR (register)" id="MSR_r">Move general-purpose register to Special register.</iform>
    <iform iformfile="mul.xml" heading="MUL, MULS" id="MUL">Multiply.</iform>
    <iform iformfile="mvn_i.xml" heading="MVN, MVNS (immediate)" id="MVN_i">Bitwise NOT (immediate).</iform>
    <iform iformfile="mvn_r.xml" heading="MVN, MVNS (register)" id="MVN_r">Bitwise NOT (register).</iform>
    <iform iformfile="mvn_rr.xml" heading="MVN, MVNS (register-shifted register)" id="MVN_rr">Bitwise NOT (register-shifted register).</iform>
    <iform iformfile="nop.xml" heading="NOP" id="NOP">No Operation.</iform>
    <iform iformfile="orn_i.xml" heading="ORN, ORNS (immediate)" id="ORN_i">Bitwise OR NOT (immediate).</iform>
    <iform iformfile="orn_r.xml" heading="ORN, ORNS (register)" id="ORN_r">Bitwise OR NOT (register).</iform>
    <iform iformfile="orr_i.xml" heading="ORR, ORRS (immediate)" id="ORR_i">Bitwise OR (immediate).</iform>
    <iform iformfile="orr_r.xml" heading="ORR, ORRS (register)" id="ORR_r">Bitwise OR (register).</iform>
    <iform iformfile="orr_rr.xml" heading="ORR, ORRS (register-shifted register)" id="ORR_rr">Bitwise OR (register-shifted register).</iform>
    <iform iformfile="pkh.xml" heading="PKHBT, PKHTB" id="PKH">Pack Halfword.</iform>
    <iform iformfile="pld_l.xml" heading="PLD (literal)" id="PLD_l">Preload Data (literal).</iform>
    <iform iformfile="pld_i.xml" heading="PLD, PLDW (immediate)" id="PLD_i">Preload Data (immediate).</iform>
    <iform iformfile="pld_r.xml" heading="PLD, PLDW (register)" id="PLD_r">Preload Data (register).</iform>
    <iform iformfile="pli_i.xml" heading="PLI (immediate, literal)" id="PLI_i">Preload Instruction (immediate, literal).</iform>
    <iform iformfile="pli_r.xml" heading="PLI (register)" id="PLI_r">Preload Instruction (register).</iform>
    <iform iformfile="pop.xml" heading="POP" id="POP">Pop Multiple Registers from Stack.</iform>
    <iform iformfile="pop_ldm.xml" heading="POP (multiple registers)" id="POP_LDM">Pop Multiple Registers from Stack: an alias of LDM, LDMIA, LDMFD.</iform>
    <iform iformfile="pop_ldr_i.xml" heading="POP (single register)" id="POP_LDR_i">Pop Single Register from Stack: an alias of LDR (immediate).</iform>
    <iform iformfile="pssbb.xml" heading="PSSBB" id="PSSBB">Physical Speculative Store Bypass Barrier.</iform>
    <iform iformfile="push.xml" heading="PUSH" id="PUSH">Push Multiple Registers to Stack.</iform>
    <iform iformfile="push_stmdb.xml" heading="PUSH (multiple registers)" id="PUSH_STMDB">Push multiple registers to Stack: an alias of STMDB, STMFD.</iform>
    <iform iformfile="push_str_i.xml" heading="PUSH (single register)" id="PUSH_STR_i">Push Single Register to Stack: an alias of STR (immediate).</iform>
    <iform iformfile="qadd.xml" heading="QADD" id="QADD">Saturating Add.</iform>
    <iform iformfile="qadd16.xml" heading="QADD16" id="QADD16">Saturating Add 16.</iform>
    <iform iformfile="qadd8.xml" heading="QADD8" id="QADD8">Saturating Add 8.</iform>
    <iform iformfile="qasx.xml" heading="QASX" id="QASX">Saturating Add and Subtract with Exchange.</iform>
    <iform iformfile="qdadd.xml" heading="QDADD" id="QDADD">Saturating Double and Add.</iform>
    <iform iformfile="qdsub.xml" heading="QDSUB" id="QDSUB">Saturating Double and Subtract.</iform>
    <iform iformfile="qsax.xml" heading="QSAX" id="QSAX">Saturating Subtract and Add with Exchange.</iform>
    <iform iformfile="qsub.xml" heading="QSUB" id="QSUB">Saturating Subtract.</iform>
    <iform iformfile="qsub16.xml" heading="QSUB16" id="QSUB16">Saturating Subtract 16.</iform>
    <iform iformfile="qsub8.xml" heading="QSUB8" id="QSUB8">Saturating Subtract 8.</iform>
    <iform iformfile="rbit.xml" heading="RBIT" id="RBIT">Reverse Bits.</iform>
    <iform iformfile="rev.xml" heading="REV" id="REV">Byte-Reverse Word.</iform>
    <iform iformfile="rev16.xml" heading="REV16" id="REV16">Byte-Reverse Packed Halfword.</iform>
    <iform iformfile="revsh.xml" heading="REVSH" id="REVSH">Byte-Reverse Signed Halfword.</iform>
    <iform iformfile="rfe.xml" heading="RFE, RFEDA, RFEDB, RFEIA, RFEIB" id="RFE">Return From Exception.</iform>
    <iform iformfile="ror_mov_r.xml" heading="ROR (immediate)" id="ROR_MOV_r">Rotate Right (immediate): an alias of MOV, MOVS (register).</iform>
    <iform iformfile="ror_mov_rr.xml" heading="ROR (register)" id="ROR_MOV_rr">Rotate Right (register): an alias of MOV, MOVS (register-shifted register).</iform>
    <iform iformfile="rors_mov_r.xml" heading="RORS (immediate)" id="RORS_MOV_r">Rotate Right, setting flags (immediate): an alias of MOV, MOVS (register).</iform>
    <iform iformfile="rors_mov_rr.xml" heading="RORS (register)" id="RORS_MOV_rr">Rotate Right, setting flags (register): an alias of MOV, MOVS (register-shifted register).</iform>
    <iform iformfile="rrx_mov_r.xml" heading="RRX" id="RRX_MOV_r">Rotate Right with Extend: an alias of MOV, MOVS (register).</iform>
    <iform iformfile="rrxs_mov_r.xml" heading="RRXS" id="RRXS_MOV_r">Rotate Right with Extend, setting flags: an alias of MOV, MOVS (register).</iform>
    <iform iformfile="rsb_i.xml" heading="RSB, RSBS (immediate)" id="RSB_i">Reverse Subtract (immediate).</iform>
    <iform iformfile="rsb_r.xml" heading="RSB, RSBS (register)" id="RSB_r">Reverse Subtract (register).</iform>
    <iform iformfile="rsb_rr.xml" heading="RSB, RSBS (register-shifted register)" id="RSB_rr">Reverse Subtract (register-shifted register).</iform>
    <iform iformfile="rsc_i.xml" heading="RSC, RSCS (immediate)" id="RSC_i">Reverse Subtract with Carry (immediate).</iform>
    <iform iformfile="rsc_r.xml" heading="RSC, RSCS (register)" id="RSC_r">Reverse Subtract with Carry (register).</iform>
    <iform iformfile="rsc_rr.xml" heading="RSC, RSCS (register-shifted register)" id="RSC_rr">Reverse Subtract (register-shifted register).</iform>
    <iform iformfile="sadd16.xml" heading="SADD16" id="SADD16">Signed Add 16.</iform>
    <iform iformfile="sadd8.xml" heading="SADD8" id="SADD8">Signed Add 8.</iform>
    <iform iformfile="sasx.xml" heading="SASX" id="SASX">Signed Add and Subtract with Exchange.</iform>
    <iform iformfile="sb.xml" heading="SB" id="SB">Speculation Barrier.</iform>
    <iform iformfile="sbc_i.xml" heading="SBC, SBCS (immediate)" id="SBC_i">Subtract with Carry (immediate).</iform>
    <iform iformfile="sbc_r.xml" heading="SBC, SBCS (register)" id="SBC_r">Subtract with Carry (register).</iform>
    <iform iformfile="sbc_rr.xml" heading="SBC, SBCS (register-shifted register)" id="SBC_rr">Subtract with Carry (register-shifted register).</iform>
    <iform iformfile="sbfx.xml" heading="SBFX" id="SBFX">Signed Bit Field Extract.</iform>
    <iform iformfile="sdiv.xml" heading="SDIV" id="SDIV">Signed Divide.</iform>
    <iform iformfile="sel.xml" heading="SEL" id="SEL">Select Bytes.</iform>
    <iform iformfile="setend.xml" heading="SETEND" id="SETEND">Set Endianness.</iform>
    <iform iformfile="setpan.xml" heading="SETPAN" id="SETPAN">Set Privileged Access Never.</iform>
    <iform iformfile="sev.xml" heading="SEV" id="SEV">Send Event.</iform>
    <iform iformfile="sevl.xml" heading="SEVL" id="SEVL">Send Event Local.</iform>
    <iform iformfile="shadd16.xml" heading="SHADD16" id="SHADD16">Signed Halving Add 16.</iform>
    <iform iformfile="shadd8.xml" heading="SHADD8" id="SHADD8">Signed Halving Add 8.</iform>
    <iform iformfile="shasx.xml" heading="SHASX" id="SHASX">Signed Halving Add and Subtract with Exchange.</iform>
    <iform iformfile="shsax.xml" heading="SHSAX" id="SHSAX">Signed Halving Subtract and Add with Exchange.</iform>
    <iform iformfile="shsub16.xml" heading="SHSUB16" id="SHSUB16">Signed Halving Subtract 16.</iform>
    <iform iformfile="shsub8.xml" heading="SHSUB8" id="SHSUB8">Signed Halving Subtract 8.</iform>
    <iform iformfile="smc.xml" heading="SMC" id="SMC">Secure Monitor Call.</iform>
    <iform iformfile="smlabb.xml" heading="SMLABB, SMLABT, SMLATB, SMLATT" id="SMLABB">Signed Multiply Accumulate (halfwords).</iform>
    <iform iformfile="smlad.xml" heading="SMLAD, SMLADX" id="SMLAD">Signed Multiply Accumulate Dual.</iform>
    <iform iformfile="smlal.xml" heading="SMLAL, SMLALS" id="SMLAL">Signed Multiply Accumulate Long.</iform>
    <iform iformfile="smlalbb.xml" heading="SMLALBB, SMLALBT, SMLALTB, SMLALTT" id="SMLALBB">Signed Multiply Accumulate Long (halfwords).</iform>
    <iform iformfile="smlald.xml" heading="SMLALD, SMLALDX" id="SMLALD">Signed Multiply Accumulate Long Dual.</iform>
    <iform iformfile="smlawb.xml" heading="SMLAWB, SMLAWT" id="SMLAWB">Signed Multiply Accumulate (word by halfword).</iform>
    <iform iformfile="smlsd.xml" heading="SMLSD, SMLSDX" id="SMLSD">Signed Multiply Subtract Dual.</iform>
    <iform iformfile="smlsld.xml" heading="SMLSLD, SMLSLDX" id="SMLSLD">Signed Multiply Subtract Long Dual.</iform>
    <iform iformfile="smmla.xml" heading="SMMLA, SMMLAR" id="SMMLA">Signed Most Significant Word Multiply Accumulate.</iform>
    <iform iformfile="smmls.xml" heading="SMMLS, SMMLSR" id="SMMLS">Signed Most Significant Word Multiply Subtract.</iform>
    <iform iformfile="smmul.xml" heading="SMMUL, SMMULR" id="SMMUL">Signed Most Significant Word Multiply.</iform>
    <iform iformfile="smuad.xml" heading="SMUAD, SMUADX" id="SMUAD">Signed Dual Multiply Add.</iform>
    <iform iformfile="smulbb.xml" heading="SMULBB, SMULBT, SMULTB, SMULTT" id="SMULBB">Signed Multiply (halfwords).</iform>
    <iform iformfile="smull.xml" heading="SMULL, SMULLS" id="SMULL">Signed Multiply Long.</iform>
    <iform iformfile="smulwb.xml" heading="SMULWB, SMULWT" id="SMULWB">Signed Multiply (word by halfword).</iform>
    <iform iformfile="smusd.xml" heading="SMUSD, SMUSDX" id="SMUSD">Signed Multiply Subtract Dual.</iform>
    <iform iformfile="srs.xml" heading="SRS, SRSDA, SRSDB, SRSIA, SRSIB" id="SRS">Store Return State.</iform>
    <iform iformfile="ssat.xml" heading="SSAT" id="SSAT">Signed Saturate.</iform>
    <iform iformfile="ssat16.xml" heading="SSAT16" id="SSAT16">Signed Saturate 16.</iform>
    <iform iformfile="ssax.xml" heading="SSAX" id="SSAX">Signed Subtract and Add with Exchange.</iform>
    <iform iformfile="ssbb.xml" heading="SSBB" id="SSBB">Speculative Store Bypass Barrier.</iform>
    <iform iformfile="ssub16.xml" heading="SSUB16" id="SSUB16">Signed Subtract 16.</iform>
    <iform iformfile="ssub8.xml" heading="SSUB8" id="SSUB8">Signed Subtract 8.</iform>
    <iform iformfile="stc.xml" heading="STC" id="STC">Store data to System register.</iform>
    <iform iformfile="stl.xml" heading="STL" id="STL">Store-Release Word.</iform>
    <iform iformfile="stlb.xml" heading="STLB" id="STLB">Store-Release Byte.</iform>
    <iform iformfile="stlex.xml" heading="STLEX" id="STLEX">Store-Release Exclusive Word.</iform>
    <iform iformfile="stlexb.xml" heading="STLEXB" id="STLEXB">Store-Release Exclusive Byte.</iform>
    <iform iformfile="stlexd.xml" heading="STLEXD" id="STLEXD">Store-Release Exclusive Doubleword.</iform>
    <iform iformfile="stlexh.xml" heading="STLEXH" id="STLEXH">Store-Release Exclusive Halfword.</iform>
    <iform iformfile="stlh.xml" heading="STLH" id="STLH">Store-Release Halfword.</iform>
    <iform iformfile="stm_u.xml" heading="STM (User registers)" id="STM_u">Store Multiple (User registers).</iform>
    <iform iformfile="stm.xml" heading="STM, STMIA, STMEA" id="STM">Store Multiple (Increment After, Empty Ascending).</iform>
    <iform iformfile="stmda.xml" heading="STMDA, STMED" id="STMDA">Store Multiple Decrement After (Empty Descending).</iform>
    <iform iformfile="stmdb.xml" heading="STMDB, STMFD" id="STMDB">Store Multiple Decrement Before (Full Descending).</iform>
    <iform iformfile="stmib.xml" heading="STMIB, STMFA" id="STMIB">Store Multiple Increment Before (Full Ascending).</iform>
    <iform iformfile="str_i.xml" heading="STR (immediate)" id="STR_i">Store Register (immediate).</iform>
    <iform iformfile="str_r.xml" heading="STR (register)" id="STR_r">Store Register (register).</iform>
    <iform iformfile="strb_i.xml" heading="STRB (immediate)" id="STRB_i">Store Register Byte (immediate).</iform>
    <iform iformfile="strb_r.xml" heading="STRB (register)" id="STRB_r">Store Register Byte (register).</iform>
    <iform iformfile="strbt.xml" heading="STRBT" id="STRBT">Store Register Byte Unprivileged.</iform>
    <iform iformfile="strd_i.xml" heading="STRD (immediate)" id="STRD_i">Store Register Dual (immediate).</iform>
    <iform iformfile="strd_r.xml" heading="STRD (register)" id="STRD_r">Store Register Dual (register).</iform>
    <iform iformfile="strex.xml" heading="STREX" id="STREX">Store Register Exclusive.</iform>
    <iform iformfile="strexb.xml" heading="STREXB" id="STREXB">Store Register Exclusive Byte.</iform>
    <iform iformfile="strexd.xml" heading="STREXD" id="STREXD">Store Register Exclusive Doubleword.</iform>
    <iform iformfile="strexh.xml" heading="STREXH" id="STREXH">Store Register Exclusive Halfword.</iform>
    <iform iformfile="strh_i.xml" heading="STRH (immediate)" id="STRH_i">Store Register Halfword (immediate).</iform>
    <iform iformfile="strh_r.xml" heading="STRH (register)" id="STRH_r">Store Register Halfword (register).</iform>
    <iform iformfile="strht.xml" heading="STRHT" id="STRHT">Store Register Halfword Unprivileged.</iform>
    <iform iformfile="strt.xml" heading="STRT" id="STRT">Store Register Unprivileged.</iform>
    <iform iformfile="sub_adr.xml" heading="SUB (immediate, from PC)" id="SUB_ADR">Subtract from PC: an alias of ADR.</iform>
    <iform iformfile="sub_i.xml" heading="SUB, SUBS (immediate)" id="SUB_i">Subtract (immediate).</iform>
    <iform iformfile="sub_r.xml" heading="SUB, SUBS (register)" id="SUB_r">Subtract (register).</iform>
    <iform iformfile="sub_rr.xml" heading="SUB, SUBS (register-shifted register)" id="SUB_rr">Subtract (register-shifted register).</iform>
    <iform iformfile="sub_sp_i.xml" heading="SUB, SUBS (SP minus immediate)" id="SUB_SP_i">Subtract from SP (immediate).</iform>
    <iform iformfile="sub_sp_r.xml" heading="SUB, SUBS (SP minus register)" id="SUB_SP_r">Subtract from SP (register).</iform>
    <iform iformfile="svc.xml" heading="SVC" id="SVC">Supervisor Call.</iform>
    <iform iformfile="sxtab.xml" heading="SXTAB" id="SXTAB">Signed Extend and Add Byte.</iform>
    <iform iformfile="sxtab16.xml" heading="SXTAB16" id="SXTAB16">Signed Extend and Add Byte 16.</iform>
    <iform iformfile="sxtah.xml" heading="SXTAH" id="SXTAH">Signed Extend and Add Halfword.</iform>
    <iform iformfile="sxtb.xml" heading="SXTB" id="SXTB">Signed Extend Byte.</iform>
    <iform iformfile="sxtb16.xml" heading="SXTB16" id="SXTB16">Signed Extend Byte 16.</iform>
    <iform iformfile="sxth.xml" heading="SXTH" id="SXTH">Signed Extend Halfword.</iform>
    <iform iformfile="tbb.xml" heading="TBB, TBH" id="TBB">Table Branch Byte or Halfword.</iform>
    <iform iformfile="teq_i.xml" heading="TEQ (immediate)" id="TEQ_i">Test Equivalence (immediate).</iform>
    <iform iformfile="teq_r.xml" heading="TEQ (register)" id="TEQ_r">Test Equivalence (register).</iform>
    <iform iformfile="teq_rr.xml" heading="TEQ (register-shifted register)" id="TEQ_rr">Test Equivalence (register-shifted register).</iform>
    <iform iformfile="tsb.xml" heading="TSB CSYNC" id="TSB">Trace Synchronization Barrier.</iform>
    <iform iformfile="tst_i.xml" heading="TST (immediate)" id="TST_i">Test (immediate).</iform>
    <iform iformfile="tst_r.xml" heading="TST (register)" id="TST_r">Test (register).</iform>
    <iform iformfile="tst_rr.xml" heading="TST (register-shifted register)" id="TST_rr">Test (register-shifted register).</iform>
    <iform iformfile="uadd16.xml" heading="UADD16" id="UADD16">Unsigned Add 16.</iform>
    <iform iformfile="uadd8.xml" heading="UADD8" id="UADD8">Unsigned Add 8.</iform>
    <iform iformfile="uasx.xml" heading="UASX" id="UASX">Unsigned Add and Subtract with Exchange.</iform>
    <iform iformfile="ubfx.xml" heading="UBFX" id="UBFX">Unsigned Bit Field Extract.</iform>
    <iform iformfile="udf.xml" heading="UDF" id="UDF">Permanently Undefined.</iform>
    <iform iformfile="udiv.xml" heading="UDIV" id="UDIV">Unsigned Divide.</iform>
    <iform iformfile="uhadd16.xml" heading="UHADD16" id="UHADD16">Unsigned Halving Add 16.</iform>
    <iform iformfile="uhadd8.xml" heading="UHADD8" id="UHADD8">Unsigned Halving Add 8.</iform>
    <iform iformfile="uhasx.xml" heading="UHASX" id="UHASX">Unsigned Halving Add and Subtract with Exchange.</iform>
    <iform iformfile="uhsax.xml" heading="UHSAX" id="UHSAX">Unsigned Halving Subtract and Add with Exchange.</iform>
    <iform iformfile="uhsub16.xml" heading="UHSUB16" id="UHSUB16">Unsigned Halving Subtract 16.</iform>
    <iform iformfile="uhsub8.xml" heading="UHSUB8" id="UHSUB8">Unsigned Halving Subtract 8.</iform>
    <iform iformfile="umaal.xml" heading="UMAAL" id="UMAAL">Unsigned Multiply Accumulate Accumulate Long.</iform>
    <iform iformfile="umlal.xml" heading="UMLAL, UMLALS" id="UMLAL">Unsigned Multiply Accumulate Long.</iform>
    <iform iformfile="umull.xml" heading="UMULL, UMULLS" id="UMULL">Unsigned Multiply Long.</iform>
    <iform iformfile="uqadd16.xml" heading="UQADD16" id="UQADD16">Unsigned Saturating Add 16.</iform>
    <iform iformfile="uqadd8.xml" heading="UQADD8" id="UQADD8">Unsigned Saturating Add 8.</iform>
    <iform iformfile="uqasx.xml" heading="UQASX" id="UQASX">Unsigned Saturating Add and Subtract with Exchange.</iform>
    <iform iformfile="uqsax.xml" heading="UQSAX" id="UQSAX">Unsigned Saturating Subtract and Add with Exchange.</iform>
    <iform iformfile="uqsub16.xml" heading="UQSUB16" id="UQSUB16">Unsigned Saturating Subtract 16.</iform>
    <iform iformfile="uqsub8.xml" heading="UQSUB8" id="UQSUB8">Unsigned Saturating Subtract 8.</iform>
    <iform iformfile="usad8.xml" heading="USAD8" id="USAD8">Unsigned Sum of Absolute Differences.</iform>
    <iform iformfile="usada8.xml" heading="USADA8" id="USADA8">Unsigned Sum of Absolute Differences and Accumulate.</iform>
    <iform iformfile="usat.xml" heading="USAT" id="USAT">Unsigned Saturate.</iform>
    <iform iformfile="usat16.xml" heading="USAT16" id="USAT16">Unsigned Saturate 16.</iform>
    <iform iformfile="usax.xml" heading="USAX" id="USAX">Unsigned Subtract and Add with Exchange.</iform>
    <iform iformfile="usub16.xml" heading="USUB16" id="USUB16">Unsigned Subtract 16.</iform>
    <iform iformfile="usub8.xml" heading="USUB8" id="USUB8">Unsigned Subtract 8.</iform>
    <iform iformfile="uxtab.xml" heading="UXTAB" id="UXTAB">Unsigned Extend and Add Byte.</iform>
    <iform iformfile="uxtab16.xml" heading="UXTAB16" id="UXTAB16">Unsigned Extend and Add Byte 16.</iform>
    <iform iformfile="uxtah.xml" heading="UXTAH" id="UXTAH">Unsigned Extend and Add Halfword.</iform>
    <iform iformfile="uxtb.xml" heading="UXTB" id="UXTB">Unsigned Extend Byte.</iform>
    <iform iformfile="uxtb16.xml" heading="UXTB16" id="UXTB16">Unsigned Extend Byte 16.</iform>
    <iform iformfile="uxth.xml" heading="UXTH" id="UXTH">Unsigned Extend Halfword.</iform>
    <iform iformfile="wfe.xml" heading="WFE" id="WFE">Wait For Event.</iform>
    <iform iformfile="wfi.xml" heading="WFI" id="WFI">Wait For Interrupt.</iform>
    <iform iformfile="yield.xml" heading="YIELD" id="YIELD">Yield hint.</iform>
  </iforms>
</alphaindex>
</file>
<file type="alphaindex" file="fpsimdindex.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<alphaindex>
  <toptitle instructionset="AArch32" />
  <iforms title="AArch32 -- SIMD&amp;FP Instructions (alphabetic order)">
    <iform iformfile="aesd.xml" heading="AESD" id="AESD">AES single round decryption.</iform>
    <iform iformfile="aese.xml" heading="AESE" id="AESE">AES single round encryption.</iform>
    <iform iformfile="aesimc.xml" heading="AESIMC" id="AESIMC">AES inverse mix columns.</iform>
    <iform iformfile="aesmc.xml" heading="AESMC" id="AESMC">AES mix columns.</iform>
    <iform iformfile="fldmx.xml" heading="FLDM*X (FLDMDBX, FLDMIAX)" id="FLDMX">FLDM*X.</iform>
    <iform iformfile="fstmx.xml" heading="FSTMDBX, FSTMIAX" id="FSTMX">FSTMX.</iform>
    <iform iformfile="sha1c.xml" heading="SHA1C" id="SHA1C">SHA1 hash update (choose).</iform>
    <iform iformfile="sha1h.xml" heading="SHA1H" id="SHA1H">SHA1 fixed rotate.</iform>
    <iform iformfile="sha1m.xml" heading="SHA1M" id="SHA1M">SHA1 hash update (majority).</iform>
    <iform iformfile="sha1p.xml" heading="SHA1P" id="SHA1P">SHA1 hash update (parity).</iform>
    <iform iformfile="sha1su0.xml" heading="SHA1SU0" id="SHA1SU0">SHA1 schedule update 0.</iform>
    <iform iformfile="sha1su1.xml" heading="SHA1SU1" id="SHA1SU1">SHA1 schedule update 1.</iform>
    <iform iformfile="sha256h.xml" heading="SHA256H" id="SHA256H">SHA256 hash update part 1.</iform>
    <iform iformfile="sha256h2.xml" heading="SHA256H2" id="SHA256H2">SHA256 hash update part 2.</iform>
    <iform iformfile="sha256su0.xml" heading="SHA256SU0" id="SHA256SU0">SHA256 schedule update 0.</iform>
    <iform iformfile="sha256su1.xml" heading="SHA256SU1" id="SHA256SU1">SHA256 schedule update 1.</iform>
    <iform iformfile="vaba.xml" heading="VABA" id="VABA">Vector Absolute Difference and Accumulate.</iform>
    <iform iformfile="vabal.xml" heading="VABAL" id="VABAL">Vector Absolute Difference and Accumulate Long.</iform>
    <iform iformfile="vabd_f.xml" heading="VABD (floating-point)" id="VABD_f">Vector Absolute Difference (floating-point).</iform>
    <iform iformfile="vabd_i.xml" heading="VABD (integer)" id="VABD_i">Vector Absolute Difference (integer).</iform>
    <iform iformfile="vabdl_i.xml" heading="VABDL (integer)" id="VABDL_i">Vector Absolute Difference Long (integer).</iform>
    <iform iformfile="vabs.xml" heading="VABS" id="VABS">Vector Absolute.</iform>
    <iform iformfile="vacge.xml" heading="VACGE" id="VACGE">Vector Absolute Compare Greater Than or Equal.</iform>
    <iform iformfile="vacgt.xml" heading="VACGT" id="VACGT">Vector Absolute Compare Greater Than.</iform>
    <iform iformfile="vacle_vacge.xml" heading="VACLE" id="VACLE_VACGE">Vector Absolute Compare Less Than or Equal: an alias of VACGE.</iform>
    <iform iformfile="vaclt_vacgt.xml" heading="VACLT" id="VACLT_VACGT">Vector Absolute Compare Less Than: an alias of VACGT.</iform>
    <iform iformfile="vadd_f.xml" heading="VADD (floating-point)" id="VADD_f">Vector Add (floating-point).</iform>
    <iform iformfile="vadd_i.xml" heading="VADD (integer)" id="VADD_i">Vector Add (integer).</iform>
    <iform iformfile="vaddhn.xml" heading="VADDHN" id="VADDHN">Vector Add and Narrow, returning High Half.</iform>
    <iform iformfile="vaddl.xml" heading="VADDL" id="VADDL">Vector Add Long.</iform>
    <iform iformfile="vaddw.xml" heading="VADDW" id="VADDW">Vector Add Wide.</iform>
    <iform iformfile="vand_vbic_i.xml" heading="VAND (immediate)" id="VAND_VBIC_i">Vector Bitwise AND (immediate): an alias of VBIC (immediate).</iform>
    <iform iformfile="vand_r.xml" heading="VAND (register)" id="VAND_r">Vector Bitwise AND (register).</iform>
    <iform iformfile="vbic_i.xml" heading="VBIC (immediate)" id="VBIC_i">Vector Bitwise Bit Clear (immediate).</iform>
    <iform iformfile="vbic_r.xml" heading="VBIC (register)" id="VBIC_r">Vector Bitwise Bit Clear (register).</iform>
    <iform iformfile="vbif.xml" heading="VBIF" id="VBIF">Vector Bitwise Insert if False.</iform>
    <iform iformfile="vbit.xml" heading="VBIT" id="VBIT">Vector Bitwise Insert if True.</iform>
    <iform iformfile="vbsl.xml" heading="VBSL" id="VBSL">Vector Bitwise Select.</iform>
    <iform iformfile="vcadd.xml" heading="VCADD" id="VCADD">Vector Complex Add.</iform>
    <iform iformfile="vceq_i.xml" heading="VCEQ (immediate #0)" id="VCEQ_i">Vector Compare Equal to Zero.</iform>
    <iform iformfile="vceq_r.xml" heading="VCEQ (register)" id="VCEQ_r">Vector Compare Equal.</iform>
    <iform iformfile="vcge_i.xml" heading="VCGE (immediate #0)" id="VCGE_i">Vector Compare Greater Than or Equal to Zero.</iform>
    <iform iformfile="vcge_r.xml" heading="VCGE (register)" id="VCGE_r">Vector Compare Greater Than or Equal.</iform>
    <iform iformfile="vcgt_i.xml" heading="VCGT (immediate #0)" id="VCGT_i">Vector Compare Greater Than Zero.</iform>
    <iform iformfile="vcgt_r.xml" heading="VCGT (register)" id="VCGT_r">Vector Compare Greater Than.</iform>
    <iform iformfile="vcle_i.xml" heading="VCLE (immediate #0)" id="VCLE_i">Vector Compare Less Than or Equal to Zero.</iform>
    <iform iformfile="vcle_vcge_r.xml" heading="VCLE (register)" id="VCLE_VCGE_r">Vector Compare Less Than or Equal: an alias of VCGE (register).</iform>
    <iform iformfile="vcls.xml" heading="VCLS" id="VCLS">Vector Count Leading Sign Bits.</iform>
    <iform iformfile="vclt_i.xml" heading="VCLT (immediate #0)" id="VCLT_i">Vector Compare Less Than Zero.</iform>
    <iform iformfile="vclt_vcgt_r.xml" heading="VCLT (register)" id="VCLT_VCGT_r">Vector Compare Less Than: an alias of VCGT (register).</iform>
    <iform iformfile="vclz.xml" heading="VCLZ" id="VCLZ">Vector Count Leading Zeros.</iform>
    <iform iformfile="vcmla.xml" heading="VCMLA" id="VCMLA">Vector Complex Multiply Accumulate.</iform>
    <iform iformfile="vcmla_s.xml" heading="VCMLA (by element)" id="VCMLA_s">Vector Complex Multiply Accumulate (by element).</iform>
    <iform iformfile="vcmp.xml" heading="VCMP" id="VCMP">Vector Compare.</iform>
    <iform iformfile="vcmpe.xml" heading="VCMPE" id="VCMPE">Vector Compare, raising Invalid Operation on NaN.</iform>
    <iform iformfile="vcnt.xml" heading="VCNT" id="VCNT">Vector Count Set Bits.</iform>
    <iform iformfile="vcvt_ds.xml" heading="VCVT (between double-precision and single-precision)" id="VCVT_ds">Convert between double-precision and single-precision.</iform>
    <iform iformfile="vcvt_xs.xml" heading="VCVT (between floating-point and fixed-point, Advanced SIMD)" id="VCVT_xs">Vector Convert between floating-point and fixed-point.</iform>
    <iform iformfile="vcvt_xv.xml" heading="VCVT (between floating-point and fixed-point, floating-point)" id="VCVT_xv">Convert between floating-point and fixed-point.</iform>
    <iform iformfile="vcvt_is.xml" heading="VCVT (between floating-point and integer, Advanced SIMD)" id="VCVT_is">Vector Convert between floating-point and integer.</iform>
    <iform iformfile="vcvt_hs.xml" heading="VCVT (between half-precision and single-precision, Advanced SIMD)" id="VCVT_hs">Vector Convert between half-precision and single-precision.</iform>
    <iform iformfile="vcvt_iv.xml" heading="VCVT (floating-point to integer, floating-point)" id="VCVT_iv">Convert floating-point to integer with Round towards Zero.</iform>
    <iform iformfile="vcvt_bfs.xml" heading="VCVT (from single-precision to BFloat16, Advanced SIMD)" id="VCVT_bfs">Vector Convert from single-precision to BFloat16.</iform>
    <iform iformfile="vcvt_vi.xml" heading="VCVT (integer to floating-point, floating-point)" id="VCVT_vi">Convert integer to floating-point.</iform>
    <iform iformfile="vcvta_asimd.xml" heading="VCVTA (Advanced SIMD)" id="VCVTA_asimd">Vector Convert floating-point to integer with Round to Nearest with Ties to Away.</iform>
    <iform iformfile="vcvta_vfp.xml" heading="VCVTA (floating-point)" id="VCVTA_vfp">Convert floating-point to integer with Round to Nearest with Ties to Away.</iform>
    <iform iformfile="vcvtb.xml" heading="VCVTB" id="VCVTB">Convert to or from a half-precision value in the bottom half of a single-precision register.</iform>
    <iform iformfile="vcvtb_bfs.xml" heading="VCVTB (BFloat16)" id="VCVTB_bfs">Converts from a single-precision value to a BFloat16 value in the bottom half of a single-precision register.</iform>
    <iform iformfile="vcvtm_asimd.xml" heading="VCVTM (Advanced SIMD)" id="VCVTM_asimd">Vector Convert floating-point to integer with Round towards -Infinity.</iform>
    <iform iformfile="vcvtm_vfp.xml" heading="VCVTM (floating-point)" id="VCVTM_vfp">Convert floating-point to integer with Round towards -Infinity.</iform>
    <iform iformfile="vcvtn_asimd.xml" heading="VCVTN (Advanced SIMD)" id="VCVTN_asimd">Vector Convert floating-point to integer with Round to Nearest.</iform>
    <iform iformfile="vcvtn_vfp.xml" heading="VCVTN (floating-point)" id="VCVTN_vfp">Convert floating-point to integer with Round to Nearest.</iform>
    <iform iformfile="vcvtp_asimd.xml" heading="VCVTP (Advanced SIMD)" id="VCVTP_asimd">Vector Convert floating-point to integer with Round towards +Infinity.</iform>
    <iform iformfile="vcvtp_vfp.xml" heading="VCVTP (floating-point)" id="VCVTP_vfp">Convert floating-point to integer with Round towards +Infinity.</iform>
    <iform iformfile="vcvtr_iv.xml" heading="VCVTR" id="VCVTR_iv">Convert floating-point to integer.</iform>
    <iform iformfile="vcvtt.xml" heading="VCVTT" id="VCVTT">Convert to or from a half-precision value in the top half of a single-precision register.</iform>
    <iform iformfile="vcvtt_bfs.xml" heading="VCVTT (BFloat16)" id="VCVTT_bfs">Converts from a single-precision value to a BFloat16 value in the top half of a single-precision register..</iform>
    <iform iformfile="vdiv.xml" heading="VDIV" id="VDIV">Divide.</iform>
    <iform iformfile="vdot_s.xml" heading="VDOT (by element)" id="VDOT_s">BFloat16 floating-point indexed dot product (vector, by element).</iform>
    <iform iformfile="vdot.xml" heading="VDOT (vector)" id="VDOT">BFloat16 floating-point (BF16) dot product (vector).</iform>
    <iform iformfile="vdup_r.xml" heading="VDUP (general-purpose register)" id="VDUP_r">Duplicate general-purpose register to vector.</iform>
    <iform iformfile="vdup_s.xml" heading="VDUP (scalar)" id="VDUP_s">Duplicate vector element to vector.</iform>
    <iform iformfile="veor.xml" heading="VEOR" id="VEOR">Vector Bitwise Exclusive-OR.</iform>
    <iform iformfile="vext.xml" heading="VEXT (byte elements)" id="VEXT">Vector Extract.</iform>
    <iform iformfile="vext_vext.xml" heading="VEXT (multibyte elements)" id="VEXT_VEXT">Vector Extract: an alias of VEXT (byte elements).</iform>
    <iform iformfile="vfma.xml" heading="VFMA" id="VFMA">Vector Fused Multiply Accumulate.</iform>
    <iform iformfile="vfma_bfs.xml" heading="VFMAB, VFMAT (BFloat16, by scalar)" id="VFMA_bfs">BFloat16 floating-point widening multiply-add long (by scalar).</iform>
    <iform iformfile="vfma_bf.xml" heading="VFMAB, VFMAT (BFloat16, vector)" id="VFMA_bf">BFloat16 floating-point widening multiply-add long (vector).</iform>
    <iform iformfile="vfmal_s.xml" heading="VFMAL (by scalar)" id="VFMAL_s">Vector Floating-point Multiply-Add Long to accumulator (by scalar).</iform>
    <iform iformfile="vfmal.xml" heading="VFMAL (vector)" id="VFMAL">Vector Floating-point Multiply-Add Long to accumulator (vector).</iform>
    <iform iformfile="vfms.xml" heading="VFMS" id="VFMS">Vector Fused Multiply Subtract.</iform>
    <iform iformfile="vfmsl_s.xml" heading="VFMSL (by scalar)" id="VFMSL_s">Vector Floating-point Multiply-Subtract Long from accumulator (by scalar).</iform>
    <iform iformfile="vfmsl.xml" heading="VFMSL (vector)" id="VFMSL">Vector Floating-point Multiply-Subtract Long from accumulator (vector).</iform>
    <iform iformfile="vfnma.xml" heading="VFNMA" id="VFNMA">Vector Fused Negate Multiply Accumulate.</iform>
    <iform iformfile="vfnms.xml" heading="VFNMS" id="VFNMS">Vector Fused Negate Multiply Subtract.</iform>
    <iform iformfile="vhadd.xml" heading="VHADD" id="VHADD">Vector Halving Add.</iform>
    <iform iformfile="vhsub.xml" heading="VHSUB" id="VHSUB">Vector Halving Subtract.</iform>
    <iform iformfile="vins.xml" heading="VINS" id="VINS">Vector move Insertion.</iform>
    <iform iformfile="vjcvt.xml" heading="VJCVT" id="VJCVT">Javascript Convert to signed fixed-point, rounding toward Zero.</iform>
    <iform iformfile="vld1_m.xml" heading="VLD1 (multiple single elements)" id="VLD1_m">Load multiple single 1-element structures to one, two, three, or four registers.</iform>
    <iform iformfile="vld1_a.xml" heading="VLD1 (single element to all lanes)" id="VLD1_a">Load single 1-element structure and replicate to all lanes of one register.</iform>
    <iform iformfile="vld1_1.xml" heading="VLD1 (single element to one lane)" id="VLD1_1">Load single 1-element structure to one lane of one register.</iform>
    <iform iformfile="vld2_m.xml" heading="VLD2 (multiple 2-element structures)" id="VLD2_m">Load multiple 2-element structures to two or four registers.</iform>
    <iform iformfile="vld2_a.xml" heading="VLD2 (single 2-element structure to all lanes)" id="VLD2_a">Load single 2-element structure and replicate to all lanes of two registers.</iform>
    <iform iformfile="vld2_1.xml" heading="VLD2 (single 2-element structure to one lane)" id="VLD2_1">Load single 2-element structure to one lane of two registers.</iform>
    <iform iformfile="vld3_m.xml" heading="VLD3 (multiple 3-element structures)" id="VLD3_m">Load multiple 3-element structures to three registers.</iform>
    <iform iformfile="vld3_a.xml" heading="VLD3 (single 3-element structure to all lanes)" id="VLD3_a">Load single 3-element structure and replicate to all lanes of three registers.</iform>
    <iform iformfile="vld3_1.xml" heading="VLD3 (single 3-element structure to one lane)" id="VLD3_1">Load single 3-element structure to one lane of three registers.</iform>
    <iform iformfile="vld4_m.xml" heading="VLD4 (multiple 4-element structures)" id="VLD4_m">Load multiple 4-element structures to four registers.</iform>
    <iform iformfile="vld4_a.xml" heading="VLD4 (single 4-element structure to all lanes)" id="VLD4_a">Load single 4-element structure and replicate to all lanes of four registers.</iform>
    <iform iformfile="vld4_1.xml" heading="VLD4 (single 4-element structure to one lane)" id="VLD4_1">Load single 4-element structure to one lane of four registers.</iform>
    <iform iformfile="vldm.xml" heading="VLDM, VLDMDB, VLDMIA" id="VLDM">Load Multiple SIMD&amp;FP registers.</iform>
    <iform iformfile="vldr_i.xml" heading="VLDR (immediate)" id="VLDR_i">Load SIMD&amp;FP register (immediate).</iform>
    <iform iformfile="vldr_l.xml" heading="VLDR (literal)" id="VLDR_l">Load SIMD&amp;FP register (literal).</iform>
    <iform iformfile="vmax_f.xml" heading="VMAX (floating-point)" id="VMAX_f">Vector Maximum (floating-point).</iform>
    <iform iformfile="vmax_i.xml" heading="VMAX (integer)" id="VMAX_i">Vector Maximum (integer).</iform>
    <iform iformfile="vmaxnm.xml" heading="VMAXNM" id="VMAXNM">Floating-point Maximum Number.</iform>
    <iform iformfile="vmin_f.xml" heading="VMIN (floating-point)" id="VMIN_f">Vector Minimum (floating-point).</iform>
    <iform iformfile="vmin_i.xml" heading="VMIN (integer)" id="VMIN_i">Vector Minimum (integer).</iform>
    <iform iformfile="vminnm.xml" heading="VMINNM" id="VMINNM">Floating-point Minimum Number.</iform>
    <iform iformfile="vmla_s.xml" heading="VMLA (by scalar)" id="VMLA_s">Vector Multiply Accumulate (by scalar).</iform>
    <iform iformfile="vmla_f.xml" heading="VMLA (floating-point)" id="VMLA_f">Vector Multiply Accumulate (floating-point).</iform>
    <iform iformfile="vmla_i.xml" heading="VMLA (integer)" id="VMLA_i">Vector Multiply Accumulate (integer).</iform>
    <iform iformfile="vmlal_s.xml" heading="VMLAL (by scalar)" id="VMLAL_s">Vector Multiply Accumulate Long (by scalar).</iform>
    <iform iformfile="vmlal_i.xml" heading="VMLAL (integer)" id="VMLAL_i">Vector Multiply Accumulate Long (integer).</iform>
    <iform iformfile="vmls_s.xml" heading="VMLS (by scalar)" id="VMLS_s">Vector Multiply Subtract (by scalar).</iform>
    <iform iformfile="vmls_f.xml" heading="VMLS (floating-point)" id="VMLS_f">Vector Multiply Subtract (floating-point).</iform>
    <iform iformfile="vmls_i.xml" heading="VMLS (integer)" id="VMLS_i">Vector Multiply Subtract (integer).</iform>
    <iform iformfile="vmlsl_s.xml" heading="VMLSL (by scalar)" id="VMLSL_s">Vector Multiply Subtract Long (by scalar).</iform>
    <iform iformfile="vmlsl_i.xml" heading="VMLSL (integer)" id="VMLSL_i">Vector Multiply Subtract Long (integer).</iform>
    <iform iformfile="vmmla.xml" heading="VMMLA" id="VMMLA">BFloat16 floating-point matrix multiply-accumulate.</iform>
    <iform iformfile="vmov_h.xml" heading="VMOV (between general-purpose register and half-precision)" id="VMOV_h">Copy 16 bits of a general-purpose register to or from a 32-bit SIMD&amp;FP register.</iform>
    <iform iformfile="vmov_s.xml" heading="VMOV (between general-purpose register and single-precision)" id="VMOV_s">Copy a general-purpose register to or from a 32-bit SIMD&amp;FP register.</iform>
    <iform iformfile="vmov_d.xml" heading="VMOV (between two general-purpose registers and a doubleword floating-point register)" id="VMOV_d">Copy two general-purpose registers to or from a SIMD&amp;FP register.</iform>
    <iform iformfile="vmov_ss.xml" heading="VMOV (between two general-purpose registers and two single-precision registers)" id="VMOV_ss">Copy two general-purpose registers to a pair of 32-bit SIMD&amp;FP registers.</iform>
    <iform iformfile="vmov_rs.xml" heading="VMOV (general-purpose register to scalar)" id="VMOV_rs">Copy a general-purpose register to a vector element.</iform>
    <iform iformfile="vmov_i.xml" heading="VMOV (immediate)" id="VMOV_i">Copy immediate value to a SIMD&amp;FP register.</iform>
    <iform iformfile="vmov_r.xml" heading="VMOV (register)" id="VMOV_r">Copy between FP registers.</iform>
    <iform iformfile="vmov_vorr_r.xml" heading="VMOV (register, SIMD)" id="VMOV_VORR_r">Copy between SIMD registers: an alias of VORR (register).</iform>
    <iform iformfile="vmov_sr.xml" heading="VMOV (scalar to general-purpose register)" id="VMOV_sr">Copy a vector element to a general-purpose register with sign or zero extension.</iform>
    <iform iformfile="vmovl.xml" heading="VMOVL" id="VMOVL">Vector Move Long.</iform>
    <iform iformfile="vmovn.xml" heading="VMOVN" id="VMOVN">Vector Move and Narrow.</iform>
    <iform iformfile="vmovx.xml" heading="VMOVX" id="VMOVX">Vector Move extraction.</iform>
    <iform iformfile="vmrs.xml" heading="VMRS" id="VMRS">Move SIMD&amp;FP Special register to general-purpose register.</iform>
    <iform iformfile="vmsr.xml" heading="VMSR" id="VMSR">Move general-purpose register to SIMD&amp;FP Special register.</iform>
    <iform iformfile="vmul_s.xml" heading="VMUL (by scalar)" id="VMUL_s">Vector Multiply (by scalar).</iform>
    <iform iformfile="vmul_f.xml" heading="VMUL (floating-point)" id="VMUL_f">Vector Multiply (floating-point).</iform>
    <iform iformfile="vmul_i.xml" heading="VMUL (integer and polynomial)" id="VMUL_i">Vector Multiply (integer and polynomial).</iform>
    <iform iformfile="vmull_s.xml" heading="VMULL (by scalar)" id="VMULL_s">Vector Multiply Long (by scalar).</iform>
    <iform iformfile="vmull_i.xml" heading="VMULL (integer and polynomial)" id="VMULL_i">Vector Multiply Long (integer and polynomial).</iform>
    <iform iformfile="vmvn_i.xml" heading="VMVN (immediate)" id="VMVN_i">Vector Bitwise NOT (immediate).</iform>
    <iform iformfile="vmvn_r.xml" heading="VMVN (register)" id="VMVN_r">Vector Bitwise NOT (register).</iform>
    <iform iformfile="vneg.xml" heading="VNEG" id="VNEG">Vector Negate.</iform>
    <iform iformfile="vnmla.xml" heading="VNMLA" id="VNMLA">Vector Negate Multiply Accumulate.</iform>
    <iform iformfile="vnmls.xml" heading="VNMLS" id="VNMLS">Vector Negate Multiply Subtract.</iform>
    <iform iformfile="vnmul.xml" heading="VNMUL" id="VNMUL">Vector Negate Multiply.</iform>
    <iform iformfile="vorn_vorr_i.xml" heading="VORN (immediate)" id="VORN_VORR_i">Vector Bitwise OR NOT (immediate): an alias of VORR (immediate).</iform>
    <iform iformfile="vorn_r.xml" heading="VORN (register)" id="VORN_r">Vector bitwise OR NOT (register).</iform>
    <iform iformfile="vorr_i.xml" heading="VORR (immediate)" id="VORR_i">Vector Bitwise OR (immediate).</iform>
    <iform iformfile="vorr_r.xml" heading="VORR (register)" id="VORR_r">Vector bitwise OR (register).</iform>
    <iform iformfile="vpadal.xml" heading="VPADAL" id="VPADAL">Vector Pairwise Add and Accumulate Long.</iform>
    <iform iformfile="vpadd_f.xml" heading="VPADD (floating-point)" id="VPADD_f">Vector Pairwise Add (floating-point).</iform>
    <iform iformfile="vpadd_i.xml" heading="VPADD (integer)" id="VPADD_i">Vector Pairwise Add (integer).</iform>
    <iform iformfile="vpaddl.xml" heading="VPADDL" id="VPADDL">Vector Pairwise Add Long.</iform>
    <iform iformfile="vpmax_f.xml" heading="VPMAX (floating-point)" id="VPMAX_f">Vector Pairwise Maximum (floating-point).</iform>
    <iform iformfile="vpmax_i.xml" heading="VPMAX (integer)" id="VPMAX_i">Vector Pairwise Maximum (integer).</iform>
    <iform iformfile="vpmin_f.xml" heading="VPMIN (floating-point)" id="VPMIN_f">Vector Pairwise Minimum (floating-point).</iform>
    <iform iformfile="vpmin_i.xml" heading="VPMIN (integer)" id="VPMIN_i">Vector Pairwise Minimum (integer).</iform>
    <iform iformfile="vpop_vldm.xml" heading="VPOP" id="VPOP_VLDM">Pop SIMD&amp;FP registers from stack: an alias of VLDM, VLDMDB, VLDMIA.</iform>
    <iform iformfile="vpush_vstm.xml" heading="VPUSH" id="VPUSH_VSTM">Push SIMD&amp;FP registers to stack: an alias of VSTM, VSTMDB, VSTMIA.</iform>
    <iform iformfile="vqabs.xml" heading="VQABS" id="VQABS">Vector Saturating Absolute.</iform>
    <iform iformfile="vqadd.xml" heading="VQADD" id="VQADD">Vector Saturating Add.</iform>
    <iform iformfile="vqdmlal.xml" heading="VQDMLAL" id="VQDMLAL">Vector Saturating Doubling Multiply Accumulate Long.</iform>
    <iform iformfile="vqdmlsl.xml" heading="VQDMLSL" id="VQDMLSL">Vector Saturating Doubling Multiply Subtract Long.</iform>
    <iform iformfile="vqdmulh.xml" heading="VQDMULH" id="VQDMULH">Vector Saturating Doubling Multiply Returning High Half.</iform>
    <iform iformfile="vqdmull.xml" heading="VQDMULL" id="VQDMULL">Vector Saturating Doubling Multiply Long.</iform>
    <iform iformfile="vqmovn.xml" heading="VQMOVN, VQMOVUN" id="VQMOVN">Vector Saturating Move and Narrow.</iform>
    <iform iformfile="vqneg.xml" heading="VQNEG" id="VQNEG">Vector Saturating Negate.</iform>
    <iform iformfile="vqrdmlah.xml" heading="VQRDMLAH" id="VQRDMLAH">Vector Saturating Rounding Doubling Multiply Accumulate Returning High Half.</iform>
    <iform iformfile="vqrdmlsh.xml" heading="VQRDMLSH" id="VQRDMLSH">Vector Saturating Rounding Doubling Multiply Subtract Returning High Half.</iform>
    <iform iformfile="vqrdmulh.xml" heading="VQRDMULH" id="VQRDMULH">Vector Saturating Rounding Doubling Multiply Returning High Half.</iform>
    <iform iformfile="vqrshl.xml" heading="VQRSHL" id="VQRSHL">Vector Saturating Rounding Shift Left.</iform>
    <iform iformfile="vqrshrn_vqmovn.xml" heading="VQRSHRN (zero)" id="VQRSHRN_VQMOVN">Vector Saturating Rounding Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.</iform>
    <iform iformfile="vqrshrn.xml" heading="VQRSHRN, VQRSHRUN" id="VQRSHRN">Vector Saturating Rounding Shift Right, Narrow.</iform>
    <iform iformfile="vqrshrun_vqmovn.xml" heading="VQRSHRUN (zero)" id="VQRSHRUN_VQMOVN">Vector Saturating Rounding Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.</iform>
    <iform iformfile="vqshl_r.xml" heading="VQSHL (register)" id="VQSHL_r">Vector Saturating Shift Left (register).</iform>
    <iform iformfile="vqshl_i.xml" heading="VQSHL, VQSHLU (immediate)" id="VQSHL_i">Vector Saturating Shift Left (immediate).</iform>
    <iform iformfile="vqshrn_vqmovn.xml" heading="VQSHRN (zero)" id="VQSHRN_VQMOVN">Vector Saturating Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.</iform>
    <iform iformfile="vqshrn.xml" heading="VQSHRN, VQSHRUN" id="VQSHRN">Vector Saturating Shift Right, Narrow.</iform>
    <iform iformfile="vqshrun_vqmovn.xml" heading="VQSHRUN (zero)" id="VQSHRUN_VQMOVN">Vector Saturating Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.</iform>
    <iform iformfile="vqsub.xml" heading="VQSUB" id="VQSUB">Vector Saturating Subtract.</iform>
    <iform iformfile="vraddhn.xml" heading="VRADDHN" id="VRADDHN">Vector Rounding Add and Narrow, returning High Half.</iform>
    <iform iformfile="vrecpe.xml" heading="VRECPE" id="VRECPE">Vector Reciprocal Estimate.</iform>
    <iform iformfile="vrecps.xml" heading="VRECPS" id="VRECPS">Vector Reciprocal Step.</iform>
    <iform iformfile="vrev16.xml" heading="VREV16" id="VREV16">Vector Reverse in halfwords.</iform>
    <iform iformfile="vrev32.xml" heading="VREV32" id="VREV32">Vector Reverse in words.</iform>
    <iform iformfile="vrev64.xml" heading="VREV64" id="VREV64">Vector Reverse in doublewords.</iform>
    <iform iformfile="vrhadd.xml" heading="VRHADD" id="VRHADD">Vector Rounding Halving Add.</iform>
    <iform iformfile="vrinta_asimd.xml" heading="VRINTA (Advanced SIMD)" id="VRINTA_asimd">Vector Round floating-point to integer towards Nearest with Ties to Away.</iform>
    <iform iformfile="vrinta_vfp.xml" heading="VRINTA (floating-point)" id="VRINTA_vfp">Round floating-point to integer to Nearest with Ties to Away.</iform>
    <iform iformfile="vrintm_asimd.xml" heading="VRINTM (Advanced SIMD)" id="VRINTM_asimd">Vector Round floating-point to integer towards -Infinity.</iform>
    <iform iformfile="vrintm_vfp.xml" heading="VRINTM (floating-point)" id="VRINTM_vfp">Round floating-point to integer towards -Infinity.</iform>
    <iform iformfile="vrintn_asimd.xml" heading="VRINTN (Advanced SIMD)" id="VRINTN_asimd">Vector Round floating-point to integer to Nearest.</iform>
    <iform iformfile="vrintn_vfp.xml" heading="VRINTN (floating-point)" id="VRINTN_vfp">Round floating-point to integer to Nearest.</iform>
    <iform iformfile="vrintp_asimd.xml" heading="VRINTP (Advanced SIMD)" id="VRINTP_asimd">Vector Round floating-point to integer towards +Infinity.</iform>
    <iform iformfile="vrintp_vfp.xml" heading="VRINTP (floating-point)" id="VRINTP_vfp">Round floating-point to integer towards +Infinity.</iform>
    <iform iformfile="vrintr_vfp.xml" heading="VRINTR" id="VRINTR_vfp">Round floating-point to integer.</iform>
    <iform iformfile="vrintx_asimd.xml" heading="VRINTX (Advanced SIMD)" id="VRINTX_asimd">Vector round floating-point to integer inexact.</iform>
    <iform iformfile="vrintx_vfp.xml" heading="VRINTX (floating-point)" id="VRINTX_vfp">Round floating-point to integer inexact.</iform>
    <iform iformfile="vrintz_asimd.xml" heading="VRINTZ (Advanced SIMD)" id="VRINTZ_asimd">Vector round floating-point to integer towards Zero.</iform>
    <iform iformfile="vrintz_vfp.xml" heading="VRINTZ (floating-point)" id="VRINTZ_vfp">Round floating-point to integer towards Zero.</iform>
    <iform iformfile="vrshl.xml" heading="VRSHL" id="VRSHL">Vector Rounding Shift Left.</iform>
    <iform iformfile="vrshr.xml" heading="VRSHR" id="VRSHR">Vector Rounding Shift Right.</iform>
    <iform iformfile="vrshr_vorr_r.xml" heading="VRSHR (zero)" id="VRSHR_VORR_r">Vector Rounding Shift Right: an alias of VORR (register).</iform>
    <iform iformfile="vrshrn.xml" heading="VRSHRN" id="VRSHRN">Vector Rounding Shift Right and Narrow.</iform>
    <iform iformfile="vrshrn_vmovn.xml" heading="VRSHRN (zero)" id="VRSHRN_VMOVN">Vector Rounding Shift Right and Narrow: an alias of VMOVN.</iform>
    <iform iformfile="vrsqrte.xml" heading="VRSQRTE" id="VRSQRTE">Vector Reciprocal Square Root Estimate.</iform>
    <iform iformfile="vrsqrts.xml" heading="VRSQRTS" id="VRSQRTS">Vector Reciprocal Square Root Step.</iform>
    <iform iformfile="vrsra.xml" heading="VRSRA" id="VRSRA">Vector Rounding Shift Right and Accumulate.</iform>
    <iform iformfile="vrsubhn.xml" heading="VRSUBHN" id="VRSUBHN">Vector Rounding Subtract and Narrow, returning High Half.</iform>
    <iform iformfile="vsdot_s.xml" heading="VSDOT (by element)" id="VSDOT_s">Dot Product index form with signed integers..</iform>
    <iform iformfile="vsdot.xml" heading="VSDOT (vector)" id="VSDOT">Dot Product vector form with signed integers..</iform>
    <iform iformfile="vsel.xml" heading="VSELEQ, VSELGE, VSELGT, VSELVS" id="VSEL">Floating-point conditional select.</iform>
    <iform iformfile="vshl_i.xml" heading="VSHL (immediate)" id="VSHL_i">Vector Shift Left (immediate).</iform>
    <iform iformfile="vshl_r.xml" heading="VSHL (register)" id="VSHL_r">Vector Shift Left (register).</iform>
    <iform iformfile="vshll.xml" heading="VSHLL" id="VSHLL">Vector Shift Left Long.</iform>
    <iform iformfile="vshr.xml" heading="VSHR" id="VSHR">Vector Shift Right.</iform>
    <iform iformfile="vshr_vorr_r.xml" heading="VSHR (zero)" id="VSHR_VORR_r">Vector Shift Right: an alias of VORR (register).</iform>
    <iform iformfile="vshrn.xml" heading="VSHRN" id="VSHRN">Vector Shift Right Narrow.</iform>
    <iform iformfile="vshrn_vmovn.xml" heading="VSHRN (zero)" id="VSHRN_VMOVN">Vector Shift Right Narrow: an alias of VMOVN.</iform>
    <iform iformfile="vsli.xml" heading="VSLI" id="VSLI">Vector Shift Left and Insert.</iform>
    <iform iformfile="vsmmla.xml" heading="VSMMLA" id="VSMMLA">Widening 8-bit signed integer matrix multiply-accumulate into 2x2 matrix.</iform>
    <iform iformfile="vsqrt.xml" heading="VSQRT" id="VSQRT">Square Root.</iform>
    <iform iformfile="vsra.xml" heading="VSRA" id="VSRA">Vector Shift Right and Accumulate.</iform>
    <iform iformfile="vsri.xml" heading="VSRI" id="VSRI">Vector Shift Right and Insert.</iform>
    <iform iformfile="vst1_m.xml" heading="VST1 (multiple single elements)" id="VST1_m">Store multiple single elements from one, two, three, or four registers.</iform>
    <iform iformfile="vst1_1.xml" heading="VST1 (single element from one lane)" id="VST1_1">Store single element from one lane of one register.</iform>
    <iform iformfile="vst2_m.xml" heading="VST2 (multiple 2-element structures)" id="VST2_m">Store multiple 2-element structures from two or four registers.</iform>
    <iform iformfile="vst2_1.xml" heading="VST2 (single 2-element structure from one lane)" id="VST2_1">Store single 2-element structure from one lane of two registers.</iform>
    <iform iformfile="vst3_m.xml" heading="VST3 (multiple 3-element structures)" id="VST3_m">Store multiple 3-element structures from three registers.</iform>
    <iform iformfile="vst3_1.xml" heading="VST3 (single 3-element structure from one lane)" id="VST3_1">Store single 3-element structure from one lane of three registers.</iform>
    <iform iformfile="vst4_m.xml" heading="VST4 (multiple 4-element structures)" id="VST4_m">Store multiple 4-element structures from four registers.</iform>
    <iform iformfile="vst4_1.xml" heading="VST4 (single 4-element structure from one lane)" id="VST4_1">Store single 4-element structure from one lane of four registers.</iform>
    <iform iformfile="vstm.xml" heading="VSTM, VSTMDB, VSTMIA" id="VSTM">Store multiple SIMD&amp;FP registers.</iform>
    <iform iformfile="vstr.xml" heading="VSTR" id="VSTR">Store SIMD&amp;FP register.</iform>
    <iform iformfile="vsub_f.xml" heading="VSUB (floating-point)" id="VSUB_f">Vector Subtract (floating-point).</iform>
    <iform iformfile="vsub_i.xml" heading="VSUB (integer)" id="VSUB_i">Vector Subtract (integer).</iform>
    <iform iformfile="vsubhn.xml" heading="VSUBHN" id="VSUBHN">Vector Subtract and Narrow, returning High Half.</iform>
    <iform iformfile="vsubl.xml" heading="VSUBL" id="VSUBL">Vector Subtract Long.</iform>
    <iform iformfile="vsubw.xml" heading="VSUBW" id="VSUBW">Vector Subtract Wide.</iform>
    <iform iformfile="vsudot_s.xml" heading="VSUDOT (by element)" id="VSUDOT_s">Dot Product index form with signed and unsigned integers (by element).</iform>
    <iform iformfile="vswp.xml" heading="VSWP" id="VSWP">Vector Swap.</iform>
    <iform iformfile="vtbl.xml" heading="VTBL, VTBX" id="VTBL">Vector Table Lookup and Extension.</iform>
    <iform iformfile="vtrn.xml" heading="VTRN" id="VTRN">Vector Transpose.</iform>
    <iform iformfile="vtst.xml" heading="VTST" id="VTST">Vector Test Bits.</iform>
    <iform iformfile="vudot_s.xml" heading="VUDOT (by element)" id="VUDOT_s">Dot Product index form with unsigned integers..</iform>
    <iform iformfile="vudot.xml" heading="VUDOT (vector)" id="VUDOT">Dot Product vector form with unsigned integers..</iform>
    <iform iformfile="vummla.xml" heading="VUMMLA" id="VUMMLA">Widening 8-bit unsigned integer matrix multiply-accumulate into 2x2 matrix.</iform>
    <iform iformfile="vusdot_s.xml" heading="VUSDOT (by element)" id="VUSDOT_s">Dot Product index form with unsigned and signed integers (by element).</iform>
    <iform iformfile="vusdot.xml" heading="VUSDOT (vector)" id="VUSDOT">Dot Product vector form with mixed-sign integers.</iform>
    <iform iformfile="vusmmla.xml" heading="VUSMMLA" id="VUSMMLA">Widening 8-bit mixed integer matrix multiply-accumulate into 2x2 matrix.</iform>
    <iform iformfile="vuzp.xml" heading="VUZP" id="VUZP">Vector Unzip.</iform>
    <iform iformfile="vuzp_vtrn.xml" heading="VUZP (alias)" id="VUZP_VTRN">Vector Unzip: an alias of VTRN.</iform>
    <iform iformfile="vzip.xml" heading="VZIP" id="VZIP">Vector Zip.</iform>
    <iform iformfile="vzip_vtrn.xml" heading="VZIP (alias)" id="VZIP_VTRN">Vector Zip: an alias of VTRN.</iform>
  </iforms>
</alphaindex>
</file>
  <sect1 id="encodingindex">
<file type="encodingindex" file="a32_encindex.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<encodingindex instructionset="A32">
  <hierarchy>
    <regdiagram form="32">
      <box hibit="31" width="4" name="cond" usename="1">
        <c colspan="4" />
      </box>
      <box hibit="27" width="3" name="op0" usename="1">
        <c colspan="3" />
      </box>
      <box hibit="24" width="20">
        <c colspan="20" />
      </box>
      <box hibit="4" width="1" name="op1" usename="1">
        <c colspan="1" />
      </box>
      <box hibit="3" width="4">
        <c colspan="4" />
      </box>
    </regdiagram>
    <node groupname="dp">
      <header>Data-processing and miscellaneous instructions</header>
      <decode>
        <box hibit="31" width="4" name="cond" usename="1">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" name="op0" usename="1">
          <c colspan="3">00x</c>
        </box>
        <box hibit="4" width="1" name="op1" usename="1">
          <c colspan="1" />
        </box>
      </decode>
      <regdiagram form="32">
        <box hibit="31" width="4">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="2">
          <c colspan="2">00</c>
        </box>
        <box hibit="25" width="1" name="op0" usename="1">
          <c colspan="1" />
        </box>
        <box hibit="24" width="5" name="op1" usename="1">
          <c colspan="5" />
        </box>
        <box hibit="19" width="12">
          <c colspan="12" />
        </box>
        <box hibit="7" width="1" name="op2" usename="1">
          <c colspan="1" />
        </box>
        <box hibit="6" width="2" name="op3" usename="1">
          <c colspan="2" />
        </box>
        <box hibit="4" width="1" name="op4" usename="1">
          <c colspan="1" />
        </box>
        <box hibit="3" width="4">
          <c colspan="4" />
        </box>
      </regdiagram>
      <node groupname="xldst">
        <header>Extra load/store</header>
        <decode>
          <box hibit="25" width="1" name="op0" usename="1">
            <c colspan="1">0</c>
          </box>
          <box hibit="24" width="5" name="op1" usename="1">
            <c colspan="5" />
          </box>
          <box hibit="7" width="1" name="op2" usename="1">
            <c colspan="1">1</c>
          </box>
          <box hibit="6" width="2" name="op3" usename="1">
            <c colspan="2">!= 00</c>
          </box>
          <box hibit="4" width="1" name="op4" usename="1">
            <c colspan="1">1</c>
          </box>
        </decode>
        <regdiagram form="32">
          <box hibit="31" width="4">
            <c colspan="4">!= 1111</c>
          </box>
          <box hibit="27" width="3">
            <c colspan="3">000</c>
          </box>
          <box hibit="24" width="2">
            <c colspan="2" />
          </box>
          <box hibit="22" width="1" name="op0" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="21" width="14">
            <c colspan="14" />
          </box>
          <box hibit="7" width="1">
            <c colspan="1">1</c>
          </box>
          <box hibit="6" width="2">
            <c colspan="2">!= 00</c>
          </box>
          <box hibit="4" width="1">
            <c colspan="1">1</c>
          </box>
          <box hibit="3" width="4">
            <c colspan="4" />
          </box>
        </regdiagram>
        <node iclass="ldstxreg">
          <header>Load/Store Dual, Half, Signed Byte (register)</header>
          <decode>
            <box hibit="22" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
          </decode>
        </node>
        <node iclass="ldstximm">
          <header>Load/Store Dual, Half, Signed Byte (immediate, literal)</header>
          <decode>
            <box hibit="22" width="1" name="op0" usename="1">
              <c colspan="1">1</c>
            </box>
          </decode>
        </node>
      </node>
      <node iclass="mul_word">
        <header>Multiply and Accumulate</header>
        <decode>
          <box hibit="25" width="1" name="op0" usename="1">
            <c colspan="1">0</c>
          </box>
          <box hibit="24" width="5" name="op1" usename="1">
            <c colspan="5">0xxxx</c>
          </box>
          <box hibit="7" width="1" name="op2" usename="1">
            <c colspan="1">1</c>
          </box>
          <box hibit="6" width="2" name="op3" usename="1">
            <c colspan="2">00</c>
          </box>
          <box hibit="4" width="1" name="op4" usename="1">
            <c colspan="1">1</c>
          </box>
        </decode>
      </node>
      <node groupname="sync">
        <header>Synchronization primitives and Load-Acquire/Store-Release</header>
        <decode>
          <box hibit="25" width="1" name="op0" usename="1">
            <c colspan="1">0</c>
          </box>
          <box hibit="24" width="5" name="op1" usename="1">
            <c colspan="5">1xxxx</c>
          </box>
          <box hibit="7" width="1" name="op2" usename="1">
            <c colspan="1">1</c>
          </box>
          <box hibit="6" width="2" name="op3" usename="1">
            <c colspan="2">00</c>
          </box>
          <box hibit="4" width="1" name="op4" usename="1">
            <c colspan="1">1</c>
          </box>
        </decode>
        <regdiagram form="32">
          <box hibit="31" width="4">
            <c colspan="4">!= 1111</c>
          </box>
          <box hibit="27" width="4">
            <c colspan="4">0001</c>
          </box>
          <box hibit="23" width="1" name="op0" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="22" width="11">
            <c colspan="11" />
          </box>
          <box hibit="11" width="2">
            <c colspan="2">11</c>
          </box>
          <box hibit="9" width="2">
            <c colspan="2" />
          </box>
          <box hibit="7" width="4">
            <c colspan="4">1001</c>
          </box>
          <box hibit="3" width="4">
            <c colspan="4" />
          </box>
        </regdiagram>
        <node iclass="UNALLOCATED_34" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="23" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
          </decode>
        </node>
        <node iclass="ldst_excl">
          <header>Load/Store Exclusive and Load-Acquire/Store-Release</header>
          <decode>
            <box hibit="23" width="1" name="op0" usename="1">
              <c colspan="1">1</c>
            </box>
          </decode>
        </node>
      </node>
      <node groupname="dpmisc">
        <header>Miscellaneous</header>
        <decode>
          <box hibit="25" width="1" name="op0" usename="1">
            <c colspan="1">0</c>
          </box>
          <box hibit="24" width="5" name="op1" usename="1">
            <c colspan="5">10xx0</c>
          </box>
          <box hibit="7" width="1" name="op2" usename="1">
            <c colspan="1">0</c>
          </box>
          <box hibit="6" width="2" name="op3" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="4" width="1" name="op4" usename="1">
            <c colspan="1" />
          </box>
        </decode>
        <regdiagram form="32">
          <box hibit="31" width="4">
            <c colspan="4">!= 1111</c>
          </box>
          <box hibit="27" width="5">
            <c colspan="5">00010</c>
          </box>
          <box hibit="22" width="2" name="op0" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="20" width="1">
            <c colspan="1">0</c>
          </box>
          <box hibit="19" width="12">
            <c colspan="12" />
          </box>
          <box hibit="7" width="1">
            <c colspan="1">0</c>
          </box>
          <box hibit="6" width="3" name="op1" usename="1">
            <c colspan="3" />
          </box>
          <box hibit="3" width="4">
            <c colspan="4" />
          </box>
        </regdiagram>
        <node iclass="UNALLOCATED_22" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="22" width="2" name="op0" usename="1">
              <c colspan="2">00</c>
            </box>
            <box hibit="6" width="3" name="op1" usename="1">
              <c colspan="3">001</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_9" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="22" width="2" name="op0" usename="1">
              <c colspan="2">00</c>
            </box>
            <box hibit="6" width="3" name="op1" usename="1">
              <c colspan="3">010</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_26" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="22" width="2" name="op0" usename="1">
              <c colspan="2">00</c>
            </box>
            <box hibit="6" width="3" name="op1" usename="1">
              <c colspan="3">011</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_14" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="22" width="2" name="op0" usename="1">
              <c colspan="2">00</c>
            </box>
            <box hibit="6" width="3" name="op1" usename="1">
              <c colspan="3">110</c>
            </box>
          </decode>
        </node>
        <node iclass="bx_reg">
          <header>Branch and Exchange (register)</header>
          <decode>
            <box hibit="22" width="2" name="op0" usename="1">
              <c colspan="2">01</c>
            </box>
            <box hibit="6" width="3" name="op1" usename="1">
              <c colspan="3">001</c>
            </box>
          </decode>
        </node>
        <node iclass="bxj_reg">
          <header>Branch and Exchange to Jazelle (register)</header>
          <decode>
            <box hibit="22" width="2" name="op0" usename="1">
              <c colspan="2">01</c>
            </box>
            <box hibit="6" width="3" name="op1" usename="1">
              <c colspan="3">010</c>
            </box>
          </decode>
        </node>
        <node iclass="blx_reg">
          <header>Branch with Link and Exchange (register)</header>
          <decode>
            <box hibit="22" width="2" name="op0" usename="1">
              <c colspan="2">01</c>
            </box>
            <box hibit="6" width="3" name="op1" usename="1">
              <c colspan="3">011</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_15" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="22" width="2" name="op0" usename="1">
              <c colspan="2">01</c>
            </box>
            <box hibit="6" width="3" name="op1" usename="1">
              <c colspan="3">110</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_24" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="22" width="2" name="op0" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="6" width="3" name="op1" usename="1">
              <c colspan="3">001</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_11" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="22" width="2" name="op0" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="6" width="3" name="op1" usename="1">
              <c colspan="3">010</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_28" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="22" width="2" name="op0" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="6" width="3" name="op1" usename="1">
              <c colspan="3">011</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_16" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="22" width="2" name="op0" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="6" width="3" name="op1" usename="1">
              <c colspan="3">110</c>
            </box>
          </decode>
        </node>
        <node iclass="clz">
          <header>Count Leading Zeros</header>
          <decode>
            <box hibit="22" width="2" name="op0" usename="1">
              <c colspan="2">11</c>
            </box>
            <box hibit="6" width="3" name="op1" usename="1">
              <c colspan="3">001</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_12" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="22" width="2" name="op0" usename="1">
              <c colspan="2">11</c>
            </box>
            <box hibit="6" width="3" name="op1" usename="1">
              <c colspan="3">010</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_29" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="22" width="2" name="op0" usename="1">
              <c colspan="2">11</c>
            </box>
            <box hibit="6" width="3" name="op1" usename="1">
              <c colspan="3">011</c>
            </box>
          </decode>
        </node>
        <node iclass="eret">
          <header>Exception Return</header>
          <decode>
            <box hibit="22" width="2" name="op0" usename="1">
              <c colspan="2">11</c>
            </box>
            <box hibit="6" width="3" name="op1" usename="1">
              <c colspan="3">110</c>
            </box>
          </decode>
        </node>
        <node iclass="except">
          <header>Exception Generation</header>
          <decode>
            <box hibit="22" width="2" name="op0" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="6" width="3" name="op1" usename="1">
              <c colspan="3">111</c>
            </box>
          </decode>
        </node>
        <node iclass="movsr_reg">
          <header>Move special register (register)</header>
          <decode>
            <box hibit="22" width="2" name="op0" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="6" width="3" name="op1" usename="1">
              <c colspan="3">000</c>
            </box>
          </decode>
        </node>
        <node iclass="crc32">
          <header>Cyclic Redundancy Check</header>
          <decode>
            <box hibit="22" width="2" name="op0" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="6" width="3" name="op1" usename="1">
              <c colspan="3">100</c>
            </box>
          </decode>
        </node>
        <node iclass="intsat">
          <header>Integer Saturating Arithmetic</header>
          <decode>
            <box hibit="22" width="2" name="op0" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="6" width="3" name="op1" usename="1">
              <c colspan="3">101</c>
            </box>
          </decode>
        </node>
      </node>
      <node iclass="mul_half">
        <header>Halfword Multiply and Accumulate</header>
        <decode>
          <box hibit="25" width="1" name="op0" usename="1">
            <c colspan="1">0</c>
          </box>
          <box hibit="24" width="5" name="op1" usename="1">
            <c colspan="5">10xx0</c>
          </box>
          <box hibit="7" width="1" name="op2" usename="1">
            <c colspan="1">1</c>
          </box>
          <box hibit="6" width="2" name="op3" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="4" width="1" name="op4" usename="1">
            <c colspan="1">0</c>
          </box>
        </decode>
      </node>
      <node groupname="dpregis">
        <header>Data-processing register (immediate shift)</header>
        <decode>
          <box hibit="25" width="1" name="op0" usename="1">
            <c colspan="1">0</c>
          </box>
          <box hibit="24" width="5" name="op1" usename="1">
            <c colspan="5">!= 10xx0</c>
          </box>
          <box hibit="7" width="1" name="op2" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="6" width="2" name="op3" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="4" width="1" name="op4" usename="1">
            <c colspan="1">0</c>
          </box>
        </decode>
        <regdiagram form="32">
          <box hibit="31" width="4">
            <c colspan="4">!= 1111</c>
          </box>
          <box hibit="27" width="3">
            <c colspan="3">000</c>
          </box>
          <box hibit="24" width="2" name="op0" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="22" width="2">
            <c colspan="2" />
          </box>
          <box hibit="20" width="1" name="op1" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="19" width="15">
            <c colspan="15" />
          </box>
          <box hibit="4" width="1">
            <c colspan="1">0</c>
          </box>
          <box hibit="3" width="4">
            <c colspan="4" />
          </box>
        </regdiagram>
        <decode_constraints>
          <decode_constraint name="op0:op1" op="!=" val="100" />
        </decode_constraints>
        <node iclass="intdp3reg_immsh">
          <header>Integer Data Processing (three register, immediate shift)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">0x</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="intdp2reg_immsh">
          <header>Integer Test and Compare (two register, immediate shift)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1">1</c>
            </box>
          </decode>
        </node>
        <node iclass="logic3reg_immsh">
          <header>Logical Arithmetic (three register, immediate shift)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">11</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
      </node>
      <node groupname="dpregrs">
        <header>Data-processing register (register shift)</header>
        <decode>
          <box hibit="25" width="1" name="op0" usename="1">
            <c colspan="1">0</c>
          </box>
          <box hibit="24" width="5" name="op1" usename="1">
            <c colspan="5">!= 10xx0</c>
          </box>
          <box hibit="7" width="1" name="op2" usename="1">
            <c colspan="1">0</c>
          </box>
          <box hibit="6" width="2" name="op3" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="4" width="1" name="op4" usename="1">
            <c colspan="1">1</c>
          </box>
        </decode>
        <regdiagram form="32">
          <box hibit="31" width="4">
            <c colspan="4">!= 1111</c>
          </box>
          <box hibit="27" width="3">
            <c colspan="3">000</c>
          </box>
          <box hibit="24" width="2" name="op0" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="22" width="2">
            <c colspan="2" />
          </box>
          <box hibit="20" width="1" name="op1" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="19" width="12">
            <c colspan="12" />
          </box>
          <box hibit="7" width="1">
            <c colspan="1">0</c>
          </box>
          <box hibit="6" width="2">
            <c colspan="2" />
          </box>
          <box hibit="4" width="1">
            <c colspan="1">1</c>
          </box>
          <box hibit="3" width="4">
            <c colspan="4" />
          </box>
        </regdiagram>
        <decode_constraints>
          <decode_constraint name="op0:op1" op="!=" val="100" />
        </decode_constraints>
        <node iclass="intdp3reg_regsh">
          <header>Integer Data Processing (three register, register shift)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">0x</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="intdp2reg_regsh">
          <header>Integer Test and Compare (two register, register shift)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1">1</c>
            </box>
          </decode>
        </node>
        <node iclass="logic3reg_regsh">
          <header>Logical Arithmetic (three register, register shift)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">11</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
      </node>
      <node groupname="dpimm">
        <header>Data-processing immediate</header>
        <decode>
          <box hibit="25" width="1" name="op0" usename="1">
            <c colspan="1">1</c>
          </box>
          <box hibit="24" width="5" name="op1" usename="1">
            <c colspan="5" />
          </box>
          <box hibit="7" width="1" name="op2" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="6" width="2" name="op3" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="4" width="1" name="op4" usename="1">
            <c colspan="1" />
          </box>
        </decode>
        <regdiagram form="32">
          <box hibit="31" width="4">
            <c colspan="4">!= 1111</c>
          </box>
          <box hibit="27" width="3">
            <c colspan="3">001</c>
          </box>
          <box hibit="24" width="2" name="op0" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="22" width="1">
            <c colspan="1" />
          </box>
          <box hibit="21" width="2" name="op1" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="19" width="20">
            <c colspan="20" />
          </box>
        </regdiagram>
        <node iclass="intdp2reg_imm">
          <header>Integer Data Processing (two register and immediate)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">0x</c>
            </box>
            <box hibit="21" width="2" name="op1" usename="1">
              <c colspan="2" />
            </box>
          </decode>
        </node>
        <node iclass="movw">
          <header>Move Halfword (immediate)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="21" width="2" name="op1" usename="1">
              <c colspan="2">00</c>
            </box>
          </decode>
        </node>
        <node iclass="movsr_hint_imm">
          <header>Move Special Register and Hints (immediate)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="21" width="2" name="op1" usename="1">
              <c colspan="2">10</c>
            </box>
          </decode>
        </node>
        <node iclass="intdp1reg_imm">
          <header>Integer Test and Compare (one register and immediate)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="21" width="2" name="op1" usename="1">
              <c colspan="2">x1</c>
            </box>
          </decode>
        </node>
        <node iclass="log2reg_imm">
          <header>Logical Arithmetic  (two register and immediate)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">11</c>
            </box>
            <box hibit="21" width="2" name="op1" usename="1">
              <c colspan="2" />
            </box>
          </decode>
        </node>
      </node>
    </node>
    <node iclass="ldstimm">
      <header>Load/Store Word, Unsigned Byte (immediate, literal)</header>
      <decode>
        <box hibit="31" width="4" name="cond" usename="1">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" name="op0" usename="1">
          <c colspan="3">010</c>
        </box>
        <box hibit="4" width="1" name="op1" usename="1">
          <c colspan="1" />
        </box>
      </decode>
    </node>
    <node iclass="ldstreg">
      <header>Load/Store Word, Unsigned Byte (register)</header>
      <decode>
        <box hibit="31" width="4" name="cond" usename="1">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" name="op0" usename="1">
          <c colspan="3">011</c>
        </box>
        <box hibit="4" width="1" name="op1" usename="1">
          <c colspan="1">0</c>
        </box>
      </decode>
    </node>
    <node groupname="media">
      <header>Media instructions</header>
      <decode>
        <box hibit="31" width="4" name="cond" usename="1">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" name="op0" usename="1">
          <c colspan="3">011</c>
        </box>
        <box hibit="4" width="1" name="op1" usename="1">
          <c colspan="1">1</c>
        </box>
      </decode>
      <regdiagram form="32">
        <box hibit="31" width="4">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3">
          <c colspan="3">011</c>
        </box>
        <box hibit="24" width="5" name="op0" usename="1">
          <c colspan="5" />
        </box>
        <box hibit="19" width="12">
          <c colspan="12" />
        </box>
        <box hibit="7" width="3" name="op1" usename="1">
          <c colspan="3" />
        </box>
        <box hibit="4" width="1">
          <c colspan="1">1</c>
        </box>
        <box hibit="3" width="4">
          <c colspan="4" />
        </box>
      </regdiagram>
      <node iclass="parallel">
        <header>Parallel Arithmetic</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">00xxx</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3" />
          </box>
        </decode>
      </node>
      <node iclass="selbytes">
        <header>Select Bytes</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">01000</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">101</c>
          </box>
        </decode>
      </node>
      <node iclass="UNALLOCATED_85" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">01000</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">001</c>
          </box>
        </decode>
      </node>
      <node iclass="pack">
        <header>Pack Halfword</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">01000</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">xx0</c>
          </box>
        </decode>
      </node>
      <node iclass="UNALLOCATED_87" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">01001</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">x01</c>
          </box>
        </decode>
      </node>
      <node iclass="UNALLOCATED_82" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">01001</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">xx0</c>
          </box>
        </decode>
      </node>
      <node iclass="UNALLOCATED_91" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">0110x</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">x01</c>
          </box>
        </decode>
      </node>
      <node iclass="UNALLOCATED_84" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">0110x</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">xx0</c>
          </box>
        </decode>
      </node>
      <node iclass="sat16">
        <header>Saturate 16-bit</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">01x10</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">001</c>
          </box>
        </decode>
      </node>
      <node iclass="UNALLOCATED_89" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">01x10</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">101</c>
          </box>
        </decode>
      </node>
      <node iclass="reverse">
        <header>Reverse Bit/Byte</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">01x11</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">x01</c>
          </box>
        </decode>
      </node>
      <node iclass="sat32">
        <header>Saturate 32-bit</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">01x1x</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">xx0</c>
          </box>
        </decode>
      </node>
      <node iclass="UNALLOCATED_93" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">01xxx</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">111</c>
          </box>
        </decode>
      </node>
      <node iclass="extend">
        <header>Extend and Add</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">01xxx</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">011</c>
          </box>
        </decode>
      </node>
      <node iclass="smul_div">
        <header>Signed multiply, Divide</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">10xxx</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3" />
          </box>
        </decode>
      </node>
      <node iclass="usad">
        <header>Unsigned Sum of Absolute Differences</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">11000</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">000</c>
          </box>
        </decode>
      </node>
      <node iclass="UNALLOCATED_96" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">11000</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">100</c>
          </box>
        </decode>
      </node>
      <node iclass="UNALLOCATED_97" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">11001</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">x00</c>
          </box>
        </decode>
      </node>
      <node iclass="UNALLOCATED_98" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">1101x</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">x00</c>
          </box>
        </decode>
      </node>
      <node iclass="UNALLOCATED_105" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">110xx</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">111</c>
          </box>
        </decode>
      </node>
      <node iclass="UNALLOCATED_106" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">1110x</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">111</c>
          </box>
        </decode>
      </node>
      <node iclass="bfi">
        <header>Bitfield Insert</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">1110x</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">x00</c>
          </box>
        </decode>
      </node>
      <node iclass="UNALLOCATED_107" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">11110</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">111</c>
          </box>
        </decode>
      </node>
      <node iclass="udf">
        <header>Permanently UNDEFINED</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">11111</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">111</c>
          </box>
        </decode>
      </node>
      <node iclass="UNALLOCATED_100" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">1111x</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">x00</c>
          </box>
        </decode>
      </node>
      <node iclass="UNALLOCATED_102" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">11x0x</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">x10</c>
          </box>
        </decode>
      </node>
      <node iclass="bfx">
        <header>Bitfield Extract</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">11x1x</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">x10</c>
          </box>
        </decode>
      </node>
      <node iclass="UNALLOCATED_104" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">11xxx</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">011</c>
          </box>
        </decode>
      </node>
      <node iclass="UNALLOCATED_101" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5">11xxx</c>
          </box>
          <box hibit="7" width="3" name="op1" usename="1">
            <c colspan="3">x01</c>
          </box>
        </decode>
      </node>
    </node>
    <node groupname="brblk">
      <header>Branch, branch with link, and block data transfer</header>
      <decode>
        <box hibit="31" width="4" name="cond" usename="1">
          <c colspan="4" />
        </box>
        <box hibit="27" width="3" name="op0" usename="1">
          <c colspan="3">10x</c>
        </box>
        <box hibit="4" width="1" name="op1" usename="1">
          <c colspan="1" />
        </box>
      </decode>
      <regdiagram form="32">
        <box hibit="31" width="4" name="cond" usename="1">
          <c colspan="4" />
        </box>
        <box hibit="27" width="2">
          <c colspan="2">10</c>
        </box>
        <box hibit="25" width="1" name="op0" usename="1">
          <c colspan="1" />
        </box>
        <box hibit="24" width="25">
          <c colspan="25" />
        </box>
      </regdiagram>
      <node iclass="ldstexcept">
        <header>Exception Save/Restore</header>
        <decode>
          <box hibit="31" width="4" name="cond" usename="1">
            <c colspan="4">1111</c>
          </box>
          <box hibit="25" width="1" name="op0" usename="1">
            <c colspan="1">0</c>
          </box>
        </decode>
      </node>
      <node iclass="ldstm">
        <header>Load/Store Multiple</header>
        <decode>
          <box hibit="31" width="4" name="cond" usename="1">
            <c colspan="4">!= 1111</c>
          </box>
          <box hibit="25" width="1" name="op0" usename="1">
            <c colspan="1">0</c>
          </box>
        </decode>
      </node>
      <node iclass="b_imm">
        <header>Branch (immediate)</header>
        <decode>
          <box hibit="31" width="4" name="cond" usename="1">
            <c colspan="4" />
          </box>
          <box hibit="25" width="1" name="op0" usename="1">
            <c colspan="1">1</c>
          </box>
        </decode>
      </node>
    </node>
    <node groupname="cops_as">
      <header>System register access, Advanced SIMD, floating-point, and Supervisor call</header>
      <decode>
        <box hibit="31" width="4" name="cond" usename="1">
          <c colspan="4" />
        </box>
        <box hibit="27" width="3" name="op0" usename="1">
          <c colspan="3">11x</c>
        </box>
        <box hibit="4" width="1" name="op1" usename="1">
          <c colspan="1" />
        </box>
      </decode>
      <regdiagram form="32">
        <box hibit="31" width="4" name="cond" usename="1">
          <c colspan="4" />
        </box>
        <box hibit="27" width="2">
          <c colspan="2">11</c>
        </box>
        <box hibit="25" width="2" name="op0" usename="1">
          <c colspan="2" />
        </box>
        <box hibit="23" width="12">
          <c colspan="12" />
        </box>
        <box hibit="11" width="2" name="op1" usename="1">
          <c colspan="2" />
        </box>
        <box hibit="9" width="5">
          <c colspan="5" />
        </box>
        <box hibit="4" width="1" name="op2" usename="1">
          <c colspan="1" />
        </box>
        <box hibit="3" width="4">
          <c colspan="4" />
        </box>
      </regdiagram>
      <node iclass="UNALLOCATED_113" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="31" width="4" name="cond" usename="1">
            <c colspan="4" />
          </box>
          <box hibit="25" width="2" name="op0" usename="1">
            <c colspan="2">0x</c>
          </box>
          <box hibit="11" width="2" name="op1" usename="1">
            <c colspan="2">0x</c>
          </box>
          <box hibit="4" width="1" name="op2" usename="1">
            <c colspan="1" />
          </box>
        </decode>
      </node>
      <node iclass="UNALLOCATED_120" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="31" width="4" name="cond" usename="1">
            <c colspan="4" />
          </box>
          <box hibit="25" width="2" name="op0" usename="1">
            <c colspan="2">10</c>
          </box>
          <box hibit="11" width="2" name="op1" usename="1">
            <c colspan="2">0x</c>
          </box>
          <box hibit="4" width="1" name="op2" usename="1">
            <c colspan="1" />
          </box>
        </decode>
      </node>
      <node groupname="svcall">
        <header>Supervisor call</header>
        <decode>
          <box hibit="31" width="4" name="cond" usename="1">
            <c colspan="4" />
          </box>
          <box hibit="25" width="2" name="op0" usename="1">
            <c colspan="2">11</c>
          </box>
          <box hibit="11" width="2" name="op1" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="4" width="1" name="op2" usename="1">
            <c colspan="1" />
          </box>
        </decode>
        <regdiagram form="32">
          <box hibit="31" width="4" name="cond" usename="1">
            <c colspan="4" />
          </box>
          <box hibit="27" width="4">
            <c colspan="4">1111</c>
          </box>
          <box hibit="23" width="24">
            <c colspan="24" />
          </box>
        </regdiagram>
        <node iclass="UNALLOCATED_142" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="31" width="4" name="cond" usename="1">
              <c colspan="4">1111</c>
            </box>
          </decode>
        </node>
        <node iclass="svc">
          <header>Supervisor Call</header>
          <decode>
            <box hibit="31" width="4" name="cond" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
          </decode>
        </node>
      </node>
      <node groupname="advsimdext">
        <header>Unconditional Advanced SIMD and floating-point instructions</header>
        <decode>
          <box hibit="31" width="4" name="cond" usename="1">
            <c colspan="4">1111</c>
          </box>
          <box hibit="25" width="2" name="op0" usename="1">
            <c colspan="2">!= 11</c>
          </box>
          <box hibit="11" width="2" name="op1" usename="1">
            <c colspan="2">1x</c>
          </box>
          <box hibit="4" width="1" name="op2" usename="1">
            <c colspan="1" />
          </box>
        </decode>
        <regdiagram form="32">
          <box hibit="31" width="6">
            <c colspan="6">111111</c>
          </box>
          <box hibit="25" width="3" name="op0" usename="1">
            <c colspan="3" />
          </box>
          <box hibit="22" width="1">
            <c colspan="1" />
          </box>
          <box hibit="21" width="6" name="op1" usename="1">
            <c colspan="6" />
          </box>
          <box hibit="15" width="4">
            <c colspan="4" />
          </box>
          <box hibit="11" width="1">
            <c colspan="1">1</c>
          </box>
          <box hibit="10" width="1" name="op2" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="9" width="2" name="op3" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="7" width="1">
            <c colspan="1" />
          </box>
          <box hibit="6" width="1" name="op4" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="5" width="1">
            <c colspan="1" />
          </box>
          <box hibit="4" width="1" name="op5" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="3" width="4">
            <c colspan="4" />
          </box>
        </regdiagram>
        <decode_constraints>
          <decode_constraint name="op0&lt;2:1&gt;" op="!=" val="11" />
        </decode_constraints>
        <node iclass="simd3reg_sameext">
          <header>Advanced SIMD three registers of the same length extension</header>
          <decode>
            <box hibit="25" width="3" name="op0" usename="1">
              <c colspan="3">0xx</c>
            </box>
            <box hibit="21" width="6" name="op1" usename="1">
              <c colspan="6" />
            </box>
            <box hibit="10" width="1" name="op2" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="9" width="2" name="op3" usename="1">
              <c colspan="2">0x</c>
            </box>
            <box hibit="6" width="1" name="op4" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="4" width="1" name="op5" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="fpcsel">
          <header>Floating-point conditional select</header>
          <decode>
            <box hibit="25" width="3" name="op0" usename="1">
              <c colspan="3">100</c>
            </box>
            <box hibit="21" width="6" name="op1" usename="1">
              <c colspan="6" />
            </box>
            <box hibit="10" width="1" name="op2" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="9" width="2" name="op3" usename="1">
              <c colspan="2">!= 00</c>
            </box>
            <box hibit="6" width="1" name="op4" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="4" width="1" name="op5" usename="1">
              <c colspan="1">0</c>
            </box>
          </decode>
        </node>
        <node iclass="fpminmaxnm">
          <header>Floating-point minNum/maxNum</header>
          <decode>
            <box hibit="25" width="3" name="op0" usename="1">
              <c colspan="3">101</c>
            </box>
            <box hibit="21" width="6" name="op1" usename="1">
              <c colspan="6">00xxxx</c>
            </box>
            <box hibit="10" width="1" name="op2" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="9" width="2" name="op3" usename="1">
              <c colspan="2">!= 00</c>
            </box>
            <box hibit="6" width="1" name="op4" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="4" width="1" name="op5" usename="1">
              <c colspan="1">0</c>
            </box>
          </decode>
        </node>
        <node iclass="fpextins">
          <header>Floating-point extraction and insertion</header>
          <decode>
            <box hibit="25" width="3" name="op0" usename="1">
              <c colspan="3">101</c>
            </box>
            <box hibit="21" width="6" name="op1" usename="1">
              <c colspan="6">110000</c>
            </box>
            <box hibit="10" width="1" name="op2" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="9" width="2" name="op3" usename="1">
              <c colspan="2">!= 00</c>
            </box>
            <box hibit="6" width="1" name="op4" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="4" width="1" name="op5" usename="1">
              <c colspan="1">0</c>
            </box>
          </decode>
        </node>
        <node iclass="fpcvtrnd">
          <header>Floating-point directed convert to integer</header>
          <decode>
            <box hibit="25" width="3" name="op0" usename="1">
              <c colspan="3">101</c>
            </box>
            <box hibit="21" width="6" name="op1" usename="1">
              <c colspan="6">111xxx</c>
            </box>
            <box hibit="10" width="1" name="op2" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="9" width="2" name="op3" usename="1">
              <c colspan="2">!= 00</c>
            </box>
            <box hibit="6" width="1" name="op4" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="4" width="1" name="op5" usename="1">
              <c colspan="1">0</c>
            </box>
          </decode>
        </node>
        <node iclass="floatdpmac">
          <header>Advanced SIMD and floating-point multiply with accumulate</header>
          <decode>
            <box hibit="25" width="3" name="op0" usename="1">
              <c colspan="3">10x</c>
            </box>
            <box hibit="21" width="6" name="op1" usename="1">
              <c colspan="6" />
            </box>
            <box hibit="10" width="1" name="op2" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="9" width="2" name="op3" usename="1">
              <c colspan="2">00</c>
            </box>
            <box hibit="6" width="1" name="op4" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="4" width="1" name="op5" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="simd_dotprod">
          <header>Advanced SIMD and floating-point dot product</header>
          <decode>
            <box hibit="25" width="3" name="op0" usename="1">
              <c colspan="3">10x</c>
            </box>
            <box hibit="21" width="6" name="op1" usename="1">
              <c colspan="6" />
            </box>
            <box hibit="10" width="1" name="op2" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="9" width="2" name="op3" usename="1">
              <c colspan="2">0x</c>
            </box>
            <box hibit="6" width="1" name="op4" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="4" width="1" name="op5" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
      </node>
      <node groupname="sysldst_mov64">
        <header>Advanced SIMD and System register load/store and 64-bit move</header>
        <decode>
          <box hibit="31" width="4" name="cond" usename="1">
            <c colspan="4">!= 1111</c>
          </box>
          <box hibit="25" width="2" name="op0" usename="1">
            <c colspan="2">0x</c>
          </box>
          <box hibit="11" width="2" name="op1" usename="1">
            <c colspan="2">1x</c>
          </box>
          <box hibit="4" width="1" name="op2" usename="1">
            <c colspan="1" />
          </box>
        </decode>
        <regdiagram form="32">
          <box hibit="31" width="4">
            <c colspan="4">!= 1111</c>
          </box>
          <box hibit="27" width="3">
            <c colspan="3">110</c>
          </box>
          <box hibit="24" width="4" name="op0" usename="1">
            <c colspan="4" />
          </box>
          <box hibit="20" width="9">
            <c colspan="9" />
          </box>
          <box hibit="11" width="1">
            <c colspan="1">1</c>
          </box>
          <box hibit="10" width="2" name="op1" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="8" width="9">
            <c colspan="9" />
          </box>
        </regdiagram>
        <node iclass="movsimdfpgp64">
          <header>Advanced SIMD and floating-point 64-bit move</header>
          <decode>
            <box hibit="24" width="4" name="op0" usename="1">
              <c colspan="4">00x0</c>
            </box>
            <box hibit="10" width="2" name="op1" usename="1">
              <c colspan="2">0x</c>
            </box>
          </decode>
        </node>
        <node iclass="movcpgp64">
          <header>System register 64-bit move</header>
          <decode>
            <box hibit="24" width="4" name="op0" usename="1">
              <c colspan="4">00x0</c>
            </box>
            <box hibit="10" width="2" name="op1" usename="1">
              <c colspan="2">11</c>
            </box>
          </decode>
        </node>
        <node iclass="ldstsimdfp">
          <header>Advanced SIMD and floating-point load/store</header>
          <decode>
            <box hibit="24" width="4" name="op0" usename="1">
              <c colspan="4">!= 00x0</c>
            </box>
            <box hibit="10" width="2" name="op1" usename="1">
              <c colspan="2">0x</c>
            </box>
          </decode>
        </node>
        <node iclass="ldstcp">
          <header>System register load/store</header>
          <decode>
            <box hibit="24" width="4" name="op0" usename="1">
              <c colspan="4">!= 00x0</c>
            </box>
            <box hibit="10" width="2" name="op1" usename="1">
              <c colspan="2">11</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_117" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="4" name="op0" usename="1">
              <c colspan="4" />
            </box>
            <box hibit="10" width="2" name="op1" usename="1">
              <c colspan="2">10</c>
            </box>
          </decode>
        </node>
      </node>
      <node groupname="sys_mov32">
        <header>Advanced SIMD and System register 32-bit move</header>
        <decode>
          <box hibit="31" width="4" name="cond" usename="1">
            <c colspan="4">!= 1111</c>
          </box>
          <box hibit="25" width="2" name="op0" usename="1">
            <c colspan="2">10</c>
          </box>
          <box hibit="11" width="2" name="op1" usename="1">
            <c colspan="2">1x</c>
          </box>
          <box hibit="4" width="1" name="op2" usename="1">
            <c colspan="1">1</c>
          </box>
        </decode>
        <regdiagram form="32">
          <box hibit="31" width="4">
            <c colspan="4">!= 1111</c>
          </box>
          <box hibit="27" width="4">
            <c colspan="4">1110</c>
          </box>
          <box hibit="23" width="3" name="op0" usename="1">
            <c colspan="3" />
          </box>
          <box hibit="20" width="9">
            <c colspan="9" />
          </box>
          <box hibit="11" width="1">
            <c colspan="1">1</c>
          </box>
          <box hibit="10" width="3" name="op1" usename="1">
            <c colspan="3" />
          </box>
          <box hibit="7" width="3">
            <c colspan="3" />
          </box>
          <box hibit="4" width="1">
            <c colspan="1">1</c>
          </box>
          <box hibit="3" width="4">
            <c colspan="4" />
          </box>
        </regdiagram>
        <node iclass="UNALLOCATED_124" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="23" width="3" name="op0" usename="1">
              <c colspan="3">000</c>
            </box>
            <box hibit="10" width="3" name="op1" usename="1">
              <c colspan="3">000</c>
            </box>
          </decode>
        </node>
        <node iclass="movfpgp16">
          <header>Floating-point 16-bit move</header>
          <decode>
            <box hibit="23" width="3" name="op0" usename="1">
              <c colspan="3">000</c>
            </box>
            <box hibit="10" width="3" name="op1" usename="1">
              <c colspan="3">001</c>
            </box>
          </decode>
        </node>
        <node iclass="movfpgp32">
          <header>Floating-point 32-bit move</header>
          <decode>
            <box hibit="23" width="3" name="op0" usename="1">
              <c colspan="3">000</c>
            </box>
            <box hibit="10" width="3" name="op1" usename="1">
              <c colspan="3">010</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_127" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="23" width="3" name="op0" usename="1">
              <c colspan="3">001</c>
            </box>
            <box hibit="10" width="3" name="op1" usename="1">
              <c colspan="3">010</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_128" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="23" width="3" name="op0" usename="1">
              <c colspan="3">01x</c>
            </box>
            <box hibit="10" width="3" name="op1" usename="1">
              <c colspan="3">010</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_129" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="23" width="3" name="op0" usename="1">
              <c colspan="3">10x</c>
            </box>
            <box hibit="10" width="3" name="op1" usename="1">
              <c colspan="3">010</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_130" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="23" width="3" name="op0" usename="1">
              <c colspan="3">110</c>
            </box>
            <box hibit="10" width="3" name="op1" usename="1">
              <c colspan="3">010</c>
            </box>
          </decode>
        </node>
        <node iclass="movfpsr">
          <header>Floating-point move special register</header>
          <decode>
            <box hibit="23" width="3" name="op0" usename="1">
              <c colspan="3">111</c>
            </box>
            <box hibit="10" width="3" name="op1" usename="1">
              <c colspan="3">010</c>
            </box>
          </decode>
        </node>
        <node iclass="movsimdgp">
          <header>Advanced SIMD 8/16/32-bit element move/duplicate</header>
          <decode>
            <box hibit="23" width="3" name="op0" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="10" width="3" name="op1" usename="1">
              <c colspan="3">011</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_133" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="23" width="3" name="op0" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="10" width="3" name="op1" usename="1">
              <c colspan="3">10x</c>
            </box>
          </decode>
        </node>
        <node iclass="movcpgp32">
          <header>System register 32-bit move</header>
          <decode>
            <box hibit="23" width="3" name="op0" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="10" width="3" name="op1" usename="1">
              <c colspan="3">11x</c>
            </box>
          </decode>
        </node>
      </node>
      <node groupname="fpdp">
        <header>Floating-point data-processing</header>
        <decode>
          <box hibit="31" width="4" name="cond" usename="1">
            <c colspan="4">!= 1111</c>
          </box>
          <box hibit="25" width="2" name="op0" usename="1">
            <c colspan="2">10</c>
          </box>
          <box hibit="11" width="2" name="op1" usename="1">
            <c colspan="2">10</c>
          </box>
          <box hibit="4" width="1" name="op2" usename="1">
            <c colspan="1">0</c>
          </box>
        </decode>
        <regdiagram form="32">
          <box hibit="31" width="4">
            <c colspan="4">!= 1111</c>
          </box>
          <box hibit="27" width="4">
            <c colspan="4">1110</c>
          </box>
          <box hibit="23" width="4" name="op0" usename="1">
            <c colspan="4" />
          </box>
          <box hibit="19" width="8">
            <c colspan="8" />
          </box>
          <box hibit="11" width="2">
            <c colspan="2">10</c>
          </box>
          <box hibit="9" width="3">
            <c colspan="3" />
          </box>
          <box hibit="6" width="1" name="op1" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="5" width="1">
            <c colspan="1" />
          </box>
          <box hibit="4" width="1">
            <c colspan="1">0</c>
          </box>
          <box hibit="3" width="4">
            <c colspan="4" />
          </box>
        </regdiagram>
        <node iclass="fpdp2reg">
          <header>Floating-point data-processing (two registers)</header>
          <decode>
            <box hibit="23" width="4" name="op0" usename="1">
              <c colspan="4">1x11</c>
            </box>
            <box hibit="6" width="1" name="op1" usename="1">
              <c colspan="1">1</c>
            </box>
          </decode>
        </node>
        <node iclass="fpimm">
          <header>Floating-point move immediate</header>
          <decode>
            <box hibit="23" width="4" name="op0" usename="1">
              <c colspan="4">1x11</c>
            </box>
            <box hibit="6" width="1" name="op1" usename="1">
              <c colspan="1">0</c>
            </box>
          </decode>
        </node>
        <node iclass="fpdp3reg">
          <header>Floating-point data-processing (three registers)</header>
          <decode>
            <box hibit="23" width="4" name="op0" usename="1">
              <c colspan="4">!= 1x11</c>
            </box>
            <box hibit="6" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
      </node>
      <node iclass="unalloc_cops3" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="31" width="4" name="cond" usename="1">
            <c colspan="4">!= 1111</c>
          </box>
          <box hibit="25" width="2" name="op0" usename="1">
            <c colspan="2">10</c>
          </box>
          <box hibit="11" width="2" name="op1" usename="1">
            <c colspan="2">11</c>
          </box>
          <box hibit="4" width="1" name="op2" usename="1">
            <c colspan="1">0</c>
          </box>
        </decode>
      </node>
    </node>
    <node groupname="uncond_as">
      <header>Unconditional instructions</header>
      <decode>
        <box hibit="31" width="4" name="cond" usename="1">
          <c colspan="4">1111</c>
        </box>
        <box hibit="27" width="3" name="op0" usename="1">
          <c colspan="3">0xx</c>
        </box>
        <box hibit="4" width="1" name="op1" usename="1">
          <c colspan="1" />
        </box>
      </decode>
      <regdiagram form="32">
        <box hibit="31" width="5">
          <c colspan="5">11110</c>
        </box>
        <box hibit="26" width="3" name="op0" usename="1">
          <c colspan="3" />
        </box>
        <box hibit="23" width="3">
          <c colspan="3" />
        </box>
        <box hibit="20" width="1" name="op1" usename="1">
          <c colspan="1" />
        </box>
        <box hibit="19" width="20">
          <c colspan="20" />
        </box>
      </regdiagram>
      <node groupname="uncondmisc">
        <header>Miscellaneous</header>
        <decode>
          <box hibit="26" width="3" name="op0" usename="1">
            <c colspan="3">00x</c>
          </box>
          <box hibit="20" width="1" name="op1" usename="1">
            <c colspan="1" />
          </box>
        </decode>
        <regdiagram form="32">
          <box hibit="31" width="7">
            <c colspan="7">1111000</c>
          </box>
          <box hibit="24" width="5" name="op0" usename="1">
            <c colspan="5" />
          </box>
          <box hibit="19" width="12">
            <c colspan="12" />
          </box>
          <box hibit="7" width="4" name="op1" usename="1">
            <c colspan="4" />
          </box>
          <box hibit="3" width="4">
            <c colspan="4" />
          </box>
        </regdiagram>
        <node iclass="UNALLOCATED_38" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="5" name="op0" usename="1">
              <c colspan="5">0xxxx</c>
            </box>
            <box hibit="7" width="4" name="op1" usename="1">
              <c colspan="4" />
            </box>
          </decode>
        </node>
        <node iclass="cps">
          <header>Change Process State</header>
          <decode>
            <box hibit="24" width="5" name="op0" usename="1">
              <c colspan="5">10000</c>
            </box>
            <box hibit="7" width="4" name="op1" usename="1">
              <c colspan="4">xx0x</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_43" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="5" name="op0" usename="1">
              <c colspan="5">10001</c>
            </box>
            <box hibit="7" width="4" name="op1" usename="1">
              <c colspan="4">1000</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_42" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="5" name="op0" usename="1">
              <c colspan="5">10001</c>
            </box>
            <box hibit="7" width="4" name="op1" usename="1">
              <c colspan="4">x100</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_41" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="5" name="op0" usename="1">
              <c colspan="5">10001</c>
            </box>
            <box hibit="7" width="4" name="op1" usename="1">
              <c colspan="4">xx01</c>
            </box>
          </decode>
        </node>
        <node iclass="setpan">
          <header>SETPAN</header>
          <decode>
            <box hibit="24" width="5" name="op0" usename="1">
              <c colspan="5">10001</c>
            </box>
            <box hibit="7" width="4" name="op1" usename="1">
              <c colspan="4">0000</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_44" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="5" name="op0" usename="1">
              <c colspan="5">1000x</c>
            </box>
            <box hibit="7" width="4" name="op1" usename="1">
              <c colspan="4">0111</c>
            </box>
          </decode>
        </node>
        <node iclass="UNPREDICTABLE_46" unpredictable="1">
          <header>UNPREDICTABLE</header>
          <decode>
            <box hibit="24" width="5" name="op0" usename="1">
              <c colspan="5">10010</c>
            </box>
            <box hibit="7" width="4" name="op1" usename="1">
              <c colspan="4">0111</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_47" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="5" name="op0" usename="1">
              <c colspan="5">10011</c>
            </box>
            <box hibit="7" width="4" name="op1" usename="1">
              <c colspan="4">0111</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_45" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="5" name="op0" usename="1">
              <c colspan="5">1001x</c>
            </box>
            <box hibit="7" width="4" name="op1" usename="1">
              <c colspan="4">xx0x</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_48" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="5" name="op0" usename="1">
              <c colspan="5">100xx</c>
            </box>
            <box hibit="7" width="4" name="op1" usename="1">
              <c colspan="4">0011</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_49" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="5" name="op0" usename="1">
              <c colspan="5">100xx</c>
            </box>
            <box hibit="7" width="4" name="op1" usename="1">
              <c colspan="4">0x10</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_50" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="5" name="op0" usename="1">
              <c colspan="5">100xx</c>
            </box>
            <box hibit="7" width="4" name="op1" usename="1">
              <c colspan="4">1x1x</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_51" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="5" name="op0" usename="1">
              <c colspan="5">101xx</c>
            </box>
            <box hibit="7" width="4" name="op1" usename="1">
              <c colspan="4" />
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_52" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="5" name="op0" usename="1">
              <c colspan="5">11xxx</c>
            </box>
            <box hibit="7" width="4" name="op1" usename="1">
              <c colspan="4" />
            </box>
          </decode>
        </node>
      </node>
      <node groupname="advsimddp">
        <header>Advanced SIMD data-processing</header>
        <decode>
          <box hibit="26" width="3" name="op0" usename="1">
            <c colspan="3">01x</c>
          </box>
          <box hibit="20" width="1" name="op1" usename="1">
            <c colspan="1" />
          </box>
        </decode>
        <regdiagram form="32">
          <box hibit="31" width="7">
            <c colspan="7">1111001</c>
          </box>
          <box hibit="24" width="1">
            <c colspan="1" />
          </box>
          <box hibit="23" width="1" name="op0" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="22" width="18">
            <c colspan="18" />
          </box>
          <box hibit="4" width="1" name="op1" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="3" width="4">
            <c colspan="4" />
          </box>
        </regdiagram>
        <node iclass="simd3reg_same">
          <header>Advanced SIMD three registers of the same length</header>
          <decode>
            <box hibit="23" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="4" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node groupname="a_simd_mulreg">
          <header>Advanced SIMD two registers, or three registers of different lengths</header>
          <decode>
            <box hibit="23" width="1" name="op0" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="4" width="1" name="op1" usename="1">
              <c colspan="1">0</c>
            </box>
          </decode>
          <regdiagram form="32">
            <box hibit="31" width="7">
              <c colspan="7">1111001</c>
            </box>
            <box hibit="24" width="1" name="op0" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="23" width="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="22" width="1">
              <c colspan="1" />
            </box>
            <box hibit="21" width="2" name="op1" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="19" width="8">
              <c colspan="8" />
            </box>
            <box hibit="11" width="2" name="op2" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="9" width="3">
              <c colspan="3" />
            </box>
            <box hibit="6" width="1" name="op3" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="5" width="1">
              <c colspan="1" />
            </box>
            <box hibit="4" width="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="3" width="4">
              <c colspan="4" />
            </box>
          </regdiagram>
          <node iclass="simd3reg_ext">
            <header>Advanced SIMD vector extract</header>
            <decode>
              <box hibit="24" width="1" name="op0" usename="1">
                <c colspan="1">0</c>
              </box>
              <box hibit="21" width="2" name="op1" usename="1">
                <c colspan="2">11</c>
              </box>
              <box hibit="11" width="2" name="op2" usename="1">
                <c colspan="2" />
              </box>
              <box hibit="6" width="1" name="op3" usename="1">
                <c colspan="1" />
              </box>
            </decode>
          </node>
          <node iclass="simd2reg_misc">
            <header>Advanced SIMD two registers misc</header>
            <decode>
              <box hibit="24" width="1" name="op0" usename="1">
                <c colspan="1">1</c>
              </box>
              <box hibit="21" width="2" name="op1" usename="1">
                <c colspan="2">11</c>
              </box>
              <box hibit="11" width="2" name="op2" usename="1">
                <c colspan="2">0x</c>
              </box>
              <box hibit="6" width="1" name="op3" usename="1">
                <c colspan="1" />
              </box>
            </decode>
          </node>
          <node iclass="simd3reg_tbl">
            <header>Advanced SIMD table permute</header>
            <decode>
              <box hibit="24" width="1" name="op0" usename="1">
                <c colspan="1">1</c>
              </box>
              <box hibit="21" width="2" name="op1" usename="1">
                <c colspan="2">11</c>
              </box>
              <box hibit="11" width="2" name="op2" usename="1">
                <c colspan="2">10</c>
              </box>
              <box hibit="6" width="1" name="op3" usename="1">
                <c colspan="1" />
              </box>
            </decode>
          </node>
          <node iclass="simd2reg_dup">
            <header>Advanced SIMD duplicate (scalar)</header>
            <decode>
              <box hibit="24" width="1" name="op0" usename="1">
                <c colspan="1">1</c>
              </box>
              <box hibit="21" width="2" name="op1" usename="1">
                <c colspan="2">11</c>
              </box>
              <box hibit="11" width="2" name="op2" usename="1">
                <c colspan="2">11</c>
              </box>
              <box hibit="6" width="1" name="op3" usename="1">
                <c colspan="1" />
              </box>
            </decode>
          </node>
          <node iclass="simd3reg_diff">
            <header>Advanced SIMD three registers of different lengths</header>
            <decode>
              <box hibit="24" width="1" name="op0" usename="1">
                <c colspan="1" />
              </box>
              <box hibit="21" width="2" name="op1" usename="1">
                <c colspan="2">!= 11</c>
              </box>
              <box hibit="11" width="2" name="op2" usename="1">
                <c colspan="2" />
              </box>
              <box hibit="6" width="1" name="op3" usename="1">
                <c colspan="1">0</c>
              </box>
            </decode>
          </node>
          <node iclass="simd2reg_scalar">
            <header>Advanced SIMD two registers and a scalar</header>
            <decode>
              <box hibit="24" width="1" name="op0" usename="1">
                <c colspan="1" />
              </box>
              <box hibit="21" width="2" name="op1" usename="1">
                <c colspan="2">!= 11</c>
              </box>
              <box hibit="11" width="2" name="op2" usename="1">
                <c colspan="2" />
              </box>
              <box hibit="6" width="1" name="op3" usename="1">
                <c colspan="1">1</c>
              </box>
            </decode>
          </node>
        </node>
        <node groupname="a_simd_12reg">
          <header>Advanced SIMD shifts and immediate generation</header>
          <decode>
            <box hibit="23" width="1" name="op0" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="4" width="1" name="op1" usename="1">
              <c colspan="1">1</c>
            </box>
          </decode>
          <regdiagram form="32">
            <box hibit="31" width="7">
              <c colspan="7">1111001</c>
            </box>
            <box hibit="24" width="1">
              <c colspan="1" />
            </box>
            <box hibit="23" width="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="22" width="1">
              <c colspan="1" />
            </box>
            <box hibit="21" width="15" name="op0" usename="1">
              <c colspan="15" />
            </box>
            <box hibit="6" width="2">
              <c colspan="2" />
            </box>
            <box hibit="4" width="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="3" width="4">
              <c colspan="4" />
            </box>
          </regdiagram>
          <node iclass="simd1reg_imm">
            <header>Advanced SIMD one register and modified immediate</header>
            <decode>
              <box hibit="21" width="15" name="op0" usename="1">
                <c colspan="15">000xxxxxxxxxxx0</c>
              </box>
            </decode>
          </node>
          <node iclass="simd2reg_shift">
            <header>Advanced SIMD two registers and shift amount</header>
            <decode>
              <box hibit="21" width="15" name="op0" usename="1">
                <c colspan="15">!= 000xxxxxxxxxxx0</c>
              </box>
            </decode>
          </node>
        </node>
      </node>
      <node groupname="uncondhints">
        <header>Memory hints and barriers</header>
        <decode>
          <box hibit="26" width="3" name="op0" usename="1">
            <c colspan="3">1xx</c>
          </box>
          <box hibit="20" width="1" name="op1" usename="1">
            <c colspan="1">1</c>
          </box>
        </decode>
        <regdiagram form="32">
          <box hibit="31" width="6">
            <c colspan="6">111101</c>
          </box>
          <box hibit="25" width="5" name="op0" usename="1">
            <c colspan="5" />
          </box>
          <box hibit="20" width="1">
            <c colspan="1">1</c>
          </box>
          <box hibit="19" width="15">
            <c colspan="15" />
          </box>
          <box hibit="4" width="1" name="op1" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="3" width="4">
            <c colspan="4" />
          </box>
        </regdiagram>
        <node iclass="UNPREDICTABLE_70" unpredictable="1">
          <header>UNPREDICTABLE</header>
          <decode>
            <box hibit="25" width="5" name="op0" usename="1">
              <c colspan="5">00xx1</c>
            </box>
            <box hibit="4" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="UNPREDICTABLE_69" unpredictable="1">
          <header>UNPREDICTABLE</header>
          <decode>
            <box hibit="25" width="5" name="op0" usename="1">
              <c colspan="5">01001</c>
            </box>
            <box hibit="4" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="barriers">
          <header>Barriers</header>
          <decode>
            <box hibit="25" width="5" name="op0" usename="1">
              <c colspan="5">01011</c>
            </box>
            <box hibit="4" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="UNPREDICTABLE_72" unpredictable="1">
          <header>UNPREDICTABLE</header>
          <decode>
            <box hibit="25" width="5" name="op0" usename="1">
              <c colspan="5">011x1</c>
            </box>
            <box hibit="4" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="preload_imm">
          <header>Preload (immediate)</header>
          <decode>
            <box hibit="25" width="5" name="op0" usename="1">
              <c colspan="5">0xxx0</c>
            </box>
            <box hibit="4" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="preload_reg">
          <header>Preload (register)</header>
          <decode>
            <box hibit="25" width="5" name="op0" usename="1">
              <c colspan="5">1xxx0</c>
            </box>
            <box hibit="4" width="1" name="op1" usename="1">
              <c colspan="1">0</c>
            </box>
          </decode>
        </node>
        <node iclass="UNPREDICTABLE_78" unpredictable="1">
          <header>UNPREDICTABLE</header>
          <decode>
            <box hibit="25" width="5" name="op0" usename="1">
              <c colspan="5">1xxx1</c>
            </box>
            <box hibit="4" width="1" name="op1" usename="1">
              <c colspan="1">0</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_79" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="25" width="5" name="op0" usename="1">
              <c colspan="5">1xxxx</c>
            </box>
            <box hibit="4" width="1" name="op1" usename="1">
              <c colspan="1">1</c>
            </box>
          </decode>
        </node>
      </node>
      <node groupname="advsimdls">
        <header>Advanced SIMD element or structure load/store</header>
        <decode>
          <box hibit="26" width="3" name="op0" usename="1">
            <c colspan="3">100</c>
          </box>
          <box hibit="20" width="1" name="op1" usename="1">
            <c colspan="1">0</c>
          </box>
        </decode>
        <regdiagram form="32">
          <box hibit="31" width="8">
            <c colspan="8">11110100</c>
          </box>
          <box hibit="23" width="1" name="op0" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="22" width="2">
            <c colspan="2" />
          </box>
          <box hibit="20" width="1">
            <c colspan="1">0</c>
          </box>
          <box hibit="19" width="8">
            <c colspan="8" />
          </box>
          <box hibit="11" width="2" name="op1" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="9" width="10">
            <c colspan="10" />
          </box>
        </regdiagram>
        <node iclass="ldstv_ms">
          <header>Advanced SIMD load/store multiple structures</header>
          <decode>
            <box hibit="23" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="11" width="2" name="op1" usename="1">
              <c colspan="2" />
            </box>
          </decode>
        </node>
        <node iclass="ldv_ssall">
          <header>Advanced SIMD load single structure to all lanes</header>
          <decode>
            <box hibit="23" width="1" name="op0" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="11" width="2" name="op1" usename="1">
              <c colspan="2">11</c>
            </box>
          </decode>
        </node>
        <node iclass="ldstv_ssone">
          <header>Advanced SIMD load/store single structure to one lane</header>
          <decode>
            <box hibit="23" width="1" name="op0" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="11" width="2" name="op1" usename="1">
              <c colspan="2">!= 11</c>
            </box>
          </decode>
        </node>
      </node>
      <node iclass="unalloc2" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="26" width="3" name="op0" usename="1">
            <c colspan="3">101</c>
          </box>
          <box hibit="20" width="1" name="op1" usename="1">
            <c colspan="1">0</c>
          </box>
        </decode>
      </node>
      <node iclass="UNALLOCATED_109" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="26" width="3" name="op0" usename="1">
            <c colspan="3">11x</c>
          </box>
          <box hibit="20" width="1" name="op1" usename="1">
            <c colspan="1">0</c>
          </box>
        </decode>
      </node>
    </node>
  </hierarchy>
  <groups heading="Top-level Encoding Groups">
    <maintable class="grouptable" size="32" howmanybits="32">
      <col bitno="31" colno="1" printwidth="0.019in" />
      <col bitno="30" colno="2" printwidth="0.019in" />
      <col bitno="29" colno="3" printwidth="0.019in" />
      <col bitno="28" colno="4" printwidth="0.019in" />
      <col bitno="27" colno="5" printwidth="0.019in" />
      <col bitno="26" colno="6" printwidth="0.019in" />
      <col bitno="25" colno="7" printwidth="0.019in" />
      <col bitno="24" colno="8" printwidth="0.019in" />
      <col bitno="23" colno="9" printwidth="0.019in" />
      <col bitno="22" colno="10" printwidth="0.019in" />
      <col bitno="21" colno="11" printwidth="0.019in" />
      <col bitno="20" colno="12" printwidth="0.019in" />
      <col bitno="19" colno="13" printwidth="0.019in" />
      <col bitno="18" colno="14" printwidth="0.019in" />
      <col bitno="17" colno="15" printwidth="0.019in" />
      <col bitno="16" colno="16" printwidth="0.019in" />
      <col bitno="15" colno="17" printwidth="0.019in" />
      <col bitno="14" colno="18" printwidth="0.019in" />
      <col bitno="13" colno="19" printwidth="0.019in" />
      <col bitno="12" colno="20" printwidth="0.019in" />
      <col bitno="11" colno="21" printwidth="0.019in" />
      <col bitno="10" colno="22" printwidth="0.019in" />
      <col bitno="9" colno="23" printwidth="0.019in" />
      <col bitno="8" colno="24" printwidth="0.019in" />
      <col bitno="7" colno="25" printwidth="0.019in" />
      <col bitno="6" colno="26" printwidth="0.019in" />
      <col bitno="5" colno="27" printwidth="0.019in" />
      <col bitno="4" colno="28" printwidth="0.019in" />
      <col bitno="3" colno="29" printwidth="0.019in" />
      <col bitno="2" colno="30" printwidth="0.019in" />
      <col bitno="1" colno="31" printwidth="0.019in" />
      <col bitno="0" colno="32" printwidth="0.019in" />
      <col colno="33" printwidth="0.400in" />
      <tableheader>
        <tr class="header1">
          <th colno="1" colspan="32">Instruction bits</th>
          <th colno="33" rowspan="2">Encoding Group</th>
        </tr>
        <tr class="header2-morebits">
          <th class="boxleft">31</th>
          <th>30</th>
          <th>29</th>
          <th>28</th>
          <th>27</th>
          <th>26</th>
          <th>25</th>
          <th>24</th>
          <th>23</th>
          <th>22</th>
          <th>21</th>
          <th>20</th>
          <th>19</th>
          <th>18</th>
          <th>17</th>
          <th>16</th>
          <th>15</th>
          <th>14</th>
          <th>13</th>
          <th>12</th>
          <th>11</th>
          <th>10</th>
          <th>9</th>
          <th>8</th>
          <th>7</th>
          <th>6</th>
          <th>5</th>
          <th>4</th>
          <th>3</th>
          <th>2</th>
          <th>1</th>
          <th class="boxright">0</th>
        </tr>
      </tableheader>
      <tablebody>
        <tr class="maintable" size="32" groupid="main" groupname="dp">
          <td colspan="4" class="boxleft">!= 1111</td>
          <td>0</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a>Data-processing and miscellaneous instructions</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="main" iclass="ldstwbi">
          <td colspan="4" class="boxleft">!= 1111</td>
          <td>0</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="ldstwbi">Load/store word and unsigned byte (immediate)</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="main" iclass="ldstwbr">
          <td colspan="4" class="boxleft">!= 1111</td>
          <td>0</td>
          <td>1</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="ldstwbr">Load/store word and unsigned byte (register)</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="main" iclass="media">
          <td colspan="4" class="boxleft">!= 1111</td>
          <td>0</td>
          <td>1</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="media">Media instructions</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="main" iclass="brblk">
          <td class="boxleft"></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="brblk">Branch, branch with link, and block data transfer</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="main" groupname="cops_as">
          <td class="boxleft"></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a>System register access, Advanced SIMD, floating-point, and Supervisor call</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="main" groupname="uncond_as">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a>Unconditional instructions</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="dp" iclass="dpregis">
          <td colspan="4" class="boxleft">!= 1111</td>
          <td>0</td>
          <td>0</td>
          <td>0</td>
          <td colspan="5">!= 10xx0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="dpregis">Data-processing and miscellaneous instructions / Data-processing register (immediate shift)</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="dp" iclass="dpregrs">
          <td colspan="4" class="boxleft">!= 1111</td>
          <td>0</td>
          <td>0</td>
          <td>0</td>
          <td colspan="5">!= 10xx0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="dpregrs">Data-processing and miscellaneous instructions / Data-processing register (register shift)</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="dp" iclass="dpmisc">
          <td colspan="4" class="boxleft">!= 1111</td>
          <td>0</td>
          <td>0</td>
          <td>0</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="dpmisc">Data-processing and miscellaneous instructions / Miscellaneous</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="dp" iclass="dphwm">
          <td colspan="4" class="boxleft">!= 1111</td>
          <td>0</td>
          <td>0</td>
          <td>0</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="dphwm">Data-processing and miscellaneous instructions / Halfword multiply and multiply accumulate</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="dp" iclass="dpmul">
          <td colspan="4" class="boxleft">!= 1111</td>
          <td>0</td>
          <td>0</td>
          <td>0</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td>0</td>
          <td>0</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="dpmul">Data-processing and miscellaneous instructions / Multiply and multiply accumulate</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="dp" iclass="sync">
          <td colspan="4" class="boxleft">!= 1111</td>
          <td>0</td>
          <td>0</td>
          <td>0</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td>0</td>
          <td>0</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="sync">Data-processing and miscellaneous instructions / Synchronization primitives and Load-Acquire/Store-Release</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="dp" iclass="xldst">
          <td colspan="4" class="boxleft">!= 1111</td>
          <td>0</td>
          <td>0</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td colspan="2">!= 00</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="xldst">Data-processing and miscellaneous instructions / Extra load/store</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="dp" iclass="dpimm">
          <td colspan="4" class="boxleft">!= 1111</td>
          <td>0</td>
          <td>0</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="dpimm">Data-processing and miscellaneous instructions / Data-processing immediate</a>
          </td>
        </tr>
        <tr class="maintable" size="32" undef="1" groupid="cops_as" iclass="unalloc_cops1">
          <td class="boxleft"></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">System register access, Advanced SIMD, floating-point, and Supervisor call / UNALLOCATED</td>
        </tr>
        <tr class="maintable" size="32" undef="1" groupid="cops_as" iclass="unalloc_cops2">
          <td class="boxleft"></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">System register access, Advanced SIMD, floating-point, and Supervisor call / UNALLOCATED</td>
        </tr>
        <tr class="maintable" size="32" groupid="cops_as" iclass="sysldst_mov64">
          <td colspan="4" class="boxleft">!= 1111</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="sysldst_mov64">System register access, Advanced SIMD, floating-point, and Supervisor call / Advanced SIMD and System register load/store and 64-bit move</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="cops_as" iclass="fpdp">
          <td colspan="4" class="boxleft">!= 1111</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="fpdp">System register access, Advanced SIMD, floating-point, and Supervisor call / Floating-point data-processing</a>
          </td>
        </tr>
        <tr class="maintable" undef="1" groupid="cops_as" iclass="unalloc_cops3">
          <td colspan="4" class="boxleft">!= 1111</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">System register access, Advanced SIMD, floating-point, and Supervisor call / UNALLOCATED</td>
        </tr>
        <tr class="maintable" size="32" groupid="cops_as" iclass="sys_mov32">
          <td colspan="4" class="boxleft">!= 1111</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="sys_mov32">System register access, Advanced SIMD, floating-point, and Supervisor call / Advanced SIMD and System register 32-bit move</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="cops_as" iclass="advsimdext">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td colspan="2">!= 11</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="advsimdext">System register access, Advanced SIMD, floating-point, and Supervisor call / Unconditional Advanced SIMD and floating-point instructions</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="cops_as" iclass="svcall">
          <td class="boxleft"></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="svcall">System register access, Advanced SIMD, floating-point, and Supervisor call / Supervisor call</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="uncond_as" iclass="uncondmisc">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td>0</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="uncondmisc">Unconditional instructions / Miscellaneous</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="uncond_as" groupname="advsimddp">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td>0</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a>Unconditional instructions / Advanced SIMD data-processing</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="uncond_as" iclass="uncondhints">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="uncondhints">Unconditional instructions / Memory hints and barriers</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="uncond_as" iclass="advsimdls">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td>1</td>
          <td>0</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="advsimdls">Unconditional instructions / Advanced SIMD element or structure load/store</a>
          </td>
        </tr>
        <tr class="maintable" undef="1" groupid="uncond_as" iclass="unalloc2">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td>1</td>
          <td>0</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">Unconditional instructions / UNALLOCATED</td>
        </tr>
        <tr class="maintable" size="32" undef="1" groupid="uncond_as" iclass="unalloc3">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td>1</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">Unconditional instructions / UNALLOCATED</td>
        </tr>
        <tr class="maintable" size="32" groupid="advsimddp" iclass="a_simd3reg_same">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td>0</td>
          <td>1</td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="a_simd3reg_same">Unconditional instructions / Advanced SIMD data-processing / Advanced SIMD three registers of the same length</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="advsimddp" iclass="a_simd_mulreg">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td>0</td>
          <td>1</td>
          <td></td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="a_simd_mulreg">Unconditional instructions / Advanced SIMD data-processing / Advanced SIMD two registers, or three registers of different lengths</a>
          </td>
        </tr>
        <tr class="maintable" size="32" groupid="advsimddp" iclass="a_simd_12reg">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td>0</td>
          <td>1</td>
          <td></td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="a_simd_12reg">Unconditional instructions / Advanced SIMD data-processing / Advanced SIMD shifts and immediate generation</a>
          </td>
        </tr>
      </tablebody>
    </maintable>
  </groups>
  <maintable class="allclasses" size="32" howmanybits="32">
    <col bitno="31" colno="1" printwidth="0.019in" />
    <col bitno="30" colno="2" printwidth="0.019in" />
    <col bitno="29" colno="3" printwidth="0.019in" />
    <col bitno="28" colno="4" printwidth="0.019in" />
    <col bitno="27" colno="5" printwidth="0.019in" />
    <col bitno="26" colno="6" printwidth="0.019in" />
    <col bitno="25" colno="7" printwidth="0.019in" />
    <col bitno="24" colno="8" printwidth="0.019in" />
    <col bitno="23" colno="9" printwidth="0.019in" />
    <col bitno="22" colno="10" printwidth="0.019in" />
    <col bitno="21" colno="11" printwidth="0.019in" />
    <col bitno="20" colno="12" printwidth="0.019in" />
    <col bitno="19" colno="13" printwidth="0.019in" />
    <col bitno="18" colno="14" printwidth="0.019in" />
    <col bitno="17" colno="15" printwidth="0.019in" />
    <col bitno="16" colno="16" printwidth="0.019in" />
    <col bitno="15" colno="17" printwidth="0.019in" />
    <col bitno="14" colno="18" printwidth="0.019in" />
    <col bitno="13" colno="19" printwidth="0.019in" />
    <col bitno="12" colno="20" printwidth="0.019in" />
    <col bitno="11" colno="21" printwidth="0.019in" />
    <col bitno="10" colno="22" printwidth="0.019in" />
    <col bitno="9" colno="23" printwidth="0.019in" />
    <col bitno="8" colno="24" printwidth="0.019in" />
    <col bitno="7" colno="25" printwidth="0.019in" />
    <col bitno="6" colno="26" printwidth="0.019in" />
    <col bitno="5" colno="27" printwidth="0.019in" />
    <col bitno="4" colno="28" printwidth="0.019in" />
    <col bitno="3" colno="29" printwidth="0.019in" />
    <col bitno="2" colno="30" printwidth="0.019in" />
    <col bitno="1" colno="31" printwidth="0.019in" />
    <col bitno="0" colno="32" printwidth="0.019in" />
    <col colno="33" printwidth="0.400in" />
    <tableheader>
      <tr class="header1">
        <th colno="1" colspan="32">Instruction bits</th>
        <th colno="33" rowspan="2">Instruction class</th>
      </tr>
      <tr class="header2-morebits">
        <th class="boxleft">31</th>
        <th>30</th>
        <th>29</th>
        <th>28</th>
        <th>27</th>
        <th>26</th>
        <th>25</th>
        <th>24</th>
        <th>23</th>
        <th>22</th>
        <th>21</th>
        <th>20</th>
        <th>19</th>
        <th>18</th>
        <th>17</th>
        <th>16</th>
        <th>15</th>
        <th>14</th>
        <th>13</th>
        <th>12</th>
        <th>11</th>
        <th>10</th>
        <th>9</th>
        <th>8</th>
        <th>7</th>
        <th>6</th>
        <th>5</th>
        <th>4</th>
        <th>3</th>
        <th>2</th>
        <th>1</th>
        <th class="boxright">0</th>
      </tr>
    </tableheader>
    <tablebody>
      <maintablesect sect="Load/store word and unsigned byte (immediate)" linkref="ldstwbi" />
      <tr class="maintable" size="32" groupid="ldstwbi" iclass="ldstimm">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldstimm">Load/Store Word, Unsigned Byte (immediate, literal)</a>
        </td>
      </tr>
      <maintablesect sect="Load/store word and unsigned byte (register)" linkref="ldstwbr" />
      <tr class="maintable" size="32" groupid="ldstwbr" iclass="ldstreg">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldstreg">Load/Store Word, Unsigned Byte (register)</a>
        </td>
      </tr>
      <maintablesect sect="Media instructions" linkref="media" />
      <tr class="maintable" size="32" groupid="media" iclass="parallel">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="parallel">Parallel Arithmetic</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="media" iclass="extend">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="extend">Extend and Add</a>
        </td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="media" iclass="UNALLOCATED_93">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" groupid="media" iclass="sat32">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="sat32">Saturate 32-bit</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="media" iclass="sat16">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="sat16">Saturate 16-bit</a>
        </td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="media" iclass="UNALLOCATED_89">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" groupid="media" iclass="reverse">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="reverse">Reverse Bit/Byte</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="media" iclass="pack">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="pack">Pack Halfword</a>
        </td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="media" iclass="UNALLOCATED_85">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" groupid="media" iclass="selbytes">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="selbytes">Select Bytes</a>
        </td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="media" iclass="UNALLOCATED_82">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="media" iclass="UNALLOCATED_87">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="media" iclass="UNALLOCATED_84">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="media" iclass="UNALLOCATED_91">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" groupid="media" iclass="smul_div">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="smul_div">Signed multiply, Divide</a>
        </td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="media" iclass="UNALLOCATED_101">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="media" iclass="UNALLOCATED_104">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="media" iclass="UNALLOCATED_102">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" groupid="media" iclass="bfx">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="bfx">Bitfield Extract</a>
        </td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="media" iclass="UNALLOCATED_105">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" groupid="media" iclass="usad">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="usad">Unsigned Sum of Absolute Differences</a>
        </td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="media" iclass="UNALLOCATED_96">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="media" iclass="UNALLOCATED_97">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="media" iclass="UNALLOCATED_98">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" groupid="media" iclass="bfi">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="bfi">Bitfield Insert</a>
        </td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="media" iclass="UNALLOCATED_106">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="media" iclass="UNALLOCATED_100">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="media" iclass="UNALLOCATED_107">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" groupid="media" iclass="udf">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="udf">Permanently UNDEFINED</a>
        </td>
      </tr>
      <maintablesect sect="Branch, branch with link, and block data transfer" linkref="brblk" />
      <tr class="maintable" size="32" groupid="brblk" iclass="b_imm">
        <td class="boxleft"></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="b_imm">Branch (immediate)</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="brblk" iclass="ldstexcept">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldstexcept">Exception Save/Restore</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="brblk" iclass="ldstm">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldstm">Load/Store Multiple</a>
        </td>
      </tr>
      <maintablesect sect="Data-processing register (immediate shift)" linkref="dpregis" />
      <tr class="maintable" size="32" groupid="dpregis" iclass="intdp3reg_immsh">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="intdp3reg_immsh">Integer Data Processing (three register, immediate shift)</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="dpregis" iclass="intdp2reg_immsh">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="intdp2reg_immsh">Integer Test and Compare (two register, immediate shift)</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="dpregis" iclass="logic3reg_immsh">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="logic3reg_immsh">Logical Arithmetic (three register, immediate shift)</a>
        </td>
      </tr>
      <maintablesect sect="Data-processing register (register shift)" linkref="dpregrs" />
      <tr class="maintable" size="32" groupid="dpregrs" iclass="intdp3reg_regsh">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="intdp3reg_regsh">Integer Data Processing (three register, register shift)</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="dpregrs" iclass="intdp2reg_regsh">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="intdp2reg_regsh">Integer Test and Compare (two register, register shift)</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="dpregrs" iclass="logic3reg_regsh">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="logic3reg_regsh">Logical Arithmetic (three register, register shift)</a>
        </td>
      </tr>
      <maintablesect sect="Miscellaneous" linkref="dpmisc" />
      <tr class="maintable" size="32" groupid="dpmisc" iclass="movsr_reg">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="movsr_reg">Move special register (register)</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="dpmisc" iclass="crc32">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="crc32">Cyclic Redundancy Check</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="dpmisc" iclass="intsat">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="intsat">Integer Saturating Arithmetic</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="dpmisc" iclass="except">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="except">Exception Generation</a>
        </td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="dpmisc" iclass="UNALLOCATED_22">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>0</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="dpmisc" iclass="UNALLOCATED_9">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>0</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="dpmisc" iclass="UNALLOCATED_26">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>0</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="dpmisc" iclass="UNALLOCATED_14">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>0</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" groupid="dpmisc" iclass="bx_reg">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="bx_reg">Branch and Exchange (register)</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="dpmisc" iclass="bxj_reg">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="bxj_reg">Branch and Exchange to Jazelle (register)</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="dpmisc" iclass="blx_reg">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="blx_reg">Branch with Link and Exchange (register)</a>
        </td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="dpmisc" iclass="UNALLOCATED_15">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="dpmisc" iclass="UNALLOCATED_24">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>0</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="dpmisc" iclass="UNALLOCATED_11">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>0</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="dpmisc" iclass="UNALLOCATED_28">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>0</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="dpmisc" iclass="UNALLOCATED_16">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>0</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" groupid="dpmisc" iclass="clz">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="clz">Count Leading Zeros</a>
        </td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="dpmisc" iclass="UNALLOCATED_12">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="dpmisc" iclass="UNALLOCATED_29">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" groupid="dpmisc" iclass="eret">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="eret">Exception Return</a>
        </td>
      </tr>
      <maintablesect sect="Halfword multiply and multiply accumulate" linkref="dphwm" />
      <tr class="maintable" size="32" groupid="dphwm" iclass="mul_half">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="mul_half">Halfword Multiply and Accumulate</a>
        </td>
      </tr>
      <maintablesect sect="Multiply and multiply accumulate" linkref="dpmul" />
      <tr class="maintable" size="32" groupid="dpmul" iclass="mul_word">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="mul_word">Multiply and Accumulate</a>
        </td>
      </tr>
      <maintablesect sect="Synchronization primitives and Load-Acquire/Store-Release" linkref="sync" />
      <tr class="maintable" size="32" undef="1" groupid="sync" iclass="UNALLOCATED_34">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" groupid="sync" iclass="ldst_excl">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldst_excl">Load/Store Exclusive and Load-Acquire/Store-Release</a>
        </td>
      </tr>
      <maintablesect sect="Extra load/store" linkref="xldst" />
      <tr class="maintable" size="32" groupid="xldst" iclass="ldstxreg">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td colspan="2">!= 00</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldstxreg">Load/Store Dual, Half, Signed Byte (register)</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="xldst" iclass="ldstximm">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td colspan="2">!= 00</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldstximm">Load/Store Dual, Half, Signed Byte (immediate, literal)</a>
        </td>
      </tr>
      <maintablesect sect="Data-processing immediate" linkref="dpimm" />
      <tr class="maintable" size="32" groupid="dpimm" iclass="intdp2reg_imm">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="intdp2reg_imm">Integer Data Processing (two register and immediate)</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="dpimm" iclass="intdp1reg_imm">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="intdp1reg_imm">Integer Test and Compare (one register and immediate)</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="dpimm" iclass="movw">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="movw">Move Halfword (immediate)</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="dpimm" iclass="movsr_hint_imm">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="movsr_hint_imm">Move Special Register and Hints (immediate)</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="dpimm" iclass="log2reg_imm">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="log2reg_imm">Logical Arithmetic  (two register and immediate)</a>
        </td>
      </tr>
      <maintablesect sect="UNALLOCATED" />
      <tr class="maintable" size="32" undef="1" groupid="unalloc_cops1" iclass="UNALLOCATED_113">
        <td class="boxleft"></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <maintablesect sect="UNALLOCATED" />
      <tr class="maintable" size="32" undef="1" groupid="unalloc_cops2" iclass="UNALLOCATED_120">
        <td class="boxleft"></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <maintablesect sect="Advanced SIMD and System register load/store and 64-bit move" linkref="sysldst_mov64" />
      <tr class="maintable" size="32" undef="1" groupid="sysldst_mov64" iclass="UNALLOCATED_117">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" groupid="sysldst_mov64" iclass="movsimdfpgp64">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="movsimdfpgp64">Advanced SIMD and floating-point 64-bit move</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="sysldst_mov64" iclass="movcpgp64">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="movcpgp64">System register 64-bit move</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="sysldst_mov64" iclass="ldstsimdfp">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td colspan="4">!= 00x0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldstsimdfp">Advanced SIMD and floating-point load/store</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="sysldst_mov64" iclass="ldstcp">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td colspan="4">!= 00x0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldstcp">System register load/store</a>
        </td>
      </tr>
      <maintablesect sect="Floating-point data-processing" linkref="fpdp" />
      <tr class="maintable" size="32" groupid="fpdp" iclass="fpimm">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="fpimm">Floating-point move immediate</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="fpdp" iclass="fpdp2reg">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="fpdp2reg">Floating-point data-processing (two registers)</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="fpdp" iclass="fpdp3reg">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td colspan="4">!= 1x11</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="fpdp3reg">Floating-point data-processing (three registers)</a>
        </td>
      </tr>
      <maintablesect sect="Advanced SIMD and System register 32-bit move" linkref="sys_mov32" />
      <tr class="maintable" size="32" groupid="sys_mov32" iclass="movsimdgp">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="movsimdgp">Advanced SIMD 8/16/32-bit element move/duplicate</a>
        </td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="sys_mov32" iclass="UNALLOCATED_133">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" groupid="sys_mov32" iclass="movcpgp32">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="movcpgp32">System register 32-bit move</a>
        </td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="sys_mov32" iclass="UNALLOCATED_124">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" groupid="sys_mov32" iclass="movfpgp16">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="movfpgp16">Floating-point 16-bit move</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="sys_mov32" iclass="movfpgp32">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="movfpgp32">Floating-point 32-bit move</a>
        </td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="sys_mov32" iclass="UNALLOCATED_127">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="sys_mov32" iclass="UNALLOCATED_128">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="sys_mov32" iclass="UNALLOCATED_129">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="sys_mov32" iclass="UNALLOCATED_130">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" groupid="sys_mov32" iclass="movfpsr">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="movfpsr">Floating-point move special register</a>
        </td>
      </tr>
      <maintablesect sect="Unconditional Advanced SIMD and floating-point instructions" linkref="advsimdext" />
      <tr class="maintable" size="32" groupid="advsimdext" iclass="simd3reg_sameext">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simd3reg_sameext">Advanced SIMD three registers of the same length extension</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="advsimdext" iclass="floatdpmac">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="floatdpmac">Advanced SIMD and floating-point multiply with accumulate</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="advsimdext" iclass="simd_dotprod">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simd_dotprod">Advanced SIMD and floating-point dot product</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="advsimdext" iclass="fpcsel">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td colspan="2">!= 00</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="fpcsel">Floating-point conditional select</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="advsimdext" iclass="fpminmaxnm">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td colspan="2">!= 00</td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="fpminmaxnm">Floating-point minNum/maxNum</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="advsimdext" iclass="fpextins">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td colspan="2">!= 00</td>
        <td></td>
        <td>1</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="fpextins">Floating-point extraction and insertion</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="advsimdext" iclass="fpcvtrnd">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td colspan="2">!= 00</td>
        <td></td>
        <td>1</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="fpcvtrnd">Floating-point directed convert to integer</a>
        </td>
      </tr>
      <maintablesect sect="Supervisor call" linkref="svcall" />
      <tr class="maintable" size="32" undef="1" groupid="svcall" iclass="UNALLOCATED_142">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" groupid="svcall" iclass="svc">
        <td colspan="4" class="boxleft">!= 1111</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="svc">Supervisor Call</a>
        </td>
      </tr>
      <maintablesect sect="Miscellaneous" linkref="uncondmisc" />
      <tr class="maintable" size="32" undef="1" groupid="uncondmisc" iclass="UNALLOCATED_38">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="uncondmisc" iclass="UNALLOCATED_49">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="uncondmisc" iclass="UNALLOCATED_48">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="uncondmisc" iclass="UNALLOCATED_50">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="uncondmisc" iclass="UNALLOCATED_44">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" groupid="uncondmisc" iclass="cps">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="cps">Change Process State</a>
        </td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="uncondmisc" iclass="UNALLOCATED_41">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="uncondmisc" iclass="UNALLOCATED_42">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" groupid="uncondmisc" iclass="setpan">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="setpan">SETPAN</a>
        </td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="uncondmisc" iclass="UNALLOCATED_43">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="uncondmisc" iclass="UNALLOCATED_45">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="uncondmisc" iclass="UNPREDICTABLE_46">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNPREDICTABLE</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="uncondmisc" iclass="UNALLOCATED_47">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="uncondmisc" iclass="UNALLOCATED_51">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="uncondmisc" iclass="UNALLOCATED_52">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <maintablesect sect="Memory hints and barriers" linkref="uncondhints" />
      <tr class="maintable" size="32" groupid="uncondhints" iclass="preload_imm">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="preload_imm">Preload (immediate)</a>
        </td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="uncondhints" iclass="UNPREDICTABLE_70">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNPREDICTABLE</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="uncondhints" iclass="UNPREDICTABLE_69">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNPREDICTABLE</td>
      </tr>
      <tr class="maintable" size="32" groupid="uncondhints" iclass="barriers">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="barriers">Barriers</a>
        </td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="uncondhints" iclass="UNPREDICTABLE_72">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNPREDICTABLE</td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="uncondhints" iclass="UNALLOCATED_79">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="32" groupid="uncondhints" iclass="preload_reg">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="preload_reg">Preload (register)</a>
        </td>
      </tr>
      <tr class="maintable" size="32" undef="1" groupid="uncondhints" iclass="UNPREDICTABLE_78">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNPREDICTABLE</td>
      </tr>
      <maintablesect sect="Advanced SIMD element or structure load/store" linkref="advsimdls" />
      <tr class="maintable" size="32" groupid="advsimdls" iclass="ldstv_ms">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldstv_ms">Advanced SIMD load/store multiple structures</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="advsimdls" iclass="ldv_ssall">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldv_ssall">Advanced SIMD load single structure to all lanes</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="advsimdls" iclass="ldstv_ssone">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="2">!= 11</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldstv_ssone">Advanced SIMD load/store single structure to one lane</a>
        </td>
      </tr>
      <maintablesect sect="UNALLOCATED" />
      <tr class="maintable" size="32" undef="1" groupid="unalloc3" iclass="UNALLOCATED_109">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <maintablesect sect="Advanced SIMD three registers of the same length" linkref="a_simd3reg_same" />
      <tr class="maintable" size="32" groupid="a_simd3reg_same" iclass="simd3reg_same">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simd3reg_same">Advanced SIMD three registers of the same length</a>
        </td>
      </tr>
      <maintablesect sect="Advanced SIMD two registers, or three registers of different lengths" linkref="a_simd_mulreg" />
      <tr class="maintable" size="32" groupid="a_simd_mulreg" iclass="simd3reg_diff">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td colspan="2">!= 11</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simd3reg_diff">Advanced SIMD three registers of different lengths</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="a_simd_mulreg" iclass="simd2reg_scalar">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td colspan="2">!= 11</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simd2reg_scalar">Advanced SIMD two registers and a scalar</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="a_simd_mulreg" iclass="simd3reg_ext">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td>0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simd3reg_ext">Advanced SIMD vector extract</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="a_simd_mulreg" iclass="simd2reg_misc">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simd2reg_misc">Advanced SIMD two registers misc</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="a_simd_mulreg" iclass="simd3reg_tbl">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simd3reg_tbl">Advanced SIMD table permute</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="a_simd_mulreg" iclass="simd2reg_dup">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td>1</td>
        <td ingroup="1">1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td ingroup="1">0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simd2reg_dup">Advanced SIMD duplicate (scalar)</a>
        </td>
      </tr>
      <maintablesect sect="Advanced SIMD shifts and immediate generation" linkref="a_simd_12reg" />
      <tr class="maintable" size="32" groupid="a_simd_12reg" iclass="simd1reg_imm">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simd1reg_imm">Advanced SIMD one register and modified immediate</a>
        </td>
      </tr>
      <tr class="maintable" size="32" groupid="a_simd_12reg" iclass="simd2reg_shift">
        <td class="boxleft" ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">1</td>
        <td ingroup="1">0</td>
        <td ingroup="1">0</td>
        <td ingroup="1">1</td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td colspan="15">!= 000xxxxxxxxxxx0</td>
        <td></td>
        <td></td>
        <td ingroup="1">1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simd2reg_shift">Advanced SIMD two registers and shift amount</a>
        </td>
      </tr>
    </tablebody>
  </maintable>
  <funcgroupheader id="dpregrs">Data-processing register (register shift)</funcgroupheader>
  <iclass_sect id="intdp3reg_regsh" title="Integer Data Processing (three register, register shift)">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="4" settings="4">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="23" width="3" name="opc" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="20" name="S" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="Rs" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" settings="1">
        <c>0</c>
      </box>
      <box hibit="6" width="2" name="stype" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="4" settings="1">
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="intdp3reg_regsh" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="39*" />
      <col colno="3" printwidth="14*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">opc</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="ANDS_rr_A1" iformfile="and_rr.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td class="iformname" iformid="AND_rr">AND, ANDS (register-shifted register)</td>
          <td class="enctags">Flag setting</td>
        </tr>
        <tr class="instructiontable" encname="EORS_rr_A1" iformfile="eor_rr.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td class="iformname" iformid="EOR_rr">EOR, EORS (register-shifted register)</td>
          <td class="enctags">Flag setting</td>
        </tr>
        <tr class="instructiontable" encname="SUBS_rr_A1" iformfile="sub_rr.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td class="iformname" iformid="SUB_rr">SUB, SUBS (register-shifted register)</td>
          <td class="enctags">Flag setting</td>
        </tr>
        <tr class="instructiontable" encname="RSBS_rr_A1" iformfile="rsb_rr.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td class="iformname" iformid="RSB_rr">RSB, RSBS (register-shifted register)</td>
          <td class="enctags">Flag setting</td>
        </tr>
        <tr class="instructiontable" encname="ADDS_rr_A1" iformfile="add_rr.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td class="iformname" iformid="ADD_rr">ADD, ADDS (register-shifted register)</td>
          <td class="enctags">Flag setting</td>
        </tr>
        <tr class="instructiontable" encname="ADCS_rr_A1" iformfile="adc_rr.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td class="iformname" iformid="ADC_rr">ADC, ADCS (register-shifted register)</td>
          <td class="enctags">Flag setting</td>
        </tr>
        <tr class="instructiontable" encname="SBCS_rr_A1" iformfile="sbc_rr.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td class="iformname" iformid="SBC_rr">SBC, SBCS (register-shifted register)</td>
          <td class="enctags">Flag setting</td>
        </tr>
        <tr class="instructiontable" encname="RSCS_rr_A1" iformfile="rsc_rr.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">111</td>
          <td class="iformname" iformid="RSC_rr">RSC, RSCS (register-shifted register)</td>
          <td class="enctags">Flag setting</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="intdp2reg_regsh" title="Integer Test and Compare (two register, register shift)">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="22" width="2" name="opc" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" settings="1">
        <c>1</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="14" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="13" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="12" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="11" width="4" name="Rs" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" settings="1">
        <c>0</c>
      </box>
      <box hibit="6" width="2" name="stype" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="4" settings="1">
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="intdp2reg_regsh" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="33*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">opc</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="TST_rr_A1" iformfile="tst_rr.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="TST_rr">TST (register-shifted register)</td>
        </tr>
        <tr class="instructiontable" encname="TEQ_rr_A1" iformfile="teq_rr.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="TEQ_rr">TEQ (register-shifted register)</td>
        </tr>
        <tr class="instructiontable" encname="CMP_rr_A1" iformfile="cmp_rr.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="CMP_rr">CMP (register-shifted register)</td>
        </tr>
        <tr class="instructiontable" encname="CMN_rr_A1" iformfile="cmn_rr.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="CMN_rr">CMN (register-shifted register)</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="logic3reg_regsh" title="Logical Arithmetic (three register, register shift)">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="22" width="2" name="opc" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" name="S" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="Rs" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" settings="1">
        <c>0</c>
      </box>
      <box hibit="6" width="2" name="stype" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="4" settings="1">
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="logic3reg_regsh" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="39*" />
      <col colno="3" printwidth="18*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">opc</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="ORRS_rr_A1" iformfile="orr_rr.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="ORR_rr">ORR, ORRS (register-shifted register)</td>
          <td class="enctags">Flag setting</td>
        </tr>
        <tr class="instructiontable" encname="MOVS_rr_A1" iformfile="mov_rr.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="MOV_rr">MOV, MOVS (register-shifted register)</td>
          <td class="enctags">A1, Flag setting</td>
        </tr>
        <tr class="instructiontable" encname="BICS_rr_A1" iformfile="bic_rr.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="BIC_rr">BIC, BICS (register-shifted register)</td>
          <td class="enctags">Flag setting</td>
        </tr>
        <tr class="instructiontable" encname="MVNS_rr_A1" iformfile="mvn_rr.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="MVN_rr">MVN, MVNS (register-shifted register)</td>
          <td class="enctags">Flag setting</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="dpregis">Data-processing register (immediate shift)</funcgroupheader>
  <iclass_sect id="intdp3reg_immsh" title="Integer Data Processing (three register, immediate shift)">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="4" settings="4">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="23" width="3" name="opc" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="20" name="S" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="5" name="imm5" usename="1">
        <c colspan="5"></c>
      </box>
      <box hibit="6" width="2" name="stype" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="intdp3reg_immsh" cols="6">
      <col colno="1" printwidth="5*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="9*" />
      <col colno="4" printwidth="12*" />
      <col colno="5" printwidth="31*" />
      <col colno="6" printwidth="36*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">opc</th>
          <th class="bitfields">S</th>
          <th class="bitfields">Rn</th>
          <th class="bitfields">imm5:stype</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="ANDS_r_A1" iformfile="and_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="AND_r">AND, ANDS (register)</td>
          <td class="enctags">A1, ANDS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="ANDS_r_A1_RRX" iformfile="and_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="AND_r">AND, ANDS (register)</td>
          <td class="enctags">A1, ANDS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="EORS_r_A1" iformfile="eor_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="EOR_r">EOR, EORS (register)</td>
          <td class="enctags">A1, EORS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="EORS_r_A1_RRX" iformfile="eor_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="EOR_r">EOR, EORS (register)</td>
          <td class="enctags">A1, EORS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="SUB_r_A1" iformfile="sub_r.xml" label="SUB, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="SUB_r">SUB, SUBS (register)</td>
          <td class="enctags">A1, SUB, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="SUB_r_A1_RRX" iformfile="sub_r.xml" label="SUB, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="SUB_r">SUB, SUBS (register)</td>
          <td class="enctags">A1, SUB, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="SUB_SP_r_A1" iformfile="sub_sp_r.xml" label="SUB, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="SUB_SP_r">SUB, SUBS (SP minus register)</td>
          <td class="enctags">A1, SUB, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="SUB_SP_r_A1_RRX" iformfile="sub_sp_r.xml" label="SUB, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="SUB_SP_r">SUB, SUBS (SP minus register)</td>
          <td class="enctags">A1, SUB, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="SUBS_r_A1" iformfile="sub_r.xml" label="SUBS, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="SUB_r">SUB, SUBS (register)</td>
          <td class="enctags">A1, SUBS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="SUBS_r_A1_RRX" iformfile="sub_r.xml" label="SUBS, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="SUB_r">SUB, SUBS (register)</td>
          <td class="enctags">A1, SUBS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="SUBS_SP_r_A1" iformfile="sub_sp_r.xml" label="SUBS, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="SUB_SP_r">SUB, SUBS (SP minus register)</td>
          <td class="enctags">A1, SUBS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="SUBS_SP_r_A1_RRX" iformfile="sub_sp_r.xml" label="SUBS, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="SUB_SP_r">SUB, SUBS (SP minus register)</td>
          <td class="enctags">A1, SUBS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="RSBS_r_A1" iformfile="rsb_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="RSB_r">RSB, RSBS (register)</td>
          <td class="enctags">A1, RSBS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="RSBS_r_A1_RRX" iformfile="rsb_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="RSB_r">RSB, RSBS (register)</td>
          <td class="enctags">A1, RSBS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="ADD_r_A1" iformfile="add_r.xml" label="ADD, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="ADD_r">ADD, ADDS (register)</td>
          <td class="enctags">A1, ADD, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="ADD_r_A1_RRX" iformfile="add_r.xml" label="ADD, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="ADD_r">ADD, ADDS (register)</td>
          <td class="enctags">A1, ADD, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="ADD_SP_r_A1" iformfile="add_sp_r.xml" label="ADD, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="ADD_SP_r">ADD, ADDS (SP plus register)</td>
          <td class="enctags">A1, ADD, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="ADD_SP_r_A1_RRX" iformfile="add_sp_r.xml" label="ADD, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="ADD_SP_r">ADD, ADDS (SP plus register)</td>
          <td class="enctags">A1, ADD, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="ADDS_r_A1" iformfile="add_r.xml" label="ADDS, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="ADD_r">ADD, ADDS (register)</td>
          <td class="enctags">A1, ADDS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="ADDS_r_A1_RRX" iformfile="add_r.xml" label="ADDS, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="ADD_r">ADD, ADDS (register)</td>
          <td class="enctags">A1, ADDS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="ADDS_SP_r_A1" iformfile="add_sp_r.xml" label="ADDS, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="ADD_SP_r">ADD, ADDS (SP plus register)</td>
          <td class="enctags">A1, ADDS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="ADDS_SP_r_A1_RRX" iformfile="add_sp_r.xml" label="ADDS, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="ADD_SP_r">ADD, ADDS (SP plus register)</td>
          <td class="enctags">A1, ADDS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="ADCS_r_A1" iformfile="adc_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="ADC_r">ADC, ADCS (register)</td>
          <td class="enctags">A1, ADCS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="ADCS_r_A1_RRX" iformfile="adc_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="ADC_r">ADC, ADCS (register)</td>
          <td class="enctags">A1, ADCS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="SBCS_r_A1" iformfile="sbc_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="SBC_r">SBC, SBCS (register)</td>
          <td class="enctags">A1, SBCS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="SBCS_r_A1_RRX" iformfile="sbc_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="SBC_r">SBC, SBCS (register)</td>
          <td class="enctags">A1, SBCS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="RSCS_r_A1" iformfile="rsc_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="RSC_r">RSC, RSCS (register)</td>
          <td class="enctags">RSCS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="RSCS_r_A1_RRX" iformfile="rsc_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="RSC_r">RSC, RSCS (register)</td>
          <td class="enctags">RSCS, rotate right with extend</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="intdp2reg_immsh" title="Integer Test and Compare (two register, immediate shift)">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="22" width="2" name="opc" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" settings="1">
        <c>1</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="14" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="13" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="12" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="11" width="5" name="imm5" usename="1">
        <c colspan="5"></c>
      </box>
      <box hibit="6" width="2" name="stype" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="intdp2reg_immsh" cols="4">
      <col colno="1" printwidth="5*" />
      <col colno="2" printwidth="12*" />
      <col colno="3" printwidth="18*" />
      <col colno="4" printwidth="30*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">opc</th>
          <th class="bitfields">imm5:stype</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="TST_r_A1" iformfile="tst_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="TST_r">TST (register)</td>
          <td class="enctags">A1, Shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="TST_r_A1_RRX" iformfile="tst_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="TST_r">TST (register)</td>
          <td class="enctags">A1, Rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="TEQ_r_A1" iformfile="teq_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="TEQ_r">TEQ (register)</td>
          <td class="enctags">A1, Shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="TEQ_r_A1_RRX" iformfile="teq_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="TEQ_r">TEQ (register)</td>
          <td class="enctags">A1, Rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="CMP_r_A1" iformfile="cmp_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="CMP_r">CMP (register)</td>
          <td class="enctags">A1, Shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="CMP_r_A1_RRX" iformfile="cmp_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="CMP_r">CMP (register)</td>
          <td class="enctags">A1, Rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="CMN_r_A1" iformfile="cmn_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="CMN_r">CMN (register)</td>
          <td class="enctags">A1, Shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="CMN_r_A1_RRX" iformfile="cmn_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="CMN_r">CMN (register)</td>
          <td class="enctags">A1, Rotate right with extend</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="logic3reg_immsh" title="Logical Arithmetic (three register, immediate shift)">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="22" width="2" name="opc" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" name="S" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="5" name="imm5" usename="1">
        <c colspan="5"></c>
      </box>
      <box hibit="6" width="2" name="stype" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="logic3reg_immsh" cols="4">
      <col colno="1" printwidth="5*" />
      <col colno="2" printwidth="12*" />
      <col colno="3" printwidth="22*" />
      <col colno="4" printwidth="36*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">opc</th>
          <th class="bitfields">imm5:stype</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="ORRS_r_A1" iformfile="orr_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="ORR_r">ORR, ORRS (register)</td>
          <td class="enctags">A1, ORRS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="ORRS_r_A1_RRX" iformfile="orr_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="ORR_r">ORR, ORRS (register)</td>
          <td class="enctags">A1, ORRS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="MOVS_r_A1" iformfile="mov_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="MOV_r">MOV, MOVS (register)</td>
          <td class="enctags">A1, MOVS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="MOVS_r_A1_RRX" iformfile="mov_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="MOV_r">MOV, MOVS (register)</td>
          <td class="enctags">A1, MOVS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="BICS_r_A1" iformfile="bic_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="BIC_r">BIC, BICS (register)</td>
          <td class="enctags">A1, BICS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="BICS_r_A1_RRX" iformfile="bic_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="BIC_r">BIC, BICS (register)</td>
          <td class="enctags">A1, BICS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="MVNS_r_A1" iformfile="mvn_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="MVN_r">MVN, MVNS (register)</td>
          <td class="enctags">A1, MVNS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="MVNS_r_A1_RRX" iformfile="mvn_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="MVN_r">MVN, MVNS (register)</td>
          <td class="enctags">A1, MVNS, rotate right with extend</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="dpmisc">Miscellaneous</funcgroupheader>
  <iclass_sect id="bx_reg" title="Branch and Exchange (register)">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="8" settings="8">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="19" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="18" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="17" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="16" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="15" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="14" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="13" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="12" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="11" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="10" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="9" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="8" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="7" width="4" settings="4">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="bx_reg" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="BX_A1" iformfile="bx.xml" first="t" last="t">
          <td class="iformname" iformid="BX">BX</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="bxj_reg" title="Branch and Exchange to Jazelle (register)">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="8" settings="8">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="19" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="18" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="17" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="16" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="15" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="14" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="13" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="12" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="11" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="10" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="9" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="8" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="7" width="4" settings="4">
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="bxj_reg" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="BXJ_A1" iformfile="bxj.xml" first="t" last="t">
          <td class="iformname" iformid="BXJ">BXJ</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="blx_reg" title="Branch with Link and Exchange (register)">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="8" settings="8">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="19" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="18" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="17" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="16" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="15" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="14" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="13" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="12" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="11" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="10" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="9" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="8" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="7" width="4" settings="4">
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="blx_reg" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="BLX_r_A1" iformfile="blx_r.xml" first="t" last="t">
          <td class="iformname" iformid="BLX_r">BLX (register)</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="clz" title="Count Leading Zeros">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="8" settings="8">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="19" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="18" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="17" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="16" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="15" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="10" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="9" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="8" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="7" width="4" settings="4">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="clz" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="CLZ_A1" iformfile="clz.xml" first="t" last="t">
          <td class="iformname" iformid="CLZ">CLZ</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="crc32" title="Cyclic Redundancy Check">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="22" width="2" name="sz" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" settings="1">
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="10" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="9" name="C" usename="1">
        <c></c>
      </box>
      <box hibit="8" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="7" width="4" settings="4">
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="crc32" cols="4">
      <col colno="1" printwidth="4*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="18*" />
      <col colno="4" printwidth="13*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">sz</th>
          <th class="bitfields">C</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="CRC32B_A1" arch_version="FEAT_CRC32" iformfile="crc32.xml" label="CRC32B" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="CRC32">CRC32</td>
          <td class="enctags">A1, CRC32B</td>
        </tr>
        <tr class="instructiontable" encname="CRC32CB_A1" arch_version="FEAT_CRC32" iformfile="crc32c.xml" label="CRC32CB" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="CRC32C">CRC32C</td>
          <td class="enctags">A1, CRC32CB</td>
        </tr>
        <tr class="instructiontable" encname="CRC32H_A1" arch_version="FEAT_CRC32" iformfile="crc32.xml" label="CRC32H" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="CRC32">CRC32</td>
          <td class="enctags">A1, CRC32H</td>
        </tr>
        <tr class="instructiontable" encname="CRC32CH_A1" arch_version="FEAT_CRC32" iformfile="crc32c.xml" label="CRC32CH" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="CRC32C">CRC32C</td>
          <td class="enctags">A1, CRC32CH</td>
        </tr>
        <tr class="instructiontable" encname="CRC32W_A1" arch_version="FEAT_CRC32" iformfile="crc32.xml" label="CRC32W" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="CRC32">CRC32</td>
          <td class="enctags">A1, CRC32W</td>
        </tr>
        <tr class="instructiontable" encname="CRC32CW_A1" arch_version="FEAT_CRC32" iformfile="crc32c.xml" label="CRC32CW" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="CRC32C">CRC32C</td>
          <td class="enctags">A1, CRC32CW</td>
        </tr>
        <tr class="instructiontable" encname="UNPREDICTABLE_17_crc32" unpred="1" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNPREDICTABLE</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="except" title="Exception Generation">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="22" width="2" name="opc" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" settings="1">
        <c>0</c>
      </box>
      <box hibit="19" width="12" name="imm12" usename="1">
        <c colspan="12"></c>
      </box>
      <box hibit="7" width="4" settings="4">
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="imm4" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="except" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">opc</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="HLT_A1" iformfile="hlt.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="HLT">HLT</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="BKPT_A1" iformfile="bkpt.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="BKPT">BKPT</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="HVC_A1" iformfile="hvc.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="HVC">HVC</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="SMC_A1_AS" iformfile="smc.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="SMC">SMC</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="eret" title="Exception Return">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="8" settings="8">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="19" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="18" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="17" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="16" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="15" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="14" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="13" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="12" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="11" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="10" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="9" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="8" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="7" width="4" settings="4">
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="3" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="2" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="1" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="0" settings="1">
        <c>(0)</c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="eret" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="ERET_A1" iformfile="eret.xml" first="t" last="t">
          <td class="iformname" iformid="ERET">ERET</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="intsat" title="Integer Saturating Arithmetic">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="22" width="2" name="opc" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" settings="1">
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="10" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="9" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="8" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="7" width="4" settings="4">
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="intsat" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">opc</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="QADD_A1" iformfile="qadd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="QADD">QADD</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="QSUB_A1" iformfile="qsub.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="QSUB">QSUB</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="QDADD_A1" iformfile="qdadd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="QDADD">QDADD</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="QDSUB_A1" iformfile="qdsub.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="QDSUB">QDSUB</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="movsr_reg" title="Move special register (register)">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="22" width="2" name="opc" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" settings="1">
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="mask" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="10" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="9" name="B" usename="1">
        <c></c>
      </box>
      <box hibit="8" name="m" usename="1">
        <c></c>
      </box>
      <box hibit="7" width="4" settings="4">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="movsr_reg" cols="4">
      <col colno="1" printwidth="5*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="23*" />
      <col colno="4" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">opc</th>
          <th class="bitfields">B</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="MRS_A1_AS" iformfile="mrs.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">x0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="MRS">MRS</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="MRS_br_A1_AS" iformfile="mrs_br.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">x0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="MRS_br">MRS (Banked register)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="MSR_r_A1_AS" iformfile="msr_r.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">x1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="MSR_r">MSR (register)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="MSR_br_A1_AS" iformfile="msr_br.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">x1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="MSR_br">MSR (Banked register)</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="dphwm">Halfword multiply and multiply accumulate</funcgroupheader>
  <iclass_sect id="mul_half" title="Halfword Multiply and Accumulate">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="22" width="2" name="opc" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" settings="1">
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Ra" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" settings="1">
        <c>1</c>
      </box>
      <box hibit="6" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="mul_half" cols="5">
      <col colno="1" printwidth="5*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="3*" />
      <col colno="4" printwidth="36*" />
      <col colno="5" printwidth="13*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">opc</th>
          <th class="bitfields">M</th>
          <th class="bitfields">N</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="SMLATT_A1" iformfile="smlabb.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="SMLABB">SMLABB, SMLABT, SMLATB, SMLATT</td>
          <td class="enctags">A1, SMLATT</td>
        </tr>
        <tr class="instructiontable" encname="SMLAWB_A1" iformfile="smlawb.xml" label="SMLAWB" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SMLAWB">SMLAWB, SMLAWT</td>
          <td class="enctags">A1, SMLAWB</td>
        </tr>
        <tr class="instructiontable" encname="SMULWB_A1" iformfile="smulwb.xml" label="SMULWB" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="SMULWB">SMULWB, SMULWT</td>
          <td class="enctags">A1, SMULWB</td>
        </tr>
        <tr class="instructiontable" encname="SMLAWT_A1" iformfile="smlawb.xml" label="SMLAWT" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SMLAWB">SMLAWB, SMLAWT</td>
          <td class="enctags">A1, SMLAWT</td>
        </tr>
        <tr class="instructiontable" encname="SMULWT_A1" iformfile="smulwb.xml" label="SMULWT" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="SMULWB">SMULWB, SMULWT</td>
          <td class="enctags">A1, SMULWT</td>
        </tr>
        <tr class="instructiontable" encname="SMLALTT_A1" iformfile="smlalbb.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="SMLALBB">SMLALBB, SMLALBT, SMLALTB, SMLALTT</td>
          <td class="enctags">A1, SMLALTT</td>
        </tr>
        <tr class="instructiontable" encname="SMULTT_A1" iformfile="smulbb.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="SMULBB">SMULBB, SMULBT, SMULTB, SMULTT</td>
          <td class="enctags">A1, SMULTT</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="dpmul">Multiply and multiply accumulate</funcgroupheader>
  <iclass_sect id="mul_word" title="Multiply and Accumulate">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="4" settings="4">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="23" width="3" name="opc" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="20" name="S" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="RdHi" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="RdLo" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" width="4" settings="4">
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="mul_word" cols="4">
      <col colno="1" printwidth="5*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="18*" />
      <col colno="4" printwidth="18*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">opc</th>
          <th class="bitfields">S</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="MULS_A1" iformfile="mul.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="MUL">MUL, MULS</td>
          <td class="enctags">A1, Flag setting</td>
        </tr>
        <tr class="instructiontable" encname="MLAS_A1" iformfile="mla.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="MLA">MLA, MLAS</td>
          <td class="enctags">A1, Flag setting</td>
        </tr>
        <tr class="instructiontable" encname="UMAAL_A1" iformfile="umaal.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="UMAAL">UMAAL</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_16_mul_word" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="MLS_A1" iformfile="mls.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="MLS">MLS</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_18_mul_word" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UMULLS_A1" iformfile="umull.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="UMULL">UMULL, UMULLS</td>
          <td class="enctags">A1, Flag setting</td>
        </tr>
        <tr class="instructiontable" encname="UMLALS_A1" iformfile="umlal.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="UMLAL">UMLAL, UMLALS</td>
          <td class="enctags">A1, Flag setting</td>
        </tr>
        <tr class="instructiontable" encname="SMULLS_A1" iformfile="smull.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="SMULL">SMULL, SMULLS</td>
          <td class="enctags">A1, Flag setting</td>
        </tr>
        <tr class="instructiontable" encname="SMLALS_A1" iformfile="smlal.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="SMLAL">SMLAL, SMLALS</td>
          <td class="enctags">A1, Flag setting</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="sync">Synchronization primitives and Load-Acquire/Store-Release</funcgroupheader>
  <iclass_sect id="ldst_excl" title="Load/Store Exclusive and Load-Acquire/Store-Release">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="22" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="xRd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="10" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="9" name="ex" usename="1">
        <c></c>
      </box>
      <box hibit="8" name="ord" usename="1">
        <c></c>
      </box>
      <box hibit="7" width="4" settings="4">
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="xRt" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="ldst_excl" cols="6">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="4*" />
      <col colno="4" printwidth="5*" />
      <col colno="5" printwidth="18*" />
      <col colno="6" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
          <th class="bitfields">L</th>
          <th class="bitfields">ex</th>
          <th class="bitfields">ord</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="STL_A1" iformfile="stl.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STL">STL</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_12_ldst_excl" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="STLEX_A1" iformfile="stlex.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STLEX">STLEX</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="STREX_A1" iformfile="strex.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="STREX">STREX</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="LDA_A1" iformfile="lda.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="LDA">LDA</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_16_ldst_excl" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="LDAEX_A1" iformfile="ldaex.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="LDAEX">LDAEX</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="LDREX_A1" iformfile="ldrex.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDREX">LDREX</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_19_ldst_excl" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="STLEXD_A1" iformfile="stlexd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STLEXD">STLEXD</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="STREXD_A1" iformfile="strexd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="STREXD">STREXD</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_22_ldst_excl" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="LDAEXD_A1" iformfile="ldaexd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="LDAEXD">LDAEXD</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="LDREXD_A1" iformfile="ldrexd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDREXD">LDREXD</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="STLB_A1" iformfile="stlb.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STLB">STLB</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_26_ldst_excl" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="STLEXB_A1" iformfile="stlexb.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STLEXB">STLEXB</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="STREXB_A1" iformfile="strexb.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="STREXB">STREXB</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="LDAB_A1" iformfile="ldab.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="LDAB">LDAB</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_30_ldst_excl" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="LDAEXB_A1" iformfile="ldaexb.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="LDAEXB">LDAEXB</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="LDREXB_A1" iformfile="ldrexb.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDREXB">LDREXB</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="STLH_A1" iformfile="stlh.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STLH">STLH</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_34_ldst_excl" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="STLEXH_A1" iformfile="stlexh.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STLEXH">STLEXH</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="STREXH_A1" iformfile="strexh.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="STREXH">STREXH</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="LDAH_A1" iformfile="ldah.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="LDAH">LDAH</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_38_ldst_excl" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="LDAEXH_A1" iformfile="ldaexh.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="LDAEXH">LDAEXH</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="LDREXH_A1" iformfile="ldrexh.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDREXH">LDREXH</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="xldst">Extra load/store</funcgroupheader>
  <iclass_sect id="ldstximm" title="Load/Store Dual, Half, Signed Byte (immediate, literal)">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="3" settings="3">
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="24" name="P" usename="1">
        <c></c>
      </box>
      <box hibit="23" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="22" settings="1">
        <c>1</c>
      </box>
      <box hibit="21" name="W" usename="1">
        <c></c>
      </box>
      <box hibit="20" name="o1" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="imm4H" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" settings="1">
        <c>1</c>
      </box>
      <box hibit="6" width="2" name="op2" usename="1" settings="2" constraint="!= 00">
        <c colspan="2">!= 00</c>
      </box>
      <box hibit="4" settings="1">
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="imm4L" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="op2" op="!=" val="00" />
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="op2" op="!=" val="00" />
    </decode_constraints>
    <instructiontable iclass="ldstximm" cols="6">
      <col colno="1" printwidth="7*" />
      <col colno="2" printwidth="4*" />
      <col colno="3" printwidth="9*" />
      <col colno="4" printwidth="5*" />
      <col colno="5" printwidth="19*" />
      <col colno="6" printwidth="18*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">P:W</th>
          <th class="bitfields">o1</th>
          <th class="bitfields">Rn</th>
          <th class="bitfields">op2</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="LDRD_l_A1" iformfile="ldrd_l.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="LDRD_l">LDRD (literal)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="LDRH_l_A1" iformfile="ldrh_l.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">!= 01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="LDRH_l">LDRH (literal)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="LDRSB_l_A1" iformfile="ldrsb_l.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">!= 01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="LDRSB_l">LDRSB (literal)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="LDRSH_l_A1" iformfile="ldrsh_l.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">!= 01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="LDRSH_l">LDRSH (literal)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="LDRD_i_A1_post" iformfile="ldrd_i.xml" label="post-indexed" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="LDRD_i">LDRD (immediate)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="STRH_i_A1_post" iformfile="strh_i.xml" label="post-indexed" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="STRH_i">STRH (immediate)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="STRD_i_A1_post" iformfile="strd_i.xml" label="post-indexed" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="STRD_i">STRD (immediate)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRH_i_A1_post" iformfile="ldrh_i.xml" label="post-indexed" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="LDRH_i">LDRH (immediate)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRSB_i_A1_post" iformfile="ldrsb_i.xml" label="post-indexed" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="LDRSB_i">LDRSB (immediate)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRSH_i_A1_post" iformfile="ldrsh_i.xml" label="post-indexed" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="LDRSH_i">LDRSH (immediate)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_16_ldstximm" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="STRHT_A1" iformfile="strht.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="STRHT">STRHT</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_21_ldstximm" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="LDRHT_A1" iformfile="ldrht.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="LDRHT">LDRHT</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="LDRSBT_A1" iformfile="ldrsbt.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="LDRSBT">LDRSBT</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="LDRSHT_A1" iformfile="ldrsht.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="LDRSHT">LDRSHT</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="LDRD_i_A1_off" iformfile="ldrd_i.xml" label="offset" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="LDRD_i">LDRD (immediate)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="STRH_i_A1_off" iformfile="strh_i.xml" label="offset" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="STRH_i">STRH (immediate)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="STRD_i_A1_off" iformfile="strd_i.xml" label="offset" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="STRD_i">STRD (immediate)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="LDRH_i_A1_off" iformfile="ldrh_i.xml" label="offset" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="LDRH_i">LDRH (immediate)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="LDRSB_i_A1_off" iformfile="ldrsb_i.xml" label="offset" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="LDRSB_i">LDRSB (immediate)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="LDRSH_i_A1_off" iformfile="ldrsh_i.xml" label="offset" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="LDRSH_i">LDRSH (immediate)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="LDRD_i_A1_pre" iformfile="ldrd_i.xml" label="pre-indexed" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="LDRD_i">LDRD (immediate)</td>
          <td class="enctags">A1, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="STRH_i_A1_pre" iformfile="strh_i.xml" label="pre-indexed" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="STRH_i">STRH (immediate)</td>
          <td class="enctags">A1, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="STRD_i_A1_pre" iformfile="strd_i.xml" label="pre-indexed" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="STRD_i">STRD (immediate)</td>
          <td class="enctags">A1, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRH_i_A1_pre" iformfile="ldrh_i.xml" label="pre-indexed" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="LDRH_i">LDRH (immediate)</td>
          <td class="enctags">A1, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRSB_i_A1_pre" iformfile="ldrsb_i.xml" label="pre-indexed" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="LDRSB_i">LDRSB (immediate)</td>
          <td class="enctags">A1, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRSH_i_A1_pre" iformfile="ldrsh_i.xml" label="pre-indexed" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="LDRSH_i">LDRSH (immediate)</td>
          <td class="enctags">A1, Pre-indexed</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldstxreg" title="Load/Store Dual, Half, Signed Byte (register)">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="3" settings="3">
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="24" name="P" usename="1">
        <c></c>
      </box>
      <box hibit="23" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="22" settings="1">
        <c>0</c>
      </box>
      <box hibit="21" name="W" usename="1">
        <c></c>
      </box>
      <box hibit="20" name="o1" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="10" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="9" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="8" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="7" settings="1">
        <c>1</c>
      </box>
      <box hibit="6" width="2" name="op2" usename="1" settings="2" constraint="!= 00">
        <c colspan="2">!= 00</c>
      </box>
      <box hibit="4" settings="1">
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="op2" op="!=" val="00" />
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="op2" op="!=" val="00" />
    </decode_constraints>
    <instructiontable iclass="ldstxreg" cols="6">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="4*" />
      <col colno="4" printwidth="5*" />
      <col colno="5" printwidth="18*" />
      <col colno="6" printwidth="18*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">P</th>
          <th class="bitfields">W</th>
          <th class="bitfields">o1</th>
          <th class="bitfields">op2</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="STRH_r_A1_post" iformfile="strh_r.xml" label="post-indexed" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="STRH_r">STRH (register)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRD_r_A1_post" iformfile="ldrd_r.xml" label="post-indexed" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="LDRD_r">LDRD (register)</td>
          <td class="enctags">Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="STRD_r_A1_post" iformfile="strd_r.xml" label="post-indexed" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="STRD_r">STRD (register)</td>
          <td class="enctags">Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRH_r_A1_post" iformfile="ldrh_r.xml" label="post-indexed" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="LDRH_r">LDRH (register)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRSB_r_A1_post" iformfile="ldrsb_r.xml" label="post-indexed" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="LDRSB_r">LDRSB (register)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRSH_r_A1_post" iformfile="ldrsh_r.xml" label="post-indexed" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="LDRSH_r">LDRSH (register)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="STRHT_A2" iformfile="strht.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="STRHT">STRHT</td>
          <td class="enctags">A2</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_16_ldstxreg" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_20_ldstxreg" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="LDRHT_A2" iformfile="ldrht.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="LDRHT">LDRHT</td>
          <td class="enctags">A2</td>
        </tr>
        <tr class="instructiontable" encname="LDRSBT_A2" iformfile="ldrsbt.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="LDRSBT">LDRSBT</td>
          <td class="enctags">A2</td>
        </tr>
        <tr class="instructiontable" encname="LDRSHT_A2" iformfile="ldrsht.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="LDRSHT">LDRSHT</td>
          <td class="enctags">A2</td>
        </tr>
        <tr class="instructiontable" encname="STRH_r_A1_pre" iformfile="strh_r.xml" label="pre-indexed" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="STRH_r">STRH (register)</td>
          <td class="enctags">A1, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRD_r_A1_pre" iformfile="ldrd_r.xml" label="pre-indexed" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="LDRD_r">LDRD (register)</td>
          <td class="enctags">Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="STRD_r_A1_pre" iformfile="strd_r.xml" label="pre-indexed" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="STRD_r">STRD (register)</td>
          <td class="enctags">Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRH_r_A1_pre" iformfile="ldrh_r.xml" label="pre-indexed" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="LDRH_r">LDRH (register)</td>
          <td class="enctags">A1, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRSB_r_A1_pre" iformfile="ldrsb_r.xml" label="pre-indexed" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="LDRSB_r">LDRSB (register)</td>
          <td class="enctags">A1, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRSH_r_A1_pre" iformfile="ldrsh_r.xml" label="pre-indexed" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="LDRSH_r">LDRSH (register)</td>
          <td class="enctags">A1, Pre-indexed</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="dpimm">Data-processing immediate</funcgroupheader>
  <iclass_sect id="intdp2reg_imm" title="Integer Data Processing (two register and immediate)">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="4" settings="4">
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="23" width="3" name="opc" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="20" name="S" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="12" name="imm12" usename="1">
        <c colspan="12"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="intdp2reg_imm" cols="5">
      <col colno="1" printwidth="5*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="9*" />
      <col colno="4" printwidth="32*" />
      <col colno="5" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">opc</th>
          <th class="bitfields">S</th>
          <th class="bitfields">Rn</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="ANDS_i_A1" iformfile="and_i.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="AND_i">AND, ANDS (immediate)</td>
          <td class="enctags">A1, ANDS</td>
        </tr>
        <tr class="instructiontable" encname="EORS_i_A1" iformfile="eor_i.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="EOR_i">EOR, EORS (immediate)</td>
          <td class="enctags">A1, EORS</td>
        </tr>
        <tr class="instructiontable" encname="SUB_i_A1" iformfile="sub_i.xml" label="SUB" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="SUB_i">SUB, SUBS (immediate)</td>
          <td class="enctags">A1, SUB</td>
        </tr>
        <tr class="instructiontable" encname="SUB_SP_i_A1" iformfile="sub_sp_i.xml" label="SUB" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="SUB_SP_i">SUB, SUBS (SP minus immediate)</td>
          <td class="enctags">A1, SUB</td>
        </tr>
        <tr class="instructiontable" encoding="a2" iformfile="adr.xml" label="A2" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="ADR">ADR</td>
          <td class="enctags">A2</td>
        </tr>
        <tr class="instructiontable" encname="SUBS_i_A1" iformfile="sub_i.xml" label="SUBS" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td class="iformname" iformid="SUB_i">SUB, SUBS (immediate)</td>
          <td class="enctags">A1, SUBS</td>
        </tr>
        <tr class="instructiontable" encname="SUBS_SP_i_A1" iformfile="sub_sp_i.xml" label="SUBS" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="SUB_SP_i">SUB, SUBS (SP minus immediate)</td>
          <td class="enctags">A1, SUBS</td>
        </tr>
        <tr class="instructiontable" encname="RSBS_i_A1" iformfile="rsb_i.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="RSB_i">RSB, RSBS (immediate)</td>
          <td class="enctags">A1, RSBS</td>
        </tr>
        <tr class="instructiontable" encname="ADD_i_A1" iformfile="add_i.xml" label="ADD" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="ADD_i">ADD, ADDS (immediate)</td>
          <td class="enctags">A1, ADD</td>
        </tr>
        <tr class="instructiontable" encname="ADD_SP_i_A1" iformfile="add_sp_i.xml" label="ADD" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="ADD_SP_i">ADD, ADDS (SP plus immediate)</td>
          <td class="enctags">A1, ADD</td>
        </tr>
        <tr class="instructiontable" encoding="a1" iformfile="adr.xml" label="A1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="ADR">ADR</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="ADDS_i_A1" iformfile="add_i.xml" label="ADDS" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td class="iformname" iformid="ADD_i">ADD, ADDS (immediate)</td>
          <td class="enctags">A1, ADDS</td>
        </tr>
        <tr class="instructiontable" encname="ADDS_SP_i_A1" iformfile="add_sp_i.xml" label="ADDS" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="ADD_SP_i">ADD, ADDS (SP plus immediate)</td>
          <td class="enctags">A1, ADDS</td>
        </tr>
        <tr class="instructiontable" encname="ADCS_i_A1" iformfile="adc_i.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ADC_i">ADC, ADCS (immediate)</td>
          <td class="enctags">A1, ADCS</td>
        </tr>
        <tr class="instructiontable" encname="SBCS_i_A1" iformfile="sbc_i.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="SBC_i">SBC, SBCS (immediate)</td>
          <td class="enctags">A1, SBCS</td>
        </tr>
        <tr class="instructiontable" encname="RSCS_i_A1" iformfile="rsc_i.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="RSC_i">RSC, RSCS (immediate)</td>
          <td class="enctags">RSCS</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="intdp1reg_imm" title="Integer Test and Compare (one register and immediate)">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="22" width="2" name="opc" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" settings="1">
        <c>1</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="14" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="13" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="12" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="11" width="12" name="imm12" usename="1">
        <c colspan="12"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="intdp1reg_imm" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">opc</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="TST_i_A1" iformfile="tst_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="TST_i">TST (immediate)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="TEQ_i_A1" iformfile="teq_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="TEQ_i">TEQ (immediate)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="CMP_i_A1" iformfile="cmp_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="CMP_i">CMP (immediate)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="CMN_i_A1" iformfile="cmn_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="CMN_i">CMN (immediate)</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="log2reg_imm" title="Logical Arithmetic  (two register and immediate)">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="22" width="2" name="opc" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" name="S" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="12" name="imm12" usename="1">
        <c colspan="12"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="log2reg_imm" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="23*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">opc</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="ORRS_i_A1" iformfile="orr_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="ORR_i">ORR, ORRS (immediate)</td>
          <td class="enctags">A1, ORRS</td>
        </tr>
        <tr class="instructiontable" encname="MOVS_i_A1" iformfile="mov_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="MOV_i">MOV, MOVS (immediate)</td>
          <td class="enctags">A1, MOVS</td>
        </tr>
        <tr class="instructiontable" encname="BICS_i_A1" iformfile="bic_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="BIC_i">BIC, BICS (immediate)</td>
          <td class="enctags">A1, BICS</td>
        </tr>
        <tr class="instructiontable" encname="MVNS_i_A1" iformfile="mvn_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="MVN_i">MVN, MVNS (immediate)</td>
          <td class="enctags">A1, MVNS</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="movw" title="Move Halfword (immediate)">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="22" name="H" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" settings="2">
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="imm4" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="12" name="imm12" usename="1">
        <c colspan="12"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="movw" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="23*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">H</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="MOV_i_A2" iformfile="mov_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="MOV_i">MOV, MOVS (immediate)</td>
          <td class="enctags">A2</td>
        </tr>
        <tr class="instructiontable" encname="MOVT_A1" iformfile="movt.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="MOVT">MOVT</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="movsr_hint_imm" title="Move Special Register and Hints (immediate)">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="22" name="R" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="imm4" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="14" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="13" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="12" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="11" width="12" name="imm12" usename="1">
        <c colspan="12"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="movsr_hint_imm" cols="4">
      <col colno="1" printwidth="10*" />
      <col colno="2" printwidth="14*" />
      <col colno="3" printwidth="31*" />
      <col colno="4" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">R:imm4</th>
          <th class="bitfields">imm12</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="MSR_i_A1_AS" iformfile="msr_i.xml" first="t" last="t">
          <td bitwidth="7" class="bitfield">!= 00000</td>
          <td bitwidth="12" class="bitfield"></td>
          <td class="iformname" iformid="MSR_i">MSR (immediate)</td>
        </tr>
        <tr class="instructiontable" encname="NOP_A1" iformfile="nop.xml" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx00000000</td>
          <td class="iformname" iformid="NOP">NOP</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="YIELD_A1" iformfile="yield.xml" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx00000001</td>
          <td class="iformname" iformid="YIELD">YIELD</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="WFE_A1" iformfile="wfe.xml" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx00000010</td>
          <td class="iformname" iformid="WFE">WFE</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="WFI_A1" iformfile="wfi.xml" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx00000011</td>
          <td class="iformname" iformid="WFI">WFI</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="SEV_A1" iformfile="sev.xml" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx00000100</td>
          <td class="iformname" iformid="SEV">SEV</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="SEVL_A1" iformfile="sevl.xml" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx00000101</td>
          <td class="iformname" iformid="SEVL">SEVL</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_18_movsr_hint_imm" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx0000011x</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_19_movsr_hint_imm" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx00001xxx</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="ESB_A1" arch_version="FEAT_RAS" iformfile="esb.xml" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx00010000</td>
          <td class="iformname" iformid="ESB">ESB</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_21_movsr_hint_imm" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx00010001</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="TSB_A1" arch_version="FEAT_TRF" iformfile="tsb.xml" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx00010010</td>
          <td class="iformname" iformid="TSB">TSB CSYNC</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_23_movsr_hint_imm" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx00010011</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="CSDB_A1" iformfile="csdb.xml" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx00010100</td>
          <td class="iformname" iformid="CSDB">CSDB</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_25_movsr_hint_imm" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx00010101</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="CLRBHB_A1" arch_version="FEAT_CLRBHB" iformfile="clrbhb.xml" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx00010110</td>
          <td class="iformname" iformid="CLRBHB">CLRBHB</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_27_movsr_hint_imm" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx00010111</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_28_movsr_hint_imm" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx00011xxx</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_29_movsr_hint_imm" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx001xxxxx</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_30_movsr_hint_imm" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx01xxxxxx</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_31_movsr_hint_imm" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx10xxxxxx</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_32_movsr_hint_imm" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx110xxxxx</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_33_movsr_hint_imm" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx1110xxxx</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="DBG_A1" iformfile="dbg.xml" first="t" last="t">
          <td bitwidth="7" class="bitfield">00000</td>
          <td bitwidth="12" class="bitfield">xxxx1111xxxx</td>
          <td class="iformname" iformid="DBG">DBG</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="ldstwbi">Load/store word and unsigned byte (immediate)</funcgroupheader>
  <iclass_sect id="ldstimm" title="Load/Store Word, Unsigned Byte (immediate, literal)">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="3" settings="3">
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="24" name="P" usename="1">
        <c></c>
      </box>
      <box hibit="23" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="22" name="o2" usename="1">
        <c></c>
      </box>
      <box hibit="21" name="W" usename="1">
        <c></c>
      </box>
      <box hibit="20" name="o1" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="12" name="imm12" usename="1">
        <c colspan="12"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="ldstimm" cols="6">
      <col colno="1" printwidth="7*" />
      <col colno="2" printwidth="4*" />
      <col colno="3" printwidth="4*" />
      <col colno="4" printwidth="9*" />
      <col colno="5" printwidth="18*" />
      <col colno="6" printwidth="18*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">P:W</th>
          <th class="bitfields">o2</th>
          <th class="bitfields">o1</th>
          <th class="bitfields">Rn</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="LDR_l_A1" iformfile="ldr_l.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">!= 01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="LDR_l">LDR (literal)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="LDRB_l_A1" iformfile="ldrb_l.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">!= 01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="LDRB_l">LDRB (literal)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="STR_i_A1_post" iformfile="str_i.xml" label="post-indexed" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="STR_i">STR (immediate)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDR_i_A1_post" iformfile="ldr_i.xml" label="post-indexed" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="LDR_i">LDR (immediate)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="STRB_i_A1_post" iformfile="strb_i.xml" label="post-indexed" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="STRB_i">STRB (immediate)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRB_i_A1_post" iformfile="ldrb_i.xml" label="post-indexed" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="LDRB_i">LDRB (immediate)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="STRT_A1" iformfile="strt.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="STRT">STRT</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="LDRT_A1" iformfile="ldrt.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="LDRT">LDRT</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="STRBT_A1" iformfile="strbt.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="STRBT">STRBT</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="LDRBT_A1" iformfile="ldrbt.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="LDRBT">LDRBT</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="STR_i_A1_off" iformfile="str_i.xml" label="offset" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="STR_i">STR (immediate)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="LDR_i_A1_off" iformfile="ldr_i.xml" label="offset" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="LDR_i">LDR (immediate)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="STRB_i_A1_off" iformfile="strb_i.xml" label="offset" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="STRB_i">STRB (immediate)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="LDRB_i_A1_off" iformfile="ldrb_i.xml" label="offset" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="LDRB_i">LDRB (immediate)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="STR_i_A1_pre" iformfile="str_i.xml" label="pre-indexed" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="STR_i">STR (immediate)</td>
          <td class="enctags">A1, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDR_i_A1_pre" iformfile="ldr_i.xml" label="pre-indexed" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="LDR_i">LDR (immediate)</td>
          <td class="enctags">A1, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="STRB_i_A1_pre" iformfile="strb_i.xml" label="pre-indexed" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="STRB_i">STRB (immediate)</td>
          <td class="enctags">A1, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRB_i_A1_pre" iformfile="ldrb_i.xml" label="pre-indexed" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="LDRB_i">LDRB (immediate)</td>
          <td class="enctags">A1, Pre-indexed</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="ldstwbr">Load/store word and unsigned byte (register)</funcgroupheader>
  <iclass_sect id="ldstreg" title="Load/Store Word, Unsigned Byte (register)">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="3" settings="3">
        <c>0</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="24" name="P" usename="1">
        <c></c>
      </box>
      <box hibit="23" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="22" name="o2" usename="1">
        <c></c>
      </box>
      <box hibit="21" name="W" usename="1">
        <c></c>
      </box>
      <box hibit="20" name="o1" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="5" name="imm5" usename="1">
        <c colspan="5"></c>
      </box>
      <box hibit="6" width="2" name="stype" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="ldstreg" cols="6">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="4*" />
      <col colno="3" printwidth="3*" />
      <col colno="4" printwidth="4*" />
      <col colno="5" printwidth="18*" />
      <col colno="6" printwidth="18*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">P</th>
          <th class="bitfields">o2</th>
          <th class="bitfields">W</th>
          <th class="bitfields">o1</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="STR_r_A1_post" iformfile="str_r.xml" label="post-indexed" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STR_r">STR (register)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDR_r_A1_post" iformfile="ldr_r.xml" label="post-indexed" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDR_r">LDR (register)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="STRT_A2" iformfile="strt.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STRT">STRT</td>
          <td class="enctags">A2</td>
        </tr>
        <tr class="instructiontable" encname="LDRT_A2" iformfile="ldrt.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDRT">LDRT</td>
          <td class="enctags">A2</td>
        </tr>
        <tr class="instructiontable" encname="STRB_r_A1_post" iformfile="strb_r.xml" label="post-indexed" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STRB_r">STRB (register)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRB_r_A1_post" iformfile="ldrb_r.xml" label="post-indexed" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDRB_r">LDRB (register)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="STRBT_A2" iformfile="strbt.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STRBT">STRBT</td>
          <td class="enctags">A2</td>
        </tr>
        <tr class="instructiontable" encname="LDRBT_A2" iformfile="ldrbt.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDRBT">LDRBT</td>
          <td class="enctags">A2</td>
        </tr>
        <tr class="instructiontable" encname="STR_r_A1_pre" iformfile="str_r.xml" label="pre-indexed" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STR_r">STR (register)</td>
          <td class="enctags">A1, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDR_r_A1_pre" iformfile="ldr_r.xml" label="pre-indexed" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDR_r">LDR (register)</td>
          <td class="enctags">A1, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="STRB_r_A1_pre" iformfile="strb_r.xml" label="pre-indexed" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STRB_r">STRB (register)</td>
          <td class="enctags">A1, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRB_r_A1_pre" iformfile="ldrb_r.xml" label="pre-indexed" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDRB_r">LDRB (register)</td>
          <td class="enctags">A1, Pre-indexed</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="media">Media instructions</funcgroupheader>
  <iclass_sect id="bfx" title="Bitfield Extract">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="22" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="21" settings="1">
        <c>1</c>
      </box>
      <box hibit="20" width="5" name="widthm1" usename="1">
        <c colspan="5"></c>
      </box>
      <box hibit="15" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="5" name="lsb" usename="1">
        <c colspan="5"></c>
      </box>
      <box hibit="6" width="3" settings="3">
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="bfx" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">U</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="SBFX_A1" iformfile="sbfx.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SBFX">SBFX</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UBFX_A1" iformfile="ubfx.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="UBFX">UBFX</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="bfi" title="Bitfield Insert">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="7" settings="7">
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="20" width="5" name="msb" usename="1">
        <c colspan="5"></c>
      </box>
      <box hibit="15" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="5" name="lsb" usename="1">
        <c colspan="5"></c>
      </box>
      <box hibit="6" width="3" settings="3">
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="bfi" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">Rn</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="BFI_A1" iformfile="bfi.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="BFI">BFI</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="BFC_A1" iformfile="bfc.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="BFC">BFC</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="extend" title="Extend and Add">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="22" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" name="op" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" name="rotate" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="9" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="8" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="7" width="4" settings="4">
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="extend" cols="5">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="4*" />
      <col colno="3" printwidth="9*" />
      <col colno="4" printwidth="18*" />
      <col colno="5" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">U</th>
          <th class="bitfields">op</th>
          <th class="bitfields">Rn</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="SXTAB16_A1" iformfile="sxtab16.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="SXTAB16">SXTAB16</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="SXTB16_A1" iformfile="sxtb16.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="SXTB16">SXTB16</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="SXTAB_A1" iformfile="sxtab.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="SXTAB">SXTAB</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="SXTB_A1" iformfile="sxtb.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="SXTB">SXTB</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="SXTAH_A1" iformfile="sxtah.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="SXTAH">SXTAH</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="SXTH_A1" iformfile="sxth.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="SXTH">SXTH</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UXTAB16_A1" iformfile="uxtab16.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="UXTAB16">UXTAB16</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UXTB16_A1" iformfile="uxtb16.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="UXTB16">UXTB16</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UXTAB_A1" iformfile="uxtab.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="UXTAB">UXTAB</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UXTB_A1" iformfile="uxtb.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="UXTB">UXTB</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UXTAH_A1" iformfile="uxtah.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="UXTAH">UXTAH</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UXTH_A1" iformfile="uxth.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="UXTH">UXTH</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="pack" title="Pack Halfword">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="8" settings="8">
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="5" name="imm5" usename="1">
        <c colspan="5"></c>
      </box>
      <box hibit="6" name="tb" usename="1">
        <c></c>
      </box>
      <box hibit="5" width="2" settings="2">
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="pack" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="11*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="PKHTB_A1" iformfile="pkh.xml" first="t" last="t">
          <td class="iformname" iformid="PKH">PKHBT, PKHTB</td>
          <td class="enctags">A1, PKHTB</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="parallel" title="Parallel Arithmetic">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="22" width="3" name="op1" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="10" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="9" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="8" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="7" name="B" usename="1">
        <c></c>
      </box>
      <box hibit="6" width="2" name="op2" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="4" settings="1">
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="parallel" cols="5">
      <col colno="1" printwidth="5*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="5*" />
      <col colno="4" printwidth="18*" />
      <col colno="5" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">op1</th>
          <th class="bitfields">B</th>
          <th class="bitfields">op2</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_parallel" undef="1" oneofthismnem="14" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SADD16_A1" iformfile="sadd16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="SADD16">SADD16</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="SASX_A1" iformfile="sasx.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="SASX">SASX</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="SSAX_A1" iformfile="ssax.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="SSAX">SSAX</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="SSUB16_A1" iformfile="ssub16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="SSUB16">SSUB16</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="SADD8_A1" iformfile="sadd8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="SADD8">SADD8</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_17_parallel" undef="1" oneofthismnem="14" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_18_parallel" undef="1" oneofthismnem="14" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SSUB8_A1" iformfile="ssub8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="SSUB8">SSUB8</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="QADD16_A1" iformfile="qadd16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="QADD16">QADD16</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="QASX_A1" iformfile="qasx.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="QASX">QASX</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="QSAX_A1" iformfile="qsax.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="QSAX">QSAX</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="QSUB16_A1" iformfile="qsub16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="QSUB16">QSUB16</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="QADD8_A1" iformfile="qadd8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="QADD8">QADD8</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_25_parallel" undef="1" oneofthismnem="14" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_26_parallel" undef="1" oneofthismnem="14" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="QSUB8_A1" iformfile="qsub8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="QSUB8">QSUB8</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="SHADD16_A1" iformfile="shadd16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="SHADD16">SHADD16</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="SHASX_A1" iformfile="shasx.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="SHASX">SHASX</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="SHSAX_A1" iformfile="shsax.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="SHSAX">SHSAX</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="SHSUB16_A1" iformfile="shsub16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="SHSUB16">SHSUB16</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="SHADD8_A1" iformfile="shadd8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="SHADD8">SHADD8</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_33_parallel" undef="1" oneofthismnem="14" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_34_parallel" undef="1" oneofthismnem="14" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SHSUB8_A1" iformfile="shsub8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="SHSUB8">SHSUB8</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_36_parallel" undef="1" oneofthismnem="14" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UADD16_A1" iformfile="uadd16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="UADD16">UADD16</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UASX_A1" iformfile="uasx.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="UASX">UASX</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="USAX_A1" iformfile="usax.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="USAX">USAX</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="USUB16_A1" iformfile="usub16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="USUB16">USUB16</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UADD8_A1" iformfile="uadd8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="UADD8">UADD8</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_42_parallel" undef="1" oneofthismnem="14" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_43_parallel" undef="1" oneofthismnem="14" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="USUB8_A1" iformfile="usub8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="USUB8">USUB8</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UQADD16_A1" iformfile="uqadd16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="UQADD16">UQADD16</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UQASX_A1" iformfile="uqasx.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="UQASX">UQASX</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UQSAX_A1" iformfile="uqsax.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="UQSAX">UQSAX</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UQSUB16_A1" iformfile="uqsub16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="UQSUB16">UQSUB16</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UQADD8_A1" iformfile="uqadd8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="UQADD8">UQADD8</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_50_parallel" undef="1" oneofthismnem="14" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_51_parallel" undef="1" oneofthismnem="14" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UQSUB8_A1" iformfile="uqsub8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="UQSUB8">UQSUB8</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UHADD16_A1" iformfile="uhadd16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="UHADD16">UHADD16</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UHASX_A1" iformfile="uhasx.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="UHASX">UHASX</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UHSAX_A1" iformfile="uhsax.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="UHSAX">UHSAX</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UHSUB16_A1" iformfile="uhsub16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="UHSUB16">UHSUB16</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UHADD8_A1" iformfile="uhadd8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="UHADD8">UHADD8</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_58_parallel" undef="1" oneofthismnem="14" first="t" last="t">
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_59_parallel" undef="1" oneofthismnem="14" first="t" last="t">
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UHSUB8_A1" iformfile="uhsub8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="UHSUB8">UHSUB8</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="udf" title="Permanently UNDEFINED">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="8" settings="8">
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="19" width="12" name="imm12" usename="1">
        <c colspan="12"></c>
      </box>
      <box hibit="7" width="4" settings="4">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="imm4" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="udf" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">cond</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_udf" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">0xxx</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_12_udf" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">10xx</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_13_udf" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">110x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UDF_A1" iformfile="udf.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">1110</td>
          <td class="iformname" iformid="UDF">UDF</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="reverse" title="Reverse Bit/Byte">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="22" name="o1" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="19" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="18" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="17" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="16" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="15" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="10" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="9" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="8" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="7" name="o2" usename="1">
        <c></c>
      </box>
      <box hibit="6" width="3" settings="3">
        <c>0</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="reverse" cols="4">
      <col colno="1" printwidth="4*" />
      <col colno="2" printwidth="4*" />
      <col colno="3" printwidth="18*" />
      <col colno="4" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">o1</th>
          <th class="bitfields">o2</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="REV_A1" iformfile="rev.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="REV">REV</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="REV16_A1" iformfile="rev16.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="REV16">REV16</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="RBIT_A1" iformfile="rbit.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="RBIT">RBIT</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="REVSH_A1" iformfile="revsh.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="REVSH">REVSH</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="sat16" title="Saturate 16-bit">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="22" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="sat_imm" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="10" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="9" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="8" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="7" width="4" settings="4">
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="sat16" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">U</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="SSAT16_A1" iformfile="ssat16.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SSAT16">SSAT16</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="USAT16_A1" iformfile="usat16.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="USAT16">USAT16</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="sat32" title="Saturate 32-bit">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="22" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="21" settings="1">
        <c>1</c>
      </box>
      <box hibit="20" width="5" name="sat_imm" usename="1">
        <c colspan="5"></c>
      </box>
      <box hibit="15" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="5" name="imm5" usename="1">
        <c colspan="5"></c>
      </box>
      <box hibit="6" name="sh" usename="1">
        <c></c>
      </box>
      <box hibit="5" width="2" settings="2">
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="sat32" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="28*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">U</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="SSAT_A1_ASR" iformfile="ssat.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SSAT">SSAT</td>
          <td class="enctags">A1, Arithmetic shift right</td>
        </tr>
        <tr class="instructiontable" encname="USAT_A1_ASR" iformfile="usat.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="USAT">USAT</td>
          <td class="enctags">A1, Arithmetic shift right</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="selbytes" title="Select Bytes">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="8" settings="8">
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="10" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="9" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="8" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="7" width="4" settings="4">
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="selbytes" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="SEL_A1" iformfile="sel.xml" first="t" last="t">
          <td class="iformname" iformid="SEL">SEL</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="smul_div" title="Signed multiply, Divide">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="22" width="3" name="op1" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="19" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Ra" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" width="3" name="op2" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="4" settings="1">
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="smul_div" cols="5">
      <col colno="1" printwidth="5*" />
      <col colno="2" printwidth="9*" />
      <col colno="3" printwidth="8*" />
      <col colno="4" printwidth="18*" />
      <col colno="5" printwidth="13*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">op1</th>
          <th class="bitfields">Ra</th>
          <th class="bitfields">op2</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="SMLAD_A1" iformfile="smlad.xml" label="SMLAD" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td class="iformname" iformid="SMLAD">SMLAD, SMLADX</td>
          <td class="enctags">A1, SMLAD</td>
        </tr>
        <tr class="instructiontable" encname="SMLADX_A1" iformfile="smlad.xml" label="SMLADX" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td class="iformname" iformid="SMLAD">SMLAD, SMLADX</td>
          <td class="enctags">A1, SMLADX</td>
        </tr>
        <tr class="instructiontable" encname="SMLSD_A1" iformfile="smlsd.xml" label="SMLSD" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="3" class="bitfield">010</td>
          <td class="iformname" iformid="SMLSD">SMLSD, SMLSDX</td>
          <td class="enctags">A1, SMLSD</td>
        </tr>
        <tr class="instructiontable" encname="SMLSDX_A1" iformfile="smlsd.xml" label="SMLSDX" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="3" class="bitfield">011</td>
          <td class="iformname" iformid="SMLSD">SMLSD, SMLSDX</td>
          <td class="enctags">A1, SMLSDX</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_19_smul_div" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="3" class="bitfield">1xx</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SMUAD_A1" iformfile="smuad.xml" label="SMUAD" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td class="iformname" iformid="SMUAD">SMUAD, SMUADX</td>
          <td class="enctags">A1, SMUAD</td>
        </tr>
        <tr class="instructiontable" encname="SMUADX_A1" iformfile="smuad.xml" label="SMUADX" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td class="iformname" iformid="SMUAD">SMUAD, SMUADX</td>
          <td class="enctags">A1, SMUADX</td>
        </tr>
        <tr class="instructiontable" encname="SMUSD_A1" iformfile="smusd.xml" label="SMUSD" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="3" class="bitfield">010</td>
          <td class="iformname" iformid="SMUSD">SMUSD, SMUSDX</td>
          <td class="enctags">A1, SMUSD</td>
        </tr>
        <tr class="instructiontable" encname="SMUSDX_A1" iformfile="smusd.xml" label="SMUSDX" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="3" class="bitfield">011</td>
          <td class="iformname" iformid="SMUSD">SMUSD, SMUSDX</td>
          <td class="enctags">A1, SMUSDX</td>
        </tr>
        <tr class="instructiontable" encname="SDIV_A1" iformfile="sdiv.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="3" class="bitfield">000</td>
          <td class="iformname" iformid="SDIV">SDIV</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_21_smul_div" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="3" class="bitfield">!= 000</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_22_smul_div" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="3" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UDIV_A1" iformfile="udiv.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="3" class="bitfield">000</td>
          <td class="iformname" iformid="UDIV">UDIV</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_24_smul_div" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="3" class="bitfield">!= 000</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SMLALD_A1" iformfile="smlald.xml" label="SMLALD" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="3" class="bitfield">000</td>
          <td class="iformname" iformid="SMLALD">SMLALD, SMLALDX</td>
          <td class="enctags">A1, SMLALD</td>
        </tr>
        <tr class="instructiontable" encname="SMLALDX_A1" iformfile="smlald.xml" label="SMLALDX" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="3" class="bitfield">001</td>
          <td class="iformname" iformid="SMLALD">SMLALD, SMLALDX</td>
          <td class="enctags">A1, SMLALDX</td>
        </tr>
        <tr class="instructiontable" encname="SMLSLD_A1" iformfile="smlsld.xml" label="SMLSLD" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="3" class="bitfield">010</td>
          <td class="iformname" iformid="SMLSLD">SMLSLD, SMLSLDX</td>
          <td class="enctags">A1, SMLSLD</td>
        </tr>
        <tr class="instructiontable" encname="SMLSLDX_A1" iformfile="smlsld.xml" label="SMLSLDX" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="3" class="bitfield">011</td>
          <td class="iformname" iformid="SMLSLD">SMLSLD, SMLSLDX</td>
          <td class="enctags">A1, SMLSLDX</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_29_smul_div" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="3" class="bitfield">1xx</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SMMLA_A1" iformfile="smmla.xml" label="SMMLA" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td class="iformname" iformid="SMMLA">SMMLA, SMMLAR</td>
          <td class="enctags">A1, SMMLA</td>
        </tr>
        <tr class="instructiontable" encname="SMMLAR_A1" iformfile="smmla.xml" label="SMMLAR" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td class="iformname" iformid="SMMLA">SMMLA, SMMLAR</td>
          <td class="enctags">A1, SMMLAR</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_34_smul_div" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="3" class="bitfield">01x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_35_smul_div" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="3" class="bitfield">10x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SMMLS_A1" iformfile="smmls.xml" label="SMMLS" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="3" class="bitfield">110</td>
          <td class="iformname" iformid="SMMLS">SMMLS, SMMLSR</td>
          <td class="enctags">A1, SMMLS</td>
        </tr>
        <tr class="instructiontable" encname="SMMLSR_A1" iformfile="smmls.xml" label="SMMLSR" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="3" class="bitfield">111</td>
          <td class="iformname" iformid="SMMLS">SMMLS, SMMLSR</td>
          <td class="enctags">A1, SMMLSR</td>
        </tr>
        <tr class="instructiontable" encname="SMMUL_A1" iformfile="smmul.xml" label="SMMUL" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td class="iformname" iformid="SMMUL">SMMUL, SMMULR</td>
          <td class="enctags">A1, SMMUL</td>
        </tr>
        <tr class="instructiontable" encname="SMMULR_A1" iformfile="smmul.xml" label="SMMULR" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td class="iformname" iformid="SMMUL">SMMUL, SMMULR</td>
          <td class="enctags">A1, SMMULR</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_38_smul_div" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="3" class="bitfield">11x</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="3" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="usad" title="Unsigned Sum of Absolute Differences">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="8" settings="8">
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Ra" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" width="4" settings="4">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="usad" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">Ra</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="USADA8_A1" iformfile="usada8.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="USADA8">USADA8</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="USAD8_A1" iformfile="usad8.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="USAD8">USAD8</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="brblk">Branch, branch with link, and block data transfer</funcgroupheader>
  <iclass_sect id="b_imm" title="Branch (immediate)">
    <regdiagram form="32" psname="">
      <box hibit="31" width="4" name="cond" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="27" width="3" settings="3">
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="24" name="H" usename="1">
        <c></c>
      </box>
      <box hibit="23" width="24" name="imm24" usename="1">
        <c colspan="24"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="b_imm" cols="4">
      <col colno="1" printwidth="9*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="21*" />
      <col colno="4" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">cond</th>
          <th class="bitfields">H</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="B_A1" iformfile="b.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="B">B</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encoding="a1" iformfile="bl_i.xml" label="A1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="BL_i">BL, BLX (immediate)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encoding="a2" iformfile="bl_i.xml" label="A2" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="BL_i">BL, BLX (immediate)</td>
          <td class="enctags">A2</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldstexcept" title="Exception Save/Restore">
    <regdiagram form="32" psname="">
      <box hibit="31" width="7" settings="7">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="24" name="P" usename="1">
        <c></c>
      </box>
      <box hibit="23" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="22" name="S" usename="1">
        <c></c>
      </box>
      <box hibit="21" name="W" usename="1">
        <c></c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="11" name="op" usename="1">
        <c colspan="11"></c>
      </box>
      <box hibit="4" width="5" name="mode" usename="1">
        <c colspan="5"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="ldstexcept" cols="6">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="3*" />
      <col colno="4" printwidth="3*" />
      <col colno="5" printwidth="33*" />
      <col colno="6" printwidth="22*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">P</th>
          <th class="bitfields">U</th>
          <th class="bitfields">S</th>
          <th class="bitfields">L</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_ldstexcept" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="RFEDA_A1_AS" iformfile="rfe.xml" label="Decrement After" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="RFE">RFE, RFEDA, RFEDB, RFEIA, RFEIB</td>
          <td class="enctags">A1, Decrement After</td>
        </tr>
        <tr class="instructiontable" encname="SRSDA_A1_AS" iformfile="srs.xml" label="Decrement After" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SRS">SRS, SRSDA, SRSDB, SRSIA, SRSIB</td>
          <td class="enctags">A1, Decrement After</td>
        </tr>
        <tr class="instructiontable" encname="RFEIA_A1_AS" iformfile="rfe.xml" label="Increment After" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="RFE">RFE, RFEDA, RFEDB, RFEIA, RFEIB</td>
          <td class="enctags">A1, Increment After</td>
        </tr>
        <tr class="instructiontable" encname="SRSIA_A1_AS" iformfile="srs.xml" label="Increment After" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SRS">SRS, SRSDA, SRSDB, SRSIA, SRSIB</td>
          <td class="enctags">A1, Increment After</td>
        </tr>
        <tr class="instructiontable" encname="RFEDB_A1_AS" iformfile="rfe.xml" label="Decrement Before" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="RFE">RFE, RFEDA, RFEDB, RFEIA, RFEIB</td>
          <td class="enctags">A1, Decrement Before</td>
        </tr>
        <tr class="instructiontable" encname="SRSDB_A1_AS" iformfile="srs.xml" label="Decrement Before" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SRS">SRS, SRSDA, SRSDB, SRSIA, SRSIB</td>
          <td class="enctags">A1, Decrement Before</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_20_ldstexcept" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="RFEIB_A1_AS" iformfile="rfe.xml" label="Increment Before" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="RFE">RFE, RFEDA, RFEDB, RFEIA, RFEIB</td>
          <td class="enctags">A1, Increment Before</td>
        </tr>
        <tr class="instructiontable" encname="SRSIB_A1_AS" iformfile="srs.xml" label="Increment Before" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SRS">SRS, SRSDA, SRSDB, SRSIA, SRSIB</td>
          <td class="enctags">A1, Increment Before</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldstm" title="Load/Store Multiple">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="3" settings="3">
        <c>1</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="24" name="P" usename="1">
        <c></c>
      </box>
      <box hibit="23" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="22" name="op" usename="1">
        <c></c>
      </box>
      <box hibit="21" name="W" usename="1">
        <c></c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="16" name="register_list" usename="1">
        <c colspan="16"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="ldstm" cols="7">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="4*" />
      <col colno="4" printwidth="3*" />
      <col colno="5" printwidth="18*" />
      <col colno="6" printwidth="24*" />
      <col colno="7" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">P</th>
          <th class="bitfields">U</th>
          <th class="bitfields">op</th>
          <th class="bitfields">L</th>
          <th class="bitfields">register_list</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="STMDA_A1" iformfile="stmda.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="16" class="bitfield"></td>
          <td class="iformname" iformid="STMDA">STMDA, STMED</td>
        </tr>
        <tr class="instructiontable" encname="LDMDA_A1" iformfile="ldmda.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="16" class="bitfield"></td>
          <td class="iformname" iformid="LDMDA">LDMDA, LDMFA</td>
        </tr>
        <tr class="instructiontable" encname="STM_A1" iformfile="stm.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="16" class="bitfield"></td>
          <td class="iformname" iformid="STM">STM, STMIA, STMEA</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="LDM_A1" iformfile="ldm.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="16" class="bitfield"></td>
          <td class="iformname" iformid="LDM">LDM, LDMIA, LDMFD</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="STM_u_A1_AS" iformfile="stm_u.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="16" class="bitfield"></td>
          <td class="iformname" iformid="STM_u">STM (User registers)</td>
        </tr>
        <tr class="instructiontable" encname="STMDB_A1" iformfile="stmdb.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="16" class="bitfield"></td>
          <td class="iformname" iformid="STMDB">STMDB, STMFD</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="LDMDB_A1" iformfile="ldmdb.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="16" class="bitfield"></td>
          <td class="iformname" iformid="LDMDB">LDMDB, LDMEA</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="LDM_u_A1_AS" iformfile="ldm_u.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="16" class="bitfield">0xxxxxxxxxxxxxxx</td>
          <td class="iformname" iformid="LDM_u">LDM (User registers)</td>
        </tr>
        <tr class="instructiontable" encname="STMIB_A1" iformfile="stmib.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="16" class="bitfield"></td>
          <td class="iformname" iformid="STMIB">STMIB, STMFA</td>
        </tr>
        <tr class="instructiontable" encname="LDMIB_A1" iformfile="ldmib.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="16" class="bitfield"></td>
          <td class="iformname" iformid="LDMIB">LDMIB, LDMED</td>
        </tr>
        <tr class="instructiontable" encname="LDM_e_A1_AS" iformfile="ldm_e.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="16" class="bitfield">1xxxxxxxxxxxxxxx</td>
          <td class="iformname" iformid="LDM_e">LDM (exception return)</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="fpdp">Floating-point data-processing</funcgroupheader>
  <iclass_sect id="fpdp3reg" title="Floating-point data-processing (three registers)">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="4" settings="4">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="23" name="o0" usename="1">
        <c></c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" name="o1" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="9" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" name="o2" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="o0:D:o1" op="!=" val="1x11" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="fpdp3reg" cols="5">
      <col colno="1" printwidth="8*" />
      <col colno="2" printwidth="6*" />
      <col colno="3" printwidth="4*" />
      <col colno="4" printwidth="23*" />
      <col colno="5" printwidth="29*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">o0:o1</th>
          <th class="bitfields">size</th>
          <th class="bitfields">o2</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_fpdp3reg" undef="1" first="t" last="t">
          <td bitwidth="4" class="bitfield">!= 111</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VMLA_f_A2_H" arch_version="FEAT_FP16" iformfile="vmla_f.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMLA_f">VMLA (floating-point)</td>
          <td class="enctags">A2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMLS_f_A2_H" arch_version="FEAT_FP16" iformfile="vmls_f.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMLS_f">VMLS (floating-point)</td>
          <td class="enctags">A2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMLA_f_A2_S" iformfile="vmla_f.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMLA_f">VMLA (floating-point)</td>
          <td class="enctags">A2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMLS_f_A2_S" iformfile="vmls_f.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMLS_f">VMLS (floating-point)</td>
          <td class="enctags">A2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMLA_f_A2_D" iformfile="vmla_f.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMLA_f">VMLA (floating-point)</td>
          <td class="enctags">A2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMLS_f_A2_D" iformfile="vmls_f.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMLS_f">VMLS (floating-point)</td>
          <td class="enctags">A2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNMLS_A1_H" arch_version="FEAT_FP16" iformfile="vnmls.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VNMLS">VNMLS</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNMLA_A1_H" arch_version="FEAT_FP16" iformfile="vnmla.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VNMLA">VNMLA</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNMLS_A1_S" iformfile="vnmls.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VNMLS">VNMLS</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNMLA_A1_S" iformfile="vnmla.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VNMLA">VNMLA</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNMLS_A1_D" iformfile="vnmls.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VNMLS">VNMLS</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNMLA_A1_D" iformfile="vnmla.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VNMLA">VNMLA</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMUL_f_A2_H" arch_version="FEAT_FP16" iformfile="vmul_f.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMUL_f">VMUL (floating-point)</td>
          <td class="enctags">A2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNMUL_A1_H" arch_version="FEAT_FP16" iformfile="vnmul.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VNMUL">VNMUL</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMUL_f_A2_S" iformfile="vmul_f.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMUL_f">VMUL (floating-point)</td>
          <td class="enctags">A2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNMUL_A1_S" iformfile="vnmul.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VNMUL">VNMUL</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMUL_f_A2_D" iformfile="vmul_f.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMUL_f">VMUL (floating-point)</td>
          <td class="enctags">A2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNMUL_A1_D" iformfile="vnmul.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VNMUL">VNMUL</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VADD_f_A2_H" arch_version="FEAT_FP16" iformfile="vadd_f.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VADD_f">VADD (floating-point)</td>
          <td class="enctags">A2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VSUB_f_A2_H" arch_version="FEAT_FP16" iformfile="vsub_f.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VSUB_f">VSUB (floating-point)</td>
          <td class="enctags">A2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VADD_f_A2_S" iformfile="vadd_f.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VADD_f">VADD (floating-point)</td>
          <td class="enctags">A2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VSUB_f_A2_S" iformfile="vsub_f.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VSUB_f">VSUB (floating-point)</td>
          <td class="enctags">A2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VADD_f_A2_D" iformfile="vadd_f.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VADD_f">VADD (floating-point)</td>
          <td class="enctags">A2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VSUB_f_A2_D" iformfile="vsub_f.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VSUB_f">VSUB (floating-point)</td>
          <td class="enctags">A2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VDIV_A1_H" arch_version="FEAT_FP16" iformfile="vdiv.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VDIV">VDIV</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VDIV_A1_S" iformfile="vdiv.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VDIV">VDIV</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VDIV_A1_D" iformfile="vdiv.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VDIV">VDIV</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFNMS_A1_H" arch_version="FEAT_FP16" iformfile="vfnms.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VFNMS">VFNMS</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFNMA_A1_H" arch_version="FEAT_FP16" iformfile="vfnma.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFNMA">VFNMA</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFNMS_A1_S" iformfile="vfnms.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VFNMS">VFNMS</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFNMA_A1_S" iformfile="vfnma.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFNMA">VFNMA</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFNMS_A1_D" iformfile="vfnms.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VFNMS">VFNMS</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFNMA_A1_D" iformfile="vfnma.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFNMA">VFNMA</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFMA_A2_H" arch_version="FEAT_FP16" iformfile="vfma.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VFMA">VFMA</td>
          <td class="enctags">A2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFMS_A2_H" arch_version="FEAT_FP16" iformfile="vfms.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFMS">VFMS</td>
          <td class="enctags">A2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFMA_A2_S" iformfile="vfma.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VFMA">VFMA</td>
          <td class="enctags">A2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFMS_A2_S" iformfile="vfms.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFMS">VFMS</td>
          <td class="enctags">A2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFMA_A2_D" iformfile="vfma.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VFMA">VFMA</td>
          <td class="enctags">A2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFMS_A2_D" iformfile="vfms.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFMS">VFMS</td>
          <td class="enctags">A2, Double-precision scalar</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="fpdp2reg" title="Floating-point data-processing (two registers)">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="19" name="o1" usename="1">
        <c></c>
      </box>
      <box hibit="18" width="3" name="opc2" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="9" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="7" name="o3" usename="1">
        <c></c>
      </box>
      <box hibit="6" settings="1">
        <c>1</c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="fpdp2reg" cols="6">
      <col colno="1" printwidth="4*" />
      <col colno="2" printwidth="6*" />
      <col colno="3" printwidth="6*" />
      <col colno="4" printwidth="4*" />
      <col colno="5" printwidth="63*" />
      <col colno="6" printwidth="42*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">o1</th>
          <th class="bitfields">opc2</th>
          <th class="bitfields">size</th>
          <th class="bitfields">o3</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_fpdp2reg" undef="1" oneofthismnem="7" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_12_fpdp2reg" undef="1" oneofthismnem="7" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VABS_A2_H" arch_version="FEAT_FP16" iformfile="vabs.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VABS">VABS</td>
          <td class="enctags">A2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMOV_r_A2_S" iformfile="vmov_r.xml" label="single-precision scalar" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMOV_r">VMOV (register)</td>
          <td class="enctags">A2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VABS_A2_S" iformfile="vabs.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VABS">VABS</td>
          <td class="enctags">A2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMOV_r_A2_D" iformfile="vmov_r.xml" label="double-precision scalar" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMOV_r">VMOV (register)</td>
          <td class="enctags">A2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VABS_A2_D" iformfile="vabs.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VABS">VABS</td>
          <td class="enctags">A2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNEG_A2_H" arch_version="FEAT_FP16" iformfile="vneg.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VNEG">VNEG</td>
          <td class="enctags">A2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VSQRT_A1_H" arch_version="FEAT_FP16" iformfile="vsqrt.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VSQRT">VSQRT</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNEG_A2_S" iformfile="vneg.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VNEG">VNEG</td>
          <td class="enctags">A2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VSQRT_A1_S" iformfile="vsqrt.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VSQRT">VSQRT</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNEG_A2_D" iformfile="vneg.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VNEG">VNEG</td>
          <td class="enctags">A2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VSQRT_A1_D" iformfile="vsqrt.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VSQRT">VSQRT</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_24_fpdp2reg" undef="1" oneofthismnem="7" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VCVTB_A1_SH" iformfile="vcvtb.xml" label="half-precision to single-precision" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVTB">VCVTB</td>
          <td class="enctags">A1, Half-precision to single-precision</td>
        </tr>
        <tr class="instructiontable" encname="VCVTT_A1_SH" iformfile="vcvtt.xml" label="half-precision to single-precision" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVTT">VCVTT</td>
          <td class="enctags">A1, Half-precision to single-precision</td>
        </tr>
        <tr class="instructiontable" encname="VCVTB_A1_DH" iformfile="vcvtb.xml" label="half-precision to double-precision" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVTB">VCVTB</td>
          <td class="enctags">A1, Half-precision to double-precision</td>
        </tr>
        <tr class="instructiontable" encname="VCVTT_A1_DH" iformfile="vcvtt.xml" label="half-precision to double-precision" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVTT">VCVTT</td>
          <td class="enctags">A1, Half-precision to double-precision</td>
        </tr>
        <tr class="instructiontable" encname="VCVTB_A1_bfs" arch_version="FEAT_AA32BF16" iformfile="vcvtb_bfs.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVTB_bfs">VCVTB (BFloat16)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VCVTT_A1_bfs" arch_version="FEAT_AA32BF16" iformfile="vcvtt_bfs.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVTT_bfs">VCVTT (BFloat16)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VCVTB_A1_HS" iformfile="vcvtb.xml" label="single-precision to half-precision" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVTB">VCVTB</td>
          <td class="enctags">A1, Single-precision to half-precision</td>
        </tr>
        <tr class="instructiontable" encname="VCVTT_A1_HS" iformfile="vcvtt.xml" label="single-precision to half-precision" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVTT">VCVTT</td>
          <td class="enctags">A1, Single-precision to half-precision</td>
        </tr>
        <tr class="instructiontable" encname="VCVTB_A1_HD" iformfile="vcvtb.xml" label="double-precision to half-precision" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVTB">VCVTB</td>
          <td class="enctags">A1, Double-precision to half-precision</td>
        </tr>
        <tr class="instructiontable" encname="VCVTT_A1_HD" iformfile="vcvtt.xml" label="double-precision to half-precision" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVTT">VCVTT</td>
          <td class="enctags">A1, Double-precision to half-precision</td>
        </tr>
        <tr class="instructiontable" encname="VCMP_A1_H" arch_version="FEAT_FP16" iformfile="vcmp.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCMP">VCMP</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCMPE_A1_H" arch_version="FEAT_FP16" iformfile="vcmpe.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCMPE">VCMPE</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCMP_A1_S" iformfile="vcmp.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCMP">VCMP</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCMPE_A1_S" iformfile="vcmpe.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCMPE">VCMPE</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCMP_A1_D" iformfile="vcmp.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCMP">VCMP</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCMPE_A1_D" iformfile="vcmpe.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCMPE">VCMPE</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCMP_A2_H" arch_version="FEAT_FP16" iformfile="vcmp.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCMP">VCMP</td>
          <td class="enctags">A2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCMPE_A2_H" arch_version="FEAT_FP16" iformfile="vcmpe.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCMPE">VCMPE</td>
          <td class="enctags">A2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCMP_A2_S" iformfile="vcmp.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCMP">VCMP</td>
          <td class="enctags">A2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCMPE_A2_S" iformfile="vcmpe.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCMPE">VCMPE</td>
          <td class="enctags">A2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCMP_A2_D" iformfile="vcmp.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCMP">VCMP</td>
          <td class="enctags">A2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCMPE_A2_D" iformfile="vcmpe.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCMPE">VCMPE</td>
          <td class="enctags">A2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTR_vfp_A1_H" arch_version="FEAT_FP16" iformfile="vrintr_vfp.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTR_vfp">VRINTR</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTZ_vfp_A1_H" arch_version="FEAT_FP16" iformfile="vrintz_vfp.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VRINTZ_vfp">VRINTZ (floating-point)</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTR_vfp_A1_S" iformfile="vrintr_vfp.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTR_vfp">VRINTR</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTZ_vfp_A1_S" iformfile="vrintz_vfp.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VRINTZ_vfp">VRINTZ (floating-point)</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTR_vfp_A1_D" iformfile="vrintr_vfp.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTR_vfp">VRINTR</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTZ_vfp_A1_D" iformfile="vrintz_vfp.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VRINTZ_vfp">VRINTZ (floating-point)</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTX_vfp_A1_H" arch_version="FEAT_FP16" iformfile="vrintx_vfp.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTX_vfp">VRINTX (floating-point)</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_56_fpdp2reg" undef="1" oneofthismnem="7" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VRINTX_vfp_A1_S" iformfile="vrintx_vfp.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTX_vfp">VRINTX (floating-point)</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_ds_A1" iformfile="vcvt_ds.xml" label="single-precision to double-precision" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVT_ds">VCVT (between double-precision and single-precision)</td>
          <td class="enctags">A1, Single-precision to double-precision</td>
        </tr>
        <tr class="instructiontable" encname="VRINTX_vfp_A1_D" iformfile="vrintx_vfp.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTX_vfp">VRINTX (floating-point)</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_sd_A1" iformfile="vcvt_ds.xml" label="double-precision to single-precision" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVT_ds">VCVT (between double-precision and single-precision)</td>
          <td class="enctags">A1, Double-precision to single-precision</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_vi_A1_H" arch_version="FEAT_FP16" iformfile="vcvt_vi.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVT_vi">VCVT (integer to floating-point, floating-point)</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_vi_A1_S" iformfile="vcvt_vi.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVT_vi">VCVT (integer to floating-point, floating-point)</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_vi_A1_D" iformfile="vcvt_vi.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVT_vi">VCVT (integer to floating-point, floating-point)</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_62_fpdp2reg" undef="1" oneofthismnem="7" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_63_fpdp2reg" undef="1" oneofthismnem="7" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_64_fpdp2reg" undef="1" oneofthismnem="7" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VJCVT_A1" arch_version="FEAT_JSCVT" iformfile="vjcvt.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VJCVT">VJCVT</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_toxv_A1_H" arch_version="FEAT_FP16" iformfile="vcvt_xv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">01x</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVT_xv">VCVT (between floating-point and fixed-point, floating-point)</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_toxv_A1_S" iformfile="vcvt_xv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">01x</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVT_xv">VCVT (between floating-point and fixed-point, floating-point)</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_toxv_A1_D" iformfile="vcvt_xv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">01x</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVT_xv">VCVT (between floating-point and fixed-point, floating-point)</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTR_uiv_A1_H" arch_version="FEAT_FP16" iformfile="vcvtr_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVTR_iv">VCVTR</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_uiv_A1_H" arch_version="FEAT_FP16" iformfile="vcvt_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVT_iv">VCVT (floating-point to integer, floating-point)</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTR_uiv_A1_S" iformfile="vcvtr_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVTR_iv">VCVTR</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_uiv_A1_S" iformfile="vcvt_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVT_iv">VCVT (floating-point to integer, floating-point)</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTR_uiv_A1_D" iformfile="vcvtr_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVTR_iv">VCVTR</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_uiv_A1_D" iformfile="vcvt_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVT_iv">VCVT (floating-point to integer, floating-point)</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTR_siv_A1_H" arch_version="FEAT_FP16" iformfile="vcvtr_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVTR_iv">VCVTR</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_siv_A1_H" arch_version="FEAT_FP16" iformfile="vcvt_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVT_iv">VCVT (floating-point to integer, floating-point)</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTR_siv_A1_S" iformfile="vcvtr_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVTR_iv">VCVTR</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_siv_A1_S" iformfile="vcvt_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVT_iv">VCVT (floating-point to integer, floating-point)</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTR_siv_A1_D" iformfile="vcvtr_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVTR_iv">VCVTR</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_siv_A1_D" iformfile="vcvt_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVT_iv">VCVT (floating-point to integer, floating-point)</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_xv_A1_H" arch_version="FEAT_FP16" iformfile="vcvt_xv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">11x</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVT_xv">VCVT (between floating-point and fixed-point, floating-point)</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_xv_A1_S" iformfile="vcvt_xv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">11x</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVT_xv">VCVT (between floating-point and fixed-point, floating-point)</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_xv_A1_D" iformfile="vcvt_xv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">11x</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVT_xv">VCVT (between floating-point and fixed-point, floating-point)</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="fpimm" title="Floating-point move immediate">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="19" width="4" name="imm4H" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="9" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="7" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="6" settings="1">
        <c>0</c>
      </box>
      <box hibit="5" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="imm4L" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="fpimm" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="29*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_fpimm" undef="1" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VMOV_i_A2_H" arch_version="FEAT_FP16" iformfile="vmov_i.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="VMOV_i">VMOV (immediate)</td>
          <td class="enctags">A2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMOV_i_A2_S" iformfile="vmov_i.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="VMOV_i">VMOV (immediate)</td>
          <td class="enctags">A2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMOV_i_A2_D" iformfile="vmov_i.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="VMOV_i">VMOV (immediate)</td>
          <td class="enctags">A2, Double-precision scalar</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="sys_mov32">Advanced SIMD and System register 32-bit move</funcgroupheader>
  <iclass_sect id="movsimdgp" title="Advanced SIMD 8/16/32-bit element move/duplicate">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="4" settings="4">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="23" width="3" name="opc1" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" settings="4">
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" width="2" name="opc2" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="4" settings="1">
        <c>1</c>
      </box>
      <box hibit="3" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="2" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="1" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="0" settings="1">
        <c>(0)</c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="movsimdgp" cols="5">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="6*" />
      <col colno="4" printwidth="43*" />
      <col colno="5" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">opc1</th>
          <th class="bitfields">L</th>
          <th class="bitfields">opc2</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VMOV_rs_A1" iformfile="vmov_rs.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">0xx</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield"></td>
          <td class="iformname" iformid="VMOV_rs">VMOV (general-purpose register to scalar)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VMOV_sr_A1" iformfile="vmov_sr.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td class="iformname" iformid="VMOV_sr">VMOV (scalar to general-purpose register)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VDUP_r_A1" iformfile="vdup_r.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">1xx</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td class="iformname" iformid="VDUP_r">VDUP (general-purpose register)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_14_movsimdgp" undef="1" first="t" last="t">
          <td bitwidth="3" class="bitfield">1xx</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="movfpgp16" title="Floating-point 16-bit move">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="7" settings="7">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="20" name="op" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" settings="4">
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="5" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="4" settings="1">
        <c>1</c>
      </box>
      <box hibit="3" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="2" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="1" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="0" settings="1">
        <c>(0)</c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="movfpgp16" cols="2">
      <col colno="1" printwidth="60*" />
      <col colno="2" printwidth="33*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VMOV_h_A1" arch_version="FEAT_FP16" iformfile="vmov_h.xml" first="t" last="t">
          <td class="iformname" iformid="VMOV_h">VMOV (between general-purpose register and half-precision)</td>
          <td class="enctags">A1, To general-purpose register</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="movfpgp32" title="Floating-point 32-bit move">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="7" settings="7">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="20" name="op" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" settings="4">
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="5" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="4" settings="1">
        <c>1</c>
      </box>
      <box hibit="3" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="2" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="1" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="0" settings="1">
        <c>(0)</c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="movfpgp32" cols="2">
      <col colno="1" printwidth="62*" />
      <col colno="2" printwidth="33*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VMOV_s_A1" iformfile="vmov_s.xml" first="t" last="t">
          <td class="iformname" iformid="VMOV_s">VMOV (between general-purpose register and single-precision)</td>
          <td class="enctags">A1, To general-purpose register</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="movfpsr" title="Floating-point move special register">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="7" settings="7">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="reg" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" settings="4">
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="7" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="6" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="5" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="4" settings="1">
        <c>1</c>
      </box>
      <box hibit="3" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="2" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="1" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="0" settings="1">
        <c>(0)</c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="movfpsr" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VMSR_A1_AS" iformfile="vmsr.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMSR">VMSR</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VMRS_A1_AS" iformfile="vmrs.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMRS">VMRS</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="movcpgp32" title="System register 32-bit move">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="4" settings="4">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="23" width="3" name="opc1" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="CRn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="3" settings="3">
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="8" name="cp15" usename="1">
        <c></c>
      </box>
      <box hibit="7" width="3" name="opc2" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="4" settings="1">
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="CRm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="movcpgp32" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="MCR_A1" iformfile="mcr.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="MCR">MCR</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="MRC_A1" iformfile="mrc.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="MRC">MRC</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="sysldst_mov64">Advanced SIMD and System register load/store and 64-bit move</funcgroupheader>
  <iclass_sect id="movsimdfpgp64" title="Advanced SIMD and floating-point 64-bit move">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" settings="1">
        <c>0</c>
      </box>
      <box hibit="20" name="op" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rt2" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="9" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="7" width="2" name="opc2" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" name="o3" usename="1">
        <c></c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="movsimdfpgp64" cols="7">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="4*" />
      <col colno="3" printwidth="6*" />
      <col colno="4" printwidth="6*" />
      <col colno="5" printwidth="4*" />
      <col colno="6" printwidth="87*" />
      <col colno="7" printwidth="36*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">D</th>
          <th class="bitfields">op</th>
          <th class="bitfields">size</th>
          <th class="bitfields">opc2</th>
          <th class="bitfields">o3</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_movsimdfpgp64" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_12_movsimdfpgp64" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_13_movsimdfpgp64" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_18_movsimdfpgp64" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VMOV_toss_A1" iformfile="vmov_ss.xml" label="from general-purpose registers" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMOV_ss">VMOV (between two general-purpose registers and two single-precision registers)</td>
          <td class="enctags">A1, From general-purpose registers</td>
        </tr>
        <tr class="instructiontable" encname="VMOV_tod_A1" iformfile="vmov_d.xml" label="from general-purpose registers" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMOV_d">VMOV (between two general-purpose registers and a doubleword floating-point register)</td>
          <td class="enctags">A1, From general-purpose registers</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_19_movsimdfpgp64" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VMOV_ss_A1" iformfile="vmov_ss.xml" label="to general-purpose registers" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMOV_ss">VMOV (between two general-purpose registers and two single-precision registers)</td>
          <td class="enctags">A1, To general-purpose registers</td>
        </tr>
        <tr class="instructiontable" encname="VMOV_d_A1" iformfile="vmov_d.xml" label="to general-purpose registers" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMOV_d">VMOV (between two general-purpose registers and a doubleword floating-point register)</td>
          <td class="enctags">A1, To general-purpose registers</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldstsimdfp" title="Advanced SIMD and floating-point load/store">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="3" settings="3">
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="24" name="P" usename="1">
        <c></c>
      </box>
      <box hibit="23" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" name="W" usename="1">
        <c></c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="9" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="7" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="P:U:D:W" op="!=" val="00x0" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="ldstsimdfp" cols="9">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="3*" />
      <col colno="4" printwidth="3*" />
      <col colno="5" printwidth="9*" />
      <col colno="6" printwidth="6*" />
      <col colno="7" printwidth="10*" />
      <col colno="8" printwidth="27*" />
      <col colno="9" printwidth="29*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="7">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">P</th>
          <th class="bitfields">U</th>
          <th class="bitfields">W</th>
          <th class="bitfields">L</th>
          <th class="bitfields">Rn</th>
          <th class="bitfields">size</th>
          <th class="bitfields">imm8</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_ldstsimdfp" undef="1" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_12_ldstsimdfp" undef="1" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VSTM_A2" iformfile="vstm.xml" label="single-precision scalar" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VSTM">VSTM, VSTMDB, VSTMIA</td>
          <td class="enctags">A2, Increment After</td>
        </tr>
        <tr class="instructiontable" encname="VSTM_A1" iformfile="vstm.xml" label="double-precision scalar" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="8" class="bitfield">xxxxxxx0</td>
          <td class="iformname" iformid="VSTM">VSTM, VSTMDB, VSTMIA</td>
          <td class="enctags">A1, Increment After</td>
        </tr>
        <tr class="instructiontable" encname="FSTMIAX_A1" iformfile="fstmx.xml" label="Increment After" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="8" class="bitfield">xxxxxxx1</td>
          <td class="iformname" iformid="FSTMX">FSTMDBX, FSTMIAX</td>
          <td class="enctags">A1, Increment After</td>
        </tr>
        <tr class="instructiontable" encname="VLDM_A2" iformfile="vldm.xml" label="single-precision scalar" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VLDM">VLDM, VLDMDB, VLDMIA</td>
          <td class="enctags">A2, Increment After</td>
        </tr>
        <tr class="instructiontable" encname="VLDM_A1" iformfile="vldm.xml" label="double-precision scalar" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="8" class="bitfield">xxxxxxx0</td>
          <td class="iformname" iformid="VLDM">VLDM, VLDMDB, VLDMIA</td>
          <td class="enctags">A1, Increment After</td>
        </tr>
        <tr class="instructiontable" encname="FLDMIAX_A1" iformfile="fldmx.xml" label="Increment After" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="8" class="bitfield">xxxxxxx1</td>
          <td class="iformname" iformid="FLDMX">FLDM*X (FLDMDBX, FLDMIAX)</td>
          <td class="enctags">A1, Increment After</td>
        </tr>
        <tr class="instructiontable" encname="VSTR_A1_H" arch_version="FEAT_FP16" iformfile="vstr.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VSTR">VSTR</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VSTR_A1_S" iformfile="vstr.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VSTR">VSTR</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VSTR_A1_D" iformfile="vstr.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VSTR">VSTR</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VLDR_A1_H" arch_version="FEAT_FP16" iformfile="vldr_i.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VLDR_i">VLDR (immediate)</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VLDR_A1_S" iformfile="vldr_i.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VLDR_i">VLDR (immediate)</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VLDR_A1_D" iformfile="vldr_i.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VLDR_i">VLDR (immediate)</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_19_ldstsimdfp" undef="1" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VSTMDB_A2" iformfile="vstm.xml" label="single-precision scalar" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VSTM">VSTM, VSTMDB, VSTMIA</td>
          <td class="enctags">A2, Decrement Before</td>
        </tr>
        <tr class="instructiontable" encname="VSTMDB_A1" iformfile="vstm.xml" label="double-precision scalar" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="8" class="bitfield">xxxxxxx0</td>
          <td class="iformname" iformid="VSTM">VSTM, VSTMDB, VSTMIA</td>
          <td class="enctags">A1, Decrement Before</td>
        </tr>
        <tr class="instructiontable" encname="FSTMDBX_A1" iformfile="fstmx.xml" label="Decrement Before" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="8" class="bitfield">xxxxxxx1</td>
          <td class="iformname" iformid="FSTMX">FSTMDBX, FSTMIAX</td>
          <td class="enctags">A1, Decrement Before</td>
        </tr>
        <tr class="instructiontable" encname="VLDMDB_A2" iformfile="vldm.xml" label="single-precision scalar" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VLDM">VLDM, VLDMDB, VLDMIA</td>
          <td class="enctags">A2, Decrement Before</td>
        </tr>
        <tr class="instructiontable" encname="VLDMDB_A1" iformfile="vldm.xml" label="double-precision scalar" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="8" class="bitfield">xxxxxxx0</td>
          <td class="iformname" iformid="VLDM">VLDM, VLDMDB, VLDMIA</td>
          <td class="enctags">A1, Decrement Before</td>
        </tr>
        <tr class="instructiontable" encname="FLDMDBX_A1" iformfile="fldmx.xml" label="Decrement Before" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="8" class="bitfield">xxxxxxx1</td>
          <td class="iformname" iformid="FLDMX">FLDM*X (FLDMDBX, FLDMIAX)</td>
          <td class="enctags">A1, Decrement Before</td>
        </tr>
        <tr class="instructiontable" encname="VLDR_l_A1_H" arch_version="FEAT_FP16" iformfile="vldr_l.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VLDR_l">VLDR (literal)</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VLDR_l_A1_S" iformfile="vldr_l.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VLDR_l">VLDR (literal)</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VLDR_l_A1_D" iformfile="vldr_l.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VLDR_l">VLDR (literal)</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_35_ldstsimdfp" undef="1" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="movcpgp64" title="System register 64-bit move">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" settings="1">
        <c>0</c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rt2" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="3" settings="3">
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="8" name="cp15" usename="1">
        <c></c>
      </box>
      <box hibit="7" width="4" name="opc1" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="3" width="4" name="CRm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="movcpgp64" cols="4">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="18*" />
      <col colno="4" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">D</th>
          <th class="bitfields">L</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_movcpgp64" undef="1" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="MCRR_A1" iformfile="mcrr.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="MCRR">MCRR</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="MRRC_A1" iformfile="mrrc.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="MRRC">MRRC</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldstcp" title="System register load/store">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="3" settings="3">
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="24" name="P" usename="1">
        <c></c>
      </box>
      <box hibit="23" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" name="W" usename="1">
        <c></c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="CRd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="3" settings="3">
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="8" name="cp15" usename="1">
        <c></c>
      </box>
      <box hibit="7" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="P:U:D:W" op="!=" val="00x0" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="ldstcp" cols="8">
      <col colno="1" printwidth="8*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="3*" />
      <col colno="4" printwidth="9*" />
      <col colno="5" printwidth="9*" />
      <col colno="6" printwidth="6*" />
      <col colno="7" printwidth="18*" />
      <col colno="8" printwidth="18*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="6">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">P:U:W</th>
          <th class="bitfields">D</th>
          <th class="bitfields">L</th>
          <th class="bitfields">Rn</th>
          <th class="bitfields">CRd</th>
          <th class="bitfields">cp15</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_21_ldstcp" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">!= 000</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">!= 0101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="LDC_l_A1" iformfile="ldc_l.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">!= 000</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="LDC_l">LDC (literal)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_22_ldstcp" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">!= 000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_20_ldstcp" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">!= 000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="STC_A1_post" iformfile="stc.xml" label="post-indexed" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0x1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STC">STC</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDC_i_A1_post" iformfile="ldc_i.xml" label="post-indexed" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0x1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="LDC_i">LDC (immediate)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="STC_A1_unind" iformfile="stc.xml" label="unindexed" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STC">STC</td>
          <td class="enctags">A1, Unindexed</td>
        </tr>
        <tr class="instructiontable" encname="LDC_i_A1_unind" iformfile="ldc_i.xml" label="unindexed" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="LDC_i">LDC (immediate)</td>
          <td class="enctags">A1, Unindexed</td>
        </tr>
        <tr class="instructiontable" encname="STC_A1_off" iformfile="stc.xml" label="offset" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1x0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STC">STC</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="LDC_i_A1_off" iformfile="ldc_i.xml" label="offset" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1x0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="LDC_i">LDC (immediate)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="STC_A1_pre" iformfile="stc.xml" label="pre-indexed" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1x1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STC">STC</td>
          <td class="enctags">A1, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDC_i_A1_pre" iformfile="ldc_i.xml" label="pre-indexed" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1x1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="LDC_i">LDC (immediate)</td>
          <td class="enctags">A1, Pre-indexed</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="advsimdext">Unconditional Advanced SIMD and floating-point instructions</funcgroupheader>
  <iclass_sect id="simd_dotprod" title="Advanced SIMD and floating-point dot product">
    <regdiagram form="32" psname="">
      <box hibit="31" width="8" settings="8">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="23" name="op1" usename="1">
        <c></c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" name="op2" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="3" settings="3">
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="8" name="op4" usename="1">
        <c></c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" name="Q" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="simd_dotprod" cols="7">
      <col colno="1" printwidth="5*" />
      <col colno="2" printwidth="5*" />
      <col colno="3" printwidth="5*" />
      <col colno="4" printwidth="3*" />
      <col colno="5" printwidth="3*" />
      <col colno="6" printwidth="21*" />
      <col colno="7" printwidth="25*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">op1</th>
          <th class="bitfields">op2</th>
          <th class="bitfields">op4</th>
          <th class="bitfields">Q</th>
          <th class="bitfields">U</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_simd_dotprod" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VDOT_s_A1_D" arch_version="FEAT_AA32BF16" iformfile="vdot_s.xml" label="64-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VDOT_s">VDOT (by element)</td>
          <td class="enctags">A1, 64-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_14_simd_dotprod" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VDOT_s_A1_Q" arch_version="FEAT_AA32BF16" iformfile="vdot_s.xml" label="128-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VDOT_s">VDOT (by element)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_15_simd_dotprod" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_16_simd_dotprod" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VSDOT_s_A1_D" arch_version="FEAT_DotProd" iformfile="vsdot_s.xml" label="64-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VSDOT_s">VSDOT (by element)</td>
          <td class="enctags">A1, 64-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VUDOT_s_A1_D" arch_version="FEAT_DotProd" iformfile="vudot_s.xml" label="64-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VUDOT_s">VUDOT (by element)</td>
          <td class="enctags">A1, 64-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSDOT_s_A1_Q" arch_version="FEAT_DotProd" iformfile="vsdot_s.xml" label="128-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VSDOT_s">VSDOT (by element)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VUDOT_s_A1_Q" arch_version="FEAT_DotProd" iformfile="vudot_s.xml" label="128-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VUDOT_s">VUDOT (by element)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_21_simd_dotprod" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_22_simd_dotprod" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VUSDOT_s_A1_D" arch_version="FEAT_AA32I8MM" iformfile="vusdot_s.xml" label="64-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VUSDOT_s">VUSDOT (by element)</td>
          <td class="enctags">A1, 64-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSUDOT_s_A1_D" arch_version="FEAT_AA32I8MM" iformfile="vsudot_s.xml" label="64-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VSUDOT_s">VSUDOT (by element)</td>
          <td class="enctags">A1, 64-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VUSDOT_s_A1_Q" arch_version="FEAT_AA32I8MM" iformfile="vusdot_s.xml" label="128-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VUSDOT_s">VUSDOT (by element)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSUDOT_s_A1_Q" arch_version="FEAT_AA32I8MM" iformfile="vsudot_s.xml" label="128-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VSUDOT_s">VSUDOT (by element)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_27_simd_dotprod" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_28_simd_dotprod" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="floatdpmac" title="Advanced SIMD and floating-point multiply with accumulate">
    <regdiagram form="32" psname="">
      <box hibit="31" width="8" settings="8">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="23" name="op1" usename="1">
        <c></c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" name="op2" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" settings="4">
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" name="Q" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="floatdpmac" cols="6">
      <col colno="1" printwidth="5*" />
      <col colno="2" printwidth="5*" />
      <col colno="3" printwidth="3*" />
      <col colno="4" printwidth="3*" />
      <col colno="5" printwidth="36*" />
      <col colno="6" printwidth="60*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">op1</th>
          <th class="bitfields">op2</th>
          <th class="bitfields">Q</th>
          <th class="bitfields">U</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VCMLA_s_A1_QH" arch_version="FEAT_FCMA" iformfile="vcmla_s.xml" label="128-bit SIMD vector of half-precision floating-point" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCMLA_s">VCMLA (by element)</td>
          <td class="enctags">A1, 128-bit SIMD vector of half-precision floating-point</td>
        </tr>
        <tr class="instructiontable" encname="VFMAL_s_A1_Q" arch_version="FEAT_FHM" iformfile="vfmal_s.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFMAL_s">VFMAL (by scalar)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VFMSL_s_A1_Q" arch_version="FEAT_FHM" iformfile="vfmsl_s.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFMSL_s">VFMSL (by scalar)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_17_floatdpmac" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VFMA_bfs_A1_Q" arch_version="FEAT_AA32BF16" iformfile="vfma_bfs.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFMA_bfs">VFMAB, VFMAT (BFloat16, by scalar)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VCMLA_s_A1_DS" arch_version="FEAT_FCMA" iformfile="vcmla_s.xml" label="64-bit SIMD vector of single-precision floating-point" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCMLA_s">VCMLA (by element)</td>
          <td class="enctags">A1, 64-bit SIMD vector of single-precision floating-point</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_21_floatdpmac" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VCMLA_s_A1_QS" arch_version="FEAT_FCMA" iformfile="vcmla_s.xml" label="128-bit SIMD vector of single-precision floating-point" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCMLA_s">VCMLA (by element)</td>
          <td class="enctags">A1, 128-bit SIMD vector of single-precision floating-point</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="simd3reg_sameext" title="Advanced SIMD three registers of the same length extension">
    <regdiagram form="32" psname="">
      <box hibit="31" width="7" settings="7">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="24" width="2" name="op1" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" name="op2" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" settings="1">
        <c>1</c>
      </box>
      <box hibit="10" name="op3" usename="1">
        <c></c>
      </box>
      <box hibit="9" settings="1">
        <c>0</c>
      </box>
      <box hibit="8" name="op4" usename="1">
        <c></c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" name="Q" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="simd3reg_sameext" cols="8">
      <col colno="1" printwidth="5*" />
      <col colno="2" printwidth="5*" />
      <col colno="3" printwidth="5*" />
      <col colno="4" printwidth="5*" />
      <col colno="5" printwidth="3*" />
      <col colno="6" printwidth="3*" />
      <col colno="7" printwidth="33*" />
      <col colno="8" printwidth="25*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="6">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">op1</th>
          <th class="bitfields">op2</th>
          <th class="bitfields">op3</th>
          <th class="bitfields">op4</th>
          <th class="bitfields">Q</th>
          <th class="bitfields">U</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VCADD_A1_D" arch_version="FEAT_FCMA" iformfile="vcadd.xml" label="64-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">x1</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCADD">VCADD</td>
          <td class="enctags">A1, 64-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_40_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">x1</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VCADD_A1_Q" arch_version="FEAT_FCMA" iformfile="vcadd.xml" label="128-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">x1</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCADD">VCADD</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_42_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">x1</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_11_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_12_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_13_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_14_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VMMLA_A1_Q" arch_version="FEAT_AA32BF16" iformfile="vmmla.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMMLA">VMMLA</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_16_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VDOT_A1_D" arch_version="FEAT_AA32BF16" iformfile="vdot.xml" label="64-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VDOT">VDOT (vector)</td>
          <td class="enctags">A1, 64-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_18_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VDOT_A1_Q" arch_version="FEAT_AA32BF16" iformfile="vdot.xml" label="128-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VDOT">VDOT (vector)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_20_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_21_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_22_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VFMAL_A1_Q" arch_version="FEAT_FHM" iformfile="vfmal.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFMAL">VFMAL (vector)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_27_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_28_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VSMMLA_A1_Q" arch_version="FEAT_AA32I8MM" iformfile="vsmmla.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VSMMLA">VSMMLA</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VUMMLA_A1_Q" arch_version="FEAT_AA32I8MM" iformfile="vummla.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VUMMLA">VUMMLA</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VSDOT_A1_D" arch_version="FEAT_DotProd" iformfile="vsdot.xml" label="64-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VSDOT">VSDOT (vector)</td>
          <td class="enctags">A1, 64-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VUDOT_A1_D" arch_version="FEAT_DotProd" iformfile="vudot.xml" label="64-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VUDOT">VUDOT (vector)</td>
          <td class="enctags">A1, 64-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSDOT_A1_Q" arch_version="FEAT_DotProd" iformfile="vsdot.xml" label="128-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VSDOT">VSDOT (vector)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VUDOT_A1_Q" arch_version="FEAT_DotProd" iformfile="vudot.xml" label="128-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VUDOT">VUDOT (vector)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VFMA_bf_A1_Q" arch_version="FEAT_AA32BF16" iformfile="vfma_bf.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFMA_bf">VFMAB, VFMAT (BFloat16, vector)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_36_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_37_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_38_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VFMSL_A1_Q" arch_version="FEAT_FHM" iformfile="vfmsl.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFMSL">VFMSL (vector)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_45_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_46_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VUSMMLA_A1_Q" arch_version="FEAT_AA32I8MM" iformfile="vusmmla.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VUSMMLA">VUSMMLA</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_48_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VUSDOT_A1_D" arch_version="FEAT_AA32I8MM" iformfile="vusdot.xml" label="64-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VUSDOT">VUSDOT (vector)</td>
          <td class="enctags">A1, 64-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_51_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VUSDOT_A1_Q" arch_version="FEAT_AA32I8MM" iformfile="vusdot.xml" label="128-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VUSDOT">VUSDOT (vector)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_52_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_53_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_54_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VCMLA_A1_Q" arch_version="FEAT_FCMA" iformfile="vcmla.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCMLA">VCMLA</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_55_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_56_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_57_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_58_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_59_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_60_simd3reg_sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="fpcsel" title="Floating-point conditional select">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" name="cc" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
        <c colspan="2">!= 00</c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" settings="1">
        <c>0</c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="size" op="!=" val="00" />
      <decode_constraint name="size" op="!=" val="00" />
    </decode_constraints>
    <instructiontable iclass="fpcsel" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="32*" />
      <col colno="3" printwidth="43*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VSELGT_A1_H" arch_version="FEAT_FP16" iformfile="vsel.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="VSEL">VSELEQ, VSELGE, VSELGT, VSELVS</td>
          <td class="enctags">A1, Greater than, half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VSELGT_A1_S" iformfile="vsel.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="VSEL">VSELEQ, VSELGE, VSELGT, VSELVS</td>
          <td class="enctags">A1, Greater than, single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VSELGT_A1_D" iformfile="vsel.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="VSEL">VSELEQ, VSELGE, VSELGT, VSELVS</td>
          <td class="enctags">A1, Greater than, double-precision scalar</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="fpcvtrnd" title="Floating-point directed convert to integer">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="3" settings="3">
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="18" name="o1" usename="1">
        <c></c>
      </box>
      <box hibit="17" width="2" name="RM" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
        <c colspan="2">!= 00</c>
      </box>
      <box hibit="7" name="op" usename="1">
        <c></c>
      </box>
      <box hibit="6" settings="1">
        <c>1</c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="size" op="!=" val="00" />
      <decode_constraint name="size" op="!=" val="00" />
    </decode_constraints>
    <instructiontable iclass="fpcvtrnd" cols="6">
      <col colno="1" printwidth="4*" />
      <col colno="2" printwidth="4*" />
      <col colno="3" printwidth="7*" />
      <col colno="4" printwidth="4*" />
      <col colno="5" printwidth="25*" />
      <col colno="6" printwidth="29*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">o1</th>
          <th class="bitfields">RM</th>
          <th class="bitfields">size</th>
          <th class="bitfields">op</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_23_fpcvtrnd" undef="1" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">!= 00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VRINTA_vfp_A1_H" arch_version="FEAT_FP16" iformfile="vrinta_vfp.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTA_vfp">VRINTA (floating-point)</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTA_vfp_A1_S" iformfile="vrinta_vfp.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTA_vfp">VRINTA (floating-point)</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTA_vfp_A1_D" iformfile="vrinta_vfp.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTA_vfp">VRINTA (floating-point)</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTN_vfp_A1_H" arch_version="FEAT_FP16" iformfile="vrintn_vfp.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTN_vfp">VRINTN (floating-point)</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTN_vfp_A1_S" iformfile="vrintn_vfp.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTN_vfp">VRINTN (floating-point)</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTN_vfp_A1_D" iformfile="vrintn_vfp.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTN_vfp">VRINTN (floating-point)</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTP_vfp_A1_H" arch_version="FEAT_FP16" iformfile="vrintp_vfp.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTP_vfp">VRINTP (floating-point)</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTP_vfp_A1_S" iformfile="vrintp_vfp.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTP_vfp">VRINTP (floating-point)</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTP_vfp_A1_D" iformfile="vrintp_vfp.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTP_vfp">VRINTP (floating-point)</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTM_vfp_A1_H" arch_version="FEAT_FP16" iformfile="vrintm_vfp.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTM_vfp">VRINTM (floating-point)</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTM_vfp_A1_S" iformfile="vrintm_vfp.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTM_vfp">VRINTM (floating-point)</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTM_vfp_A1_D" iformfile="vrintm_vfp.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTM_vfp">VRINTM (floating-point)</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTA_vfp_A1_H" arch_version="FEAT_FP16" iformfile="vcvta_vfp.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTA_vfp">VCVTA (floating-point)</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTA_vfp_A1_S" iformfile="vcvta_vfp.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTA_vfp">VCVTA (floating-point)</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTA_vfp_A1_D" iformfile="vcvta_vfp.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTA_vfp">VCVTA (floating-point)</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTN_vfp_A1_H" arch_version="FEAT_FP16" iformfile="vcvtn_vfp.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTN_vfp">VCVTN (floating-point)</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTN_vfp_A1_S" iformfile="vcvtn_vfp.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTN_vfp">VCVTN (floating-point)</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTN_vfp_A1_D" iformfile="vcvtn_vfp.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTN_vfp">VCVTN (floating-point)</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTP_vfp_A1_H" arch_version="FEAT_FP16" iformfile="vcvtp_vfp.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTP_vfp">VCVTP (floating-point)</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTP_vfp_A1_S" iformfile="vcvtp_vfp.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTP_vfp">VCVTP (floating-point)</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTP_vfp_A1_D" iformfile="vcvtp_vfp.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTP_vfp">VCVTP (floating-point)</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTM_vfp_A1_H" arch_version="FEAT_FP16" iformfile="vcvtm_vfp.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTM_vfp">VCVTM (floating-point)</td>
          <td class="enctags">A1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTM_vfp_A1_S" iformfile="vcvtm_vfp.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTM_vfp">VCVTM (floating-point)</td>
          <td class="enctags">A1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTM_vfp_A1_D" iformfile="vcvtm_vfp.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTM_vfp">VCVTM (floating-point)</td>
          <td class="enctags">A1, Double-precision scalar</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="fpextins" title="Floating-point extraction and insertion">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="6" settings="6">
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
        <c colspan="2">!= 00</c>
      </box>
      <box hibit="7" name="op" usename="1">
        <c></c>
      </box>
      <box hibit="6" settings="1">
        <c>1</c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="size" op="!=" val="00" />
      <decode_constraint name="size" op="!=" val="00" />
    </decode_constraints>
    <instructiontable iclass="fpextins" cols="4">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="4*" />
      <col colno="3" printwidth="18*" />
      <col colno="4" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
          <th class="bitfields">op</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_fpextins" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VMOVX_A1" arch_version="FEAT_FP16" iformfile="vmovx.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMOVX">VMOVX</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VINS_A1" arch_version="FEAT_FP16" iformfile="vins.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VINS">VINS</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_14_fpextins" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="fpminmaxnm" title="Floating-point minNum/maxNum">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" settings="2">
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
        <c colspan="2">!= 00</c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" name="op" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="size" op="!=" val="00" />
      <decode_constraint name="size" op="!=" val="00" />
    </decode_constraints>
    <instructiontable iclass="fpminmaxnm" cols="4">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="4*" />
      <col colno="3" printwidth="18*" />
      <col colno="4" printwidth="29*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
          <th class="bitfields">op</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VMAXNM_A2_H" arch_version="FEAT_FP16" iformfile="vmaxnm.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMAXNM">VMAXNM</td>
          <td class="enctags">A2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMINNM_A2_H" arch_version="FEAT_FP16" iformfile="vminnm.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMINNM">VMINNM</td>
          <td class="enctags">A2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMAXNM_A2_S" iformfile="vmaxnm.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMAXNM">VMAXNM</td>
          <td class="enctags">A2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMINNM_A2_S" iformfile="vminnm.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMINNM">VMINNM</td>
          <td class="enctags">A2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMAXNM_A2_D" iformfile="vmaxnm.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMAXNM">VMAXNM</td>
          <td class="enctags">A2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMINNM_A2_D" iformfile="vminnm.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMINNM">VMINNM</td>
          <td class="enctags">A2, Double-precision scalar</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="svcall">Supervisor call</funcgroupheader>
  <iclass_sect id="svc" title="Supervisor Call">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="27" width="4" settings="4">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="23" width="24" name="imm24" usename="1">
        <c colspan="24"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond" op="!=" val="1111" />
      <decode_constraint name="cond" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="svc" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="SVC_A1" iformfile="svc.xml" first="t" last="t">
          <td class="iformname" iformid="SVC">SVC</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="uncondmisc">Miscellaneous</funcgroupheader>
  <iclass_sect id="cps" title="Change Process State">
    <regdiagram form="32" psname="">
      <box hibit="31" width="12" settings="12">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="19" width="2" name="imod" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="17" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="16" name="op" usename="1">
        <c></c>
      </box>
      <box hibit="15" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="14" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="13" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="12" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="11" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="10" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="9" name="E" usename="1">
        <c></c>
      </box>
      <box hibit="8" name="A" usename="1">
        <c></c>
      </box>
      <box hibit="7" name="I" usename="1">
        <c></c>
      </box>
      <box hibit="6" name="F" usename="1">
        <c></c>
      </box>
      <box hibit="5" settings="1">
        <c>0</c>
      </box>
      <box hibit="4" width="5" name="mode" usename="1">
        <c colspan="5"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="cps" cols="8">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="4*" />
      <col colno="4" printwidth="3*" />
      <col colno="5" printwidth="3*" />
      <col colno="6" printwidth="7*" />
      <col colno="7" printwidth="19*" />
      <col colno="8" printwidth="39*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="6">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">imod</th>
          <th class="bitfields">M</th>
          <th class="bitfields">op</th>
          <th class="bitfields">I</th>
          <th class="bitfields">F</th>
          <th class="bitfields">mode</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="SETEND_A1" iformfile="setend.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="5" class="bitfield">0xxxx</td>
          <td class="iformname" iformid="SETEND">SETEND</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="CPS_A1_AS" iformfile="cps.xml" label="change mode" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="5" class="bitfield"></td>
          <td class="iformname" iformid="CPS">CPS, CPSID, CPSIE</td>
          <td class="enctags">A1, Change mode</td>
        </tr>
        <tr class="instructiontable" encname="CPSIE_A1_ASM" iformfile="cps.xml" label="interrupt enable and change mode" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="5" class="bitfield"></td>
          <td class="iformname" iformid="CPS">CPS, CPSID, CPSIE</td>
          <td class="enctags">A1, Interrupt enable and change mode</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_17_cps" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="5" class="bitfield">1xxxx</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_18_cps" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="5" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_19_cps" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="5" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="CPSID_A1_ASM" iformfile="cps.xml" label="interrupt disable and change mode" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="5" class="bitfield"></td>
          <td class="iformname" iformid="CPS">CPS, CPSID, CPSIE</td>
          <td class="enctags">A1, Interrupt disable and change mode</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="setpan" title="SETPAN">
    <regdiagram form="32" psname="">
      <box hibit="31" width="12" settings="12">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="19" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="18" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="17" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="16" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="15" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="14" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="13" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="12" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="11" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="10" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="9" name="imm1" usename="1">
        <c></c>
      </box>
      <box hibit="8" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="7" width="4" settings="4">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="3" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="2" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="1" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="0" settings="1">
        <c>(0)</c>
      </box>
    </regdiagram>
    <instructiontable iclass="setpan" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="SETPAN_A1" arch_version="FEAT_PAN" iformfile="setpan.xml" first="t" last="t">
          <td class="iformname" iformid="SETPAN">SETPAN</td>
          <td class="enctags">A1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="uncondhints">Memory hints and barriers</funcgroupheader>
  <iclass_sect id="barriers" title="Barriers">
    <regdiagram form="32" psname="">
      <box hibit="31" width="12" settings="12">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="19" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="18" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="17" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="16" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="15" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="14" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="13" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="12" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="11" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="10" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="9" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="8" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="7" width="4" name="opcode" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="3" width="4" name="option" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="barriers" cols="4">
      <col colno="1" printwidth="8*" />
      <col colno="2" printwidth="9*" />
      <col colno="3" printwidth="18*" />
      <col colno="4" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">opcode</th>
          <th class="bitfields">option</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNPREDICTABLE_11_barriers" unpred="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNPREDICTABLE</td>
        </tr>
        <tr class="instructiontable" encname="CLREX_A1" iformfile="clrex.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="CLREX">CLREX</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNPREDICTABLE_13_barriers" unpred="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">001x</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNPREDICTABLE</td>
        </tr>
        <tr class="instructiontable" encname="DSB_A1" iformfile="dsb.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="4" class="bitfield">!= 0x00</td>
          <td class="iformname" iformid="DSB">DSB</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="SSBB_A1" iformfile="ssbb.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="4" class="bitfield">0000</td>
          <td class="iformname" iformid="SSBB">SSBB</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="PSSBB_A1" iformfile="pssbb.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="4" class="bitfield">0100</td>
          <td class="iformname" iformid="PSSBB">PSSBB</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="DMB_A1" iformfile="dmb.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="DMB">DMB</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="ISB_A1" iformfile="isb.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ISB">ISB</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="SB_A1" arch_version="FEAT_SB" iformfile="sb.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="SB">SB</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNPREDICTABLE_20_barriers" unpred="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">1xxx</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNPREDICTABLE</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="preload_imm" title="Preload (immediate)">
    <regdiagram form="32" psname="">
      <box hibit="31" width="7" settings="7">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="24" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="23" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="22" name="R" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" settings="2">
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="14" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="13" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="12" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="11" width="12" name="imm12" usename="1">
        <c colspan="12"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="preload_imm" cols="5">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="9*" />
      <col colno="4" printwidth="31*" />
      <col colno="5" printwidth="19*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">D</th>
          <th class="bitfields">R</th>
          <th class="bitfields">Rn</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="RESERVED_nop_hint_11_preload_imm" reserved_nop_hint="1" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="PLI_i_A1" iformfile="pli_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="PLI_i">PLI (immediate, literal)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="PLD_l_A1" iformfile="pld_l.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="PLD_l">PLD (literal)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="PLDW_i_A1" iformfile="pld_i.xml" label="preload write" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="PLD_i">PLD, PLDW (immediate)</td>
          <td class="enctags">A1, Preload write</td>
        </tr>
        <tr class="instructiontable" encname="PLD_i_A1" iformfile="pld_i.xml" label="preload read" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="PLD_i">PLD, PLDW (immediate)</td>
          <td class="enctags">A1, Preload read</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="preload_reg" title="Preload (register)">
    <regdiagram form="32" psname="">
      <box hibit="31" width="7" settings="7">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="24" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="23" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="22" name="o2" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" settings="2">
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="14" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="13" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="12" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="11" width="5" name="imm5" usename="1">
        <c colspan="5"></c>
      </box>
      <box hibit="6" width="2" name="stype" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="preload_reg" cols="5">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="4*" />
      <col colno="3" printwidth="12*" />
      <col colno="4" printwidth="31*" />
      <col colno="5" printwidth="45*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">D</th>
          <th class="bitfields">o2</th>
          <th class="bitfields">imm5:stype</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="RESERVED_nop_hint_11_preload_reg" reserved_nop_hint="1" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="7" class="bitfield"></td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="PLI_r_A1" iformfile="pli_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="PLI_r">PLI (register)</td>
          <td class="enctags">A1, Shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="PLI_r_A1_RRX" iformfile="pli_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="PLI_r">PLI (register)</td>
          <td class="enctags">A1, Rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="PLDW_r_A1" iformfile="pld_r.xml" label="preload write, optional shift or rotate" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="PLD_r">PLD, PLDW (register)</td>
          <td class="enctags">A1, Preload write, optional shift or rotate</td>
        </tr>
        <tr class="instructiontable" encname="PLDW_r_A1_RRX" iformfile="pld_r.xml" label="preload write, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="PLD_r">PLD, PLDW (register)</td>
          <td class="enctags">A1, Preload write, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="PLD_r_A1" iformfile="pld_r.xml" label="preload read, optional shift or rotate" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="7" class="bitfield">!= 0000011</td>
          <td class="iformname" iformid="PLD_r">PLD, PLDW (register)</td>
          <td class="enctags">A1, Preload read, optional shift or rotate</td>
        </tr>
        <tr class="instructiontable" encname="PLD_r_A1_RRX" iformfile="pld_r.xml" label="preload read, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="7" class="bitfield">0000011</td>
          <td class="iformname" iformid="PLD_r">PLD, PLDW (register)</td>
          <td class="enctags">A1, Preload read, rotate right with extend</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="advsimdls">Advanced SIMD element or structure load/store</funcgroupheader>
  <iclass_sect id="ldv_ssall" title="Advanced SIMD load single structure to all lanes">
    <regdiagram form="32" psname="">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="20" settings="1">
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="9" width="2" name="N" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="7" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="5" name="T" usename="1">
        <c></c>
      </box>
      <box hibit="4" name="a" usename="1">
        <c></c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="ldv_ssall" cols="6">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="4*" />
      <col colno="3" printwidth="3*" />
      <col colno="4" printwidth="9*" />
      <col colno="5" printwidth="48*" />
      <col colno="6" printwidth="18*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
          <th class="bitfields">N</th>
          <th class="bitfields">a</th>
          <th class="bitfields">Rm</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_ldv_ssall" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_a_A1_postr" iformfile="vld1_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD1_a">VLD1 (single element to all lanes)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_a_A1_posti" iformfile="vld1_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD1_a">VLD1 (single element to all lanes)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_a_A1_nowb" iformfile="vld1_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD1_a">VLD1 (single element to all lanes)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_a_A1_postr" iformfile="vld2_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD2_a">VLD2 (single 2-element structure to all lanes)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_a_A1_posti" iformfile="vld2_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD2_a">VLD2 (single 2-element structure to all lanes)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_a_A1_nowb" iformfile="vld2_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD2_a">VLD2 (single 2-element structure to all lanes)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_a_A1_postr" iformfile="vld3_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD3_a">VLD3 (single 3-element structure to all lanes)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_a_A1_posti" iformfile="vld3_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD3_a">VLD3 (single 3-element structure to all lanes)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_a_A1_nowb" iformfile="vld3_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD3_a">VLD3 (single 3-element structure to all lanes)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_12_ldv_ssall" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_a_A1_postr" iformfile="vld4_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD4_a">VLD4 (single 4-element structure to all lanes)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_a_A1_posti" iformfile="vld4_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD4_a">VLD4 (single 4-element structure to all lanes)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_a_A1_nowb" iformfile="vld4_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD4_a">VLD4 (single 4-element structure to all lanes)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldstv_ms" title="Advanced SIMD load/store multiple structures">
    <regdiagram form="32" psname="">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="20" settings="1">
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="itype" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="5" width="2" name="align" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="ldstv_ms" cols="5">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="7*" />
      <col colno="3" printwidth="9*" />
      <col colno="4" printwidth="38*" />
      <col colno="5" printwidth="18*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
          <th class="bitfields">itype</th>
          <th class="bitfields">Rm</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VST4_m_A1_postr" iformfile="vst4_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">000x</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST4_m">VST4 (multiple 4-element structures)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST4_m_A1_posti" iformfile="vst4_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">000x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST4_m">VST4 (multiple 4-element structures)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST4_m_A1_nowb" iformfile="vst4_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">000x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST4_m">VST4 (multiple 4-element structures)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_A4_postr" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">A4, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_A4_posti" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">A4, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_A4_nowb" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">A4, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST2_m_A2_postr" iformfile="vst2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST2_m">VST2 (multiple 2-element structures)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST2_m_A2_posti" iformfile="vst2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST2_m">VST2 (multiple 2-element structures)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST2_m_A2_nowb" iformfile="vst2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST2_m">VST2 (multiple 2-element structures)</td>
          <td class="enctags">A2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST3_m_A1_postr" iformfile="vst3_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">010x</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST3_m">VST3 (multiple 3-element structures)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST3_m_A1_posti" iformfile="vst3_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">010x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST3_m">VST3 (multiple 3-element structures)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST3_m_A1_nowb" iformfile="vst3_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">010x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST3_m">VST3 (multiple 3-element structures)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_A3_postr" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">A3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_A3_posti" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">A3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_A3_nowb" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">A3, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_A1_postr" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_A1_posti" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_A1_nowb" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST2_m_A1_postr" iformfile="vst2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">100x</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST2_m">VST2 (multiple 2-element structures)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST2_m_A1_posti" iformfile="vst2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">100x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST2_m">VST2 (multiple 2-element structures)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST2_m_A1_nowb" iformfile="vst2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">100x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST2_m">VST2 (multiple 2-element structures)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_A2_postr" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_A2_posti" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_A2_nowb" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">A2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_m_A1_postr" iformfile="vld4_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">000x</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD4_m">VLD4 (multiple 4-element structures)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_m_A1_posti" iformfile="vld4_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">000x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD4_m">VLD4 (multiple 4-element structures)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_m_A1_nowb" iformfile="vld4_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">000x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD4_m">VLD4 (multiple 4-element structures)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_A4_postr" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">A4, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_A4_posti" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">A4, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_A4_nowb" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">A4, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_m_A2_postr" iformfile="vld2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD2_m">VLD2 (multiple 2-element structures)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_m_A2_posti" iformfile="vld2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD2_m">VLD2 (multiple 2-element structures)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_m_A2_nowb" iformfile="vld2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD2_m">VLD2 (multiple 2-element structures)</td>
          <td class="enctags">A2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_m_A1_postr" iformfile="vld3_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">010x</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD3_m">VLD3 (multiple 3-element structures)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_m_A1_posti" iformfile="vld3_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">010x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD3_m">VLD3 (multiple 3-element structures)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_m_A1_nowb" iformfile="vld3_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">010x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD3_m">VLD3 (multiple 3-element structures)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_59_ldstv_ms" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_A3_postr" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">A3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_A3_posti" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">A3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_A3_nowb" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">A3, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_A1_postr" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_A1_posti" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_A1_nowb" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_60_ldstv_ms" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">11xx</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_m_A1_postr" iformfile="vld2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">100x</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD2_m">VLD2 (multiple 2-element structures)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_m_A1_posti" iformfile="vld2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">100x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD2_m">VLD2 (multiple 2-element structures)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_m_A1_nowb" iformfile="vld2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">100x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD2_m">VLD2 (multiple 2-element structures)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_A2_postr" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_A2_posti" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_A2_nowb" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">A2, Offset</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldstv_ssone" title="Advanced SIMD load/store single structure to one lane">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="20" settings="1">
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" name="size" usename="1" settings="2" constraint="!= 11">
        <c colspan="2">!= 11</c>
      </box>
      <box hibit="9" width="2" name="N" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="7" width="4" name="index_align" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="size" op="!=" val="11" />
      <decode_constraint name="size" op="!=" val="11" />
    </decode_constraints>
    <instructiontable iclass="ldstv_ssone" cols="6">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="6*" />
      <col colno="3" printwidth="4*" />
      <col colno="4" printwidth="9*" />
      <col colno="5" printwidth="49*" />
      <col colno="6" printwidth="18*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
          <th class="bitfields">size</th>
          <th class="bitfields">N</th>
          <th class="bitfields">Rm</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VST1_1_A1_postr" iformfile="vst1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST1_1">VST1 (single element from one lane)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_1_A1_posti" iformfile="vst1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST1_1">VST1 (single element from one lane)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_1_A1_nowb" iformfile="vst1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST1_1">VST1 (single element from one lane)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST2_1_A1_postr" iformfile="vst2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST2_1">VST2 (single 2-element structure from one lane)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST2_1_A1_posti" iformfile="vst2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST2_1">VST2 (single 2-element structure from one lane)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST2_1_A1_nowb" iformfile="vst2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST2_1">VST2 (single 2-element structure from one lane)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST3_1_A1_postr" iformfile="vst3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST3_1">VST3 (single 3-element structure from one lane)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST3_1_A1_posti" iformfile="vst3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST3_1">VST3 (single 3-element structure from one lane)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST3_1_A1_nowb" iformfile="vst3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST3_1">VST3 (single 3-element structure from one lane)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST4_1_A1_postr" iformfile="vst4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST4_1">VST4 (single 4-element structure from one lane)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST4_1_A1_posti" iformfile="vst4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST4_1">VST4 (single 4-element structure from one lane)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST4_1_A1_nowb" iformfile="vst4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST4_1">VST4 (single 4-element structure from one lane)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST1_1_A2_postr" iformfile="vst1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST1_1">VST1 (single element from one lane)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_1_A2_posti" iformfile="vst1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST1_1">VST1 (single element from one lane)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_1_A2_nowb" iformfile="vst1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST1_1">VST1 (single element from one lane)</td>
          <td class="enctags">A2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST2_1_A2_postr" iformfile="vst2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST2_1">VST2 (single 2-element structure from one lane)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST2_1_A2_posti" iformfile="vst2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST2_1">VST2 (single 2-element structure from one lane)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST2_1_A2_nowb" iformfile="vst2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST2_1">VST2 (single 2-element structure from one lane)</td>
          <td class="enctags">A2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST3_1_A2_postr" iformfile="vst3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST3_1">VST3 (single 3-element structure from one lane)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST3_1_A2_posti" iformfile="vst3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST3_1">VST3 (single 3-element structure from one lane)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST3_1_A2_nowb" iformfile="vst3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST3_1">VST3 (single 3-element structure from one lane)</td>
          <td class="enctags">A2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST4_1_A2_postr" iformfile="vst4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST4_1">VST4 (single 4-element structure from one lane)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST4_1_A2_posti" iformfile="vst4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST4_1">VST4 (single 4-element structure from one lane)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST4_1_A2_nowb" iformfile="vst4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST4_1">VST4 (single 4-element structure from one lane)</td>
          <td class="enctags">A2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST1_1_A3_postr" iformfile="vst1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST1_1">VST1 (single element from one lane)</td>
          <td class="enctags">A3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_1_A3_posti" iformfile="vst1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST1_1">VST1 (single element from one lane)</td>
          <td class="enctags">A3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_1_A3_nowb" iformfile="vst1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST1_1">VST1 (single element from one lane)</td>
          <td class="enctags">A3, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST2_1_A3_postr" iformfile="vst2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST2_1">VST2 (single 2-element structure from one lane)</td>
          <td class="enctags">A3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST2_1_A3_posti" iformfile="vst2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST2_1">VST2 (single 2-element structure from one lane)</td>
          <td class="enctags">A3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST2_1_A3_nowb" iformfile="vst2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST2_1">VST2 (single 2-element structure from one lane)</td>
          <td class="enctags">A3, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST3_1_A3_postr" iformfile="vst3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST3_1">VST3 (single 3-element structure from one lane)</td>
          <td class="enctags">A3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST3_1_A3_posti" iformfile="vst3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST3_1">VST3 (single 3-element structure from one lane)</td>
          <td class="enctags">A3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST3_1_A3_nowb" iformfile="vst3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST3_1">VST3 (single 3-element structure from one lane)</td>
          <td class="enctags">A3, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST4_1_A3_postr" iformfile="vst4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST4_1">VST4 (single 4-element structure from one lane)</td>
          <td class="enctags">A3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST4_1_A3_posti" iformfile="vst4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST4_1">VST4 (single 4-element structure from one lane)</td>
          <td class="enctags">A3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST4_1_A3_nowb" iformfile="vst4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST4_1">VST4 (single 4-element structure from one lane)</td>
          <td class="enctags">A3, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_1_A1_postr" iformfile="vld1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD1_1">VLD1 (single element to one lane)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_1_A1_posti" iformfile="vld1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD1_1">VLD1 (single element to one lane)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_1_A1_nowb" iformfile="vld1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD1_1">VLD1 (single element to one lane)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_1_A1_postr" iformfile="vld2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD2_1">VLD2 (single 2-element structure to one lane)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_1_A1_posti" iformfile="vld2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD2_1">VLD2 (single 2-element structure to one lane)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_1_A1_nowb" iformfile="vld2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD2_1">VLD2 (single 2-element structure to one lane)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_1_A1_postr" iformfile="vld3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD3_1">VLD3 (single 3-element structure to one lane)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_1_A1_posti" iformfile="vld3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD3_1">VLD3 (single 3-element structure to one lane)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_1_A1_nowb" iformfile="vld3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD3_1">VLD3 (single 3-element structure to one lane)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_1_A1_postr" iformfile="vld4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD4_1">VLD4 (single 4-element structure to one lane)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_1_A1_posti" iformfile="vld4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD4_1">VLD4 (single 4-element structure to one lane)</td>
          <td class="enctags">A1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_1_A1_nowb" iformfile="vld4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD4_1">VLD4 (single 4-element structure to one lane)</td>
          <td class="enctags">A1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_1_A2_postr" iformfile="vld1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD1_1">VLD1 (single element to one lane)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_1_A2_posti" iformfile="vld1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD1_1">VLD1 (single element to one lane)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_1_A2_nowb" iformfile="vld1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD1_1">VLD1 (single element to one lane)</td>
          <td class="enctags">A2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_1_A2_postr" iformfile="vld2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD2_1">VLD2 (single 2-element structure to one lane)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_1_A2_posti" iformfile="vld2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD2_1">VLD2 (single 2-element structure to one lane)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_1_A2_nowb" iformfile="vld2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD2_1">VLD2 (single 2-element structure to one lane)</td>
          <td class="enctags">A2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_1_A2_postr" iformfile="vld3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD3_1">VLD3 (single 3-element structure to one lane)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_1_A2_posti" iformfile="vld3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD3_1">VLD3 (single 3-element structure to one lane)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_1_A2_nowb" iformfile="vld3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD3_1">VLD3 (single 3-element structure to one lane)</td>
          <td class="enctags">A2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_1_A2_postr" iformfile="vld4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD4_1">VLD4 (single 4-element structure to one lane)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_1_A2_posti" iformfile="vld4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD4_1">VLD4 (single 4-element structure to one lane)</td>
          <td class="enctags">A2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_1_A2_nowb" iformfile="vld4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD4_1">VLD4 (single 4-element structure to one lane)</td>
          <td class="enctags">A2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_1_A3_postr" iformfile="vld1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD1_1">VLD1 (single element to one lane)</td>
          <td class="enctags">A3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_1_A3_posti" iformfile="vld1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD1_1">VLD1 (single element to one lane)</td>
          <td class="enctags">A3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_1_A3_nowb" iformfile="vld1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD1_1">VLD1 (single element to one lane)</td>
          <td class="enctags">A3, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_1_A3_postr" iformfile="vld2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD2_1">VLD2 (single 2-element structure to one lane)</td>
          <td class="enctags">A3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_1_A3_posti" iformfile="vld2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD2_1">VLD2 (single 2-element structure to one lane)</td>
          <td class="enctags">A3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_1_A3_nowb" iformfile="vld2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD2_1">VLD2 (single 2-element structure to one lane)</td>
          <td class="enctags">A3, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_1_A3_postr" iformfile="vld3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD3_1">VLD3 (single 3-element structure to one lane)</td>
          <td class="enctags">A3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_1_A3_posti" iformfile="vld3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD3_1">VLD3 (single 3-element structure to one lane)</td>
          <td class="enctags">A3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_1_A3_nowb" iformfile="vld3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD3_1">VLD3 (single 3-element structure to one lane)</td>
          <td class="enctags">A3, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_1_A3_postr" iformfile="vld4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD4_1">VLD4 (single 4-element structure to one lane)</td>
          <td class="enctags">A3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_1_A3_posti" iformfile="vld4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD4_1">VLD4 (single 4-element structure to one lane)</td>
          <td class="enctags">A3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_1_A3_nowb" iformfile="vld4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD4_1">VLD4 (single 4-element structure to one lane)</td>
          <td class="enctags">A3, Offset</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="a_simd3reg_same">Advanced SIMD three registers of the same length</funcgroupheader>
  <iclass_sect id="simd3reg_same" title="Advanced SIMD three registers of the same length">
    <regdiagram form="32" psname="">
      <box hibit="31" width="7" settings="7">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="24" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="23" settings="1">
        <c>0</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="opc" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" name="Q" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" name="o1" usename="1">
        <c></c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="simd3reg_same" cols="7">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="6*" />
      <col colno="3" printwidth="6*" />
      <col colno="4" printwidth="3*" />
      <col colno="5" printwidth="4*" />
      <col colno="6" printwidth="31*" />
      <col colno="7" printwidth="25*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">U</th>
          <th class="bitfields">size</th>
          <th class="bitfields">opc</th>
          <th class="bitfields">Q</th>
          <th class="bitfields">o1</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VFMA_A1_Q" iformfile="vfma.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFMA">VFMA</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VADD_f_A1_Q" iformfile="vadd_f.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VADD_f">VADD (floating-point)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VMLA_f_A1_Q" iformfile="vmla_f.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMLA_f">VMLA (floating-point)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="a2" iformfile="vceq_r.xml" label="A2" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCEQ_r">VCEQ (register)</td>
          <td class="enctags">A2, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VMAX_f_A1_Q" iformfile="vmax_f.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMAX_f">VMAX (floating-point)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VRECPS_A1_Q" iformfile="vrecps.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VRECPS">VRECPS</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VHADD_A1_Q" iformfile="vhadd.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VHADD">VHADD</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VAND_r_A1_Q" iformfile="vand_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VAND_r">VAND (register)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQADD_A1_Q" iformfile="vqadd.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VQADD">VQADD</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VRHADD_A1_Q" iformfile="vrhadd.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRHADD">VRHADD</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="SHA1C_A1" arch_version="FEAT_SHA1" iformfile="sha1c.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SHA1C">SHA1C</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VHSUB_A1_Q" iformfile="vhsub.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VHSUB">VHSUB</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VBIC_r_A1_Q" iformfile="vbic_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VBIC_r">VBIC (register)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQSUB_A1_Q" iformfile="vqsub.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VQSUB">VQSUB</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="a1" iformfile="vcgt_r.xml" label="A1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCGT_r">VCGT (register)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="a1" iformfile="vcge_r.xml" label="A1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCGE_r">VCGE (register)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="SHA1P_A1" arch_version="FEAT_SHA1" iformfile="sha1p.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SHA1P">SHA1P</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VFMS_A1_Q" iformfile="vfms.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFMS">VFMS</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSUB_f_A1_Q" iformfile="vsub_f.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VSUB_f">VSUB (floating-point)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VMLS_f_A1_Q" iformfile="vmls_f.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMLS_f">VMLS (floating-point)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_109_simd3reg_same" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VMIN_f_A1_Q" iformfile="vmin_f.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMIN_f">VMIN (floating-point)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VRSQRTS_A1_Q" iformfile="vrsqrts.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VRSQRTS">VRSQRTS</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSHL_r_A1_Q" iformfile="vshl_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VSHL_r">VSHL (register)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VADD_i_A1_Q" iformfile="vadd_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VADD_i">VADD (integer)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VORR_r_A1_Q" iformfile="vorr_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VORR_r">VORR (register)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VTST_A1_Q" iformfile="vtst.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VTST">VTST</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQSHL_r_A1_Q" iformfile="vqshl_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VQSHL_r">VQSHL (register)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VMLA_i_A1_Q" iformfile="vmla_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMLA_i">VMLA (integer)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VRSHL_A1_Q" iformfile="vrshl.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRSHL">VRSHL</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQRSHL_A1_Q" iformfile="vqrshl.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VQRSHL">VQRSHL</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQDMULH_A1_Q" iformfile="vqdmulh.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VQDMULH">VQDMULH</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="SHA1M_A1" arch_version="FEAT_SHA1" iformfile="sha1m.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SHA1M">SHA1M</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VPADD_i_A1" iformfile="vpadd_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VPADD_i">VPADD (integer)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VMAX_i_A1_Q" iformfile="vmax_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMAX_i">VMAX (integer)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VORN_r_A1_Q" iformfile="vorn_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VORN_r">VORN (register)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VMIN_i_A1_Q" iformfile="vmin_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMIN_i">VMIN (integer)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VABD_i_A1_Q" iformfile="vabd_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VABD_i">VABD (integer)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VABA_A1_Q" iformfile="vaba.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VABA">VABA</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="SHA1SU0_A1" arch_version="FEAT_SHA1" iformfile="sha1su0.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SHA1SU0">SHA1SU0</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VPADD_f_A1" iformfile="vpadd_f.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VPADD_f">VPADD (floating-point)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VMUL_f_A1_Q" iformfile="vmul_f.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMUL_f">VMUL (floating-point)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="a2" iformfile="vcge_r.xml" label="A2" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCGE_r">VCGE (register)</td>
          <td class="enctags">A2, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VACGE_A1_Q" iformfile="vacge.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VACGE">VACGE</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VPMAX_f_A1" iformfile="vpmax_f.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VPMAX_f">VPMAX (floating-point)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VMAXNM_A1_Q" iformfile="vmaxnm.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMAXNM">VMAXNM</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VEOR_A1_Q" iformfile="veor.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VEOR">VEOR</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VMUL_i_A1_Q" iformfile="vmul_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMUL_i">VMUL (integer and polynomial)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="SHA256H_A1" arch_version="FEAT_SHA256" iformfile="sha256h.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SHA256H">SHA256H</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VPMAX_i_A1" iformfile="vpmax_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VPMAX_i">VPMAX (integer)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VBSL_A1_Q" iformfile="vbsl.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VBSL">VBSL</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VPMIN_i_A1" iformfile="vpmin_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VPMIN_i">VPMIN (integer)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_65_simd3reg_same" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SHA256H2_A1" arch_version="FEAT_SHA256" iformfile="sha256h2.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SHA256H2">SHA256H2</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VABD_f_A1_Q" iformfile="vabd_f.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VABD_f">VABD (floating-point)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="a2" iformfile="vcgt_r.xml" label="A2" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCGT_r">VCGT (register)</td>
          <td class="enctags">A2, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VACGT_A1_Q" iformfile="vacgt.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VACGT">VACGT</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VPMIN_f_A1" iformfile="vpmin_f.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VPMIN_f">VPMIN (floating-point)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VMINNM_A1_Q" iformfile="vminnm.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMINNM">VMINNM</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSUB_i_A1_Q" iformfile="vsub_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VSUB_i">VSUB (integer)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VBIT_A1_Q" iformfile="vbit.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VBIT">VBIT</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="a1" iformfile="vceq_r.xml" label="A1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCEQ_r">VCEQ (register)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VMLS_i_A1_Q" iformfile="vmls_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMLS_i">VMLS (integer)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQRDMULH_A1_Q" iformfile="vqrdmulh.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VQRDMULH">VQRDMULH</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="SHA256SU1_A1" arch_version="FEAT_SHA256" iformfile="sha256su1.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SHA256SU1">SHA256SU1</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VQRDMLAH_A1_Q" arch_version="FEAT_RDM" iformfile="vqrdmlah.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VQRDMLAH">VQRDMLAH</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VBIF_A1_Q" iformfile="vbif.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VBIF">VBIF</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQRDMLSH_A1_Q" arch_version="FEAT_RDM" iformfile="vqrdmlsh.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VQRDMLSH">VQRDMLSH</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_124_simd3reg_same" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="a_simd_mulreg">Advanced SIMD two registers, or three registers of different lengths</funcgroupheader>
  <iclass_sect id="simd2reg_dup" title="Advanced SIMD duplicate (scalar)">
    <regdiagram form="32" psname="">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="19" width="4" name="imm4" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="9" width="3" name="opc" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="6" name="Q" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="simd2reg_dup" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">opc</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VDUP_s_A1_Q" iformfile="vdup_s.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td class="iformname" iformid="VDUP_s">VDUP (scalar)</td>
          <td class="enctags">A1, </td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_13_simd2reg_dup" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_14_simd2reg_dup" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="3" class="bitfield">01x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_15_simd2reg_dup" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="3" class="bitfield">1xx</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="simd3reg_tbl" title="Advanced SIMD table permute">
    <regdiagram form="32" psname="">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="9" width="2" name="len" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" name="op" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="simd3reg_tbl" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VTBX_A1" iformfile="vtbl.xml" first="t" last="t">
          <td class="iformname" iformid="VTBL">VTBL, VTBX</td>
          <td class="enctags">A1, VTBX</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="simd3reg_diff" title="Advanced SIMD three registers of different lengths">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="7" settings="7">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="24" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="23" settings="1">
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
        <c colspan="2">!= 11</c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="opc" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" settings="1">
        <c>0</c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="size" op="!=" val="11" />
      <decode_constraint name="size" op="!=" val="11" />
    </decode_constraints>
    <instructiontable iclass="simd3reg_diff" cols="4">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="6*" />
      <col colno="3" printwidth="32*" />
      <col colno="4" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">U</th>
          <th class="bitfields">opc</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VADDL_A1" iformfile="vaddl.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0000</td>
          <td class="iformname" iformid="VADDL">VADDL</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VADDW_A1" iformfile="vaddw.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td class="iformname" iformid="VADDW">VADDW</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VSUBL_A1" iformfile="vsubl.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td class="iformname" iformid="VSUBL">VSUBL</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VADDHN_A1" iformfile="vaddhn.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0100</td>
          <td class="iformname" iformid="VADDHN">VADDHN</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VSUBW_A1" iformfile="vsubw.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td class="iformname" iformid="VSUBW">VSUBW</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VSUBHN_A1" iformfile="vsubhn.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td class="iformname" iformid="VSUBHN">VSUBHN</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VQDMLAL_A1" iformfile="vqdmlal.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1001</td>
          <td class="iformname" iformid="VQDMLAL">VQDMLAL</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VABAL_A1" iformfile="vabal.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td class="iformname" iformid="VABAL">VABAL</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VQDMLSL_A1" iformfile="vqdmlsl.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td class="iformname" iformid="VQDMLSL">VQDMLSL</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VQDMULL_A1" iformfile="vqdmull.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VQDMULL">VQDMULL</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VABDL_i_A1" iformfile="vabdl_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td class="iformname" iformid="VABDL_i">VABDL (integer)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VMLAL_i_A1" iformfile="vmlal_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td class="iformname" iformid="VMLAL_i">VMLAL (integer)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VMLSL_i_A1" iformfile="vmlsl_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td class="iformname" iformid="VMLSL_i">VMLSL (integer)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VRADDHN_A1" iformfile="vraddhn.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0100</td>
          <td class="iformname" iformid="VRADDHN">VRADDHN</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VRSUBHN_A1" iformfile="vrsubhn.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td class="iformname" iformid="VRSUBHN">VRSUBHN</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VMULL_i_A1" iformfile="vmull_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">11x0</td>
          <td class="iformname" iformid="VMULL_i">VMULL (integer and polynomial)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_23_simd3reg_diff" undef="1" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1001</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_26_simd3reg_diff" undef="1" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_29_simd3reg_diff" undef="1" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_30_simd3reg_diff" undef="1" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="simd2reg_scalar" title="Advanced SIMD two registers and a scalar">
    <regdiagram form="32" psname="" tworows="1">
      <box hibit="31" width="7" settings="7">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="24" name="Q" usename="1">
        <c></c>
      </box>
      <box hibit="23" settings="1">
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
        <c colspan="2">!= 11</c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="opc" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" settings="1">
        <c>1</c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="size" op="!=" val="11" />
      <decode_constraint name="size" op="!=" val="11" />
    </decode_constraints>
    <instructiontable iclass="simd2reg_scalar" cols="4">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="6*" />
      <col colno="3" printwidth="19*" />
      <col colno="4" printwidth="25*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">Q</th>
          <th class="bitfields">opc</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VMLA_s_A1_Q" iformfile="vmla_s.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">000x</td>
          <td class="iformname" iformid="VMLA_s">VMLA (by scalar)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQDMLAL_A2" iformfile="vqdmlal.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td class="iformname" iformid="VQDMLAL">VQDMLAL</td>
          <td class="enctags">A2</td>
        </tr>
        <tr class="instructiontable" encname="VMLAL_s_A1" iformfile="vmlal_s.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td class="iformname" iformid="VMLAL_s">VMLAL (by scalar)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VQDMLSL_A2" iformfile="vqdmlsl.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td class="iformname" iformid="VQDMLSL">VQDMLSL</td>
          <td class="enctags">A2</td>
        </tr>
        <tr class="instructiontable" encname="VMLS_s_A1_Q" iformfile="vmls_s.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">010x</td>
          <td class="iformname" iformid="VMLS_s">VMLS (by scalar)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQDMULL_A2" iformfile="vqdmull.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td class="iformname" iformid="VQDMULL">VQDMULL</td>
          <td class="enctags">A2</td>
        </tr>
        <tr class="instructiontable" encname="VMLSL_s_A1" iformfile="vmlsl_s.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td class="iformname" iformid="VMLSL_s">VMLSL (by scalar)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VMUL_s_A1_Q" iformfile="vmul_s.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">100x</td>
          <td class="iformname" iformid="VMUL_s">VMUL (by scalar)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_15_simd2reg_scalar" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VMULL_s_A1" iformfile="vmull_s.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td class="iformname" iformid="VMULL_s">VMULL (by scalar)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_20_simd2reg_scalar" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VQDMULH_A2_Q" iformfile="vqdmulh.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td class="iformname" iformid="VQDMULH">VQDMULH</td>
          <td class="enctags">A2, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQRDMULH_A2_Q" iformfile="vqrdmulh.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VQRDMULH">VQRDMULH</td>
          <td class="enctags">A2, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_25_simd2reg_scalar" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VQRDMLAH_A2_Q" arch_version="FEAT_RDM" iformfile="vqrdmlah.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1110</td>
          <td class="iformname" iformid="VQRDMLAH">VQRDMLAH</td>
          <td class="enctags">A2, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQRDMLSH_A2_Q" arch_version="FEAT_RDM" iformfile="vqrdmlsh.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VQRDMLSH">VQRDMLSH</td>
          <td class="enctags">A2, 128-bit SIMD vector</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="simd2reg_misc" title="Advanced SIMD two registers misc">
    <regdiagram form="32" psname="">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="19" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="17" width="2" name="opc1" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" settings="1">
        <c>0</c>
      </box>
      <box hibit="10" width="4" name="opc2" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="6" name="Q" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="simd2reg_misc" cols="6">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="6*" />
      <col colno="3" printwidth="6*" />
      <col colno="4" printwidth="3*" />
      <col colno="5" printwidth="67*" />
      <col colno="6" printwidth="40*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
          <th class="bitfields">opc1</th>
          <th class="bitfields">opc2</th>
          <th class="bitfields">Q</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VREV64_A1_Q" iformfile="vrev64.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VREV64">VREV64</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VREV32_A1_Q" iformfile="vrev32.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VREV32">VREV32</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VREV16_A1_Q" iformfile="vrev16.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VREV16">VREV16</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_17_simd2reg_misc" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VPADDL_A1_Q" iformfile="vpaddl.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">010x</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VPADDL">VPADDL</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="AESE_A1" arch_version="FEAT_AES" iformfile="aese.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="AESE">AESE</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="AESD_A1" arch_version="FEAT_AES" iformfile="aesd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="AESD">AESD</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="AESMC_A1" arch_version="FEAT_AES" iformfile="aesmc.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="AESMC">AESMC</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="AESIMC_A1" arch_version="FEAT_AES" iformfile="aesimc.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="AESIMC">AESIMC</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VCLS_A1_Q" iformfile="vcls.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCLS">VCLS</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSWP_A1_Q" iformfile="vswp.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VSWP">VSWP</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCLZ_A1_Q" iformfile="vclz.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCLZ">VCLZ</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCNT_A1_Q" iformfile="vcnt.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCNT">VCNT</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VMVN_r_A1_Q" iformfile="vmvn_r.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VMVN_r">VMVN (register)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_76_simd2reg_misc" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VPADAL_A1_Q" iformfile="vpadal.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">110x</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VPADAL">VPADAL</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQABS_A1_Q" iformfile="vqabs.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VQABS">VQABS</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQNEG_A1_Q" iformfile="vqneg.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VQNEG">VQNEG</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCGT_i_A1_Q" iformfile="vcgt_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">x000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCGT_i">VCGT (immediate #0)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCGE_i_A1_Q" iformfile="vcge_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">x001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCGE_i">VCGE (immediate #0)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCEQ_i_A1_Q" iformfile="vceq_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">x010</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCEQ_i">VCEQ (immediate #0)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCLE_i_A1_Q" iformfile="vcle_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">x011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCLE_i">VCLE (immediate #0)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCLT_i_A1_Q" iformfile="vclt_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">x100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCLT_i">VCLT (immediate #0)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VABS_A1_Q" iformfile="vabs.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">x110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VABS">VABS</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VNEG_A1_Q" iformfile="vneg.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">x111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VNEG">VNEG</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="SHA1H_A1" arch_version="FEAT_SHA1" iformfile="sha1h.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="SHA1H">SHA1H</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_bfs_A1" arch_version="FEAT_AA32BF16" iformfile="vcvt_bfs.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVT_bfs">VCVT (from single-precision to BFloat16, Advanced SIMD)</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VTRN_A1_Q" iformfile="vtrn.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VTRN">VTRN</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VUZP_A1_Q" iformfile="vuzp.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VUZP">VUZP</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VZIP_A1_Q" iformfile="vzip.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VZIP">VZIP</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VMOVN_A1" iformfile="vmovn.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMOVN">VMOVN</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VQMOVUN_A1" iformfile="vqmovn.xml" label="VQMOVUN" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VQMOVN">VQMOVN, VQMOVUN</td>
          <td class="enctags">A1, Unsigned result</td>
        </tr>
        <tr class="instructiontable" encname="VQMOVN_A1" iformfile="vqmovn.xml" label="VQMOVN" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VQMOVN">VQMOVN, VQMOVUN</td>
          <td class="enctags">A1, Signed result</td>
        </tr>
        <tr class="instructiontable" encname="VSHLL_A2" iformfile="vshll.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VSHLL">VSHLL</td>
          <td class="enctags">A2</td>
        </tr>
        <tr class="instructiontable" encname="SHA1SU1_A1" arch_version="FEAT_SHA1" iformfile="sha1su1.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SHA1SU1">SHA1SU1</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="SHA256SU0_A1" arch_version="FEAT_SHA256" iformfile="sha256su0.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="SHA256SU0">SHA256SU0</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VRINTN_asimd_A1_Q" iformfile="vrintn_asimd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VRINTN_asimd">VRINTN (Advanced SIMD)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VRINTX_asimd_A1_Q" iformfile="vrintx_asimd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VRINTX_asimd">VRINTX (Advanced SIMD)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VRINTA_asimd_A1_Q" iformfile="vrinta_asimd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VRINTA_asimd">VRINTA (Advanced SIMD)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VRINTZ_asimd_A1_Q" iformfile="vrintz_asimd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VRINTZ_asimd">VRINTZ (Advanced SIMD)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_78_simd2reg_misc" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_hs_A1" iformfile="vcvt_hs.xml" label="single-precision to half-precision" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVT_hs">VCVT (between half-precision and single-precision, Advanced SIMD)</td>
          <td class="enctags">A1, Single-precision to half-precision</td>
        </tr>
        <tr class="instructiontable" encname="VRINTM_asimd_A1_Q" iformfile="vrintm_asimd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VRINTM_asimd">VRINTM (Advanced SIMD)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_sh_A1" iformfile="vcvt_hs.xml" label="half-precision to single-precision" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVT_hs">VCVT (between half-precision and single-precision, Advanced SIMD)</td>
          <td class="enctags">A1, Half-precision to single-precision</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_83_simd2reg_misc" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VRINTP_asimd_A1_Q" iformfile="vrintp_asimd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VRINTP_asimd">VRINTP (Advanced SIMD)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCVTA_asimd_A1_Q" iformfile="vcvta_asimd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">000x</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTA_asimd">VCVTA (Advanced SIMD)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCVTN_asimd_A1_Q" iformfile="vcvtn_asimd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">001x</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTN_asimd">VCVTN (Advanced SIMD)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCVTP_asimd_A1_Q" iformfile="vcvtp_asimd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">010x</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTP_asimd">VCVTP (Advanced SIMD)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCVTM_asimd_A1_Q" iformfile="vcvtm_asimd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">011x</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTM_asimd">VCVTM (Advanced SIMD)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VRECPE_A1_Q" iformfile="vrecpe.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">10x0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VRECPE">VRECPE</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VRSQRTE_A1_Q" iformfile="vrsqrte.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">10x1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VRSQRTE">VRSQRTE</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_79_simd2reg_misc" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_is_A1_Q" iformfile="vcvt_is.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">11xx</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVT_is">VCVT (between floating-point and integer, Advanced SIMD)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="simd3reg_ext" title="Advanced SIMD vector extract">
    <regdiagram form="32" psname="">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="imm4" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" name="Q" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="simd3reg_ext" cols="2">
      <col colno="1" printwidth="22*" />
      <col colno="2" printwidth="25*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VEXT_A1_Q" iformfile="vext.xml" first="t" last="t">
          <td class="iformname" iformid="VEXT">VEXT (byte elements)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="a_simd_12reg">Advanced SIMD shifts and immediate generation</funcgroupheader>
  <iclass_sect id="simd1reg_imm" title="Advanced SIMD one register and modified immediate">
    <regdiagram form="32" psname="">
      <box hibit="31" width="7" settings="7">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="24" name="i" usename="1">
        <c></c>
      </box>
      <box hibit="23" settings="1">
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="3" settings="3">
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="18" width="3" name="imm3" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="cmode" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" settings="1">
        <c>0</c>
      </box>
      <box hibit="6" name="Q" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="op" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="imm4" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="simd1reg_imm" cols="4">
      <col colno="1" printwidth="7*" />
      <col colno="2" printwidth="4*" />
      <col colno="3" printwidth="18*" />
      <col colno="4" printwidth="25*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">cmode</th>
          <th class="bitfields">op</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encoding="a1" iformfile="vmov_i.xml" label="A1" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0xx0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMOV_i">VMOV (immediate)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="a1" iformfile="vmvn_i.xml" label="A1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">0xx0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMVN_i">VMVN (immediate)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="a1" iformfile="vorr_i.xml" label="A1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0xx1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VORR_i">VORR (immediate)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="a1" iformfile="vbic_i.xml" label="A1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0xx1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VBIC_i">VBIC (immediate)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="a3" iformfile="vmov_i.xml" label="A3" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">10x0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMOV_i">VMOV (immediate)</td>
          <td class="enctags">A3, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="a2" iformfile="vmvn_i.xml" label="A2" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">10x0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMVN_i">VMVN (immediate)</td>
          <td class="enctags">A2, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="a2" iformfile="vorr_i.xml" label="A2" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">10x1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VORR_i">VORR (immediate)</td>
          <td class="enctags">A2, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="a2" iformfile="vbic_i.xml" label="A2" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">10x1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VBIC_i">VBIC (immediate)</td>
          <td class="enctags">A2, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="a4" iformfile="vmov_i.xml" label="A4" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">11xx</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMOV_i">VMOV (immediate)</td>
          <td class="enctags">A4, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="a3" iformfile="vmvn_i.xml" label="A3" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">110x</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMVN_i">VMVN (immediate)</td>
          <td class="enctags">A3, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="a5" iformfile="vmov_i.xml" label="A5" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMOV_i">VMOV (immediate)</td>
          <td class="enctags">A5, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_33_simd1reg_imm" undef="1" first="t" last="t">
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="simd2reg_shift" title="Advanced SIMD two registers and shift amount">
    <regdiagram form="32" psname="">
      <box hibit="31" width="7" settings="7">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="24" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="23" settings="1">
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="3" name="imm3H" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="18" width="3" name="imm3L" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="opc" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="6" name="Q" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="imm3H:imm3L:Vd:opc:L" op="!=" val="000xxxxxxxxxxx0" />
    </decode_constraints>
    <instructiontable iclass="simd2reg_shift" cols="7">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="9*" />
      <col colno="3" printwidth="7*" />
      <col colno="4" printwidth="6*" />
      <col colno="5" printwidth="3*" />
      <col colno="6" printwidth="62*" />
      <col colno="7" printwidth="42*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">U</th>
          <th class="bitfields">imm3H:L</th>
          <th class="bitfields">imm3L</th>
          <th class="bitfields">opc</th>
          <th class="bitfields">Q</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VSHR_A1_Q" iformfile="vshr.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VSHR">VSHR</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSRA_A1_Q" iformfile="vsra.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VSRA">VSRA</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VMOVL_A1" iformfile="vmovl.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMOVL">VMOVL</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VRSHR_A1_Q" iformfile="vrshr.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VRSHR">VRSHR</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VRSRA_A1_D" iformfile="vrsra.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VRSRA">VRSRA</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQSHL_i_A1_Q" iformfile="vqshl_i.xml" label="VQSHL" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VQSHL_i">VQSHL, VQSHLU (immediate)</td>
          <td class="enctags">A1, 128-bit SIMD vector, signed result</td>
        </tr>
        <tr class="instructiontable" encname="VQSHRN_A1" iformfile="vqshrn.xml" label="VQSHRN" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1001</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VQSHRN">VQSHRN, VQSHRUN</td>
          <td class="enctags">A1, Signed result</td>
        </tr>
        <tr class="instructiontable" encname="VQRSHRN_A1" iformfile="vqrshrn.xml" label="VQRSHRN" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1001</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VQRSHRN">VQRSHRN, VQRSHRUN</td>
          <td class="enctags">A1, Signed result</td>
        </tr>
        <tr class="instructiontable" encname="VSHLL_A1" iformfile="vshll.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VSHLL">VSHLL</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_xs_A1_Q" iformfile="vcvt_xs.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">11xx</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVT_xs">VCVT (between floating-point and fixed-point, Advanced SIMD)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSHL_i_A1_Q" iformfile="vshl_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VSHL_i">VSHL (immediate)</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSHRN_A1" iformfile="vshrn.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VSHRN">VSHRN</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VRSHRN_A1" iformfile="vrshrn.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VRSHRN">VRSHRN</td>
          <td class="enctags">A1</td>
        </tr>
        <tr class="instructiontable" encname="VSRI_A1_Q" iformfile="vsri.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VSRI">VSRI</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSLI_A1_Q" iformfile="vsli.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VSLI">VSLI</td>
          <td class="enctags">A1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQSHLU_i_A1_Q" iformfile="vqshl_i.xml" label="VQSHLU" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VQSHL_i">VQSHL, VQSHLU (immediate)</td>
          <td class="enctags">A1, 128-bit SIMD vector, unsigned result</td>
        </tr>
        <tr class="instructiontable" encname="VQSHRUN_A1" iformfile="vqshrn.xml" label="VQSHRUN" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VQSHRN">VQSHRN, VQSHRUN</td>
          <td class="enctags">A1, Unsigned result</td>
        </tr>
        <tr class="instructiontable" encname="VQRSHRUN_A1" iformfile="vqrshrn.xml" label="VQRSHRUN" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VQRSHRN">VQRSHRN, VQRSHRUN</td>
          <td class="enctags">A1, Unsigned result</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <mappings>
    <mapping from="fpdp" to_isa="T32" to="fpdp" />
    <mapping from="ldv_ssall" to_isa="T32" to="asimldall" />
    <mapping from="simd3reg_sameext" to_isa="T32" to="simd_3sameext" />
    <mapping from="simd2reg_dup" to_isa="T32" to="simd_dup_sc" />
    <mapping from="fpminmaxnm" to_isa="T32" to="fp_minmax" />
    <mapping from="simd3reg_diff" to_isa="T32" to="simd_3diff" />
    <mapping from="sysreg_mov32" to_isa="T32" to="sysreg_mov32" />
    <mapping from="simd3reg_tbl" to_isa="T32" to="simd_tbl" />
    <mapping from="fpdp2reg" to_isa="T32" to="fp_2r" />
    <mapping from="simd3reg_same" to_isa="T32" to="simd_3same" />
    <mapping from="movsimdgp" to_isa="T32" to="simd_dup_el" />
    <mapping from="fpdp3reg" to_isa="T32" to="fp_3r" />
    <mapping from="sysldst_mov64" to_isa="T32" to="sysldst_mov64" />
    <mapping from="fpsimd_mov32" to_isa="T32" to="fpsimd_mov32" />
    <mapping from="simd2reg_misc" to_isa="T32" to="simd_2r_misc" />
    <mapping from="movfpsr" to_isa="T32" to="fp_msr" />
    <mapping from="ldstsimdfp" to_isa="T32" to="simdfp_ldst" />
    <mapping from="fpcsel" to_isa="T32" to="fp_csel" />
    <mapping from="movsimdfpgp64" to_isa="T32" to="simdfp_mov64" />
    <mapping from="fpcvtrnd" to_isa="T32" to="fp_toint" />
    <mapping from="advsimddp" to_isa="T32" to="simddp" />
    <mapping from="simd2reg_shift" to_isa="T32" to="simd_2r_shift" />
    <mapping from="movfpgp32" to_isa="T32" to="fp_mov32" />
    <mapping from="simd2reg_scalarext" to_isa="T32" to="simd_2r_scext" />
    <mapping from="ldstv_ms" to_isa="T32" to="asimldstms" />
    <mapping from="simd1reg_imm" to_isa="T32" to="simd_1r_imm" />
    <mapping from="simdldst_mov64" to_isa="T32" to="simdldst_mov64" />
    <mapping from="advsimdls" to_isa="T32" to="vldst" />
    <mapping from="fpimm" to_isa="T32" to="fp_movi" />
    <mapping from="simd3reg_ext" to_isa="T32" to="simd_ext" />
    <mapping from="ldstv_ssone" to_isa="T32" to="asimldstss" />
    <mapping from="simd2reg_scalar" to_isa="T32" to="simd_2r_sc" />
  </mappings>
</encodingindex>
</file>
<file type="encodingindex" file="t32_encindex.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<encodingindex instructionset="T32">
  <hierarchy>
    <regdiagram form="16x2">
      <box hibit="31" width="3" name="op0" usename="1">
        <c colspan="3" />
      </box>
      <box hibit="28" width="2" name="op1" usename="1">
        <c colspan="2" />
      </box>
      <box hibit="26" width="27">
        <c colspan="27" />
      </box>
    </regdiagram>
    <node groupname="n">
      <header>16-bit</header>
      <decode>
        <box hibit="31" width="3" name="op0" usename="1">
          <c colspan="3">!= 111</c>
        </box>
        <box hibit="28" width="2" name="op1" usename="1">
          <c colspan="2" />
        </box>
      </decode>
      <regdiagram form="16">
        <box hibit="31" width="6" name="op0" usename="1">
          <c colspan="6" />
        </box>
        <box hibit="25" width="26">
          <c colspan="26" />
        </box>
      </regdiagram>
      <decode_constraints>
        <decode_constraint name="op0&lt;5:3&gt;" op="!=" val="111" />
      </decode_constraints>
      <node groupname="sftdpi">
        <header>Shift (immediate), add, subtract, move, and compare</header>
        <decode>
          <box hibit="31" width="6" name="op0" usename="1">
            <c colspan="6">00xxxx</c>
          </box>
        </decode>
        <regdiagram form="16">
          <box hibit="31" width="2">
            <c colspan="2">00</c>
          </box>
          <box hibit="29" width="1" name="op0" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="28" width="2" name="op1" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="26" width="1" name="op2" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="25" width="26">
            <c colspan="26" />
          </box>
        </regdiagram>
        <node iclass="addsub16_3l">
          <header>Add, subtract (three low registers)</header>
          <decode>
            <box hibit="29" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="28" width="2" name="op1" usename="1">
              <c colspan="2">11</c>
            </box>
            <box hibit="26" width="1" name="op2" usename="1">
              <c colspan="1">0</c>
            </box>
          </decode>
        </node>
        <node iclass="addsub16_2l_imm">
          <header>Add, subtract (two low registers and immediate)</header>
          <decode>
            <box hibit="29" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="28" width="2" name="op1" usename="1">
              <c colspan="2">11</c>
            </box>
            <box hibit="26" width="1" name="op2" usename="1">
              <c colspan="1">1</c>
            </box>
          </decode>
        </node>
        <node iclass="shift16_imm">
          <header>Shift (immediate)</header>
          <decode>
            <box hibit="29" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="28" width="2" name="op1" usename="1">
              <c colspan="2">!= 11</c>
            </box>
            <box hibit="26" width="1" name="op2" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="addsub16_1l_imm">
          <header>Add, subtract, compare, move (one low register and immediate)</header>
          <decode>
            <box hibit="29" width="1" name="op0" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="28" width="2" name="op1" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="26" width="1" name="op2" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
      </node>
      <node iclass="dpint16_2l">
        <header>Data-processing (two low registers)</header>
        <decode>
          <box hibit="31" width="6" name="op0" usename="1">
            <c colspan="6">010000</c>
          </box>
        </decode>
      </node>
      <node groupname="spcd">
        <header>Special data instructions and branch and exchange</header>
        <decode>
          <box hibit="31" width="6" name="op0" usename="1">
            <c colspan="6">010001</c>
          </box>
        </decode>
        <regdiagram form="16">
          <box hibit="31" width="6">
            <c colspan="6">010001</c>
          </box>
          <box hibit="25" width="2" name="op0" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="23" width="24">
            <c colspan="24" />
          </box>
        </regdiagram>
        <node iclass="bx16">
          <header>Branch and exchange</header>
          <decode>
            <box hibit="25" width="2" name="op0" usename="1">
              <c colspan="2">11</c>
            </box>
          </decode>
        </node>
        <node iclass="addsub16_2h">
          <header>Add, subtract, compare, move (two high registers)</header>
          <decode>
            <box hibit="25" width="2" name="op0" usename="1">
              <c colspan="2">!= 11</c>
            </box>
          </decode>
        </node>
      </node>
      <node iclass="ldlit16">
        <header>Load literal</header>
        <decode>
          <box hibit="31" width="6" name="op0" usename="1">
            <c colspan="6">01001x</c>
          </box>
        </decode>
      </node>
      <node iclass="ldst16_reg">
        <header>Load/store (register offset)</header>
        <decode>
          <box hibit="31" width="6" name="op0" usename="1">
            <c colspan="6">0101xx</c>
          </box>
        </decode>
      </node>
      <node iclass="ldst16_imm">
        <header>Load/store word/byte (immediate offset)</header>
        <decode>
          <box hibit="31" width="6" name="op0" usename="1">
            <c colspan="6">011xxx</c>
          </box>
        </decode>
      </node>
      <node iclass="ldsth16_imm">
        <header>Load/store halfword (immediate offset)</header>
        <decode>
          <box hibit="31" width="6" name="op0" usename="1">
            <c colspan="6">1000xx</c>
          </box>
        </decode>
      </node>
      <node iclass="ldst16_sp">
        <header>Load/store (SP-relative)</header>
        <decode>
          <box hibit="31" width="6" name="op0" usename="1">
            <c colspan="6">1001xx</c>
          </box>
        </decode>
      </node>
      <node iclass="addpcsp16">
        <header>Add PC/SP (immediate)</header>
        <decode>
          <box hibit="31" width="6" name="op0" usename="1">
            <c colspan="6">1010xx</c>
          </box>
        </decode>
      </node>
      <node groupname="misc16">
        <header>Miscellaneous 16-bit instructions</header>
        <decode>
          <box hibit="31" width="6" name="op0" usename="1">
            <c colspan="6">1011xx</c>
          </box>
        </decode>
        <regdiagram form="16">
          <box hibit="31" width="4">
            <c colspan="4">1011</c>
          </box>
          <box hibit="27" width="4" name="op0" usename="1">
            <c colspan="4" />
          </box>
          <box hibit="23" width="2" name="op1" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="21" width="1" name="op2" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="20" width="1">
            <c colspan="1" />
          </box>
          <box hibit="19" width="4" name="op3" usename="1">
            <c colspan="4" />
          </box>
          <box hibit="15" width="16">
            <c colspan="16" />
          </box>
        </regdiagram>
        <node iclass="adjsp16">
          <header>Adjust SP (immediate)</header>
          <decode>
            <box hibit="27" width="4" name="op0" usename="1">
              <c colspan="4">0000</c>
            </box>
            <box hibit="23" width="2" name="op1" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="21" width="1" name="op2" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op3" usename="1">
              <c colspan="4" />
            </box>
          </decode>
        </node>
        <node iclass="ext16">
          <header>Extend</header>
          <decode>
            <box hibit="27" width="4" name="op0" usename="1">
              <c colspan="4">0010</c>
            </box>
            <box hibit="23" width="2" name="op1" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="21" width="1" name="op2" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op3" usename="1">
              <c colspan="4" />
            </box>
          </decode>
        </node>
        <node iclass="setpan16">
          <header>SETPAN</header>
          <decode>
            <box hibit="27" width="4" name="op0" usename="1">
              <c colspan="4">0110</c>
            </box>
            <box hibit="23" width="2" name="op1" usename="1">
              <c colspan="2">00</c>
            </box>
            <box hibit="21" width="1" name="op2" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="19" width="4" name="op3" usename="1">
              <c colspan="4" />
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_24" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="27" width="4" name="op0" usename="1">
              <c colspan="4">0110</c>
            </box>
            <box hibit="23" width="2" name="op1" usename="1">
              <c colspan="2">00</c>
            </box>
            <box hibit="21" width="1" name="op2" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="19" width="4" name="op3" usename="1">
              <c colspan="4" />
            </box>
          </decode>
        </node>
        <node iclass="cps16">
          <header>Change Processor State</header>
          <decode>
            <box hibit="27" width="4" name="op0" usename="1">
              <c colspan="4">0110</c>
            </box>
            <box hibit="23" width="2" name="op1" usename="1">
              <c colspan="2">01</c>
            </box>
            <box hibit="21" width="1" name="op2" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op3" usename="1">
              <c colspan="4" />
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_26" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="27" width="4" name="op0" usename="1">
              <c colspan="4">0110</c>
            </box>
            <box hibit="23" width="2" name="op1" usename="1">
              <c colspan="2">1x</c>
            </box>
            <box hibit="21" width="1" name="op2" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op3" usename="1">
              <c colspan="4" />
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_27" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="27" width="4" name="op0" usename="1">
              <c colspan="4">0111</c>
            </box>
            <box hibit="23" width="2" name="op1" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="21" width="1" name="op2" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op3" usename="1">
              <c colspan="4" />
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_28" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="27" width="4" name="op0" usename="1">
              <c colspan="4">1000</c>
            </box>
            <box hibit="23" width="2" name="op1" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="21" width="1" name="op2" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op3" usename="1">
              <c colspan="4" />
            </box>
          </decode>
        </node>
        <node iclass="hlt16">
          <header>Halting breakpoint</header>
          <decode>
            <box hibit="27" width="4" name="op0" usename="1">
              <c colspan="4">1010</c>
            </box>
            <box hibit="23" width="2" name="op1" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="21" width="1" name="op2" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op3" usename="1">
              <c colspan="4" />
            </box>
          </decode>
        </node>
        <node iclass="rev16">
          <header>Reverse bytes</header>
          <decode>
            <box hibit="27" width="4" name="op0" usename="1">
              <c colspan="4">1010</c>
            </box>
            <box hibit="23" width="2" name="op1" usename="1">
              <c colspan="2">!= 10</c>
            </box>
            <box hibit="21" width="1" name="op2" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op3" usename="1">
              <c colspan="4" />
            </box>
          </decode>
        </node>
        <node iclass="bkpt16">
          <header>Software breakpoint</header>
          <decode>
            <box hibit="27" width="4" name="op0" usename="1">
              <c colspan="4">1110</c>
            </box>
            <box hibit="23" width="2" name="op1" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="21" width="1" name="op2" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op3" usename="1">
              <c colspan="4" />
            </box>
          </decode>
        </node>
        <node iclass="hints16">
          <header>Hints</header>
          <decode>
            <box hibit="27" width="4" name="op0" usename="1">
              <c colspan="4">1111</c>
            </box>
            <box hibit="23" width="2" name="op1" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="21" width="1" name="op2" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op3" usename="1">
              <c colspan="4">0000</c>
            </box>
          </decode>
        </node>
        <node iclass="it16">
          <header>If-Then</header>
          <decode>
            <box hibit="27" width="4" name="op0" usename="1">
              <c colspan="4">1111</c>
            </box>
            <box hibit="23" width="2" name="op1" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="21" width="1" name="op2" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op3" usename="1">
              <c colspan="4">!= 0000</c>
            </box>
          </decode>
        </node>
        <node iclass="cbznz16">
          <header>Compare and branch zero/non-zero</header>
          <decode>
            <box hibit="27" width="4" name="op0" usename="1">
              <c colspan="4">x0x1</c>
            </box>
            <box hibit="23" width="2" name="op1" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="21" width="1" name="op2" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op3" usename="1">
              <c colspan="4" />
            </box>
          </decode>
        </node>
        <node iclass="pushpop16">
          <header>Push and Pop</header>
          <decode>
            <box hibit="27" width="4" name="op0" usename="1">
              <c colspan="4">x10x</c>
            </box>
            <box hibit="23" width="2" name="op1" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="21" width="1" name="op2" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op3" usename="1">
              <c colspan="4" />
            </box>
          </decode>
        </node>
      </node>
      <node iclass="ldstm16">
        <header>Load/store multiple</header>
        <decode>
          <box hibit="31" width="6" name="op0" usename="1">
            <c colspan="6">1100xx</c>
          </box>
        </decode>
      </node>
      <node groupname="brc">
        <header>Conditional branch, and Supervisor Call</header>
        <decode>
          <box hibit="31" width="6" name="op0" usename="1">
            <c colspan="6">1101xx</c>
          </box>
        </decode>
        <regdiagram form="16">
          <box hibit="31" width="4">
            <c colspan="4">1101</c>
          </box>
          <box hibit="27" width="4" name="op0" usename="1">
            <c colspan="4" />
          </box>
          <box hibit="23" width="24">
            <c colspan="24" />
          </box>
        </regdiagram>
        <node iclass="except16">
          <header>Exception generation</header>
          <decode>
            <box hibit="27" width="4" name="op0" usename="1">
              <c colspan="4">111x</c>
            </box>
          </decode>
        </node>
        <node iclass="bcond16">
          <header>Conditional branch</header>
          <decode>
            <box hibit="27" width="4" name="op0" usename="1">
              <c colspan="4">!= 111x</c>
            </box>
          </decode>
        </node>
      </node>
    </node>
    <node iclass="b16">
      <header>Unconditional branch</header>
      <decode>
        <box hibit="31" width="3" name="op0" usename="1">
          <c colspan="3">111</c>
        </box>
        <box hibit="28" width="2" name="op1" usename="1">
          <c colspan="2">00</c>
        </box>
      </decode>
    </node>
    <node groupname="w">
      <header>32-bit</header>
      <decode>
        <box hibit="31" width="3" name="op0" usename="1">
          <c colspan="3">111</c>
        </box>
        <box hibit="28" width="2" name="op1" usename="1">
          <c colspan="2">!= 00</c>
        </box>
      </decode>
      <regdiagram form="16x2">
        <box hibit="31" width="3">
          <c colspan="3">111</c>
        </box>
        <box hibit="28" width="4" name="op0" usename="1">
          <c colspan="4" />
        </box>
        <box hibit="24" width="5" name="op1" usename="1">
          <c colspan="5" />
        </box>
        <box hibit="19" width="4">
          <c colspan="4" />
        </box>
        <box hibit="15" width="1" name="op3" usename="1">
          <c colspan="1" />
        </box>
        <box hibit="14" width="15">
          <c colspan="15" />
        </box>
      </regdiagram>
      <decode_constraints>
        <decode_constraint name="op0&lt;3:2&gt;" op="!=" val="00" />
      </decode_constraints>
      <node groupname="cpaf">
        <header>System register access, Advanced SIMD, and floating-point</header>
        <decode>
          <box hibit="28" width="4" name="op0" usename="1">
            <c colspan="4">x11x</c>
          </box>
          <box hibit="24" width="5" name="op1" usename="1">
            <c colspan="5" />
          </box>
          <box hibit="15" width="1" name="op3" usename="1">
            <c colspan="1" />
          </box>
        </decode>
        <regdiagram form="16x2">
          <box hibit="31" width="3">
            <c colspan="3">111</c>
          </box>
          <box hibit="28" width="1" name="op0" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="27" width="2">
            <c colspan="2">11</c>
          </box>
          <box hibit="25" width="2" name="op1" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="23" width="12">
            <c colspan="12" />
          </box>
          <box hibit="11" width="2" name="op2" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="9" width="5">
            <c colspan="5" />
          </box>
          <box hibit="4" width="1" name="op3" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="3" width="4">
            <c colspan="4" />
          </box>
        </regdiagram>
        <node iclass="unalloc_cops1" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="28" width="1" name="op0" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="25" width="2" name="op1" usename="1">
              <c colspan="2">0x</c>
            </box>
            <box hibit="11" width="2" name="op2" usename="1">
              <c colspan="2">0x</c>
            </box>
            <box hibit="4" width="1" name="op3" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="unalloc_cops2" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="28" width="1" name="op0" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="25" width="2" name="op1" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="11" width="2" name="op2" usename="1">
              <c colspan="2">0x</c>
            </box>
            <box hibit="4" width="1" name="op3" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node groupname="simddp">
          <header>Advanced SIMD data-processing</header>
          <decode>
            <box hibit="28" width="1" name="op0" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="25" width="2" name="op1" usename="1">
              <c colspan="2">11</c>
            </box>
            <box hibit="11" width="2" name="op2" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="4" width="1" name="op3" usename="1">
              <c colspan="1" />
            </box>
          </decode>
          <regdiagram form="16x2">
            <box hibit="31" width="3">
              <c colspan="3">111</c>
            </box>
            <box hibit="28" width="1">
              <c colspan="1" />
            </box>
            <box hibit="27" width="4">
              <c colspan="4">1111</c>
            </box>
            <box hibit="23" width="1" name="op0" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="22" width="18">
              <c colspan="18" />
            </box>
            <box hibit="4" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="3" width="4">
              <c colspan="4" />
            </box>
          </regdiagram>
          <node iclass="simd_3same">
            <header>Advanced SIMD three registers of the same length</header>
            <decode>
              <box hibit="23" width="1" name="op0" usename="1">
                <c colspan="1">0</c>
              </box>
              <box hibit="4" width="1" name="op1" usename="1">
                <c colspan="1" />
              </box>
            </decode>
          </node>
          <node groupname="t_simd_mulreg">
            <header>Advanced SIMD two registers, or three registers of different lengths</header>
            <decode>
              <box hibit="23" width="1" name="op0" usename="1">
                <c colspan="1">1</c>
              </box>
              <box hibit="4" width="1" name="op1" usename="1">
                <c colspan="1">0</c>
              </box>
            </decode>
            <regdiagram form="16x2">
              <box hibit="31" width="3">
                <c colspan="3">111</c>
              </box>
              <box hibit="28" width="1" name="op0" usename="1">
                <c colspan="1" />
              </box>
              <box hibit="27" width="5">
                <c colspan="5">11111</c>
              </box>
              <box hibit="22" width="1">
                <c colspan="1" />
              </box>
              <box hibit="21" width="2" name="op1" usename="1">
                <c colspan="2" />
              </box>
              <box hibit="19" width="8">
                <c colspan="8" />
              </box>
              <box hibit="11" width="2" name="op2" usename="1">
                <c colspan="2" />
              </box>
              <box hibit="9" width="3">
                <c colspan="3" />
              </box>
              <box hibit="6" width="1" name="op3" usename="1">
                <c colspan="1" />
              </box>
              <box hibit="5" width="1">
                <c colspan="1" />
              </box>
              <box hibit="4" width="1">
                <c colspan="1">0</c>
              </box>
              <box hibit="3" width="4">
                <c colspan="4" />
              </box>
            </regdiagram>
            <node iclass="simd_ext">
              <header>Advanced SIMD vector extract</header>
              <decode>
                <box hibit="28" width="1" name="op0" usename="1">
                  <c colspan="1">0</c>
                </box>
                <box hibit="21" width="2" name="op1" usename="1">
                  <c colspan="2">11</c>
                </box>
                <box hibit="11" width="2" name="op2" usename="1">
                  <c colspan="2" />
                </box>
                <box hibit="6" width="1" name="op3" usename="1">
                  <c colspan="1" />
                </box>
              </decode>
            </node>
            <node iclass="simd_2r_misc">
              <header>Advanced SIMD two registers misc</header>
              <decode>
                <box hibit="28" width="1" name="op0" usename="1">
                  <c colspan="1">1</c>
                </box>
                <box hibit="21" width="2" name="op1" usename="1">
                  <c colspan="2">11</c>
                </box>
                <box hibit="11" width="2" name="op2" usename="1">
                  <c colspan="2">0x</c>
                </box>
                <box hibit="6" width="1" name="op3" usename="1">
                  <c colspan="1" />
                </box>
              </decode>
            </node>
            <node iclass="simd_tbl">
              <header>Advanced SIMD table permute</header>
              <decode>
                <box hibit="28" width="1" name="op0" usename="1">
                  <c colspan="1">1</c>
                </box>
                <box hibit="21" width="2" name="op1" usename="1">
                  <c colspan="2">11</c>
                </box>
                <box hibit="11" width="2" name="op2" usename="1">
                  <c colspan="2">10</c>
                </box>
                <box hibit="6" width="1" name="op3" usename="1">
                  <c colspan="1" />
                </box>
              </decode>
            </node>
            <node iclass="simd_dup_sc">
              <header>Advanced SIMD duplicate (scalar)</header>
              <decode>
                <box hibit="28" width="1" name="op0" usename="1">
                  <c colspan="1">1</c>
                </box>
                <box hibit="21" width="2" name="op1" usename="1">
                  <c colspan="2">11</c>
                </box>
                <box hibit="11" width="2" name="op2" usename="1">
                  <c colspan="2">11</c>
                </box>
                <box hibit="6" width="1" name="op3" usename="1">
                  <c colspan="1" />
                </box>
              </decode>
            </node>
            <node iclass="simd_3diff">
              <header>Advanced SIMD three registers of different lengths</header>
              <decode>
                <box hibit="28" width="1" name="op0" usename="1">
                  <c colspan="1" />
                </box>
                <box hibit="21" width="2" name="op1" usename="1">
                  <c colspan="2">!= 11</c>
                </box>
                <box hibit="11" width="2" name="op2" usename="1">
                  <c colspan="2" />
                </box>
                <box hibit="6" width="1" name="op3" usename="1">
                  <c colspan="1">0</c>
                </box>
              </decode>
            </node>
            <node iclass="simd_2r_sc">
              <header>Advanced SIMD two registers and a scalar</header>
              <decode>
                <box hibit="28" width="1" name="op0" usename="1">
                  <c colspan="1" />
                </box>
                <box hibit="21" width="2" name="op1" usename="1">
                  <c colspan="2">!= 11</c>
                </box>
                <box hibit="11" width="2" name="op2" usename="1">
                  <c colspan="2" />
                </box>
                <box hibit="6" width="1" name="op3" usename="1">
                  <c colspan="1">1</c>
                </box>
              </decode>
            </node>
          </node>
          <node groupname="t_simd_12reg">
            <header>Advanced SIMD shifts and immediate generation</header>
            <decode>
              <box hibit="23" width="1" name="op0" usename="1">
                <c colspan="1">1</c>
              </box>
              <box hibit="4" width="1" name="op1" usename="1">
                <c colspan="1">1</c>
              </box>
            </decode>
            <regdiagram form="16x2">
              <box hibit="31" width="3">
                <c colspan="3">111</c>
              </box>
              <box hibit="28" width="1">
                <c colspan="1" />
              </box>
              <box hibit="27" width="5">
                <c colspan="5">11111</c>
              </box>
              <box hibit="22" width="1">
                <c colspan="1" />
              </box>
              <box hibit="21" width="15" name="op0" usename="1">
                <c colspan="15" />
              </box>
              <box hibit="6" width="2">
                <c colspan="2" />
              </box>
              <box hibit="4" width="1">
                <c colspan="1">1</c>
              </box>
              <box hibit="3" width="4">
                <c colspan="4" />
              </box>
            </regdiagram>
            <node iclass="simd_1r_imm">
              <header>Advanced SIMD one register and modified immediate</header>
              <decode>
                <box hibit="21" width="15" name="op0" usename="1">
                  <c colspan="15">000xxxxxxxxxxx0</c>
                </box>
              </decode>
            </node>
            <node iclass="simd_2r_shift">
              <header>Advanced SIMD two registers and shift amount</header>
              <decode>
                <box hibit="21" width="15" name="op0" usename="1">
                  <c colspan="15">!= 000xxxxxxxxxxx0</c>
                </box>
              </decode>
            </node>
          </node>
        </node>
        <node groupname="sysldst_mov64">
          <header>Advanced SIMD and System register load/store and 64-bit move</header>
          <decode>
            <box hibit="28" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="25" width="2" name="op1" usename="1">
              <c colspan="2">0x</c>
            </box>
            <box hibit="11" width="2" name="op2" usename="1">
              <c colspan="2">1x</c>
            </box>
            <box hibit="4" width="1" name="op3" usename="1">
              <c colspan="1" />
            </box>
          </decode>
          <regdiagram form="16x2">
            <box hibit="31" width="7">
              <c colspan="7">1110110</c>
            </box>
            <box hibit="24" width="4" name="op0" usename="1">
              <c colspan="4" />
            </box>
            <box hibit="20" width="9">
              <c colspan="9" />
            </box>
            <box hibit="11" width="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="10" width="2" name="op1" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="8" width="9">
              <c colspan="9" />
            </box>
          </regdiagram>
          <node iclass="simdfp_mov64">
            <header>Advanced SIMD and floating-point 64-bit move</header>
            <decode>
              <box hibit="24" width="4" name="op0" usename="1">
                <c colspan="4">00x0</c>
              </box>
              <box hibit="10" width="2" name="op1" usename="1">
                <c colspan="2">0x</c>
              </box>
            </decode>
          </node>
          <node iclass="cp_mov64">
            <header>System register 64-bit move</header>
            <decode>
              <box hibit="24" width="4" name="op0" usename="1">
                <c colspan="4">00x0</c>
              </box>
              <box hibit="10" width="2" name="op1" usename="1">
                <c colspan="2">11</c>
              </box>
            </decode>
          </node>
          <node iclass="simdfp_ldst">
            <header>Advanced SIMD and floating-point load/store</header>
            <decode>
              <box hibit="24" width="4" name="op0" usename="1">
                <c colspan="4">!= 00x0</c>
              </box>
              <box hibit="10" width="2" name="op1" usename="1">
                <c colspan="2">0x</c>
              </box>
            </decode>
          </node>
          <node iclass="cp_ldst">
            <header>System register Load/Store</header>
            <decode>
              <box hibit="24" width="4" name="op0" usename="1">
                <c colspan="4">!= 00x0</c>
              </box>
              <box hibit="10" width="2" name="op1" usename="1">
                <c colspan="2">11</c>
              </box>
            </decode>
          </node>
          <node iclass="UNALLOCATED_120" unallocated="1">
            <header>UNALLOCATED</header>
            <decode>
              <box hibit="24" width="4" name="op0" usename="1">
                <c colspan="4" />
              </box>
              <box hibit="10" width="2" name="op1" usename="1">
                <c colspan="2">10</c>
              </box>
            </decode>
          </node>
        </node>
        <node groupname="sys_mov32">
          <header>Advanced SIMD and System register 32-bit move</header>
          <decode>
            <box hibit="28" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="25" width="2" name="op1" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="11" width="2" name="op2" usename="1">
              <c colspan="2">1x</c>
            </box>
            <box hibit="4" width="1" name="op3" usename="1">
              <c colspan="1">1</c>
            </box>
          </decode>
          <regdiagram form="16x2">
            <box hibit="31" width="8">
              <c colspan="8">11101110</c>
            </box>
            <box hibit="23" width="3" name="op0" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="20" width="9">
              <c colspan="9" />
            </box>
            <box hibit="11" width="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="10" width="3" name="op1" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="7" width="3">
              <c colspan="3" />
            </box>
            <box hibit="4" width="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="3" width="4">
              <c colspan="4" />
            </box>
          </regdiagram>
          <node iclass="UNALLOCATED_127" unallocated="1">
            <header>UNALLOCATED</header>
            <decode>
              <box hibit="23" width="3" name="op0" usename="1">
                <c colspan="3">000</c>
              </box>
              <box hibit="10" width="3" name="op1" usename="1">
                <c colspan="3">000</c>
              </box>
            </decode>
          </node>
          <node iclass="fp_mov16">
            <header>Floating-point 16-bit move</header>
            <decode>
              <box hibit="23" width="3" name="op0" usename="1">
                <c colspan="3">000</c>
              </box>
              <box hibit="10" width="3" name="op1" usename="1">
                <c colspan="3">001</c>
              </box>
            </decode>
          </node>
          <node iclass="fp_mov32">
            <header>Floating-point 32-bit move</header>
            <decode>
              <box hibit="23" width="3" name="op0" usename="1">
                <c colspan="3">000</c>
              </box>
              <box hibit="10" width="3" name="op1" usename="1">
                <c colspan="3">010</c>
              </box>
            </decode>
          </node>
          <node iclass="UNALLOCATED_130" unallocated="1">
            <header>UNALLOCATED</header>
            <decode>
              <box hibit="23" width="3" name="op0" usename="1">
                <c colspan="3">001</c>
              </box>
              <box hibit="10" width="3" name="op1" usename="1">
                <c colspan="3">010</c>
              </box>
            </decode>
          </node>
          <node iclass="UNALLOCATED_131" unallocated="1">
            <header>UNALLOCATED</header>
            <decode>
              <box hibit="23" width="3" name="op0" usename="1">
                <c colspan="3">01x</c>
              </box>
              <box hibit="10" width="3" name="op1" usename="1">
                <c colspan="3">010</c>
              </box>
            </decode>
          </node>
          <node iclass="UNALLOCATED_132" unallocated="1">
            <header>UNALLOCATED</header>
            <decode>
              <box hibit="23" width="3" name="op0" usename="1">
                <c colspan="3">10x</c>
              </box>
              <box hibit="10" width="3" name="op1" usename="1">
                <c colspan="3">010</c>
              </box>
            </decode>
          </node>
          <node iclass="UNALLOCATED_133" unallocated="1">
            <header>UNALLOCATED</header>
            <decode>
              <box hibit="23" width="3" name="op0" usename="1">
                <c colspan="3">110</c>
              </box>
              <box hibit="10" width="3" name="op1" usename="1">
                <c colspan="3">010</c>
              </box>
            </decode>
          </node>
          <node iclass="fp_msr">
            <header>Floating-point move special register</header>
            <decode>
              <box hibit="23" width="3" name="op0" usename="1">
                <c colspan="3">111</c>
              </box>
              <box hibit="10" width="3" name="op1" usename="1">
                <c colspan="3">010</c>
              </box>
            </decode>
          </node>
          <node iclass="simd_dup_el">
            <header>Advanced SIMD 8/16/32-bit element move/duplicate</header>
            <decode>
              <box hibit="23" width="3" name="op0" usename="1">
                <c colspan="3" />
              </box>
              <box hibit="10" width="3" name="op1" usename="1">
                <c colspan="3">011</c>
              </box>
            </decode>
          </node>
          <node iclass="UNALLOCATED_136" unallocated="1">
            <header>UNALLOCATED</header>
            <decode>
              <box hibit="23" width="3" name="op0" usename="1">
                <c colspan="3" />
              </box>
              <box hibit="10" width="3" name="op1" usename="1">
                <c colspan="3">10x</c>
              </box>
            </decode>
          </node>
          <node iclass="cp_mov32">
            <header>System register 32-bit move</header>
            <decode>
              <box hibit="23" width="3" name="op0" usename="1">
                <c colspan="3" />
              </box>
              <box hibit="10" width="3" name="op1" usename="1">
                <c colspan="3">11x</c>
              </box>
            </decode>
          </node>
        </node>
        <node groupname="fpdp">
          <header>Floating-point data-processing</header>
          <decode>
            <box hibit="28" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="25" width="2" name="op1" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="11" width="2" name="op2" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="4" width="1" name="op3" usename="1">
              <c colspan="1">0</c>
            </box>
          </decode>
          <regdiagram form="16x2">
            <box hibit="31" width="8">
              <c colspan="8">11101110</c>
            </box>
            <box hibit="23" width="4" name="op0" usename="1">
              <c colspan="4" />
            </box>
            <box hibit="19" width="8">
              <c colspan="8" />
            </box>
            <box hibit="11" width="2">
              <c colspan="2">10</c>
            </box>
            <box hibit="9" width="3">
              <c colspan="3" />
            </box>
            <box hibit="6" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="5" width="1">
              <c colspan="1" />
            </box>
            <box hibit="4" width="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="3" width="4">
              <c colspan="4" />
            </box>
          </regdiagram>
          <node iclass="fp_2r">
            <header>Floating-point data-processing (two registers)</header>
            <decode>
              <box hibit="23" width="4" name="op0" usename="1">
                <c colspan="4">1x11</c>
              </box>
              <box hibit="6" width="1" name="op1" usename="1">
                <c colspan="1">1</c>
              </box>
            </decode>
          </node>
          <node iclass="fp_movi">
            <header>Floating-point move immediate</header>
            <decode>
              <box hibit="23" width="4" name="op0" usename="1">
                <c colspan="4">1x11</c>
              </box>
              <box hibit="6" width="1" name="op1" usename="1">
                <c colspan="1">0</c>
              </box>
            </decode>
          </node>
          <node iclass="fp_3r">
            <header>Floating-point data-processing (three registers)</header>
            <decode>
              <box hibit="23" width="4" name="op0" usename="1">
                <c colspan="4">!= 1x11</c>
              </box>
              <box hibit="6" width="1" name="op1" usename="1">
                <c colspan="1" />
              </box>
            </decode>
          </node>
        </node>
        <node iclass="unalloc_cops_3" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="28" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="25" width="2" name="op1" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="11" width="2" name="op2" usename="1">
              <c colspan="2">11</c>
            </box>
            <box hibit="4" width="1" name="op3" usename="1">
              <c colspan="1">0</c>
            </box>
          </decode>
        </node>
        <node groupname="advsimdext">
          <header>Additional Advanced SIMD and floating-point instructions</header>
          <decode>
            <box hibit="28" width="1" name="op0" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="25" width="2" name="op1" usename="1">
              <c colspan="2">!= 11</c>
            </box>
            <box hibit="11" width="2" name="op2" usename="1">
              <c colspan="2">1x</c>
            </box>
            <box hibit="4" width="1" name="op3" usename="1">
              <c colspan="1" />
            </box>
          </decode>
          <regdiagram form="16x2">
            <box hibit="31" width="6">
              <c colspan="6">111111</c>
            </box>
            <box hibit="25" width="3" name="op0" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="22" width="1">
              <c colspan="1" />
            </box>
            <box hibit="21" width="6" name="op1" usename="1">
              <c colspan="6" />
            </box>
            <box hibit="15" width="4">
              <c colspan="4" />
            </box>
            <box hibit="11" width="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="10" width="1" name="op2" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="9" width="2" name="op3" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="7" width="1">
              <c colspan="1" />
            </box>
            <box hibit="6" width="1" name="op4" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="5" width="1">
              <c colspan="1" />
            </box>
            <box hibit="4" width="1" name="op5" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="3" width="4">
              <c colspan="4" />
            </box>
          </regdiagram>
          <decode_constraints>
            <decode_constraint name="op0&lt;2:1&gt;" op="!=" val="11" />
          </decode_constraints>
          <node iclass="simd_3sameext">
            <header>Advanced SIMD three registers of the same length extension</header>
            <decode>
              <box hibit="25" width="3" name="op0" usename="1">
                <c colspan="3">0xx</c>
              </box>
              <box hibit="21" width="6" name="op1" usename="1">
                <c colspan="6" />
              </box>
              <box hibit="10" width="1" name="op2" usename="1">
                <c colspan="1" />
              </box>
              <box hibit="9" width="2" name="op3" usename="1">
                <c colspan="2">0x</c>
              </box>
              <box hibit="6" width="1" name="op4" usename="1">
                <c colspan="1" />
              </box>
              <box hibit="4" width="1" name="op5" usename="1">
                <c colspan="1" />
              </box>
            </decode>
          </node>
          <node iclass="fp_csel">
            <header>Floating-point conditional select</header>
            <decode>
              <box hibit="25" width="3" name="op0" usename="1">
                <c colspan="3">100</c>
              </box>
              <box hibit="21" width="6" name="op1" usename="1">
                <c colspan="6" />
              </box>
              <box hibit="10" width="1" name="op2" usename="1">
                <c colspan="1">0</c>
              </box>
              <box hibit="9" width="2" name="op3" usename="1">
                <c colspan="2">!= 00</c>
              </box>
              <box hibit="6" width="1" name="op4" usename="1">
                <c colspan="1">0</c>
              </box>
              <box hibit="4" width="1" name="op5" usename="1">
                <c colspan="1">0</c>
              </box>
            </decode>
          </node>
          <node iclass="fp_minmax">
            <header>Floating-point minNum/maxNum</header>
            <decode>
              <box hibit="25" width="3" name="op0" usename="1">
                <c colspan="3">101</c>
              </box>
              <box hibit="21" width="6" name="op1" usename="1">
                <c colspan="6">00xxxx</c>
              </box>
              <box hibit="10" width="1" name="op2" usename="1">
                <c colspan="1">0</c>
              </box>
              <box hibit="9" width="2" name="op3" usename="1">
                <c colspan="2">!= 00</c>
              </box>
              <box hibit="6" width="1" name="op4" usename="1">
                <c colspan="1" />
              </box>
              <box hibit="4" width="1" name="op5" usename="1">
                <c colspan="1">0</c>
              </box>
            </decode>
          </node>
          <node iclass="fp_extins">
            <header>Floating-point extraction and insertion</header>
            <decode>
              <box hibit="25" width="3" name="op0" usename="1">
                <c colspan="3">101</c>
              </box>
              <box hibit="21" width="6" name="op1" usename="1">
                <c colspan="6">110000</c>
              </box>
              <box hibit="10" width="1" name="op2" usename="1">
                <c colspan="1">0</c>
              </box>
              <box hibit="9" width="2" name="op3" usename="1">
                <c colspan="2">!= 00</c>
              </box>
              <box hibit="6" width="1" name="op4" usename="1">
                <c colspan="1">1</c>
              </box>
              <box hibit="4" width="1" name="op5" usename="1">
                <c colspan="1">0</c>
              </box>
            </decode>
          </node>
          <node iclass="fp_toint">
            <header>Floating-point directed convert to integer</header>
            <decode>
              <box hibit="25" width="3" name="op0" usename="1">
                <c colspan="3">101</c>
              </box>
              <box hibit="21" width="6" name="op1" usename="1">
                <c colspan="6">111xxx</c>
              </box>
              <box hibit="10" width="1" name="op2" usename="1">
                <c colspan="1">0</c>
              </box>
              <box hibit="9" width="2" name="op3" usename="1">
                <c colspan="2">!= 00</c>
              </box>
              <box hibit="6" width="1" name="op4" usename="1">
                <c colspan="1">1</c>
              </box>
              <box hibit="4" width="1" name="op5" usename="1">
                <c colspan="1">0</c>
              </box>
            </decode>
          </node>
          <node iclass="tfloatdpmac">
            <header>Advanced SIMD and floating-point multiply with accumulate</header>
            <decode>
              <box hibit="25" width="3" name="op0" usename="1">
                <c colspan="3">10x</c>
              </box>
              <box hibit="21" width="6" name="op1" usename="1">
                <c colspan="6" />
              </box>
              <box hibit="10" width="1" name="op2" usename="1">
                <c colspan="1">0</c>
              </box>
              <box hibit="9" width="2" name="op3" usename="1">
                <c colspan="2">00</c>
              </box>
              <box hibit="6" width="1" name="op4" usename="1">
                <c colspan="1" />
              </box>
              <box hibit="4" width="1" name="op5" usename="1">
                <c colspan="1" />
              </box>
            </decode>
          </node>
          <node iclass="tsimd_dotprod">
            <header>Advanced SIMD and floating-point dot product</header>
            <decode>
              <box hibit="25" width="3" name="op0" usename="1">
                <c colspan="3">10x</c>
              </box>
              <box hibit="21" width="6" name="op1" usename="1">
                <c colspan="6" />
              </box>
              <box hibit="10" width="1" name="op2" usename="1">
                <c colspan="1">1</c>
              </box>
              <box hibit="9" width="2" name="op3" usename="1">
                <c colspan="2">0x</c>
              </box>
              <box hibit="6" width="1" name="op4" usename="1">
                <c colspan="1" />
              </box>
              <box hibit="4" width="1" name="op5" usename="1">
                <c colspan="1" />
              </box>
            </decode>
          </node>
        </node>
      </node>
      <node iclass="ldstm">
        <header>Load/store multiple</header>
        <decode>
          <box hibit="28" width="4" name="op0" usename="1">
            <c colspan="4">0100</c>
          </box>
          <box hibit="24" width="5" name="op1" usename="1">
            <c colspan="5">xx0xx</c>
          </box>
          <box hibit="15" width="1" name="op3" usename="1">
            <c colspan="1" />
          </box>
        </decode>
      </node>
      <node groupname="dstd">
        <header>Load/store dual, load/store exclusive, load-acquire/store-release, and table branch</header>
        <decode>
          <box hibit="28" width="4" name="op0" usename="1">
            <c colspan="4">0100</c>
          </box>
          <box hibit="24" width="5" name="op1" usename="1">
            <c colspan="5">xx1xx</c>
          </box>
          <box hibit="15" width="1" name="op3" usename="1">
            <c colspan="1" />
          </box>
        </decode>
        <regdiagram form="16x2">
          <box hibit="31" width="7">
            <c colspan="7">1110100</c>
          </box>
          <box hibit="24" width="4" name="op0" usename="1">
            <c colspan="4" />
          </box>
          <box hibit="20" width="1" name="op1" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="19" width="4" name="op2" usename="1">
            <c colspan="4" />
          </box>
          <box hibit="15" width="8">
            <c colspan="8" />
          </box>
          <box hibit="7" width="3" name="op3" usename="1">
            <c colspan="3" />
          </box>
          <box hibit="4" width="5">
            <c colspan="5" />
          </box>
        </regdiagram>
        <decode_constraints>
          <decode_constraint name="op0&lt;1&gt;" op="==" val="1" />
        </decode_constraints>
        <node iclass="ldstex">
          <header>Load/store exclusive</header>
          <decode>
            <box hibit="24" width="4" name="op0" usename="1">
              <c colspan="4">0010</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4" />
            </box>
            <box hibit="7" width="3" name="op3" usename="1">
              <c colspan="3" />
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_45" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="4" name="op0" usename="1">
              <c colspan="4">0110</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4" />
            </box>
            <box hibit="7" width="3" name="op3" usename="1">
              <c colspan="3">000</c>
            </box>
          </decode>
        </node>
        <node iclass="tblbr">
          <header>Table branch</header>
          <decode>
            <box hibit="24" width="4" name="op0" usename="1">
              <c colspan="4">0110</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4" />
            </box>
            <box hibit="7" width="3" name="op3" usename="1">
              <c colspan="3">000</c>
            </box>
          </decode>
        </node>
        <node iclass="ldstex_bhd">
          <header>Load/store exclusive byte/half/dual</header>
          <decode>
            <box hibit="24" width="4" name="op0" usename="1">
              <c colspan="4">0110</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4" />
            </box>
            <box hibit="7" width="3" name="op3" usename="1">
              <c colspan="3">01x</c>
            </box>
          </decode>
        </node>
        <node iclass="ldastl">
          <header>Load-acquire / Store-release</header>
          <decode>
            <box hibit="24" width="4" name="op0" usename="1">
              <c colspan="4">0110</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4" />
            </box>
            <box hibit="7" width="3" name="op3" usename="1">
              <c colspan="3">1xx</c>
            </box>
          </decode>
        </node>
        <node iclass="ldstd_post">
          <header>Load/store dual (immediate, post-indexed)</header>
          <decode>
            <box hibit="24" width="4" name="op0" usename="1">
              <c colspan="4">0x11</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="7" width="3" name="op3" usename="1">
              <c colspan="3" />
            </box>
          </decode>
        </node>
        <node iclass="ldstd_imm">
          <header>Load/store dual (immediate)</header>
          <decode>
            <box hibit="24" width="4" name="op0" usename="1">
              <c colspan="4">1x10</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="7" width="3" name="op3" usename="1">
              <c colspan="3" />
            </box>
          </decode>
        </node>
        <node iclass="ldstd_pre">
          <header>Load/store dual (immediate, pre-indexed)</header>
          <decode>
            <box hibit="24" width="4" name="op0" usename="1">
              <c colspan="4">1x11</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="7" width="3" name="op3" usename="1">
              <c colspan="3" />
            </box>
          </decode>
        </node>
        <node iclass="lddlit">
          <header>Load dual (literal)</header>
          <decode>
            <box hibit="24" width="4" name="op0" usename="1">
              <c colspan="4">!= 0xx0</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">1111</c>
            </box>
            <box hibit="7" width="3" name="op3" usename="1">
              <c colspan="3" />
            </box>
          </decode>
        </node>
      </node>
      <node iclass="dpint_shiftr">
        <header>Data-processing (shifted register)</header>
        <decode>
          <box hibit="28" width="4" name="op0" usename="1">
            <c colspan="4">0101</c>
          </box>
          <box hibit="24" width="5" name="op1" usename="1">
            <c colspan="5" />
          </box>
          <box hibit="15" width="1" name="op3" usename="1">
            <c colspan="1" />
          </box>
        </decode>
      </node>
      <node groupname="bcrtrl">
        <header>Branches and miscellaneous control</header>
        <decode>
          <box hibit="28" width="4" name="op0" usename="1">
            <c colspan="4">10xx</c>
          </box>
          <box hibit="24" width="5" name="op1" usename="1">
            <c colspan="5" />
          </box>
          <box hibit="15" width="1" name="op3" usename="1">
            <c colspan="1">1</c>
          </box>
        </decode>
        <regdiagram form="16x2">
          <box hibit="31" width="5">
            <c colspan="5">11110</c>
          </box>
          <box hibit="26" width="1" name="op0" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="25" width="4" name="op1" usename="1">
            <c colspan="4" />
          </box>
          <box hibit="21" width="2" name="op2" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="19" width="4">
            <c colspan="4" />
          </box>
          <box hibit="15" width="1">
            <c colspan="1">1</c>
          </box>
          <box hibit="14" width="3" name="op3" usename="1">
            <c colspan="3" />
          </box>
          <box hibit="11" width="1">
            <c colspan="1" />
          </box>
          <box hibit="10" width="3" name="op4" usename="1">
            <c colspan="3" />
          </box>
          <box hibit="7" width="2">
            <c colspan="2" />
          </box>
          <box hibit="5" width="1" name="op5" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="4" width="5">
            <c colspan="5" />
          </box>
        </regdiagram>
        <node iclass="msr_spec">
          <header>MSR (special)</header>
          <decode>
            <box hibit="26" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="25" width="4" name="op1" usename="1">
              <c colspan="4">1110</c>
            </box>
            <box hibit="21" width="2" name="op2" usename="1">
              <c colspan="2">0x</c>
            </box>
            <box hibit="14" width="3" name="op3" usename="1">
              <c colspan="3">0x0</c>
            </box>
            <box hibit="10" width="3" name="op4" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="5" width="1" name="op5" usename="1">
              <c colspan="1">0</c>
            </box>
          </decode>
        </node>
        <node iclass="msr_bank">
          <header>MSR (banked)</header>
          <decode>
            <box hibit="26" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="25" width="4" name="op1" usename="1">
              <c colspan="4">1110</c>
            </box>
            <box hibit="21" width="2" name="op2" usename="1">
              <c colspan="2">0x</c>
            </box>
            <box hibit="14" width="3" name="op3" usename="1">
              <c colspan="3">0x0</c>
            </box>
            <box hibit="10" width="3" name="op4" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="5" width="1" name="op5" usename="1">
              <c colspan="1">1</c>
            </box>
          </decode>
        </node>
        <node iclass="hints">
          <header>Hints</header>
          <decode>
            <box hibit="26" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="25" width="4" name="op1" usename="1">
              <c colspan="4">1110</c>
            </box>
            <box hibit="21" width="2" name="op2" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="14" width="3" name="op3" usename="1">
              <c colspan="3">0x0</c>
            </box>
            <box hibit="10" width="3" name="op4" usename="1">
              <c colspan="3">000</c>
            </box>
            <box hibit="5" width="1" name="op5" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="cps">
          <header>Change processor state</header>
          <decode>
            <box hibit="26" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="25" width="4" name="op1" usename="1">
              <c colspan="4">1110</c>
            </box>
            <box hibit="21" width="2" name="op2" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="14" width="3" name="op3" usename="1">
              <c colspan="3">0x0</c>
            </box>
            <box hibit="10" width="3" name="op4" usename="1">
              <c colspan="3">!= 000</c>
            </box>
            <box hibit="5" width="1" name="op5" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="system">
          <header>Miscellaneous system</header>
          <decode>
            <box hibit="26" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="25" width="4" name="op1" usename="1">
              <c colspan="4">1110</c>
            </box>
            <box hibit="21" width="2" name="op2" usename="1">
              <c colspan="2">11</c>
            </box>
            <box hibit="14" width="3" name="op3" usename="1">
              <c colspan="3">0x0</c>
            </box>
            <box hibit="10" width="3" name="op4" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="5" width="1" name="op5" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="bx_jaz">
          <header>Branch and Exchange Jazelle</header>
          <decode>
            <box hibit="26" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="25" width="4" name="op1" usename="1">
              <c colspan="4">1111</c>
            </box>
            <box hibit="21" width="2" name="op2" usename="1">
              <c colspan="2">00</c>
            </box>
            <box hibit="14" width="3" name="op3" usename="1">
              <c colspan="3">0x0</c>
            </box>
            <box hibit="10" width="3" name="op4" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="5" width="1" name="op5" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="eret">
          <header>Exception return</header>
          <decode>
            <box hibit="26" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="25" width="4" name="op1" usename="1">
              <c colspan="4">1111</c>
            </box>
            <box hibit="21" width="2" name="op2" usename="1">
              <c colspan="2">01</c>
            </box>
            <box hibit="14" width="3" name="op3" usename="1">
              <c colspan="3">0x0</c>
            </box>
            <box hibit="10" width="3" name="op4" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="5" width="1" name="op5" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="mrs_spec">
          <header>MRS (special)</header>
          <decode>
            <box hibit="26" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="25" width="4" name="op1" usename="1">
              <c colspan="4">1111</c>
            </box>
            <box hibit="21" width="2" name="op2" usename="1">
              <c colspan="2">1x</c>
            </box>
            <box hibit="14" width="3" name="op3" usename="1">
              <c colspan="3">0x0</c>
            </box>
            <box hibit="10" width="3" name="op4" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="5" width="1" name="op5" usename="1">
              <c colspan="1">0</c>
            </box>
          </decode>
        </node>
        <node iclass="mrs_bank">
          <header>MRS (banked)</header>
          <decode>
            <box hibit="26" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="25" width="4" name="op1" usename="1">
              <c colspan="4">1111</c>
            </box>
            <box hibit="21" width="2" name="op2" usename="1">
              <c colspan="2">1x</c>
            </box>
            <box hibit="14" width="3" name="op3" usename="1">
              <c colspan="3">0x0</c>
            </box>
            <box hibit="10" width="3" name="op4" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="5" width="1" name="op5" usename="1">
              <c colspan="1">1</c>
            </box>
          </decode>
        </node>
        <node iclass="dcps">
          <header>DCPS</header>
          <decode>
            <box hibit="26" width="1" name="op0" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="25" width="4" name="op1" usename="1">
              <c colspan="4">1110</c>
            </box>
            <box hibit="21" width="2" name="op2" usename="1">
              <c colspan="2">00</c>
            </box>
            <box hibit="14" width="3" name="op3" usename="1">
              <c colspan="3">000</c>
            </box>
            <box hibit="10" width="3" name="op4" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="5" width="1" name="op5" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_66" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="26" width="1" name="op0" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="25" width="4" name="op1" usename="1">
              <c colspan="4">1110</c>
            </box>
            <box hibit="21" width="2" name="op2" usename="1">
              <c colspan="2">00</c>
            </box>
            <box hibit="14" width="3" name="op3" usename="1">
              <c colspan="3">010</c>
            </box>
            <box hibit="10" width="3" name="op4" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="5" width="1" name="op5" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_67" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="26" width="1" name="op0" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="25" width="4" name="op1" usename="1">
              <c colspan="4">1110</c>
            </box>
            <box hibit="21" width="2" name="op2" usename="1">
              <c colspan="2">01</c>
            </box>
            <box hibit="14" width="3" name="op3" usename="1">
              <c colspan="3">0x0</c>
            </box>
            <box hibit="10" width="3" name="op4" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="5" width="1" name="op5" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_68" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="26" width="1" name="op0" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="25" width="4" name="op1" usename="1">
              <c colspan="4">1110</c>
            </box>
            <box hibit="21" width="2" name="op2" usename="1">
              <c colspan="2">1x</c>
            </box>
            <box hibit="14" width="3" name="op3" usename="1">
              <c colspan="3">0x0</c>
            </box>
            <box hibit="10" width="3" name="op4" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="5" width="1" name="op5" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_69" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="26" width="1" name="op0" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="25" width="4" name="op1" usename="1">
              <c colspan="4">1111</c>
            </box>
            <box hibit="21" width="2" name="op2" usename="1">
              <c colspan="2">0x</c>
            </box>
            <box hibit="14" width="3" name="op3" usename="1">
              <c colspan="3">0x0</c>
            </box>
            <box hibit="10" width="3" name="op4" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="5" width="1" name="op5" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="except">
          <header>Exception generation</header>
          <decode>
            <box hibit="26" width="1" name="op0" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="25" width="4" name="op1" usename="1">
              <c colspan="4">1111</c>
            </box>
            <box hibit="21" width="2" name="op2" usename="1">
              <c colspan="2">1x</c>
            </box>
            <box hibit="14" width="3" name="op3" usename="1">
              <c colspan="3">0x0</c>
            </box>
            <box hibit="10" width="3" name="op4" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="5" width="1" name="op5" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="bcond">
          <header>Conditional branch</header>
          <decode>
            <box hibit="26" width="1" name="op0" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="25" width="4" name="op1" usename="1">
              <c colspan="4">!= 111x</c>
            </box>
            <box hibit="21" width="2" name="op2" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="14" width="3" name="op3" usename="1">
              <c colspan="3">0x0</c>
            </box>
            <box hibit="10" width="3" name="op4" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="5" width="1" name="op5" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="b">
          <header>Unconditional branch</header>
          <decode>
            <box hibit="26" width="1" name="op0" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="25" width="4" name="op1" usename="1">
              <c colspan="4" />
            </box>
            <box hibit="21" width="2" name="op2" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="14" width="3" name="op3" usename="1">
              <c colspan="3">0x1</c>
            </box>
            <box hibit="10" width="3" name="op4" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="5" width="1" name="op5" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="blx">
          <header>Unconditional branch and link exchange</header>
          <decode>
            <box hibit="26" width="1" name="op0" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="25" width="4" name="op1" usename="1">
              <c colspan="4" />
            </box>
            <box hibit="21" width="2" name="op2" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="14" width="3" name="op3" usename="1">
              <c colspan="3">1x0</c>
            </box>
            <box hibit="10" width="3" name="op4" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="5" width="1" name="op5" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
        <node iclass="bl">
          <header>Unconditional branch and link</header>
          <decode>
            <box hibit="26" width="1" name="op0" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="25" width="4" name="op1" usename="1">
              <c colspan="4" />
            </box>
            <box hibit="21" width="2" name="op2" usename="1">
              <c colspan="2" />
            </box>
            <box hibit="14" width="3" name="op3" usename="1">
              <c colspan="3">1x1</c>
            </box>
            <box hibit="10" width="3" name="op4" usename="1">
              <c colspan="3" />
            </box>
            <box hibit="5" width="1" name="op5" usename="1">
              <c colspan="1" />
            </box>
          </decode>
        </node>
      </node>
      <node iclass="dpint_immm">
        <header>Data-processing (modified immediate)</header>
        <decode>
          <box hibit="28" width="4" name="op0" usename="1">
            <c colspan="4">10x0</c>
          </box>
          <box hibit="24" width="5" name="op1" usename="1">
            <c colspan="5" />
          </box>
          <box hibit="15" width="1" name="op3" usename="1">
            <c colspan="1">0</c>
          </box>
        </decode>
      </node>
      <node groupname="imm">
        <header>Data-processing (plain binary immediate)</header>
        <decode>
          <box hibit="28" width="4" name="op0" usename="1">
            <c colspan="4">10x1</c>
          </box>
          <box hibit="24" width="5" name="op1" usename="1">
            <c colspan="5">xxxx0</c>
          </box>
          <box hibit="15" width="1" name="op3" usename="1">
            <c colspan="1">0</c>
          </box>
        </decode>
        <regdiagram form="16x2">
          <box hibit="31" width="5">
            <c colspan="5">11110</c>
          </box>
          <box hibit="26" width="1">
            <c colspan="1" />
          </box>
          <box hibit="25" width="1">
            <c colspan="1">1</c>
          </box>
          <box hibit="24" width="1" name="op0" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="23" width="1">
            <c colspan="1" />
          </box>
          <box hibit="22" width="2" name="op1" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="20" width="1">
            <c colspan="1">0</c>
          </box>
          <box hibit="19" width="4">
            <c colspan="4" />
          </box>
          <box hibit="15" width="1">
            <c colspan="1">0</c>
          </box>
          <box hibit="14" width="15">
            <c colspan="15" />
          </box>
        </regdiagram>
        <node iclass="dpint_imms">
          <header>Data-processing (simple immediate)</header>
          <decode>
            <box hibit="24" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="22" width="2" name="op1" usename="1">
              <c colspan="2">0x</c>
            </box>
          </decode>
        </node>
        <node iclass="movw">
          <header>Move Wide (16-bit immediate)</header>
          <decode>
            <box hibit="24" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="22" width="2" name="op1" usename="1">
              <c colspan="2">10</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_53" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="22" width="2" name="op1" usename="1">
              <c colspan="2">11</c>
            </box>
          </decode>
        </node>
        <node iclass="sat_bit">
          <header>Saturate, Bitfield</header>
          <decode>
            <box hibit="24" width="1" name="op0" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="22" width="2" name="op1" usename="1">
              <c colspan="2" />
            </box>
          </decode>
        </node>
      </node>
      <node iclass="unalloc" unallocated="1">
        <header>UNALLOCATED</header>
        <decode>
          <box hibit="28" width="4" name="op0" usename="1">
            <c colspan="4">10x1</c>
          </box>
          <box hibit="24" width="5" name="op1" usename="1">
            <c colspan="5">xxxx1</c>
          </box>
          <box hibit="15" width="1" name="op3" usename="1">
            <c colspan="1">0</c>
          </box>
        </decode>
      </node>
      <node groupname="vldst">
        <header>Advanced SIMD element or structure load/store</header>
        <decode>
          <box hibit="28" width="4" name="op0" usename="1">
            <c colspan="4">1100</c>
          </box>
          <box hibit="24" width="5" name="op1" usename="1">
            <c colspan="5">1xxx0</c>
          </box>
          <box hibit="15" width="1" name="op3" usename="1">
            <c colspan="1" />
          </box>
        </decode>
        <regdiagram form="16x2">
          <box hibit="31" width="8">
            <c colspan="8">11111001</c>
          </box>
          <box hibit="23" width="1" name="op0" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="22" width="2">
            <c colspan="2" />
          </box>
          <box hibit="20" width="1">
            <c colspan="1">0</c>
          </box>
          <box hibit="19" width="8">
            <c colspan="8" />
          </box>
          <box hibit="11" width="2" name="op1" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="9" width="10">
            <c colspan="10" />
          </box>
        </regdiagram>
        <node iclass="asimldstms">
          <header>Advanced SIMD load/store multiple structures</header>
          <decode>
            <box hibit="23" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="11" width="2" name="op1" usename="1">
              <c colspan="2" />
            </box>
          </decode>
        </node>
        <node iclass="asimldall">
          <header>Advanced SIMD load single structure to all lanes</header>
          <decode>
            <box hibit="23" width="1" name="op0" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="11" width="2" name="op1" usename="1">
              <c colspan="2">11</c>
            </box>
          </decode>
        </node>
        <node iclass="asimldstss">
          <header>Advanced SIMD load/store single structure to one lane</header>
          <decode>
            <box hibit="23" width="1" name="op0" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="11" width="2" name="op1" usename="1">
              <c colspan="2">!= 11</c>
            </box>
          </decode>
        </node>
      </node>
      <node groupname="ldst">
        <header>Load/store single</header>
        <decode>
          <box hibit="28" width="4" name="op0" usename="1">
            <c colspan="4">1100</c>
          </box>
          <box hibit="24" width="5" name="op1" usename="1">
            <c colspan="5">!= 1xxx0</c>
          </box>
          <box hibit="15" width="1" name="op3" usename="1">
            <c colspan="1" />
          </box>
        </decode>
        <regdiagram form="16x2">
          <box hibit="31" width="7">
            <c colspan="7">1111100</c>
          </box>
          <box hibit="24" width="2" name="op0" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="22" width="2">
            <c colspan="2" />
          </box>
          <box hibit="20" width="1" name="op1" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="19" width="4" name="op2" usename="1">
            <c colspan="4" />
          </box>
          <box hibit="15" width="4">
            <c colspan="4" />
          </box>
          <box hibit="11" width="6" name="op3" usename="1">
            <c colspan="6" />
          </box>
          <box hibit="5" width="6">
            <c colspan="6" />
          </box>
        </regdiagram>
        <decode_constraints>
          <decode_constraint name="op0&lt;1&gt;:op1" op="!=" val="10" />
        </decode_constraints>
        <node iclass="ldst_unsigned_reg">
          <header>Load/store, unsigned (register offset)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">00</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6">000000</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_90" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">00</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6">000001</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_91" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">00</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6">00001x</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_92" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">00</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6">0001xx</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_93" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">00</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6">001xxx</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_94" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">00</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6">01xxxx</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_99" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">00</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6">10x0xx</c>
            </box>
          </decode>
        </node>
        <node iclass="ldst_unsigned_post">
          <header>Load/store, unsigned (immediate, post-indexed)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">00</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6">10x1xx</c>
            </box>
          </decode>
        </node>
        <node iclass="ldst_unsigned_nimm">
          <header>Load/store, unsigned (negative immediate)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">00</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6">1100xx</c>
            </box>
          </decode>
        </node>
        <node iclass="ldst_unsigned_unpriv">
          <header>Load/store, unsigned (unprivileged)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">00</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6">1110xx</c>
            </box>
          </decode>
        </node>
        <node iclass="ldst_unsigned_pre">
          <header>Load/store, unsigned (immediate, pre-indexed)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">00</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6">11x1xx</c>
            </box>
          </decode>
        </node>
        <node iclass="ldst_unsigned_pimm">
          <header>Load/store, unsigned (positive immediate)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">01</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6" />
            </box>
          </decode>
        </node>
        <node iclass="ldlit_unsigned">
          <header>Load, unsigned (literal)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">0x</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6" />
            </box>
          </decode>
        </node>
        <node iclass="ldst_signed_reg">
          <header>Load/store, signed (register offset)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6">000000</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_77" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6">000001</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_78" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6">00001x</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_79" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6">0001xx</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_80" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6">001xxx</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_81" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6">01xxxx</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_86" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6">10x0xx</c>
            </box>
          </decode>
        </node>
        <node iclass="ldst_signed_post">
          <header>Load/store, signed (immediate, post-indexed)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6">10x1xx</c>
            </box>
          </decode>
        </node>
        <node iclass="ldst_signed_nimm">
          <header>Load/store, signed (negative immediate)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6">1100xx</c>
            </box>
          </decode>
        </node>
        <node iclass="ldst_signed_unpriv">
          <header>Load/store, signed (unprivileged)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6">1110xx</c>
            </box>
          </decode>
        </node>
        <node iclass="ldst_signed_pre">
          <header>Load/store, signed (immediate, pre-indexed)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">10</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6">11x1xx</c>
            </box>
          </decode>
        </node>
        <node iclass="ldst_signed_pimm">
          <header>Load/store, signed (positive immediate)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">11</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6" />
            </box>
          </decode>
        </node>
        <node iclass="ldlit_signed">
          <header>Load, signed (literal)</header>
          <decode>
            <box hibit="24" width="2" name="op0" usename="1">
              <c colspan="2">1x</c>
            </box>
            <box hibit="20" width="1" name="op1" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="19" width="4" name="op2" usename="1">
              <c colspan="4">1111</c>
            </box>
            <box hibit="11" width="6" name="op3" usename="1">
              <c colspan="6" />
            </box>
          </decode>
        </node>
      </node>
      <node groupname="reg">
        <header>Data-processing (register)</header>
        <decode>
          <box hibit="28" width="4" name="op0" usename="1">
            <c colspan="4">1101</c>
          </box>
          <box hibit="24" width="5" name="op1" usename="1">
            <c colspan="5">0xxxx</c>
          </box>
          <box hibit="15" width="1" name="op3" usename="1">
            <c colspan="1" />
          </box>
        </decode>
        <regdiagram form="16x2">
          <box hibit="31" width="8">
            <c colspan="8">11111010</c>
          </box>
          <box hibit="23" width="1" name="op0" usename="1">
            <c colspan="1" />
          </box>
          <box hibit="22" width="7">
            <c colspan="7" />
          </box>
          <box hibit="15" width="4" name="op1" usename="1">
            <c colspan="4" />
          </box>
          <box hibit="11" width="4">
            <c colspan="4" />
          </box>
          <box hibit="7" width="4" name="op2" usename="1">
            <c colspan="4" />
          </box>
          <box hibit="3" width="4">
            <c colspan="4" />
          </box>
        </regdiagram>
        <node iclass="shiftr">
          <header>Register shifts</header>
          <decode>
            <box hibit="23" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="15" width="4" name="op1" usename="1">
              <c colspan="4">1111</c>
            </box>
            <box hibit="7" width="4" name="op2" usename="1">
              <c colspan="4">0000</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_105" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="23" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="15" width="4" name="op1" usename="1">
              <c colspan="4">1111</c>
            </box>
            <box hibit="7" width="4" name="op2" usename="1">
              <c colspan="4">0001</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_106" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="23" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="15" width="4" name="op1" usename="1">
              <c colspan="4">1111</c>
            </box>
            <box hibit="7" width="4" name="op2" usename="1">
              <c colspan="4">001x</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_107" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="23" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="15" width="4" name="op1" usename="1">
              <c colspan="4">1111</c>
            </box>
            <box hibit="7" width="4" name="op2" usename="1">
              <c colspan="4">01xx</c>
            </box>
          </decode>
        </node>
        <node iclass="extendr">
          <header>Register extends</header>
          <decode>
            <box hibit="23" width="1" name="op0" usename="1">
              <c colspan="1">0</c>
            </box>
            <box hibit="15" width="4" name="op1" usename="1">
              <c colspan="4">1111</c>
            </box>
            <box hibit="7" width="4" name="op2" usename="1">
              <c colspan="4">1xxx</c>
            </box>
          </decode>
        </node>
        <node iclass="addsub_par">
          <header>Parallel add-subtract</header>
          <decode>
            <box hibit="23" width="1" name="op0" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="15" width="4" name="op1" usename="1">
              <c colspan="4">1111</c>
            </box>
            <box hibit="7" width="4" name="op2" usename="1">
              <c colspan="4">0xxx</c>
            </box>
          </decode>
        </node>
        <node iclass="dpint_2r">
          <header>Data-processing (two source registers)</header>
          <decode>
            <box hibit="23" width="1" name="op0" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="15" width="4" name="op1" usename="1">
              <c colspan="4">1111</c>
            </box>
            <box hibit="7" width="4" name="op2" usename="1">
              <c colspan="4">10xx</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_111" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="23" width="1" name="op0" usename="1">
              <c colspan="1">1</c>
            </box>
            <box hibit="15" width="4" name="op1" usename="1">
              <c colspan="4">1111</c>
            </box>
            <box hibit="7" width="4" name="op2" usename="1">
              <c colspan="4">11xx</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_103" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="23" width="1" name="op0" usename="1">
              <c colspan="1" />
            </box>
            <box hibit="15" width="4" name="op1" usename="1">
              <c colspan="4">!= 1111</c>
            </box>
            <box hibit="7" width="4" name="op2" usename="1">
              <c colspan="4" />
            </box>
          </decode>
        </node>
      </node>
      <node groupname="mul">
        <header>Multiply, multiply accumulate, and absolute difference</header>
        <decode>
          <box hibit="28" width="4" name="op0" usename="1">
            <c colspan="4">1101</c>
          </box>
          <box hibit="24" width="5" name="op1" usename="1">
            <c colspan="5">10xxx</c>
          </box>
          <box hibit="15" width="1" name="op3" usename="1">
            <c colspan="1" />
          </box>
        </decode>
        <regdiagram form="16x2">
          <box hibit="31" width="9">
            <c colspan="9">111110110</c>
          </box>
          <box hibit="22" width="15">
            <c colspan="15" />
          </box>
          <box hibit="7" width="2" name="op0" usename="1">
            <c colspan="2" />
          </box>
          <box hibit="5" width="6">
            <c colspan="6" />
          </box>
        </regdiagram>
        <node iclass="mul_abd">
          <header>Multiply and absolute difference</header>
          <decode>
            <box hibit="7" width="2" name="op0" usename="1">
              <c colspan="2">00</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_113" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="7" width="2" name="op0" usename="1">
              <c colspan="2">01</c>
            </box>
          </decode>
        </node>
        <node iclass="UNALLOCATED_114" unallocated="1">
          <header>UNALLOCATED</header>
          <decode>
            <box hibit="7" width="2" name="op0" usename="1">
              <c colspan="2">1x</c>
            </box>
          </decode>
        </node>
      </node>
      <node iclass="lmul_div">
        <header>Long multiply and divide</header>
        <decode>
          <box hibit="28" width="4" name="op0" usename="1">
            <c colspan="4">1101</c>
          </box>
          <box hibit="24" width="5" name="op1" usename="1">
            <c colspan="5">11xxx</c>
          </box>
          <box hibit="15" width="1" name="op3" usename="1">
            <c colspan="1" />
          </box>
        </decode>
      </node>
    </node>
  </hierarchy>
  <groups heading="Top-level Encoding Groups">
    <maintable class="grouptable" size="16x2" howmanybits="32">
      <col bitno="31" colno="1" printwidth="0.019in" />
      <col bitno="30" colno="2" printwidth="0.019in" />
      <col bitno="29" colno="3" printwidth="0.019in" />
      <col bitno="28" colno="4" printwidth="0.019in" />
      <col bitno="27" colno="5" printwidth="0.019in" />
      <col bitno="26" colno="6" printwidth="0.019in" />
      <col bitno="25" colno="7" printwidth="0.019in" />
      <col bitno="24" colno="8" printwidth="0.019in" />
      <col bitno="23" colno="9" printwidth="0.019in" />
      <col bitno="22" colno="10" printwidth="0.019in" />
      <col bitno="21" colno="11" printwidth="0.019in" />
      <col bitno="20" colno="12" printwidth="0.019in" />
      <col bitno="19" colno="13" printwidth="0.019in" />
      <col bitno="18" colno="14" printwidth="0.019in" />
      <col bitno="17" colno="15" printwidth="0.019in" />
      <col bitno="16" colno="16" printwidth="0.019in" />
      <col bitno="15" colno="17" printwidth="0.019in" />
      <col bitno="14" colno="18" printwidth="0.019in" />
      <col bitno="13" colno="19" printwidth="0.019in" />
      <col bitno="12" colno="20" printwidth="0.019in" />
      <col bitno="11" colno="21" printwidth="0.019in" />
      <col bitno="10" colno="22" printwidth="0.019in" />
      <col bitno="9" colno="23" printwidth="0.019in" />
      <col bitno="8" colno="24" printwidth="0.019in" />
      <col bitno="7" colno="25" printwidth="0.019in" />
      <col bitno="6" colno="26" printwidth="0.019in" />
      <col bitno="5" colno="27" printwidth="0.019in" />
      <col bitno="4" colno="28" printwidth="0.019in" />
      <col bitno="3" colno="29" printwidth="0.019in" />
      <col bitno="2" colno="30" printwidth="0.019in" />
      <col bitno="1" colno="31" printwidth="0.019in" />
      <col bitno="0" colno="32" printwidth="0.019in" />
      <col colno="33" printwidth="0.400in" />
      <tableheader>
        <tr class="header1">
          <th colno="1" colspan="32">Instruction bits</th>
          <th colno="33" rowspan="2">Encoding Group</th>
        </tr>
        <tr class="header2-morebits">
          <th class="boxleft">15</th>
          <th>14</th>
          <th>13</th>
          <th>12</th>
          <th>11</th>
          <th>10</th>
          <th>9</th>
          <th>8</th>
          <th>7</th>
          <th>6</th>
          <th>5</th>
          <th>4</th>
          <th>3</th>
          <th>2</th>
          <th>1</th>
          <th>0</th>
          <th>15</th>
          <th>14</th>
          <th>13</th>
          <th>12</th>
          <th>11</th>
          <th>10</th>
          <th>9</th>
          <th>8</th>
          <th>7</th>
          <th>6</th>
          <th>5</th>
          <th>4</th>
          <th>3</th>
          <th>2</th>
          <th>1</th>
          <th class="boxright">0</th>
        </tr>
      </tableheader>
      <tablebody>
        <tr class="maintable" size="16" groupid="main" groupname="n">
          <td colspan="3" class="boxleft">!= 111</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td colspan="16" class="t16-padding"></td>
          <td class="iclassname">
            <a>16-bit</a>
          </td>
        </tr>
        <tr class="maintable" size="16" groupid="main" iclass="ub">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td colspan="16" class="t16-padding"></td>
          <td class="iclassname">
            <a classid="ub">16-bit Unconditional Branch</a>
          </td>
        </tr>
        <tr class="maintable" size="16x2" groupid="main" groupname="w">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td colspan="2">!= 00</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a>32-bit</a>
          </td>
        </tr>
        <tr class="maintable" size="16" groupid="n" iclass="sftdpi">
          <td class="boxleft">0</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td colspan="16" class="t16-padding"></td>
          <td class="iclassname">
            <a classid="sftdpi">16-bit / Shift (immediate), add, subtract, move, and compare</a>
          </td>
        </tr>
        <tr class="maintable" size="16" groupid="n" iclass="dp">
          <td class="boxleft">0</td>
          <td>1</td>
          <td>0</td>
          <td>0</td>
          <td>0</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td colspan="16" class="t16-padding"></td>
          <td class="iclassname">
            <a classid="dp">16-bit / Data-processing</a>
          </td>
        </tr>
        <tr class="maintable" size="16" groupid="n" iclass="spcd">
          <td class="boxleft">0</td>
          <td>1</td>
          <td>0</td>
          <td>0</td>
          <td>0</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td colspan="16" class="t16-padding"></td>
          <td class="iclassname">
            <a classid="spcd">16-bit / Special data instructions and branch and exchange</a>
          </td>
        </tr>
        <tr class="maintable" size="16" groupid="n" iclass="ldrl">
          <td class="boxleft">0</td>
          <td>1</td>
          <td>0</td>
          <td>0</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td colspan="16" class="t16-padding"></td>
          <td class="iclassname">
            <a classid="ldrl">16-bit / Load from Literal Pool</a>
          </td>
        </tr>
        <tr class="maintable" size="16" groupid="n" iclass="ldstr">
          <td class="boxleft">0</td>
          <td>1</td>
          <td>0</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td colspan="16" class="t16-padding"></td>
          <td class="iclassname">
            <a classid="ldstr">16-bit / Load/store single (register)</a>
          </td>
        </tr>
        <tr class="maintable" size="16" groupid="n" iclass="ldstwb">
          <td class="boxleft">0</td>
          <td>1</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td colspan="16" class="t16-padding"></td>
          <td class="iclassname">
            <a classid="ldstwb">16-bit / Load/store single word and unsigned byte (immediate)</a>
          </td>
        </tr>
        <tr class="maintable" size="16" groupid="n" iclass="ldsthw">
          <td class="boxleft">1</td>
          <td>0</td>
          <td>0</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td colspan="16" class="t16-padding"></td>
          <td class="iclassname">
            <a classid="ldsthw">16-bit / Load/store single halfword (immediate)</a>
          </td>
        </tr>
        <tr class="maintable" size="16" groupid="n" iclass="ldstsp">
          <td class="boxleft">1</td>
          <td>0</td>
          <td>0</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td colspan="16" class="t16-padding"></td>
          <td class="iclassname">
            <a classid="ldstsp">16-bit / Load/store single (SP-relative)</a>
          </td>
        </tr>
        <tr class="maintable" size="16" groupid="n" iclass="adradds">
          <td class="boxleft">1</td>
          <td>0</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td colspan="16" class="t16-padding"></td>
          <td class="iclassname">
            <a classid="adradds">16-bit / ADR and ADD (SP plus register)</a>
          </td>
        </tr>
        <tr class="maintable" size="16" groupid="n" iclass="misc16">
          <td class="boxleft">1</td>
          <td>0</td>
          <td>1</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td colspan="16" class="t16-padding"></td>
          <td class="iclassname">
            <a classid="misc16">16-bit / Miscellaneous 16-bit instructions</a>
          </td>
        </tr>
        <tr class="maintable" size="16" groupid="n" iclass="ldstmg">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>0</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td colspan="16" class="t16-padding"></td>
          <td class="iclassname">
            <a classid="ldstmg">16-bit / Load/Store multiple registers</a>
          </td>
        </tr>
        <tr class="maintable" size="16" groupid="n" iclass="brc">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>0</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td colspan="16" class="t16-padding"></td>
          <td class="iclassname">
            <a classid="brc">16-bit / Conditional branch, and Supervisor Call</a>
          </td>
        </tr>
        <tr class="maintable" size="16x2" groupid="w" iclass="dstm">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td>1</td>
          <td>0</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="dstm">32-bit / Load/store multiple</a>
          </td>
        </tr>
        <tr class="maintable" size="16x2" groupid="w" iclass="dstd">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td>1</td>
          <td>0</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="dstd">32-bit / Load/store dual, load/store exclusive, load-acquire/store-release, and table branch</a>
          </td>
        </tr>
        <tr class="maintable" size="16x2" groupid="w" iclass="shfr">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td>1</td>
          <td>0</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="shfr">32-bit / Data-processing (shifted register)</a>
          </td>
        </tr>
        <tr class="maintable" size="16x2" groupid="w" iclass="modi">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="modi">32-bit / Data-processing (modified immediate)</a>
          </td>
        </tr>
        <tr class="maintable" size="16x2" groupid="w" iclass="imm">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="imm">32-bit / Data-processing (plain binary immediate)</a>
          </td>
        </tr>
        <tr class="maintable" undef="1" groupid="w" iclass="unalloc">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">32-bit / UNALLOCATED</td>
        </tr>
        <tr class="maintable" size="16x2" groupid="w" iclass="bcrtrl">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="bcrtrl">32-bit / Branches and miscellaneous control</a>
          </td>
        </tr>
        <tr class="maintable" size="16x2" groupid="w" iclass="ldst">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td>0</td>
          <td colspan="5">!= 1xxx0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="ldst">32-bit / Load/store single</a>
          </td>
        </tr>
        <tr class="maintable" size="16x2" groupid="w" iclass="vldst">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td>0</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="vldst">32-bit / Advanced SIMD element or structure load/store</a>
          </td>
        </tr>
        <tr class="maintable" size="16x2" groupid="w" iclass="reg">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="reg">32-bit / Data-processing (register)</a>
          </td>
        </tr>
        <tr class="maintable" size="16x2" groupid="w" iclass="mul">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="mul">32-bit / Multiply, multiply accumulate, and absolute difference</a>
          </td>
        </tr>
        <tr class="maintable" size="16x2" groupid="w" iclass="lmul">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="lmul">32-bit / Long multiply, long multiply accumulate, and divide</a>
          </td>
        </tr>
        <tr class="maintable" size="16x2" groupid="w" groupname="cpaf">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td></td>
          <td>1</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a>32-bit / System register access, Advanced SIMD, and floating-point</a>
          </td>
        </tr>
        <tr class="maintable" undef="1" groupid="cpaf" iclass="unalloc_cops1">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td></td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">32-bit / System register access, Advanced SIMD, and floating-point / UNALLOCATED</td>
        </tr>
        <tr class="maintable" undef="1" groupid="cpaf" iclass="unalloc_cops2">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td></td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">32-bit / System register access, Advanced SIMD, and floating-point / UNALLOCATED</td>
        </tr>
        <tr class="maintable" size="16x2" groupid="cpaf" iclass="sysldst_mov64">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="sysldst_mov64">32-bit / System register access, Advanced SIMD, and floating-point / Advanced SIMD and System register load/store and 64-bit move</a>
          </td>
        </tr>
        <tr class="maintable" size="16x2" groupid="cpaf" iclass="fpdp">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="fpdp">32-bit / System register access, Advanced SIMD, and floating-point / Floating-point data-processing</a>
          </td>
        </tr>
        <tr class="maintable" undef="1" groupid="cpaf" iclass="unalloc_cops_3">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">32-bit / System register access, Advanced SIMD, and floating-point / UNALLOCATED</td>
        </tr>
        <tr class="maintable" size="16x2" groupid="cpaf" iclass="sys_mov32">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="sys_mov32">32-bit / System register access, Advanced SIMD, and floating-point / Advanced SIMD and System register 32-bit move</a>
          </td>
        </tr>
        <tr class="maintable" size="16x2" groupid="cpaf" iclass="advsimdext">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td colspan="2">!= 11</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="advsimdext">32-bit / System register access, Advanced SIMD, and floating-point / Additional Advanced SIMD and floating-point instructions</a>
          </td>
        </tr>
        <tr class="maintable" size="16x2" groupid="cpaf" groupname="simddp">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td></td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a>32-bit / System register access, Advanced SIMD, and floating-point / Advanced SIMD data-processing</a>
          </td>
        </tr>
        <tr class="maintable" size="16x2" groupid="simddp" iclass="t_simd_3r_same">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td></td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="t_simd_3r_same">32-bit / System register access, Advanced SIMD, and floating-point / Advanced SIMD data-processing / Advanced SIMD three registers of the same length</a>
          </td>
        </tr>
        <tr class="maintable" size="16x2" groupid="simddp" iclass="t_simd_mulreg">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td></td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>0</td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="t_simd_mulreg">32-bit / System register access, Advanced SIMD, and floating-point / Advanced SIMD data-processing / Advanced SIMD two registers, or three registers of different lengths</a>
          </td>
        </tr>
        <tr class="maintable" size="16x2" groupid="simddp" iclass="t_simd_12reg">
          <td class="boxleft">1</td>
          <td>1</td>
          <td>1</td>
          <td></td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td></td>
          <td>1</td>
          <td></td>
          <td></td>
          <td></td>
          <td class="boxright"></td>
          <td class="iclassname">
            <a classid="t_simd_12reg">32-bit / System register access, Advanced SIMD, and floating-point / Advanced SIMD data-processing / Advanced SIMD shifts and immediate generation</a>
          </td>
        </tr>
      </tablebody>
    </maintable>
  </groups>
  <maintable class="allclasses" size="16x2" howmanybits="32">
    <col bitno="31" colno="1" printwidth="0.019in" />
    <col bitno="30" colno="2" printwidth="0.019in" />
    <col bitno="29" colno="3" printwidth="0.019in" />
    <col bitno="28" colno="4" printwidth="0.019in" />
    <col bitno="27" colno="5" printwidth="0.019in" />
    <col bitno="26" colno="6" printwidth="0.019in" />
    <col bitno="25" colno="7" printwidth="0.019in" />
    <col bitno="24" colno="8" printwidth="0.019in" />
    <col bitno="23" colno="9" printwidth="0.019in" />
    <col bitno="22" colno="10" printwidth="0.019in" />
    <col bitno="21" colno="11" printwidth="0.019in" />
    <col bitno="20" colno="12" printwidth="0.019in" />
    <col bitno="19" colno="13" printwidth="0.019in" />
    <col bitno="18" colno="14" printwidth="0.019in" />
    <col bitno="17" colno="15" printwidth="0.019in" />
    <col bitno="16" colno="16" printwidth="0.019in" />
    <col bitno="15" colno="17" printwidth="0.019in" />
    <col bitno="14" colno="18" printwidth="0.019in" />
    <col bitno="13" colno="19" printwidth="0.019in" />
    <col bitno="12" colno="20" printwidth="0.019in" />
    <col bitno="11" colno="21" printwidth="0.019in" />
    <col bitno="10" colno="22" printwidth="0.019in" />
    <col bitno="9" colno="23" printwidth="0.019in" />
    <col bitno="8" colno="24" printwidth="0.019in" />
    <col bitno="7" colno="25" printwidth="0.019in" />
    <col bitno="6" colno="26" printwidth="0.019in" />
    <col bitno="5" colno="27" printwidth="0.019in" />
    <col bitno="4" colno="28" printwidth="0.019in" />
    <col bitno="3" colno="29" printwidth="0.019in" />
    <col bitno="2" colno="30" printwidth="0.019in" />
    <col bitno="1" colno="31" printwidth="0.019in" />
    <col bitno="0" colno="32" printwidth="0.019in" />
    <col colno="33" printwidth="0.400in" />
    <tableheader>
      <tr class="header1">
        <th colno="1" colspan="32">Instruction bits</th>
        <th colno="33" rowspan="2">Instruction class</th>
      </tr>
      <tr class="header2-morebits">
        <th class="boxleft">15</th>
        <th>14</th>
        <th>13</th>
        <th>12</th>
        <th>11</th>
        <th>10</th>
        <th>9</th>
        <th>8</th>
        <th>7</th>
        <th>6</th>
        <th>5</th>
        <th>4</th>
        <th>3</th>
        <th>2</th>
        <th>1</th>
        <th>0</th>
        <th>15</th>
        <th>14</th>
        <th>13</th>
        <th>12</th>
        <th>11</th>
        <th>10</th>
        <th>9</th>
        <th>8</th>
        <th>7</th>
        <th>6</th>
        <th>5</th>
        <th>4</th>
        <th>3</th>
        <th>2</th>
        <th>1</th>
        <th class="boxright">0</th>
      </tr>
    </tableheader>
    <tablebody>
      <tr class="maintable" size="16x2" iclass="tsimd_dotprod">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="tsimd_dotprod">Advanced SIMD and floating-point dot product</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="dcps">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="dcps">DCPS</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="shiftr">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="shiftr">Register shifts</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="ldst_unsigned_unpriv">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldst_unsigned_unpriv">Load/store, unsigned (unprivileged)</a>
        </td>
      </tr>
      <tr class="maintable" size="16" iclass="ldst16_imm">
        <td class="boxleft">0</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="ldst16_imm">Load/store word/byte (immediate offset)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="fp_2r">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="fp_2r">Floating-point data-processing (two registers)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="lmul_div">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="lmul_div">Long multiply and divide</a>
        </td>
      </tr>
      <tr class="maintable" size="16" iclass="bcond16">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td colspan="4">!= 111x</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="bcond16">Conditional branch</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="simd_ext">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simd_ext">Advanced SIMD vector extract</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_79">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td>1</td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" iclass="ldst_unsigned_nimm">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldst_unsigned_nimm">Load/store, unsigned (negative immediate)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="asimldall">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="asimldall">Advanced SIMD load single structure to all lanes</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_99">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_106">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_123">
        <td class="boxleft"></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16" iclass="pushpop16">
        <td class="boxleft">1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="pushpop16">Push and Pop</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="ldst_signed_pimm">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td>1</td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldst_signed_pimm">Load/store, signed (positive immediate)</a>
        </td>
      </tr>
      <tr class="maintable" size="16" iclass="ldlit16">
        <td class="boxleft">0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="ldlit16">Load literal</a>
        </td>
      </tr>
      <tr class="maintable" size="16" iclass="ext16">
        <td class="boxleft">1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="ext16">Extend</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="system">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="system">Miscellaneous system</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_136">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" iclass="fp_msr">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="fp_msr">Floating-point move special register</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="fp_mov32">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="fp_mov32">Floating-point 32-bit move</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_80">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td>1</td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" iclass="tfloatdpmac">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="tfloatdpmac">Advanced SIMD and floating-point multiply with accumulate</a>
        </td>
      </tr>
      <tr class="maintable" size="16" iclass="addsub16_2h">
        <td class="boxleft">0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td colspan="2">!= 11</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="addsub16_2h">Add, subtract, compare, move (two high registers)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="simd_dup_sc">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simd_dup_sc">Advanced SIMD duplicate (scalar)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="ldstex_bhd">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldstex_bhd">Load/store exclusive byte/half/dual</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="fp_movi">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="fp_movi">Floating-point move immediate</a>
        </td>
      </tr>
      <tr class="maintable" size="16" iclass="except16">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="except16">Exception generation</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="fp_minmax">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td colspan="2">!= 00</td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="fp_minmax">Floating-point minNum/maxNum</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="cp_mov32">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="cp_mov32">System register 32-bit move</a>
        </td>
      </tr>
      <tr class="maintable" size="16" iclass="ldst16_reg">
        <td class="boxleft">0</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="ldst16_reg">Load/store (register offset)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="dpint_2r">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="dpint_2r">Data-processing (two source registers)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_113">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" iclass="simd_dup_el">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simd_dup_el">Advanced SIMD 8/16/32-bit element move/duplicate</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="simd_tbl">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simd_tbl">Advanced SIMD table permute</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="fp_3r">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td colspan="4">!= 1x11</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="fp_3r">Floating-point data-processing (three registers)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_132">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" iclass="ldstex">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldstex">Load/store exclusive</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_77">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td>1</td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16" iclass="b16">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="b16">Unconditional branch</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="eret">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="eret">Exception return</a>
        </td>
      </tr>
      <tr class="maintable" size="16" iclass="addsub16_1l_imm">
        <td class="boxleft">0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="addsub16_1l_imm">Add, subtract, compare, move (one low register and immediate)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="ldlit_unsigned">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldlit_unsigned">Load, unsigned (literal)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="blx">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="blx">Unconditional branch and link exchange</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_133">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" iclass="dpint_imms">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="dpint_imms">Data-processing (simple immediate)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_93">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" iclass="simd_3sameext">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simd_3sameext">Advanced SIMD three registers of the same length extension</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_114">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16" iclass="rev16">
        <td class="boxleft">1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td colspan="2">!= 10</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="rev16">Reverse bytes</a>
        </td>
      </tr>
      <tr class="maintable" size="16" iclass="addsub16_3l">
        <td class="boxleft">0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="addsub16_3l">Add, subtract (three low registers)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_92">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" iclass="mul_abd">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="mul_abd">Multiply and absolute difference</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="dpint_immm">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="dpint_immm">Data-processing (modified immediate)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="ldst_signed_pre">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td>1</td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldst_signed_pre">Load/store, signed (immediate, pre-indexed)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="ldst_unsigned_pre">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldst_unsigned_pre">Load/store, unsigned (immediate, pre-indexed)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="ldstm">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldstm">Load/store multiple</a>
        </td>
      </tr>
      <tr class="maintable" size="16" undef="1" iclass="UNALLOCATED_27">
        <td class="boxleft">1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_81">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td>1</td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16" iclass="adjsp16">
        <td class="boxleft">1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="adjsp16">Adjust SP (immediate)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_116">
        <td class="boxleft"></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_86">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td>1</td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_130">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" iclass="addsub_par">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="addsub_par">Parallel add-subtract</a>
        </td>
      </tr>
      <tr class="maintable" size="16" iclass="dpint16_2l">
        <td class="boxleft">0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="dpint16_2l">Data-processing (two low registers)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_67">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" iclass="ldst_unsigned_reg">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldst_unsigned_reg">Load/store, unsigned (register offset)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_90">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" iclass="lddlit">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td hover="** != 00">*</td>
        <td></td>
        <td>1</td>
        <td hover="** != 00">*</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="lddlit">Load dual (literal)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_105">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16" iclass="addpcsp16">
        <td class="boxleft">1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="addpcsp16">Add PC/SP (immediate)</a>
        </td>
      </tr>
      <tr class="maintable" size="16" iclass="addsub16_2l_imm">
        <td class="boxleft">0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="addsub16_2l_imm">Add, subtract (two low registers and immediate)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="simd_1r_imm">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simd_1r_imm">Advanced SIMD one register and modified immediate</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="tblbr">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="tblbr">Table branch</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_127">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_45">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" iclass="ldstd_pre">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldstd_pre">Load/store dual (immediate, pre-indexed)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="mrs_spec">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="mrs_spec">MRS (special)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_66">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" iclass="ldstd_imm">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldstd_imm">Load/store dual (immediate)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="ldastl">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldastl">Load-acquire / Store-release</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="movw">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="movw">Move Wide (16-bit immediate)</a>
        </td>
      </tr>
      <tr class="maintable" size="16" iclass="ldst16_sp">
        <td class="boxleft">1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="ldst16_sp">Load/store (SP-relative)</a>
        </td>
      </tr>
      <tr class="maintable" size="16" iclass="cps16">
        <td class="boxleft">1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="cps16">Change Processor State</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="b">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="b">Unconditional branch</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="simdfp_mov64">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simdfp_mov64">Advanced SIMD and floating-point 64-bit move</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_53">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_103">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_131">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16" iclass="bkpt16">
        <td class="boxleft">1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="bkpt16">Software breakpoint</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="ldlit_signed">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldlit_signed">Load, signed (literal)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="cp_mov64">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="cp_mov64">System register 64-bit move</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="bx_jaz">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="bx_jaz">Branch and Exchange Jazelle</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="hints">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="hints">Hints</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="ldstd_post">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldstd_post">Load/store dual (immediate, post-indexed)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="simd_2r_misc">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simd_2r_misc">Advanced SIMD two registers misc</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="msr_bank">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="msr_bank">MSR (banked)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_107">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" iclass="ldst_unsigned_post">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldst_unsigned_post">Load/store, unsigned (immediate, post-indexed)</a>
        </td>
      </tr>
      <tr class="maintable" size="16" iclass="shift16_imm">
        <td class="boxleft">0</td>
        <td>0</td>
        <td>0</td>
        <td colspan="2">!= 11</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="shift16_imm">Shift (immediate)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="ldst_signed_post">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td>1</td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldst_signed_post">Load/store, signed (immediate, post-indexed)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_111">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" iclass="asimldstss">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="2">!= 11</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="asimldstss">Advanced SIMD load/store single structure to one lane</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="msr_spec">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="msr_spec">MSR (special)</a>
        </td>
      </tr>
      <tr class="maintable" size="16" undef="1" iclass="UNALLOCATED_26">
        <td class="boxleft">1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_69">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16" iclass="cbznz16">
        <td class="boxleft">1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="cbznz16">Compare and branch zero/non-zero</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="fp_mov16">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="fp_mov16">Floating-point 16-bit move</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="simd_3diff">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td colspan="2">!= 11</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simd_3diff">Advanced SIMD three registers of different lengths</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="simd_2r_sc">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td colspan="2">!= 11</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simd_2r_sc">Advanced SIMD two registers and a scalar</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_120">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16" iclass="ldstm16">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="ldstm16">Load/store multiple</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="ldst_signed_reg">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td>1</td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldst_signed_reg">Load/store, signed (register offset)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="simdfp_ldst">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td colspan="4">!= 00x0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simdfp_ldst">Advanced SIMD and floating-point load/store</a>
        </td>
      </tr>
      <tr class="maintable" size="16" iclass="it16">
        <td class="boxleft">1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="4">!= 0000</td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="it16">If-Then</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="simd_3same">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simd_3same">Advanced SIMD three registers of the same length</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="asimldstms">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="asimldstms">Advanced SIMD load/store multiple structures</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="dpint_shiftr">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="dpint_shiftr">Data-processing (shifted register)</a>
        </td>
      </tr>
      <tr class="maintable" size="16" iclass="ldsth16_imm">
        <td class="boxleft">1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="ldsth16_imm">Load/store halfword (immediate offset)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="bcond">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td colspan="4">!= 111x</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="bcond">Conditional branch</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_94">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16" iclass="bx16">
        <td class="boxleft">0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="bx16">Branch and exchange</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="cp_ldst">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td colspan="4">!= 00x0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="cp_ldst">System register Load/Store</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_78">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td>1</td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" iclass="except">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="except">Exception generation</a>
        </td>
      </tr>
      <tr class="maintable" size="16" iclass="hlt16">
        <td class="boxleft">1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="hlt16">Halting breakpoint</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="extendr">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="extendr">Register extends</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="simd_2r_shift">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td colspan="15">!= 000xxxxxxxxxxx0</td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="simd_2r_shift">Advanced SIMD two registers and shift amount</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="ldst_unsigned_pimm">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldst_unsigned_pimm">Load/store, unsigned (positive immediate)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_68">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" iclass="ldst_signed_unpriv">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td>1</td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldst_signed_unpriv">Load/store, signed (unprivileged)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="mrs_bank">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="mrs_bank">MRS (banked)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="fp_toint">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td colspan="2">!= 00</td>
        <td></td>
        <td>1</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="fp_toint">Floating-point directed convert to integer</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="fp_csel">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td colspan="2">!= 00</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="fp_csel">Floating-point conditional select</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="fp_extins">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td colspan="2">!= 00</td>
        <td></td>
        <td>1</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="fp_extins">Floating-point extraction and insertion</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="cps">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>0</td>
        <td></td>
        <td colspan="3">!= 000</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="cps">Change processor state</a>
        </td>
      </tr>
      <tr class="maintable" size="16" undef="1" iclass="UNALLOCATED_24">
        <td class="boxleft">1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16" undef="1" iclass="UNALLOCATED_28">
        <td class="boxleft">1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16x2" iclass="sat_bit">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="sat_bit">Saturate, Bitfield</a>
        </td>
      </tr>
      <tr class="maintable" size="16" iclass="hints16">
        <td class="boxleft">1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="hints16">Hints</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" undef="1" iclass="UNALLOCATED_91">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">UNALLOCATED</td>
      </tr>
      <tr class="maintable" size="16" iclass="setpan16">
        <td class="boxleft">1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td colspan="16" class="t16-padding"></td>
        <td class="iclassname">
          <a classid="setpan16">SETPAN</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="ldst_signed_nimm">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td>1</td>
        <td colspan="4">!= 1111</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="ldst_signed_nimm">Load/store, signed (negative immediate)</a>
        </td>
      </tr>
      <tr class="maintable" size="16x2" iclass="bl">
        <td class="boxleft">1</td>
        <td>1</td>
        <td>1</td>
        <td>1</td>
        <td>0</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td>1</td>
        <td>1</td>
        <td></td>
        <td>1</td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td></td>
        <td class="boxright"></td>
        <td class="iclassname">
          <a classid="bl">Unconditional branch and link</a>
        </td>
      </tr>
    </tablebody>
  </maintable>
  <funcgroupheader id="sftdpi">Shift (immediate), add, subtract, move, and compare</funcgroupheader>
  <iclass_sect id="addsub16_3l" title="Add, subtract (three low registers)">
    <regdiagram form="16" psname="">
      <box hibit="31" width="6" settings="6">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="25" name="S" usename="1">
        <c></c>
      </box>
      <box hibit="24" width="3" name="Rm" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="21" width="3" name="Rn" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="18" width="3" name="Rd" usename="1">
        <c colspan="3"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="addsub16_3l" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="22*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">S</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="ADD_r_T1" iformfile="add_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="ADD_r">ADD, ADDS (register)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="SUB_r_T1" iformfile="sub_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="SUB_r">SUB, SUBS (register)</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="addsub16_2l_imm" title="Add, subtract (two low registers and immediate)">
    <regdiagram form="16" psname="">
      <box hibit="31" width="6" settings="6">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="25" name="S" usename="1">
        <c></c>
      </box>
      <box hibit="24" width="3" name="imm3" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="21" width="3" name="Rn" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="18" width="3" name="Rd" usename="1">
        <c colspan="3"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="addsub16_2l_imm" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="23*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">S</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="ADD_i_T1" iformfile="add_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="ADD_i">ADD, ADDS (immediate)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="SUB_i_T1" iformfile="sub_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="SUB_i">SUB, SUBS (immediate)</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="addsub16_1l_imm" title="Add, subtract, compare, move (one low register and immediate)">
    <regdiagram form="16" psname="">
      <box hibit="31" width="3" settings="3">
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="28" width="2" name="op" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="26" width="3" name="Rd" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="23" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="addsub16_1l_imm" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="23*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">op</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="MOV_i_T1" iformfile="mov_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="MOV_i">MOV, MOVS (immediate)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="CMP_i_T1" iformfile="cmp_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="CMP_i">CMP (immediate)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="ADD_i_T2" iformfile="add_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="ADD_i">ADD, ADDS (immediate)</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="SUB_i_T2" iformfile="sub_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="SUB_i">SUB, SUBS (immediate)</td>
          <td class="enctags">T2</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="shift16_imm" title="Shift (immediate)">
    <regdiagram form="16" psname="" tworows="1">
      <box hibit="31" width="3" settings="3">
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="28" width="2" name="op" usename="1" settings="2" constraint="!= 11">
        <c colspan="2">!= 11</c>
      </box>
      <box hibit="26" width="5" name="imm5" usename="1">
        <c colspan="5"></c>
      </box>
      <box hibit="21" width="3" name="Rm" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="18" width="3" name="Rd" usename="1">
        <c colspan="3"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="op" op="!=" val="11" />
      <decode_constraint name="op" op="!=" val="11" />
    </decode_constraints>
    <instructiontable iclass="shift16_imm" cols="2">
      <col colno="1" printwidth="22*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="MOV_r_T2" iformfile="mov_r.xml" first="t" last="t">
          <td class="iformname" iformid="MOV_r">MOV, MOVS (register)</td>
          <td class="enctags">T2</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="dp">Data-processing</funcgroupheader>
  <iclass_sect id="dpint16_2l" title="Data-processing (two low registers)">
    <regdiagram form="16" psname="">
      <box hibit="31" width="6" settings="6">
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="25" width="4" name="op" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="21" width="3" name="Rs" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="18" width="3" name="Rd" usename="1">
        <c colspan="3"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="dpint16_2l" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="39*" />
      <col colno="3" printwidth="28*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">op</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="AND_r_T1" iformfile="and_r.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0000</td>
          <td class="iformname" iformid="AND_r">AND, ANDS (register)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="EOR_r_T1" iformfile="eor_r.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0001</td>
          <td class="iformname" iformid="EOR_r">EOR, EORS (register)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="MOV_rr_T1_LSL" iformfile="mov_rr.xml" label="logical shift left" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0010</td>
          <td class="iformname" iformid="MOV_rr">MOV, MOVS (register-shifted register)</td>
          <td class="enctags">T1, Logical shift left</td>
        </tr>
        <tr class="instructiontable" encname="MOV_rr_T1_LSR" iformfile="mov_rr.xml" label="logical shift right" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0011</td>
          <td class="iformname" iformid="MOV_rr">MOV, MOVS (register-shifted register)</td>
          <td class="enctags">T1, Logical shift right</td>
        </tr>
        <tr class="instructiontable" encname="MOV_rr_T1_ASR" iformfile="mov_rr.xml" label="arithmetic shift right" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0100</td>
          <td class="iformname" iformid="MOV_rr">MOV, MOVS (register-shifted register)</td>
          <td class="enctags">T1, Arithmetic shift right</td>
        </tr>
        <tr class="instructiontable" encname="ADC_r_T1" iformfile="adc_r.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0101</td>
          <td class="iformname" iformid="ADC_r">ADC, ADCS (register)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="SBC_r_T1" iformfile="sbc_r.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0110</td>
          <td class="iformname" iformid="SBC_r">SBC, SBCS (register)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="MOV_rr_T1_ROR" iformfile="mov_rr.xml" label="rotate right" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0111</td>
          <td class="iformname" iformid="MOV_rr">MOV, MOVS (register-shifted register)</td>
          <td class="enctags">T1, Rotate right</td>
        </tr>
        <tr class="instructiontable" encname="TST_r_T1" iformfile="tst_r.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">1000</td>
          <td class="iformname" iformid="TST_r">TST (register)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="RSB_i_T1" iformfile="rsb_i.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">1001</td>
          <td class="iformname" iformid="RSB_i">RSB, RSBS (immediate)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="CMP_r_T1" iformfile="cmp_r.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">1010</td>
          <td class="iformname" iformid="CMP_r">CMP (register)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="CMN_r_T1" iformfile="cmn_r.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">1011</td>
          <td class="iformname" iformid="CMN_r">CMN (register)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="ORR_r_T1" iformfile="orr_r.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">1100</td>
          <td class="iformname" iformid="ORR_r">ORR, ORRS (register)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="MUL_T1" iformfile="mul.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="MUL">MUL, MULS</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="BIC_r_T1" iformfile="bic_r.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">1110</td>
          <td class="iformname" iformid="BIC_r">BIC, BICS (register)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="MVN_r_T1" iformfile="mvn_r.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="MVN_r">MVN, MVNS (register)</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="spcd">Special data instructions and branch and exchange</funcgroupheader>
  <iclass_sect id="addsub16_2h" title="Add, subtract, compare, move (two high registers)">
    <regdiagram form="16" psname="" tworows="1">
      <box hibit="31" width="6" settings="6">
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="25" width="2" name="op" usename="1" settings="2" constraint="!= 11">
        <c colspan="2">!= 11</c>
      </box>
      <box hibit="23" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="22" width="4" name="Rs" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="18" width="3" name="Rd" usename="1">
        <c colspan="3"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="op" op="!=" val="11" />
      <decode_constraint name="op" op="!=" val="11" />
    </decode_constraints>
    <instructiontable iclass="addsub16_2h" cols="5">
      <col colno="1" printwidth="4*" />
      <col colno="2" printwidth="9*" />
      <col colno="3" printwidth="9*" />
      <col colno="4" printwidth="30*" />
      <col colno="5" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">op</th>
          <th class="bitfields">D:Rd</th>
          <th class="bitfields">Rs</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="ADD_r_T2" iformfile="add_r.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="8" class="bitfield">!= 1101</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td class="iformname" iformid="ADD_r">ADD, ADDS (register)</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encoding="t1" iformfile="add_sp_r.xml" label="T1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="8" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="ADD_SP_r">ADD, ADDS (SP plus register)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encoding="t2" iformfile="add_sp_r.xml" label="T2" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="8" class="bitfield">1101</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td class="iformname" iformid="ADD_SP_r">ADD, ADDS (SP plus register)</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="CMP_r_T2" iformfile="cmp_r.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="8" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="CMP_r">CMP (register)</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="MOV_r_T1" iformfile="mov_r.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="8" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="MOV_r">MOV, MOVS (register)</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="bx16" title="Branch and exchange">
    <regdiagram form="16" psname="">
      <box hibit="31" width="8" settings="8">
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="23" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="22" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="18" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="17" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="16" settings="1">
        <c>(0)</c>
      </box>
    </regdiagram>
    <instructiontable iclass="bx16" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="BX_T1" iformfile="bx.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="BX">BX</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="BLX_r_T1" iformfile="blx_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="BLX_r">BLX (register)</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="ldrl">Load from Literal Pool</funcgroupheader>
  <iclass_sect id="ldlit16" title="Load literal">
    <regdiagram form="16" psname="">
      <box hibit="31" width="5" settings="5">
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="26" width="3" name="Rt" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="23" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="ldlit16" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="LDR_l_T1" iformfile="ldr_l.xml" first="t" last="t">
          <td class="iformname" iformid="LDR_l">LDR (literal)</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="ldstr">Load/store single (register)</funcgroupheader>
  <iclass_sect id="ldst16_reg" title="Load/store (register offset)">
    <regdiagram form="16" psname="">
      <box hibit="31" width="4" settings="4">
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="27" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="26" name="B" usename="1">
        <c></c>
      </box>
      <box hibit="25" name="H" usename="1">
        <c></c>
      </box>
      <box hibit="24" width="3" name="Rm" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="21" width="3" name="Rn" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="18" width="3" name="Rt" usename="1">
        <c colspan="3"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="ldst16_reg" cols="5">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="3*" />
      <col colno="4" printwidth="18*" />
      <col colno="5" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
          <th class="bitfields">B</th>
          <th class="bitfields">H</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="STR_r_T1" iformfile="str_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STR_r">STR (register)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="STRH_r_T1" iformfile="strh_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="STRH_r">STRH (register)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="STRB_r_T1" iformfile="strb_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STRB_r">STRB (register)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDRSB_r_T1" iformfile="ldrsb_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDRSB_r">LDRSB (register)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDR_r_T1" iformfile="ldr_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="LDR_r">LDR (register)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDRH_r_T1" iformfile="ldrh_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDRH_r">LDRH (register)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDRB_r_T1" iformfile="ldrb_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="LDRB_r">LDRB (register)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDRSH_r_T1" iformfile="ldrsh_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDRSH_r">LDRSH (register)</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="ldstwb">Load/store single word and unsigned byte (immediate)</funcgroupheader>
  <iclass_sect id="ldst16_imm" title="Load/store word/byte (immediate offset)">
    <regdiagram form="16" psname="">
      <box hibit="31" width="3" settings="3">
        <c>0</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="28" name="B" usename="1">
        <c></c>
      </box>
      <box hibit="27" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="26" width="5" name="imm5" usename="1">
        <c colspan="5"></c>
      </box>
      <box hibit="21" width="3" name="Rn" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="18" width="3" name="Rt" usename="1">
        <c colspan="3"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="ldst16_imm" cols="4">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="18*" />
      <col colno="4" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">B</th>
          <th class="bitfields">L</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="STR_i_T1" iformfile="str_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STR_i">STR (immediate)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDR_i_T1" iformfile="ldr_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDR_i">LDR (immediate)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="STRB_i_T1" iformfile="strb_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STRB_i">STRB (immediate)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDRB_i_T1" iformfile="ldrb_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDRB_i">LDRB (immediate)</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="ldsthw">Load/store single halfword (immediate)</funcgroupheader>
  <iclass_sect id="ldsth16_imm" title="Load/store halfword (immediate offset)">
    <regdiagram form="16" psname="">
      <box hibit="31" width="4" settings="4">
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="27" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="26" width="5" name="imm5" usename="1">
        <c colspan="5"></c>
      </box>
      <box hibit="21" width="3" name="Rn" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="18" width="3" name="Rt" usename="1">
        <c colspan="3"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="ldsth16_imm" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="STRH_i_T1" iformfile="strh_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STRH_i">STRH (immediate)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDRH_i_T1" iformfile="ldrh_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDRH_i">LDRH (immediate)</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="ldstsp">Load/store single (SP-relative)</funcgroupheader>
  <iclass_sect id="ldst16_sp" title="Load/store (SP-relative)">
    <regdiagram form="16" psname="">
      <box hibit="31" width="4" settings="4">
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="27" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="26" width="3" name="Rt" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="23" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="ldst16_sp" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="STR_i_T2" iformfile="str_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STR_i">STR (immediate)</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="LDR_i_T2" iformfile="ldr_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDR_i">LDR (immediate)</td>
          <td class="enctags">T2</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="adradds">ADR and ADD (SP plus register)</funcgroupheader>
  <iclass_sect id="addpcsp16" title="Add PC/SP (immediate)">
    <regdiagram form="16" psname="">
      <box hibit="31" width="4" settings="4">
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="27" name="SP" usename="1">
        <c></c>
      </box>
      <box hibit="26" width="3" name="Rd" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="23" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="addpcsp16" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="31*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">SP</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="ADR_T1" iformfile="adr.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="ADR">ADR</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="ADD_SP_i_T1" iformfile="add_sp_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="ADD_SP_i">ADD, ADDS (SP plus immediate)</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="misc16">Miscellaneous 16-bit instructions</funcgroupheader>
  <iclass_sect id="adjsp16" title="Adjust SP (immediate)">
    <regdiagram form="16" psname="">
      <box hibit="31" width="8" settings="8">
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="23" name="S" usename="1">
        <c></c>
      </box>
      <box hibit="22" width="7" name="imm7" usename="1">
        <c colspan="7"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="adjsp16" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="32*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">S</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="ADD_SP_i_T2" iformfile="add_sp_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="ADD_SP_i">ADD, ADDS (SP plus immediate)</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="SUB_SP_i_T1" iformfile="sub_sp_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="SUB_SP_i">SUB, SUBS (SP minus immediate)</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="cps16" title="Change Processor State">
    <regdiagram form="16" psname="">
      <box hibit="31" width="10" settings="10">
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="21" name="op" usename="1">
        <c></c>
      </box>
      <box hibit="20" width="5" name="flags" usename="1">
        <c colspan="5"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="cps16" cols="4">
      <col colno="1" printwidth="4*" />
      <col colno="2" printwidth="7*" />
      <col colno="3" printwidth="19*" />
      <col colno="4" printwidth="23*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">op</th>
          <th class="bitfields">flags</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="SETEND_T1" iformfile="setend.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="5" class="bitfield"></td>
          <td class="iformname" iformid="SETEND">SETEND</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="CPSIE_T1_AS" iformfile="cps.xml" label="interrupt enable" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="5" class="bitfield">0xxxx</td>
          <td class="iformname" iformid="CPS">CPS, CPSID, CPSIE</td>
          <td class="enctags">T1, Interrupt enable</td>
        </tr>
        <tr class="instructiontable" encname="CPSID_T1_AS" iformfile="cps.xml" label="interrupt disable" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="5" class="bitfield">1xxxx</td>
          <td class="iformname" iformid="CPS">CPS, CPSID, CPSIE</td>
          <td class="enctags">T1, Interrupt disable</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="cbznz16" title="Compare and branch zero/non-zero">
    <regdiagram form="16" psname="">
      <box hibit="31" width="4" settings="4">
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="27" name="op" usename="1">
        <c></c>
      </box>
      <box hibit="26" settings="1">
        <c>0</c>
      </box>
      <box hibit="25" name="i" usename="1">
        <c></c>
      </box>
      <box hibit="24" settings="1">
        <c>1</c>
      </box>
      <box hibit="23" width="5" name="imm5" usename="1">
        <c colspan="5"></c>
      </box>
      <box hibit="18" width="3" name="Rn" usename="1">
        <c colspan="3"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="cbznz16" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="CBNZ_T1" iformfile="cbnz.xml" first="t" last="t">
          <td class="iformname" iformid="CBNZ">CBNZ, CBZ</td>
          <td class="enctags">CBNZ</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ext16" title="Extend">
    <regdiagram form="16" psname="">
      <box hibit="31" width="8" settings="8">
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="23" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="22" name="B" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="3" name="Rm" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="18" width="3" name="Rd" usename="1">
        <c colspan="3"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="ext16" cols="4">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="18*" />
      <col colno="4" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">U</th>
          <th class="bitfields">B</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="SXTH_T1" iformfile="sxth.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SXTH">SXTH</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="SXTB_T1" iformfile="sxtb.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="SXTB">SXTB</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UXTH_T1" iformfile="uxth.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="UXTH">UXTH</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UXTB_T1" iformfile="uxtb.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="UXTB">UXTB</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="hlt16" title="Halting breakpoint">
    <regdiagram form="16" psname="">
      <box hibit="31" width="10" settings="10">
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="21" width="6" name="imm6" usename="1">
        <c colspan="6"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="hlt16" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="HLT_T1" iformfile="hlt.xml" first="t" last="t">
          <td class="iformname" iformid="HLT">HLT</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="hints16" title="Hints">
    <regdiagram form="16" psname="">
      <box hibit="31" width="8" settings="8">
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="23" width="4" name="hint" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="19" width="4" settings="4">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
    </regdiagram>
    <instructiontable iclass="hints16" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="31*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">hint</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="NOP_T1" iformfile="nop.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0000</td>
          <td class="iformname" iformid="NOP">NOP</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="YIELD_T1" iformfile="yield.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0001</td>
          <td class="iformname" iformid="YIELD">YIELD</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="WFE_T1" iformfile="wfe.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0010</td>
          <td class="iformname" iformid="WFE">WFE</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="WFI_T1" iformfile="wfi.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0011</td>
          <td class="iformname" iformid="WFI">WFI</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="SEV_T1" iformfile="sev.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0100</td>
          <td class="iformname" iformid="SEV">SEV</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="SEVL_T1" iformfile="sevl.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0101</td>
          <td class="iformname" iformid="SEVL">SEVL</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_17_hints16" reserved_nop_hint="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">011x</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_18_hints16" reserved_nop_hint="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">1xxx</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="it16" title="If-Then">
    <regdiagram form="16" psname="" tworows="1">
      <box hibit="31" width="8" settings="8">
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="23" width="4" name="firstcond" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="19" width="4" name="mask" usename="1" settings="4" constraint="!= 0000">
        <c colspan="4">!= 0000</c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="mask" op="!=" val="0000" />
      <decode_constraint name="mask" op="!=" val="0000" />
    </decode_constraints>
    <instructiontable iclass="it16" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="IT_T1" iformfile="it.xml" first="t" last="t">
          <td class="iformname" iformid="IT">IT</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="pushpop16" title="Push and Pop">
    <regdiagram form="16" psname="">
      <box hibit="31" width="4" settings="4">
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="27" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="26" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="24" name="P" usename="1">
        <c></c>
      </box>
      <box hibit="23" width="8" name="register_list" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="pushpop16" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="PUSH_T1" iformfile="push.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="PUSH">PUSH</td>
        </tr>
        <tr class="instructiontable" encname="POP_T1" iformfile="pop.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="POP">POP</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="rev16" title="Reverse bytes">
    <regdiagram form="16" psname="" tworows="1">
      <box hibit="31" width="8" settings="8">
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="23" width="2" name="op" usename="1" settings="2" constraint="!= 10">
        <c colspan="2">!= 10</c>
      </box>
      <box hibit="21" width="3" name="Rm" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="18" width="3" name="Rd" usename="1">
        <c colspan="3"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="op" op="!=" val="10" />
      <decode_constraint name="op" op="!=" val="10" />
    </decode_constraints>
    <instructiontable iclass="rev16" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">op</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="REV_T1" iformfile="rev.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="REV">REV</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="REV16_T1" iformfile="rev16.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="REV16">REV16</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="REVSH_T1" iformfile="revsh.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="REVSH">REVSH</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="setpan16" title="SETPAN">
    <regdiagram form="16" psname="">
      <box hibit="31" width="11" settings="11">
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="20" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="19" name="imm1" usename="1">
        <c></c>
      </box>
      <box hibit="18" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="17" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="16" settings="1">
        <c>(0)</c>
      </box>
    </regdiagram>
    <instructiontable iclass="setpan16" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="SETPAN_T1" arch_version="FEAT_PAN" iformfile="setpan.xml" first="t" last="t">
          <td class="iformname" iformid="SETPAN">SETPAN</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="bkpt16" title="Software breakpoint">
    <regdiagram form="16" psname="">
      <box hibit="31" width="8" settings="8">
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="23" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="bkpt16" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="BKPT_T1" iformfile="bkpt.xml" first="t" last="t">
          <td class="iformname" iformid="BKPT">BKPT</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="ldstmg">Load/Store multiple registers</funcgroupheader>
  <iclass_sect id="ldstm16" title="Load/store multiple">
    <regdiagram form="16" psname="">
      <box hibit="31" width="4" settings="4">
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="27" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="26" width="3" name="Rn" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="23" width="8" name="register_list" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="ldstm16" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="19*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="STM_T1" iformfile="stm.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STM">STM, STMIA, STMEA</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDM_T1" iformfile="ldm.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDM">LDM, LDMIA, LDMFD</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="brc">Conditional branch, and Supervisor Call</funcgroupheader>
  <iclass_sect id="bcond16" title="Conditional branch">
    <regdiagram form="16" psname="">
      <box hibit="31" width="4" settings="4">
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="27" width="4" name="cond" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="23" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond&lt;3:1&gt;&lt;3:1&gt;" op="!=" val="111x" />
      <decode_constraint name="cond&lt;3:1&gt;&lt;3:1&gt;" op="!=" val="111x" />
    </decode_constraints>
    <instructiontable iclass="bcond16" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="B_T1" iformfile="b.xml" first="t" last="t">
          <td class="iformname" iformid="B">B</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="except16" title="Exception generation">
    <regdiagram form="16" psname="">
      <box hibit="31" width="7" settings="7">
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="24" name="S" usename="1">
        <c></c>
      </box>
      <box hibit="23" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="except16" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">S</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UDF_T1" iformfile="udf.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="UDF">UDF</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="SVC_T1" iformfile="svc.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="SVC">SVC</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="ub">16-bit Unconditional Branch</funcgroupheader>
  <iclass_sect id="b16" title="Unconditional branch">
    <regdiagram form="16" psname="">
      <box hibit="31" width="5" settings="5">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="26" width="11" name="imm11" usename="1">
        <c colspan="11"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="b16" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="B_T2" iformfile="b.xml" first="t" last="t">
          <td class="iformname" iformid="B">B</td>
          <td class="enctags">T2</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="dstm">Load/store multiple</funcgroupheader>
  <iclass_sect id="ldstm" title="Load/store multiple">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="7" settings="7">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="24" width="2" name="opc" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="22" settings="1">
        <c>0</c>
      </box>
      <box hibit="21" name="W" usename="1">
        <c></c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" name="P" usename="1">
        <c></c>
      </box>
      <box hibit="14" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="13" width="14" name="register_list" usename="1">
        <c colspan="14"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="ldstm" cols="4">
      <col colno="1" printwidth="5*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="33*" />
      <col colno="4" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">opc</th>
          <th class="bitfields">L</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encoding="t1" iformfile="srs.xml" label="T1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SRS">SRS, SRSDA, SRSDB, SRSIA, SRSIB</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encoding="t1" iformfile="rfe.xml" label="T1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="RFE">RFE, RFEDA, RFEDB, RFEIA, RFEIB</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="STM_T2" iformfile="stm.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STM">STM, STMIA, STMEA</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="LDM_T2" iformfile="ldm.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDM">LDM, LDMIA, LDMFD</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="STMDB_T1" iformfile="stmdb.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STMDB">STMDB, STMFD</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDMDB_T1" iformfile="ldmdb.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDMDB">LDMDB, LDMEA</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encoding="t2" iformfile="srs.xml" label="T2" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SRS">SRS, SRSDA, SRSDB, SRSIA, SRSIB</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encoding="t2" iformfile="rfe.xml" label="T2" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="RFE">RFE, RFEDA, RFEDB, RFEIA, RFEIB</td>
          <td class="enctags">T2</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="fpdp">Floating-point data-processing</funcgroupheader>
  <iclass_sect id="fp_3r" title="Floating-point data-processing (three registers)">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="8" settings="8">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="23" name="o0" usename="1">
        <c></c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" name="o1" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="9" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" name="o2" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="o0:D:o1" op="!=" val="1x11" />
    </decode_constraints>
    <instructiontable iclass="fp_3r" cols="5">
      <col colno="1" printwidth="8*" />
      <col colno="2" printwidth="6*" />
      <col colno="3" printwidth="4*" />
      <col colno="4" printwidth="23*" />
      <col colno="5" printwidth="29*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">o0:o1</th>
          <th class="bitfields">size</th>
          <th class="bitfields">o2</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_fp_3r" undef="1" first="t" last="t">
          <td bitwidth="4" class="bitfield">!= 111</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VMLA_f_T2_H" arch_version="FEAT_FP16" iformfile="vmla_f.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMLA_f">VMLA (floating-point)</td>
          <td class="enctags">T2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMLS_f_T2_H" arch_version="FEAT_FP16" iformfile="vmls_f.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMLS_f">VMLS (floating-point)</td>
          <td class="enctags">T2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMLA_f_T2_S" iformfile="vmla_f.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMLA_f">VMLA (floating-point)</td>
          <td class="enctags">T2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMLS_f_T2_S" iformfile="vmls_f.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMLS_f">VMLS (floating-point)</td>
          <td class="enctags">T2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMLA_f_T2_D" iformfile="vmla_f.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMLA_f">VMLA (floating-point)</td>
          <td class="enctags">T2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMLS_f_T2_D" iformfile="vmls_f.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMLS_f">VMLS (floating-point)</td>
          <td class="enctags">T2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNMLS_T1_H" arch_version="FEAT_FP16" iformfile="vnmls.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VNMLS">VNMLS</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNMLA_T1_H" arch_version="FEAT_FP16" iformfile="vnmla.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VNMLA">VNMLA</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNMLS_T1_S" iformfile="vnmls.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VNMLS">VNMLS</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNMLA_T1_S" iformfile="vnmla.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VNMLA">VNMLA</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNMLS_T1_D" iformfile="vnmls.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VNMLS">VNMLS</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNMLA_T1_D" iformfile="vnmla.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VNMLA">VNMLA</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMUL_f_T2_H" arch_version="FEAT_FP16" iformfile="vmul_f.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMUL_f">VMUL (floating-point)</td>
          <td class="enctags">T2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNMUL_T1_H" arch_version="FEAT_FP16" iformfile="vnmul.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VNMUL">VNMUL</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMUL_f_T2_S" iformfile="vmul_f.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMUL_f">VMUL (floating-point)</td>
          <td class="enctags">T2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNMUL_T1_S" iformfile="vnmul.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VNMUL">VNMUL</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMUL_f_T2_D" iformfile="vmul_f.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMUL_f">VMUL (floating-point)</td>
          <td class="enctags">T2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNMUL_T1_D" iformfile="vnmul.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VNMUL">VNMUL</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VADD_f_T2_H" arch_version="FEAT_FP16" iformfile="vadd_f.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VADD_f">VADD (floating-point)</td>
          <td class="enctags">T2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VSUB_f_T2_H" arch_version="FEAT_FP16" iformfile="vsub_f.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VSUB_f">VSUB (floating-point)</td>
          <td class="enctags">T2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VADD_f_T2_S" iformfile="vadd_f.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VADD_f">VADD (floating-point)</td>
          <td class="enctags">T2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VSUB_f_T2_S" iformfile="vsub_f.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VSUB_f">VSUB (floating-point)</td>
          <td class="enctags">T2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VADD_f_T2_D" iformfile="vadd_f.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VADD_f">VADD (floating-point)</td>
          <td class="enctags">T2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VSUB_f_T2_D" iformfile="vsub_f.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VSUB_f">VSUB (floating-point)</td>
          <td class="enctags">T2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VDIV_T1_H" arch_version="FEAT_FP16" iformfile="vdiv.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VDIV">VDIV</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VDIV_T1_S" iformfile="vdiv.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VDIV">VDIV</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VDIV_T1_D" iformfile="vdiv.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VDIV">VDIV</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFNMS_T1_H" arch_version="FEAT_FP16" iformfile="vfnms.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VFNMS">VFNMS</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFNMA_T1_H" arch_version="FEAT_FP16" iformfile="vfnma.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFNMA">VFNMA</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFNMS_T1_S" iformfile="vfnms.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VFNMS">VFNMS</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFNMA_T1_S" iformfile="vfnma.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFNMA">VFNMA</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFNMS_T1_D" iformfile="vfnms.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VFNMS">VFNMS</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFNMA_T1_D" iformfile="vfnma.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFNMA">VFNMA</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFMA_T2_H" arch_version="FEAT_FP16" iformfile="vfma.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VFMA">VFMA</td>
          <td class="enctags">T2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFMS_T2_H" arch_version="FEAT_FP16" iformfile="vfms.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFMS">VFMS</td>
          <td class="enctags">T2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFMA_T2_S" iformfile="vfma.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VFMA">VFMA</td>
          <td class="enctags">T2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFMS_T2_S" iformfile="vfms.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFMS">VFMS</td>
          <td class="enctags">T2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFMA_T2_D" iformfile="vfma.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VFMA">VFMA</td>
          <td class="enctags">T2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VFMS_T2_D" iformfile="vfms.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFMS">VFMS</td>
          <td class="enctags">T2, Double-precision scalar</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="fp_2r" title="Floating-point data-processing (two registers)">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="19" name="o1" usename="1">
        <c></c>
      </box>
      <box hibit="18" width="3" name="opc2" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="9" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="7" name="o3" usename="1">
        <c></c>
      </box>
      <box hibit="6" settings="1">
        <c>1</c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="fp_2r" cols="6">
      <col colno="1" printwidth="4*" />
      <col colno="2" printwidth="6*" />
      <col colno="3" printwidth="6*" />
      <col colno="4" printwidth="4*" />
      <col colno="5" printwidth="63*" />
      <col colno="6" printwidth="42*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">o1</th>
          <th class="bitfields">opc2</th>
          <th class="bitfields">size</th>
          <th class="bitfields">o3</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_fp_2r" undef="1" oneofthismnem="7" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_12_fp_2r" undef="1" oneofthismnem="7" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VABS_T2_H" arch_version="FEAT_FP16" iformfile="vabs.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VABS">VABS</td>
          <td class="enctags">T2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMOV_r_T2_S" iformfile="vmov_r.xml" label="single-precision scalar" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMOV_r">VMOV (register)</td>
          <td class="enctags">T2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VABS_T2_S" iformfile="vabs.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VABS">VABS</td>
          <td class="enctags">T2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMOV_r_T2_D" iformfile="vmov_r.xml" label="double-precision scalar" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMOV_r">VMOV (register)</td>
          <td class="enctags">T2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VABS_T2_D" iformfile="vabs.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VABS">VABS</td>
          <td class="enctags">T2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNEG_T2_H" arch_version="FEAT_FP16" iformfile="vneg.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VNEG">VNEG</td>
          <td class="enctags">T2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VSQRT_T1_H" arch_version="FEAT_FP16" iformfile="vsqrt.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VSQRT">VSQRT</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNEG_T2_S" iformfile="vneg.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VNEG">VNEG</td>
          <td class="enctags">T2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VSQRT_T1_S" iformfile="vsqrt.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VSQRT">VSQRT</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VNEG_T2_D" iformfile="vneg.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VNEG">VNEG</td>
          <td class="enctags">T2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VSQRT_T1_D" iformfile="vsqrt.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VSQRT">VSQRT</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_24_fp_2r" undef="1" oneofthismnem="7" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VCVTB_T1_SH" iformfile="vcvtb.xml" label="half-precision to single-precision" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVTB">VCVTB</td>
          <td class="enctags">T1, Half-precision to single-precision</td>
        </tr>
        <tr class="instructiontable" encname="VCVTT_T1_SH" iformfile="vcvtt.xml" label="half-precision to single-precision" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVTT">VCVTT</td>
          <td class="enctags">T1, Half-precision to single-precision</td>
        </tr>
        <tr class="instructiontable" encname="VCVTB_T1_DH" iformfile="vcvtb.xml" label="half-precision to double-precision" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVTB">VCVTB</td>
          <td class="enctags">T1, Half-precision to double-precision</td>
        </tr>
        <tr class="instructiontable" encname="VCVTT_T1_DH" iformfile="vcvtt.xml" label="half-precision to double-precision" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVTT">VCVTT</td>
          <td class="enctags">T1, Half-precision to double-precision</td>
        </tr>
        <tr class="instructiontable" encname="VCVTB_T1_bfs" arch_version="FEAT_AA32BF16" iformfile="vcvtb_bfs.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVTB_bfs">VCVTB (BFloat16)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VCVTT_T1_bfs" arch_version="FEAT_AA32BF16" iformfile="vcvtt_bfs.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVTT_bfs">VCVTT (BFloat16)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VCVTB_T1_HS" iformfile="vcvtb.xml" label="single-precision to half-precision" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVTB">VCVTB</td>
          <td class="enctags">T1, Single-precision to half-precision</td>
        </tr>
        <tr class="instructiontable" encname="VCVTT_T1_HS" iformfile="vcvtt.xml" label="single-precision to half-precision" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVTT">VCVTT</td>
          <td class="enctags">T1, Single-precision to half-precision</td>
        </tr>
        <tr class="instructiontable" encname="VCVTB_T1_HD" iformfile="vcvtb.xml" label="double-precision to half-precision" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVTB">VCVTB</td>
          <td class="enctags">T1, Double-precision to half-precision</td>
        </tr>
        <tr class="instructiontable" encname="VCVTT_T1_HD" iformfile="vcvtt.xml" label="double-precision to half-precision" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVTT">VCVTT</td>
          <td class="enctags">T1, Double-precision to half-precision</td>
        </tr>
        <tr class="instructiontable" encname="VCMP_T1_H" arch_version="FEAT_FP16" iformfile="vcmp.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCMP">VCMP</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCMPE_T1_H" arch_version="FEAT_FP16" iformfile="vcmpe.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCMPE">VCMPE</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCMP_T1_S" iformfile="vcmp.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCMP">VCMP</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCMPE_T1_S" iformfile="vcmpe.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCMPE">VCMPE</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCMP_T1_D" iformfile="vcmp.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCMP">VCMP</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCMPE_T1_D" iformfile="vcmpe.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCMPE">VCMPE</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCMP_T2_H" arch_version="FEAT_FP16" iformfile="vcmp.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCMP">VCMP</td>
          <td class="enctags">T2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCMPE_T2_H" arch_version="FEAT_FP16" iformfile="vcmpe.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCMPE">VCMPE</td>
          <td class="enctags">T2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCMP_T2_S" iformfile="vcmp.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCMP">VCMP</td>
          <td class="enctags">T2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCMPE_T2_S" iformfile="vcmpe.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCMPE">VCMPE</td>
          <td class="enctags">T2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCMP_T2_D" iformfile="vcmp.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCMP">VCMP</td>
          <td class="enctags">T2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCMPE_T2_D" iformfile="vcmpe.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCMPE">VCMPE</td>
          <td class="enctags">T2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTR_vfp_T1_H" arch_version="FEAT_FP16" iformfile="vrintr_vfp.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTR_vfp">VRINTR</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTZ_vfp_T1_H" arch_version="FEAT_FP16" iformfile="vrintz_vfp.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VRINTZ_vfp">VRINTZ (floating-point)</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTR_vfp_T1_S" iformfile="vrintr_vfp.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTR_vfp">VRINTR</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTZ_vfp_T1_S" iformfile="vrintz_vfp.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VRINTZ_vfp">VRINTZ (floating-point)</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTR_vfp_T1_D" iformfile="vrintr_vfp.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTR_vfp">VRINTR</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTZ_vfp_T1_D" iformfile="vrintz_vfp.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VRINTZ_vfp">VRINTZ (floating-point)</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTX_vfp_T1_H" arch_version="FEAT_FP16" iformfile="vrintx_vfp.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTX_vfp">VRINTX (floating-point)</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_56_fp_2r" undef="1" oneofthismnem="7" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VRINTX_vfp_T1_S" iformfile="vrintx_vfp.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTX_vfp">VRINTX (floating-point)</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_ds_T1" iformfile="vcvt_ds.xml" label="single-precision to double-precision" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVT_ds">VCVT (between double-precision and single-precision)</td>
          <td class="enctags">T1, Single-precision to double-precision</td>
        </tr>
        <tr class="instructiontable" encname="VRINTX_vfp_T1_D" iformfile="vrintx_vfp.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTX_vfp">VRINTX (floating-point)</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_sd_T1" iformfile="vcvt_ds.xml" label="double-precision to single-precision" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVT_ds">VCVT (between double-precision and single-precision)</td>
          <td class="enctags">T1, Double-precision to single-precision</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_vi_T1_H" arch_version="FEAT_FP16" iformfile="vcvt_vi.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVT_vi">VCVT (integer to floating-point, floating-point)</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_vi_T1_S" iformfile="vcvt_vi.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVT_vi">VCVT (integer to floating-point, floating-point)</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_vi_T1_D" iformfile="vcvt_vi.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVT_vi">VCVT (integer to floating-point, floating-point)</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_62_fp_2r" undef="1" oneofthismnem="7" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_63_fp_2r" undef="1" oneofthismnem="7" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_64_fp_2r" undef="1" oneofthismnem="7" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VJCVT_T1" arch_version="FEAT_JSCVT" iformfile="vjcvt.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VJCVT">VJCVT</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_toxv_T1_H" arch_version="FEAT_FP16" iformfile="vcvt_xv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">01x</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVT_xv">VCVT (between floating-point and fixed-point, floating-point)</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_toxv_T1_S" iformfile="vcvt_xv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">01x</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVT_xv">VCVT (between floating-point and fixed-point, floating-point)</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_toxv_T1_D" iformfile="vcvt_xv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">01x</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVT_xv">VCVT (between floating-point and fixed-point, floating-point)</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTR_uiv_T1_H" arch_version="FEAT_FP16" iformfile="vcvtr_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVTR_iv">VCVTR</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_uiv_T1_H" arch_version="FEAT_FP16" iformfile="vcvt_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVT_iv">VCVT (floating-point to integer, floating-point)</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTR_uiv_T1_S" iformfile="vcvtr_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVTR_iv">VCVTR</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_uiv_T1_S" iformfile="vcvt_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVT_iv">VCVT (floating-point to integer, floating-point)</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTR_uiv_T1_D" iformfile="vcvtr_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVTR_iv">VCVTR</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_uiv_T1_D" iformfile="vcvt_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVT_iv">VCVT (floating-point to integer, floating-point)</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTR_siv_T1_H" arch_version="FEAT_FP16" iformfile="vcvtr_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVTR_iv">VCVTR</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_siv_T1_H" arch_version="FEAT_FP16" iformfile="vcvt_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVT_iv">VCVT (floating-point to integer, floating-point)</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTR_siv_T1_S" iformfile="vcvtr_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVTR_iv">VCVTR</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_siv_T1_S" iformfile="vcvt_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVT_iv">VCVT (floating-point to integer, floating-point)</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTR_siv_T1_D" iformfile="vcvtr_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVTR_iv">VCVTR</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_siv_T1_D" iformfile="vcvt_iv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVT_iv">VCVT (floating-point to integer, floating-point)</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_xv_T1_H" arch_version="FEAT_FP16" iformfile="vcvt_xv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">11x</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVT_xv">VCVT (between floating-point and fixed-point, floating-point)</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_xv_T1_S" iformfile="vcvt_xv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">11x</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVT_xv">VCVT (between floating-point and fixed-point, floating-point)</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_xv_T1_D" iformfile="vcvt_xv.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="3" class="bitfield">11x</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVT_xv">VCVT (between floating-point and fixed-point, floating-point)</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="fp_movi" title="Floating-point move immediate">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="19" width="4" name="imm4H" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="9" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="7" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="6" settings="1">
        <c>0</c>
      </box>
      <box hibit="5" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="imm4L" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="fp_movi" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="29*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_fp_movi" undef="1" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VMOV_i_T2_H" arch_version="FEAT_FP16" iformfile="vmov_i.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="VMOV_i">VMOV (immediate)</td>
          <td class="enctags">T2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMOV_i_T2_S" iformfile="vmov_i.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="VMOV_i">VMOV (immediate)</td>
          <td class="enctags">T2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMOV_i_T2_D" iformfile="vmov_i.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="VMOV_i">VMOV (immediate)</td>
          <td class="enctags">T2, Double-precision scalar</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="dstd">Load/store dual, load/store exclusive, load-acquire/store-release, and table branch</funcgroupheader>
  <iclass_sect id="lddlit" title="Load dual (literal)">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="7" settings="7">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="24" name="P" usename="1">
        <c></c>
      </box>
      <box hibit="23" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="22" settings="1">
        <c>1</c>
      </box>
      <box hibit="21" name="W" usename="1">
        <c></c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" settings="4">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="Rt2" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="P:W" op="!=" val="0xx0" />
    </decode_constraints>
    <instructiontable iclass="lddlit" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="LDRD_l_T1" iformfile="ldrd_l.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDRD_l">LDRD (literal)</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldastl" title="Load-acquire / Store-release">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="11" settings="11">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="Rt2" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" settings="1">
        <c>1</c>
      </box>
      <box hibit="6" name="op" usename="1">
        <c></c>
      </box>
      <box hibit="5" width="2" name="sz" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="3" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="ldastl" cols="5">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="4*" />
      <col colno="3" printwidth="4*" />
      <col colno="4" printwidth="18*" />
      <col colno="5" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
          <th class="bitfields">op</th>
          <th class="bitfields">sz</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="STLB_T1" iformfile="stlb.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="STLB">STLB</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="STLH_T1" iformfile="stlh.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="STLH">STLH</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="STL_T1" iformfile="stl.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="STL">STL</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_14_ldastl" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="STLEXB_T1" iformfile="stlexb.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="STLEXB">STLEXB</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="STLEXH_T1" iformfile="stlexh.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="STLEXH">STLEXH</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="STLEX_T1" iformfile="stlex.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="STLEX">STLEX</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="STLEXD_T1" iformfile="stlexd.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="STLEXD">STLEXD</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDAB_T1" iformfile="ldab.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="LDAB">LDAB</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDAH_T1" iformfile="ldah.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="LDAH">LDAH</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDA_T1" iformfile="lda.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="LDA">LDA</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_22_ldastl" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="LDAEXB_T1" iformfile="ldaexb.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="LDAEXB">LDAEXB</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDAEXH_T1" iformfile="ldaexh.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="LDAEXH">LDAEXH</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDAEX_T1" iformfile="ldaex.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="LDAEX">LDAEX</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDAEXD_T1" iformfile="ldaexd.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="LDAEXD">LDAEXD</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldstd_imm" title="Load/store dual (immediate)">
    <regdiagram form="16x2" psname="" tworows="1">
      <box hibit="31" width="8" settings="8">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="23" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="22" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="Rt2" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="Rn" op="!=" val="1111" />
      <decode_constraint name="Rn" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="ldstd_imm" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="12*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="STRD_i_T1_off" iformfile="strd_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STRD_i">STRD (immediate)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="LDRD_i_T1_off" iformfile="ldrd_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDRD_i">LDRD (immediate)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldstd_post" title="Load/store dual (immediate, post-indexed)">
    <regdiagram form="16x2" psname="" tworows="1">
      <box hibit="31" width="8" settings="8">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="23" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="22" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="Rt2" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="Rn" op="!=" val="1111" />
      <decode_constraint name="Rn" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="ldstd_post" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="18*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="STRD_i_T1_post" iformfile="strd_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STRD_i">STRD (immediate)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRD_i_T1_post" iformfile="ldrd_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDRD_i">LDRD (immediate)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldstd_pre" title="Load/store dual (immediate, pre-indexed)">
    <regdiagram form="16x2" psname="" tworows="1">
      <box hibit="31" width="8" settings="8">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="23" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="22" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="Rt2" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="Rn" op="!=" val="1111" />
      <decode_constraint name="Rn" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="ldstd_pre" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="17*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="STRD_i_T1_pre" iformfile="strd_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STRD_i">STRD (immediate)</td>
          <td class="enctags">T1, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRD_i_T1_pre" iformfile="ldrd_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDRD_i">LDRD (immediate)</td>
          <td class="enctags">T1, Pre-indexed</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldstex" title="Load/store exclusive">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="11" settings="11">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="ldstex" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="STREX_T1" iformfile="strex.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STREX">STREX</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDREX_T1" iformfile="ldrex.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDREX">LDREX</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldstex_bhd" title="Load/store exclusive byte/half/dual">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="11" settings="11">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="Rt2" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" width="2" settings="2">
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="5" width="2" name="sz" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="3" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="ldstex_bhd" cols="4">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="4*" />
      <col colno="3" printwidth="18*" />
      <col colno="4" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
          <th class="bitfields">sz</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="STREXB_T1" iformfile="strexb.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="STREXB">STREXB</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="STREXH_T1" iformfile="strexh.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="STREXH">STREXH</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_13_ldstex_bhd" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="STREXD_T1" iformfile="strexd.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="STREXD">STREXD</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDREXB_T1" iformfile="ldrexb.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="LDREXB">LDREXB</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDREXH_T1" iformfile="ldrexh.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="LDREXH">LDREXH</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_17_ldstex_bhd" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="LDREXD_T1" iformfile="ldrexd.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="LDREXD">LDREXD</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="tblbr" title="Table branch">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="12" settings="12">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="14" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="13" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="12" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="11" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="10" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="9" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="8" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="7" width="3" settings="3">
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="4" name="H" usename="1">
        <c></c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="tblbr" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="TBH_T1" iformfile="tbb.xml" first="t" last="t">
          <td class="iformname" iformid="TBB">TBB, TBH</td>
          <td class="enctags">Halfword</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="sys_mov32">Advanced SIMD and System register 32-bit move</funcgroupheader>
  <iclass_sect id="simd_dup_el" title="Advanced SIMD 8/16/32-bit element move/duplicate">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="8" settings="8">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="23" width="3" name="opc1" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" settings="4">
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" width="2" name="opc2" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="4" settings="1">
        <c>1</c>
      </box>
      <box hibit="3" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="2" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="1" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="0" settings="1">
        <c>(0)</c>
      </box>
    </regdiagram>
    <instructiontable iclass="simd_dup_el" cols="5">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="6*" />
      <col colno="4" printwidth="43*" />
      <col colno="5" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">opc1</th>
          <th class="bitfields">L</th>
          <th class="bitfields">opc2</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VMOV_rs_T1" iformfile="vmov_rs.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">0xx</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield"></td>
          <td class="iformname" iformid="VMOV_rs">VMOV (general-purpose register to scalar)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VMOV_sr_T1" iformfile="vmov_sr.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td class="iformname" iformid="VMOV_sr">VMOV (scalar to general-purpose register)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VDUP_r_T1" iformfile="vdup_r.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">1xx</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td class="iformname" iformid="VDUP_r">VDUP (general-purpose register)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_14_simd_dup_el" undef="1" first="t" last="t">
          <td bitwidth="3" class="bitfield">1xx</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="fp_mov16" title="Floating-point 16-bit move">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="11" settings="11">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="20" name="op" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" settings="4">
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="5" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="4" settings="1">
        <c>1</c>
      </box>
      <box hibit="3" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="2" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="1" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="0" settings="1">
        <c>(0)</c>
      </box>
    </regdiagram>
    <instructiontable iclass="fp_mov16" cols="2">
      <col colno="1" printwidth="60*" />
      <col colno="2" printwidth="33*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VMOV_h_T1" arch_version="FEAT_FP16" iformfile="vmov_h.xml" first="t" last="t">
          <td class="iformname" iformid="VMOV_h">VMOV (between general-purpose register and half-precision)</td>
          <td class="enctags">T1, To general-purpose register</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="fp_mov32" title="Floating-point 32-bit move">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="11" settings="11">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="20" name="op" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" settings="4">
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="5" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="4" settings="1">
        <c>1</c>
      </box>
      <box hibit="3" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="2" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="1" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="0" settings="1">
        <c>(0)</c>
      </box>
    </regdiagram>
    <instructiontable iclass="fp_mov32" cols="2">
      <col colno="1" printwidth="62*" />
      <col colno="2" printwidth="33*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VMOV_s_T1" iformfile="vmov_s.xml" first="t" last="t">
          <td class="iformname" iformid="VMOV_s">VMOV (between general-purpose register and single-precision)</td>
          <td class="enctags">T1, To general-purpose register</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="fp_msr" title="Floating-point move special register">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="11" settings="11">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="reg" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" settings="4">
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="7" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="6" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="5" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="4" settings="1">
        <c>1</c>
      </box>
      <box hibit="3" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="2" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="1" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="0" settings="1">
        <c>(0)</c>
      </box>
    </regdiagram>
    <instructiontable iclass="fp_msr" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VMSR_T1_AS" iformfile="vmsr.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMSR">VMSR</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VMRS_T1_AS" iformfile="vmrs.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMRS">VMRS</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="cp_mov32" title="System register 32-bit move">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="8" settings="8">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="23" width="3" name="opc1" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="CRn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="3" settings="3">
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="8" name="cp15" usename="1">
        <c></c>
      </box>
      <box hibit="7" width="3" name="opc2" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="4" settings="1">
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="CRm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="cp_mov32" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="MCR_T1" iformfile="mcr.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="MCR">MCR</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="MRC_T1" iformfile="mrc.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="MRC">MRC</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="sysldst_mov64">Advanced SIMD and System register load/store and 64-bit move</funcgroupheader>
  <iclass_sect id="simdfp_mov64" title="Advanced SIMD and floating-point 64-bit move">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" settings="1">
        <c>0</c>
      </box>
      <box hibit="20" name="op" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rt2" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="9" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="7" width="2" name="opc2" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" name="o3" usename="1">
        <c></c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="simdfp_mov64" cols="7">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="4*" />
      <col colno="3" printwidth="6*" />
      <col colno="4" printwidth="6*" />
      <col colno="5" printwidth="4*" />
      <col colno="6" printwidth="87*" />
      <col colno="7" printwidth="36*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">D</th>
          <th class="bitfields">op</th>
          <th class="bitfields">size</th>
          <th class="bitfields">opc2</th>
          <th class="bitfields">o3</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_simdfp_mov64" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_12_simdfp_mov64" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_19_simdfp_mov64" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_17_simdfp_mov64" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VMOV_toss_T1" iformfile="vmov_ss.xml" label="from general-purpose registers" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMOV_ss">VMOV (between two general-purpose registers and two single-precision registers)</td>
          <td class="enctags">T1, From general-purpose registers</td>
        </tr>
        <tr class="instructiontable" encname="VMOV_tod_T1" iformfile="vmov_d.xml" label="from general-purpose registers" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMOV_d">VMOV (between two general-purpose registers and a doubleword floating-point register)</td>
          <td class="enctags">T1, From general-purpose registers</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_18_simdfp_mov64" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VMOV_ss_T1" iformfile="vmov_ss.xml" label="to general-purpose registers" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMOV_ss">VMOV (between two general-purpose registers and two single-precision registers)</td>
          <td class="enctags">T1, To general-purpose registers</td>
        </tr>
        <tr class="instructiontable" encname="VMOV_d_T1" iformfile="vmov_d.xml" label="to general-purpose registers" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMOV_d">VMOV (between two general-purpose registers and a doubleword floating-point register)</td>
          <td class="enctags">T1, To general-purpose registers</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="simdfp_ldst" title="Advanced SIMD and floating-point load/store">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="7" settings="7">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="24" name="P" usename="1">
        <c></c>
      </box>
      <box hibit="23" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" name="W" usename="1">
        <c></c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="9" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="7" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="P:U:D:W" op="!=" val="00x0" />
    </decode_constraints>
    <instructiontable iclass="simdfp_ldst" cols="9">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="3*" />
      <col colno="4" printwidth="3*" />
      <col colno="5" printwidth="9*" />
      <col colno="6" printwidth="6*" />
      <col colno="7" printwidth="10*" />
      <col colno="8" printwidth="27*" />
      <col colno="9" printwidth="29*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="7">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">P</th>
          <th class="bitfields">U</th>
          <th class="bitfields">W</th>
          <th class="bitfields">L</th>
          <th class="bitfields">Rn</th>
          <th class="bitfields">size</th>
          <th class="bitfields">imm8</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_simdfp_ldst" undef="1" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_12_simdfp_ldst" undef="1" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VSTM_T2" iformfile="vstm.xml" label="single-precision scalar" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VSTM">VSTM, VSTMDB, VSTMIA</td>
          <td class="enctags">T2, Increment After</td>
        </tr>
        <tr class="instructiontable" encname="VSTM_T1" iformfile="vstm.xml" label="double-precision scalar" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="8" class="bitfield">xxxxxxx0</td>
          <td class="iformname" iformid="VSTM">VSTM, VSTMDB, VSTMIA</td>
          <td class="enctags">T1, Increment After</td>
        </tr>
        <tr class="instructiontable" encname="FSTMIAX_T1" iformfile="fstmx.xml" label="Increment After" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="8" class="bitfield">xxxxxxx1</td>
          <td class="iformname" iformid="FSTMX">FSTMDBX, FSTMIAX</td>
          <td class="enctags">T1, Increment After</td>
        </tr>
        <tr class="instructiontable" encname="VLDM_T2" iformfile="vldm.xml" label="single-precision scalar" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VLDM">VLDM, VLDMDB, VLDMIA</td>
          <td class="enctags">T2, Increment After</td>
        </tr>
        <tr class="instructiontable" encname="VLDM_T1" iformfile="vldm.xml" label="double-precision scalar" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="8" class="bitfield">xxxxxxx0</td>
          <td class="iformname" iformid="VLDM">VLDM, VLDMDB, VLDMIA</td>
          <td class="enctags">T1, Increment After</td>
        </tr>
        <tr class="instructiontable" encname="FLDMIAX_T1" iformfile="fldmx.xml" label="Increment After" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="8" class="bitfield">xxxxxxx1</td>
          <td class="iformname" iformid="FLDMX">FLDM*X (FLDMDBX, FLDMIAX)</td>
          <td class="enctags">T1, Increment After</td>
        </tr>
        <tr class="instructiontable" encname="VSTR_T1_H" arch_version="FEAT_FP16" iformfile="vstr.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VSTR">VSTR</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VSTR_T1_S" iformfile="vstr.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VSTR">VSTR</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VSTR_T1_D" iformfile="vstr.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VSTR">VSTR</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VLDR_T1_H" arch_version="FEAT_FP16" iformfile="vldr_i.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VLDR_i">VLDR (immediate)</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VLDR_T1_S" iformfile="vldr_i.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VLDR_i">VLDR (immediate)</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VLDR_T1_D" iformfile="vldr_i.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VLDR_i">VLDR (immediate)</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_19_simdfp_ldst" undef="1" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VSTMDB_T2" iformfile="vstm.xml" label="single-precision scalar" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VSTM">VSTM, VSTMDB, VSTMIA</td>
          <td class="enctags">T2, Decrement Before</td>
        </tr>
        <tr class="instructiontable" encname="VSTMDB_T1" iformfile="vstm.xml" label="double-precision scalar" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="8" class="bitfield">xxxxxxx0</td>
          <td class="iformname" iformid="VSTM">VSTM, VSTMDB, VSTMIA</td>
          <td class="enctags">T1, Decrement Before</td>
        </tr>
        <tr class="instructiontable" encname="FSTMDBX_T1" iformfile="fstmx.xml" label="Decrement Before" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="8" class="bitfield">xxxxxxx1</td>
          <td class="iformname" iformid="FSTMX">FSTMDBX, FSTMIAX</td>
          <td class="enctags">T1, Decrement Before</td>
        </tr>
        <tr class="instructiontable" encname="VLDMDB_T2" iformfile="vldm.xml" label="single-precision scalar" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VLDM">VLDM, VLDMDB, VLDMIA</td>
          <td class="enctags">T2, Decrement Before</td>
        </tr>
        <tr class="instructiontable" encname="VLDMDB_T1" iformfile="vldm.xml" label="double-precision scalar" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="8" class="bitfield">xxxxxxx0</td>
          <td class="iformname" iformid="VLDM">VLDM, VLDMDB, VLDMIA</td>
          <td class="enctags">T1, Decrement Before</td>
        </tr>
        <tr class="instructiontable" encname="FLDMDBX_T1" iformfile="fldmx.xml" label="Decrement Before" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="8" class="bitfield">xxxxxxx1</td>
          <td class="iformname" iformid="FLDMX">FLDM*X (FLDMDBX, FLDMIAX)</td>
          <td class="enctags">T1, Decrement Before</td>
        </tr>
        <tr class="instructiontable" encname="VLDR_l_T1_H" arch_version="FEAT_FP16" iformfile="vldr_l.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VLDR_l">VLDR (literal)</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VLDR_l_T1_S" iformfile="vldr_l.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VLDR_l">VLDR (literal)</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VLDR_l_T1_D" iformfile="vldr_l.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname" iformid="VLDR_l">VLDR (literal)</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_35_simdfp_ldst" undef="1" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="8" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="cp_mov64" title="System register 64-bit move">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" settings="1">
        <c>0</c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rt2" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="3" settings="3">
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="8" name="cp15" usename="1">
        <c></c>
      </box>
      <box hibit="7" width="4" name="opc1" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="3" width="4" name="CRm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="cp_mov64" cols="4">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="18*" />
      <col colno="4" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">D</th>
          <th class="bitfields">L</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_cp_mov64" undef="1" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="MCRR_T1" iformfile="mcrr.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="MCRR">MCRR</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="MRRC_T1" iformfile="mrrc.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="MRRC">MRRC</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="cp_ldst" title="System register Load/Store">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="7" settings="7">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="24" name="P" usename="1">
        <c></c>
      </box>
      <box hibit="23" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" name="W" usename="1">
        <c></c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="CRd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="3" settings="3">
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="8" name="cp15" usename="1">
        <c></c>
      </box>
      <box hibit="7" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="P:U:D:W" op="!=" val="00x0" />
    </decode_constraints>
    <instructiontable iclass="cp_ldst" cols="8">
      <col colno="1" printwidth="8*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="3*" />
      <col colno="4" printwidth="9*" />
      <col colno="5" printwidth="9*" />
      <col colno="6" printwidth="6*" />
      <col colno="7" printwidth="18*" />
      <col colno="8" printwidth="18*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="6">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">P:U:W</th>
          <th class="bitfields">D</th>
          <th class="bitfields">L</th>
          <th class="bitfields">Rn</th>
          <th class="bitfields">CRd</th>
          <th class="bitfields">cp15</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_21_cp_ldst" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">!= 000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">!= 0101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="LDC_l_T1" iformfile="ldc_l.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">!= 000</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="LDC_l">LDC (literal)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_22_cp_ldst" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">!= 000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_20_cp_ldst" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">!= 000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="STC_T1_post" iformfile="stc.xml" label="post-indexed" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0x1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STC">STC</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDC_i_T1_post" iformfile="ldc_i.xml" label="post-indexed" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0x1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="LDC_i">LDC (immediate)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="STC_T1_unind" iformfile="stc.xml" label="unindexed" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STC">STC</td>
          <td class="enctags">T1, Unindexed</td>
        </tr>
        <tr class="instructiontable" encname="LDC_i_T1_unind" iformfile="ldc_i.xml" label="unindexed" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="LDC_i">LDC (immediate)</td>
          <td class="enctags">T1, Unindexed</td>
        </tr>
        <tr class="instructiontable" encname="STC_T1_off" iformfile="stc.xml" label="offset" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1x0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STC">STC</td>
          <td class="enctags">T1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="LDC_i_T1_off" iformfile="ldc_i.xml" label="offset" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1x0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="LDC_i">LDC (immediate)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="STC_T1_pre" iformfile="stc.xml" label="pre-indexed" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1x1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STC">STC</td>
          <td class="enctags">T1, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDC_i_T1_pre" iformfile="ldc_i.xml" label="pre-indexed" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1x1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="LDC_i">LDC (immediate)</td>
          <td class="enctags">T1, Pre-indexed</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="shfr">Data-processing (shifted register)</funcgroupheader>
  <iclass_sect id="dpint_shiftr" title="Data-processing (shifted register)">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="7" settings="7">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="24" width="4" name="op1" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="20" name="S" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="14" width="3" name="imm3" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="11" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" width="2" name="imm2" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="5" width="2" name="stype" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="dpint_shiftr" cols="7">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="9*" />
      <col colno="4" printwidth="17*" />
      <col colno="5" printwidth="9*" />
      <col colno="6" printwidth="31*" />
      <col colno="7" printwidth="36*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">op1</th>
          <th class="bitfields">S</th>
          <th class="bitfields">Rn</th>
          <th class="bitfields">imm3:imm2:stype</th>
          <th class="bitfields">Rd</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="AND_r_T2" iformfile="and_r.xml" label="AND, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="AND_r">AND, ANDS (register)</td>
          <td class="enctags">T2, AND, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="AND_r_T2_RRX" iformfile="and_r.xml" label="AND, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="AND_r">AND, ANDS (register)</td>
          <td class="enctags">T2, AND, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="ANDS_r_T2" iformfile="and_r.xml" label="ANDS, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="AND_r">AND, ANDS (register)</td>
          <td class="enctags">T2, ANDS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="TST_r_T2" iformfile="tst_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="TST_r">TST (register)</td>
          <td class="enctags">T2, Shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="ANDS_r_T2_RRX" iformfile="and_r.xml" label="ANDS, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="AND_r">AND, ANDS (register)</td>
          <td class="enctags">T2, ANDS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="TST_r_T2_RRX" iformfile="tst_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="TST_r">TST (register)</td>
          <td class="enctags">T2, Rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="BICS_r_T2" iformfile="bic_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="BIC_r">BIC, BICS (register)</td>
          <td class="enctags">T2, BICS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="BICS_r_T2_RRX" iformfile="bic_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="BIC_r">BIC, BICS (register)</td>
          <td class="enctags">T2, BICS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="ORR_r_T2" iformfile="orr_r.xml" label="ORR, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ORR_r">ORR, ORRS (register)</td>
          <td class="enctags">T2, ORR, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="ORR_r_T2_RRX" iformfile="orr_r.xml" label="ORR, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ORR_r">ORR, ORRS (register)</td>
          <td class="enctags">T2, ORR, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="MOV_r_T3" iformfile="mov_r.xml" label="MOV, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="MOV_r">MOV, MOVS (register)</td>
          <td class="enctags">T3, MOV, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="MOV_r_T3_RRX" iformfile="mov_r.xml" label="MOV, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="MOV_r">MOV, MOVS (register)</td>
          <td class="enctags">T3, MOV, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="ORRS_r_T2" iformfile="orr_r.xml" label="ORRS, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ORR_r">ORR, ORRS (register)</td>
          <td class="enctags">T2, ORRS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="ORRS_r_T2_RRX" iformfile="orr_r.xml" label="ORRS, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ORR_r">ORR, ORRS (register)</td>
          <td class="enctags">T2, ORRS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="MOVS_r_T3" iformfile="mov_r.xml" label="MOVS, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="MOV_r">MOV, MOVS (register)</td>
          <td class="enctags">T3, MOVS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="MOVS_r_T3_RRX" iformfile="mov_r.xml" label="MOVS, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="MOV_r">MOV, MOVS (register)</td>
          <td class="enctags">T3, MOVS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="ORN_r_T1" iformfile="orn_r.xml" label="ORN, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ORN_r">ORN, ORNS (register)</td>
          <td class="enctags">ORN, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="ORN_r_T1_RRX" iformfile="orn_r.xml" label="ORN, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ORN_r">ORN, ORNS (register)</td>
          <td class="enctags">ORN, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="MVN_r_T2" iformfile="mvn_r.xml" label="MVN, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="MVN_r">MVN, MVNS (register)</td>
          <td class="enctags">T2, MVN, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="MVN_r_T2_RRX" iformfile="mvn_r.xml" label="MVN, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="MVN_r">MVN, MVNS (register)</td>
          <td class="enctags">T2, MVN, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="ORNS_r_T1" iformfile="orn_r.xml" label="ORNS, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ORN_r">ORN, ORNS (register)</td>
          <td class="enctags">ORNS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="ORNS_r_T1_RRX" iformfile="orn_r.xml" label="ORNS, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ORN_r">ORN, ORNS (register)</td>
          <td class="enctags">ORNS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="MVNS_r_T2" iformfile="mvn_r.xml" label="MVNS, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="MVN_r">MVN, MVNS (register)</td>
          <td class="enctags">T2, MVNS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="MVNS_r_T2_RRX" iformfile="mvn_r.xml" label="MVNS, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="MVN_r">MVN, MVNS (register)</td>
          <td class="enctags">T2, MVNS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="EOR_r_T2" iformfile="eor_r.xml" label="EOR, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="EOR_r">EOR, EORS (register)</td>
          <td class="enctags">T2, EOR, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="EOR_r_T2_RRX" iformfile="eor_r.xml" label="EOR, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="EOR_r">EOR, EORS (register)</td>
          <td class="enctags">T2, EOR, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="EORS_r_T2" iformfile="eor_r.xml" label="EORS, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="EOR_r">EOR, EORS (register)</td>
          <td class="enctags">T2, EORS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="TEQ_r_T1" iformfile="teq_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="TEQ_r">TEQ (register)</td>
          <td class="enctags">T1, Shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="EORS_r_T2_RRX" iformfile="eor_r.xml" label="EORS, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="EOR_r">EOR, EORS (register)</td>
          <td class="enctags">T2, EORS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="TEQ_r_T1_RRX" iformfile="teq_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="TEQ_r">TEQ (register)</td>
          <td class="enctags">T1, Rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_43_dpint_shiftr" undef="1" oneofthismnem="7" first="t" last="t">
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="PKHBT_T1" iformfile="pkh.xml" label="PKHBT" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">xxxxx00</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="PKH">PKHBT, PKHTB</td>
          <td class="enctags">T1, PKHBT</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_45_dpint_shiftr" undef="1" oneofthismnem="7" first="t" last="t">
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">xxxxx01</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="PKHTB_T1" iformfile="pkh.xml" label="PKHTB" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">xxxxx10</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="PKH">PKHBT, PKHTB</td>
          <td class="enctags">T1, PKHTB</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_47_dpint_shiftr" undef="1" oneofthismnem="7" first="t" last="t">
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">xxxxx11</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_48_dpint_shiftr" undef="1" oneofthismnem="7" first="t" last="t">
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="ADD_r_T3" iformfile="add_r.xml" label="ADD, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ADD_r">ADD, ADDS (register)</td>
          <td class="enctags">T3, ADD, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="ADD_r_T3_RRX" iformfile="add_r.xml" label="ADD, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ADD_r">ADD, ADDS (register)</td>
          <td class="enctags">T3, ADD, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="ADD_SP_r_T3" iformfile="add_sp_r.xml" label="ADD, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ADD_SP_r">ADD, ADDS (SP plus register)</td>
          <td class="enctags">T3, ADD, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="ADD_SP_r_T3_RRX" iformfile="add_sp_r.xml" label="ADD, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ADD_SP_r">ADD, ADDS (SP plus register)</td>
          <td class="enctags">T3, ADD, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="CMN_r_T2" iformfile="cmn_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="CMN_r">CMN (register)</td>
          <td class="enctags">T2, Shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="ADDS_r_T3" iformfile="add_r.xml" label="ADDS, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="ADD_r">ADD, ADDS (register)</td>
          <td class="enctags">T3, ADDS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="ADDS_r_T3_RRX" iformfile="add_r.xml" label="ADDS, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="ADD_r">ADD, ADDS (register)</td>
          <td class="enctags">T3, ADDS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="CMN_r_T2_RRX" iformfile="cmn_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="CMN_r">CMN (register)</td>
          <td class="enctags">T2, Rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="ADDS_SP_r_T3" iformfile="add_sp_r.xml" label="ADDS, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="ADD_SP_r">ADD, ADDS (SP plus register)</td>
          <td class="enctags">T3, ADDS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="ADDS_SP_r_T3_RRX" iformfile="add_sp_r.xml" label="ADDS, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="ADD_SP_r">ADD, ADDS (SP plus register)</td>
          <td class="enctags">T3, ADDS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_59_dpint_shiftr" undef="1" oneofthismnem="7" first="t" last="t">
          <td bitwidth="4" class="bitfield">1001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="ADCS_r_T2" iformfile="adc_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ADC_r">ADC, ADCS (register)</td>
          <td class="enctags">T2, ADCS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="ADCS_r_T2_RRX" iformfile="adc_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ADC_r">ADC, ADCS (register)</td>
          <td class="enctags">T2, ADCS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="SBCS_r_T2" iformfile="sbc_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">1011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="SBC_r">SBC, SBCS (register)</td>
          <td class="enctags">T2, SBCS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="SBCS_r_T2_RRX" iformfile="sbc_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">1011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="SBC_r">SBC, SBCS (register)</td>
          <td class="enctags">T2, SBCS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_68_dpint_shiftr" undef="1" oneofthismnem="7" first="t" last="t">
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SUB_r_T2" iformfile="sub_r.xml" label="SUB, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="SUB_r">SUB, SUBS (register)</td>
          <td class="enctags">T2, SUB, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="SUB_r_T2_RRX" iformfile="sub_r.xml" label="SUB, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="SUB_r">SUB, SUBS (register)</td>
          <td class="enctags">T2, SUB, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="SUB_SP_r_T1" iformfile="sub_sp_r.xml" label="SUB, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="SUB_SP_r">SUB, SUBS (SP minus register)</td>
          <td class="enctags">T1, SUB, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="SUB_SP_r_T1_RRX" iformfile="sub_sp_r.xml" label="SUB, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="SUB_SP_r">SUB, SUBS (SP minus register)</td>
          <td class="enctags">T1, SUB, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="CMP_r_T3" iformfile="cmp_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="CMP_r">CMP (register)</td>
          <td class="enctags">T3, Shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="SUBS_r_T2" iformfile="sub_r.xml" label="SUBS, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="SUB_r">SUB, SUBS (register)</td>
          <td class="enctags">T2, SUBS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="SUBS_r_T2_RRX" iformfile="sub_r.xml" label="SUBS, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="SUB_r">SUB, SUBS (register)</td>
          <td class="enctags">T2, SUBS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="CMP_r_T3_RRX" iformfile="cmp_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="CMP_r">CMP (register)</td>
          <td class="enctags">T3, Rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="SUBS_SP_r_T1" iformfile="sub_sp_r.xml" label="SUBS, shift or rotate by value" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="SUB_SP_r">SUB, SUBS (SP minus register)</td>
          <td class="enctags">T1, SUBS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="SUBS_SP_r_T1_RRX" iformfile="sub_sp_r.xml" label="SUBS, rotate right with extend" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="SUB_SP_r">SUB, SUBS (SP minus register)</td>
          <td class="enctags">T1, SUBS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="RSBS_r_T1" iformfile="rsb_r.xml" label="shift or rotate by value" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">!= 0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="RSB_r">RSB, RSBS (register)</td>
          <td class="enctags">T1, RSBS, shift or rotate by value</td>
        </tr>
        <tr class="instructiontable" encname="RSBS_r_T1_RRX" iformfile="rsb_r.xml" label="rotate right with extend" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield">0000011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="RSB_r">RSB, RSBS (register)</td>
          <td class="enctags">T1, RSBS, rotate right with extend</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_83_dpint_shiftr" undef="1" oneofthismnem="7" first="t" last="t">
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="11" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="advsimdext">Additional Advanced SIMD and floating-point instructions</funcgroupheader>
  <iclass_sect id="tsimd_dotprod" title="Advanced SIMD and floating-point dot product">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="8" settings="8">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="23" name="op1" usename="1">
        <c></c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" name="op2" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="3" settings="3">
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="8" name="op4" usename="1">
        <c></c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" name="Q" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="tsimd_dotprod" cols="7">
      <col colno="1" printwidth="5*" />
      <col colno="2" printwidth="5*" />
      <col colno="3" printwidth="5*" />
      <col colno="4" printwidth="3*" />
      <col colno="5" printwidth="3*" />
      <col colno="6" printwidth="21*" />
      <col colno="7" printwidth="25*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">op1</th>
          <th class="bitfields">op2</th>
          <th class="bitfields">op4</th>
          <th class="bitfields">Q</th>
          <th class="bitfields">U</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_tsimd_dotprod" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VDOT_s_T1_D" arch_version="FEAT_AA32BF16" iformfile="vdot_s.xml" label="64-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VDOT_s">VDOT (by element)</td>
          <td class="enctags">T1, 64-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_14_tsimd_dotprod" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VDOT_s_T1_Q" arch_version="FEAT_AA32BF16" iformfile="vdot_s.xml" label="128-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VDOT_s">VDOT (by element)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_15_tsimd_dotprod" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_16_tsimd_dotprod" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VSDOT_s_T1_D" arch_version="FEAT_DotProd" iformfile="vsdot_s.xml" label="64-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VSDOT_s">VSDOT (by element)</td>
          <td class="enctags">T1, 64-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VUDOT_s_T1_D" arch_version="FEAT_DotProd" iformfile="vudot_s.xml" label="64-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VUDOT_s">VUDOT (by element)</td>
          <td class="enctags">T1, 64-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSDOT_s_T1_Q" arch_version="FEAT_DotProd" iformfile="vsdot_s.xml" label="128-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VSDOT_s">VSDOT (by element)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VUDOT_s_T1_Q" arch_version="FEAT_DotProd" iformfile="vudot_s.xml" label="128-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VUDOT_s">VUDOT (by element)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_21_tsimd_dotprod" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_22_tsimd_dotprod" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VUSDOT_s_T1_D" arch_version="FEAT_AA32I8MM" iformfile="vusdot_s.xml" label="64-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VUSDOT_s">VUSDOT (by element)</td>
          <td class="enctags">T1, 64-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSUDOT_s_T1_D" arch_version="FEAT_AA32I8MM" iformfile="vsudot_s.xml" label="64-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VSUDOT_s">VSUDOT (by element)</td>
          <td class="enctags">T1, 64-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VUSDOT_s_T1_Q" arch_version="FEAT_AA32I8MM" iformfile="vusdot_s.xml" label="128-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VUSDOT_s">VUSDOT (by element)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSUDOT_s_T1_Q" arch_version="FEAT_AA32I8MM" iformfile="vsudot_s.xml" label="128-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VSUDOT_s">VSUDOT (by element)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_27_tsimd_dotprod" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_28_tsimd_dotprod" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="tfloatdpmac" title="Advanced SIMD and floating-point multiply with accumulate">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="8" settings="8">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="23" name="op1" usename="1">
        <c></c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" name="op2" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" settings="4">
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" name="Q" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="tfloatdpmac" cols="6">
      <col colno="1" printwidth="5*" />
      <col colno="2" printwidth="5*" />
      <col colno="3" printwidth="3*" />
      <col colno="4" printwidth="3*" />
      <col colno="5" printwidth="36*" />
      <col colno="6" printwidth="60*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">op1</th>
          <th class="bitfields">op2</th>
          <th class="bitfields">Q</th>
          <th class="bitfields">U</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VCMLA_s_T1_QH" arch_version="FEAT_FCMA" iformfile="vcmla_s.xml" label="128-bit SIMD vector of half-precision floating-point" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCMLA_s">VCMLA (by element)</td>
          <td class="enctags">T1, 128-bit SIMD vector of half-precision floating-point</td>
        </tr>
        <tr class="instructiontable" encname="VFMAL_s_T1_Q" arch_version="FEAT_FHM" iformfile="vfmal_s.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFMAL_s">VFMAL (by scalar)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VFMSL_s_T1_Q" arch_version="FEAT_FHM" iformfile="vfmsl_s.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFMSL_s">VFMSL (by scalar)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_17_tfloatdpmac" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VFMA_bfs_T1_Q" arch_version="FEAT_AA32BF16" iformfile="vfma_bfs.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFMA_bfs">VFMAB, VFMAT (BFloat16, by scalar)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VCMLA_s_T1_DS" arch_version="FEAT_FCMA" iformfile="vcmla_s.xml" label="64-bit SIMD vector of single-precision floating-point" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCMLA_s">VCMLA (by element)</td>
          <td class="enctags">T1, 64-bit SIMD vector of single-precision floating-point</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_21_tfloatdpmac" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VCMLA_s_T1_QS" arch_version="FEAT_FCMA" iformfile="vcmla_s.xml" label="128-bit SIMD vector of single-precision floating-point" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCMLA_s">VCMLA (by element)</td>
          <td class="enctags">T1, 128-bit SIMD vector of single-precision floating-point</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="simd_3sameext" title="Advanced SIMD three registers of the same length extension">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="7" settings="7">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="24" width="2" name="op1" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" name="op2" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" settings="1">
        <c>1</c>
      </box>
      <box hibit="10" name="op3" usename="1">
        <c></c>
      </box>
      <box hibit="9" settings="1">
        <c>0</c>
      </box>
      <box hibit="8" name="op4" usename="1">
        <c></c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" name="Q" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="simd_3sameext" cols="8">
      <col colno="1" printwidth="5*" />
      <col colno="2" printwidth="5*" />
      <col colno="3" printwidth="5*" />
      <col colno="4" printwidth="5*" />
      <col colno="5" printwidth="3*" />
      <col colno="6" printwidth="3*" />
      <col colno="7" printwidth="33*" />
      <col colno="8" printwidth="25*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="6">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">op1</th>
          <th class="bitfields">op2</th>
          <th class="bitfields">op3</th>
          <th class="bitfields">op4</th>
          <th class="bitfields">Q</th>
          <th class="bitfields">U</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VCADD_T1_D" arch_version="FEAT_FCMA" iformfile="vcadd.xml" label="64-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">x1</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCADD">VCADD</td>
          <td class="enctags">T1, 64-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_40_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">x1</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VCADD_T1_Q" arch_version="FEAT_FCMA" iformfile="vcadd.xml" label="128-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">x1</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCADD">VCADD</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_42_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">x1</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_11_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_12_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_13_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_14_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VMMLA_T1_Q" arch_version="FEAT_AA32BF16" iformfile="vmmla.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMMLA">VMMLA</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_16_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VDOT_T1_D" arch_version="FEAT_AA32BF16" iformfile="vdot.xml" label="64-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VDOT">VDOT (vector)</td>
          <td class="enctags">T1, 64-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_18_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VDOT_T1_Q" arch_version="FEAT_AA32BF16" iformfile="vdot.xml" label="128-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VDOT">VDOT (vector)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_20_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_21_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_22_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VFMAL_T1_Q" arch_version="FEAT_FHM" iformfile="vfmal.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFMAL">VFMAL (vector)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_27_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_28_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VSMMLA_T1_Q" arch_version="FEAT_AA32I8MM" iformfile="vsmmla.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VSMMLA">VSMMLA</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VUMMLA_T1_Q" arch_version="FEAT_AA32I8MM" iformfile="vummla.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VUMMLA">VUMMLA</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VSDOT_T1_D" arch_version="FEAT_DotProd" iformfile="vsdot.xml" label="64-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VSDOT">VSDOT (vector)</td>
          <td class="enctags">T1, 64-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VUDOT_T1_D" arch_version="FEAT_DotProd" iformfile="vudot.xml" label="64-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VUDOT">VUDOT (vector)</td>
          <td class="enctags">T1, 64-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSDOT_T1_Q" arch_version="FEAT_DotProd" iformfile="vsdot.xml" label="128-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VSDOT">VSDOT (vector)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VUDOT_T1_Q" arch_version="FEAT_DotProd" iformfile="vudot.xml" label="128-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VUDOT">VUDOT (vector)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VFMA_bf_T1_Q" arch_version="FEAT_AA32BF16" iformfile="vfma_bf.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFMA_bf">VFMAB, VFMAT (BFloat16, vector)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_36_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_37_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_38_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VFMSL_T1_Q" arch_version="FEAT_FHM" iformfile="vfmsl.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFMSL">VFMSL (vector)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_45_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_46_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VUSMMLA_T1_Q" arch_version="FEAT_AA32I8MM" iformfile="vusmmla.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VUSMMLA">VUSMMLA</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_48_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VUSDOT_T1_D" arch_version="FEAT_AA32I8MM" iformfile="vusdot.xml" label="64-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VUSDOT">VUSDOT (vector)</td>
          <td class="enctags">T1, 64-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_51_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VUSDOT_T1_Q" arch_version="FEAT_AA32I8MM" iformfile="vusdot.xml" label="128-bit SIMD vector" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VUSDOT">VUSDOT (vector)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_52_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_53_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_54_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VCMLA_T1_Q" arch_version="FEAT_FCMA" iformfile="vcmla.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCMLA">VCMLA</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_55_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_56_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_57_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_58_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_59_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_60_simd_3sameext" undef="1" oneofthismnem="29" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="fp_csel" title="Floating-point conditional select">
    <regdiagram form="16x2" psname="" tworows="1">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" name="cc" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
        <c colspan="2">!= 00</c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" settings="1">
        <c>0</c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="size" op="!=" val="00" />
      <decode_constraint name="size" op="!=" val="00" />
    </decode_constraints>
    <instructiontable iclass="fp_csel" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="32*" />
      <col colno="3" printwidth="43*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VSELGT_T1_H" arch_version="FEAT_FP16" iformfile="vsel.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="VSEL">VSELEQ, VSELGE, VSELGT, VSELVS</td>
          <td class="enctags">T1, Greater than, half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VSELGT_T1_S" iformfile="vsel.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="VSEL">VSELEQ, VSELGE, VSELGT, VSELVS</td>
          <td class="enctags">T1, Greater than, single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VSELGT_T1_D" iformfile="vsel.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="VSEL">VSELEQ, VSELGE, VSELGT, VSELVS</td>
          <td class="enctags">T1, Greater than, double-precision scalar</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="fp_toint" title="Floating-point directed convert to integer">
    <regdiagram form="16x2" psname="" tworows="1">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="3" settings="3">
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="18" name="o1" usename="1">
        <c></c>
      </box>
      <box hibit="17" width="2" name="RM" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
        <c colspan="2">!= 00</c>
      </box>
      <box hibit="7" name="op" usename="1">
        <c></c>
      </box>
      <box hibit="6" settings="1">
        <c>1</c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="size" op="!=" val="00" />
      <decode_constraint name="size" op="!=" val="00" />
    </decode_constraints>
    <instructiontable iclass="fp_toint" cols="6">
      <col colno="1" printwidth="4*" />
      <col colno="2" printwidth="4*" />
      <col colno="3" printwidth="7*" />
      <col colno="4" printwidth="4*" />
      <col colno="5" printwidth="25*" />
      <col colno="6" printwidth="29*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">o1</th>
          <th class="bitfields">RM</th>
          <th class="bitfields">size</th>
          <th class="bitfields">op</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_23_fp_toint" undef="1" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">!= 00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VRINTA_vfp_T1_H" arch_version="FEAT_FP16" iformfile="vrinta_vfp.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTA_vfp">VRINTA (floating-point)</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTA_vfp_T1_S" iformfile="vrinta_vfp.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTA_vfp">VRINTA (floating-point)</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTA_vfp_T1_D" iformfile="vrinta_vfp.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTA_vfp">VRINTA (floating-point)</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTN_vfp_T1_H" arch_version="FEAT_FP16" iformfile="vrintn_vfp.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTN_vfp">VRINTN (floating-point)</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTN_vfp_T1_S" iformfile="vrintn_vfp.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTN_vfp">VRINTN (floating-point)</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTN_vfp_T1_D" iformfile="vrintn_vfp.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTN_vfp">VRINTN (floating-point)</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTP_vfp_T1_H" arch_version="FEAT_FP16" iformfile="vrintp_vfp.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTP_vfp">VRINTP (floating-point)</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTP_vfp_T1_S" iformfile="vrintp_vfp.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTP_vfp">VRINTP (floating-point)</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTP_vfp_T1_D" iformfile="vrintp_vfp.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTP_vfp">VRINTP (floating-point)</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTM_vfp_T1_H" arch_version="FEAT_FP16" iformfile="vrintm_vfp.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTM_vfp">VRINTM (floating-point)</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTM_vfp_T1_S" iformfile="vrintm_vfp.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTM_vfp">VRINTM (floating-point)</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VRINTM_vfp_T1_D" iformfile="vrintm_vfp.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRINTM_vfp">VRINTM (floating-point)</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTA_vfp_T1_H" arch_version="FEAT_FP16" iformfile="vcvta_vfp.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTA_vfp">VCVTA (floating-point)</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTA_vfp_T1_S" iformfile="vcvta_vfp.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTA_vfp">VCVTA (floating-point)</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTA_vfp_T1_D" iformfile="vcvta_vfp.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTA_vfp">VCVTA (floating-point)</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTN_vfp_T1_H" arch_version="FEAT_FP16" iformfile="vcvtn_vfp.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTN_vfp">VCVTN (floating-point)</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTN_vfp_T1_S" iformfile="vcvtn_vfp.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTN_vfp">VCVTN (floating-point)</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTN_vfp_T1_D" iformfile="vcvtn_vfp.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTN_vfp">VCVTN (floating-point)</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTP_vfp_T1_H" arch_version="FEAT_FP16" iformfile="vcvtp_vfp.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTP_vfp">VCVTP (floating-point)</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTP_vfp_T1_S" iformfile="vcvtp_vfp.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTP_vfp">VCVTP (floating-point)</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTP_vfp_T1_D" iformfile="vcvtp_vfp.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTP_vfp">VCVTP (floating-point)</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTM_vfp_T1_H" arch_version="FEAT_FP16" iformfile="vcvtm_vfp.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTM_vfp">VCVTM (floating-point)</td>
          <td class="enctags">T1, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTM_vfp_T1_S" iformfile="vcvtm_vfp.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTM_vfp">VCVTM (floating-point)</td>
          <td class="enctags">T1, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VCVTM_vfp_T1_D" iformfile="vcvtm_vfp.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTM_vfp">VCVTM (floating-point)</td>
          <td class="enctags">T1, Double-precision scalar</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="fp_extins" title="Floating-point extraction and insertion">
    <regdiagram form="16x2" psname="" tworows="1">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="6" settings="6">
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
        <c colspan="2">!= 00</c>
      </box>
      <box hibit="7" name="op" usename="1">
        <c></c>
      </box>
      <box hibit="6" settings="1">
        <c>1</c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="size" op="!=" val="00" />
      <decode_constraint name="size" op="!=" val="00" />
    </decode_constraints>
    <instructiontable iclass="fp_extins" cols="4">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="4*" />
      <col colno="3" printwidth="18*" />
      <col colno="4" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
          <th class="bitfields">op</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_fp_extins" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VMOVX_T1" arch_version="FEAT_FP16" iformfile="vmovx.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMOVX">VMOVX</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VINS_T1" arch_version="FEAT_FP16" iformfile="vins.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VINS">VINS</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_14_fp_extins" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="fp_minmax" title="Floating-point minNum/maxNum">
    <regdiagram form="16x2" psname="" tworows="1">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" settings="2">
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
        <c colspan="2">!= 00</c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" name="op" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="size" op="!=" val="00" />
      <decode_constraint name="size" op="!=" val="00" />
    </decode_constraints>
    <instructiontable iclass="fp_minmax" cols="4">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="4*" />
      <col colno="3" printwidth="18*" />
      <col colno="4" printwidth="29*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
          <th class="bitfields">op</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VMAXNM_T2_H" arch_version="FEAT_FP16" iformfile="vmaxnm.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMAXNM">VMAXNM</td>
          <td class="enctags">T2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMINNM_T2_H" arch_version="FEAT_FP16" iformfile="vminnm.xml" label="half-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMINNM">VMINNM</td>
          <td class="enctags">T2, Half-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMAXNM_T2_S" iformfile="vmaxnm.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMAXNM">VMAXNM</td>
          <td class="enctags">T2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMINNM_T2_S" iformfile="vminnm.xml" label="single-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMINNM">VMINNM</td>
          <td class="enctags">T2, Single-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMAXNM_T2_D" iformfile="vmaxnm.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMAXNM">VMAXNM</td>
          <td class="enctags">T2, Double-precision scalar</td>
        </tr>
        <tr class="instructiontable" encname="VMINNM_T2_D" iformfile="vminnm.xml" label="double-precision scalar" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMINNM">VMINNM</td>
          <td class="enctags">T2, Double-precision scalar</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="modi">Data-processing (modified immediate)</funcgroupheader>
  <iclass_sect id="dpint_immm" title="Data-processing (modified immediate)">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="5" settings="5">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="26" name="i" usename="1">
        <c></c>
      </box>
      <box hibit="25" settings="1">
        <c>0</c>
      </box>
      <box hibit="24" width="4" name="op1" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="20" name="S" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" settings="1">
        <c>0</c>
      </box>
      <box hibit="14" width="3" name="imm3" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="11" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="dpint_immm" cols="6">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="9*" />
      <col colno="4" printwidth="9*" />
      <col colno="5" printwidth="32*" />
      <col colno="6" printwidth="18*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">op1</th>
          <th class="bitfields">S</th>
          <th class="bitfields">Rn</th>
          <th class="bitfields">Rd</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="AND_i_T1" iformfile="and_i.xml" label="AND" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="AND_i">AND, ANDS (immediate)</td>
          <td class="enctags">T1, AND</td>
        </tr>
        <tr class="instructiontable" encname="ANDS_i_T1" iformfile="and_i.xml" label="ANDS" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="AND_i">AND, ANDS (immediate)</td>
          <td class="enctags">T1, ANDS</td>
        </tr>
        <tr class="instructiontable" encname="TST_i_T1" iformfile="tst_i.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="TST_i">TST (immediate)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="BICS_i_T1" iformfile="bic_i.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="BIC_i">BIC, BICS (immediate)</td>
          <td class="enctags">T1, BICS</td>
        </tr>
        <tr class="instructiontable" encname="ORR_i_T1" iformfile="orr_i.xml" label="ORR" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ORR_i">ORR, ORRS (immediate)</td>
          <td class="enctags">T1, ORR</td>
        </tr>
        <tr class="instructiontable" encname="MOV_i_T2" iformfile="mov_i.xml" label="MOV" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="MOV_i">MOV, MOVS (immediate)</td>
          <td class="enctags">T2, MOV</td>
        </tr>
        <tr class="instructiontable" encname="ORRS_i_T1" iformfile="orr_i.xml" label="ORRS" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ORR_i">ORR, ORRS (immediate)</td>
          <td class="enctags">T1, ORRS</td>
        </tr>
        <tr class="instructiontable" encname="MOVS_i_T2" iformfile="mov_i.xml" label="MOVS" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="MOV_i">MOV, MOVS (immediate)</td>
          <td class="enctags">T2, MOVS</td>
        </tr>
        <tr class="instructiontable" encname="ORN_i_T1" iformfile="orn_i.xml" label="not flag setting" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ORN_i">ORN, ORNS (immediate)</td>
          <td class="enctags">Not flag setting</td>
        </tr>
        <tr class="instructiontable" encname="MVN_i_T1" iformfile="mvn_i.xml" label="MVN" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="MVN_i">MVN, MVNS (immediate)</td>
          <td class="enctags">T1, MVN</td>
        </tr>
        <tr class="instructiontable" encname="ORNS_i_T1" iformfile="orn_i.xml" label="flag setting" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ORN_i">ORN, ORNS (immediate)</td>
          <td class="enctags">Flag setting</td>
        </tr>
        <tr class="instructiontable" encname="MVNS_i_T1" iformfile="mvn_i.xml" label="MVNS" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="MVN_i">MVN, MVNS (immediate)</td>
          <td class="enctags">T1, MVNS</td>
        </tr>
        <tr class="instructiontable" encname="EOR_i_T1" iformfile="eor_i.xml" label="EOR" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="EOR_i">EOR, EORS (immediate)</td>
          <td class="enctags">T1, EOR</td>
        </tr>
        <tr class="instructiontable" encname="EORS_i_T1" iformfile="eor_i.xml" label="EORS" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="EOR_i">EOR, EORS (immediate)</td>
          <td class="enctags">T1, EORS</td>
        </tr>
        <tr class="instructiontable" encname="TEQ_i_T1" iformfile="teq_i.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="TEQ_i">TEQ (immediate)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_27_dpint_immm" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_28_dpint_immm" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="4" class="bitfield">011x</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="ADD_i_T3" iformfile="add_i.xml" label="ADD" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ADD_i">ADD, ADDS (immediate)</td>
          <td class="enctags">T3, ADD</td>
        </tr>
        <tr class="instructiontable" encname="ADD_SP_i_T3" iformfile="add_sp_i.xml" label="ADD" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ADD_SP_i">ADD, ADDS (SP plus immediate)</td>
          <td class="enctags">T3, ADD</td>
        </tr>
        <tr class="instructiontable" encname="ADDS_i_T3" iformfile="add_i.xml" label="ADDS" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="ADD_i">ADD, ADDS (immediate)</td>
          <td class="enctags">T3, ADDS</td>
        </tr>
        <tr class="instructiontable" encname="ADDS_SP_i_T3" iformfile="add_sp_i.xml" label="ADDS" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="ADD_SP_i">ADD, ADDS (SP plus immediate)</td>
          <td class="enctags">T3, ADDS</td>
        </tr>
        <tr class="instructiontable" encname="CMN_i_T1" iformfile="cmn_i.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="CMN_i">CMN (immediate)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_34_dpint_immm" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="4" class="bitfield">1001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="ADCS_i_T1" iformfile="adc_i.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ADC_i">ADC, ADCS (immediate)</td>
          <td class="enctags">T1, ADCS</td>
        </tr>
        <tr class="instructiontable" encname="SBCS_i_T1" iformfile="sbc_i.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">1011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="SBC_i">SBC, SBCS (immediate)</td>
          <td class="enctags">T1, SBCS</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_39_dpint_immm" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SUB_i_T3" iformfile="sub_i.xml" label="SUB" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="SUB_i">SUB, SUBS (immediate)</td>
          <td class="enctags">T3, SUB</td>
        </tr>
        <tr class="instructiontable" encname="SUB_SP_i_T2" iformfile="sub_sp_i.xml" label="SUB" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="SUB_SP_i">SUB, SUBS (SP minus immediate)</td>
          <td class="enctags">T2, SUB</td>
        </tr>
        <tr class="instructiontable" encname="SUBS_i_T3" iformfile="sub_i.xml" label="SUBS" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1101</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="SUB_i">SUB, SUBS (immediate)</td>
          <td class="enctags">T3, SUBS</td>
        </tr>
        <tr class="instructiontable" encname="SUBS_SP_i_T2" iformfile="sub_sp_i.xml" label="SUBS" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="SUB_SP_i">SUB, SUBS (SP minus immediate)</td>
          <td class="enctags">T2, SUBS</td>
        </tr>
        <tr class="instructiontable" encname="CMP_i_T2" iformfile="cmp_i.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="CMP_i">CMP (immediate)</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="RSBS_i_T2" iformfile="rsb_i.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="RSB_i">RSB, RSBS (immediate)</td>
          <td class="enctags">T2, RSBS</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_47_dpint_immm" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="imm">Data-processing (plain binary immediate)</funcgroupheader>
  <iclass_sect id="dpint_imms" title="Data-processing (simple immediate)">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="5" settings="5">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="26" name="i" usename="1">
        <c></c>
      </box>
      <box hibit="25" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="23" name="o1" usename="1">
        <c></c>
      </box>
      <box hibit="22" settings="1">
        <c>0</c>
      </box>
      <box hibit="21" name="o2" usename="1">
        <c></c>
      </box>
      <box hibit="20" settings="1">
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" settings="1">
        <c>0</c>
      </box>
      <box hibit="14" width="3" name="imm3" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="11" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="dpint_imms" cols="5">
      <col colno="1" printwidth="4*" />
      <col colno="2" printwidth="4*" />
      <col colno="3" printwidth="9*" />
      <col colno="4" printwidth="32*" />
      <col colno="5" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">o1</th>
          <th class="bitfields">o2</th>
          <th class="bitfields">Rn</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="ADD_i_T4" iformfile="add_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="ADD_i">ADD, ADDS (immediate)</td>
          <td class="enctags">T4</td>
        </tr>
        <tr class="instructiontable" encname="ADD_SP_i_T4" iformfile="add_sp_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="ADD_SP_i">ADD, ADDS (SP plus immediate)</td>
          <td class="enctags">T4</td>
        </tr>
        <tr class="instructiontable" encoding="t3" iformfile="adr.xml" label="T3" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="ADR">ADR</td>
          <td class="enctags">T3</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_14_dpint_imms" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_15_dpint_imms" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SUB_i_T4" iformfile="sub_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="SUB_i">SUB, SUBS (immediate)</td>
          <td class="enctags">T4</td>
        </tr>
        <tr class="instructiontable" encname="SUB_SP_i_T3" iformfile="sub_sp_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="SUB_SP_i">SUB, SUBS (SP minus immediate)</td>
          <td class="enctags">T3</td>
        </tr>
        <tr class="instructiontable" encoding="t2" iformfile="adr.xml" label="T2" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="ADR">ADR</td>
          <td class="enctags">T2</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="movw" title="Move Wide (16-bit immediate)">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="5" settings="5">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="26" name="i" usename="1">
        <c></c>
      </box>
      <box hibit="25" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="23" name="o1" usename="1">
        <c></c>
      </box>
      <box hibit="22" width="3" settings="3">
        <c>1</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="imm4" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" settings="1">
        <c>0</c>
      </box>
      <box hibit="14" width="3" name="imm3" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="11" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="movw" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="23*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">o1</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="MOV_i_T3" iformfile="mov_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="MOV_i">MOV, MOVS (immediate)</td>
          <td class="enctags">T3</td>
        </tr>
        <tr class="instructiontable" encname="MOVT_T1" iformfile="movt.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="MOVT">MOVT</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="sat_bit" title="Saturate, Bitfield">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="5" settings="5">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="26" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="25" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="23" width="3" name="op1" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="20" settings="1">
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" settings="1">
        <c>0</c>
      </box>
      <box hibit="14" width="3" name="imm3" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="11" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" width="2" name="imm2" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="5" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="4" width="5" name="widthm1" usename="1">
        <c colspan="5"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="sat_bit" cols="5">
      <col colno="1" printwidth="5*" />
      <col colno="2" printwidth="9*" />
      <col colno="3" printwidth="11*" />
      <col colno="4" printwidth="18*" />
      <col colno="5" printwidth="28*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">op1</th>
          <th class="bitfields">Rn</th>
          <th class="bitfields">imm3:imm2</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="SSAT_T1_LSL" iformfile="ssat.xml" label="logical shift left" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="9" class="bitfield"></td>
          <td class="iformname" iformid="SSAT">SSAT</td>
          <td class="enctags">T1, Logical shift left</td>
        </tr>
        <tr class="instructiontable" encname="SSAT_T1_ASR" iformfile="ssat.xml" label="arithmetic shift right" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="9" class="bitfield">!= 00000</td>
          <td class="iformname" iformid="SSAT">SSAT</td>
          <td class="enctags">T1, Arithmetic shift right</td>
        </tr>
        <tr class="instructiontable" encname="SSAT16_T1" iformfile="ssat16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="9" class="bitfield">00000</td>
          <td class="iformname" iformid="SSAT16">SSAT16</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="SBFX_T1" iformfile="sbfx.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="9" class="bitfield"></td>
          <td class="iformname" iformid="SBFX">SBFX</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="BFI_T1" iformfile="bfi.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="9" class="bitfield"></td>
          <td class="iformname" iformid="BFI">BFI</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="BFC_T1" iformfile="bfc.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="9" class="bitfield"></td>
          <td class="iformname" iformid="BFC">BFC</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="USAT_T1_LSL" iformfile="usat.xml" label="logical shift left" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="9" class="bitfield"></td>
          <td class="iformname" iformid="USAT">USAT</td>
          <td class="enctags">T1, Logical shift left</td>
        </tr>
        <tr class="instructiontable" encname="USAT_T1_ASR" iformfile="usat.xml" label="arithmetic shift right" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="9" class="bitfield">!= 00000</td>
          <td class="iformname" iformid="USAT">USAT</td>
          <td class="enctags">T1, Arithmetic shift right</td>
        </tr>
        <tr class="instructiontable" encname="USAT16_T1" iformfile="usat16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="9" class="bitfield">00000</td>
          <td class="iformname" iformid="USAT16">USAT16</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UBFX_T1" iformfile="ubfx.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="9" class="bitfield"></td>
          <td class="iformname" iformid="UBFX">UBFX</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_21_sat_bit" undef="1" first="t" last="t">
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="9" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="bcrtrl">Branches and miscellaneous control</funcgroupheader>
  <iclass_sect id="bx_jaz" title="Branch and Exchange Jazelle">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="12" settings="12">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="13" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="12" settings="1">
        <c>0</c>
      </box>
      <box hibit="11" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="10" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="9" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="8" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="7" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="6" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="5" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="4" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="3" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="2" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="1" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="0" settings="1">
        <c>(0)</c>
      </box>
    </regdiagram>
    <instructiontable iclass="bx_jaz" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="BXJ_T1" iformfile="bxj.xml" first="t" last="t">
          <td class="iformname" iformid="BXJ">BXJ</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="cps" title="Change processor state">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="12" settings="12">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="19" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="18" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="17" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="16" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="15" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="13" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="12" settings="1">
        <c>0</c>
      </box>
      <box hibit="11" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="10" width="2" name="imod" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="8" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="7" name="A" usename="1">
        <c></c>
      </box>
      <box hibit="6" name="I" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="F" usename="1">
        <c></c>
      </box>
      <box hibit="4" width="5" name="mode" usename="1">
        <c colspan="5"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="imod:M" op="!=" val="000" />
    </decode_constraints>
    <instructiontable iclass="cps" cols="4">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="19*" />
      <col colno="4" printwidth="39*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">imod</th>
          <th class="bitfields">M</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="CPS_T2_AS" iformfile="cps.xml" label="change mode" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="CPS">CPS, CPSID, CPSIE</td>
          <td class="enctags">T2, Change mode</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_12_cps" undef="1" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="CPSIE_T2_ASM" iformfile="cps.xml" label="interrupt enable and change mode" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="CPS">CPS, CPSID, CPSIE</td>
          <td class="enctags">T2, Interrupt enable and change mode</td>
        </tr>
        <tr class="instructiontable" encname="CPSID_T2_ASM" iformfile="cps.xml" label="interrupt disable and change mode" oneofthismnem="3" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="CPS">CPS, CPSID, CPSIE</td>
          <td class="enctags">T2, Interrupt disable and change mode</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="bcond" title="Conditional branch">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="5" settings="5">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="26" name="S" usename="1">
        <c></c>
      </box>
      <box hibit="25" width="4" name="cond" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="21" width="6" name="imm6" usename="1">
        <c colspan="6"></c>
      </box>
      <box hibit="15" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="13" name="J1" usename="1">
        <c></c>
      </box>
      <box hibit="12" settings="1">
        <c>0</c>
      </box>
      <box hibit="11" name="J2" usename="1">
        <c></c>
      </box>
      <box hibit="10" width="11" name="imm11" usename="1">
        <c colspan="11"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="cond&lt;3:1&gt;&lt;3:1&gt;" op="!=" val="111x" />
      <decode_constraint name="cond&lt;3:1&gt;&lt;3:1&gt;" op="!=" val="111x" />
    </decode_constraints>
    <instructiontable iclass="bcond" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="B_T3" iformfile="b.xml" first="t" last="t">
          <td class="iformname" iformid="B">B</td>
          <td class="enctags">T3</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="dcps" title="DCPS">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="12" settings="12">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="imm4" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" settings="4">
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="11" width="10" name="imm10" usename="1">
        <c colspan="10"></c>
      </box>
      <box hibit="1" width="2" name="opt" usename="1">
        <c colspan="2"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="dcps" cols="5">
      <col colno="1" printwidth="9*" />
      <col colno="2" printwidth="15*" />
      <col colno="3" printwidth="5*" />
      <col colno="4" printwidth="18*" />
      <col colno="5" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">imm4</th>
          <th class="bitfields">imm10</th>
          <th class="bitfields">opt</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_dcps" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="10" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_16_dcps" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="10" class="bitfield">!= 0000000000</td>
          <td bitwidth="2" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_12_dcps" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="10" class="bitfield">0000000000</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="DCPS1_T1" iformfile="dcps1.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="10" class="bitfield">0000000000</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="DCPS1">DCPS1</td>
        </tr>
        <tr class="instructiontable" encname="DCPS2_T1" iformfile="dcps2.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="10" class="bitfield">0000000000</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="DCPS2">DCPS2</td>
        </tr>
        <tr class="instructiontable" encname="DCPS3_T1" iformfile="dcps3.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="10" class="bitfield">0000000000</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="DCPS3">DCPS3</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="except" title="Exception generation">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="11" settings="11">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="20" name="o1" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="imm4" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="13" name="o2" usename="1">
        <c></c>
      </box>
      <box hibit="12" settings="1">
        <c>0</c>
      </box>
      <box hibit="11" width="12" name="imm12" usename="1">
        <c colspan="12"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="except" cols="4">
      <col colno="1" printwidth="4*" />
      <col colno="2" printwidth="4*" />
      <col colno="3" printwidth="18*" />
      <col colno="4" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">o1</th>
          <th class="bitfields">o2</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="HVC_T1" iformfile="hvc.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="HVC">HVC</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_12_except" undef="1" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SMC_T1_AS" iformfile="smc.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SMC">SMC</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UDF_T2" iformfile="udf.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="UDF">UDF</td>
          <td class="enctags">T2</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="eret" title="Exception return">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="12" settings="12">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="13" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="12" settings="1">
        <c>0</c>
      </box>
      <box hibit="11" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="10" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="9" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="8" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="7" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="eret" cols="3">
      <col colno="1" printwidth="17*" />
      <col colno="2" printwidth="23*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">Rn:imm8</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="SUBS_PC_T5_AS" iformfile="sub_i.xml" first="t" last="t">
          <td bitwidth="20" class="bitfield">!= 111000000000</td>
          <td class="iformname" iformid="SUB_i">SUB, SUBS (immediate)</td>
          <td class="enctags">T5</td>
        </tr>
        <tr class="instructiontable" encname="ERET_T1" iformfile="eret.xml" first="t" last="t">
          <td bitwidth="20" class="bitfield">111000000000</td>
          <td class="iformname" iformid="ERET">ERET</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="hints" title="Hints">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="12" settings="12">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="19" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="18" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="17" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="16" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="15" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="13" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="12" settings="1">
        <c>0</c>
      </box>
      <box hibit="11" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="10" width="3" settings="3">
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="7" width="4" name="hint" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="3" width="4" name="option" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="hints" cols="4">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="8*" />
      <col colno="3" printwidth="31*" />
      <col colno="4" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">hint</th>
          <th class="bitfields">option</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="NOP_T2" iformfile="nop.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="4" class="bitfield">0000</td>
          <td class="iformname" iformid="NOP">NOP</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="YIELD_T2" iformfile="yield.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td class="iformname" iformid="YIELD">YIELD</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="WFE_T2" iformfile="wfe.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td class="iformname" iformid="WFE">WFE</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="WFI_T2" iformfile="wfi.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td class="iformname" iformid="WFI">WFI</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="SEV_T2" iformfile="sev.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="4" class="bitfield">0100</td>
          <td class="iformname" iformid="SEV">SEV</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="SEVL_T2" iformfile="sevl.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td class="iformname" iformid="SEVL">SEVL</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_17_hints" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="4" class="bitfield">011x</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_18_hints" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="4" class="bitfield">1xxx</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="ESB_T1" arch_version="FEAT_RAS" iformfile="esb.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="4" class="bitfield">0000</td>
          <td class="iformname" iformid="ESB">ESB</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_20_hints" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="TSB_T1" arch_version="FEAT_TRF" iformfile="tsb.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td class="iformname" iformid="TSB">TSB CSYNC</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_22_hints" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="CSDB_T1" iformfile="csdb.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="4" class="bitfield">0100</td>
          <td class="iformname" iformid="CSDB">CSDB</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_24_hints" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="CLRBHB_T1" arch_version="FEAT_CLRBHB" iformfile="clrbhb.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td class="iformname" iformid="CLRBHB">CLRBHB</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_26_hints" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_27_hints" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="4" class="bitfield">1xxx</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_28_hints" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="4" class="bitfield">001x</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_29_hints" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="4" class="bitfield">01xx</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_30_hints" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="4" class="bitfield">10xx</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_31_hints" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="4" class="bitfield">110x</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_32_hints" reserved_nop_hint="1" oneofthismnem="12" first="t" last="t">
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="DBG_T1" iformfile="dbg.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="DBG">DBG</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="mrs_bank" title="MRS (banked)">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="11" settings="11">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="20" name="R" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="m1" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="13" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="12" settings="1">
        <c>0</c>
      </box>
      <box hibit="11" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="6" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="5" settings="1">
        <c>1</c>
      </box>
      <box hibit="4" name="m" usename="1">
        <c></c>
      </box>
      <box hibit="3" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="2" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="1" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="0" settings="1">
        <c>(0)</c>
      </box>
    </regdiagram>
    <instructiontable iclass="mrs_bank" cols="2">
      <col colno="1" printwidth="23*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="MRS_br_T1_AS" iformfile="mrs_br.xml" first="t" last="t">
          <td class="iformname" iformid="MRS_br">MRS (Banked register)</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="mrs_spec" title="MRS (special)">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="11" settings="11">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="20" name="R" usename="1">
        <c></c>
      </box>
      <box hibit="19" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="18" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="17" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="16" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="15" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="13" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="12" settings="1">
        <c>0</c>
      </box>
      <box hibit="11" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="6" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="5" settings="1">
        <c>0</c>
      </box>
      <box hibit="4" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="3" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="2" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="1" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="0" settings="1">
        <c>(0)</c>
      </box>
    </regdiagram>
    <instructiontable iclass="mrs_spec" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="MRS_T1_AS" iformfile="mrs.xml" first="t" last="t">
          <td class="iformname" iformid="MRS">MRS</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="msr_bank" title="MSR (banked)">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="11" settings="11">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="20" name="R" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="13" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="12" settings="1">
        <c>0</c>
      </box>
      <box hibit="11" width="4" name="m1" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="6" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="5" settings="1">
        <c>1</c>
      </box>
      <box hibit="4" name="m" usename="1">
        <c></c>
      </box>
      <box hibit="3" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="2" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="1" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="0" settings="1">
        <c>(0)</c>
      </box>
    </regdiagram>
    <instructiontable iclass="msr_bank" cols="2">
      <col colno="1" printwidth="23*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="MSR_br_T1_AS" iformfile="msr_br.xml" first="t" last="t">
          <td class="iformname" iformid="MSR_br">MSR (Banked register)</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="msr_spec" title="MSR (special)">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="11" settings="11">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="20" name="R" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="13" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="12" settings="1">
        <c>0</c>
      </box>
      <box hibit="11" width="4" name="mask" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="6" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="5" settings="1">
        <c>0</c>
      </box>
      <box hibit="4" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="3" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="2" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="1" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="0" settings="1">
        <c>(0)</c>
      </box>
    </regdiagram>
    <instructiontable iclass="msr_spec" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="MSR_r_T1_AS" iformfile="msr_r.xml" first="t" last="t">
          <td class="iformname" iformid="MSR_r">MSR (register)</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="system" title="Miscellaneous system">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="12" settings="12">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="19" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="18" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="17" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="16" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="15" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="13" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="12" settings="1">
        <c>0</c>
      </box>
      <box hibit="11" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="10" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="9" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="8" settings="1">
        <c>(1)</c>
      </box>
      <box hibit="7" width="4" name="opc" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="3" width="4" name="option" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="system" cols="4">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="9*" />
      <col colno="3" printwidth="18*" />
      <col colno="4" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">opc</th>
          <th class="bitfields">option</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_system" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">000x</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="CLREX_T1" iformfile="clrex.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="CLREX">CLREX</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_13_system" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="DSB_T1" iformfile="dsb.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="4" class="bitfield">!= 0x00</td>
          <td class="iformname" iformid="DSB">DSB</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="SSBB_T1" iformfile="ssbb.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="4" class="bitfield">0000</td>
          <td class="iformname" iformid="SSBB">SSBB</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="PSSBB_T1" iformfile="pssbb.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="4" class="bitfield">0100</td>
          <td class="iformname" iformid="PSSBB">PSSBB</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="DMB_T1" iformfile="dmb.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="DMB">DMB</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="ISB_T1" iformfile="isb.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="ISB">ISB</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="SB_T1" arch_version="FEAT_SB" iformfile="sb.xml" first="t" last="t">
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="SB">SB</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_20_system" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">1xxx</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="b" title="Unconditional branch">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="5" settings="5">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="26" name="S" usename="1">
        <c></c>
      </box>
      <box hibit="25" width="10" name="imm10" usename="1">
        <c colspan="10"></c>
      </box>
      <box hibit="15" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="13" name="J1" usename="1">
        <c></c>
      </box>
      <box hibit="12" settings="1">
        <c>1</c>
      </box>
      <box hibit="11" name="J2" usename="1">
        <c></c>
      </box>
      <box hibit="10" width="11" name="imm11" usename="1">
        <c colspan="11"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="b" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="B_T4" iformfile="b.xml" first="t" last="t">
          <td class="iformname" iformid="B">B</td>
          <td class="enctags">T4</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="bl" title="Unconditional branch and link">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="5" settings="5">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="26" name="S" usename="1">
        <c></c>
      </box>
      <box hibit="25" width="10" name="imm10" usename="1">
        <c colspan="10"></c>
      </box>
      <box hibit="15" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="13" name="J1" usename="1">
        <c></c>
      </box>
      <box hibit="12" settings="1">
        <c>1</c>
      </box>
      <box hibit="11" name="J2" usename="1">
        <c></c>
      </box>
      <box hibit="10" width="11" name="imm11" usename="1">
        <c colspan="11"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="bl" cols="2">
      <col colno="1" printwidth="21*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="BL_i_T1" iformfile="bl_i.xml" first="t" last="t">
          <td class="iformname" iformid="BL_i">BL, BLX (immediate)</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="blx" title="Unconditional branch and link exchange">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="5" settings="5">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="26" name="S" usename="1">
        <c></c>
      </box>
      <box hibit="25" width="10" name="imm10" usename="1">
        <c colspan="10"></c>
      </box>
      <box hibit="15" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="13" name="J1" usename="1">
        <c></c>
      </box>
      <box hibit="12" settings="1">
        <c>0</c>
      </box>
      <box hibit="11" name="J2" usename="1">
        <c></c>
      </box>
      <box hibit="10" width="11" name="imm11" usename="1">
        <c colspan="11"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="blx" cols="2">
      <col colno="1" printwidth="21*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="BL_i_T2" iformfile="bl_i.xml" first="t" last="t">
          <td class="iformname" iformid="BL_i">BL, BLX (immediate)</td>
          <td class="enctags">T2</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="ldst">Load/store single</funcgroupheader>
  <iclass_sect id="ldlit_signed" title="Load, signed (literal)">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="8" settings="8">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="23" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="22" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" width="5" settings="5">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="12" name="imm12" usename="1">
        <c colspan="12"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="ldlit_signed" cols="4">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="9*" />
      <col colno="3" printwidth="31*" />
      <col colno="4" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
          <th class="bitfields">Rt</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="LDRSB_l_T1" iformfile="ldrsb_l.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="LDRSB_l">LDRSB (literal)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="PLI_i_T3" iformfile="pli_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="PLI_i">PLI (immediate, literal)</td>
          <td class="enctags">T3</td>
        </tr>
        <tr class="instructiontable" encname="LDRSH_l_T1" iformfile="ldrsh_l.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="LDRSH_l">LDRSH (literal)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_14_ldlit_signed" reserved_nop_hint="1" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_15_ldlit_signed" undef="1" first="t" last="t">
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldlit_unsigned" title="Load, unsigned (literal)">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="8" settings="8">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="23" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="22" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" settings="4">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="12" name="imm12" usename="1">
        <c colspan="12"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="ldlit_unsigned" cols="5">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="9*" />
      <col colno="4" printwidth="18*" />
      <col colno="5" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
          <th class="bitfields">L</th>
          <th class="bitfields">Rt</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="PLD_l_T1" iformfile="pld_l.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="PLD_l">PLD (literal)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDRB_l_T1" iformfile="ldrb_l.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="LDRB_l">LDRB (literal)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDRH_l_T1" iformfile="ldrh_l.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="LDRH_l">LDRH (literal)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDR_l_T2" iformfile="ldr_l.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="LDR_l">LDR (literal)</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_15_ldlit_unsigned" undef="1" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldst_signed_post" title="Load/store, signed (immediate, post-indexed)">
    <regdiagram form="16x2" psname="" tworows="1">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="22" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" settings="1">
        <c>1</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="9" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="8" settings="1">
        <c>1</c>
      </box>
      <box hibit="7" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="Rn" op="!=" val="1111" />
      <decode_constraint name="Rn" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="ldst_signed_post" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="19*" />
      <col colno="3" printwidth="18*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="LDRSB_i_T2_post" iformfile="ldrsb_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="LDRSB_i">LDRSB (immediate)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRSH_i_T2_post" iformfile="ldrsh_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="LDRSH_i">LDRSH (immediate)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_13_ldst_signed_post" undef="1" first="t" last="t">
          <td bitwidth="2" class="bitfield">1x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldst_signed_pre" title="Load/store, signed (immediate, pre-indexed)">
    <regdiagram form="16x2" psname="" tworows="1">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="22" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" settings="1">
        <c>1</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="9" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="8" settings="1">
        <c>1</c>
      </box>
      <box hibit="7" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="Rn" op="!=" val="1111" />
      <decode_constraint name="Rn" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="ldst_signed_pre" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="19*" />
      <col colno="3" printwidth="17*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="LDRSB_i_T2_pre" iformfile="ldrsb_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="LDRSB_i">LDRSB (immediate)</td>
          <td class="enctags">T2, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRSH_i_T2_pre" iformfile="ldrsh_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="LDRSH_i">LDRSH (immediate)</td>
          <td class="enctags">T2, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_13_ldst_signed_pre" undef="1" first="t" last="t">
          <td bitwidth="2" class="bitfield">1x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldst_signed_nimm" title="Load/store, signed (negative immediate)">
    <regdiagram form="16x2" psname="" tworows="1">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="22" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" settings="1">
        <c>1</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" settings="4">
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="7" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="Rn" op="!=" val="1111" />
      <decode_constraint name="Rn" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="ldst_signed_nimm" cols="4">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="9*" />
      <col colno="3" printwidth="31*" />
      <col colno="4" printwidth="12*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
          <th class="bitfields">Rt</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="LDRSB_i_T2_off" iformfile="ldrsb_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="LDRSB_i">LDRSB (immediate)</td>
          <td class="enctags">T2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="PLI_i_T2" iformfile="pli_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="PLI_i">PLI (immediate, literal)</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="LDRSH_i_T2_off" iformfile="ldrsh_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="LDRSH_i">LDRSH (immediate)</td>
          <td class="enctags">T2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_14_ldst_signed_nimm" reserved_nop_hint="1" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_15_ldst_signed_nimm" undef="1" first="t" last="t">
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldst_signed_pimm" title="Load/store, signed (positive immediate)">
    <regdiagram form="16x2" psname="" tworows="1">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="22" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" settings="1">
        <c>1</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="12" name="imm12" usename="1">
        <c colspan="12"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="Rn" op="!=" val="1111" />
      <decode_constraint name="Rn" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="ldst_signed_pimm" cols="4">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="9*" />
      <col colno="3" printwidth="31*" />
      <col colno="4" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
          <th class="bitfields">Rt</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="LDRSB_i_T1" iformfile="ldrsb_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="LDRSB_i">LDRSB (immediate)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="PLI_i_T1" iformfile="pli_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="PLI_i">PLI (immediate, literal)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDRSH_i_T1" iformfile="ldrsh_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="LDRSH_i">LDRSH (immediate)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_14_ldst_signed_pimm" reserved_nop_hint="1" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldst_signed_reg" title="Load/store, signed (register offset)">
    <regdiagram form="16x2" psname="" tworows="1">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="22" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" settings="1">
        <c>1</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="6" settings="6">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="5" width="2" name="imm2" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="Rn" op="!=" val="1111" />
      <decode_constraint name="Rn" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="ldst_signed_reg" cols="4">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="9*" />
      <col colno="3" printwidth="31*" />
      <col colno="4" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
          <th class="bitfields">Rt</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="LDRSB_r_T2" iformfile="ldrsb_r.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="LDRSB_r">LDRSB (register)</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="PLI_r_T1" iformfile="pli_r.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="PLI_r">PLI (register)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDRSH_r_T2" iformfile="ldrsh_r.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="LDRSH_r">LDRSH (register)</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="RESERVED_nop_hint_14_ldst_signed_reg" reserved_nop_hint="1" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname">Reserved hint, behaves as NOP</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_15_ldst_signed_reg" undef="1" first="t" last="t">
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldst_signed_unpriv" title="Load/store, signed (unprivileged)">
    <regdiagram form="16x2" psname="" tworows="1">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="22" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" settings="1">
        <c>1</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" settings="4">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="7" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="Rn" op="!=" val="1111" />
      <decode_constraint name="Rn" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="ldst_signed_unpriv" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="LDRSBT_T1" iformfile="ldrsbt.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="LDRSBT">LDRSBT</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDRSHT_T1" iformfile="ldrsht.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="LDRSHT">LDRSHT</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_13_ldst_signed_unpriv" undef="1" first="t" last="t">
          <td bitwidth="2" class="bitfield">1x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldst_unsigned_post" title="Load/store, unsigned (immediate, post-indexed)">
    <regdiagram form="16x2" psname="" tworows="1">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="22" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="9" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="8" settings="1">
        <c>1</c>
      </box>
      <box hibit="7" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="Rn" op="!=" val="1111" />
      <decode_constraint name="Rn" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="ldst_unsigned_post" cols="4">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="18*" />
      <col colno="4" printwidth="18*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
          <th class="bitfields">L</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="STRB_i_T3_post" iformfile="strb_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STRB_i">STRB (immediate)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRB_i_T3_post" iformfile="ldrb_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDRB_i">LDRB (immediate)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="STRH_i_T3_post" iformfile="strh_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STRH_i">STRH (immediate)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRH_i_T3_post" iformfile="ldrh_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDRH_i">LDRH (immediate)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="STR_i_T4_post" iformfile="str_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STR_i">STR (immediate)</td>
          <td class="enctags">T4, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDR_i_T4_post" iformfile="ldr_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDR_i">LDR (immediate)</td>
          <td class="enctags">T4, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_17_ldst_unsigned_post" undef="1" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldst_unsigned_pre" title="Load/store, unsigned (immediate, pre-indexed)">
    <regdiagram form="16x2" psname="" tworows="1">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="22" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="9" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="8" settings="1">
        <c>1</c>
      </box>
      <box hibit="7" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="Rn" op="!=" val="1111" />
      <decode_constraint name="Rn" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="ldst_unsigned_pre" cols="4">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="18*" />
      <col colno="4" printwidth="17*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
          <th class="bitfields">L</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="STRB_i_T3_pre" iformfile="strb_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STRB_i">STRB (immediate)</td>
          <td class="enctags">T3, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRB_i_T3_pre" iformfile="ldrb_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDRB_i">LDRB (immediate)</td>
          <td class="enctags">T3, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="STRH_i_T3_pre" iformfile="strh_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STRH_i">STRH (immediate)</td>
          <td class="enctags">T3, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDRH_i_T3_pre" iformfile="ldrh_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDRH_i">LDRH (immediate)</td>
          <td class="enctags">T3, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="STR_i_T4_pre" iformfile="str_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STR_i">STR (immediate)</td>
          <td class="enctags">T4, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="LDR_i_T4_pre" iformfile="ldr_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDR_i">LDR (immediate)</td>
          <td class="enctags">T4, Pre-indexed</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_17_ldst_unsigned_pre" undef="1" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldst_unsigned_nimm" title="Load/store, unsigned (negative immediate)">
    <regdiagram form="16x2" psname="" tworows="1">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="22" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" settings="4">
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="7" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="Rn" op="!=" val="1111" />
      <decode_constraint name="Rn" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="ldst_unsigned_nimm" cols="5">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="9*" />
      <col colno="4" printwidth="23*" />
      <col colno="5" printwidth="19*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
          <th class="bitfields">L</th>
          <th class="bitfields">Rt</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="STRB_i_T3_offn" iformfile="strb_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="STRB_i">STRB (immediate)</td>
          <td class="enctags">T3, Offset</td>
        </tr>
        <tr class="instructiontable" encname="LDRB_i_T3_off" iformfile="ldrb_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="LDRB_i">LDRB (immediate)</td>
          <td class="enctags">T3, Offset</td>
        </tr>
        <tr class="instructiontable" encname="PLD_i_T2" iformfile="pld_i.xml" label="preload read" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="PLD_i">PLD, PLDW (immediate)</td>
          <td class="enctags">T2, Preload read</td>
        </tr>
        <tr class="instructiontable" encname="STRH_i_T3_offn" iformfile="strh_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="STRH_i">STRH (immediate)</td>
          <td class="enctags">T3, Offset</td>
        </tr>
        <tr class="instructiontable" encname="LDRH_i_T3_off" iformfile="ldrh_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="LDRH_i">LDRH (immediate)</td>
          <td class="enctags">T3, Offset</td>
        </tr>
        <tr class="instructiontable" encname="PLDW_i_T2" iformfile="pld_i.xml" label="preload write" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="PLD_i">PLD, PLDW (immediate)</td>
          <td class="enctags">T2, Preload write</td>
        </tr>
        <tr class="instructiontable" encname="STR_i_T4_off" iformfile="str_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="STR_i">STR (immediate)</td>
          <td class="enctags">T4, Offset</td>
        </tr>
        <tr class="instructiontable" encname="LDR_i_T4_off" iformfile="ldr_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="LDR_i">LDR (immediate)</td>
          <td class="enctags">T4, Offset</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_19_ldst_unsigned_nimm" undef="1" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldst_unsigned_pimm" title="Load/store, unsigned (positive immediate)">
    <regdiagram form="16x2" psname="" tworows="1">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="22" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="12" name="imm12" usename="1">
        <c colspan="12"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="Rn" op="!=" val="1111" />
      <decode_constraint name="Rn" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="ldst_unsigned_pimm" cols="5">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="9*" />
      <col colno="4" printwidth="23*" />
      <col colno="5" printwidth="19*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
          <th class="bitfields">L</th>
          <th class="bitfields">Rt</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="STRB_i_T2" iformfile="strb_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="STRB_i">STRB (immediate)</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="LDRB_i_T2" iformfile="ldrb_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="LDRB_i">LDRB (immediate)</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="PLD_i_T1" iformfile="pld_i.xml" label="preload read" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="PLD_i">PLD, PLDW (immediate)</td>
          <td class="enctags">T1, Preload read</td>
        </tr>
        <tr class="instructiontable" encname="STRH_i_T2" iformfile="strh_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="STRH_i">STRH (immediate)</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="LDRH_i_T2" iformfile="ldrh_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="LDRH_i">LDRH (immediate)</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="PLDW_i_T1" iformfile="pld_i.xml" label="preload write" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="PLD_i">PLD, PLDW (immediate)</td>
          <td class="enctags">T1, Preload write</td>
        </tr>
        <tr class="instructiontable" encname="STR_i_T3" iformfile="str_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="STR_i">STR (immediate)</td>
          <td class="enctags">T3</td>
        </tr>
        <tr class="instructiontable" encname="LDR_i_T3" iformfile="ldr_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="LDR_i">LDR (immediate)</td>
          <td class="enctags">T3</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldst_unsigned_reg" title="Load/store, unsigned (register offset)">
    <regdiagram form="16x2" psname="" tworows="1">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="22" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="6" settings="6">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="5" width="2" name="imm2" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="Rn" op="!=" val="1111" />
      <decode_constraint name="Rn" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="ldst_unsigned_reg" cols="5">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="9*" />
      <col colno="4" printwidth="22*" />
      <col colno="5" printwidth="19*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
          <th class="bitfields">L</th>
          <th class="bitfields">Rt</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="STRB_r_T2" iformfile="strb_r.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="STRB_r">STRB (register)</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="LDRB_r_T2" iformfile="ldrb_r.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="LDRB_r">LDRB (register)</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="PLD_r_T1" iformfile="pld_r.xml" label="preload read" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="PLD_r">PLD, PLDW (register)</td>
          <td class="enctags">T1, Preload read</td>
        </tr>
        <tr class="instructiontable" encname="STRH_r_T2" iformfile="strh_r.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="STRH_r">STRH (register)</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="LDRH_r_T2" iformfile="ldrh_r.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="LDRH_r">LDRH (register)</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="PLDW_r_T1" iformfile="pld_r.xml" label="preload write" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="PLD_r">PLD, PLDW (register)</td>
          <td class="enctags">T1, Preload write</td>
        </tr>
        <tr class="instructiontable" encname="STR_r_T2" iformfile="str_r.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="STR_r">STR (register)</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="LDR_r_T2" iformfile="ldr_r.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname" iformid="LDR_r">LDR (register)</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_19_ldst_unsigned_reg" undef="1" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="ldst_unsigned_unpriv" title="Load/store, unsigned (unprivileged)">
    <regdiagram form="16x2" psname="" tworows="1">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="22" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
        <c colspan="4">!= 1111</c>
      </box>
      <box hibit="15" width="4" name="Rt" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" settings="4">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="7" width="8" name="imm8" usename="1">
        <c colspan="8"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="Rn" op="!=" val="1111" />
      <decode_constraint name="Rn" op="!=" val="1111" />
    </decode_constraints>
    <instructiontable iclass="ldst_unsigned_unpriv" cols="4">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="18*" />
      <col colno="4" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
          <th class="bitfields">L</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="STRBT_T1" iformfile="strbt.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STRBT">STRBT</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDRBT_T1" iformfile="ldrbt.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDRBT">LDRBT</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="STRHT_T1" iformfile="strht.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STRHT">STRHT</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDRHT_T1" iformfile="ldrht.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDRHT">LDRHT</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="STRT_T1" iformfile="strt.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="STRT">STRT</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="LDRT_T1" iformfile="ldrt.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="LDRT">LDRT</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_17_ldst_unsigned_unpriv" undef="1" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="vldst">Advanced SIMD element or structure load/store</funcgroupheader>
  <iclass_sect id="asimldall" title="Advanced SIMD load single structure to all lanes">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="20" settings="1">
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="9" width="2" name="N" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="7" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="5" name="T" usename="1">
        <c></c>
      </box>
      <box hibit="4" name="a" usename="1">
        <c></c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="asimldall" cols="6">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="4*" />
      <col colno="3" printwidth="3*" />
      <col colno="4" printwidth="9*" />
      <col colno="5" printwidth="48*" />
      <col colno="6" printwidth="18*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
          <th class="bitfields">N</th>
          <th class="bitfields">a</th>
          <th class="bitfields">Rm</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_11_asimldall" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_a_T1_postr" iformfile="vld1_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD1_a">VLD1 (single element to all lanes)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_a_T1_posti" iformfile="vld1_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD1_a">VLD1 (single element to all lanes)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_a_T1_nowb" iformfile="vld1_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD1_a">VLD1 (single element to all lanes)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_a_T1_postr" iformfile="vld2_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD2_a">VLD2 (single 2-element structure to all lanes)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_a_T1_posti" iformfile="vld2_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD2_a">VLD2 (single 2-element structure to all lanes)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_a_T1_nowb" iformfile="vld2_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD2_a">VLD2 (single 2-element structure to all lanes)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_a_T1_postr" iformfile="vld3_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD3_a">VLD3 (single 3-element structure to all lanes)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_a_T1_posti" iformfile="vld3_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD3_a">VLD3 (single 3-element structure to all lanes)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_a_T1_nowb" iformfile="vld3_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD3_a">VLD3 (single 3-element structure to all lanes)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_12_asimldall" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_a_T1_postr" iformfile="vld4_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD4_a">VLD4 (single 4-element structure to all lanes)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_a_T1_posti" iformfile="vld4_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD4_a">VLD4 (single 4-element structure to all lanes)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_a_T1_nowb" iformfile="vld4_a.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD4_a">VLD4 (single 4-element structure to all lanes)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="asimldstms" title="Advanced SIMD load/store multiple structures">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="20" settings="1">
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="itype" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="5" width="2" name="align" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="asimldstms" cols="5">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="7*" />
      <col colno="3" printwidth="9*" />
      <col colno="4" printwidth="38*" />
      <col colno="5" printwidth="18*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
          <th class="bitfields">itype</th>
          <th class="bitfields">Rm</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VST4_m_T1_postr" iformfile="vst4_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">000x</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST4_m">VST4 (multiple 4-element structures)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST4_m_T1_posti" iformfile="vst4_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">000x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST4_m">VST4 (multiple 4-element structures)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST4_m_T1_nowb" iformfile="vst4_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">000x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST4_m">VST4 (multiple 4-element structures)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_T4_postr" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">T4, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_T4_posti" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">T4, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_T4_nowb" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">T4, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST2_m_T2_postr" iformfile="vst2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST2_m">VST2 (multiple 2-element structures)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST2_m_T2_posti" iformfile="vst2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST2_m">VST2 (multiple 2-element structures)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST2_m_T2_nowb" iformfile="vst2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST2_m">VST2 (multiple 2-element structures)</td>
          <td class="enctags">T2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST3_m_T1_postr" iformfile="vst3_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">010x</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST3_m">VST3 (multiple 3-element structures)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST3_m_T1_posti" iformfile="vst3_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">010x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST3_m">VST3 (multiple 3-element structures)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST3_m_T1_nowb" iformfile="vst3_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">010x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST3_m">VST3 (multiple 3-element structures)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_T3_postr" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_T3_posti" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_T3_nowb" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">T3, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_T1_postr" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_T1_posti" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_T1_nowb" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST2_m_T1_postr" iformfile="vst2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">100x</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST2_m">VST2 (multiple 2-element structures)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST2_m_T1_posti" iformfile="vst2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">100x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST2_m">VST2 (multiple 2-element structures)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST2_m_T1_nowb" iformfile="vst2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">100x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST2_m">VST2 (multiple 2-element structures)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_T2_postr" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_T2_posti" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_m_T2_nowb" iformfile="vst1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST1_m">VST1 (multiple single elements)</td>
          <td class="enctags">T2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_m_T1_postr" iformfile="vld4_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">000x</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD4_m">VLD4 (multiple 4-element structures)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_m_T1_posti" iformfile="vld4_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">000x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD4_m">VLD4 (multiple 4-element structures)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_m_T1_nowb" iformfile="vld4_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">000x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD4_m">VLD4 (multiple 4-element structures)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_T4_postr" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">T4, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_T4_posti" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">T4, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_T4_nowb" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">T4, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_m_T2_postr" iformfile="vld2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD2_m">VLD2 (multiple 2-element structures)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_m_T2_posti" iformfile="vld2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD2_m">VLD2 (multiple 2-element structures)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_m_T2_nowb" iformfile="vld2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD2_m">VLD2 (multiple 2-element structures)</td>
          <td class="enctags">T2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_m_T1_postr" iformfile="vld3_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">010x</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD3_m">VLD3 (multiple 3-element structures)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_m_T1_posti" iformfile="vld3_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">010x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD3_m">VLD3 (multiple 3-element structures)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_m_T1_nowb" iformfile="vld3_m.xml" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">010x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD3_m">VLD3 (multiple 3-element structures)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_59_asimldstms" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_T3_postr" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_T3_posti" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_T3_nowb" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">T3, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_T1_postr" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_T1_posti" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_T1_nowb" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_60_asimldstms" undef="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">11xx</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_m_T1_postr" iformfile="vld2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">100x</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD2_m">VLD2 (multiple 2-element structures)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_m_T1_posti" iformfile="vld2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">100x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD2_m">VLD2 (multiple 2-element structures)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_m_T1_nowb" iformfile="vld2_m.xml" oneofthismnem="6" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">100x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD2_m">VLD2 (multiple 2-element structures)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_T2_postr" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_T2_posti" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_m_T2_nowb" iformfile="vld1_m.xml" oneofthismnem="12" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD1_m">VLD1 (multiple single elements)</td>
          <td class="enctags">T2, Offset</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="asimldstss" title="Advanced SIMD load/store single structure to one lane">
    <regdiagram form="16x2" psname="" tworows="1">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="20" settings="1">
        <c>0</c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" name="size" usename="1" settings="2" constraint="!= 11">
        <c colspan="2">!= 11</c>
      </box>
      <box hibit="9" width="2" name="N" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="7" width="4" name="index_align" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="size" op="!=" val="11" />
      <decode_constraint name="size" op="!=" val="11" />
    </decode_constraints>
    <instructiontable iclass="asimldstss" cols="6">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="6*" />
      <col colno="3" printwidth="4*" />
      <col colno="4" printwidth="9*" />
      <col colno="5" printwidth="49*" />
      <col colno="6" printwidth="18*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">L</th>
          <th class="bitfields">size</th>
          <th class="bitfields">N</th>
          <th class="bitfields">Rm</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VST1_1_T1_postr" iformfile="vst1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST1_1">VST1 (single element from one lane)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_1_T1_posti" iformfile="vst1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST1_1">VST1 (single element from one lane)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_1_T1_nowb" iformfile="vst1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST1_1">VST1 (single element from one lane)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST2_1_T1_postr" iformfile="vst2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST2_1">VST2 (single 2-element structure from one lane)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST2_1_T1_posti" iformfile="vst2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST2_1">VST2 (single 2-element structure from one lane)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST2_1_T1_nowb" iformfile="vst2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST2_1">VST2 (single 2-element structure from one lane)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST3_1_T1_postr" iformfile="vst3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST3_1">VST3 (single 3-element structure from one lane)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST3_1_T1_posti" iformfile="vst3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST3_1">VST3 (single 3-element structure from one lane)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST3_1_T1_nowb" iformfile="vst3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST3_1">VST3 (single 3-element structure from one lane)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST4_1_T1_postr" iformfile="vst4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST4_1">VST4 (single 4-element structure from one lane)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST4_1_T1_posti" iformfile="vst4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST4_1">VST4 (single 4-element structure from one lane)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST4_1_T1_nowb" iformfile="vst4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST4_1">VST4 (single 4-element structure from one lane)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST1_1_T2_postr" iformfile="vst1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST1_1">VST1 (single element from one lane)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_1_T2_posti" iformfile="vst1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST1_1">VST1 (single element from one lane)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_1_T2_nowb" iformfile="vst1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST1_1">VST1 (single element from one lane)</td>
          <td class="enctags">T2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST2_1_T2_postr" iformfile="vst2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST2_1">VST2 (single 2-element structure from one lane)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST2_1_T2_posti" iformfile="vst2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST2_1">VST2 (single 2-element structure from one lane)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST2_1_T2_nowb" iformfile="vst2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST2_1">VST2 (single 2-element structure from one lane)</td>
          <td class="enctags">T2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST3_1_T2_postr" iformfile="vst3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST3_1">VST3 (single 3-element structure from one lane)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST3_1_T2_posti" iformfile="vst3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST3_1">VST3 (single 3-element structure from one lane)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST3_1_T2_nowb" iformfile="vst3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST3_1">VST3 (single 3-element structure from one lane)</td>
          <td class="enctags">T2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST4_1_T2_postr" iformfile="vst4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST4_1">VST4 (single 4-element structure from one lane)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST4_1_T2_posti" iformfile="vst4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST4_1">VST4 (single 4-element structure from one lane)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST4_1_T2_nowb" iformfile="vst4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST4_1">VST4 (single 4-element structure from one lane)</td>
          <td class="enctags">T2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST1_1_T3_postr" iformfile="vst1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST1_1">VST1 (single element from one lane)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_1_T3_posti" iformfile="vst1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST1_1">VST1 (single element from one lane)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST1_1_T3_nowb" iformfile="vst1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST1_1">VST1 (single element from one lane)</td>
          <td class="enctags">T3, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST2_1_T3_postr" iformfile="vst2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST2_1">VST2 (single 2-element structure from one lane)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST2_1_T3_posti" iformfile="vst2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST2_1">VST2 (single 2-element structure from one lane)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST2_1_T3_nowb" iformfile="vst2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST2_1">VST2 (single 2-element structure from one lane)</td>
          <td class="enctags">T3, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST3_1_T3_postr" iformfile="vst3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST3_1">VST3 (single 3-element structure from one lane)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST3_1_T3_posti" iformfile="vst3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST3_1">VST3 (single 3-element structure from one lane)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST3_1_T3_nowb" iformfile="vst3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST3_1">VST3 (single 3-element structure from one lane)</td>
          <td class="enctags">T3, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VST4_1_T3_postr" iformfile="vst4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VST4_1">VST4 (single 4-element structure from one lane)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST4_1_T3_posti" iformfile="vst4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VST4_1">VST4 (single 4-element structure from one lane)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VST4_1_T3_nowb" iformfile="vst4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VST4_1">VST4 (single 4-element structure from one lane)</td>
          <td class="enctags">T3, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_1_T1_postr" iformfile="vld1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD1_1">VLD1 (single element to one lane)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_1_T1_posti" iformfile="vld1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD1_1">VLD1 (single element to one lane)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_1_T1_nowb" iformfile="vld1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD1_1">VLD1 (single element to one lane)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_1_T1_postr" iformfile="vld2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD2_1">VLD2 (single 2-element structure to one lane)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_1_T1_posti" iformfile="vld2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD2_1">VLD2 (single 2-element structure to one lane)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_1_T1_nowb" iformfile="vld2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD2_1">VLD2 (single 2-element structure to one lane)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_1_T1_postr" iformfile="vld3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD3_1">VLD3 (single 3-element structure to one lane)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_1_T1_posti" iformfile="vld3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD3_1">VLD3 (single 3-element structure to one lane)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_1_T1_nowb" iformfile="vld3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD3_1">VLD3 (single 3-element structure to one lane)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_1_T1_postr" iformfile="vld4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD4_1">VLD4 (single 4-element structure to one lane)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_1_T1_posti" iformfile="vld4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD4_1">VLD4 (single 4-element structure to one lane)</td>
          <td class="enctags">T1, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_1_T1_nowb" iformfile="vld4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD4_1">VLD4 (single 4-element structure to one lane)</td>
          <td class="enctags">T1, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_1_T2_postr" iformfile="vld1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD1_1">VLD1 (single element to one lane)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_1_T2_posti" iformfile="vld1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD1_1">VLD1 (single element to one lane)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_1_T2_nowb" iformfile="vld1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD1_1">VLD1 (single element to one lane)</td>
          <td class="enctags">T2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_1_T2_postr" iformfile="vld2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD2_1">VLD2 (single 2-element structure to one lane)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_1_T2_posti" iformfile="vld2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD2_1">VLD2 (single 2-element structure to one lane)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_1_T2_nowb" iformfile="vld2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD2_1">VLD2 (single 2-element structure to one lane)</td>
          <td class="enctags">T2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_1_T2_postr" iformfile="vld3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD3_1">VLD3 (single 3-element structure to one lane)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_1_T2_posti" iformfile="vld3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD3_1">VLD3 (single 3-element structure to one lane)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_1_T2_nowb" iformfile="vld3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD3_1">VLD3 (single 3-element structure to one lane)</td>
          <td class="enctags">T2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_1_T2_postr" iformfile="vld4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD4_1">VLD4 (single 4-element structure to one lane)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_1_T2_posti" iformfile="vld4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD4_1">VLD4 (single 4-element structure to one lane)</td>
          <td class="enctags">T2, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_1_T2_nowb" iformfile="vld4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD4_1">VLD4 (single 4-element structure to one lane)</td>
          <td class="enctags">T2, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_1_T3_postr" iformfile="vld1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD1_1">VLD1 (single element to one lane)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_1_T3_posti" iformfile="vld1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD1_1">VLD1 (single element to one lane)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD1_1_T3_nowb" iformfile="vld1_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD1_1">VLD1 (single element to one lane)</td>
          <td class="enctags">T3, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_1_T3_postr" iformfile="vld2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD2_1">VLD2 (single 2-element structure to one lane)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_1_T3_posti" iformfile="vld2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD2_1">VLD2 (single 2-element structure to one lane)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD2_1_T3_nowb" iformfile="vld2_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD2_1">VLD2 (single 2-element structure to one lane)</td>
          <td class="enctags">T3, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_1_T3_postr" iformfile="vld3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD3_1">VLD3 (single 3-element structure to one lane)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_1_T3_posti" iformfile="vld3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD3_1">VLD3 (single 3-element structure to one lane)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD3_1_T3_nowb" iformfile="vld3_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD3_1">VLD3 (single 3-element structure to one lane)</td>
          <td class="enctags">T3, Offset</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_1_T3_postr" iformfile="vld4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">!= 11x1</td>
          <td class="iformname" iformid="VLD4_1">VLD4 (single 4-element structure to one lane)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_1_T3_posti" iformfile="vld4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VLD4_1">VLD4 (single 4-element structure to one lane)</td>
          <td class="enctags">T3, Post-indexed</td>
        </tr>
        <tr class="instructiontable" encname="VLD4_1_T3_nowb" iformfile="vld4_1.xml" oneofthismnem="9" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VLD4_1">VLD4 (single 4-element structure to one lane)</td>
          <td class="enctags">T3, Offset</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="reg">Data-processing (register)</funcgroupheader>
  <iclass_sect id="dpint_2r" title="Data-processing (two source registers)">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="22" width="3" name="op1" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" settings="4">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="11" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="5" width="2" name="op2" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="dpint_2r" cols="4">
      <col colno="1" printwidth="5*" />
      <col colno="2" printwidth="5*" />
      <col colno="3" printwidth="18*" />
      <col colno="4" printwidth="13*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">op1</th>
          <th class="bitfields">op2</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="QADD_T1" iformfile="qadd.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="QADD">QADD</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="QDADD_T1" iformfile="qdadd.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="QDADD">QDADD</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="QSUB_T1" iformfile="qsub.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="QSUB">QSUB</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="QDSUB_T1" iformfile="qdsub.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="QDSUB">QDSUB</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="REV_T2" iformfile="rev.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="REV">REV</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="REV16_T2" iformfile="rev16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="REV16">REV16</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="RBIT_T1" iformfile="rbit.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="RBIT">RBIT</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="REVSH_T2" iformfile="revsh.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="REVSH">REVSH</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="SEL_T1" iformfile="sel.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="SEL">SEL</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_20_dpint_2r" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_21_dpint_2r" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="CLZ_T1" iformfile="clz.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="CLZ">CLZ</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_23_dpint_2r" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_24_dpint_2r" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="CRC32B_T1" arch_version="FEAT_CRC32" iformfile="crc32.xml" label="CRC32B" oneofthismnem="3" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="CRC32">CRC32</td>
          <td class="enctags">T1, CRC32B</td>
        </tr>
        <tr class="instructiontable" encname="CRC32H_T1" arch_version="FEAT_CRC32" iformfile="crc32.xml" label="CRC32H" oneofthismnem="3" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="CRC32">CRC32</td>
          <td class="enctags">T1, CRC32H</td>
        </tr>
        <tr class="instructiontable" encname="CRC32W_T1" arch_version="FEAT_CRC32" iformfile="crc32.xml" label="CRC32W" oneofthismnem="3" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="CRC32">CRC32</td>
          <td class="enctags">T1, CRC32W</td>
        </tr>
        <tr class="instructiontable" encname="UNPREDICTABLE_28_dpint_2r" unpred="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname">UNPREDICTABLE</td>
        </tr>
        <tr class="instructiontable" encname="CRC32CB_T1" arch_version="FEAT_CRC32" iformfile="crc32c.xml" label="CRC32CB" oneofthismnem="3" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="CRC32C">CRC32C</td>
          <td class="enctags">T1, CRC32CB</td>
        </tr>
        <tr class="instructiontable" encname="CRC32CH_T1" arch_version="FEAT_CRC32" iformfile="crc32c.xml" label="CRC32CH" oneofthismnem="3" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="CRC32C">CRC32C</td>
          <td class="enctags">T1, CRC32CH</td>
        </tr>
        <tr class="instructiontable" encname="CRC32CW_T1" arch_version="FEAT_CRC32" iformfile="crc32c.xml" label="CRC32CW" oneofthismnem="3" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="CRC32C">CRC32C</td>
          <td class="enctags">T1, CRC32CW</td>
        </tr>
        <tr class="instructiontable" encname="UNPREDICTABLE_32_dpint_2r" unpred="1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname">UNPREDICTABLE</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_33_dpint_2r" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="3" class="bitfield">11x</td>
          <td bitwidth="2" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="addsub_par" title="Parallel add-subtract">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
      </box>
      <box hibit="22" width="3" name="op1" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" settings="4">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="11" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" settings="1">
        <c>0</c>
      </box>
      <box hibit="6" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="H" usename="1">
        <c></c>
      </box>
      <box hibit="4" name="S" usename="1">
        <c></c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="addsub_par" cols="6">
      <col colno="1" printwidth="5*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="3*" />
      <col colno="4" printwidth="3*" />
      <col colno="5" printwidth="18*" />
      <col colno="6" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">op1</th>
          <th class="bitfields">U</th>
          <th class="bitfields">H</th>
          <th class="bitfields">S</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="SADD8_T1" iformfile="sadd8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SADD8">SADD8</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="QADD8_T1" iformfile="qadd8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="QADD8">QADD8</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="SHADD8_T1" iformfile="shadd8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SHADD8">SHADD8</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_14_addsub_par" undef="1" oneofthismnem="13" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UADD8_T1" iformfile="uadd8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="UADD8">UADD8</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UQADD8_T1" iformfile="uqadd8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="UQADD8">UQADD8</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UHADD8_T1" iformfile="uhadd8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="UHADD8">UHADD8</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_18_addsub_par" undef="1" oneofthismnem="13" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SADD16_T1" iformfile="sadd16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SADD16">SADD16</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="QADD16_T1" iformfile="qadd16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="QADD16">QADD16</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="SHADD16_T1" iformfile="shadd16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SHADD16">SHADD16</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_22_addsub_par" undef="1" oneofthismnem="13" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UADD16_T1" iformfile="uadd16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="UADD16">UADD16</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UQADD16_T1" iformfile="uqadd16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="UQADD16">UQADD16</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UHADD16_T1" iformfile="uhadd16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="UHADD16">UHADD16</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_26_addsub_par" undef="1" oneofthismnem="13" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SASX_T1" iformfile="sasx.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SASX">SASX</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="QASX_T1" iformfile="qasx.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="QASX">QASX</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="SHASX_T1" iformfile="shasx.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SHASX">SHASX</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_30_addsub_par" undef="1" oneofthismnem="13" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UASX_T1" iformfile="uasx.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="UASX">UASX</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UQASX_T1" iformfile="uqasx.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="UQASX">UQASX</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UHASX_T1" iformfile="uhasx.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="UHASX">UHASX</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_34_addsub_par" undef="1" oneofthismnem="13" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SSUB8_T1" iformfile="ssub8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SSUB8">SSUB8</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="QSUB8_T1" iformfile="qsub8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="QSUB8">QSUB8</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="SHSUB8_T1" iformfile="shsub8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SHSUB8">SHSUB8</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_38_addsub_par" undef="1" oneofthismnem="13" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="USUB8_T1" iformfile="usub8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="USUB8">USUB8</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UQSUB8_T1" iformfile="uqsub8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="UQSUB8">UQSUB8</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UHSUB8_T1" iformfile="uhsub8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="UHSUB8">UHSUB8</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_42_addsub_par" undef="1" oneofthismnem="13" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SSUB16_T1" iformfile="ssub16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SSUB16">SSUB16</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="QSUB16_T1" iformfile="qsub16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="QSUB16">QSUB16</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="SHSUB16_T1" iformfile="shsub16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SHSUB16">SHSUB16</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_46_addsub_par" undef="1" oneofthismnem="13" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="USUB16_T1" iformfile="usub16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="USUB16">USUB16</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UQSUB16_T1" iformfile="uqsub16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="UQSUB16">UQSUB16</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UHSUB16_T1" iformfile="uhsub16.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="UHSUB16">UHSUB16</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_50_addsub_par" undef="1" oneofthismnem="13" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SSAX_T1" iformfile="ssax.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SSAX">SSAX</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="QSAX_T1" iformfile="qsax.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="QSAX">QSAX</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="SHSAX_T1" iformfile="shsax.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SHSAX">SHSAX</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_54_addsub_par" undef="1" oneofthismnem="13" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="USAX_T1" iformfile="usax.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="USAX">USAX</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UQSAX_T1" iformfile="uqsax.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="UQSAX">UQSAX</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UHSAX_T1" iformfile="uhsax.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="UHSAX">UHSAX</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_58_addsub_par" undef="1" oneofthismnem="13" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_59_addsub_par" undef="1" oneofthismnem="13" first="t" last="t">
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="extendr" title="Register extends">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="22" width="2" name="op1" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" settings="4">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="11" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" settings="1">
        <c>1</c>
      </box>
      <box hibit="6" settings="1">
        <c>(0)</c>
      </box>
      <box hibit="5" width="2" name="rotate" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="extendr" cols="5">
      <col colno="1" printwidth="5*" />
      <col colno="2" printwidth="3*" />
      <col colno="3" printwidth="9*" />
      <col colno="4" printwidth="18*" />
      <col colno="5" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">op1</th>
          <th class="bitfields">U</th>
          <th class="bitfields">Rn</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="SXTAH_T1" iformfile="sxtah.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="SXTAH">SXTAH</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="SXTH_T2" iformfile="sxth.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="SXTH">SXTH</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="UXTAH_T1" iformfile="uxtah.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="UXTAH">UXTAH</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UXTH_T2" iformfile="uxth.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="UXTH">UXTH</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="SXTAB16_T1" iformfile="sxtab16.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="SXTAB16">SXTAB16</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="SXTB16_T1" iformfile="sxtb16.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="SXTB16">SXTB16</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UXTAB16_T1" iformfile="uxtab16.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="UXTAB16">UXTAB16</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UXTB16_T1" iformfile="uxtb16.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="UXTB16">UXTB16</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="SXTAB_T1" iformfile="sxtab.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="SXTAB">SXTAB</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="SXTB_T2" iformfile="sxtb.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="SXTB">SXTB</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="UXTAB_T1" iformfile="uxtab.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname" iformid="UXTAB">UXTAB</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UXTB_T2" iformfile="uxtb.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="UXTB">UXTB</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_23_extendr" undef="1" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="shiftr" title="Register shifts">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="22" width="2" name="stype" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="20" name="S" usename="1">
        <c></c>
      </box>
      <box hibit="19" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" settings="4">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="11" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" width="4" settings="4">
        <c>0</c>
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Rs" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="shiftr" cols="2">
      <col colno="1" printwidth="39*" />
      <col colno="2" printwidth="18*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="MOVS_rr_T2" iformfile="mov_rr.xml" first="t" last="t">
          <td class="iformname" iformid="MOV_rr">MOV, MOVS (register-shifted register)</td>
          <td class="enctags">T2, Flag setting</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="mul">Multiply, multiply accumulate, and absolute difference</funcgroupheader>
  <iclass_sect id="mul_abd" title="Multiply and absolute difference">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="22" width="3" name="op1" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Ra" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="Rd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" width="2" settings="2">
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="5" width="2" name="op2" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="mul_abd" cols="5">
      <col colno="1" printwidth="5*" />
      <col colno="2" printwidth="9*" />
      <col colno="3" printwidth="5*" />
      <col colno="4" printwidth="32*" />
      <col colno="5" printwidth="12*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">op1</th>
          <th class="bitfields">Ra</th>
          <th class="bitfields">op2</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="MLA_T1" iformfile="mla.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="MLA">MLA, MLAS</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="MLS_T1" iformfile="mls.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="MLS">MLS</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_14_mul_abd" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="MUL_T2" iformfile="mul.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="MUL">MUL, MULS</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="SMLABB_T1" iformfile="smlabb.xml" label="SMLABB" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="SMLABB">SMLABB, SMLABT, SMLATB, SMLATT</td>
          <td class="enctags">T1, SMLABB</td>
        </tr>
        <tr class="instructiontable" encname="SMLABT_T1" iformfile="smlabb.xml" label="SMLABT" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="SMLABB">SMLABB, SMLABT, SMLATB, SMLATT</td>
          <td class="enctags">T1, SMLABT</td>
        </tr>
        <tr class="instructiontable" encname="SMLATB_T1" iformfile="smlabb.xml" label="SMLATB" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="SMLABB">SMLABB, SMLABT, SMLATB, SMLATT</td>
          <td class="enctags">T1, SMLATB</td>
        </tr>
        <tr class="instructiontable" encname="SMLATT_T1" iformfile="smlabb.xml" label="SMLATT" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="SMLABB">SMLABB, SMLABT, SMLATB, SMLATT</td>
          <td class="enctags">T1, SMLATT</td>
        </tr>
        <tr class="instructiontable" encname="SMULBB_T1" iformfile="smulbb.xml" label="SMULBB" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="SMULBB">SMULBB, SMULBT, SMULTB, SMULTT</td>
          <td class="enctags">T1, SMULBB</td>
        </tr>
        <tr class="instructiontable" encname="SMULBT_T1" iformfile="smulbb.xml" label="SMULBT" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="SMULBB">SMULBB, SMULBT, SMULTB, SMULTT</td>
          <td class="enctags">T1, SMULBT</td>
        </tr>
        <tr class="instructiontable" encname="SMULTB_T1" iformfile="smulbb.xml" label="SMULTB" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td class="iformname" iformid="SMULBB">SMULBB, SMULBT, SMULTB, SMULTT</td>
          <td class="enctags">T1, SMULTB</td>
        </tr>
        <tr class="instructiontable" encname="SMULTT_T1" iformfile="smulbb.xml" label="SMULTT" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td class="iformname" iformid="SMULBB">SMULBB, SMULBT, SMULTB, SMULTT</td>
          <td class="enctags">T1, SMULTT</td>
        </tr>
        <tr class="instructiontable" encname="SMLAD_T1" iformfile="smlad.xml" label="SMLAD" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="SMLAD">SMLAD, SMLADX</td>
          <td class="enctags">T1, SMLAD</td>
        </tr>
        <tr class="instructiontable" encname="SMLADX_T1" iformfile="smlad.xml" label="SMLADX" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="SMLAD">SMLAD, SMLADX</td>
          <td class="enctags">T1, SMLADX</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_27_mul_abd" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SMUAD_T1" iformfile="smuad.xml" label="SMUAD" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="SMUAD">SMUAD, SMUADX</td>
          <td class="enctags">T1, SMUAD</td>
        </tr>
        <tr class="instructiontable" encname="SMUADX_T1" iformfile="smuad.xml" label="SMUADX" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="SMUAD">SMUAD, SMUADX</td>
          <td class="enctags">T1, SMUADX</td>
        </tr>
        <tr class="instructiontable" encname="SMLAWB_T1" iformfile="smlawb.xml" label="SMLAWB" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="SMLAWB">SMLAWB, SMLAWT</td>
          <td class="enctags">T1, SMLAWB</td>
        </tr>
        <tr class="instructiontable" encname="SMLAWT_T1" iformfile="smlawb.xml" label="SMLAWT" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="SMLAWB">SMLAWB, SMLAWT</td>
          <td class="enctags">T1, SMLAWT</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_32_mul_abd" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SMULWB_T1" iformfile="smulwb.xml" label="SMULWB" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="SMULWB">SMULWB, SMULWT</td>
          <td class="enctags">T1, SMULWB</td>
        </tr>
        <tr class="instructiontable" encname="SMULWT_T1" iformfile="smulwb.xml" label="SMULWT" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="SMULWB">SMULWB, SMULWT</td>
          <td class="enctags">T1, SMULWT</td>
        </tr>
        <tr class="instructiontable" encname="SMLSD_T1" iformfile="smlsd.xml" label="SMLSD" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="SMLSD">SMLSD, SMLSDX</td>
          <td class="enctags">T1, SMLSD</td>
        </tr>
        <tr class="instructiontable" encname="SMLSDX_T1" iformfile="smlsd.xml" label="SMLSDX" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="SMLSD">SMLSD, SMLSDX</td>
          <td class="enctags">T1, SMLSDX</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_37_mul_abd" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SMUSD_T1" iformfile="smusd.xml" label="SMUSD" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="SMUSD">SMUSD, SMUSDX</td>
          <td class="enctags">T1, SMUSD</td>
        </tr>
        <tr class="instructiontable" encname="SMUSDX_T1" iformfile="smusd.xml" label="SMUSDX" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="SMUSD">SMUSD, SMUSDX</td>
          <td class="enctags">T1, SMUSDX</td>
        </tr>
        <tr class="instructiontable" encname="SMMLA_T1" iformfile="smmla.xml" label="SMMLA" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="SMMLA">SMMLA, SMMLAR</td>
          <td class="enctags">T1, SMMLA</td>
        </tr>
        <tr class="instructiontable" encname="SMMLAR_T1" iformfile="smmla.xml" label="SMMLAR" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="SMMLA">SMMLA, SMMLAR</td>
          <td class="enctags">T1, SMMLAR</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_42_mul_abd" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SMMUL_T1" iformfile="smmul.xml" label="SMMUL" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="SMMUL">SMMUL, SMMULR</td>
          <td class="enctags">T1, SMMUL</td>
        </tr>
        <tr class="instructiontable" encname="SMMULR_T1" iformfile="smmul.xml" label="SMMULR" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="SMMUL">SMMUL, SMMULR</td>
          <td class="enctags">T1, SMMULR</td>
        </tr>
        <tr class="instructiontable" encname="SMMLS_T1" iformfile="smmls.xml" label="SMMLS" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="SMMLS">SMMLS, SMMLSR</td>
          <td class="enctags">T1, SMMLS</td>
        </tr>
        <tr class="instructiontable" encname="SMMLSR_T1" iformfile="smmls.xml" label="SMMLSR" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname" iformid="SMMLS">SMMLS, SMMLSR</td>
          <td class="enctags">T1, SMMLSR</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_45_mul_abd" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="USADA8_T1" iformfile="usada8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="USADA8">USADA8</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_48_mul_abd" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_49_mul_abd" undef="1" oneofthismnem="8" first="t" last="t">
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="4" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="USAD8_T1" iformfile="usad8.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td class="iformname" iformid="USAD8">USAD8</td>
          <td class="enctags">T1</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="t_simd_3r_same">Advanced SIMD three registers of the same length</funcgroupheader>
  <iclass_sect id="simd_3same" title="Advanced SIMD three registers of the same length">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="3" settings="3">
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="28" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="opc" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" name="Q" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" name="o1" usename="1">
        <c></c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="simd_3same" cols="7">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="6*" />
      <col colno="3" printwidth="6*" />
      <col colno="4" printwidth="3*" />
      <col colno="5" printwidth="4*" />
      <col colno="6" printwidth="31*" />
      <col colno="7" printwidth="25*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">U</th>
          <th class="bitfields">size</th>
          <th class="bitfields">opc</th>
          <th class="bitfields">Q</th>
          <th class="bitfields">o1</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VFMA_T1_Q" iformfile="vfma.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFMA">VFMA</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VADD_f_T1_Q" iformfile="vadd_f.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VADD_f">VADD (floating-point)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VMLA_f_T1_Q" iformfile="vmla_f.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMLA_f">VMLA (floating-point)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="t2" iformfile="vceq_r.xml" label="T2" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCEQ_r">VCEQ (register)</td>
          <td class="enctags">T2, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VMAX_f_T1_Q" iformfile="vmax_f.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMAX_f">VMAX (floating-point)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VRECPS_T1_Q" iformfile="vrecps.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VRECPS">VRECPS</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VHADD_T1_Q" iformfile="vhadd.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VHADD">VHADD</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VAND_r_T1_Q" iformfile="vand_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VAND_r">VAND (register)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQADD_T1_Q" iformfile="vqadd.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VQADD">VQADD</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VRHADD_T1_Q" iformfile="vrhadd.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRHADD">VRHADD</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="SHA1C_T1" arch_version="FEAT_SHA1" iformfile="sha1c.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SHA1C">SHA1C</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VHSUB_T1_Q" iformfile="vhsub.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VHSUB">VHSUB</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VBIC_r_T1_Q" iformfile="vbic_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VBIC_r">VBIC (register)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQSUB_T1_Q" iformfile="vqsub.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VQSUB">VQSUB</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="t1" iformfile="vcgt_r.xml" label="T1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCGT_r">VCGT (register)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="t1" iformfile="vcge_r.xml" label="T1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCGE_r">VCGE (register)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="SHA1P_T1" arch_version="FEAT_SHA1" iformfile="sha1p.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SHA1P">SHA1P</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VFMS_T1_Q" iformfile="vfms.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VFMS">VFMS</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSUB_f_T1_Q" iformfile="vsub_f.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VSUB_f">VSUB (floating-point)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VMLS_f_T1_Q" iformfile="vmls_f.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMLS_f">VMLS (floating-point)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_109_simd_3same" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VMIN_f_T1_Q" iformfile="vmin_f.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMIN_f">VMIN (floating-point)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VRSQRTS_T1_Q" iformfile="vrsqrts.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VRSQRTS">VRSQRTS</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSHL_r_T1_Q" iformfile="vshl_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VSHL_r">VSHL (register)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VADD_i_T1_Q" iformfile="vadd_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VADD_i">VADD (integer)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VORR_r_T1_Q" iformfile="vorr_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VORR_r">VORR (register)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VTST_T1_Q" iformfile="vtst.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VTST">VTST</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQSHL_r_T1_Q" iformfile="vqshl_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VQSHL_r">VQSHL (register)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VMLA_i_T1_Q" iformfile="vmla_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMLA_i">VMLA (integer)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VRSHL_T1_Q" iformfile="vrshl.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VRSHL">VRSHL</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQRSHL_T1_Q" iformfile="vqrshl.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VQRSHL">VQRSHL</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQDMULH_T1_Q" iformfile="vqdmulh.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VQDMULH">VQDMULH</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="SHA1M_T1" arch_version="FEAT_SHA1" iformfile="sha1m.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SHA1M">SHA1M</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VPADD_i_T1" iformfile="vpadd_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VPADD_i">VPADD (integer)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VMAX_i_T1_Q" iformfile="vmax_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMAX_i">VMAX (integer)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VORN_r_T1_Q" iformfile="vorn_r.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VORN_r">VORN (register)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VMIN_i_T1_Q" iformfile="vmin_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMIN_i">VMIN (integer)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VABD_i_T1_Q" iformfile="vabd_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VABD_i">VABD (integer)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VABA_T1_Q" iformfile="vaba.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VABA">VABA</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="SHA1SU0_T1" arch_version="FEAT_SHA1" iformfile="sha1su0.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SHA1SU0">SHA1SU0</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VPADD_f_T1" iformfile="vpadd_f.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VPADD_f">VPADD (floating-point)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VMUL_f_T1_Q" iformfile="vmul_f.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMUL_f">VMUL (floating-point)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="t2" iformfile="vcge_r.xml" label="T2" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCGE_r">VCGE (register)</td>
          <td class="enctags">T2, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VACGE_T1_Q" iformfile="vacge.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VACGE">VACGE</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VPMAX_f_T1" iformfile="vpmax_f.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VPMAX_f">VPMAX (floating-point)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VMAXNM_T1_Q" iformfile="vmaxnm.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">0x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMAXNM">VMAXNM</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VEOR_T1_Q" iformfile="veor.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VEOR">VEOR</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VMUL_i_T1_Q" iformfile="vmul_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMUL_i">VMUL (integer and polynomial)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="SHA256H_T1" arch_version="FEAT_SHA256" iformfile="sha256h.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SHA256H">SHA256H</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VPMAX_i_T1" iformfile="vpmax_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VPMAX_i">VPMAX (integer)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VBSL_T1_Q" iformfile="vbsl.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VBSL">VBSL</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VPMIN_i_T1" iformfile="vpmin_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VPMIN_i">VPMIN (integer)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_65_simd_3same" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SHA256H2_T1" arch_version="FEAT_SHA256" iformfile="sha256h2.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SHA256H2">SHA256H2</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VABD_f_T1_Q" iformfile="vabd_f.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VABD_f">VABD (floating-point)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="t2" iformfile="vcgt_r.xml" label="T2" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCGT_r">VCGT (register)</td>
          <td class="enctags">T2, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VACGT_T1_Q" iformfile="vacgt.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VACGT">VACGT</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VPMIN_f_T1" iformfile="vpmin_f.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VPMIN_f">VPMIN (floating-point)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VMINNM_T1_Q" iformfile="vminnm.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">1x</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMINNM">VMINNM</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSUB_i_T1_Q" iformfile="vsub_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VSUB_i">VSUB (integer)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VBIT_T1_Q" iformfile="vbit.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VBIT">VBIT</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="t1" iformfile="vceq_r.xml" label="T1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCEQ_r">VCEQ (register)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VMLS_i_T1_Q" iformfile="vmls_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMLS_i">VMLS (integer)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQRDMULH_T1_Q" iformfile="vqrdmulh.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VQRDMULH">VQRDMULH</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="SHA256SU1_T1" arch_version="FEAT_SHA256" iformfile="sha256su1.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SHA256SU1">SHA256SU1</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VQRDMLAH_T1_Q" arch_version="FEAT_RDM" iformfile="vqrdmlah.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VQRDMLAH">VQRDMLAH</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VBIF_T1_Q" iformfile="vbif.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VBIF">VBIF</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQRDMLSH_T1_Q" arch_version="FEAT_RDM" iformfile="vqrdmlsh.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VQRDMLSH">VQRDMLSH</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_124_simd_3same" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="t_simd_mulreg">Advanced SIMD two registers, or three registers of different lengths</funcgroupheader>
  <iclass_sect id="simd_dup_sc" title="Advanced SIMD duplicate (scalar)">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="19" width="4" name="imm4" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="9" width="3" name="opc" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="6" name="Q" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="simd_dup_sc" cols="3">
      <col colno="1" printwidth="15*" />
      <col colno="2" printwidth="18*" />
      <col colno="3" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">opc</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VDUP_s_T1_Q" iformfile="vdup_s.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td class="iformname" iformid="VDUP_s">VDUP (scalar)</td>
          <td class="enctags">T1, </td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_13_simd_dup_sc" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_14_simd_dup_sc" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="3" class="bitfield">01x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_15_simd_dup_sc" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="3" class="bitfield">1xx</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="simd_tbl" title="Advanced SIMD table permute">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="2" settings="2">
        <c>1</c>
        <c>0</c>
      </box>
      <box hibit="9" width="2" name="len" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" name="op" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="simd_tbl" cols="2">
      <col colno="1" printwidth="18*" />
      <col colno="2" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VTBX_T1" iformfile="vtbl.xml" first="t" last="t">
          <td class="iformname" iformid="VTBL">VTBL, VTBX</td>
          <td class="enctags">T1, VTBX</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="simd_3diff" title="Advanced SIMD three registers of different lengths">
    <regdiagram form="16x2" psname="" tworows="1">
      <box hibit="31" width="3" settings="3">
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="28" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
        <c colspan="2">!= 11</c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="opc" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" settings="1">
        <c>0</c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="size" op="!=" val="11" />
      <decode_constraint name="size" op="!=" val="11" />
    </decode_constraints>
    <instructiontable iclass="simd_3diff" cols="4">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="6*" />
      <col colno="3" printwidth="32*" />
      <col colno="4" printwidth="10*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">U</th>
          <th class="bitfields">opc</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VADDL_T1" iformfile="vaddl.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0000</td>
          <td class="iformname" iformid="VADDL">VADDL</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VADDW_T1" iformfile="vaddw.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td class="iformname" iformid="VADDW">VADDW</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VSUBL_T1" iformfile="vsubl.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td class="iformname" iformid="VSUBL">VSUBL</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VADDHN_T1" iformfile="vaddhn.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0100</td>
          <td class="iformname" iformid="VADDHN">VADDHN</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VSUBW_T1" iformfile="vsubw.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td class="iformname" iformid="VSUBW">VSUBW</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VSUBHN_T1" iformfile="vsubhn.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td class="iformname" iformid="VSUBHN">VSUBHN</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VQDMLAL_T1" iformfile="vqdmlal.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1001</td>
          <td class="iformname" iformid="VQDMLAL">VQDMLAL</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VABAL_T1" iformfile="vabal.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td class="iformname" iformid="VABAL">VABAL</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VQDMLSL_T1" iformfile="vqdmlsl.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td class="iformname" iformid="VQDMLSL">VQDMLSL</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VQDMULL_T1" iformfile="vqdmull.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VQDMULL">VQDMULL</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VABDL_i_T1" iformfile="vabdl_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td class="iformname" iformid="VABDL_i">VABDL (integer)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VMLAL_i_T1" iformfile="vmlal_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td class="iformname" iformid="VMLAL_i">VMLAL (integer)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VMLSL_i_T1" iformfile="vmlsl_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td class="iformname" iformid="VMLSL_i">VMLSL (integer)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VRADDHN_T1" iformfile="vraddhn.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0100</td>
          <td class="iformname" iformid="VRADDHN">VRADDHN</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VRSUBHN_T1" iformfile="vrsubhn.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td class="iformname" iformid="VRSUBHN">VRSUBHN</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VMULL_i_T1" iformfile="vmull_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">11x0</td>
          <td class="iformname" iformid="VMULL_i">VMULL (integer and polynomial)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_23_simd_3diff" undef="1" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1001</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_26_simd_3diff" undef="1" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_29_simd_3diff" undef="1" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_30_simd_3diff" undef="1" oneofthismnem="4" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="simd_2r_sc" title="Advanced SIMD two registers and a scalar">
    <regdiagram form="16x2" psname="" tworows="1">
      <box hibit="31" width="3" settings="3">
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="28" name="Q" usename="1">
        <c></c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
        <c colspan="2">!= 11</c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="opc" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" settings="1">
        <c>1</c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="size" op="!=" val="11" />
      <decode_constraint name="size" op="!=" val="11" />
    </decode_constraints>
    <instructiontable iclass="simd_2r_sc" cols="4">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="6*" />
      <col colno="3" printwidth="19*" />
      <col colno="4" printwidth="25*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">Q</th>
          <th class="bitfields">opc</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VMLA_s_T1_Q" iformfile="vmla_s.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">000x</td>
          <td class="iformname" iformid="VMLA_s">VMLA (by scalar)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQDMLAL_T2" iformfile="vqdmlal.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td class="iformname" iformid="VQDMLAL">VQDMLAL</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="VMLAL_s_T1" iformfile="vmlal_s.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td class="iformname" iformid="VMLAL_s">VMLAL (by scalar)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VQDMLSL_T2" iformfile="vqdmlsl.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td class="iformname" iformid="VQDMLSL">VQDMLSL</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="VMLS_s_T1_Q" iformfile="vmls_s.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">010x</td>
          <td class="iformname" iformid="VMLS_s">VMLS (by scalar)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQDMULL_T2" iformfile="vqdmull.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td class="iformname" iformid="VQDMULL">VQDMULL</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="VMLSL_s_T1" iformfile="vmlsl_s.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td class="iformname" iformid="VMLSL_s">VMLSL (by scalar)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VMUL_s_T1_Q" iformfile="vmul_s.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">100x</td>
          <td class="iformname" iformid="VMUL_s">VMUL (by scalar)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_15_simd_2r_sc" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VMULL_s_T1" iformfile="vmull_s.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td class="iformname" iformid="VMULL_s">VMULL (by scalar)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_20_simd_2r_sc" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VQDMULH_T2_Q" iformfile="vqdmulh.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td class="iformname" iformid="VQDMULH">VQDMULH</td>
          <td class="enctags">T2, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQRDMULH_T2_Q" iformfile="vqrdmulh.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="VQRDMULH">VQRDMULH</td>
          <td class="enctags">T2, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_25_simd_2r_sc" undef="1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VQRDMLAH_T2_Q" arch_version="FEAT_RDM" iformfile="vqrdmlah.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1110</td>
          <td class="iformname" iformid="VQRDMLAH">VQRDMLAH</td>
          <td class="enctags">T2, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQRDMLSH_T2_Q" arch_version="FEAT_RDM" iformfile="vqrdmlsh.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="VQRDMLSH">VQRDMLSH</td>
          <td class="enctags">T2, 128-bit SIMD vector</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="simd_2r_misc" title="Advanced SIMD two registers misc">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="19" width="2" name="size" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="17" width="2" name="opc1" usename="1">
        <c colspan="2"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" settings="1">
        <c>0</c>
      </box>
      <box hibit="10" width="4" name="opc2" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="6" name="Q" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="simd_2r_misc" cols="6">
      <col colno="1" printwidth="6*" />
      <col colno="2" printwidth="6*" />
      <col colno="3" printwidth="6*" />
      <col colno="4" printwidth="3*" />
      <col colno="5" printwidth="67*" />
      <col colno="6" printwidth="40*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">size</th>
          <th class="bitfields">opc1</th>
          <th class="bitfields">opc2</th>
          <th class="bitfields">Q</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VREV64_T1_Q" iformfile="vrev64.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VREV64">VREV64</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VREV32_T1_Q" iformfile="vrev32.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VREV32">VREV32</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VREV16_T1_Q" iformfile="vrev16.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VREV16">VREV16</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_17_simd_2r_misc" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VPADDL_T1_Q" iformfile="vpaddl.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">010x</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VPADDL">VPADDL</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="AESE_T1" arch_version="FEAT_AES" iformfile="aese.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="AESE">AESE</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="AESD_T1" arch_version="FEAT_AES" iformfile="aesd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="AESD">AESD</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="AESMC_T1" arch_version="FEAT_AES" iformfile="aesmc.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="AESMC">AESMC</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="AESIMC_T1" arch_version="FEAT_AES" iformfile="aesimc.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="AESIMC">AESIMC</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VCLS_T1_Q" iformfile="vcls.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCLS">VCLS</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSWP_T1_Q" iformfile="vswp.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VSWP">VSWP</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCLZ_T1_Q" iformfile="vclz.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCLZ">VCLZ</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCNT_T1_Q" iformfile="vcnt.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCNT">VCNT</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VMVN_r_T1_Q" iformfile="vmvn_r.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VMVN_r">VMVN (register)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_76_simd_2r_misc" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VPADAL_T1_Q" iformfile="vpadal.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">110x</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VPADAL">VPADAL</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQABS_T1_Q" iformfile="vqabs.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VQABS">VQABS</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQNEG_T1_Q" iformfile="vqneg.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">00</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VQNEG">VQNEG</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCGT_i_T1_Q" iformfile="vcgt_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">x000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCGT_i">VCGT (immediate #0)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCGE_i_T1_Q" iformfile="vcge_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">x001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCGE_i">VCGE (immediate #0)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCEQ_i_T1_Q" iformfile="vceq_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">x010</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCEQ_i">VCEQ (immediate #0)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCLE_i_T1_Q" iformfile="vcle_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">x011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCLE_i">VCLE (immediate #0)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCLT_i_T1_Q" iformfile="vclt_i.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">x100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCLT_i">VCLT (immediate #0)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VABS_T1_Q" iformfile="vabs.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">x110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VABS">VABS</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VNEG_T1_Q" iformfile="vneg.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">x111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VNEG">VNEG</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="SHA1H_T1" arch_version="FEAT_SHA1" iformfile="sha1h.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="SHA1H">SHA1H</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_bfs_T1" arch_version="FEAT_AA32BF16" iformfile="vcvt_bfs.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield">01</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VCVT_bfs">VCVT (from single-precision to BFloat16, Advanced SIMD)</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VTRN_T1_Q" iformfile="vtrn.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VTRN">VTRN</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VUZP_T1_Q" iformfile="vuzp.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VUZP">VUZP</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VZIP_T1_Q" iformfile="vzip.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VZIP">VZIP</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VMOVN_T1" iformfile="vmovn.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMOVN">VMOVN</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VQMOVUN_T1" iformfile="vqmovn.xml" label="VQMOVUN" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VQMOVN">VQMOVN, VQMOVUN</td>
          <td class="enctags">T1, Unsigned result</td>
        </tr>
        <tr class="instructiontable" encname="VQMOVN_T1" iformfile="vqmovn.xml" label="VQMOVN" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VQMOVN">VQMOVN, VQMOVUN</td>
          <td class="enctags">T1, Signed result</td>
        </tr>
        <tr class="instructiontable" encname="VSHLL_T2" iformfile="vshll.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VSHLL">VSHLL</td>
          <td class="enctags">T2</td>
        </tr>
        <tr class="instructiontable" encname="SHA1SU1_T1" arch_version="FEAT_SHA1" iformfile="sha1su1.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="SHA1SU1">SHA1SU1</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="SHA256SU0_T1" arch_version="FEAT_SHA256" iformfile="sha256su0.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="SHA256SU0">SHA256SU0</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VRINTN_asimd_T1_Q" iformfile="vrintn_asimd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VRINTN_asimd">VRINTN (Advanced SIMD)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VRINTX_asimd_T1_Q" iformfile="vrintx_asimd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VRINTX_asimd">VRINTX (Advanced SIMD)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VRINTA_asimd_T1_Q" iformfile="vrinta_asimd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VRINTA_asimd">VRINTA (Advanced SIMD)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VRINTZ_asimd_T1_Q" iformfile="vrintz_asimd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VRINTZ_asimd">VRINTZ (Advanced SIMD)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_78_simd_2r_misc" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_hs_T1" iformfile="vcvt_hs.xml" label="single-precision to half-precision" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVT_hs">VCVT (between half-precision and single-precision, Advanced SIMD)</td>
          <td class="enctags">T1, Single-precision to half-precision</td>
        </tr>
        <tr class="instructiontable" encname="VRINTM_asimd_T1_Q" iformfile="vrintm_asimd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VRINTM_asimd">VRINTM (Advanced SIMD)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_sh_T1" iformfile="vcvt_hs.xml" label="half-precision to single-precision" oneofthismnem="2" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VCVT_hs">VCVT (between half-precision and single-precision, Advanced SIMD)</td>
          <td class="enctags">T1, Half-precision to single-precision</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_83_simd_2r_misc" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VRINTP_asimd_T1_Q" iformfile="vrintp_asimd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VRINTP_asimd">VRINTP (Advanced SIMD)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCVTA_asimd_T1_Q" iformfile="vcvta_asimd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">000x</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTA_asimd">VCVTA (Advanced SIMD)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCVTN_asimd_T1_Q" iformfile="vcvtn_asimd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">001x</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTN_asimd">VCVTN (Advanced SIMD)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCVTP_asimd_T1_Q" iformfile="vcvtp_asimd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">010x</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTP_asimd">VCVTP (Advanced SIMD)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VCVTM_asimd_T1_Q" iformfile="vcvtm_asimd.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">011x</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVTM_asimd">VCVTM (Advanced SIMD)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VRECPE_T1_Q" iformfile="vrecpe.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">10x0</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VRECPE">VRECPE</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VRSQRTE_T1_Q" iformfile="vrsqrte.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">10x1</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VRSQRTE">VRSQRTE</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_79_simd_2r_misc" undef="1" oneofthismnem="5" first="t" last="t">
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="2" class="bitfield">10</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_is_T1_Q" iformfile="vcvt_is.xml" first="t" last="t">
          <td bitwidth="2" class="bitfield"></td>
          <td bitwidth="2" class="bitfield">11</td>
          <td bitwidth="4" class="bitfield">11xx</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVT_is">VCVT (between floating-point and integer, Advanced SIMD)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="simd_ext" title="Advanced SIMD vector extract">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="2" settings="2">
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="19" width="4" name="Vn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="imm4" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" name="N" usename="1">
        <c></c>
      </box>
      <box hibit="6" name="Q" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>0</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="simd_ext" cols="2">
      <col colno="1" printwidth="22*" />
      <col colno="2" printwidth="25*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th rowspan="1" class="iformname">Instruction page</th>
          <th rowspan="1" class="enctags">Encoding</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VEXT_T1_Q" iformfile="vext.xml" first="t" last="t">
          <td class="iformname" iformid="VEXT">VEXT (byte elements)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="t_simd_12reg">Advanced SIMD shifts and immediate generation</funcgroupheader>
  <iclass_sect id="simd_1r_imm" title="Advanced SIMD one register and modified immediate">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="3" settings="3">
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="28" name="i" usename="1">
        <c></c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="3" settings="3">
        <c>0</c>
        <c>0</c>
        <c>0</c>
      </box>
      <box hibit="18" width="3" name="imm3" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="cmode" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" settings="1">
        <c>0</c>
      </box>
      <box hibit="6" name="Q" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="op" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="imm4" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="simd_1r_imm" cols="4">
      <col colno="1" printwidth="7*" />
      <col colno="2" printwidth="4*" />
      <col colno="3" printwidth="18*" />
      <col colno="4" printwidth="25*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">cmode</th>
          <th class="bitfields">op</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encoding="t1" iformfile="vmov_i.xml" label="T1" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">0xx0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMOV_i">VMOV (immediate)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="t1" iformfile="vmvn_i.xml" label="T1" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">0xx0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMVN_i">VMVN (immediate)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="t1" iformfile="vorr_i.xml" label="T1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0xx1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VORR_i">VORR (immediate)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="t1" iformfile="vbic_i.xml" label="T1" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">0xx1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VBIC_i">VBIC (immediate)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="t3" iformfile="vmov_i.xml" label="T3" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">10x0</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMOV_i">VMOV (immediate)</td>
          <td class="enctags">T3, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="t2" iformfile="vmvn_i.xml" label="T2" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">10x0</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMVN_i">VMVN (immediate)</td>
          <td class="enctags">T2, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="t2" iformfile="vorr_i.xml" label="T2" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">10x1</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VORR_i">VORR (immediate)</td>
          <td class="enctags">T2, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="t2" iformfile="vbic_i.xml" label="T2" oneofthismnem="2" first="t" last="t">
          <td bitwidth="4" class="bitfield">10x1</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VBIC_i">VBIC (immediate)</td>
          <td class="enctags">T2, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="t4" iformfile="vmov_i.xml" label="T4" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">11xx</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMOV_i">VMOV (immediate)</td>
          <td class="enctags">T4, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="t3" iformfile="vmvn_i.xml" label="T3" oneofthismnem="3" first="t" last="t">
          <td bitwidth="4" class="bitfield">110x</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMVN_i">VMVN (immediate)</td>
          <td class="enctags">T3, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encoding="t5" iformfile="vmov_i.xml" label="T5" oneofthismnem="4" first="t" last="t">
          <td bitwidth="4" class="bitfield">1110</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VMOV_i">VMOV (immediate)</td>
          <td class="enctags">T5, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_33_simd_1r_imm" undef="1" first="t" last="t">
          <td bitwidth="4" class="bitfield">1111</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <iclass_sect id="simd_2r_shift" title="Advanced SIMD two registers and shift amount">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="3" settings="3">
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="28" name="U" usename="1">
        <c></c>
      </box>
      <box hibit="27" width="5" settings="5">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="22" name="D" usename="1">
        <c></c>
      </box>
      <box hibit="21" width="3" name="imm3H" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="18" width="3" name="imm3L" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="15" width="4" name="Vd" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="opc" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" name="L" usename="1">
        <c></c>
      </box>
      <box hibit="6" name="Q" usename="1">
        <c></c>
      </box>
      <box hibit="5" name="M" usename="1">
        <c></c>
      </box>
      <box hibit="4" settings="1">
        <c>1</c>
      </box>
      <box hibit="3" width="4" name="Vm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <decode_constraints>
      <decode_constraint name="imm3H:imm3L:Vd:opc:L" op="!=" val="000xxxxxxxxxxx0" />
    </decode_constraints>
    <instructiontable iclass="simd_2r_shift" cols="7">
      <col colno="1" printwidth="3*" />
      <col colno="2" printwidth="9*" />
      <col colno="3" printwidth="7*" />
      <col colno="4" printwidth="6*" />
      <col colno="5" printwidth="3*" />
      <col colno="6" printwidth="62*" />
      <col colno="7" printwidth="42*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">U</th>
          <th class="bitfields">imm3H:L</th>
          <th class="bitfields">imm3L</th>
          <th class="bitfields">opc</th>
          <th class="bitfields">Q</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="VSHR_T1_Q" iformfile="vshr.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0000</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VSHR">VSHR</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSRA_T1_Q" iformfile="vsra.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VSRA">VSRA</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VMOVL_T1" iformfile="vmovl.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VMOVL">VMOVL</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VRSHR_T1_Q" iformfile="vrshr.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0010</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VRSHR">VRSHR</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VRSRA_T1_Q" iformfile="vrsra.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0011</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VRSRA">VRSRA</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQSHL_i_T1_Q" iformfile="vqshl_i.xml" label="VQSHL" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VQSHL_i">VQSHL, VQSHLU (immediate)</td>
          <td class="enctags">T1, 128-bit SIMD vector, signed result</td>
        </tr>
        <tr class="instructiontable" encname="VQSHRN_T1" iformfile="vqshrn.xml" label="VQSHRN" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1001</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VQSHRN">VQSHRN, VQSHRUN</td>
          <td class="enctags">T1, Signed result</td>
        </tr>
        <tr class="instructiontable" encname="VQRSHRN_T1" iformfile="vqrshrn.xml" label="VQRSHRN" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1001</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VQRSHRN">VQRSHRN, VQRSHRUN</td>
          <td class="enctags">T1, Signed result</td>
        </tr>
        <tr class="instructiontable" encname="VSHLL_T1" iformfile="vshll.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VSHLL">VSHLL</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VCVT_xs_T1_Q" iformfile="vcvt_xs.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield"></td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">11xx</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VCVT_xs">VCVT (between floating-point and fixed-point, Advanced SIMD)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSHL_i_T1_Q" iformfile="vshl_i.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VSHL_i">VSHL (immediate)</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSHRN_T1" iformfile="vshrn.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VSHRN">VSHRN</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VRSHRN_T1" iformfile="vrshrn.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">0</td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VRSHRN">VRSHRN</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="VSRI_T1_Q" iformfile="vsri.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0100</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VSRI">VSRI</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VSLI_T1_Q" iformfile="vsli.xml" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0101</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VSLI">VSLI</td>
          <td class="enctags">T1, 128-bit SIMD vector</td>
        </tr>
        <tr class="instructiontable" encname="VQSHLU_i_T1_Q" iformfile="vqshl_i.xml" label="VQSHLU" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td bitwidth="1" class="bitfield"></td>
          <td class="iformname" iformid="VQSHL_i">VQSHL, VQSHLU (immediate)</td>
          <td class="enctags">T1, 128-bit SIMD vector, unsigned result</td>
        </tr>
        <tr class="instructiontable" encname="VQSHRUN_T1" iformfile="vqshrn.xml" label="VQSHRUN" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">0</td>
          <td class="iformname" iformid="VQSHRN">VQSHRN, VQSHRUN</td>
          <td class="enctags">T1, Unsigned result</td>
        </tr>
        <tr class="instructiontable" encname="VQRSHRUN_T1" iformfile="vqrshrn.xml" label="VQRSHRUN" oneofthismnem="2" first="t" last="t">
          <td bitwidth="1" class="bitfield">1</td>
          <td bitwidth="15" class="bitfield">!= 0000</td>
          <td bitwidth="3" class="bitfield"></td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td bitwidth="1" class="bitfield">1</td>
          <td class="iformname" iformid="VQRSHRN">VQRSHRN, VQRSHRUN</td>
          <td class="enctags">T1, Unsigned result</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <funcgroupheader id="lmul">Long multiply, long multiply accumulate, and divide</funcgroupheader>
  <iclass_sect id="lmul_div" title="Long multiply and divide">
    <regdiagram form="16x2" psname="">
      <box hibit="31" width="9" settings="9">
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
        <c>0</c>
        <c>1</c>
        <c>1</c>
        <c>1</c>
      </box>
      <box hibit="22" width="3" name="op1" usename="1">
        <c colspan="3"></c>
      </box>
      <box hibit="19" width="4" name="Rn" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="15" width="4" name="RdLo" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="11" width="4" name="RdHi" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="7" width="4" name="op2" usename="1">
        <c colspan="4"></c>
      </box>
      <box hibit="3" width="4" name="Rm" usename="1">
        <c colspan="4"></c>
      </box>
    </regdiagram>
    <instructiontable iclass="lmul_div" cols="4">
      <col colno="1" printwidth="5*" />
      <col colno="2" printwidth="9*" />
      <col colno="3" printwidth="36*" />
      <col colno="4" printwidth="13*" />
      <thead class="instructiontable">
        <tr id="heading1">
          <th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
          <th rowspan="2" class="iformname">Instruction page</th>
          <th rowspan="2" class="enctags">Encoding</th>
        </tr>
        <tr id="heading2">
          <th class="bitfields">op1</th>
          <th class="bitfields">op2</th>
        </tr>
      </thead>
      <tbody>
        <tr class="instructiontable" encname="UNALLOCATED_12_lmul_div" undef="1" oneofthismnem="17" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="4" class="bitfield">!= 0000</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SMULL_T1" iformfile="smull.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">000</td>
          <td bitwidth="4" class="bitfield">0000</td>
          <td class="iformname" iformid="SMULL">SMULL, SMULLS</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_13_lmul_div" undef="1" oneofthismnem="17" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SDIV_T1" iformfile="sdiv.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">001</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="SDIV">SDIV</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_16_lmul_div" undef="1" oneofthismnem="17" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="4" class="bitfield">!= 0000</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UMULL_T1" iformfile="umull.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">010</td>
          <td bitwidth="4" class="bitfield">0000</td>
          <td class="iformname" iformid="UMULL">UMULL, UMULLS</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_17_lmul_div" undef="1" oneofthismnem="17" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="4" class="bitfield">!= 1111</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UDIV_T1" iformfile="udiv.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">011</td>
          <td bitwidth="4" class="bitfield">1111</td>
          <td class="iformname" iformid="UDIV">UDIV</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="SMLAL_T1" iformfile="smlal.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="4" class="bitfield">0000</td>
          <td class="iformname" iformid="SMLAL">SMLAL, SMLALS</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_20_lmul_div" undef="1" oneofthismnem="17" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_21_lmul_div" undef="1" oneofthismnem="17" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="4" class="bitfield">001x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_22_lmul_div" undef="1" oneofthismnem="17" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="4" class="bitfield">01xx</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SMLALBB_T1" iformfile="smlalbb.xml" label="SMLALBB" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="4" class="bitfield">1000</td>
          <td class="iformname" iformid="SMLALBB">SMLALBB, SMLALBT, SMLALTB, SMLALTT</td>
          <td class="enctags">T1, SMLALBB</td>
        </tr>
        <tr class="instructiontable" encname="SMLALBT_T1" iformfile="smlalbb.xml" label="SMLALBT" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="4" class="bitfield">1001</td>
          <td class="iformname" iformid="SMLALBB">SMLALBB, SMLALBT, SMLALTB, SMLALTT</td>
          <td class="enctags">T1, SMLALBT</td>
        </tr>
        <tr class="instructiontable" encname="SMLALTB_T1" iformfile="smlalbb.xml" label="SMLALTB" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="4" class="bitfield">1010</td>
          <td class="iformname" iformid="SMLALBB">SMLALBB, SMLALBT, SMLALTB, SMLALTT</td>
          <td class="enctags">T1, SMLALTB</td>
        </tr>
        <tr class="instructiontable" encname="SMLALTT_T1" iformfile="smlalbb.xml" label="SMLALTT" oneofthismnem="4" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="4" class="bitfield">1011</td>
          <td class="iformname" iformid="SMLALBB">SMLALBB, SMLALBT, SMLALTB, SMLALTT</td>
          <td class="enctags">T1, SMLALTT</td>
        </tr>
        <tr class="instructiontable" encname="SMLALD_T1" iformfile="smlald.xml" label="SMLALD" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td class="iformname" iformid="SMLALD">SMLALD, SMLALDX</td>
          <td class="enctags">T1, SMLALD</td>
        </tr>
        <tr class="instructiontable" encname="SMLALDX_T1" iformfile="smlald.xml" label="SMLALDX" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="SMLALD">SMLALD, SMLALDX</td>
          <td class="enctags">T1, SMLALDX</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_29_lmul_div" undef="1" oneofthismnem="17" first="t" last="t">
          <td bitwidth="3" class="bitfield">100</td>
          <td bitwidth="4" class="bitfield">111x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_30_lmul_div" undef="1" oneofthismnem="17" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="4" class="bitfield">0xxx</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_31_lmul_div" undef="1" oneofthismnem="17" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="4" class="bitfield">10xx</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="SMLSLD_T1" iformfile="smlsld.xml" label="SMLSLD" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="4" class="bitfield">1100</td>
          <td class="iformname" iformid="SMLSLD">SMLSLD, SMLSLDX</td>
          <td class="enctags">T1, SMLSLD</td>
        </tr>
        <tr class="instructiontable" encname="SMLSLDX_T1" iformfile="smlsld.xml" label="SMLSLDX" oneofthismnem="2" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="4" class="bitfield">1101</td>
          <td class="iformname" iformid="SMLSLD">SMLSLD, SMLSLDX</td>
          <td class="enctags">T1, SMLSLDX</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_34_lmul_div" undef="1" oneofthismnem="17" first="t" last="t">
          <td bitwidth="3" class="bitfield">101</td>
          <td bitwidth="4" class="bitfield">111x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UMLAL_T1" iformfile="umlal.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="4" class="bitfield">0000</td>
          <td class="iformname" iformid="UMLAL">UMLAL, UMLALS</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_36_lmul_div" undef="1" oneofthismnem="17" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="4" class="bitfield">0001</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_37_lmul_div" undef="1" oneofthismnem="17" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="4" class="bitfield">001x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_38_lmul_div" undef="1" oneofthismnem="17" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="4" class="bitfield">010x</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UMAAL_T1" iformfile="umaal.xml" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="4" class="bitfield">0110</td>
          <td class="iformname" iformid="UMAAL">UMAAL</td>
          <td class="enctags">T1</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_40_lmul_div" undef="1" oneofthismnem="17" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="4" class="bitfield">0111</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_41_lmul_div" undef="1" oneofthismnem="17" first="t" last="t">
          <td bitwidth="3" class="bitfield">110</td>
          <td bitwidth="4" class="bitfield">1xxx</td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
        <tr class="instructiontable" encname="UNALLOCATED_42_lmul_div" undef="1" oneofthismnem="17" first="t" last="t">
          <td bitwidth="3" class="bitfield">111</td>
          <td bitwidth="4" class="bitfield"></td>
          <td class="iformname">UNALLOCATED</td>
        </tr>
      </tbody>
    </instructiontable>
  </iclass_sect>
  <mappings>
    <mapping from="fpdp" to_isa="A32" to="fpdp" />
    <mapping from="simd_1r_imm" to_isa="A32" to="simd1reg_imm" />
    <mapping from="asimldstss" to_isa="A32" to="ldstv_ssone" />
    <mapping from="simddp" to_isa="A32" to="advsimddp" />
    <mapping from="sysldst_mov64" to_isa="A32" to="sysldst_mov64" />
    <mapping from="fp_2r" to_isa="A32" to="fpdp2reg" />
    <mapping from="simd_ext" to_isa="A32" to="simd3reg_ext" />
    <mapping from="simd_2r_sc" to_isa="A32" to="simd2reg_scalar" />
    <mapping from="simd_3diff" to_isa="A32" to="simd3reg_diff" />
    <mapping from="simdfp_ldst" to_isa="A32" to="ldstsimdfp" />
    <mapping from="asimldall" to_isa="A32" to="ldv_ssall" />
    <mapping from="simd_3sameext" to_isa="A32" to="simd3reg_sameext" />
    <mapping from="simdldst_mov64" to_isa="A32" to="simdldst_mov64" />
    <mapping from="simdfp_mov64" to_isa="A32" to="movsimdfpgp64" />
    <mapping from="simd_3same" to_isa="A32" to="simd3reg_same" />
    <mapping from="asimldstms" to_isa="A32" to="ldstv_ms" />
    <mapping from="simd_2r_scext" to_isa="A32" to="simd2reg_scalarext" />
    <mapping from="fp_msr" to_isa="A32" to="movfpsr" />
    <mapping from="sysreg_mov32" to_isa="A32" to="sysreg_mov32" />
    <mapping from="fp_mov32" to_isa="A32" to="movfpgp32" />
    <mapping from="fpsimd_mov32" to_isa="A32" to="fpsimd_mov32" />
    <mapping from="simd_dup_sc" to_isa="A32" to="simd2reg_dup" />
    <mapping from="fp_movi" to_isa="A32" to="fpimm" />
    <mapping from="simd_2r_shift" to_isa="A32" to="simd2reg_shift" />
    <mapping from="fp_minmax" to_isa="A32" to="fpminmaxnm" />
    <mapping from="fp_csel" to_isa="A32" to="fpcsel" />
    <mapping from="fp_toint" to_isa="A32" to="fpcvtrnd" />
    <mapping from="simd_2r_misc" to_isa="A32" to="simd2reg_misc" />
    <mapping from="simd_dup_el" to_isa="A32" to="movsimdgp" />
    <mapping from="vldst" to_isa="A32" to="advsimdls" />
    <mapping from="simd_tbl" to_isa="A32" to="simd3reg_tbl" />
    <mapping from="fp_3r" to_isa="A32" to="fpdp3reg" />
  </mappings>
</encodingindex>
</file>
  </sect1>
  <sect1 id="iformpages">
    <title>Instruction pages in alphabetical order</title>
    <para>This section lists every instruction.</para>
<file type="instructionsection" file="adc_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ADC_i" title="ADC, ADCS (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>ADC, ADCS (immediate)</heading>
  <desc>
    <brief>
      <para>Add with Carry (immediate)</para>
    </brief>
    <authored>
      <para>Add with Carry (immediate) adds an immediate value and the Carry flag value to a register value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the ADCS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The ADC variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The ADCS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/ADC_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="ADC_i_A1" oneofinclass="2" oneof="4" label="ADC" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADC" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>ADC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="ADCS_i_A1" oneofinclass="2" oneof="4" label="ADCS" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADCS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>ADCS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADC_i/A1_A.txt" mylink="aarch32.instrs.ADC_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = (S == '1');  imm32 = <a link="impl-aarch32.A32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) A32ExpandImm(bits(12) imm12)">A32ExpandImm</a>(imm12);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/ADC_i/T1_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="ADC_i_T1" oneofinclass="2" oneof="4" label="ADC" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADC" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>ADC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="ADCS_i_T1" oneofinclass="2" oneof="4" label="ADCS" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADCS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>ADCS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADC_i/T1_A.txt" mylink="aarch32.instrs.ADC_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = (S == '1');  imm32 = <a link="impl-aarch32.T32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) T32ExpandImm(bits(12) imm12)">T32ExpandImm</a>(i:imm3:imm8);</line>
<line>if d == 15 || n == 15 then UNPREDICTABLE;  // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ADC_i_A1, ADC_i_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADC_i_A1, ADC_i_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADC_i_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the ADC variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the ADCS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADC_i_T1" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADC_i_A1" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADC_i_T1" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADC_i_A1" symboldefcount="1">
      <symbol link="sa_const_1">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: an immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADC_i_T1" symboldefcount="2">
      <symbol link="sa_const">&lt;const&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: an immediate value. See <xref linkend="BABGHAGA">Modified immediate constants in T32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/ADC_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], imm32, PSTATE.C);</line>
<line>    if d == 15 then          // Can only occur for A32 encoding</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="adc_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ADC_r" title="ADC, ADCS (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>ADC, ADCS (register)</heading>
  <desc>
    <brief>
      <para>Add with Carry (register)</para>
    </brief>
    <authored>
      <para>Add with Carry (register) adds a register value, the Carry flag value, and an optionally-shifted register value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the ADCS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The ADC variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The ADCS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>In T32 assembly:</para>
      <list type="unordered">
        <listitem><content>Outside an IT block, if <syntax>ADCS &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rd&gt;</syntax> has <syntax>&lt;Rd&gt;</syntax> and <syntax>&lt;Rn&gt;</syntax> both in the range R0-R7, it is assembled using encoding T1 as though <syntax>ADCS &lt;Rd&gt;, &lt;Rn&gt;</syntax> had been written.</content></listitem>
        <listitem><content>Inside an IT block, if <syntax>ADC&lt;c&gt; &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rd&gt;</syntax> has <syntax>&lt;Rd&gt;</syntax> and <syntax>&lt;Rn&gt;</syntax> both in the range R0-R7, it is assembled using encoding T1 as though <syntax>ADC&lt;c&gt; &lt;Rd&gt;, &lt;Rn&gt;</syntax> had been written.</content></listitem>
      </list>
      <para>To prevent either of these happening, use the .W qualifier.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/ADC_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ADC_r_A1_RRX" oneofinclass="4" oneof="9" label="ADC, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADC" />
          <docvar key="mnemonic-shift-type" value="ADC-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ADC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="ADC_r_A1" oneofinclass="4" oneof="9" label="ADC, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADC" />
          <docvar key="mnemonic-shift-type" value="ADC-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>ADC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="ADCS_r_A1_RRX" oneofinclass="4" oneof="9" label="ADCS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADCS" />
          <docvar key="mnemonic-shift-type" value="ADCS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ADCS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="ADCS_r_A1" oneofinclass="4" oneof="9" label="ADCS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADCS" />
          <docvar key="mnemonic-shift-type" value="ADCS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>ADCS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADC_r/A1_A.txt" mylink="aarch32.instrs.ADC_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ADC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/ADC_r/T1_A.txt">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="4" name="op" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rdn" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="ADC_r_T1" oneofinclass="1" oneof="9" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADC" />
        </docvars>
        <asmtemplate comment="Inside IT block"><text>ADC</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate comment="Outside IT block"><text>ADCS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADC_r/T1_A.txt" mylink="aarch32.instrs.ADC_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdn);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>();</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/ADC_r/T2_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ADC_r_T2_RRX" oneofinclass="4" oneof="9" label="ADC, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADC" />
          <docvar key="mnemonic-shift-type" value="ADC-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ADC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="ADC_r_T2" oneofinclass="4" oneof="9" label="ADC, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADC" />
          <docvar key="mnemonic-shift-type" value="ADC-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Inside IT block, and &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>ADC</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>ADC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="ADCS_r_T2_RRX" oneofinclass="4" oneof="9" label="ADCS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADCS" />
          <docvar key="mnemonic-shift-type" value="ADCS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ADCS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="ADCS_r_T2" oneofinclass="4" oneof="9" label="ADCS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADCS" />
          <docvar key="mnemonic-shift-type" value="ADCS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Outside IT block, and &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>ADCS.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>ADCS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADC_r/T2_A.txt" mylink="aarch32.instrs.ADC_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm3:imm2);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ADC_r_A1, ADC_r_T1, ADC_r_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADC_r_A1, ADC_r_T1, ADC_r_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADC_r_T1" symboldefcount="1">
      <symbol link="sa_rdn">&lt;Rdn&gt;</symbol>
      <account encodedin="Rdn">
        <intro>
          <para>Is the first general-purpose source register and the destination register, encoded in the "Rdn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADC_r_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the ADC variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the ADCS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADC_r_T2" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADC_r_A1" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADC_r_T2" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADC_r_A1" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="ADC-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADC_r_T1, ADC_r_T2" symboldefcount="2">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADC_r_A1, ADC_r_T2" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="ADC_r_A1" symboldefcount="1">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADC_r_T2" symboldefcount="2">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm3:imm2" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/ADC_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], shifted, PSTATE.C);</line>
<line>    if d == 15 then          // Can only occur for A32 encoding</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="adc_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ADC_rr" title="ADC, ADCS (register-shifted register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
  </docvars>
  <heading>ADC, ADCS (register-shifted register)</heading>
  <desc>
    <brief>
      <para>Add with Carry (register-shifted register)</para>
    </brief>
    <authored>
      <para>Add with Carry (register-shifted register) adds a register value, the Carry flag value, and a register-shifted register value.  It writes the result to the destination register, and can optionally update the condition flags based on the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/ADC_rr/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ADCS_rr_A1" oneofinclass="2" oneof="2" label="Flag setting" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADCS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>ADCS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="Third general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <encoding name="ADC_rr_A1" oneofinclass="2" oneof="2" label="Not flag setting" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADC" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>ADC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="Third general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADC_rr/A1_A.txt" mylink="aarch32.instrs.ADC_rr.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);</line>
<line>setflags = (S == '1');  shift_t = <a link="impl-aarch32.DecodeRegShift.1" file="shared_pseudocode.xml" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</a>(stype);</line>
<line>if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ADC_rr_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADC_rr_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADC_rr_A1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADC_rr_A1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADC_rr_A1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADC_rr_A1" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="ADC_rr_A1" symboldefcount="1">
      <symbol link="sa_rs">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the third general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/ADC_rr/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shift_n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[s]&lt;7:0&gt;);</line>
<line>    shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], shifted, PSTATE.C);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>    if setflags then</line>
<line>        PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="add_adr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ADD_ADR" title="ADD (immediate, to PC) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="ADD" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="ADR" />
  </docvars>
  <heading>ADD (immediate, to PC)</heading>
  <desc>
    <brief>Add to PC</brief>
    <longer> adds an immediate value to the Align(PC, 4) value to form a PC-relative address, and writes the result to the destination register.  Arm recommends that, where possible, software avoids using this alias</longer>
  </desc>
  <aliasto refiform="adr.xml" iformid="ADR">ADR</aliasto>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="ADR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_ADR_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="alias_mnemonic" value="ADD" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADR" />
        </docvars>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, PC, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="adr.xml#ADR_A1">ADR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_label_2" hover="The label of an instruction or literal data item whose address is to be loaded into {syntax{&lt;Rd&gt;}}">&lt;label&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ADR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="">
        <box hibit="31" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="27" name="SP" settings="1">
          <c>0</c>
        </box>
        <box hibit="26" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="23" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_ADR_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="alias_mnemonic" value="ADD" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADR" />
        </docvars>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, PC, #</text><a link="sa_imm8" hover="Unsigned immediate, multiple of 4 [0-1020] (field &quot;imm8&quot;)">&lt;imm8&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="adr.xml#ADR_T1">ADR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_label" hover="The label of an instruction or literal data item whose address is to be loaded into {syntax{&lt;Rd&gt;}}">&lt;label&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T3" oneof="3" id="iclass_t3" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ADR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_ADR_T3" oneofinclass="1" oneof="3" label="T3">
        <docvars>
          <docvar key="alias_mnemonic" value="ADD" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADR" />
        </docvars>
        <asmtemplate comment="&lt;Rd&gt;, &lt;imm12&gt; can be represented in T1"><text>ADDW</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, PC, #</text><a link="sa_imm12" hover="12-bit unsigned immediate [0-4095] (field &quot;i:imm3:imm8&quot;)">&lt;imm12&gt;</a></asmtemplate>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, PC, #</text><a link="sa_imm12" hover="12-bit unsigned immediate [0-4095] (field &quot;i:imm3:imm8&quot;)">&lt;imm12&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="adr.xml#ADR_T3">ADR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_label_1" hover="The label of an instruction or literal data item whose address is to be loaded into {syntax{&lt;Rd&gt;}}">&lt;label&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ADD_ADR_A1, ADD_ADR_T1, ADD_ADR_T3" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_ADR_A1, ADD_ADR_T1, ADD_ADR_T3" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_ADR_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If the PC is used, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_ADR_T1, ADD_ADR_T3" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>For encoding T1 and T3: is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_ADR_A1" symboldefcount="1">
      <symbol link="sa_label_2">&lt;label&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: the label of an instruction or literal data item whose address is to be loaded into <syntax>&lt;Rd&gt;</syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the <instruction>ADR</instruction> instruction to this label.</para>
          <para>If the offset is zero or positive, encoding A1 is used, with <field>imm32</field> equal to the offset.</para>
          <para>If the offset is negative, encoding A2 is used, with <field>imm32</field> equal to the size of the offset. That is, the use of encoding A2 indicates that the required offset is minus the value of <field>imm32</field>.</para>
          <para>Permitted values of the size of the offset are any of the constants described in <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_ADR_T1" symboldefcount="2">
      <symbol link="sa_label">&lt;label&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: the label of an instruction or literal data item whose address is to be loaded into <syntax>&lt;Rd&gt;</syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the <instruction>ADR</instruction> instruction to this label. Permitted values of the size of the offset are multiples of 4 in the range 0 to 1020.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_ADR_T3" symboldefcount="3">
      <symbol link="sa_label_1">&lt;label&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3: the label of an instruction or literal data item whose address is to be loaded into <syntax>&lt;Rd&gt;</syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the <instruction>ADR</instruction> instruction to this label.</para>
          <para>If the offset is zero or positive, encoding T3 is used, with <field>imm32</field> equal to the offset.</para>
          <para>If the offset is negative, encoding T2 is used, with <field>imm32</field> equal to the size of the offset. That is, the use of encoding T2 indicates that the required offset is minus the value of <field>imm32</field>.</para>
          <para>Permitted values of the size of the offset are 0-4095.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_ADR_T1" symboldefcount="1">
      <symbol link="sa_imm8">&lt;imm8&gt;</symbol>
      <account encodedin="imm8">
        <intro>
          <para>Is an unsigned immediate, a multiple of 4, in the range 0 to 1020, encoded in the "imm8" field as &lt;imm8&gt;/4.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_ADR_T3" symboldefcount="1">
      <symbol link="sa_imm12">&lt;imm12&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <intro>
          <para>Is a 12-bit unsigned immediate, in the range 0 to 4095, encoded in the "i:imm3:imm8" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_ADR_A1" symboldefcount="1">
      <symbol link="sa_const">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <intro>
          <para>An immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="add_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ADD_i" title="ADD, ADDS (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>ADD, ADDS (immediate)</heading>
  <desc>
    <brief>
      <para>Add (immediate)</para>
    </brief>
    <authored>
      <para>Add (immediate) adds an immediate value to a register value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the ADDS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. If the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The ADD variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The ADDS variant of the instruction performs an exception return without the use of the stack. Arm deprecates use of this instruction. However, in this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>When multiple encodings of the same length are available for an instruction, encoding T3 is preferred to encoding T4 (if encoding T4 is required, use the <instruction>ADDW</instruction> syntax). Encoding T1 is preferred to encoding T2 if <syntax>&lt;Rd&gt;</syntax> is specified and encoding T2 is preferred to encoding T1 if <syntax>&lt;Rd&gt;</syntax> is omitted.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="5">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt>, </txt>
      <a href="#iclass_t3">T3</a>
      <txt> and </txt>
      <a href="#iclass_t4">T4</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="5" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/ADD_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_i_A1" oneofinclass="2" oneof="7" label="ADD" bitdiffs="S == 0 &amp;&amp; Rn != 11x1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADD" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_2" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="ADDS_i_A1" oneofinclass="2" oneof="7" label="ADDS" bitdiffs="S == 1 &amp;&amp; Rn != 1101">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADDS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn">
          <c>N</c>
          <c>N</c>
          <c>Z</c>
          <c>N</c>
        </box>
        <asmtemplate><text>ADDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_2" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_i/A1_A.txt" mylink="aarch32.instrs.ADD_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' &amp;&amp; S == '0' then SEE "ADR";</line>
<line>if Rn == '1101' then SEE "ADD (SP plus immediate)";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = (S == '1');  imm32 = <a link="impl-aarch32.A32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) A32ExpandImm(bits(12) imm12)">A32ExpandImm</a>(imm12);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="5" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ADD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/ADD_i/T1_A.txt">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="25" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="21" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_i_T1" oneofinclass="1" oneof="7" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADD" />
        </docvars>
        <asmtemplate comment="Inside IT block"><text>ADD</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_imm3" hover="3-bit unsigned immediate [0-7] (field &quot;imm3&quot;)">&lt;imm3&gt;</a></asmtemplate>
        <asmtemplate comment="Outside IT block"><text>ADDS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_imm3" hover="3-bit unsigned immediate [0-7] (field &quot;imm3&quot;)">&lt;imm3&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_i/T1_A.txt" mylink="aarch32.instrs.ADD_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>();  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm3, 32);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="5" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ADD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/ADD_i/T2_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="28" width="2" name="op" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" width="3" name="Rdn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="23" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_i_T2" oneofinclass="1" oneof="7" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADD" />
        </docvars>
        <asmtemplate comment="Inside IT block, and &lt;Rdn&gt;, &lt;imm8&gt; can be represented in T1"><text>ADD</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdn" hover="General-purpose source and destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>, #</text><a link="sa_imm8" hover="8-bit unsigned immediate [0-255] (field &quot;imm8&quot;)">&lt;imm8&gt;</a></asmtemplate>
        <asmtemplate comment="Inside IT block, and &lt;Rdn&gt;, &lt;imm8&gt; cannot be represented in T1"><text>ADD</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdn" hover="General-purpose source and destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdn" hover="General-purpose source and destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>, #</text><a link="sa_imm8" hover="8-bit unsigned immediate [0-255] (field &quot;imm8&quot;)">&lt;imm8&gt;</a></asmtemplate>
        <asmtemplate comment="Outside IT block, and &lt;Rdn&gt;, &lt;imm8&gt; can be represented in T1"><text>ADDS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdn" hover="General-purpose source and destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>, #</text><a link="sa_imm8" hover="8-bit unsigned immediate [0-255] (field &quot;imm8&quot;)">&lt;imm8&gt;</a></asmtemplate>
        <asmtemplate comment="Outside IT block, and &lt;Rdn&gt;, &lt;imm8&gt; cannot be represented in T1"><text>ADDS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdn" hover="General-purpose source and destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdn" hover="General-purpose source and destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>, #</text><a link="sa_imm8" hover="8-bit unsigned immediate [0-255] (field &quot;imm8&quot;)">&lt;imm8&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_i/T2_A.txt" mylink="aarch32.instrs.ADD_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdn);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdn);  setflags = !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>();  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T3" oneof="5" id="iclass_t3" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/ADD_i/T3_A.txt" tworows="1">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1101">
          <c colspan="4">!= 1101</c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_i_T3" oneofinclass="2" oneof="7" label="ADD" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADD" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate comment="Inside IT block, and &lt;Rd&gt;, &lt;Rn&gt;, &lt;const&gt; can be represented in T1 or T2"><text>ADD</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="ADDS_i_T3" oneofinclass="2" oneof="7" label="ADDS" bitdiffs="S == 1 &amp;&amp; Rd != 1111">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADDS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Outside IT block, and &lt;Rd&gt;, &lt;Rn&gt;, &lt;const&gt; can be represented in T1 or T2"><text>ADDS.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
        <asmtemplate><text>ADDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_i/T3_A.txt" mylink="aarch32.instrs.ADD_i.T3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rd == '1111' &amp;&amp; S == '1' then SEE "CMN (immediate)";</line>
<line>if Rn == '1101' then SEE "ADD (SP plus immediate)";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = (S == '1');  imm32 = <a link="impl-aarch32.T32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) T32ExpandImm(bits(12) imm12)">T32ExpandImm</a>(i:imm3:imm8);</line>
<line>if (d == 15 &amp;&amp; !setflags) || n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T4" oneof="5" id="iclass_t4" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T4" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ADDW" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/ADD_i/T4_A.txt" tworows="1">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 11x1">
          <c colspan="4">!= 11x1</c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_i_T4" oneofinclass="1" oneof="7" label="T4">
        <docvars>
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADDW" />
        </docvars>
        <asmtemplate comment="&lt;imm12&gt; cannot be represented in T1, T2, or T3"><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_2" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_imm12" hover="12-bit unsigned immediate [0-4095] (field &quot;i:imm3:imm8&quot;)">&lt;imm12&gt;</a></asmtemplate>
        <asmtemplate comment="&lt;imm12&gt; can be represented in T1, T2, or T3"><text>ADDW</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_2" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_imm12" hover="12-bit unsigned immediate [0-4095] (field &quot;i:imm3:imm8&quot;)">&lt;imm12&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_i/T4_A.txt" mylink="aarch32.instrs.ADD_i.T4_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "ADR";</line>
<line>if Rn == '1101' then SEE "ADD (SP plus immediate)";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(i:imm3:imm8, 32);</line>
<line>if d == 15 then UNPREDICTABLE;   // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ADD_i_A1, ADD_i_T1, ADD_i_T2, ADD_i_T3, ADD_i_T4" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_i_A1, ADD_i_T1, ADD_i_T2, ADD_i_T3, ADD_i_T4" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_i_T2" symboldefcount="1">
      <symbol link="sa_rdn">&lt;Rdn&gt;</symbol>
      <account encodedin="Rdn">
        <intro>
          <para>Is the general-purpose source and destination register, encoded in the "Rdn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_i_T2" symboldefcount="1">
      <symbol link="sa_imm8">&lt;imm8&gt;</symbol>
      <account encodedin="imm8">
        <intro>
          <para>Is a 8-bit unsigned immediate, in the range 0 to 255, encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_i_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADD" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>. If the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the ADD variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the ADDS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;. Arm deprecates use of this instruction.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_i_T1, ADD_i_T3, ADD_i_T4" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1, T3 and T4: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_i_A1, ADD_i_T4" symboldefcount="1">
      <symbol link="sa_rn_2">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>For encoding A1 and T4: is the general-purpose source register, encoded in the "Rn" field. If the SP is used, see <xref linkend="A32T32-base.instructions.ADD_SP_i">ADD (SP plus immediate)</xref>. If the PC is used, see <xref linkend="A32T32-base.instructions.ADR">ADR</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_i_T1" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADD" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_i_T3" symboldefcount="3">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADD" />
        </docvars>
        <intro>
          <para>For encoding T3: is the general-purpose source register, encoded in the "Rn" field. If the SP is used, see <xref linkend="A32T32-base.instructions.ADD_SP_i">ADD (SP plus immediate)</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_i_T1" symboldefcount="1">
      <symbol link="sa_imm3">&lt;imm3&gt;</symbol>
      <account encodedin="imm3">
        <intro>
          <para>Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "imm3" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_i_T4" symboldefcount="1">
      <symbol link="sa_imm12">&lt;imm12&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <intro>
          <para>Is a 12-bit unsigned immediate, in the range 0 to 4095, encoded in the "i:imm3:imm8" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_i_A1" symboldefcount="1">
      <symbol link="sa_const_1">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: an immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_i_T3" symboldefcount="2">
      <symbol link="sa_const">&lt;const&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3: an immediate value. See <xref linkend="BABGHAGA">Modified immediate constants in T32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/ADD_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then</line>
<line>    if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>        EncodingSpecificOperations();</line>
<line>        (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], imm32, '0');</line>
<line>        if d == 15 then          // Can only occur for A32 encoding</line>
<line>            if setflags then</line>
<line>                <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>            else</line>
<line>                <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>            if setflags then</line>
<line>                PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
<line>else</line>
<line>    if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>        EncodingSpecificOperations();</line>
<line>        (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], imm32, '0');</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="add_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ADD_r" title="ADD, ADDS (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>ADD, ADDS (register)</heading>
  <desc>
    <brief>
      <para>Add (register)</para>
    </brief>
    <authored>
      <para>Add (register) adds a register value and an optionally-shifted register value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the ADDS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. If the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The ADD variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The ADDS variant of the instruction performs an exception return without the use of the stack. Arm deprecates use of this instruction. However, in this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>Inside an IT block, if <syntax>ADD&lt;c&gt; &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rd&gt;</syntax> cannot be assembled using encoding T1, it is assembled using encoding T2 as though <syntax>ADD&lt;c&gt; &lt;Rd&gt;, &lt;Rn&gt;</syntax> had been written. To prevent this happening, use the <syntax>.W</syntax> qualifier.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/ADD_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1101">
          <c colspan="4">!= 1101</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_r_A1_RRX" oneofinclass="4" oneof="10" label="ADD, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADD" />
          <docvar key="mnemonic-shift-type" value="ADD-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_2" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_2" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_2" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="ADD_r_A1" oneofinclass="4" oneof="10" label="ADD, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADD" />
          <docvar key="mnemonic-shift-type" value="ADD-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_2" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_2" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_2" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="ADDS_r_A1_RRX" oneofinclass="4" oneof="10" label="ADDS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADDS" />
          <docvar key="mnemonic-shift-type" value="ADDS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ADDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_2" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_2" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_2" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="ADDS_r_A1" oneofinclass="4" oneof="10" label="ADDS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADDS" />
          <docvar key="mnemonic-shift-type" value="ADDS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>ADDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_2" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_2" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_2" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_r/A1_A.txt" mylink="aarch32.instrs.ADD_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1101' then SEE "ADD (SP plus register)";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ADD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/ADD_r/T1_A.txt">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="25" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="21" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_r_T1" oneofinclass="1" oneof="10" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADD" />
        </docvars>
        <asmtemplate comment="Inside IT block"><text>ADD</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate comment="Outside IT block"><text>ADDS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_r/T1_A.txt" mylink="aarch32.instrs.ADD_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>();</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ADD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/ADD_r/T2_A.txt" tworows="1">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="25" width="2" name="op" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" name="DN" usename="1">
          <c></c>
        </box>
        <box hibit="22" width="4" name="Rm" usename="1" settings="4" constraint="!= 1101">
          <c colspan="4">!= 1101</c>
        </box>
        <box hibit="18" width="3" name="Rdn" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_r_T2" oneofinclass="1" oneof="10" label="T2" bitdiffs="!(DN == 1 &amp;&amp; Rdn == 101)">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADD" />
        </docvars>
        <box hibit="23" width="8" name="DN:Rdn">
          <c>N</c>
          <c>N</c>
          <c>Z</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Preferred syntax, Inside IT block"><text>ADD</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdn" hover="General-purpose source and destination register (field &quot;DN:Rdn&quot;)">&lt;Rdn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdn" hover="General-purpose source and destination register (field &quot;DN:Rdn&quot;)">&lt;Rdn&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdn" hover="General-purpose source and destination register (field &quot;DN:Rdn&quot;)">&lt;Rdn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_r/T2_A.txt" mylink="aarch32.instrs.ADD_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (DN:Rdn) == '1101' || Rm == '1101' then SEE "ADD (SP plus register)";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(DN:Rdn);  n = d;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = FALSE;  (shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
<line>if n == 15 &amp;&amp; m == 15 then UNPREDICTABLE;</line>
<line>if d == 15 &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T3" oneof="4" id="iclass_t3" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/ADD_r/T3_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1101">
          <c colspan="4">!= 1101</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_r_T3_RRX" oneofinclass="4" oneof="10" label="ADD, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADD" />
          <docvar key="mnemonic-shift-type" value="ADD-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="ADD_r_T3" oneofinclass="4" oneof="10" label="ADD, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADD" />
          <docvar key="mnemonic-shift-type" value="ADD-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Inside IT block, and &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>ADD</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate comment="&lt;Rd&gt; == &lt;Rn&gt;, and &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T2"><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="ADDS_r_T3_RRX" oneofinclass="4" oneof="10" label="ADDS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm3 == 000 &amp;&amp; Rd != 1111 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADDS" />
          <docvar key="mnemonic-shift-type" value="ADDS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="11" width="4" name="Rd">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ADDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="ADDS_r_T3" oneofinclass="4" oneof="10" label="ADDS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11) &amp;&amp; Rd != 1111">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADDS" />
          <docvar key="mnemonic-shift-type" value="ADDS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <box hibit="11" width="4" name="Rd">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Outside IT block, and &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1 or T2"><text>ADDS.W </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>ADDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_r/T3_A.txt" mylink="aarch32.instrs.ADD_r.T3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rd == '1111' &amp;&amp; S == '1' then SEE "CMN (register)";</line>
<line>if Rn == '1101' then SEE "ADD (SP plus register)";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm3:imm2);</line>
<line>if (d == 15 &amp;&amp; !setflags) || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ADD_r_A1, ADD_r_T1, ADD_r_T2, ADD_r_T3" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_r_A1, ADD_r_T1, ADD_r_T2, ADD_r_T3" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_r_T2" symboldefcount="1">
      <symbol link="sa_rdn">&lt;Rdn&gt;</symbol>
      <account encodedin="DN:Rdn">
        <intro>
          <para>Is the general-purpose source and destination register, encoded in the "DN:Rdn" field. If the PC is used, the instruction is a branch to the address calculated by the operation. This is a simple branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
          <para>The assembler language allows <syntax>&lt;Rdn&gt;</syntax> to be specified once or twice in the assembler syntax. When used inside an IT block, and <syntax>&lt;Rdn&gt;</syntax> and <syntax>&lt;Rm&gt;</syntax> are in the range R0 to R7, <syntax>&lt;Rdn&gt;</syntax> must be specified once so that encoding T2 is preferred to encoding T1. In all other cases there is no difference in behavior when <syntax>&lt;Rdn&gt;</syntax> is specified once or twice.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_r_A1" symboldefcount="1">
      <symbol link="sa_rd_2">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="ADD-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>. If the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the ADD variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the ADDS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;. Arm deprecates use of this instruction.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_r_T1" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose destination register, encoded in the "Rd" field.</para>
          <para>When used inside an IT block, <syntax>&lt;Rd&gt;</syntax> must be specified. When used outside an IT block, <syntax>&lt;Rd&gt;</syntax> is optional, and:</para>
          <list type="unordered">
            <listitem><content>If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>.</content></listitem>
            <listitem><content>If present, encoding T1 is preferred to encoding T2.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_r_T3" symboldefcount="3">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic-shift-type" value="ADD-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding T3: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_r_A1" symboldefcount="1">
      <symbol link="sa_rn_2">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="ADD-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the first general-purpose source register, encoded in the "Rn" field. The PC can be used. If the SP is used, see <xref linkend="A32T32-base.instructions.ADD_SP_r">ADD (SP plus register)</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_r_T1" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_r_T3" symboldefcount="3">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic-shift-type" value="ADD-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding T3: is the first general-purpose source register, encoded in the "Rn" field. If the SP is used, see <xref linkend="A32T32-base.instructions.ADD_SP_r">ADD (SP plus register)</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_r_A1" symboldefcount="1">
      <symbol link="sa_rm_2">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="ADD-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_r_T1, ADD_r_T3" symboldefcount="2">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T3: is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_r_T2" symboldefcount="3">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_r_A1, ADD_r_T3" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="ADD_r_A1" symboldefcount="1">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_r_T3" symboldefcount="2">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm3:imm2" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/ADD_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], shifted, '0');</line>
<line>    if d == 15 then</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="add_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ADD_rr" title="ADD, ADDS (register-shifted register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
  </docvars>
  <heading>ADD, ADDS (register-shifted register)</heading>
  <desc>
    <brief>
      <para>Add (register-shifted register)</para>
    </brief>
    <authored>
      <para>Add (register-shifted register) adds a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/ADD_rr/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ADDS_rr_A1" oneofinclass="2" oneof="2" label="Flag setting" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADDS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>ADDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="Third general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <encoding name="ADD_rr_A1" oneofinclass="2" oneof="2" label="Not flag setting" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADD" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="Third general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_rr/A1_A.txt" mylink="aarch32.instrs.ADD_rr.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);</line>
<line>setflags = (S == '1');  shift_t = <a link="impl-aarch32.DecodeRegShift.1" file="shared_pseudocode.xml" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</a>(stype);</line>
<line>if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ADD_rr_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_rr_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_rr_A1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_rr_A1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_rr_A1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_rr_A1" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="ADD_rr_A1" symboldefcount="1">
      <symbol link="sa_rs">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the third general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/ADD_rr/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shift_n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[s]&lt;7:0&gt;);</line>
<line>    shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], shifted, '0');</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>    if setflags then</line>
<line>        PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="add_sp_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ADD_SP_i" title="ADD, ADDS (SP plus immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>ADD, ADDS (SP plus immediate)</heading>
  <desc>
    <brief>
      <para>Add to SP (immediate)</para>
    </brief>
    <authored>
      <para>Add to SP (immediate) adds an immediate value to the SP value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the ADDS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The ADD variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The ADDS variant of the instruction performs an exception return without the use of the stack. Arm deprecates use of this instruction. However, in this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="5">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt>, </txt>
      <a href="#iclass_t3">T3</a>
      <txt> and </txt>
      <a href="#iclass_t4">T4</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="5" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/ADD_SP_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_SP_i_A1" oneofinclass="2" oneof="7" label="ADD" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADD" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_2" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="ADDS_SP_i_A1" oneofinclass="2" oneof="7" label="ADDS" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADDS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>ADDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_2" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_SP_i/A1_A.txt" mylink="aarch32.instrs.ADD_SP_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  setflags = (S == '1');  imm32 = <a link="impl-aarch32.A32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) A32ExpandImm(bits(12) imm12)">A32ExpandImm</a>(imm12);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="5" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ADD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/ADD_SP_i/T1_A.txt">
        <box hibit="31" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="27" name="SP" settings="1">
          <c>1</c>
        </box>
        <box hibit="26" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="23" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_SP_i_T1" oneofinclass="1" oneof="7" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADD" />
        </docvars>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, SP, #</text><a link="sa_imm8" hover="Unsigned immediate, multiple of 4 [0-1020] (field &quot;imm8&quot;)">&lt;imm8&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_SP_i/T1_A.txt" mylink="aarch32.instrs.ADD_SP_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  setflags = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="5" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ADD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/ADD_SP_i/T2_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" width="7" name="imm7" usename="1">
          <c colspan="7"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_SP_i_T2" oneofinclass="1" oneof="7" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADD" />
        </docvars>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_sp" hover="Stack pointer">{SP,}</a><text> SP, #</text><a link="sa_imm7" hover="Unsigned immediate, multiple of 4 [0-508] (field &quot;imm7&quot;)">&lt;imm7&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_SP_i/T2_A.txt" mylink="aarch32.instrs.ADD_SP_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = 13;  setflags = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm7:'00', 32);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T3" oneof="5" id="iclass_t3" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/ADD_SP_i/T3_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_SP_i_T3" oneofinclass="2" oneof="7" label="ADD" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADD" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate comment="&lt;Rd&gt;, &lt;const&gt; can be represented in T1 or T2"><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="ADDS_SP_i_T3" oneofinclass="2" oneof="7" label="ADDS" bitdiffs="S == 1 &amp;&amp; Rd != 1111">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADDS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>ADDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_SP_i/T3_A.txt" mylink="aarch32.instrs.ADD_SP_i.T3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rd == '1111' &amp;&amp; S == '1' then SEE "CMN (immediate)";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  setflags = (S == '1');  imm32 = <a link="impl-aarch32.T32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) T32ExpandImm(bits(12) imm12)">T32ExpandImm</a>(i:imm3:imm8);</line>
<line>if d == 15 &amp;&amp; !setflags then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T4" oneof="5" id="iclass_t4" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T4" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ADDW" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/ADD_SP_i/T4_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_SP_i_T4" oneofinclass="1" oneof="7" label="T4">
        <docvars>
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADDW" />
        </docvars>
        <asmtemplate comment="&lt;imm12&gt; cannot be represented in T1, T2, or T3"><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, #</text><a link="sa_imm12" hover="12-bit unsigned immediate [0-4095] (field &quot;i:imm3:imm8&quot;)">&lt;imm12&gt;</a></asmtemplate>
        <asmtemplate comment="&lt;imm12&gt; can be represented in T1, T2, or T3"><text>ADDW</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, #</text><a link="sa_imm12" hover="12-bit unsigned immediate [0-4095] (field &quot;i:imm3:imm8&quot;)">&lt;imm12&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_SP_i/T4_A.txt" mylink="aarch32.instrs.ADD_SP_i.T4_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  setflags = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(i:imm3:imm8, 32);</line>
<line>if d == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ADD_SP_i_A1, ADD_SP_i_T1, ADD_SP_i_T2, ADD_SP_i_T3, ADD_SP_i_T4" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_i_A1, ADD_SP_i_T1, ADD_SP_i_T2, ADD_SP_i_T3, ADD_SP_i_T4" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_i_T2" symboldefcount="1">
      <symbol link="sa_sp">SP,</symbol>
      <account encodedin="">
        <intro>
          <para>Is the stack pointer.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_i_T2" symboldefcount="1">
      <symbol link="sa_imm7">&lt;imm7&gt;</symbol>
      <account encodedin="imm7">
        <intro>
          <para>Is the unsigned immediate, a multiple of 4, in the range 0 to 508, encoded in the "imm7" field as &lt;imm7&gt;/4.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_i_A1" symboldefcount="1">
      <symbol link="sa_rd_2">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADD" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the SP. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the ADD variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the ADDS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_i_T1" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADD" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_i_T3, ADD_SP_i_T4" symboldefcount="3">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3 and T4: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the SP.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_i_T1" symboldefcount="1">
      <symbol link="sa_imm8">&lt;imm8&gt;</symbol>
      <account encodedin="imm8">
        <intro>
          <para>Is an unsigned immediate, a multiple of 4, in the range 0 to 1020, encoded in the "imm8" field as &lt;imm8&gt;/4.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_i_T4" symboldefcount="1">
      <symbol link="sa_imm12">&lt;imm12&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <intro>
          <para>Is a 12-bit unsigned immediate, in the range 0 to 4095, encoded in the "i:imm3:imm8" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_i_A1" symboldefcount="1">
      <symbol link="sa_const_1">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: an immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_i_T3" symboldefcount="2">
      <symbol link="sa_const">&lt;const&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3: an immediate value. See <xref linkend="BABGHAGA">Modified immediate constants in T32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/ADD_SP_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[13], imm32, '0');</line>
<line>    if d == 15 then          // Can only occur for A32 encoding</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="add_sp_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ADD_SP_r" title="ADD, ADDS (SP plus register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>ADD, ADDS (SP plus register)</heading>
  <desc>
    <brief>
      <para>Add to SP (register)</para>
    </brief>
    <authored>
      <para>Add to SP (register) adds an optionally-shifted register value to the SP value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the ADDS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The ADD variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The ADDS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/ADD_SP_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_SP_r_A1_RRX" oneofinclass="4" oneof="10" label="ADD, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADD" />
          <docvar key="mnemonic-shift-type" value="ADD-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> , RRX</text></asmtemplate>
      </encoding>
      <encoding name="ADD_SP_r_A1" oneofinclass="4" oneof="10" label="ADD, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADD" />
          <docvar key="mnemonic-shift-type" value="ADD-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="ADDS_SP_r_A1_RRX" oneofinclass="4" oneof="10" label="ADDS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADDS" />
          <docvar key="mnemonic-shift-type" value="ADDS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ADDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> , RRX</text></asmtemplate>
      </encoding>
      <encoding name="ADDS_SP_r_A1" oneofinclass="4" oneof="10" label="ADDS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADDS" />
          <docvar key="mnemonic-shift-type" value="ADDS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>ADDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_SP_r/A1_A.txt" mylink="aarch32.instrs.ADD_SP_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ADD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/ADD_SP_r/T1_A.txt">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="25" width="2" name="op" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" name="DM" usename="1">
          <c></c>
        </box>
        <box hibit="22" width="4" name="Rs" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="18" width="3" name="Rdm" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_SP_r_T1" oneofinclass="1" oneof="10" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADD" />
        </docvars>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdm" hover="General-purpose destination and second source register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rdm" hover="General-purpose destination and second source register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_SP_r/T1_A.txt" mylink="aarch32.instrs.ADD_SP_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(DM:Rdm);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(DM:Rdm);  setflags = FALSE;</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
<line>if d == 15 &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ADD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/ADD_SP_r/T2_A.txt" tworows="1">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="25" width="2" name="op" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" name="D" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" width="4" name="Rm" usename="1" settings="4" constraint="!= 1101">
          <c colspan="4">!= 1101</c>
        </box>
        <box hibit="18" width="3" name="Rd" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="ADD_SP_r_T2" oneofinclass="1" oneof="10" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADD" />
        </docvars>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_sp" hover="Stack pointer">{SP,}</a><text> SP, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_SP_r/T2_A.txt" mylink="aarch32.instrs.ADD_SP_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rm == '1101' then SEE "encoding T1";</line>
<line>d = 13;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = FALSE;</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T3" oneof="4" id="iclass_t3" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/ADD_SP_r/T3_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_SP_r_T3_RRX" oneofinclass="4" oneof="10" label="ADD, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADD" />
          <docvar key="mnemonic-shift-type" value="ADD-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="ADD_SP_r_T3" oneofinclass="4" oneof="10" label="ADD, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADD" />
          <docvar key="mnemonic-shift-type" value="ADD-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="&lt;Rd&gt;, &lt;Rm&gt; can be represented in T1 or T2"><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="ADDS_SP_r_T3_RRX" oneofinclass="4" oneof="10" label="ADDS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm3 == 000 &amp;&amp; Rd != 1111 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADDS" />
          <docvar key="mnemonic-shift-type" value="ADDS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="11" width="4" name="Rd">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ADDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="ADDS_SP_r_T3" oneofinclass="4" oneof="10" label="ADDS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11) &amp;&amp; Rd != 1111">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADDS" />
          <docvar key="mnemonic-shift-type" value="ADDS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <box hibit="11" width="4" name="Rd">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>ADDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_SP_r/T3_A.txt" mylink="aarch32.instrs.ADD_SP_r.T3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rd == '1111' &amp;&amp; S == '1' then SEE "CMN (register)";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm3:imm2);</line>
<line>if (d == 15 &amp;&amp; !setflags) || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ADD_SP_r_A1, ADD_SP_r_T1, ADD_SP_r_T2, ADD_SP_r_T3" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_r_A1, ADD_SP_r_T1, ADD_SP_r_T2, ADD_SP_r_T3" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_r_T2" symboldefcount="1">
      <symbol link="sa_sp">SP,</symbol>
      <account encodedin="">
        <intro>
          <para>Is the stack pointer.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_r_T1" symboldefcount="1">
      <symbol link="sa_rdm">&lt;Rdm&gt;</symbol>
      <account encodedin="Rdm">
        <intro>
          <para>Is the general-purpose destination and second source register, encoded in the "Rdm" field. If omitted, this register is the SP. Arm deprecates using the PC as the destination register, but if the PC is used, the instruction is a branch to the address calculated by the operation. This is a simple branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_r_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the SP. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the ADD variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the ADDS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_r_T3" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the SP.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_r_A1, ADD_SP_r_T2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>For encoding A1 and T2: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_r_T3" symboldefcount="2">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic-shift-type" value="ADD-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding T3: is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_r_A1, ADD_SP_r_T3" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="ADD_SP_r_A1" symboldefcount="1">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_r_T3" symboldefcount="2">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm3:imm2" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/ADD_SP_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[13], shifted, '0');</line>
<line>    if d == 15 then</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="adr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ADR" title="ADR -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="ADR" />
  </docvars>
  <heading>ADR</heading>
  <desc>
    <brief>
      <para>Form PC-relative address</para>
    </brief>
    <authored>
      <para>Form PC-relative address adds an immediate value to the PC value to form a PC-relative address, and writes the result to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>The instruction aliases permit the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see <xref linkend="BABGCIBA">Use of labels in UAL instruction syntax</xref>.</para>
    </syntaxnotes>
  </desc>
  <alias_list howmany="2">
    <alias_list_intro>This instruction is used by the aliases </alias_list_intro>
    <aliasref aliaspageid="ADD_ADR" aliasfile="add_adr.xml" hover="Add to PC" punct=" and ">
      <text>ADD (immediate, to PC)</text>
      <aliaspref>Never</aliaspref>
    </aliasref>
    <aliasref aliaspageid="SUB_ADR" aliasfile="sub_adr.xml" hover="Subtract from PC" punct=".">
      <text>SUB (immediate, from PC)</text>
      <aliaspref labels="T2">i:imm3:imm8 == '000000000000'</aliaspref>
      <aliaspref labels="A2">imm12 == '000000000000'</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink />
      <text> below for details of when each alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <classesintro count="5">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="5" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="ADR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/ADR/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="ADR_A1" oneofinclass="1" oneof="5" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADR" />
        </docvars>
        <asmtemplate><text>ADR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_label_2" hover="The label of an instruction or literal data item whose address is to be loaded into {syntax{&lt;Rd&gt;}}">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADR/A1_A.txt" mylink="aarch32.instrs.ADR.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  imm32 = <a link="impl-aarch32.A32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) A32ExpandImm(bits(12) imm12)">A32ExpandImm</a>(imm12);  add = TRUE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="5" id="iclass_a2" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="ADR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/ADR/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="ADR_A2" oneofinclass="1" oneof="5" label="A2">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADR" />
        </docvars>
        <asmtemplate><text>ADR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_label_2" hover="The label of an instruction or literal data item whose address is to be loaded into {syntax{&lt;Rd&gt;}}">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADR/A2_A.txt" mylink="aarch32.instrs.ADR.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  imm32 = <a link="impl-aarch32.A32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) A32ExpandImm(bits(12) imm12)">A32ExpandImm</a>(imm12);  add = FALSE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="5" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ADR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/ADR/T1_A.txt">
        <box hibit="31" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="27" name="SP" settings="1">
          <c>0</c>
        </box>
        <box hibit="26" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="23" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="ADR_T1" oneofinclass="1" oneof="5" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADR" />
        </docvars>
        <asmtemplate><text>ADR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_label" hover="The label of an instruction or literal data item whose address is to be loaded into {syntax{&lt;Rd&gt;}}">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADR/T1_A.txt" mylink="aarch32.instrs.ADR.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);  add = TRUE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="5" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ADR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/ADR/T2_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="ADR_T2" oneofinclass="1" oneof="5" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADR" />
        </docvars>
        <asmtemplate><text>ADR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_label_1" hover="The label of an instruction or literal data item whose address is to be loaded into {syntax{&lt;Rd&gt;}}">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADR/T2_A.txt" mylink="aarch32.instrs.ADR.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(i:imm3:imm8, 32);  add = FALSE;</line>
<line>if d == 15 then UNPREDICTABLE;     // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T3" oneof="5" id="iclass_t3" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ADR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/ADR/T3_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="ADR_T3" oneofinclass="1" oneof="5" label="T3">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADR" />
        </docvars>
        <asmtemplate comment="&lt;Rd&gt;, &lt;label&gt; can be presented in T1"><text>ADR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_label_1" hover="The label of an instruction or literal data item whose address is to be loaded into {syntax{&lt;Rd&gt;}}">&lt;label&gt;</a></asmtemplate>
        <asmtemplate><text>ADR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_label_1" hover="The label of an instruction or literal data item whose address is to be loaded into {syntax{&lt;Rd&gt;}}">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADR/T3_A.txt" mylink="aarch32.instrs.ADR.T3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(i:imm3:imm8, 32);  add = TRUE;</line>
<line>if d == 15 then UNPREDICTABLE;   // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ADR_A1, ADR_A2, ADR_T1, ADR_T2, ADR_T3" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADR_A1, ADR_A2, ADR_T1, ADR_T2, ADR_T3" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADR_A1, ADR_A2" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1 and A2: is the general-purpose destination register, encoded in the "Rd" field. If the PC is used, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADR_T1, ADR_T2, ADR_T3" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1, T2 and T3: is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADR_A1, ADR_A2" symboldefcount="1">
      <symbol link="sa_label_2">&lt;label&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1 and A2: the label of an instruction or literal data item whose address is to be loaded into <syntax>&lt;Rd&gt;</syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the <instruction>ADR</instruction> instruction to this label.</para>
          <para>If the offset is zero or positive, encoding A1 is used, with <field>imm32</field> equal to the offset.</para>
          <para>If the offset is negative, encoding A2 is used, with <field>imm32</field> equal to the size of the offset. That is, the use of encoding A2 indicates that the required offset is minus the value of <field>imm32</field>.</para>
          <para>Permitted values of the size of the offset are any of the constants described in <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADR_T1" symboldefcount="2">
      <symbol link="sa_label">&lt;label&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: the label of an instruction or literal data item whose address is to be loaded into <syntax>&lt;Rd&gt;</syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the <instruction>ADR</instruction> instruction to this label. Permitted values of the size of the offset are multiples of 4 in the range 0 to 1020.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADR_T2, ADR_T3" symboldefcount="3">
      <symbol link="sa_label_1">&lt;label&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2 and T3: the label of an instruction or literal data item whose address is to be loaded into <syntax>&lt;Rd&gt;</syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the <instruction>ADR</instruction> instruction to this label.</para>
          <para>If the offset is zero or positive, encoding T3 is used, with <field>imm32</field> equal to the offset.</para>
          <para>If the offset is negative, encoding T2 is used, with <field>imm32</field> equal to the size of the offset. That is, the use of encoding T2 indicates that the required offset is minus the value of <field>imm32</field>.</para>
          <para>Permitted values of the size of the offset are 0-4095.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/ADR/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    result = if add then (<a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4) + imm32) else (<a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4) - imm32);</line>
<line>    if d == 15 then          // Can only occur for A32 encodings</line>
<line>        <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="aesd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="AESD" title="AESD -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="AESD" />
  </docvars>
  <heading>AESD</heading>
  <desc>
    <brief>
      <para>AES single round decryption</para>
    </brief>
    <authored>
      <para>AES single round decryption.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="AESD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_AES" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/AESD/A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="AESD_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="AESD" />
        </docvars>
        <asmtemplate><text>AESD.</text><a link="sa_dt" hover="Data type (field &quot;size&quot;) [8,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/AESD/A1_A.txt" mylink="aarch32.instrs.AESD.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveAESExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAESExt()">HaveAESExt</a>() then UNDEFINED;</line>
<line>if size != '00' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="AESD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_AES" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/AESD/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="AESD_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="AESD" />
        </docvars>
        <asmtemplate><text>AESD.</text><a link="sa_dt" hover="Data type (field &quot;size&quot;) [8,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/AESD/T1_A.txt" mylink="aarch32.instrs.AESD.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveAESExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAESExt()">HaveAESExt</a>() then UNDEFINED;</line>
<line>if size != '00' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="AESD_A1, AESD_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">1x</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="AESD_A1, AESD_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AESD_A1, AESD_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/AESD/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations(); <a link="impl-aarch32.CheckCryptoEnabled32.0" file="shared_pseudocode.xml" hover="function: CheckCryptoEnabled32()">CheckCryptoEnabled32</a>();</line>
<line>    op1 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[d&gt;&gt;1]; op2 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1];</line>
<line>    <a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = <a link="impl-shared.AESInvSubBytes.1" file="shared_pseudocode.xml" hover="function: bits(128) AESInvSubBytes(bits(128) op)">AESInvSubBytes</a>(<a link="impl-shared.AESInvShiftRows.1" file="shared_pseudocode.xml" hover="function: bits(128) AESInvShiftRows(bits(128) op)">AESInvShiftRows</a>(op1 EOR op2));</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="aese.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="AESE" title="AESE -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="AESE" />
  </docvars>
  <heading>AESE</heading>
  <desc>
    <brief>
      <para>AES single round encryption</para>
    </brief>
    <authored>
      <para>AES single round encryption.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="AESE" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_AES" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/AESE/A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="AESE_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="AESE" />
        </docvars>
        <asmtemplate><text>AESE.</text><a link="sa_dt" hover="Data type (field &quot;size&quot;) [8,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/AESE/A1_A.txt" mylink="aarch32.instrs.AESE.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveAESExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAESExt()">HaveAESExt</a>() then UNDEFINED;</line>
<line>if size != '00' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="AESE" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_AES" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/AESE/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="AESE_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="AESE" />
        </docvars>
        <asmtemplate><text>AESE.</text><a link="sa_dt" hover="Data type (field &quot;size&quot;) [8,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/AESE/T1_A.txt" mylink="aarch32.instrs.AESE.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveAESExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAESExt()">HaveAESExt</a>() then UNDEFINED;</line>
<line>if size != '00' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="AESE_A1, AESE_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">1x</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="AESE_A1, AESE_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AESE_A1, AESE_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/AESE/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations(); <a link="impl-aarch32.CheckCryptoEnabled32.0" file="shared_pseudocode.xml" hover="function: CheckCryptoEnabled32()">CheckCryptoEnabled32</a>();</line>
<line>    op1 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[d&gt;&gt;1]; op2 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1];</line>
<line>    <a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = <a link="impl-shared.AESSubBytes.1" file="shared_pseudocode.xml" hover="function: bits(128) AESSubBytes(bits(128) op)">AESSubBytes</a>(<a link="impl-shared.AESShiftRows.1" file="shared_pseudocode.xml" hover="function: bits(128) AESShiftRows(bits(128) op)">AESShiftRows</a>(op1 EOR op2));</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="aesimc.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="AESIMC" title="AESIMC -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="AESIMC" />
  </docvars>
  <heading>AESIMC</heading>
  <desc>
    <brief>
      <para>AES inverse mix columns</para>
    </brief>
    <authored>
      <para>AES inverse mix columns.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="AESIMC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_AES" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/AESIMC/A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="AESIMC_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="AESIMC" />
        </docvars>
        <asmtemplate><text>AESIMC.</text><a link="sa_dt" hover="Data type (field &quot;size&quot;) [8,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/AESIMC/A1_A.txt" mylink="aarch32.instrs.AESIMC.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveAESExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAESExt()">HaveAESExt</a>() then UNDEFINED;</line>
<line>if size != '00' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="AESIMC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_AES" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/AESIMC/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="AESIMC_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="AESIMC" />
        </docvars>
        <asmtemplate><text>AESIMC.</text><a link="sa_dt" hover="Data type (field &quot;size&quot;) [8,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/AESIMC/T1_A.txt" mylink="aarch32.instrs.AESIMC.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveAESExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAESExt()">HaveAESExt</a>() then UNDEFINED;</line>
<line>if size != '00' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="AESIMC_A1, AESIMC_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">1x</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="AESIMC_A1, AESIMC_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AESIMC_A1, AESIMC_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/AESIMC/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations(); <a link="impl-aarch32.CheckCryptoEnabled32.0" file="shared_pseudocode.xml" hover="function: CheckCryptoEnabled32()">CheckCryptoEnabled32</a>();</line>
<line>    <a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = <a link="impl-shared.AESInvMixColumns.1" file="shared_pseudocode.xml" hover="function: bits(128) AESInvMixColumns(bits (128) op)">AESInvMixColumns</a>(<a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="aesmc.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="AESMC" title="AESMC -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="AESMC" />
  </docvars>
  <heading>AESMC</heading>
  <desc>
    <brief>
      <para>AES mix columns</para>
    </brief>
    <authored>
      <para>AES mix columns.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="AESMC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_AES" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/AESMC/A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="AESMC_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="AESMC" />
        </docvars>
        <asmtemplate><text>AESMC.</text><a link="sa_dt" hover="Data type (field &quot;size&quot;) [8,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/AESMC/A1_A.txt" mylink="aarch32.instrs.AESMC.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveAESExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAESExt()">HaveAESExt</a>() then UNDEFINED;</line>
<line>if size != '00' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="AESMC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_AES" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/AESMC/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="AESMC_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="AESMC" />
        </docvars>
        <asmtemplate><text>AESMC.</text><a link="sa_dt" hover="Data type (field &quot;size&quot;) [8,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/AESMC/T1_A.txt" mylink="aarch32.instrs.AESMC.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveAESExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAESExt()">HaveAESExt</a>() then UNDEFINED;</line>
<line>if size != '00' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="AESMC_A1, AESMC_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">1x</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="AESMC_A1, AESMC_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AESMC_A1, AESMC_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/AESMC/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations(); <a link="impl-aarch32.CheckCryptoEnabled32.0" file="shared_pseudocode.xml" hover="function: CheckCryptoEnabled32()">CheckCryptoEnabled32</a>();</line>
<line>    <a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = <a link="impl-shared.AESMixColumns.1" file="shared_pseudocode.xml" hover="function: bits(128) AESMixColumns(bits (128) op)">AESMixColumns</a>(<a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="and_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="AND_i" title="AND, ANDS (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>AND, ANDS (immediate)</heading>
  <desc>
    <brief>
      <para>Bitwise AND (immediate)</para>
    </brief>
    <authored>
      <para>Bitwise AND (immediate) performs a bitwise AND of a register value and an immediate value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the ANDS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The AND variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The ANDS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/AND_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="AND_i_A1" oneofinclass="2" oneof="4" label="AND" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="AND" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>AND</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="ANDS_i_A1" oneofinclass="2" oneof="4" label="ANDS" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ANDS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>ANDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/AND_i/A1_A.txt" mylink="aarch32.instrs.AND_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = (S == '1');</line>
<line>(imm32, carry) = <a link="impl-aarch32.A32ExpandImm_C.2" file="shared_pseudocode.xml" hover="function: (bits(32), bit) A32ExpandImm_C(bits(12) imm12, bit carry_in)">A32ExpandImm_C</a>(imm12, PSTATE.C);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/AND_i/T1_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="AND_i_T1" oneofinclass="2" oneof="4" label="AND" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="AND" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>AND</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="ANDS_i_T1" oneofinclass="2" oneof="4" label="ANDS" bitdiffs="S == 1 &amp;&amp; Rd != 1111">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ANDS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>ANDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/AND_i/T1_A.txt" mylink="aarch32.instrs.AND_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rd == '1111' &amp;&amp; S == '1' then SEE "TST (immediate)";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = (S == '1');</line>
<line>(imm32, carry) = <a link="impl-aarch32.T32ExpandImm_C.2" file="shared_pseudocode.xml" hover="function: (bits(32), bit) T32ExpandImm_C(bits(12) imm12, bit carry_in)">T32ExpandImm_C</a>(i:imm3:imm8, PSTATE.C);</line>
<line>if (d == 15 &amp;&amp; !setflags) || n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="AND_i_A1, AND_i_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AND_i_A1, AND_i_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AND_i_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the AND variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the ANDS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AND_i_T1" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AND_i_A1" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AND_i_T1" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AND_i_A1" symboldefcount="1">
      <symbol link="sa_const_1">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: an immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AND_i_T1" symboldefcount="2">
      <symbol link="sa_const">&lt;const&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: an immediate value. See <xref linkend="BABGHAGA">Modified immediate constants in T32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/AND_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    result = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] AND imm32;</line>
<line>    if d == 15 then          // Can only occur for A32 encoding</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.N = result&lt;31&gt;;</line>
<line>            PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>            PSTATE.C = carry;</line>
<line>            // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="and_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="AND_r" title="AND, ANDS (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>AND, ANDS (register)</heading>
  <desc>
    <brief>
      <para>Bitwise AND (register)</para>
    </brief>
    <authored>
      <para>Bitwise AND (register) performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the ANDS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The AND variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The ANDS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>In T32 assembly:</para>
      <list type="unordered">
        <listitem><content>Outside an IT block, if <syntax>ANDS &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rd&gt;</syntax> has <syntax>&lt;Rd&gt;</syntax> and <syntax>&lt;Rn&gt;</syntax> both in the range R0-R7, it is assembled using encoding T1 as though <syntax>ANDS &lt;Rd&gt;, &lt;Rn&gt;</syntax> had been written.</content></listitem>
        <listitem><content>Inside an IT block, if <syntax>AND&lt;c&gt; &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rd&gt;</syntax> has <syntax>&lt;Rd&gt;</syntax> and <syntax>&lt;Rn&gt;</syntax> both in the range R0-R7, it is assembled using encoding T1 as though <syntax>AND&lt;c&gt; &lt;Rd&gt;, &lt;Rn&gt;</syntax> had been written.</content></listitem>
      </list>
      <para>To prevent either of these happening, use the <syntax>.W</syntax> qualifier.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/AND_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="AND_r_A1_RRX" oneofinclass="4" oneof="9" label="AND, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="AND" />
          <docvar key="mnemonic-shift-type" value="AND-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>AND</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="AND_r_A1" oneofinclass="4" oneof="9" label="AND, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="AND" />
          <docvar key="mnemonic-shift-type" value="AND-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>AND</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="ANDS_r_A1_RRX" oneofinclass="4" oneof="9" label="ANDS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ANDS" />
          <docvar key="mnemonic-shift-type" value="ANDS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ANDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="ANDS_r_A1" oneofinclass="4" oneof="9" label="ANDS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ANDS" />
          <docvar key="mnemonic-shift-type" value="ANDS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>ANDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/AND_r/A1_A.txt" mylink="aarch32.instrs.AND_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="AND" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/AND_r/T1_A.txt">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="4" name="op" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rdn" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="AND_r_T1" oneofinclass="1" oneof="9" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="AND" />
        </docvars>
        <asmtemplate comment="Inside IT block"><text>AND</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate comment="Outside IT block"><text>ANDS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/AND_r/T1_A.txt" mylink="aarch32.instrs.AND_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdn);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>();</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/AND_r/T2_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="AND_r_T2_RRX" oneofinclass="4" oneof="9" label="AND, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="AND" />
          <docvar key="mnemonic-shift-type" value="AND-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>AND</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="AND_r_T2" oneofinclass="4" oneof="9" label="AND, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="AND" />
          <docvar key="mnemonic-shift-type" value="AND-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Inside IT block, and &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>AND</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>AND</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="ANDS_r_T2_RRX" oneofinclass="4" oneof="9" label="ANDS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm3 == 000 &amp;&amp; Rd != 1111 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ANDS" />
          <docvar key="mnemonic-shift-type" value="ANDS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="11" width="4" name="Rd">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ANDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="ANDS_r_T2" oneofinclass="4" oneof="9" label="ANDS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11) &amp;&amp; Rd != 1111">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ANDS" />
          <docvar key="mnemonic-shift-type" value="ANDS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <box hibit="11" width="4" name="Rd">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Outside IT block, and &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>ANDS.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>ANDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/AND_r/T2_A.txt" mylink="aarch32.instrs.AND_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rd == '1111' &amp;&amp; S == '1' then SEE "TST (register)";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm3:imm2);</line>
<line>if (d == 15 &amp;&amp; !setflags) || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="AND_r_A1, AND_r_T1, AND_r_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AND_r_A1, AND_r_T1, AND_r_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AND_r_T1" symboldefcount="1">
      <symbol link="sa_rdn">&lt;Rdn&gt;</symbol>
      <account encodedin="Rdn">
        <intro>
          <para>Is the first general-purpose source register and the destination register, encoded in the "Rdn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AND_r_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the AND variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the ANDS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AND_r_T2" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AND_r_A1" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AND_r_T2" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AND_r_A1" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="AND-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AND_r_T1, AND_r_T2" symboldefcount="2">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AND_r_A1, AND_r_T2" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="AND_r_A1" symboldefcount="1">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AND_r_T2" symboldefcount="2">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm3:imm2" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/AND_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    (shifted, carry) = <a link="impl-aarch32.Shift_C.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift_C</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    result = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] AND shifted;</line>
<line>    if d == 15 then          // Can only occur for A32 encoding</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.N = result&lt;31&gt;;</line>
<line>            PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>            PSTATE.C = carry;</line>
<line>            // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="and_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="AND_rr" title="AND, ANDS (register-shifted register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
  </docvars>
  <heading>AND, ANDS (register-shifted register)</heading>
  <desc>
    <brief>
      <para>Bitwise AND (register-shifted register)</para>
    </brief>
    <authored>
      <para>Bitwise AND (register-shifted register) performs a bitwise AND of a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/AND_rr/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ANDS_rr_A1" oneofinclass="2" oneof="2" label="Flag setting" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ANDS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>ANDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="Third general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <encoding name="AND_rr_A1" oneofinclass="2" oneof="2" label="Not flag setting" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="AND" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>AND</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="Third general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/AND_rr/A1_A.txt" mylink="aarch32.instrs.AND_rr.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);</line>
<line>setflags = (S == '1');  shift_t = <a link="impl-aarch32.DecodeRegShift.1" file="shared_pseudocode.xml" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</a>(stype);</line>
<line>if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="AND_rr_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AND_rr_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AND_rr_A1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AND_rr_A1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AND_rr_A1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="AND_rr_A1" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="AND_rr_A1" symboldefcount="1">
      <symbol link="sa_rs">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the third general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/AND_rr/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shift_n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[s]&lt;7:0&gt;);</line>
<line>    (shifted, carry) = <a link="impl-aarch32.Shift_C.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift_C</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    result = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] AND shifted;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>    if setflags then</line>
<line>        PSTATE.N = result&lt;31&gt;;</line>
<line>        PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>        PSTATE.C = carry;</line>
<line>        // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="asr_mov_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ASR_MOV_r" title="ASR (immediate) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="ASR" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MOV" />
  </docvars>
  <heading>ASR (immediate)</heading>
  <desc>
    <brief>
      <para>Arithmetic Shift Right (immediate)</para>
    </brief>
    <authored>
      <para>Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in copies of its sign bit, and writes the result to the destination register.</para>
    </authored>
  </desc>
  <aliasto refiform="mov_r.xml" iformid="MOV_r">MOV, MOVS (register)</aliasto>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ASR_MOV_r_A1" oneofinclass="1" oneof="3" label="MOV, shift or rotate by value">
        <docvars>
          <docvar key="alias_mnemonic" value="ASR" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <asmtemplate><text>ASR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_3" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_2" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_1" hover="Shift amount [1-32] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOV_r_A1">MOV</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_3" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_2" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, ASR #</text><a link="sa_imm_1" hover="Shift amount [1-32] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MOV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="28" width="2" name="op" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="ASR_MOV_r_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="alias_mnemonic" value="ASR" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
        </docvars>
        <asmtemplate comment="Inside IT block"><text>ASR</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_1" hover="Shift amount [1-32] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOV_r_T2">MOV</a><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, ASR #</text><a link="sa_imm_1" hover="Shift amount [1-32] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
          <aliascond><a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T3" oneof="3" id="iclass_t3" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ASR_MOV_r_T3" oneofinclass="1" oneof="3" label="MOV, shift or rotate by value">
        <docvars>
          <docvar key="alias_mnemonic" value="ASR" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <asmtemplate comment="Inside IT block, and &lt;Rd&gt;, &lt;Rm&gt;, &lt;imm&gt; can be represented in T2"><text>ASR</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_2" hover="Shift amount [1-32] (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a></asmtemplate>
        <asmtemplate><text>ASR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_2" hover="Shift amount [1-32] (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOV_r_T3">MOV</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, ASR #</text><a link="sa_imm_2" hover="Shift amount [1-32] (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ASR_MOV_r_A1, ASR_MOV_r_T2, ASR_MOV_r_T3" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASR_MOV_r_A1, ASR_MOV_r_T2, ASR_MOV_r_T3" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASR_MOV_r_A1" symboldefcount="1">
      <symbol link="sa_rd_3">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. Arm deprecates using the PC as the destination register, but if the PC is used, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASR_MOV_r_T2, ASR_MOV_r_T3" symboldefcount="2">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>For encoding T2 and T3: is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASR_MOV_r_A1" symboldefcount="1">
      <symbol link="sa_rm_2">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASR_MOV_r_T2, ASR_MOV_r_T3" symboldefcount="2">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>For encoding T2 and T3: is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASR_MOV_r_A1, ASR_MOV_r_T2" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm5">
        <intro>
          <para>For encoding A1 and T2: is the shift amount, in the range 1 to 32, encoded in the "imm5" field as &lt;imm&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASR_MOV_r_T3" symboldefcount="2">
      <symbol link="sa_imm_2">&lt;imm&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding T3: is the shift amount, in the range 1 to 32, encoded in the "imm3:imm2" field as &lt;imm&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="asr_mov_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ASR_MOV_rr" title="ASR (register) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="ASR" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MOV" />
  </docvars>
  <heading>ASR (register)</heading>
  <desc>
    <brief>Arithmetic Shift Right (register)</brief>
    <longer> shifts a register value right by a variable number of bits, shifting in copies of its sign bit, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register</longer>
  </desc>
  <aliasto refiform="mov_rr.xml" iformid="MOV_rr">MOV, MOVS (register-shifted register)</aliasto>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ASR_MOV_rr_A1" oneofinclass="1" oneof="3" label="Not flag setting">
        <docvars>
          <docvar key="alias_mnemonic" value="ASR" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOV" />
        </docvars>
        <asmtemplate><text>ASR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOV_rr_A1">MOV</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, ASR </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MOV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="" tworows="1">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="4" name="op" usename="1" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="21" width="3" name="Rs" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rdm" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="ASR_MOV_rr_T1_ASR" oneofinclass="1" oneof="3" label="Arithmetic shift right">
        <docvars>
          <docvar key="alias_mnemonic" value="ASR" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-asr" />
          <docvar key="shift-type" value="asr" />
        </docvars>
        <asmtemplate comment="Inside IT block"><text>ASR</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOV_rr_T1_ASR">MOV</a><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, ASR </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond><a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="stype" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ASR_MOV_rr_T2" oneofinclass="1" oneof="3" label="Not flag setting">
        <docvars>
          <docvar key="alias_mnemonic" value="ASR" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
        </docvars>
        <asmtemplate comment="Inside IT block, and &lt;Rd&gt;, &lt;Rm&gt;, &lt;shift&gt;, &lt;Rs&gt; can be represented in T1"><text>ASR</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <asmtemplate><text>ASR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOV_rr_T2">MOV</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, ASR </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ASR_MOV_rr_A1, ASR_MOV_rr_T1_ASR, ASR_MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASR_MOV_rr_A1, ASR_MOV_rr_T1_ASR, ASR_MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASR_MOV_rr_T1_ASR" symboldefcount="1">
      <symbol link="sa_rdm_1">&lt;Rdm&gt;</symbol>
      <account encodedin="Rdm">
        <intro>
          <para>Is the first general-purpose source register and the destination register, encoded in the "Rdm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASR_MOV_rr_A1, ASR_MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASR_MOV_rr_A1, ASR_MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASR_MOV_rr_A1, ASR_MOV_rr_T1_ASR, ASR_MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_rs_1">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the second general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="asrs_mov_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ASRS_MOV_r" title="ASRS (immediate) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="ASRS" />
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>ASRS (immediate)</heading>
  <desc>
    <brief>
      <para>Arithmetic Shift Right, setting flags (immediate)</para>
    </brief>
    <authored>
      <para>Arithmetic Shift Right, setting flags (immediate) shifts a register value right by an immediate number of bits, shifting in copies of its sign bit, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, this instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
        <listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem>
        <listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem>
        <listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem>
      </list>
    </authored>
  </desc>
  <aliasto refiform="mov_r.xml" iformid="MOV_r">MOV, MOVS (register)</aliasto>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ASRS_MOVS_r_A1" oneofinclass="1" oneof="3" label="MOVS, shift or rotate by value">
        <docvars>
          <docvar key="alias_mnemonic" value="ASRS" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOVS" />
          <docvar key="mnemonic-shift-type" value="MOVS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <asmtemplate><text>ASRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_4" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_2" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_1" hover="Shift amount [1-32] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOVS_r_A1">MOVS</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_4" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_2" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, ASR #</text><a link="sa_imm_1" hover="Shift amount [1-32] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MOV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="28" width="2" name="op" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="ASRS_MOV_r_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="alias_mnemonic" value="ASRS" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
        </docvars>
        <asmtemplate comment="Outside IT block"><text>ASRS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_1" hover="Shift amount [1-32] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOV_r_T2">MOVS</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, ASR #</text><a link="sa_imm_1" hover="Shift amount [1-32] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
          <aliascond>!<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T3" oneof="3" id="iclass_t3" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ASRS_MOVS_r_T3" oneofinclass="1" oneof="3" label="MOVS, shift or rotate by value">
        <docvars>
          <docvar key="alias_mnemonic" value="ASRS" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOVS" />
          <docvar key="mnemonic-shift-type" value="MOVS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <asmtemplate comment="Outside IT block, and &lt;Rd&gt;, &lt;Rm&gt;, &lt;imm&gt; can be represented in T2"><text>ASRS.W </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_2" hover="Shift amount [1-32] (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a></asmtemplate>
        <asmtemplate><text>ASRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_2" hover="Shift amount [1-32] (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOVS_r_T3">MOVS</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, ASR #</text><a link="sa_imm_2" hover="Shift amount [1-32] (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ASRS_MOVS_r_A1, ASRS_MOVS_r_T3" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASRS_MOVS_r_A1, ASRS_MOV_r_T2, ASRS_MOVS_r_T3" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASRS_MOVS_r_A1" symboldefcount="1">
      <symbol link="sa_rd_4">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. Arm deprecates using the PC as the destination register, but if the PC is used, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASRS_MOV_r_T2, ASRS_MOVS_r_T3" symboldefcount="2">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>For encoding T2 and T3: is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASRS_MOVS_r_A1" symboldefcount="1">
      <symbol link="sa_rm_2">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASRS_MOV_r_T2, ASRS_MOVS_r_T3" symboldefcount="2">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>For encoding T2 and T3: is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASRS_MOVS_r_A1, ASRS_MOV_r_T2" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm5">
        <intro>
          <para>For encoding A1 and T2: is the shift amount, in the range 1 to 32, encoded in the "imm5" field as &lt;imm&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASRS_MOVS_r_T3" symboldefcount="2">
      <symbol link="sa_imm_2">&lt;imm&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding T3: is the shift amount, in the range 1 to 32, encoded in the "imm3:imm2" field as &lt;imm&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="asrs_mov_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ASRS_MOV_rr" title="ASRS (register) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="ASRS" />
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>ASRS (register)</heading>
  <desc>
    <brief>Arithmetic Shift Right, setting flags (register)</brief>
    <longer> shifts a register value right by a variable number of bits, shifting in copies of its sign bit, writes the result to the destination register, and updates the condition flags based on the result. The variable number of bits is read from the bottom byte of a register</longer>
  </desc>
  <aliasto refiform="mov_rr.xml" iformid="MOV_rr">MOV, MOVS (register-shifted register)</aliasto>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ASRS_MOVS_rr_A1" oneofinclass="1" oneof="3" label="Flag setting">
        <docvars>
          <docvar key="alias_mnemonic" value="ASRS" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOVS" />
        </docvars>
        <asmtemplate><text>ASRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOVS_rr_A1">MOVS</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, ASR </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MOV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="" tworows="1">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="4" name="op" usename="1" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="21" width="3" name="Rs" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rdm" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="ASRS_MOV_rr_T1_ASR" oneofinclass="1" oneof="3" label="Arithmetic shift right">
        <docvars>
          <docvar key="alias_mnemonic" value="ASRS" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-asr" />
          <docvar key="shift-type" value="asr" />
        </docvars>
        <asmtemplate comment="Outside IT block"><text>ASRS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOV_rr_T1_ASR">MOVS</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, ASR </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond>!<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="stype" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ASRS_MOVS_rr_T2" oneofinclass="1" oneof="3" label="Flag setting">
        <docvars>
          <docvar key="alias_mnemonic" value="ASRS" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOVS" />
        </docvars>
        <asmtemplate comment="Outside IT block, and &lt;Rd&gt;, &lt;Rm&gt;, &lt;shift&gt;, &lt;Rs&gt; can be represented in T1"><text>ASRS.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <asmtemplate><text>ASRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOVS_rr_T2">MOVS</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, ASR </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ASRS_MOVS_rr_A1, ASRS_MOVS_rr_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASRS_MOVS_rr_A1, ASRS_MOV_rr_T1_ASR, ASRS_MOVS_rr_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASRS_MOV_rr_T1_ASR" symboldefcount="1">
      <symbol link="sa_rdm_1">&lt;Rdm&gt;</symbol>
      <account encodedin="Rdm">
        <intro>
          <para>Is the first general-purpose source register and the destination register, encoded in the "Rdm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASRS_MOVS_rr_A1, ASRS_MOVS_rr_T2" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASRS_MOVS_rr_A1, ASRS_MOVS_rr_T2" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ASRS_MOVS_rr_A1, ASRS_MOV_rr_T1_ASR, ASRS_MOVS_rr_T2" symboldefcount="1">
      <symbol link="sa_rs_1">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the second general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="b.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="B" title="B -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="B" />
  </docvars>
  <heading>B</heading>
  <desc>
    <brief>
      <para>Branch</para>
    </brief>
    <authored>
      <para>Branch causes a branch to a target address.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
      <para>Related encodings: <xref linkend="T32.encoding_index.bcrtrl">Branches and miscellaneous control</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="5">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt>, </txt>
      <a href="#iclass_t3">T3</a>
      <txt> and </txt>
      <a href="#iclass_t4">T4</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="5" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="B" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/B/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" width="24" name="imm24" usename="1">
          <c colspan="24"></c>
        </box>
      </regdiagram>
      <encoding name="B_A1" oneofinclass="1" oneof="5" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="B" />
        </docvars>
        <asmtemplate><text>B</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_label_4" hover="The label of instruction that is to be branched to">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/B/A1_A.txt" mylink="aarch32.instrs.B.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>imm32 = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm24:'00', 32);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="5" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="B" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/B/T1_A.txt" tworows="1">
        <box hibit="31" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="27" width="4" name="cond" usename="1" settings="4" constraint="!= 111x">
          <c colspan="4">!= 111x</c>
        </box>
        <box hibit="23" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="B_T1" oneofinclass="1" oneof="5" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="B" />
        </docvars>
        <asmtemplate comment="Not permitted in IT block"><text>B</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_label" hover="The label of instruction that is to be branched to">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/B/T1_A.txt" mylink="aarch32.instrs.B.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if cond == '1110' then SEE "UDF";</line>
<line>if cond == '1111' then SEE "SVC";</line>
<line>imm32 = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm8:'0', 32);</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="5" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="B" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/B/T2_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="26" width="11" name="imm11" usename="1">
          <c colspan="11"></c>
        </box>
      </regdiagram>
      <encoding name="B_T2" oneofinclass="1" oneof="5" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="B" />
        </docvars>
        <asmtemplate comment="Outside or last in IT block"><text>B</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_label_1" hover="The label of instruction that is to be branched to">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/B/T2_A.txt" mylink="aarch32.instrs.B.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>imm32 = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm11:'0', 32);</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T3" oneof="5" id="iclass_t3" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="B" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/B/T3_A.txt" tworows="1">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="25" width="4" name="cond" usename="1" settings="4" constraint="!= 111x">
          <c colspan="4">!= 111x</c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" name="J1" usename="1">
          <c></c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" name="J2" usename="1">
          <c></c>
        </box>
        <box hibit="10" width="11" name="imm11" usename="1">
          <c colspan="11"></c>
        </box>
      </regdiagram>
      <encoding name="B_T3" oneofinclass="1" oneof="5" label="T3">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="B" />
        </docvars>
        <asmtemplate comment="Not permitted in IT block, and &lt;label&gt; can be represented in T1"><text>B</text><a link="sa_c_2" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><a link="sa_label_2" hover="The label of instruction that is to be branched to">&lt;label&gt;</a></asmtemplate>
        <asmtemplate comment="Not permitted in IT block"><text>B</text><a link="sa_c_2" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_label_2" hover="The label of instruction that is to be branched to">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/B/T3_A.txt" mylink="aarch32.instrs.B.T3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if cond&lt;3:1&gt; == '111' then SEE "Related encodings";</line>
<line>imm32 = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(S:J2:J1:imm6:imm11:'0', 32);</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T4" oneof="5" id="iclass_t4" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T4" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="B" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/B/T4_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="25" width="10" name="imm10" usename="1">
          <c colspan="10"></c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" name="J1" usename="1">
          <c></c>
        </box>
        <box hibit="12" settings="1">
          <c>1</c>
        </box>
        <box hibit="11" name="J2" usename="1">
          <c></c>
        </box>
        <box hibit="10" width="11" name="imm11" usename="1">
          <c colspan="11"></c>
        </box>
      </regdiagram>
      <encoding name="B_T4" oneofinclass="1" oneof="5" label="T4">
        <docvars>
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="B" />
        </docvars>
        <asmtemplate comment="&lt;label&gt; can be represented in T2"><text>B</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_label_3" hover="The label of instruction that is to be branched to">&lt;label&gt;</a></asmtemplate>
        <asmtemplate><text>B</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_label_3" hover="The label of instruction that is to be branched to">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/B/T4_A.txt" mylink="aarch32.instrs.B.T4_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>I1 = NOT(J1 EOR S);  I2 = NOT(J2 EOR S);  imm32 = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(S:I1:I2:imm10:imm11:'0', 32);</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="B_A1, B_T2, B_T4" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For encoding A1, T2 and T4: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="B_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. Must not be <value>AL</value> or omitted.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="B_T3" symboldefcount="3">
      <symbol link="sa_c_2">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. <syntax>&lt;c&gt;</syntax> must not be <value>AL</value> or omitted.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="B_A1, B_T1, B_T2, B_T3, B_T4" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="B_A1" symboldefcount="1">
      <symbol link="sa_label_4">&lt;label&gt;</symbol>
      <account encodedin="imm24">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the <instruction>B</instruction> instruction to this label, then selects an encoding that sets <field>imm32</field> to that offset.</para>
          <para>Permitted offsets are multiples of 4 in the range –33554432 to 33554428.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="B_T1" symboldefcount="2">
      <symbol link="sa_label">&lt;label&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the <instruction>B</instruction> instruction to this label, then selects an encoding that sets <field>imm32</field> to that offset. Permitted offsets are even numbers in the range –256 to 254.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="B_T2" symboldefcount="3">
      <symbol link="sa_label_1">&lt;label&gt;</symbol>
      <account encodedin="imm11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the <instruction>B</instruction> instruction to this label, then selects an encoding that sets <field>imm32</field> to that offset. Permitted offsets are even numbers in the range –2048 to 2046.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="B_T3" symboldefcount="4">
      <symbol link="sa_label_2">&lt;label&gt;</symbol>
      <account encodedin="S:J2:J1:imm6:imm11">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the <instruction>B</instruction> instruction to this label, then selects an encoding that sets <field>imm32</field> to that offset.</para>
          <para>Permitted offsets are even numbers in the range –1048576 to 1048574.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="B_T4" symboldefcount="5">
      <symbol link="sa_label_3">&lt;label&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T4" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T4: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the <instruction>B</instruction> instruction to this label, then selects an encoding that sets <field>imm32</field> to that offset.</para>
          <para>Permitted offsets are even numbers in the range –16777216 to 16777214.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/B/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.BranchWritePC.2" file="shared_pseudocode.xml" hover="function: BranchWritePC(bits(32) address_in, BranchType branch_type)">BranchWritePC</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a> + imm32, <a link="BranchType_DIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</a>);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="bfc.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="BFC" title="BFC -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="BFC" />
  </docvars>
  <heading>BFC</heading>
  <desc>
    <brief>
      <para>Bit Field Clear</para>
    </brief>
    <authored>
      <para>Bit Field Clear clears any number of adjacent bits at any position in a register, without affecting the other bits in the register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="BFC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/BFC/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="7" settings="7">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="msb" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="lsb" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="BFC_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BFC" />
        </docvars>
        <asmtemplate><text>BFC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_lsb_1" hover="Least significant bit to be cleared [0-31] (field &quot;lsb&quot;)">&lt;lsb&gt;</a><text>, #</text><a link="sa_width" hover="Number of bits to be cleared [1-32-&lt;lsb&gt;] (field &quot;msb&quot;)">&lt;width&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BFC/A1_A.txt" mylink="aarch32.instrs.BFC.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  msbit = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(msb);  lsbit = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(lsb);</line>
<line>if d == 15 then UNPREDICTABLE;</line>
<line>if msbit &lt; lsbit then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>msbit &lt; lsbit</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="BFC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/BFC/T1_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" width="2" name="op1&lt;2:1&gt;" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="21" name="op1&lt;0&gt;" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" width="5" name="msb" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="BFC_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BFC" />
        </docvars>
        <asmtemplate><text>BFC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_lsb" hover="Least significant bit that is to be cleared [0-31] (field &quot;imm3:imm2&quot;)">&lt;lsb&gt;</a><text>, #</text><a link="sa_width" hover="Number of bits to be cleared [1-32-&lt;lsb&gt;] (field &quot;msb&quot;)">&lt;width&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BFC/T1_A.txt" mylink="aarch32.instrs.BFC.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  msbit = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(msb);  lsbit = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm3:imm2);</line>
<line>if d == 15 then UNPREDICTABLE;  // Armv8-A removes UNPREDICTABLE for R13</line>
<line>if msbit &lt; lsbit then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>msbit &lt; lsbit</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="BFC_A1, BFC_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BFC_A1, BFC_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BFC_A1, BFC_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BFC_A1" symboldefcount="1">
      <symbol link="sa_lsb_1">&lt;lsb&gt;</symbol>
      <account encodedin="lsb">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the least significant bit to be cleared, in the range 0 to 31, encoded in the "lsb" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BFC_T1" symboldefcount="2">
      <symbol link="sa_lsb">&lt;lsb&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the least significant bit that is to be cleared, in the range 0 to 31, encoded in the "imm3:imm2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BFC_A1, BFC_T1" symboldefcount="1">
      <symbol link="sa_width">&lt;width&gt;</symbol>
      <account encodedin="msb">
        <intro>
          <para>Is the number of bits to be cleared, in the range 1 to 32-&lt;lsb&gt;, encoded in the "msb" field as &lt;lsb&gt;+&lt;width&gt;-1.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/BFC/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;msbit:lsbit&gt; = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>('0', (msbit-lsbit)+1);</line>
<line>    // Other bits of R[d] are unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="bfi.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="BFI" title="BFI -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="BFI" />
  </docvars>
  <heading>BFI</heading>
  <desc>
    <brief>
      <para>Bit Field Insert</para>
    </brief>
    <authored>
      <para>Bit Field Insert copies any number of low order bits from a register into the same number of adjacent bits at any position in the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="BFI" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/BFI/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="7" settings="7">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="msb" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="lsb" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
      </regdiagram>
      <encoding name="BFI_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BFI" />
        </docvars>
        <asmtemplate><text>BFI</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_lsb_1" hover="Least significant destination bit [0-31] (field &quot;lsb&quot;)">&lt;lsb&gt;</a><text>, #</text><a link="sa_width" hover="Number of bits to be copied [1-32-&lt;lsb&gt;] (field &quot;msb&quot;)">&lt;width&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BFI/A1_A.txt" mylink="aarch32.instrs.BFI.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "BFC";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  msbit = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(msb);  lsbit = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(lsb);</line>
<line>if d == 15 then UNPREDICTABLE;</line>
<line>if msbit &lt; lsbit then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>msbit &lt; lsbit</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="BFI" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/BFI/T1_A.txt" tworows="1">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" width="2" name="op1&lt;2:1&gt;" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="21" name="op1&lt;0&gt;" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" width="5" name="msb" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="BFI_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BFI" />
        </docvars>
        <asmtemplate><text>BFI</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_lsb" hover="Least significant destination bit [0-31] (field &quot;imm3:imm2&quot;)">&lt;lsb&gt;</a><text>, #</text><a link="sa_width" hover="Number of bits to be copied [1-32-&lt;lsb&gt;] (field &quot;msb&quot;)">&lt;width&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BFI/T1_A.txt" mylink="aarch32.instrs.BFI.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "BFC";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  msbit = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(msb);  lsbit = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm3:imm2);</line>
<line>if d == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
<line>if msbit &lt; lsbit then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>msbit &lt; lsbit</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="BFI_A1, BFI_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BFI_A1, BFI_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BFI_A1, BFI_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BFI_A1, BFI_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BFI_A1" symboldefcount="1">
      <symbol link="sa_lsb_1">&lt;lsb&gt;</symbol>
      <account encodedin="lsb">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the least significant destination bit, in the range 0 to 31, encoded in the "lsb" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BFI_T1" symboldefcount="2">
      <symbol link="sa_lsb">&lt;lsb&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the least significant destination bit, in the range 0 to 31, encoded in the "imm3:imm2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BFI_A1, BFI_T1" symboldefcount="1">
      <symbol link="sa_width">&lt;width&gt;</symbol>
      <account encodedin="msb">
        <intro>
          <para>Is the number of bits to be copied, in the range 1 to 32-&lt;lsb&gt;, encoded in the "msb" field as &lt;lsb&gt;+&lt;width&gt;-1.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/BFI/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;msbit:lsbit&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;(msbit-lsbit):0&gt;;</line>
<line>    // Other bits of R[d] are unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="bic_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="BIC_i" title="BIC, BICS (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>BIC, BICS (immediate)</heading>
  <desc>
    <brief>
      <para>Bitwise Bit Clear (immediate)</para>
    </brief>
    <authored>
      <para>Bitwise Bit Clear (immediate) performs a bitwise AND of a register value and the complement of an immediate value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the BICS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The BIC variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The BICS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/BIC_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="BIC_i_A1" oneofinclass="2" oneof="4" label="BIC" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BIC" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>BIC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="BICS_i_A1" oneofinclass="2" oneof="4" label="BICS" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BICS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>BICS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BIC_i/A1_A.txt" mylink="aarch32.instrs.BIC_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = (S == '1');</line>
<line>(imm32, carry) = <a link="impl-aarch32.A32ExpandImm_C.2" file="shared_pseudocode.xml" hover="function: (bits(32), bit) A32ExpandImm_C(bits(12) imm12, bit carry_in)">A32ExpandImm_C</a>(imm12, PSTATE.C);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/BIC_i/T1_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="BIC_i_T1" oneofinclass="2" oneof="4" label="BIC" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BIC" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>BIC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="BICS_i_T1" oneofinclass="2" oneof="4" label="BICS" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BICS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>BICS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BIC_i/T1_A.txt" mylink="aarch32.instrs.BIC_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = (S == '1');</line>
<line>(imm32, carry) = <a link="impl-aarch32.T32ExpandImm_C.2" file="shared_pseudocode.xml" hover="function: (bits(32), bit) T32ExpandImm_C(bits(12) imm12, bit carry_in)">T32ExpandImm_C</a>(i:imm3:imm8, PSTATE.C);</line>
<line>if d == 15 || n == 15 then UNPREDICTABLE;  // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="BIC_i_A1, BIC_i_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BIC_i_A1, BIC_i_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BIC_i_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the BIC variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the BICS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BIC_i_T1" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BIC_i_A1" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BIC_i_T1" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BIC_i_A1" symboldefcount="1">
      <symbol link="sa_const_1">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: an immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BIC_i_T1" symboldefcount="2">
      <symbol link="sa_const">&lt;const&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: an immediate value. See <xref linkend="BABGHAGA">Modified immediate constants in T32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/BIC_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    result = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] AND NOT(imm32);</line>
<line>    if d == 15 then          // Can only occur for A32 encoding</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.N = result&lt;31&gt;;</line>
<line>            PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>            PSTATE.C = carry;</line>
<line>            // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="bic_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="BIC_r" title="BIC, BICS (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>BIC, BICS (register)</heading>
  <desc>
    <brief>
      <para>Bitwise Bit Clear (register)</para>
    </brief>
    <authored>
      <para>Bitwise Bit Clear (register) performs a bitwise AND of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the BICS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The BIC variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The BICS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/BIC_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="BIC_r_A1_RRX" oneofinclass="4" oneof="9" label="BIC, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BIC" />
          <docvar key="mnemonic-shift-type" value="BIC-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>BIC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="BIC_r_A1" oneofinclass="4" oneof="9" label="BIC, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BIC" />
          <docvar key="mnemonic-shift-type" value="BIC-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>BIC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="BICS_r_A1_RRX" oneofinclass="4" oneof="9" label="BICS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BICS" />
          <docvar key="mnemonic-shift-type" value="BICS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>BICS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="BICS_r_A1" oneofinclass="4" oneof="9" label="BICS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BICS" />
          <docvar key="mnemonic-shift-type" value="BICS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>BICS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BIC_r/A1_A.txt" mylink="aarch32.instrs.BIC_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="BIC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/BIC_r/T1_A.txt">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="4" name="op" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rdn" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="BIC_r_T1" oneofinclass="1" oneof="9" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BIC" />
        </docvars>
        <asmtemplate comment="Inside IT block"><text>BIC</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate comment="Outside IT block"><text>BICS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BIC_r/T1_A.txt" mylink="aarch32.instrs.BIC_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdn);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>();</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/BIC_r/T2_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="BIC_r_T2_RRX" oneofinclass="4" oneof="9" label="BIC, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BIC" />
          <docvar key="mnemonic-shift-type" value="BIC-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>BIC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="BIC_r_T2" oneofinclass="4" oneof="9" label="BIC, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BIC" />
          <docvar key="mnemonic-shift-type" value="BIC-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Inside IT block, and &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>BIC</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>BIC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="BICS_r_T2_RRX" oneofinclass="4" oneof="9" label="BICS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BICS" />
          <docvar key="mnemonic-shift-type" value="BICS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>BICS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="BICS_r_T2" oneofinclass="4" oneof="9" label="BICS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BICS" />
          <docvar key="mnemonic-shift-type" value="BICS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Outside IT block, and &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>BICS.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>BICS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BIC_r/T2_A.txt" mylink="aarch32.instrs.BIC_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm3:imm2);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;  // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="BIC_r_A1, BIC_r_T1, BIC_r_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BIC_r_A1, BIC_r_T1, BIC_r_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BIC_r_T1" symboldefcount="1">
      <symbol link="sa_rdn">&lt;Rdn&gt;</symbol>
      <account encodedin="Rdn">
        <intro>
          <para>Is the first general-purpose source register and the destination register, encoded in the "Rdn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BIC_r_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the BIC variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the BICS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BIC_r_T2" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BIC_r_A1" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BIC_r_T2" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BIC_r_A1" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="BIC-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BIC_r_T1, BIC_r_T2" symboldefcount="2">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BIC_r_A1, BIC_r_T2" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="BIC_r_A1" symboldefcount="1">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BIC_r_T2" symboldefcount="2">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm3:imm2" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/BIC_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    (shifted, carry) = <a link="impl-aarch32.Shift_C.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift_C</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    result = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] AND NOT(shifted);</line>
<line>    if d == 15 then          // Can only occur for A32 encoding</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.N = result&lt;31&gt;;</line>
<line>            PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>            PSTATE.C = carry;</line>
<line>            // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="bic_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="BIC_rr" title="BIC, BICS (register-shifted register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
  </docvars>
  <heading>BIC, BICS (register-shifted register)</heading>
  <desc>
    <brief>
      <para>Bitwise Bit Clear (register-shifted register)</para>
    </brief>
    <authored>
      <para>Bitwise Bit Clear (register-shifted register) performs a bitwise AND of a register value and the complement of a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/BIC_rr/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="BICS_rr_A1" oneofinclass="2" oneof="2" label="Flag setting" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BICS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>BICS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <encoding name="BIC_rr_A1" oneofinclass="2" oneof="2" label="Not flag setting" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BIC" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>BIC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BIC_rr/A1_A.txt" mylink="aarch32.instrs.BIC_rr.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);</line>
<line>setflags = (S == '1');  shift_t = <a link="impl-aarch32.DecodeRegShift.1" file="shared_pseudocode.xml" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</a>(stype);</line>
<line>if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="BIC_rr_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BIC_rr_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BIC_rr_A1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BIC_rr_A1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BIC_rr_A1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BIC_rr_A1" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="BIC_rr_A1" symboldefcount="1">
      <symbol link="sa_rs">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/BIC_rr/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shift_n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[s]&lt;7:0&gt;);</line>
<line>    (shifted, carry) = <a link="impl-aarch32.Shift_C.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift_C</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    result = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] AND NOT(shifted);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>    if setflags then</line>
<line>        PSTATE.N = result&lt;31&gt;;</line>
<line>        PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>        PSTATE.C = carry;</line>
<line>        // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="bkpt.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="BKPT" title="BKPT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="BKPT" />
  </docvars>
  <heading>BKPT</heading>
  <desc>
    <brief>
      <para>Breakpoint</para>
    </brief>
    <authored>
      <para>Breakpoint causes a Breakpoint Instruction exception.</para>
      <para>Breakpoint is always unconditional, even when inside an IT block.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="BKPT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/BKPT/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="BKPT_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BKPT" />
        </docvars>
        <asmtemplate><text>BKPT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a>{#}</a><a link="sa_imm_1" hover="16-bit unsigned immediate [0-65535] (field &quot;imm12:imm4&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BKPT/A1_A.txt" mylink="aarch32.instrs.BKPT.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>imm16 = imm12:imm4;</line>
<line>if cond != '1110' then UNPREDICTABLE;  // BKPT must be encoded with AL condition</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNCOND" />
          <cu_type constraint="Constraint_COND" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="BKPT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/BKPT/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="BKPT_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BKPT" />
        </docvars>
        <asmtemplate><text>BKPT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a>{#}</a><a link="sa_imm" hover="8-bit unsigned immediate [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BKPT/T1_A.txt" mylink="aarch32.instrs.BKPT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>imm16 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 16);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="BKPT_A1, BKPT_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. A <instruction>BKPT</instruction> instruction must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BKPT_A1" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm12:imm4">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm12:imm4" field. This value:</para>
          <list type="unordered">
            <listitem><content>Is recorded in the Comment field of ESR_ELx.ISS if the Software Breakpoint Instruction exception is taken to an exception level that is using AArch64.</content></listitem>
            <listitem><content>Is ignored otherwise.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BKPT_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is a 8-bit unsigned immediate, in the range 0 to 255, encoded in the "imm8" field. This value:</para>
          <list type="unordered">
            <listitem><content>Is recorded in the Comment field of ESR_ELx.ISS if the Software Breakpoint Instruction exception is taken to an exception level that is using AArch64.</content></listitem>
            <listitem><content>Is ignored otherwise.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/BKPT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations();</line>
<line><a link="AArch32.SoftwareBreakpoint.1" file="shared_pseudocode.xml" hover="function: AArch32.SoftwareBreakpoint(bits(16) immediate)">AArch32.SoftwareBreakpoint</a>(imm16);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="bl_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="BL_i" title="BL, BLX (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>BL, BLX (immediate)</heading>
  <desc>
    <brief>
      <para>Branch with Link and optional Exchange (immediate)</para>
    </brief>
    <authored>
      <para>Branch with Link calls a subroutine at a PC-relative address, and setting LR to the return address.</para>
      <para>Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine at a PC-relative address, setting LR to the return address, and changes the instruction set from A32 to T32, or from T32 to A32.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="BL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/BL_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="H" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" width="24" name="imm24" usename="1">
          <c colspan="24"></c>
        </box>
      </regdiagram>
      <encoding name="BL_i_A1" oneofinclass="1" oneof="4" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BL" />
        </docvars>
        <asmtemplate><text>BL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_label_2" hover="The label of instruction that is to be branched to">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BL_i/A1_A.txt" mylink="aarch32.instrs.BL_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>imm32 = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm24:'00', 32);  targetInstrSet = <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="BLX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/BL_i/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="H" usename="1">
          <c></c>
        </box>
        <box hibit="23" width="24" name="imm24" usename="1">
          <c colspan="24"></c>
        </box>
      </regdiagram>
      <encoding name="BL_i_A2" oneofinclass="1" oneof="4" label="A2">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BLX" />
        </docvars>
        <asmtemplate><text>BLX</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_label_3" hover="The label of instruction that is to be branched to">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BL_i/A2_A.txt" mylink="aarch32.instrs.BL_i.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>imm32 = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm24:H:'0', 32);  targetInstrSet = <a link="InstrSet_T32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_T32</a>;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="BL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/BL_i/T1_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="25" width="10" name="imm10" usename="1">
          <c colspan="10"></c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="13" name="J1" usename="1">
          <c></c>
        </box>
        <box hibit="12" settings="1">
          <c>1</c>
        </box>
        <box hibit="11" name="J2" usename="1">
          <c></c>
        </box>
        <box hibit="10" width="11" name="imm11" usename="1">
          <c colspan="11"></c>
        </box>
      </regdiagram>
      <encoding name="BL_i_T1" oneofinclass="1" oneof="4" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BL" />
        </docvars>
        <asmtemplate><text>BL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_label" hover="The label of instruction that is to be branched to">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BL_i/T1_A.txt" mylink="aarch32.instrs.BL_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>I1 = NOT(J1 EOR S);  I2 = NOT(J2 EOR S);  imm32 = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(S:I1:I2:imm10:imm11:'0', 32);</line>
<line>targetInstrSet = <a link="InstrSet_T32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_T32</a>;</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="BLX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/BL_i/T2_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="25" width="10" name="imm10H" usename="1">
          <c colspan="10"></c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="13" name="J1" usename="1">
          <c></c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" name="J2" usename="1">
          <c></c>
        </box>
        <box hibit="10" width="10" name="imm10L" usename="1">
          <c colspan="10"></c>
        </box>
        <box hibit="0" name="H" usename="1">
          <c></c>
        </box>
      </regdiagram>
      <encoding name="BL_i_T2" oneofinclass="1" oneof="4" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BLX" />
        </docvars>
        <asmtemplate><text>BLX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_label_1" hover="The label of instruction that is to be branched to">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BL_i/T2_A.txt" mylink="aarch32.instrs.BL_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if H == '1' then UNDEFINED;</line>
<line>I1 = NOT(J1 EOR S);  I2 = NOT(J2 EOR S);  imm32 = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(S:I1:I2:imm10H:imm10L:'00', 32);</line>
<line>targetInstrSet = <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>;</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="BL_i_A1, BL_i_T1, BL_i_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For encoding A1, T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BL_i_A2" symboldefcount="2">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BLX" />
        </docvars>
        <intro>
          <para>For encoding A2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. <syntax>&lt;c&gt;</syntax> must be <value>AL</value> or omitted.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BL_i_A1, BL_i_A2, BL_i_T1, BL_i_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BL_i_A1" symboldefcount="1">
      <symbol link="sa_label_2">&lt;label&gt;</symbol>
      <account encodedin="imm24">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BL" />
        </docvars>
        <intro>
          <para>For encoding A1: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the <instruction>BL</instruction> instruction to this label, then selects an encoding that sets <field>imm32</field> to that offset.</para>
          <para>Permitted offsets are multiples of 4 in the range –33554432 to 33554428.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BL_i_A2" symboldefcount="2">
      <symbol link="sa_label_3">&lt;label&gt;</symbol>
      <account encodedin="imm24:H">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BLX" />
        </docvars>
        <intro>
          <para>For encoding A2: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the <instruction>BLX</instruction> instruction to this label, then selects an encoding with <field>imm32</field> set to that offset.</para>
          <para>Permitted offsets are even numbers in the range –33554432 to 33554430.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BL_i_T1" symboldefcount="3">
      <symbol link="sa_label">&lt;label&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BL" />
        </docvars>
        <intro>
          <para>For encoding T1: the label of the instruction that is to be branched to.</para>
          <para>The assembler calculates the required value of the offset from the PC value of the <instruction>BL</instruction> instruction to this label, then selects an encoding with <field>imm32</field> set to that offset.</para>
          <para>Permitted offsets are even numbers in the range –16777216 to 16777214.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BL_i_T2" symboldefcount="4">
      <symbol link="sa_label_1">&lt;label&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BLX" />
        </docvars>
        <intro>
          <para>For encoding T2: the label of the instruction that is to be branched to.</para>
          <para>The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the <instruction>BLX</instruction> instruction to this label, then selects an encoding with <field>imm32</field> set to that offset.</para>
          <para>Permitted offsets are multiples of 4 in the range –16777216 to 16777212.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/BL_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then</line>
<line>        <a link="impl-aarch32.LR.write.none" file="shared_pseudocode.xml" hover="accessor: LR = bits(32) value">LR</a> = <a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a> - 4;</line>
<line>    else</line>
<line>        <a link="impl-aarch32.LR.write.none" file="shared_pseudocode.xml" hover="accessor: LR = bits(32) value">LR</a> = <a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>&lt;31:1&gt; : '1';</line>
<line>    bits(32) targetAddress;</line>
<line>    if targetInstrSet == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then</line>
<line>        targetAddress = <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4) + imm32;</line>
<line>    else</line>
<line>        targetAddress = <a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a> + imm32;</line>
<line>    <a link="impl-aarch32.SelectInstrSet.1" file="shared_pseudocode.xml" hover="function: SelectInstrSet(InstrSet iset)">SelectInstrSet</a>(targetInstrSet);</line>
<line>    <a link="impl-aarch32.BranchWritePC.2" file="shared_pseudocode.xml" hover="function: BranchWritePC(bits(32) address_in, BranchType branch_type)">BranchWritePC</a>(targetAddress, <a link="BranchType_DIRCALL" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIRCALL</a>);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="blx_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="BLX_r" title="BLX (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="BLX" />
  </docvars>
  <heading>BLX (register)</heading>
  <desc>
    <brief>
      <para>Branch with Link and Exchange (register)</para>
    </brief>
    <authored>
      <para>Branch with Link and Exchange (register) calls a subroutine at an address specified in the register, and if necessary changes to the instruction set indicated by bit[0] of the register value. If the value in bit[0] is 0, the instruction set after the branch will be A32. If the value in bit[0] is 1, the instruction set after the branch will be T32.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="BLX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/BLX_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="8" settings="8">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="BLX_r_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BLX" />
        </docvars>
        <asmtemplate><text>BLX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rm" hover="General-purpose register holding address to be branched to (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BLX_r/A1_A.txt" mylink="aarch32.instrs.BLX_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="BLX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/BLX_r/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="18" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="BLX_r_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BLX" />
        </docvars>
        <asmtemplate><text>BLX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rm" hover="General-purpose register holding address to be branched to (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BLX_r/T1_A.txt" mylink="aarch32.instrs.BLX_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if m == 15 then UNPREDICTABLE;</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="BLX_r_A1, BLX_r_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BLX_r_A1, BLX_r_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BLX_r_A1, BLX_r_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose register holding the address to be branched to, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/BLX_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    target = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>    bits(32) next_instr_addr;</line>
<line>    if <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then</line>
<line>        next_instr_addr = <a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a> - 4;</line>
<line>        <a link="impl-aarch32.LR.write.none" file="shared_pseudocode.xml" hover="accessor: LR = bits(32) value">LR</a> = next_instr_addr;</line>
<line>    else</line>
<line>        next_instr_addr = <a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a> - 2;</line>
<line>        <a link="impl-aarch32.LR.write.none" file="shared_pseudocode.xml" hover="accessor: LR = bits(32) value">LR</a> = next_instr_addr&lt;31:1&gt; : '1';</line>
<line>    <a link="impl-aarch32.BXWritePC.2" file="shared_pseudocode.xml" hover="function: BXWritePC(bits(32) address_in, BranchType branch_type)">BXWritePC</a>(target, <a link="BranchType_INDCALL" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDCALL</a>);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="bx.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="BX" title="BX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="BX" />
  </docvars>
  <heading>BX</heading>
  <desc>
    <brief>
      <para>Branch and Exchange</para>
    </brief>
    <authored>
      <para>Branch and Exchange causes a branch to an address and instruction set specified by a register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="BX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/BX/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="8" settings="8">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="BX_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BX" />
        </docvars>
        <asmtemplate><text>BX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose register holding address to be branched to (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BX/A1_A.txt" mylink="aarch32.instrs.BX.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="BX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/BX/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="18" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="BX_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BX" />
        </docvars>
        <asmtemplate><text>BX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rm" hover="General-purpose register holding address to be branched to (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BX/T1_A.txt" mylink="aarch32.instrs.BX.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="BX_A1, BX_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BX_A1, BX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BX_A1" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose register holding the address to be branched to, encoded in the "Rm" field. The PC can be used.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BX_T1" symboldefcount="2">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose register holding the address to be branched to, encoded in the "Rm" field. The PC can be used.</para>
          <note>
            <para>If <syntax>&lt;Rm&gt;</syntax> is the PC at a non word-aligned address, it results in <arm-defined-word>unpredictable</arm-defined-word> behavior because the address passed to the <function>BXWritePC()</function> pseudocode function has bits&lt;1:0&gt; = '10'.</para>
          </note>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/BX/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.BXWritePC.2" file="shared_pseudocode.xml" hover="function: BXWritePC(bits(32) address_in, BranchType branch_type)">BXWritePC</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], <a link="BranchType_INDIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDIR</a>);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="bxj.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="BXJ" title="BXJ -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="BXJ" />
  </docvars>
  <heading>BXJ</heading>
  <desc>
    <brief>
      <para>Branch and Exchange, previously Branch and Exchange Jazelle</para>
    </brief>
    <authored>
      <para>Branch and Exchange, previously Branch and Exchange Jazelle.</para>
      <para><instruction>BXJ</instruction> behaves as a <instruction>BX</instruction> instruction, see <xref linkend="A32T32-base.instructions.BX">BX</xref>. This means it causes a branch to an address and instruction set specified by a register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="BXJ" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/BXJ/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="8" settings="8">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="BXJ_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BXJ" />
        </docvars>
        <asmtemplate><text>BXJ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rm" hover="General-purpose register holding address to be branched to (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BXJ/A1_A.txt" mylink="aarch32.instrs.BXJ.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="BXJ" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/BXJ/T1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="BXJ_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BXJ" />
        </docvars>
        <asmtemplate><text>BXJ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rm" hover="General-purpose register holding address to be branched to (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BXJ/T1_A.txt" mylink="aarch32.instrs.BXJ.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if m == 15 then UNPREDICTABLE;  // Armv8-A removes UNPREDICTABLE for R13</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="BXJ_A1, BXJ_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BXJ_A1, BXJ_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BXJ_A1, BXJ_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose register holding the address to be branched to, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/BXJ/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.BXWritePC.2" file="shared_pseudocode.xml" hover="function: BXWritePC(bits(32) address_in, BranchType branch_type)">BXWritePC</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], <a link="BranchType_INDIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDIR</a>);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="cbnz.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="CBNZ" title="CBNZ, CBZ -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="T1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="T32" />
  </docvars>
  <heading>CBNZ, CBZ</heading>
  <desc>
    <brief>
      <para>Compare and Branch on Nonzero or Zero</para>
    </brief>
    <authored>
      <para>Compare and Branch on Nonzero and Compare and Branch on Zero compare the value in a register with zero, and conditionally branch forward a constant value. They do not affect the condition flags.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="T1" oneof="1" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/CBNZ/T1_A.txt">
        <box hibit="31" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="27" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="26" settings="1">
          <c>0</c>
        </box>
        <box hibit="25" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="24" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="18" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="CBNZ_T1" oneofinclass="2" oneof="2" label="CBNZ" bitdiffs="op == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CBNZ" />
        </docvars>
        <box hibit="27" width="1" name="op">
          <c>1</c>
        </box>
        <asmtemplate><text>CBNZ</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose register to be tested (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_label" hover="Label to be conditionally branched to">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CBZ_T1" oneofinclass="2" oneof="2" label="CBZ" bitdiffs="op == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CBZ" />
        </docvars>
        <box hibit="27" width="1" name="op">
          <c>0</c>
        </box>
        <asmtemplate><text>CBZ</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose register to be tested (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_label" hover="Label to be conditionally branched to">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CBNZ/T1_A.txt" mylink="aarch32.instrs.CBNZ.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(i:imm5:'0', 32);  nonzero = (op == '1');</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="CBNZ_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CBNZ_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose register to be tested, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CBNZ_T1" symboldefcount="1">
      <symbol link="sa_label">&lt;label&gt;</symbol>
      <account encodedin="i:imm5">
        <intro>
          <para>Is the program label to be conditionally branched to. Its offset from the PC, a multiple of 2 and in the range 0 to 126, is encoded as "i:imm5" times 2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/CBNZ/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations();</line>
<line>if nonzero != <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]) then</line>
<line>    <a link="impl-aarch32.CBWritePC.1" file="shared_pseudocode.xml" hover="function: CBWritePC(bits(32) address_in)">CBWritePC</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a> + imm32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="clrbhb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="CLRBHB" title="CLRBHB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="CLRBHB" />
  </docvars>
  <heading>CLRBHB</heading>
  <desc>
    <brief>
      <para>Clear Branch History</para>
    </brief>
    <authored>
      <para>Clear Branch History clears the branch history for the current context to the extent that branch history information created before the <instruction>CLRBHB</instruction> instruction cannot be used by code before the <instruction>CLRBHB</instruction> instruction to exploitatively control the execution of any indirect branches in code in the current context that appear in program order after the instruction.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="CLRBHB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.9" feature="FEAT_CLRBHB" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/CLRBHB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="R" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="imm4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" width="12" name="imm12" settings="12">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="CLRBHB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CLRBHB" />
        </docvars>
        <asmtemplate><text>CLRBHB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CLRBHB/A1_A.txt" mylink="aarch32.instrs.CLRBHB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveFeatCLRBHB.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatCLRBHB()">HaveFeatCLRBHB</a>() then <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();   // Instruction executes as NOP</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="CLRBHB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.9" feature="FEAT_CLRBHB" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/CLRBHB/T1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="hint" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="option" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="CLRBHB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CLRBHB" />
        </docvars>
        <asmtemplate><text>CLRBHB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CLRBHB/T1_A.txt" mylink="aarch32.instrs.CLRBHB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveFeatCLRBHB.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatCLRBHB()">HaveFeatCLRBHB</a>() then <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();   // Instruction executes as NOP</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="CLRBHB_A1, CLRBHB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CLRBHB_A1, CLRBHB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/CLRBHB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-shared.Hint_CLRBHB.0" file="shared_pseudocode.xml" hover="function: Hint_CLRBHB()">Hint_CLRBHB</a>();</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="clrex.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="CLREX" title="CLREX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="CLREX" />
  </docvars>
  <heading>CLREX</heading>
  <desc>
    <brief>
      <para>Clear-Exclusive</para>
    </brief>
    <authored>
      <para>Clear-Exclusive clears the local monitor of the executing PE.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="CLREX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/CLREX/A1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" name="opcode" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="option" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="CLREX_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CLREX" />
        </docvars>
        <asmtemplate><text>CLREX</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CLREX/A1_A.txt" mylink="aarch32.instrs.CLREX.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="CLREX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/CLREX/T1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="option" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="CLREX_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CLREX" />
        </docvars>
        <asmtemplate><text>CLREX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CLREX/T1_A.txt" mylink="aarch32.instrs.CLREX.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="CLREX_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. Must be <value>AL</value> or omitted.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CLREX_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CLREX_A1, CLREX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/CLREX/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-shared.ClearExclusiveLocal.1" file="shared_pseudocode.xml" hover="function: ClearExclusiveLocal(integer processorid)">ClearExclusiveLocal</a>(<a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>());</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="clz.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="CLZ" title="CLZ -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="CLZ" />
  </docvars>
  <heading>CLZ</heading>
  <desc>
    <brief>
      <para>Count Leading Zeros</para>
    </brief>
    <authored>
      <para>Count Leading Zeros returns the number of binary zero bits before the first binary one bit in a value.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="CLZ" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/CLZ/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="8" settings="8">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="CLZ_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CLZ" />
        </docvars>
        <asmtemplate><text>CLZ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CLZ/A1_A.txt" mylink="aarch32.instrs.CLZ.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="CLZ" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/CLZ/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="CLZ_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CLZ" />
        </docvars>
        <asmtemplate><text>CLZ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CLZ/T1_A.txt" mylink="aarch32.instrs.CLZ.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if m != n || d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>m != n</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_NONE" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="m = UInt(Rn);" />
          </cu_type>
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="CLZ_A1, CLZ_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CLZ_A1, CLZ_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CLZ_A1, CLZ_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CLZ_A1" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CLZ_T1" symboldefcount="2">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose source register, encoded in the "Rm" field. It must be encoded with an identical value in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/CLZ/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    result = <a link="impl-shared.CountLeadingZeroBits.1" file="shared_pseudocode.xml" hover="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result&lt;31:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="cmn_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="CMN_i" title="CMN (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="CMN" />
  </docvars>
  <heading>CMN (immediate)</heading>
  <desc>
    <brief>
      <para>Compare Negative (immediate)</para>
    </brief>
    <authored>
      <para>Compare Negative (immediate) adds a register value and an immediate value. It updates the condition flags based on the result, and discards the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="CMN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/CMN_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="CMN_i_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CMN" />
        </docvars>
        <asmtemplate><text>CMN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CMN_i/A1_A.txt" mylink="aarch32.instrs.CMN_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-aarch32.A32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) A32ExpandImm(bits(12) imm12)">A32ExpandImm</a>(imm12);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="CMN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/CMN_i/T1_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="CMN_i_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CMN" />
        </docvars>
        <asmtemplate><text>CMN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CMN_i/T1_A.txt" mylink="aarch32.instrs.CMN_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-aarch32.T32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) T32ExpandImm(bits(12) imm12)">T32ExpandImm</a>(i:imm3:imm8);</line>
<line>if n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="CMN_i_A1, CMN_i_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMN_i_A1, CMN_i_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMN_i_A1" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMN_i_T1" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMN_i_A1" symboldefcount="1">
      <symbol link="sa_const_1">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: an immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMN_i_T1" symboldefcount="2">
      <symbol link="sa_const">&lt;const&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: an immediate value. See <xref linkend="BABGHAGA">Modified immediate constants in T32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/CMN_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], imm32, '0');</line>
<line>    PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="cmn_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="CMN_r" title="CMN (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="CMN" />
  </docvars>
  <heading>CMN (register)</heading>
  <desc>
    <brief>
      <para>Compare Negative (register)</para>
    </brief>
    <authored>
      <para>Compare Negative (register) adds a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="CMN" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/CMN_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="CMN_r_A1_RRX" oneofinclass="2" oneof="5" label="Rotate right with extend" bitdiffs="imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CMN" />
          <docvar key="mnemonic-shift-type" value="CMN-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>CMN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="CMN_r_A1" oneofinclass="2" oneof="5" label="Shift or rotate by value" bitdiffs="!(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CMN" />
          <docvar key="mnemonic-shift-type" value="CMN-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>CMN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CMN_r/A1_A.txt" mylink="aarch32.instrs.CMN_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="CMN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/CMN_r/T1_A.txt">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="4" name="op" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="CMN_r_T1" oneofinclass="1" oneof="5" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CMN" />
        </docvars>
        <asmtemplate><text>CMN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CMN_r/T1_A.txt" mylink="aarch32.instrs.CMN_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="CMN" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/CMN_r/T2_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="CMN_r_T2_RRX" oneofinclass="2" oneof="5" label="Rotate right with extend" bitdiffs="imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CMN" />
          <docvar key="mnemonic-shift-type" value="CMN-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>CMN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="CMN_r_T2" oneofinclass="2" oneof="5" label="Shift or rotate by value" bitdiffs="!(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CMN" />
          <docvar key="mnemonic-shift-type" value="CMN-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="&lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>CMN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>CMN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CMN_r/T2_A.txt" mylink="aarch32.instrs.CMN_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm3:imm2);</line>
<line>if n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="CMN_r_A1, CMN_r_T1, CMN_r_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMN_r_A1, CMN_r_T1, CMN_r_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMN_r_A1" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="CMN-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMN_r_T1, CMN_r_T2" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMN_r_A1" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="CMN-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMN_r_T1, CMN_r_T2" symboldefcount="2">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMN_r_A1, CMN_r_T2" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="CMN_r_A1" symboldefcount="1">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMN_r_T2" symboldefcount="2">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm3:imm2" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/CMN_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], shifted, '0');</line>
<line>    PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="cmn_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="CMN_rr" title="CMN (register-shifted register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
    <docvar key="mnemonic" value="CMN" />
  </docvars>
  <heading>CMN (register-shifted register)</heading>
  <desc>
    <brief>
      <para>Compare Negative (register-shifted register)</para>
    </brief>
    <authored>
      <para>Compare Negative (register-shifted register) adds a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="CMN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/CMN_rr/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="CMN_rr_A1" oneofinclass="1" oneof="1" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CMN" />
        </docvars>
        <asmtemplate><text>CMN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_type" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;type&gt;</a><text> </text><a link="sa_rs" hover="Third general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CMN_rr/A1_A.txt" mylink="aarch32.instrs.CMN_rr.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);</line>
<line>shift_t = <a link="impl-aarch32.DecodeRegShift.1" file="shared_pseudocode.xml" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</a>(stype);</line>
<line>if n == 15 || m == 15 || s == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="CMN_rr_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMN_rr_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMN_rr_A1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMN_rr_A1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMN_rr_A1" symboldefcount="1">
      <symbol link="sa_type">&lt;type&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;type&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="CMN_rr_A1" symboldefcount="1">
      <symbol link="sa_rs">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the third general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/CMN_rr/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shift_n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[s]&lt;7:0&gt;);</line>
<line>    shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], shifted, '0');</line>
<line>    PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="cmp_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="CMP_i" title="CMP (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="CMP" />
  </docvars>
  <heading>CMP (immediate)</heading>
  <desc>
    <brief>
      <para>Compare (immediate)</para>
    </brief>
    <authored>
      <para>Compare (immediate) subtracts an immediate value from a register value. It updates the condition flags based on the result, and discards the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="CMP" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/CMP_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="CMP_i_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CMP" />
        </docvars>
        <asmtemplate><text>CMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn_2" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CMP_i/A1_A.txt" mylink="aarch32.instrs.CMP_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-aarch32.A32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) A32ExpandImm(bits(12) imm12)">A32ExpandImm</a>(imm12);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="CMP" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/CMP_i/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="28" width="2" name="op" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="26" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="23" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="CMP_i_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CMP" />
        </docvars>
        <asmtemplate><text>CMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_imm8" hover="8-bit unsigned immediate [0-255] (field &quot;imm8&quot;)">&lt;imm8&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CMP_i/T1_A.txt" mylink="aarch32.instrs.CMP_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="CMP" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/CMP_i/T2_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="CMP_i_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CMP" />
        </docvars>
        <asmtemplate comment="&lt;Rd&gt;, &lt;const&gt; can be represented in T1"><text>CMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
        <asmtemplate><text>CMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CMP_i/T2_A.txt" mylink="aarch32.instrs.CMP_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-aarch32.T32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) T32ExpandImm(bits(12) imm12)">T32ExpandImm</a>(i:imm3:imm8);</line>
<line>if n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="CMP_i_A1, CMP_i_T1, CMP_i_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMP_i_A1, CMP_i_T1, CMP_i_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMP_i_A1" symboldefcount="1">
      <symbol link="sa_rn_2">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMP_i_T1" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is a general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMP_i_T2" symboldefcount="3">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMP_i_T1" symboldefcount="1">
      <symbol link="sa_imm8">&lt;imm8&gt;</symbol>
      <account encodedin="imm8">
        <intro>
          <para>Is a 8-bit unsigned immediate, in the range 0 to 255, encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMP_i_A1" symboldefcount="1">
      <symbol link="sa_const_1">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: an immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMP_i_T2" symboldefcount="2">
      <symbol link="sa_const">&lt;const&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: an immediate value. See <xref linkend="BABGHAGA">Modified immediate constants in T32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/CMP_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], NOT(imm32), '1');</line>
<line>    PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="cmp_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="CMP_r" title="CMP (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="CMP" />
  </docvars>
  <heading>CMP (register)</heading>
  <desc>
    <brief>
      <para>Compare (register)</para>
    </brief>
    <authored>
      <para>Compare (register) subtracts an optionally-shifted register value from a register value. It updates the condition flags based on the result, and discards the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="CMP" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/CMP_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="CMP_r_A1_RRX" oneofinclass="2" oneof="6" label="Rotate right with extend" bitdiffs="imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CMP" />
          <docvar key="mnemonic-shift-type" value="CMP-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>CMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn_2" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="CMP_r_A1" oneofinclass="2" oneof="6" label="Shift or rotate by value" bitdiffs="!(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CMP" />
          <docvar key="mnemonic-shift-type" value="CMP-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>CMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn_2" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CMP_r/A1_A.txt" mylink="aarch32.instrs.CMP_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="CMP" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/CMP_r/T1_A.txt">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="4" name="op" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="CMP_r_T1" oneofinclass="1" oneof="6" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CMP" />
        </docvars>
        <asmtemplate comment="&lt;Rn&gt; and &lt;Rm&gt; both from R0-R7"><text>CMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CMP_r/T1_A.txt" mylink="aarch32.instrs.CMP_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="CMP" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/CMP_r/T2_A.txt">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="25" width="2" name="op" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="23" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="22" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="18" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="CMP_r_T2" oneofinclass="1" oneof="6" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CMP" />
        </docvars>
        <asmtemplate comment="&lt;Rn&gt; and &lt;Rm&gt; not both from R0-R7"><text>CMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;N:Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CMP_r/T2_A.txt" mylink="aarch32.instrs.CMP_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
<line>if n &lt; 8 &amp;&amp; m &lt; 8 then UNPREDICTABLE;</line>
<line>if n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n &lt; 8 &amp;&amp; m &lt; 8</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_NONE" />
          <cu_type>
            <cu_type_text>The condition flags become <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T3" oneof="4" id="iclass_t3" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="CMP" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/CMP_r/T3_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="CMP_r_T3_RRX" oneofinclass="2" oneof="6" label="Rotate right with extend" bitdiffs="imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CMP" />
          <docvar key="mnemonic-shift-type" value="CMP-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>CMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="CMP_r_T3" oneofinclass="2" oneof="6" label="Shift or rotate by value" bitdiffs="!(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CMP" />
          <docvar key="mnemonic-shift-type" value="CMP-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="&lt;Rn&gt;, &lt;Rm&gt; can be represented in T1 or T2"><text>CMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>CMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CMP_r/T3_A.txt" mylink="aarch32.instrs.CMP_r.T3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm3:imm2);</line>
<line>if n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="CMP_r_A1, CMP_r_T1, CMP_r_T2, CMP_r_T3" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMP_r_A1, CMP_r_T1, CMP_r_T2, CMP_r_T3" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMP_r_A1" symboldefcount="1">
      <symbol link="sa_rn_2">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="CMP-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMP_r_T1, CMP_r_T3" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T3: is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMP_r_T2" symboldefcount="3">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="N:Rn">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the first general-purpose source register, encoded in the "N:Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMP_r_A1" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="CMP-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMP_r_T1, CMP_r_T2, CMP_r_T3" symboldefcount="2">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1, T2 and T3: is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMP_r_A1, CMP_r_T3" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="CMP_r_A1" symboldefcount="1">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMP_r_T3" symboldefcount="2">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm3:imm2" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/CMP_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], NOT(shifted), '1');</line>
<line>    PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="cmp_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="CMP_rr" title="CMP (register-shifted register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
    <docvar key="mnemonic" value="CMP" />
  </docvars>
  <heading>CMP (register-shifted register)</heading>
  <desc>
    <brief>
      <para>Compare (register-shifted register)</para>
    </brief>
    <authored>
      <para>Compare (register-shifted register) subtracts a register-shifted register value from a register value. It updates the condition flags based on the result, and discards the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="CMP" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/CMP_rr/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="CMP_rr_A1" oneofinclass="1" oneof="1" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CMP" />
        </docvars>
        <asmtemplate><text>CMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_type" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;type&gt;</a><text> </text><a link="sa_rs" hover="Third general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CMP_rr/A1_A.txt" mylink="aarch32.instrs.CMP_rr.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);</line>
<line>shift_t = <a link="impl-aarch32.DecodeRegShift.1" file="shared_pseudocode.xml" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</a>(stype);</line>
<line>if n == 15 || m == 15 || s == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="CMP_rr_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMP_rr_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMP_rr_A1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMP_rr_A1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CMP_rr_A1" symboldefcount="1">
      <symbol link="sa_type">&lt;type&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;type&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="CMP_rr_A1" symboldefcount="1">
      <symbol link="sa_rs">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the third general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/CMP_rr/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shift_n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[s]&lt;7:0&gt;);</line>
<line>    shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], NOT(shifted), '1');</line>
<line>    PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="cps.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="CPS" title="CPS, CPSID, CPSIE -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>CPS, CPSID, CPSIE</heading>
  <desc>
    <brief>
      <para>Change PE State</para>
    </brief>
    <authored>
      <para>Change PE State changes one or more of the <xref linkend="BEIDIGBH">PSTATE</xref>.{A, I, F} interrupt mask bits and, optionally, the <xref linkend="BEIDIGBH">PSTATE</xref>.M mode field, without changing any other <xref linkend="BEIDIGBH">PSTATE</xref> bits.</para>
      <para><instruction>CPS</instruction> is treated as <instruction>NOP</instruction> if executed in User mode unless it is defined as being <arm-defined-word>constrained unpredictable</arm-defined-word> elsewhere in this section.</para>
      <para>The PE checks whether the value being written to PSTATE.M is legal. See <xref linkend="CHDDFIGE">Illegal changes to PSTATE.M</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Hint instructions: In encoding T2, if the <field>imod</field> field is <binarynumber>00</binarynumber> and the <field>M</field> bit is <binarynumber>0</binarynumber>, a hint instruction is encoded. To determine which hint instruction, see <xref linkend="T32.encoding_index.bcrtrl">Branches and miscellaneous control</xref>.</para>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="5" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="5"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/CPS/A1_AS.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="2" name="imod" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="16" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" name="E" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" name="A" usename="1">
          <c></c>
        </box>
        <box hibit="7" name="I" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="5" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" width="5" name="mode" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="CPS_A1_AS" oneofinclass="5" oneof="12" label="Change mode" bitdiffs="imod == 00 &amp;&amp; M == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cps-type" value="cps-mode" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CPS" />
        </docvars>
        <box hibit="19" width="2" name="imod">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="17" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>CPS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> #</text><a link="sa_mode" hover="Number of mode to change to [0-31] (field &quot;mode&quot;)">&lt;mode&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CPSID_A1_AS" oneofinclass="5" oneof="12" label="Interrupt disable" bitdiffs="imod == 11 &amp;&amp; M == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cps-type" value="cps-id" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CPSID" />
        </docvars>
        <box hibit="19" width="2" name="imod">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="17" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>CPSID</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_iflags" hover="Sequence of one or more of following, specifying which interrupt mask bits are affected:&#10;$a: Sets the A bit in the instruction, causing the specified effect on {xref{ARMARM_BEIDIGBH}{PSTATE}}">&lt;iflags&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CPSID_A1_ASM" oneofinclass="5" oneof="12" label="Interrupt disable and change mode" bitdiffs="imod == 11 &amp;&amp; M == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cps-type" value="cps-id-mode" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CPSID" />
        </docvars>
        <box hibit="19" width="2" name="imod">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="17" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>CPSID</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_iflags" hover="Sequence of one or more of following, specifying which interrupt mask bits are affected:&#10;$a: Sets the A bit in the instruction, causing the specified effect on {xref{ARMARM_BEIDIGBH}{PSTATE}}">&lt;iflags&gt;</a><text> , #</text><a link="sa_mode" hover="Number of mode to change to [0-31] (field &quot;mode&quot;)">&lt;mode&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CPSIE_A1_AS" oneofinclass="5" oneof="12" label="Interrupt enable" bitdiffs="imod == 10 &amp;&amp; M == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cps-type" value="cps-ie" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CPSIE" />
        </docvars>
        <box hibit="19" width="2" name="imod">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="17" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>CPSIE</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_iflags" hover="Sequence of one or more of following, specifying which interrupt mask bits are affected:&#10;$a: Sets the A bit in the instruction, causing the specified effect on {xref{ARMARM_BEIDIGBH}{PSTATE}}">&lt;iflags&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CPSIE_A1_ASM" oneofinclass="5" oneof="12" label="Interrupt enable and change mode" bitdiffs="imod == 10 &amp;&amp; M == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cps-type" value="cps-ie-mode" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CPSIE" />
        </docvars>
        <box hibit="19" width="2" name="imod">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="17" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>CPSIE</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_iflags" hover="Sequence of one or more of following, specifying which interrupt mask bits are affected:&#10;$a: Sets the A bit in the instruction, causing the specified effect on {xref{ARMARM_BEIDIGBH}{PSTATE}}">&lt;iflags&gt;</a><text> , #</text><a link="sa_mode" hover="Number of mode to change to [0-31] (field &quot;mode&quot;)">&lt;mode&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CPS/A1_AS.txt" mylink="aarch32.instrs.CPS.A1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if mode != '00000' &amp;&amp; M == '0' then UNPREDICTABLE;</line>
<line>if (imod&lt;1&gt; == '1' &amp;&amp; A:I:F == '000') || (imod&lt;1&gt; == '0' &amp;&amp; A:I:F != '000') then UNPREDICTABLE;</line>
<line>enable = (imod == '10');  disable = (imod == '11');  changemode = (M == '1');</line>
<line>affectA = (A == '1');  affectI = (I == '1');  affectF = (F == '1');</line>
<line>if (imod == '00' &amp;&amp; M == '0') || imod == '01' then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>imod == '01'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>imod == '00' &amp;&amp; M == '0'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>mode != '00000' &amp;&amp; M == '0'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="changemode = TRUE" />
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as described, and the value specified by mode is ignored. There are no additional side-effects.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>imod&lt;1&gt; == '1' &amp;&amp; A:I:F == '000'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction behaves as if imod&lt;1&gt; == '0'.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction behaves as if A:I:F has an <arm-defined-word>unknown</arm-defined-word> nonzero value.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>imod&lt;1&gt; == '0' &amp;&amp; A:I:F != '000'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction behaves as if imod&lt;1&gt; == '1'.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction behaves as if A:I:F == '000'.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/CPS/T1_AS.txt">
        <box hibit="31" width="10" settings="10">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="21" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="im" usename="1">
          <c></c>
        </box>
        <box hibit="19" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="18" name="A" usename="1">
          <c></c>
        </box>
        <box hibit="17" name="I" usename="1">
          <c></c>
        </box>
        <box hibit="16" name="F" usename="1">
          <c></c>
        </box>
      </regdiagram>
      <encoding name="CPSID_T1_AS" oneofinclass="2" oneof="12" label="Interrupt disable" bitdiffs="im == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="cps-type" value="cps-id" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CPSID" />
        </docvars>
        <box hibit="20" width="1" name="im">
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>CPSID</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_iflags" hover="Sequence of one or more of following, specifying which interrupt mask bits are affected:&#10;$a: Sets the A bit in the instruction, causing the specified effect on {xref{ARMARM_BEIDIGBH}{PSTATE}}">&lt;iflags&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CPSIE_T1_AS" oneofinclass="2" oneof="12" label="Interrupt enable" bitdiffs="im == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="cps-type" value="cps-ie" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CPSIE" />
        </docvars>
        <box hibit="20" width="1" name="im">
          <c>0</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>CPSIE</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_iflags" hover="Sequence of one or more of following, specifying which interrupt mask bits are affected:&#10;$a: Sets the A bit in the instruction, causing the specified effect on {xref{ARMARM_BEIDIGBH}{PSTATE}}">&lt;iflags&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CPS/T1_AS.txt" mylink="aarch32.instrs.CPS.T1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if A:I:F == '000' then UNPREDICTABLE;</line>
<line>enable = (im == '0');  disable = (im == '1');  changemode = FALSE;</line>
<line>affectA = (A == '1');  affectI = (I == '1');  affectF = (F == '1');</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>A:I:F == '000'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="5" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="5"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/CPS/T2_AS.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" width="2" name="imod" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="8" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="7" name="A" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="I" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="4" width="5" name="mode" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="CPS_T2_AS" oneofinclass="5" oneof="12" label="Change mode" bitdiffs="imod == 00 &amp;&amp; M == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="cps-type" value="cps-mode" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CPS" />
        </docvars>
        <box hibit="10" width="2" name="imod">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>CPS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> #</text><a link="sa_mode" hover="Number of mode to change to [0-31] (field &quot;mode&quot;)">&lt;mode&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CPSID_T2_AS" oneofinclass="5" oneof="12" label="Interrupt disable" bitdiffs="imod == 11 &amp;&amp; M == 0">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="cps-type" value="cps-id" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CPSID" />
        </docvars>
        <box hibit="10" width="2" name="imod">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>CPSID.W </text><a link="sa_iflags" hover="Sequence of one or more of following, specifying which interrupt mask bits are affected:&#10;$a: Sets the A bit in the instruction, causing the specified effect on {xref{ARMARM_BEIDIGBH}{PSTATE}}">&lt;iflags&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CPSID_T2_ASM" oneofinclass="5" oneof="12" label="Interrupt disable and change mode" bitdiffs="imod == 11 &amp;&amp; M == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="cps-type" value="cps-id-mode" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CPSID" />
        </docvars>
        <box hibit="10" width="2" name="imod">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>CPSID</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_iflags" hover="Sequence of one or more of following, specifying which interrupt mask bits are affected:&#10;$a: Sets the A bit in the instruction, causing the specified effect on {xref{ARMARM_BEIDIGBH}{PSTATE}}">&lt;iflags&gt;</a><text>, #</text><a link="sa_mode" hover="Number of mode to change to [0-31] (field &quot;mode&quot;)">&lt;mode&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CPSIE_T2_AS" oneofinclass="5" oneof="12" label="Interrupt enable" bitdiffs="imod == 10 &amp;&amp; M == 0">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="cps-type" value="cps-ie" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CPSIE" />
        </docvars>
        <box hibit="10" width="2" name="imod">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>CPSIE.W </text><a link="sa_iflags" hover="Sequence of one or more of following, specifying which interrupt mask bits are affected:&#10;$a: Sets the A bit in the instruction, causing the specified effect on {xref{ARMARM_BEIDIGBH}{PSTATE}}">&lt;iflags&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CPSIE_T2_ASM" oneofinclass="5" oneof="12" label="Interrupt enable and change mode" bitdiffs="imod == 10 &amp;&amp; M == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="cps-type" value="cps-ie-mode" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CPSIE" />
        </docvars>
        <box hibit="10" width="2" name="imod">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>CPSIE</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_iflags" hover="Sequence of one or more of following, specifying which interrupt mask bits are affected:&#10;$a: Sets the A bit in the instruction, causing the specified effect on {xref{ARMARM_BEIDIGBH}{PSTATE}}">&lt;iflags&gt;</a><text>, #</text><a link="sa_mode" hover="Number of mode to change to [0-31] (field &quot;mode&quot;)">&lt;mode&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CPS/T2_AS.txt" mylink="aarch32.instrs.CPS.T2_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if imod == '00' &amp;&amp; M == '0' then SEE "Hint instructions";</line>
<line>if mode != '00000' &amp;&amp; M == '0' then UNPREDICTABLE;</line>
<line>if (imod&lt;1&gt; == '1' &amp;&amp; A:I:F == '000') || (imod&lt;1&gt; == '0' &amp;&amp; A:I:F != '000') then UNPREDICTABLE;</line>
<line>enable = (imod == '10');  disable = (imod == '11');  changemode = (M == '1');</line>
<line>affectA = (A == '1');  affectI = (I == '1');  affectF = (F == '1');</line>
<line>if imod == '01' || <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>imod == '01'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>mode != '00000' &amp;&amp; M == '0'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="changemode = TRUE" />
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as described, and the value specified by mode is ignored. There are no additional side-effects.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>imod&lt;1&gt; == '1' &amp;&amp; A:I:F == '000'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction behaves as if imod&lt;1&gt; == '0'.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction behaves as if A:I:F has an <arm-defined-word>unknown</arm-defined-word> nonzero value.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>imod&lt;1&gt; == '0' &amp;&amp; A:I:F != '000'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction behaves as if imod&lt;1&gt; == '1'.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction behaves as if A:I:F == '000'.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="CPS_A1_AS, CPSIE_T1_AS, CPS_T2_AS" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CPSIE_A1_AS, CPSIE_T1_AS, CPSIE_T2_AS" symboldefcount="1">
      <symbol link="sa_iflags">&lt;iflags&gt;</symbol>
      <account encodedin="A:I:F">
        <intro>
          <para>Is a sequence of one or more of the following, specifying which interrupt mask bits are affected:</para>
          <list type="param">
            <listitem>
              <param>a</param><content>Sets the A bit in the instruction, causing the specified effect on <xref linkend="BEIDIGBH">PSTATE</xref>.A, the SError interrupt mask bit.</content>
            </listitem>
            <listitem>
              <param>i</param><content>Sets the I bit in the instruction, causing the specified effect on <xref linkend="BEIDIGBH">PSTATE</xref>.I, the IRQ interrupt mask bit.</content>
            </listitem>
            <listitem>
              <param>f</param><content>Sets the F bit in the instruction, causing the specified effect on <xref linkend="BEIDIGBH">PSTATE</xref>.F, the FIQ interrupt mask bit.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CPS_A1_AS, CPS_T2_AS" symboldefcount="1">
      <symbol link="sa_mode">&lt;mode&gt;</symbol>
      <account encodedin="mode">
        <intro>
          <para>Is the number of the mode to change to, in the range 0 to 31, encoded in the "mode" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/CPS/Op_AS.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if PSTATE.EL != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        if enable then</line>
<line>            if affectA then PSTATE.A = '0';</line>
<line>            if affectI then PSTATE.I = '0';</line>
<line>            if affectF then PSTATE.F = '0';</line>
<line>        if disable then</line>
<line>            if affectA then PSTATE.A = '1';</line>
<line>            if affectI then PSTATE.I = '1';</line>
<line>            if affectF then PSTATE.F = '1';</line>
<line>        if changemode then</line>
<line>            // AArch32.WriteModeByInstr() sets PSTATE.IL to 1 if this is an illegal mode change.</line>
<line>            <a link="AArch32.WriteModeByInstr.1" file="shared_pseudocode.xml" hover="function: AArch32.WriteModeByInstr(bits(5) mode)">AArch32.WriteModeByInstr</a>(mode);</line>
<line>else</line>
<line>    EncodingSpecificOperations();</line>
<line>    if PSTATE.EL != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        if enable then</line>
<line>            if affectA then PSTATE.A = '0';</line>
<line>            if affectI then PSTATE.I = '0';</line>
<line>            if affectF then PSTATE.F = '0';</line>
<line>        if disable then</line>
<line>            if affectA then PSTATE.A = '1';</line>
<line>            if affectI then PSTATE.I = '1';</line>
<line>            if affectF then PSTATE.F = '1';</line>
<line>        if changemode then</line>
<line>            // AArch32.WriteModeByInstr() sets PSTATE.IL to 1 if this is an illegal mode change.</line>
<line>            <a link="AArch32.WriteModeByInstr.1" file="shared_pseudocode.xml" hover="function: AArch32.WriteModeByInstr(bits(5) mode)">AArch32.WriteModeByInstr</a>(mode);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="crc32.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="CRC32" title="CRC32 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>CRC32</heading>
  <desc>
    <brief>
      <para>CRC32</para>
    </brief>
    <authored>
      <para><instruction>CRC32</instruction> performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, or 32 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial <hexnumber>0x04C11DB7</hexnumber> is used for the CRC calculation.</para>
      <para>In an Armv8.0 implementation, this is an <arm-defined-word>optional</arm-defined-word> instruction. From Armv8.1, it is mandatory for all implementations to implement this instruction.</para>
      <note>
        <para><xref linkend="AArch32.id_isar5">ID_ISAR5</xref>.CRC32 indicates whether this instruction is supported in the T32 and A32 instruction sets.</para>
      </note>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_CRC32" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/CRC32/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="sz" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" name="C" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="CRC32B_A1" oneofinclass="3" oneof="6" label="CRC32B" bitdiffs="sz == 00">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CRC32B" />
        </docvars>
        <box hibit="22" width="2" name="sz">
          <c>0</c>
          <c>0</c>
        </box>
        <asmtemplate><text>CRC32B</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose accumulator output register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose accumulator input register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose data source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CRC32H_A1" oneofinclass="3" oneof="6" label="CRC32H" bitdiffs="sz == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CRC32H" />
        </docvars>
        <box hibit="22" width="2" name="sz">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>CRC32H</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose accumulator output register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose accumulator input register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose data source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CRC32W_A1" oneofinclass="3" oneof="6" label="CRC32W" bitdiffs="sz == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CRC32W" />
        </docvars>
        <box hibit="22" width="2" name="sz">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>CRC32W</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose accumulator output register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose accumulator input register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose data source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CRC32/A1_A.txt" mylink="aarch32.instrs.CRC32.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if ! <a link="impl-shared.HaveCRCExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveCRCExt()">HaveCRCExt</a>() then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>size = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);</line>
<line>crc32c = (C == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>if size == 64 then UNPREDICTABLE;</line>
<line>if cond != '1110' then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == 64</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="size = 32;" />
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNCOND" />
          <cu_type constraint="Constraint_COND" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_CRC32" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/CRC32/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="C" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="sz" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="CRC32B_T1" oneofinclass="3" oneof="6" label="CRC32B" bitdiffs="sz == 00">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CRC32B" />
        </docvars>
        <box hibit="5" width="2" name="sz">
          <c>0</c>
          <c>0</c>
        </box>
        <asmtemplate><text>CRC32B</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose accumulator output register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose accumulator input register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose data source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CRC32H_T1" oneofinclass="3" oneof="6" label="CRC32H" bitdiffs="sz == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CRC32H" />
        </docvars>
        <box hibit="5" width="2" name="sz">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>CRC32H</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose accumulator output register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose accumulator input register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose data source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CRC32W_T1" oneofinclass="3" oneof="6" label="CRC32W" bitdiffs="sz == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CRC32W" />
        </docvars>
        <box hibit="5" width="2" name="sz">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>CRC32W</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose accumulator output register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose accumulator input register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose data source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CRC32/T1_A.txt" mylink="aarch32.instrs.CRC32.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if ! <a link="impl-shared.HaveCRCExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveCRCExt()">HaveCRCExt</a>() then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>size = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);</line>
<line>crc32c = (C == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>if size == 64 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == 64</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="size = 32;" />
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="CRC32B_A1, CRC32B_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. A <instruction>CRC32</instruction> instruction must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CRC32B_A1, CRC32B_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose accumulator output register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CRC32B_A1, CRC32B_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose accumulator input register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CRC32B_A1, CRC32B_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose data source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/CRC32/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line></line>
<line>    acc = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];             // accumulator</line>
<line>    val = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;size-1:0&gt;;   // input value</line>
<line>    poly = (if crc32c then 0x1EDC6F41 else 0x04C11DB7)&lt;31:0&gt;;</line>
<line>    tempacc = <a link="impl-shared.BitReverse.1" file="shared_pseudocode.xml" hover="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(acc):<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(size);</line>
<line>    tempval = <a link="impl-shared.BitReverse.1" file="shared_pseudocode.xml" hover="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(val):<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32);</line>
<line>    // Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.BitReverse.1" file="shared_pseudocode.xml" hover="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(<a link="impl-shared.Poly32Mod2.2" file="shared_pseudocode.xml" hover="function: bits(32) Poly32Mod2(bits(N) data_in, bits(32) poly)">Poly32Mod2</a>(tempacc EOR tempval, poly));</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="crc32c.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="CRC32C" title="CRC32C -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>CRC32C</heading>
  <desc>
    <brief>
      <para>CRC32C</para>
    </brief>
    <authored>
      <para><instruction>CRC32C</instruction> performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, or 32 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial <hexnumber>0x1EDC6F41</hexnumber> is used for the CRC calculation.</para>
      <para>In an Armv8.0 implementation, this is an <arm-defined-word>optional</arm-defined-word> instruction. From Armv8.1, it is mandatory for all implementations to implement this instruction.</para>
      <note>
        <para><xref linkend="AArch32.id_isar5">ID_ISAR5</xref>.CRC32 indicates whether this instruction is supported in the T32 and A32 instruction sets.</para>
      </note>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_CRC32" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/CRC32/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="sz" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" name="C" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="CRC32CB_A1" oneofinclass="3" oneof="6" label="CRC32CB" bitdiffs="sz == 00">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CRC32CB" />
        </docvars>
        <box hibit="22" width="2" name="sz">
          <c>0</c>
          <c>0</c>
        </box>
        <asmtemplate><text>CRC32CB</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose accumulator output register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose accumulator input register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose data source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CRC32CH_A1" oneofinclass="3" oneof="6" label="CRC32CH" bitdiffs="sz == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CRC32CH" />
        </docvars>
        <box hibit="22" width="2" name="sz">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>CRC32CH</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose accumulator output register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose accumulator input register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose data source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CRC32CW_A1" oneofinclass="3" oneof="6" label="CRC32CW" bitdiffs="sz == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CRC32CW" />
        </docvars>
        <box hibit="22" width="2" name="sz">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>CRC32CW</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose accumulator output register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose accumulator input register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose data source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CRC32/A1_A.txt" mylink="aarch32.instrs.CRC32.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if ! <a link="impl-shared.HaveCRCExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveCRCExt()">HaveCRCExt</a>() then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>size = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);</line>
<line>crc32c = (C == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>if size == 64 then UNPREDICTABLE;</line>
<line>if cond != '1110' then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == 64</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="size = 32;" />
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNCOND" />
          <cu_type constraint="Constraint_COND" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_CRC32" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/CRC32/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="C" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="sz" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="CRC32CB_T1" oneofinclass="3" oneof="6" label="CRC32CB" bitdiffs="sz == 00">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CRC32CB" />
        </docvars>
        <box hibit="5" width="2" name="sz">
          <c>0</c>
          <c>0</c>
        </box>
        <asmtemplate><text>CRC32CB</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose accumulator output register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose accumulator input register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose data source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CRC32CH_T1" oneofinclass="3" oneof="6" label="CRC32CH" bitdiffs="sz == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CRC32CH" />
        </docvars>
        <box hibit="5" width="2" name="sz">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>CRC32CH</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose accumulator output register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose accumulator input register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose data source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CRC32CW_T1" oneofinclass="3" oneof="6" label="CRC32CW" bitdiffs="sz == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CRC32CW" />
        </docvars>
        <box hibit="5" width="2" name="sz">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>CRC32CW</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose accumulator output register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose accumulator input register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose data source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CRC32/T1_A.txt" mylink="aarch32.instrs.CRC32.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if ! <a link="impl-shared.HaveCRCExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveCRCExt()">HaveCRCExt</a>() then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>size = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);</line>
<line>crc32c = (C == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>if size == 64 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == 64</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="size = 32;" />
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="CRC32CB_A1, CRC32CB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. A <instruction>CRC32C</instruction> instruction must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CRC32CB_A1, CRC32CB_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose accumulator output register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CRC32CB_A1, CRC32CB_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose accumulator input register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CRC32CB_A1, CRC32CB_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose data source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/CRC32/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line></line>
<line>    acc = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];             // accumulator</line>
<line>    val = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;size-1:0&gt;;   // input value</line>
<line>    poly = (if crc32c then 0x1EDC6F41 else 0x04C11DB7)&lt;31:0&gt;;</line>
<line>    tempacc = <a link="impl-shared.BitReverse.1" file="shared_pseudocode.xml" hover="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(acc):<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(size);</line>
<line>    tempval = <a link="impl-shared.BitReverse.1" file="shared_pseudocode.xml" hover="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(val):<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32);</line>
<line>    // Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.BitReverse.1" file="shared_pseudocode.xml" hover="function: bits(N) BitReverse(bits(N) data)">BitReverse</a>(<a link="impl-shared.Poly32Mod2.2" file="shared_pseudocode.xml" hover="function: bits(32) Poly32Mod2(bits(N) data_in, bits(32) poly)">Poly32Mod2</a>(tempacc EOR tempval, poly));</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="csdb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="CSDB" title="CSDB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="CSDB" />
  </docvars>
  <heading>CSDB</heading>
  <desc>
    <brief>
      <para>Consumption of Speculative Data Barrier</para>
    </brief>
    <authored>
      <para>Consumption of Speculative Data Barrier is a memory barrier that controls speculative execution and data value prediction.</para>
      <para>No instruction other than branch instructions and instructions that write to the PC appearing in program order after the CSDB can be speculatively executed using the results of any:</para>
      <list type="unordered">
        <listitem><content>Data value predictions of any instructions.</content></listitem>
        <listitem><content>PSTATE.{N,Z,C,V} predictions of any instructions other than conditional branch instructions and conditional instructions that write to the PC appearing in program order before the CSDB that have not been architecturally resolved.</content></listitem>
      </list>
      <note>
        <para>For purposes of the definition of CSDB, PSTATE.{N,Z,C,V} is not considered a data value. This definition permits:</para>
        <list type="unordered">
          <listitem><content>Control flow speculation before and after the CSDB.</content></listitem>
          <listitem><content>Speculative execution of conditional data processing instructions after the CSDB, unless they use the results of data value or PSTATE.{N,Z,C,V} predictions of instructions appearing in program order before the CSDB that have not been architecturally resolved.</content></listitem>
        </list>
      </note>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="CSDB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/CSDB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="R" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="imm4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" width="12" name="imm12" settings="12">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="CSDB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CSDB" />
        </docvars>
        <asmtemplate><text>CSDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CSDB/A1_A.txt" mylink="aarch32.instrs.CSDB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if cond != '1110' then UNPREDICTABLE;      // CSDB must be encoded with AL condition</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNCOND" />
          <cu_type constraint="Constraint_COND" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="CSDB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/CSDB/T1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="hint" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="option" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="CSDB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CSDB" />
        </docvars>
        <asmtemplate><text>CSDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CSDB/T1_A.txt" mylink="aarch32.instrs.CSDB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNCOND" />
          <cu_type constraint="Constraint_COND" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="CSDB_A1, CSDB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CSDB_A1, CSDB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/CSDB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line></line>
<line>    <a link="impl-shared.ConsumptionOfSpeculativeDataBarrier.0" file="shared_pseudocode.xml" hover="function: ConsumptionOfSpeculativeDataBarrier()">ConsumptionOfSpeculativeDataBarrier</a>();</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="dbg.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="DBG" title="DBG -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="DBG" />
  </docvars>
  <heading>DBG</heading>
  <desc>
    <brief>
      <para>Debug hint</para>
    </brief>
    <authored>
      <para><instruction>DBG</instruction> executes as a <instruction>NOP</instruction>. Arm deprecates any use of the <instruction>DBG</instruction> instruction.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="DBG" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/DBG/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="R" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="2" name="imm4&lt;3:2&gt;" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="17" width="2" name="imm4&lt;1:0&gt;" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" width="8" settings="8">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="option" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="DBG_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="DBG" />
        </docvars>
        <asmtemplate><text>DBG</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> #</text><a link="sa_option" hover="4-bit unsigned immediate [0-15] (field &quot;option&quot;)">&lt;option&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/DBG/A1_A.txt" mylink="aarch32.instrs.DBG.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// DBG executes as a NOP. The 'option' field is ignored</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="DBG" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/DBG/T1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="hint" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="option" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="DBG_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="DBG" />
        </docvars>
        <asmtemplate><text>DBG</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> #</text><a link="sa_option" hover="4-bit unsigned immediate [0-15] (field &quot;option&quot;)">&lt;option&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/DBG/T1_A.txt" mylink="aarch32.instrs.DBG.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// DBG executes as a NOP. The 'option' field is ignored</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="DBG_A1, DBG_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="DBG_A1, DBG_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="DBG_A1, DBG_T1" symboldefcount="1">
      <symbol link="sa_option">&lt;option&gt;</symbol>
      <account encodedin="option">
        <intro>
          <para>Is a 4-bit unsigned immediate, in the range 0 to 15, encoded in the "option" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/DBG/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="dcps1.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="DCPS1" title="DCPS1 -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="T1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="T32" />
    <docvar key="mnemonic" value="DCPS1" />
  </docvars>
  <heading>DCPS1</heading>
  <desc>
    <brief>
      <para>Debug Change PE State to EL1</para>
    </brief>
    <authored>
      <para>Debug Change PE State to EL1 allows the debugger to move the PE into EL1 from EL0 or to a specific mode at the current Exception level.</para>
      <para><instruction>DCPS1</instruction> is <arm-defined-word>undefined</arm-defined-word> if any of:</para>
      <list type="unordered">
        <listitem><content>The PE is in Non-debug state.</content></listitem>
        <listitem><content>EL2 is implemented, EL2 is implemented and enabled in the current Security state, and any of:<list type="unordered"><listitem><content>EL2 is using AArch32 and HCR.TGE is set to 1.</content></listitem><listitem><content>EL2 is using AArch64 and HCR_EL2.TGE is set to 1.</content></listitem></list></content></listitem>
      </list>
      <para>When the PE executes <instruction>DCPS1</instruction> at EL0, EL1 or EL3:</para>
      <list type="unordered">
        <listitem><content>If EL3 or EL1 is using AArch32, the PE enters SVC mode and LR_svc, SPSR_svc, DLR, and DSPSR become <arm-defined-word>UNKNOWN</arm-defined-word>. If <instruction>DCPS1</instruction> is executed in Monitor mode, SCR.NS is cleared to 0.</content></listitem>
        <listitem><content>If EL1 is using AArch64, the PE enters EL1 using AArch64, selects SP_EL1, and ELR_EL1, ESR_EL1, SPSR_EL1, DLR_EL0 and DSPSR_EL0 become <arm-defined-word>UNKNOWN</arm-defined-word>.</content></listitem>
      </list>
      <para>When the PE executes <instruction>DCPS1</instruction> at EL2 the PE does not change mode, and ELR_hyp, HSR, SPSR_hyp, DLR and DSPSR become <arm-defined-word>UNKNOWN</arm-defined-word>.</para>
      <para>For more information on the operation of the DCPS&lt;n&gt; instructions, see <xref linkend="dcps">DCPS</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="T1" oneof="1" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="DCPS1" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/DCPS1/T1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="imm4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="11" width="10" name="imm10" settings="10">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="1" width="2" name="opt" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="DCPS1_T1" oneofinclass="1" oneof="1" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="DCPS1" />
        </docvars>
        <asmtemplate><text>DCPS1</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/DCPS1/T1_A.txt" mylink="aarch32.instrs.DCPS1.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required.</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all"></explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/DCPS1/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if !<a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() then UNDEFINED;</line>
<line></line>
<line>if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>    tge = if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then HCR.TGE else HCR_EL2.TGE;</line>
<line>    if tge == '1' then UNDEFINED;</line>
<line></line>
<line>if PSTATE.EL != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> || <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>    if PSTATE.M == <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a> then SCR.NS = '0';</line>
<line>    if PSTATE.EL != <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>        <a link="AArch32.WriteMode.1" file="shared_pseudocode.xml" hover="function: AArch32.WriteMode(bits(5) mode)">AArch32.WriteMode</a>(<a link="M32_Svc" file="shared_pseudocode.xml" hover="constant bits(5) M32_Svc = '10011'">M32_Svc</a>);</line>
<line>        PSTATE.E = SCTLR.EE;</line>
<line>        if <a link="impl-shared.HavePANExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePANExt()">HavePANExt</a>() &amp;&amp; SCTLR.SPAN == '0' then PSTATE.PAN = '1';</line>
<line>        LR_svc = bits(32) UNKNOWN;</line>
<line>        SPSR_svc = bits(32) UNKNOWN;</line>
<line>    else</line>
<line>        PSTATE.E = HSCTLR.EE;</line>
<line>        ELR_hyp = bits(32) UNKNOWN;</line>
<line>        HSR = bits(32) UNKNOWN;</line>
<line>        SPSR_hyp = bits(32) UNKNOWN;</line>
<line></line>
<line>    DLR = bits(32) UNKNOWN;</line>
<line>    DSPSR = bits(32) UNKNOWN;</line>
<line>else                                        // Targeting EL1 using AArch64</line>
<line>    <a link="AArch64.MaybeZeroRegisterUppers.0" file="shared_pseudocode.xml" hover="function: AArch64.MaybeZeroRegisterUppers()">AArch64.MaybeZeroRegisterUppers</a>();</line>
<line>    MaybeZeroSVEUppers(EL1);</line>
<line>    PSTATE.nRW = '0';</line>
<line>    PSTATE.SP = '1';</line>
<line>    PSTATE.EL = <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>    if <a link="impl-shared.HavePANExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePANExt()">HavePANExt</a>() &amp;&amp; SCTLR_EL1.SPAN == '0' then PSTATE.PAN = '1';</line>
<line>    if <a link="impl-shared.HaveUAOExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveUAOExt()">HaveUAOExt</a>() then PSTATE.UAO = '0';</line>
<line></line>
<line>    ELR_EL1 = bits(64) UNKNOWN;</line>
<line>    ESR_EL1 = bits(64) UNKNOWN;</line>
<line>    SPSR_EL1 = bits(64) UNKNOWN;</line>
<line></line>
<line>    DLR_EL0 = bits(64) UNKNOWN;</line>
<line>    DSPSR_EL0 = bits(64) UNKNOWN;</line>
<line></line>
<line>    // SCTLR_EL1.IESB might be ignored in Debug state.</line>
<line>    if (<a link="impl-shared.HaveIESB.0" file="shared_pseudocode.xml" hover="function: boolean HaveIESB()">HaveIESB</a>() &amp;&amp; SCTLR_EL1.IESB == '1' &amp;&amp;</line>
<line>          !<a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_IESBinDebug" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_IESBinDebug</a>)) then</line>
<line>        <a link="impl-shared.SynchronizeErrors.0" file="shared_pseudocode.xml" hover="function: SynchronizeErrors()">SynchronizeErrors</a>();</line>
<line></line>
<line><a link="impl-shared.UpdateEDSCRFields.0" file="shared_pseudocode.xml" hover="function: UpdateEDSCRFields()">UpdateEDSCRFields</a>();                        // Update EDSCR PE state flags</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="dcps2.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="DCPS2" title="DCPS2 -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="T1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="T32" />
    <docvar key="mnemonic" value="DCPS2" />
  </docvars>
  <heading>DCPS2</heading>
  <desc>
    <brief>
      <para>Debug Change PE State to EL2</para>
    </brief>
    <authored>
      <para>Debug Change PE State to EL2 allows the debugger to move the PE into EL2 from a lower Exception level.</para>
      <para><instruction>DCPS2</instruction> is <arm-defined-word>undefined</arm-defined-word> if any of:</para>
      <list type="unordered">
        <listitem><content>The PE is in Non-debug state.</content></listitem>
        <listitem><content>EL2 is not implemented.</content></listitem>
        <listitem><content>The PE is in Secure state and any of:<list type="unordered"><listitem><content>Secure EL2 is not implemented.</content></listitem><listitem><content>Secure EL2 is implemented and Secure EL2 is disabled.</content></listitem></list></content></listitem>
      </list>
      <para>When the PE executes <instruction>DCPS2</instruction>:</para>
      <list type="unordered">
        <listitem><content>If EL2 is using AArch32, the PE enters Hyp mode and ELR_hyp, HSR, SPSR_hyp, DLR and DSPSR become <arm-defined-word>UNKNOWN</arm-defined-word>.</content></listitem>
        <listitem><content>If EL2 is using AArch64, the PE enters EL2 using AArch64, selects SP_EL2, and ELR_EL2, ESR_EL2, SPSR_EL2, DLR_EL0 and DSPSR_EL0 become <arm-defined-word>UNKNOWN</arm-defined-word>.</content></listitem>
      </list>
      <para>For more information on the operation of the DCPS&lt;n&gt; instructions, see <xref linkend="dcps">DCPS</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="T1" oneof="1" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="DCPS2" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/DCPS2/T1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="imm4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="11" width="10" name="imm10" settings="10">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="1" width="2" name="opt" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="DCPS2_T1" oneofinclass="1" oneof="1" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="DCPS2" />
        </docvars>
        <asmtemplate><text>DCPS2</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/DCPS2/T1_A.txt" mylink="aarch32.instrs.DCPS2.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then UNDEFINED;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all"></explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/DCPS2/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if !<a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() || !<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then UNDEFINED;</line>
<line></line>
<line>if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>    <a link="AArch32.WriteMode.1" file="shared_pseudocode.xml" hover="function: AArch32.WriteMode(bits(5) mode)">AArch32.WriteMode</a>(<a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a>);</line>
<line>    PSTATE.E = HSCTLR.EE;</line>
<line></line>
<line>    ELR_hyp = bits(32) UNKNOWN;</line>
<line>    HSR = bits(32) UNKNOWN;</line>
<line>    SPSR_hyp = bits(32) UNKNOWN;</line>
<line></line>
<line>    DLR = bits(32) UNKNOWN;</line>
<line>    DSPSR = bits(32) UNKNOWN;</line>
<line>else                                        // Targeting EL2 using AArch64</line>
<line>    <a link="AArch64.MaybeZeroRegisterUppers.0" file="shared_pseudocode.xml" hover="function: AArch64.MaybeZeroRegisterUppers()">AArch64.MaybeZeroRegisterUppers</a>();</line>
<line>    MaybeZeroSVEUppers(EL2);</line>
<line>    PSTATE.nRW = '0';</line>
<line>    PSTATE.SP = '1';</line>
<line>    PSTATE.EL = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>    if <a link="impl-shared.HavePANExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePANExt()">HavePANExt</a>() &amp;&amp; SCTLR_EL2.SPAN == '0' &amp;&amp; HCR_EL2.E2H == '1' &amp;&amp; HCR_EL2.TGE == '1' then</line>
<line>        PSTATE.PAN = '1';</line>
<line>    if <a link="impl-shared.HaveUAOExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveUAOExt()">HaveUAOExt</a>() then PSTATE.UAO = '0';</line>
<line></line>
<line>    ELR_EL2 = bits(64) UNKNOWN;</line>
<line>    ESR_EL2 = bits(64) UNKNOWN;</line>
<line>    SPSR_EL2 = bits(64) UNKNOWN;</line>
<line></line>
<line>    DLR_EL0 = bits(64) UNKNOWN;</line>
<line>    DSPSR_EL0 = bits(64) UNKNOWN;</line>
<line></line>
<line>    // SCTLR_EL2.IESB might be ignored in Debug state.</line>
<line>    if (<a link="impl-shared.HaveIESB.0" file="shared_pseudocode.xml" hover="function: boolean HaveIESB()">HaveIESB</a>() &amp;&amp; SCTLR_EL2.IESB == '1' &amp;&amp;</line>
<line>          !<a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_IESBinDebug" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_IESBinDebug</a>)) then</line>
<line>        <a link="impl-shared.SynchronizeErrors.0" file="shared_pseudocode.xml" hover="function: SynchronizeErrors()">SynchronizeErrors</a>();</line>
<line></line>
<line><a link="impl-shared.UpdateEDSCRFields.0" file="shared_pseudocode.xml" hover="function: UpdateEDSCRFields()">UpdateEDSCRFields</a>();                        // Update EDSCR PE state flags</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="dcps3.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="DCPS3" title="DCPS3 -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="T1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="T32" />
    <docvar key="mnemonic" value="DCPS3" />
  </docvars>
  <heading>DCPS3</heading>
  <desc>
    <brief>
      <para>Debug Change PE State to EL3</para>
    </brief>
    <authored>
      <para>Debug Change PE State to EL3 allows the debugger to move the PE into EL3 from a lower Exception level or to a specific mode at the current Exception level.</para>
      <para><instruction>DCPS3</instruction> is <arm-defined-word>undefined</arm-defined-word> if any of:</para>
      <list type="unordered">
        <listitem><content>The PE is in Non-debug state.</content></listitem>
        <listitem><content>EL3 is not implemented.</content></listitem>
        <listitem><content>EDSCR.SDD is set to 1.</content></listitem>
      </list>
      <para>When the PE executes <instruction>DCPS3</instruction>:</para>
      <list type="unordered">
        <listitem><content>If EL3 is using AArch32, the PE enters Monitor mode and LR_mon, SPSR_mon, DLR and DSPSR become <arm-defined-word>UNKNOWN</arm-defined-word>. If <instruction>DCPS3</instruction> is executed in Monitor mode, SCR.NS is cleared to 0.</content></listitem>
        <listitem><content>If EL3 is using AArch64, the PE enters EL3 using AArch64, selects SP_EL3, and ELR_EL3, ESR_EL3, SPSR_EL3, DLR_EL0 and DSPSR_EL0 become <arm-defined-word>UNKNOWN</arm-defined-word>.</content></listitem>
      </list>
      <para>For more information on the operation of the DCPS&lt;n&gt; instructions, see <xref linkend="dcps">DCPS</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="T1" oneof="1" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="DCPS3" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/DCPS3/T1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="imm4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="11" width="10" name="imm10" settings="10">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="1" width="2" name="opt" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="DCPS3_T1" oneofinclass="1" oneof="1" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="DCPS3" />
        </docvars>
        <asmtemplate><text>DCPS3</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/DCPS3/T1_A.txt" mylink="aarch32.instrs.DCPS3.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then UNDEFINED;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all"></explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/DCPS3/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if !<a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() || EDSCR.SDD == '1' then UNDEFINED;</line>
<line></line>
<line>if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>    from_secure = <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>;</line>
<line>    if PSTATE.M == <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a> then SCR.NS = '0';</line>
<line>    <a link="AArch32.WriteMode.1" file="shared_pseudocode.xml" hover="function: AArch32.WriteMode(bits(5) mode)">AArch32.WriteMode</a>(<a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a>);</line>
<line>    if <a link="impl-shared.HavePANExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePANExt()">HavePANExt</a>() then</line>
<line>        if !from_secure then</line>
<line>            PSTATE.PAN = '0';</line>
<line>        elsif SCTLR.SPAN == '0' then</line>
<line>            PSTATE.PAN = '1';</line>
<line>    PSTATE.E = SCTLR.EE;</line>
<line></line>
<line>    LR_mon = bits(32) UNKNOWN;</line>
<line>    SPSR_mon = bits(32) UNKNOWN;</line>
<line></line>
<line>    DLR = bits(32) UNKNOWN;</line>
<line>    DSPSR = bits(32) UNKNOWN;</line>
<line>else                                        // Targeting EL3 using AArch64</line>
<line>    <a link="AArch64.MaybeZeroRegisterUppers.0" file="shared_pseudocode.xml" hover="function: AArch64.MaybeZeroRegisterUppers()">AArch64.MaybeZeroRegisterUppers</a>();</line>
<line>    MaybeZeroSVEUppers(EL3);</line>
<line>    PSTATE.nRW = '0';</line>
<line>    PSTATE.SP = '1';</line>
<line>    PSTATE.EL = <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line>    if <a link="impl-shared.HaveUAOExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveUAOExt()">HaveUAOExt</a>() then PSTATE.UAO = '0';</line>
<line></line>
<line>    ELR_EL3 = bits(64) UNKNOWN;</line>
<line>    ESR_EL3 = bits(64) UNKNOWN;</line>
<line>    SPSR_EL3 = bits(64) UNKNOWN;</line>
<line></line>
<line>    DLR_EL0 = bits(64) UNKNOWN;</line>
<line>    DSPSR_EL0 = bits(64) UNKNOWN;</line>
<line></line>
<line>    sync_errors = <a link="impl-shared.HaveIESB.0" file="shared_pseudocode.xml" hover="function: boolean HaveIESB()">HaveIESB</a>() &amp;&amp; SCTLR_EL3.IESB == '1';</line>
<line>    if <a link="impl-shared.HaveDoubleFaultExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDoubleFaultExt()">HaveDoubleFaultExt</a>() &amp;&amp; <a link="impl-shared.EffectiveEA.0" file="shared_pseudocode.xml" hover="function: bit EffectiveEA()">EffectiveEA</a>() == '1' &amp;&amp; SCR_EL3.NMEA == '1' then</line>
<line>        sync_errors = TRUE;</line>
<line>    // SCTLR_EL3.IESB might be ignored in Debug state.</line>
<line>    if !<a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_IESBinDebug" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_IESBinDebug</a>) then</line>
<line>        sync_errors = FALSE;</line>
<line>    if sync_errors then <a link="impl-shared.SynchronizeErrors.0" file="shared_pseudocode.xml" hover="function: SynchronizeErrors()">SynchronizeErrors</a>();</line>
<line></line>
<line><a link="impl-shared.UpdateEDSCRFields.0" file="shared_pseudocode.xml" hover="function: UpdateEDSCRFields()">UpdateEDSCRFields</a>();                        // Update EDSCR PE state flags</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="dmb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="DMB" title="DMB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="DMB" />
  </docvars>
  <heading>DMB</heading>
  <desc>
    <brief>
      <para>Data Memory Barrier</para>
    </brief>
    <authored>
      <para>Data Memory Barrier is a memory barrier that ensures the ordering of observations of memory accesses, see <xref linkend="AA32CHDCIFHJ">Data Memory Barrier (DMB)</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="DMB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/DMB/A1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" name="opcode" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="option" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="DMB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="DMB" />
        </docvars>
        <asmtemplate><text>DMB</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_option" hover="Specifies an optional limitation on the barrier operation">&lt;option&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/DMB/A1_A.txt" mylink="aarch32.instrs.DMB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="DMB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/DMB/T1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="option" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="DMB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="DMB" />
        </docvars>
        <asmtemplate><text>DMB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_option" hover="Specifies an optional limitation on the barrier operation">&lt;option&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/DMB/T1_A.txt" mylink="aarch32.instrs.DMB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="DMB_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. Must be <value>AL</value> or omitted.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="DMB_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="DMB_A1, DMB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="DMB_A1, DMB_T1" symboldefcount="1">
      <symbol link="sa_option">&lt;option&gt;</symbol>
      <account encodedin="option">
        <intro>
          <para>Specifies an optional limitation on the barrier operation. Values are:</para>
          <list type="param">
            <listitem>
              <param>SY</param><content>Full system is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Can be omitted. This option is referred to as the full system barrier. Encoded as option = <binarynumber>0b1111</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>ST</param><content>Full system is the required shareability domain, writes are the required access type, both before and after the barrier instruction. <value>SYST</value> is a synonym for <value>ST</value>. Encoded as option = <binarynumber>0b1110</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>LD</param><content>Full system is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = <binarynumber>0b1101</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>ISH</param><content>Inner Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as option = <binarynumber>0b1011</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>ISHST</param><content>Inner Shareable is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as option = <binarynumber>0b1010</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>ISHLD</param><content>Inner Shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = <binarynumber>0b1001</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>NSH</param><content>Non-shareable is the required shareability domain, reads and writes are the required access, both before and after the barrier instruction. Encoded as option = <binarynumber>0b0111</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>NSHST</param><content>Non-shareable is the required shareability domain, writes are the required access type both before and after the barrier instruction. Encoded as option = <binarynumber>0b0110</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>NSHLD</param><content>Non-shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = <binarynumber>0b0101</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>OSH</param><content>Outer Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as option = <binarynumber>0b0011</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>OSHST</param><content>Outer Shareable is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as option = <binarynumber>0b0010</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>OSHLD</param><content>Outer Shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = <binarynumber>0b0001</binarynumber>.</content>
            </listitem>
          </list>
          <para>For more information on whether an access is before or after a barrier instruction, see <xref linkend="AA32CHDCIFHJ">Data Memory Barrier (DMB)</xref>. All other encodings of option are reserved. All unsupported and reserved options must execute as a full system DMB operation, but software must not rely on this behavior.</para>
          <note>
            <para>The instruction supports the following alternative <syntax>&lt;option&gt;</syntax> values, but Arm recommends that software does not use these alternative values:</para>
            <list type="unordered">
              <listitem><content><value>SH</value> as an alias for <value>ISH</value>.</content></listitem>
              <listitem><content><value>SHST</value> as an alias for <value>ISHST</value>.</content></listitem>
              <listitem><content><value>UN</value> as an alias for <value>NSH</value>.</content></listitem>
              <listitem><content><value>UNST</value> as an alias for <value>NSHST</value>.</content></listitem>
            </list>
          </note>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/DMB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="MBReqDomain" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain</a> domain;</line>
<line>    <a link="MBReqTypes" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes</a> types;</line>
<line>    case option of</line>
<line>        when '0001'  domain = <a link="MBReqDomain_OuterShareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_OuterShareable</a>;  types = <a link="MBReqTypes_Reads" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_Reads</a>;</line>
<line>        when '0010'  domain = <a link="MBReqDomain_OuterShareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_OuterShareable</a>;  types = <a link="MBReqTypes_Writes" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_Writes</a>;</line>
<line>        when '0011'  domain = <a link="MBReqDomain_OuterShareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_OuterShareable</a>;  types = <a link="MBReqTypes_All" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_All</a>;</line>
<line>        when '0101'  domain = <a link="MBReqDomain_Nonshareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_Nonshareable</a>;    types = <a link="MBReqTypes_Reads" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_Reads</a>;</line>
<line>        when '0110'  domain = <a link="MBReqDomain_Nonshareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_Nonshareable</a>;    types = <a link="MBReqTypes_Writes" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_Writes</a>;</line>
<line>        when '0111'  domain = <a link="MBReqDomain_Nonshareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_Nonshareable</a>;    types = <a link="MBReqTypes_All" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_All</a>;</line>
<line>        when '1001'  domain = <a link="MBReqDomain_InnerShareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_InnerShareable</a>;  types = <a link="MBReqTypes_Reads" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_Reads</a>;</line>
<line>        when '1010'  domain = <a link="MBReqDomain_InnerShareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_InnerShareable</a>;  types = <a link="MBReqTypes_Writes" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_Writes</a>;</line>
<line>        when '1011'  domain = <a link="MBReqDomain_InnerShareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_InnerShareable</a>;  types = <a link="MBReqTypes_All" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_All</a>;</line>
<line>        when '1101'  domain = <a link="MBReqDomain_FullSystem" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_FullSystem</a>;      types = <a link="MBReqTypes_Reads" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_Reads</a>;</line>
<line>        when '1110'  domain = <a link="MBReqDomain_FullSystem" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_FullSystem</a>;      types = <a link="MBReqTypes_Writes" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_Writes</a>;</line>
<line>        otherwise    domain = <a link="MBReqDomain_FullSystem" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_FullSystem</a>;      types = <a link="MBReqTypes_All" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_All</a>;</line>
<line></line>
<line>    if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        if HCR.BSU == '11' then</line>
<line>            domain = <a link="MBReqDomain_FullSystem" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_FullSystem</a>;</line>
<line>        if HCR.BSU == '10' &amp;&amp; domain != <a link="MBReqDomain_FullSystem" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_FullSystem</a> then</line>
<line>            domain = <a link="MBReqDomain_OuterShareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_OuterShareable</a>;</line>
<line>        if HCR.BSU == '01' &amp;&amp; domain == <a link="MBReqDomain_Nonshareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_Nonshareable</a> then</line>
<line>            domain = <a link="MBReqDomain_InnerShareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_InnerShareable</a>;</line>
<line></line>
<line>    <a link="impl-shared.DataMemoryBarrier.2" file="shared_pseudocode.xml" hover="function: DataMemoryBarrier(MBReqDomain domain, MBReqTypes types)">DataMemoryBarrier</a>(domain, types);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="dsb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="DSB" title="DSB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="DSB" />
  </docvars>
  <heading>DSB</heading>
  <desc>
    <brief>
      <para>Data Synchronization Barrier</para>
    </brief>
    <authored>
      <para>Data Synchronization Barrier is a memory barrier that ensures the completion of memory accesses, see <xref linkend="AA32CHDIJCDJ">Data Synchronization Barrier (DSB)</xref>.</para>
      <para>An AArch32 DSB instruction does not require the completion of any AArch64 TLB maintenance instructions, regardless of the nXS qualifier, appearing in program order before the AArch32 DSB.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="DSB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/DSB/A1_A.txt" tworows="1">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" name="opcode" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="option" usename="1" settings="4" constraint="!= 0x00">
          <c colspan="4">!= 0x00</c>
        </box>
      </regdiagram>
      <encoding name="DSB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="DSB" />
        </docvars>
        <asmtemplate><text>DSB</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_option" hover="Specifies an optional limitation on the barrier operation">&lt;option&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/DSB/A1_A.txt" mylink="aarch32.instrs.DSB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="DSB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/DSB/T1_A.txt" tworows="1">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="option" usename="1" settings="4" constraint="!= 0x00">
          <c colspan="4">!= 0x00</c>
        </box>
      </regdiagram>
      <encoding name="DSB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="DSB" />
        </docvars>
        <asmtemplate><text>DSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_option" hover="Specifies an optional limitation on the barrier operation">&lt;option&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/DSB/T1_A.txt" mylink="aarch32.instrs.DSB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="DSB_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. Must be <value>AL</value> or omitted.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="DSB_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="DSB_A1, DSB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="DSB_A1, DSB_T1" symboldefcount="1">
      <symbol link="sa_option">&lt;option&gt;</symbol>
      <account encodedin="option">
        <intro>
          <para>Specifies an optional limitation on the barrier operation. Values are:</para>
          <list type="param">
            <listitem>
              <param>SY</param><content>Full system is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Can be omitted. This option is referred to as the full system barrier. Encoded as option = <binarynumber>0b1111</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>ST</param><content>Full system is the required shareability domain, writes are the required access type, both before and after the barrier instruction. <value>SYST</value> is a synonym for <value>ST</value>. Encoded as option = <binarynumber>0b1110</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>LD</param><content>Full system is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = <binarynumber>0b1101</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>ISH</param><content>Inner Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as option = <binarynumber>0b1011</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>ISHST</param><content>Inner Shareable is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as option = <binarynumber>0b1010</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>ISHLD</param><content>Inner Shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = <binarynumber>0b1001</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>NSH</param><content>Non-shareable is the required shareability domain, reads and writes are the required access, both before and after the barrier instruction. Encoded as option = <binarynumber>0b0111</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>NSHST</param><content>Non-shareable is the required shareability domain, writes are the required access type both before and after the barrier instruction. Encoded as option = <binarynumber>0b0110</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>NSHLD</param><content>Non-shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = <binarynumber>0b0101</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>OSH</param><content>Outer Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as option = <binarynumber>0b0011</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>OSHST</param><content>Outer Shareable is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as option = <binarynumber>0b0010</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>OSHLD</param><content>Outer Shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as option = <binarynumber>0b0001</binarynumber>.</content>
            </listitem>
          </list>
          <para>For more information on whether an access is before or after a barrier instruction, see <xref linkend="AA32CHDIJCDJ">Data Synchronization Barrier (DSB)</xref>. All other encodings of option are reserved, other than the values <binarynumber>0b0000</binarynumber> and <binarynumber>0b0100</binarynumber>. All unsupported and reserved options must execute as a full system DSB operation, but software must not rely on this behavior.</para>
          <note>
            <para>The value <binarynumber>0b0000</binarynumber> is used to encode SSBB and the value <binarynumber>0b0100</binarynumber> is used to encode PSSBB.</para>
            <para>The instruction supports the following alternative <syntax>&lt;option&gt;</syntax> values, but Arm recommends that software does not use these alternative values:</para>
            <list type="unordered">
              <listitem><content><value>SH</value> as an alias for <value>ISH</value>.</content></listitem>
              <listitem><content><value>SHST</value> as an alias for <value>ISHST</value>.</content></listitem>
              <listitem><content><value>UN</value> as an alias for <value>NSH</value>.</content></listitem>
              <listitem><content><value>UNST</value> as an alias for <value>NSHST</value>.</content></listitem>
            </list>
          </note>
        </intro>
      </account>
      <arch_variants>
        <arch_variant name="ARMv8.0-A" />
      </arch_variants>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/DSB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    boolean nXS;</line>
<line>    if <a link="impl-shared.HaveFeatXS.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatXS()">HaveFeatXS</a>() then</line>
<line>        nXS = (PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp;</line>
<line>            IsHCRXEL2Enabled() &amp;&amp; HCRX_EL2.FnXS == '1');</line>
<line>    else</line>
<line>        nXS = FALSE;</line>
<line>    <a link="MBReqDomain" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain</a> domain;</line>
<line>    <a link="MBReqTypes" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes</a> types;</line>
<line>    case option of</line>
<line>        when '0001'  domain = <a link="MBReqDomain_OuterShareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_OuterShareable</a>;  types = <a link="MBReqTypes_Reads" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_Reads</a>;</line>
<line>        when '0010'  domain = <a link="MBReqDomain_OuterShareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_OuterShareable</a>;  types = <a link="MBReqTypes_Writes" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_Writes</a>;</line>
<line>        when '0011'  domain = <a link="MBReqDomain_OuterShareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_OuterShareable</a>;  types = <a link="MBReqTypes_All" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_All</a>;</line>
<line>        when '0101'  domain = <a link="MBReqDomain_Nonshareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_Nonshareable</a>;    types = <a link="MBReqTypes_Reads" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_Reads</a>;</line>
<line>        when '0110'  domain = <a link="MBReqDomain_Nonshareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_Nonshareable</a>;    types = <a link="MBReqTypes_Writes" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_Writes</a>;</line>
<line>        when '0111'  domain = <a link="MBReqDomain_Nonshareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_Nonshareable</a>;    types = <a link="MBReqTypes_All" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_All</a>;</line>
<line>        when '1001'  domain = <a link="MBReqDomain_InnerShareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_InnerShareable</a>;  types = <a link="MBReqTypes_Reads" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_Reads</a>;</line>
<line>        when '1010'  domain = <a link="MBReqDomain_InnerShareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_InnerShareable</a>;  types = <a link="MBReqTypes_Writes" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_Writes</a>;</line>
<line>        when '1011'  domain = <a link="MBReqDomain_InnerShareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_InnerShareable</a>;  types = <a link="MBReqTypes_All" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_All</a>;</line>
<line>        when '1101'  domain = <a link="MBReqDomain_FullSystem" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_FullSystem</a>;      types = <a link="MBReqTypes_Reads" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_Reads</a>;</line>
<line>        when '1110'  domain = <a link="MBReqDomain_FullSystem" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_FullSystem</a>;      types = <a link="MBReqTypes_Writes" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_Writes</a>;</line>
<line>        otherwise</line>
<line>            assert !(option IN {'0x00'});</line>
<line>            domain = <a link="MBReqDomain_FullSystem" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_FullSystem</a>;  types = <a link="MBReqTypes_All" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_All</a>;</line>
<line></line>
<line>    if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        if HCR.BSU == '11' then</line>
<line>            domain = <a link="MBReqDomain_FullSystem" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_FullSystem</a>;</line>
<line>        if HCR.BSU == '10' &amp;&amp; domain != <a link="MBReqDomain_FullSystem" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_FullSystem</a> then</line>
<line>            domain = <a link="MBReqDomain_OuterShareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_OuterShareable</a>;</line>
<line>        if HCR.BSU == '01' &amp;&amp; domain == <a link="MBReqDomain_Nonshareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_Nonshareable</a> then</line>
<line>            domain = <a link="MBReqDomain_InnerShareable" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_InnerShareable</a>;</line>
<line></line>
<line>    <a link="impl-shared.DataSynchronizationBarrier.3" file="shared_pseudocode.xml" hover="function: DataSynchronizationBarrier(MBReqDomain domain, MBReqTypes types, boolean nXS)">DataSynchronizationBarrier</a>(domain, types, nXS);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="eor_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="EOR_i" title="EOR, EORS (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>EOR, EORS (immediate)</heading>
  <desc>
    <brief>
      <para>Bitwise Exclusive-OR (immediate)</para>
    </brief>
    <authored>
      <para>Bitwise Exclusive-OR (immediate) performs a bitwise exclusive-OR of a register value and an immediate value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the EORS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The EOR variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The EORS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/EOR_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="EOR_i_A1" oneofinclass="2" oneof="4" label="EOR" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="EOR" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>EOR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="EORS_i_A1" oneofinclass="2" oneof="4" label="EORS" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="EORS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>EORS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/EOR_i/A1_A.txt" mylink="aarch32.instrs.EOR_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = (S == '1');</line>
<line>(imm32, carry) = <a link="impl-aarch32.A32ExpandImm_C.2" file="shared_pseudocode.xml" hover="function: (bits(32), bit) A32ExpandImm_C(bits(12) imm12, bit carry_in)">A32ExpandImm_C</a>(imm12, PSTATE.C);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/EOR_i/T1_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="EOR_i_T1" oneofinclass="2" oneof="4" label="EOR" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="EOR" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>EOR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="EORS_i_T1" oneofinclass="2" oneof="4" label="EORS" bitdiffs="S == 1 &amp;&amp; Rd != 1111">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="EORS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>EORS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/EOR_i/T1_A.txt" mylink="aarch32.instrs.EOR_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rd == '1111' &amp;&amp; S == '1' then SEE "TEQ (immediate)";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = (S == '1');</line>
<line>(imm32, carry) = <a link="impl-aarch32.T32ExpandImm_C.2" file="shared_pseudocode.xml" hover="function: (bits(32), bit) T32ExpandImm_C(bits(12) imm12, bit carry_in)">T32ExpandImm_C</a>(i:imm3:imm8, PSTATE.C);</line>
<line>if (d == 15 &amp;&amp; !setflags) || n == 15 then UNPREDICTABLE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="EOR_i_A1, EOR_i_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EOR_i_A1, EOR_i_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EOR_i_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the EOR variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the EORS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EOR_i_T1" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EOR_i_A1" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EOR_i_T1" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EOR_i_A1" symboldefcount="1">
      <symbol link="sa_const_1">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: an immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EOR_i_T1" symboldefcount="2">
      <symbol link="sa_const">&lt;const&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: an immediate value. See <xref linkend="BABGHAGA">Modified immediate constants in T32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/EOR_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    result = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] EOR imm32;</line>
<line>    if d == 15 then          // Can only occur for A32 encoding</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.N = result&lt;31&gt;;</line>
<line>            PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>            PSTATE.C = carry;</line>
<line>            // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="eor_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="EOR_r" title="EOR, EORS (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>EOR, EORS (register)</heading>
  <desc>
    <brief>
      <para>Bitwise Exclusive-OR (register)</para>
    </brief>
    <authored>
      <para>Bitwise Exclusive-OR (register) performs a bitwise exclusive-OR of a register value and an optionally-shifted register value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the EORS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The EOR variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The EORS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>In T32 assembly:</para>
      <list type="unordered">
        <listitem><content>Outside an IT block, if <syntax>EORS &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rd&gt;</syntax> has <syntax>&lt;Rd&gt;</syntax> and <syntax>&lt;Rn&gt;</syntax> both in the range R0-R7, it is assembled using encoding T1 as though <syntax>EORS &lt;Rd&gt;, &lt;Rn&gt;</syntax> had been written</content></listitem>
        <listitem><content>Inside an IT block, if <syntax>EOR&lt;c&gt; &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rd&gt;</syntax> has <syntax>&lt;Rd&gt;</syntax> and <syntax>&lt;Rn&gt;</syntax> both in the range R0-R7, it is assembled using encoding T1 as though <syntax>EOR&lt;c&gt; &lt;Rd&gt;, &lt;Rn&gt;</syntax> had been written.</content></listitem>
      </list>
      <para>To prevent either of these happening, use the <syntax>.W</syntax> qualifier.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/EOR_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="EOR_r_A1_RRX" oneofinclass="4" oneof="9" label="EOR, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="EOR" />
          <docvar key="mnemonic-shift-type" value="EOR-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>EOR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="EOR_r_A1" oneofinclass="4" oneof="9" label="EOR, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="EOR" />
          <docvar key="mnemonic-shift-type" value="EOR-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>EOR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="EORS_r_A1_RRX" oneofinclass="4" oneof="9" label="EORS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="EORS" />
          <docvar key="mnemonic-shift-type" value="EORS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>EORS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="EORS_r_A1" oneofinclass="4" oneof="9" label="EORS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="EORS" />
          <docvar key="mnemonic-shift-type" value="EORS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>EORS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/EOR_r/A1_A.txt" mylink="aarch32.instrs.EOR_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="EOR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/EOR_r/T1_A.txt">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="4" name="op" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rdn" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="EOR_r_T1" oneofinclass="1" oneof="9" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="EOR" />
        </docvars>
        <asmtemplate comment="Inside IT block"><text>EOR</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate comment="Outside IT block"><text>EORS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/EOR_r/T1_A.txt" mylink="aarch32.instrs.EOR_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdn);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>();</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/EOR_r/T2_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="EOR_r_T2_RRX" oneofinclass="4" oneof="9" label="EOR, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="EOR" />
          <docvar key="mnemonic-shift-type" value="EOR-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>EOR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="EOR_r_T2" oneofinclass="4" oneof="9" label="EOR, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="EOR" />
          <docvar key="mnemonic-shift-type" value="EOR-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Inside IT block, and &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>EOR</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>EOR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="EORS_r_T2_RRX" oneofinclass="4" oneof="9" label="EORS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm3 == 000 &amp;&amp; Rd != 1111 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="EORS" />
          <docvar key="mnemonic-shift-type" value="EORS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="11" width="4" name="Rd">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>EORS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="EORS_r_T2" oneofinclass="4" oneof="9" label="EORS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11) &amp;&amp; Rd != 1111">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="EORS" />
          <docvar key="mnemonic-shift-type" value="EORS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <box hibit="11" width="4" name="Rd">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Outside IT block, and &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>EORS.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>EORS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/EOR_r/T2_A.txt" mylink="aarch32.instrs.EOR_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rd == '1111' &amp;&amp; S == '1' then SEE "TEQ (register)";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm3:imm2);</line>
<line>if (d == 15 &amp;&amp; !setflags) || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="EOR_r_A1, EOR_r_T1, EOR_r_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EOR_r_A1, EOR_r_T1, EOR_r_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EOR_r_T1" symboldefcount="1">
      <symbol link="sa_rdn">&lt;Rdn&gt;</symbol>
      <account encodedin="Rdn">
        <intro>
          <para>Is the first general-purpose source register and the destination register, encoded in the "Rdn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EOR_r_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the EOR variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the EORS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EOR_r_T2" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EOR_r_A1" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EOR_r_T2" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EOR_r_A1" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="EOR-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EOR_r_T1, EOR_r_T2" symboldefcount="2">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EOR_r_A1, EOR_r_T2" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="EOR_r_A1" symboldefcount="1">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EOR_r_T2" symboldefcount="2">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm3:imm2" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/EOR_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    (shifted, carry) = <a link="impl-aarch32.Shift_C.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift_C</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    result = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] EOR shifted;</line>
<line>    if d == 15 then          // Can only occur for A32 encoding</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.N = result&lt;31&gt;;</line>
<line>            PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>            PSTATE.C = carry;</line>
<line>            // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="eor_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="EOR_rr" title="EOR, EORS (register-shifted register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
  </docvars>
  <heading>EOR, EORS (register-shifted register)</heading>
  <desc>
    <brief>
      <para>Bitwise Exclusive-OR (register-shifted register)</para>
    </brief>
    <authored>
      <para>Bitwise Exclusive-OR (register-shifted register) performs a bitwise exclusive-OR of a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/EOR_rr/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="EORS_rr_A1" oneofinclass="2" oneof="2" label="Flag setting" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="EORS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>EORS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="Third general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <encoding name="EOR_rr_A1" oneofinclass="2" oneof="2" label="Not flag setting" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="EOR" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>EOR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="Third general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/EOR_rr/A1_A.txt" mylink="aarch32.instrs.EOR_rr.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);</line>
<line>setflags = (S == '1');  shift_t = <a link="impl-aarch32.DecodeRegShift.1" file="shared_pseudocode.xml" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</a>(stype);</line>
<line>if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="EOR_rr_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EOR_rr_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EOR_rr_A1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EOR_rr_A1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EOR_rr_A1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="EOR_rr_A1" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="EOR_rr_A1" symboldefcount="1">
      <symbol link="sa_rs">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the third general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/EOR_rr/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shift_n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[s]&lt;7:0&gt;);</line>
<line>    (shifted, carry) = <a link="impl-aarch32.Shift_C.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift_C</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    result = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] EOR shifted;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>    if setflags then</line>
<line>        PSTATE.N = result&lt;31&gt;;</line>
<line>        PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>        PSTATE.C = carry;</line>
<line>        // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="eret.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ERET" title="ERET -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="ERET" />
  </docvars>
  <heading>ERET</heading>
  <desc>
    <brief>
      <para>Exception Return</para>
    </brief>
    <authored>
      <para>Exception Return.</para>
      <para>The PE branches to the address held in the register holding the preferred return address, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</para>
      <para>The register holding the preferred return address is:</para>
      <list type="unordered">
        <listitem><content><xref linkend="AArch32.elr_hyp">ELR_hyp</xref>, when executing in Hyp mode.</content></listitem>
        <listitem><content>LR, when executing in a mode other than Hyp mode, User mode, or System mode.</content></listitem>
      </list>
      <para>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</para>
      <para>Exception Return is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</para>
      <para>In Debug state, the T1 encoding of <instruction>ERET</instruction> executes the DRPS operation.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="ERET" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/ERET/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="8" settings="8">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="3" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="ERET_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ERET" />
        </docvars>
        <asmtemplate><text>ERET</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ERET/A1_A.txt" mylink="aarch32.instrs.ERET.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ERET" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/ERET/T1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" width="8" name="imm8" settings="8">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="ERET_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ERET" />
        </docvars>
        <asmtemplate><text>ERET</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ERET/T1_A.txt" mylink="aarch32.instrs.ERET.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ERET_A1, ERET_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ERET_A1, ERET_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/ERET/Op_AS.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if !<a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() then</line>
<line>        if PSTATE.M IN {<a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a>,<a link="M32_System" file="shared_pseudocode.xml" hover="constant bits(5) M32_System = '11111'">M32_System</a>} then</line>
<line>            UNPREDICTABLE;                        // UNDEFINED or NOP</line>
<line>        else</line>
<line>            new_pc_value = if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then ELR_hyp else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[14];</line>
<line>            <a link="AArch32.ExceptionReturn.2" file="shared_pseudocode.xml" hover="function: AArch32.ExceptionReturn(bits(32) new_pc_in, bits(32) spsr)">AArch32.ExceptionReturn</a>(new_pc_value, <a link="impl-shared.SPSR.read.0" file="shared_pseudocode.xml" hover="accessor: bits(N) SPSR[]">SPSR</a>[]);</line>
<line>    else                                          // Perform DRPS operation in Debug state</line>
<line>        if PSTATE.M == <a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a> then</line>
<line>            UNDEFINED;</line>
<line>        elsif PSTATE.M == <a link="M32_System" file="shared_pseudocode.xml" hover="constant bits(5) M32_System = '11111'">M32_System</a> then</line>
<line>            UNPREDICTABLE;                        // UNDEFINED or NOP</line>
<line>        else</line>
<line>            <a link="impl-shared.SynchronizeContext.0" file="shared_pseudocode.xml" hover="function: SynchronizeContext()">SynchronizeContext</a>();</line>
<line>            <a link="impl-shared.DebugRestorePSR.0" file="shared_pseudocode.xml" hover="function: DebugRestorePSR()">DebugRestorePSR</a>();</line>
</pstext>
    </ps>
  </ps_section>
  <constrained_unpredictables ps_block="Operation">
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>PSTATE.M IN {M32_User,M32_System}</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
    </cu_case>
  </constrained_unpredictables>
</instructionsection>
</file>
<file type="instructionsection" file="esb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ESB" title="ESB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="ESB" />
  </docvars>
  <heading>ESB</heading>
  <desc>
    <brief>
      <para>Error Synchronization Barrier</para>
    </brief>
    <authored>
      <para>Error Synchronization Barrier is an error synchronization event that might also update DISR and VDISR. This instruction can be used at all Exception levels and in Debug state.</para>
      <para>In Debug state, this instruction behaves as if SError interrupts are masked at all Exception levels. See Error Synchronization Barrier in the ARM(R) Reliability, Availability, and Serviceability (RAS) Specification, Armv8, for Armv8-A architecture profile.</para>
      <para>If the RAS Extension is not implemented, this instruction executes as a <instruction>NOP</instruction>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="ESB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_RAS" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/ESB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="R" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="imm4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" width="12" name="imm12" settings="12">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="ESB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ESB" />
        </docvars>
        <asmtemplate><text>ESB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ESB/A1_A.txt" mylink="aarch32.instrs.ESB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveRASExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveRASExt()">HaveRASExt</a>() then <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();  // Instruction executes as NOP</line>
<line>if cond != '1110' then UNPREDICTABLE;      // ESB must be encoded with AL condition</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNCOND" />
          <cu_type constraint="Constraint_COND" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ESB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_RAS" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/ESB/T1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="hint" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="option" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="ESB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ESB" />
        </docvars>
        <asmtemplate><text>ESB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ESB/T1_A.txt" mylink="aarch32.instrs.ESB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveRASExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveRASExt()">HaveRASExt</a>() then <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();  // Instruction executes as NOP</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNCOND" />
          <cu_type constraint="Constraint_COND" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ESB_A1, ESB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ESB_A1, ESB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/ESB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line></line>
<line>    <a link="impl-shared.SynchronizeErrors.0" file="shared_pseudocode.xml" hover="function: SynchronizeErrors()">SynchronizeErrors</a>();</line>
<line>    <a link="AArch32.ESBOperation.0" file="shared_pseudocode.xml" hover="function: AArch32.ESBOperation()">AArch32.ESBOperation</a>();</line>
<line>    if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then <a link="AArch32.vESBOperation.0" file="shared_pseudocode.xml" hover="function: AArch32.vESBOperation()">AArch32.vESBOperation</a>();</line>
<line>    <a link="impl-shared.TakeUnmaskedSErrorInterrupts.0" file="shared_pseudocode.xml" hover="function: TakeUnmaskedSErrorInterrupts()">TakeUnmaskedSErrorInterrupts</a>();</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="fldmx.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="FLDMX" title="FLDM*X (FLDMDBX, FLDMIAX) -- AArch32" type="instruction">
  <docvars>
    <docvar key="fpdatasize" value="doubleprec" />
    <docvar key="instr-class" value="fpsimd" />
  </docvars>
  <heading>FLDM*X (FLDMDBX, FLDMIAX)</heading>
  <desc>
    <brief>
      <para>FLDM*X</para>
    </brief>
    <authored>
      <para>FLDMDBX is the Decrement Before variant of this instruction, and FLDMIAX is the Increment After variant. FLDM*X loads multiple SIMD&amp;FP registers from consecutive locations in the Advanced SIMD and floating-point register file using an address from a general-purpose register.</para>
      <para>Arm deprecates use of FLDMDBX and FLDMIAX, except for disassembly purposes, and reassembly of disassembled code.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simdfp_mov64">Advanced SIMD and floating-point 64-bit move</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.movsimdfpgp64">Advanced SIMD and floating-point 64-bit move</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="fpdatasize" value="doubleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLDM/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="7" name="imm8&lt;7:1&gt;" usename="1">
          <c colspan="7"></c>
        </box>
        <box hibit="0" name="imm8&lt;0&gt;" usename="1" settings="1">
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="FLDMDBX_A1" oneofinclass="2" oneof="4" label="Decrement Before" bitdiffs="P == 1 &amp;&amp; U == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="FLDMDBX" />
          <docvar key="mnemonic-fpdatasize" value="FLDMDBX-doubleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>FLDMDBX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>!, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
      </encoding>
      <encoding name="FLDMIAX_A1" oneofinclass="2" oneof="4" label="Increment After" bitdiffs="P == 0 &amp;&amp; U == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="inc-after" />
          <docvar key="mnemonic" value="FLDMIAX" />
          <docvar key="mnemonic-fpdatasize" value="FLDMIAX-doubleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>1</c>
        </box>
        <asmtemplate><text>FLDMIAX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="Specifies base register writeback (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLDM/T1A1_A.txt" mylink="aarch32.instrs.VLDM.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; U == '0' &amp;&amp; W == '0' then SEE "Related encodings";</line>
<line>if P == '1' &amp;&amp; W == '0' then SEE "VLDR";</line>
<line>if P == U &amp;&amp; W == '1' then UNDEFINED;</line>
<line>// Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)</line>
<line>single_regs = FALSE;  add = (U == '1');  wback = (W == '1');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
<line>regs = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm8) DIV 2;  // If UInt(imm8) is odd, see "FLDM*X".</line>
<line>if n == 15 &amp;&amp; (wback || <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>) then UNPREDICTABLE;</line>
<line>if regs == 0 || regs &gt; 16 || (d+regs) &gt; 32 then UNPREDICTABLE;</line>
<line>if imm8&lt;0&gt; == '1' &amp;&amp; (d+regs) &gt; 16 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>regs == 0</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction operates as a <instruction>VLDM</instruction> with the same addressing mode but loads no registers.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>regs &gt; 16 || (d+regs) &gt; 16</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="fpdatasize" value="doubleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLDM/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="7" name="imm8&lt;7:1&gt;" usename="1">
          <c colspan="7"></c>
        </box>
        <box hibit="0" name="imm8&lt;0&gt;" usename="1" settings="1">
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="FLDMDBX_T1" oneofinclass="2" oneof="4" label="Decrement Before" bitdiffs="P == 1 &amp;&amp; U == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="FLDMDBX" />
          <docvar key="mnemonic-fpdatasize" value="FLDMDBX-doubleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>FLDMDBX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>!, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
      </encoding>
      <encoding name="FLDMIAX_T1" oneofinclass="2" oneof="4" label="Increment After" bitdiffs="P == 0 &amp;&amp; U == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="ldmstm-mode" value="inc-after" />
          <docvar key="mnemonic" value="FLDMIAX" />
          <docvar key="mnemonic-fpdatasize" value="FLDMIAX-doubleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>1</c>
        </box>
        <asmtemplate><text>FLDMIAX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="Specifies base register writeback (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLDM/T1A1_A.txt" mylink="aarch32.instrs.VLDM.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; U == '0' &amp;&amp; W == '0' then SEE "Related encodings";</line>
<line>if P == '1' &amp;&amp; W == '0' then SEE "VLDR";</line>
<line>if P == U &amp;&amp; W == '1' then UNDEFINED;</line>
<line>// Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)</line>
<line>single_regs = FALSE;  add = (U == '1');  wback = (W == '1');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
<line>regs = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm8) DIV 2;  // If UInt(imm8) is odd, see "FLDM*X".</line>
<line>if n == 15 &amp;&amp; (wback || <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>) then UNPREDICTABLE;</line>
<line>if regs == 0 || regs &gt; 16 || (d+regs) &gt; 32 then UNPREDICTABLE;</line>
<line>if imm8&lt;0&gt; == '1' &amp;&amp; (d+regs) &gt; 16 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>regs == 0</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction operates as a <instruction>VLDM</instruction> with the same addressing mode but loads no registers.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>regs &gt; 16 || (d+regs) &gt; 16</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="FLDMIAX_A1, FLDMIAX_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FLDMIAX_A1, FLDMIAX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FLDMIAX_A1, FLDMIAX_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field. If writeback is not specified, the PC can be used.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FLDMIAX_A1, FLDMIAX_T1" symboldefcount="1">
      <symbol link="sa_0d33">!</symbol>
      <account encodedin="W">
        <intro>
          <para>Specifies base register writeback. Encoded in the "W" field as 1 if present, otherwise 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FLDMIAX_A1, FLDMIAX_T1" symboldefcount="1">
      <symbol link="sa_dreglist">&lt;dreglist&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the list of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred. The first register in the list is encoded in "D:Vd", and "imm8" is set to twice the number of registers in the list plus one. The list must contain at least one register, all registers must be in the range D0-D15, and must not contain more than 16 registers.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VLDM/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    address = if add then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]-imm32;</line>
<line></line>
<line>    for r = 0 to regs-1</line>
<line>        if single_regs then</line>
<line>            <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d+r] = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,4];</line>
<line>            address = address+4;</line>
<line>        else</line>
<line>            word1 = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,4];</line>
<line>            word2 = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address+4,4];</line>
<line>            address = address+8;</line>
<line></line>
<line>            // Combine the word-aligned words in the correct order for current endianness.</line>
<line>            <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_ASIMD" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_ASIMD</a>) then word1:word2 else word2:word1;</line>
<line></line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = if add then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]+imm32 else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]-imm32;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="fstmx.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="FSTMX" title="FSTMDBX, FSTMIAX -- AArch32" type="instruction">
  <docvars>
    <docvar key="fpdatasize" value="doubleprec" />
    <docvar key="instr-class" value="fpsimd" />
  </docvars>
  <heading>FSTMDBX, FSTMIAX</heading>
  <desc>
    <brief>
      <para>FSTMX</para>
    </brief>
    <authored>
      <para>FSTMX stores multiple SIMD&amp;FP registers from the Advanced SIMD and floating-point register file to consecutive locations in using an address from a general-purpose register.</para>
      <para>Arm deprecates use of FSTMDBX and FSTMIAX, except for disassembly purposes, and reassembly of disassembled code.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simdfp_mov64">Advanced SIMD and floating-point 64-bit move</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.movsimdfpgp64">Advanced SIMD and floating-point 64-bit move</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="fpdatasize" value="doubleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSTM/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="7" name="imm8&lt;7:1&gt;" usename="1">
          <c colspan="7"></c>
        </box>
        <box hibit="0" name="imm8&lt;0&gt;" usename="1" settings="1">
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="FSTMDBX_A1" oneofinclass="2" oneof="4" label="Decrement Before" bitdiffs="P == 1 &amp;&amp; U == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="FSTMDBX" />
          <docvar key="mnemonic-fpdatasize" value="FSTMDBX-doubleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>FSTMDBX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>!, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
      </encoding>
      <encoding name="FSTMIAX_A1" oneofinclass="2" oneof="4" label="Increment After" bitdiffs="P == 0 &amp;&amp; U == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="inc-after" />
          <docvar key="mnemonic" value="FSTMIAX" />
          <docvar key="mnemonic-fpdatasize" value="FSTMIAX-doubleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>1</c>
        </box>
        <asmtemplate><text>FSTMIAX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="Specifies base register writeback (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSTM/T1A1_A.txt" mylink="aarch32.instrs.VSTM.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; U == '0' &amp;&amp; W == '0' then SEE "Related encodings";</line>
<line>if P == '1' &amp;&amp; W == '0' then SEE "VSTR";</line>
<line>if P == U &amp;&amp; W == '1' then UNDEFINED;</line>
<line>// Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)</line>
<line>single_regs = FALSE;  add = (U == '1');  wback = (W == '1');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
<line>regs = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm8) DIV 2;  // If UInt(imm8) is odd, see "FSTDBMX, FSTMIAX".</line>
<line>if n == 15 &amp;&amp; (wback || <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>) then UNPREDICTABLE;</line>
<line>if regs == 0 || regs &gt; 16 || (d+regs) &gt; 32 then UNPREDICTABLE;</line>
<line>if imm8&lt;0&gt; == '1' &amp;&amp; (d+regs) &gt; 16 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>regs == 0</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction operates as a <instruction>VSTM</instruction> with the same addressing mode but stores no registers.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>regs &gt; 16 || (d+regs) &gt; 16</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="fpdatasize" value="doubleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSTM/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="7" name="imm8&lt;7:1&gt;" usename="1">
          <c colspan="7"></c>
        </box>
        <box hibit="0" name="imm8&lt;0&gt;" usename="1" settings="1">
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="FSTMDBX_T1" oneofinclass="2" oneof="4" label="Decrement Before" bitdiffs="P == 1 &amp;&amp; U == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="FSTMDBX" />
          <docvar key="mnemonic-fpdatasize" value="FSTMDBX-doubleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>FSTMDBX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>!, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
      </encoding>
      <encoding name="FSTMIAX_T1" oneofinclass="2" oneof="4" label="Increment After" bitdiffs="P == 0 &amp;&amp; U == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="ldmstm-mode" value="inc-after" />
          <docvar key="mnemonic" value="FSTMIAX" />
          <docvar key="mnemonic-fpdatasize" value="FSTMIAX-doubleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>1</c>
        </box>
        <asmtemplate><text>FSTMIAX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="Specifies base register writeback (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSTM/T1A1_A.txt" mylink="aarch32.instrs.VSTM.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; U == '0' &amp;&amp; W == '0' then SEE "Related encodings";</line>
<line>if P == '1' &amp;&amp; W == '0' then SEE "VSTR";</line>
<line>if P == U &amp;&amp; W == '1' then UNDEFINED;</line>
<line>// Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)</line>
<line>single_regs = FALSE;  add = (U == '1');  wback = (W == '1');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
<line>regs = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm8) DIV 2;  // If UInt(imm8) is odd, see "FSTDBMX, FSTMIAX".</line>
<line>if n == 15 &amp;&amp; (wback || <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>) then UNPREDICTABLE;</line>
<line>if regs == 0 || regs &gt; 16 || (d+regs) &gt; 32 then UNPREDICTABLE;</line>
<line>if imm8&lt;0&gt; == '1' &amp;&amp; (d+regs) &gt; 16 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>regs == 0</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction operates as a <instruction>VSTM</instruction> with the same addressing mode but stores no registers.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>regs &gt; 16 || (d+regs) &gt; 16</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="FSTMIAX_A1, FSTMIAX_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FSTMIAX_A1, FSTMIAX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FSTMIAX_A1, FSTMIAX_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field. If writeback is not specified, the PC can be used. However, Arm deprecates use of the PC.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FSTMIAX_A1, FSTMIAX_T1" symboldefcount="1">
      <symbol link="sa_0d33">!</symbol>
      <account encodedin="W">
        <intro>
          <para>Specifies base register writeback. Encoded in the "W" field as 1 if present, otherwise 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FSTMIAX_A1, FSTMIAX_T1" symboldefcount="1">
      <symbol link="sa_dreglist">&lt;dreglist&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the list of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred. The first register in the list is encoded in "D:Vd", and "imm8" is set to twice the number of registers in the list plus one. The list must contain at least one register, all registers must be in the range D0-D15, and must not contain more than 16 registers.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VSTM/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    address = if add then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]-imm32;</line>
<line>    for r = 0 to regs-1</line>
<line>        if single_regs then</line>
<line>            <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,4] = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d+r];</line>
<line>            address = address+4;</line>
<line>        else</line>
<line>            // Store as two word-aligned words in the correct order for current endianness.</line>
<line>            if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_ASIMD" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_ASIMD</a>) then</line>
<line>                <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,4] =  <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r]&lt;63:32&gt;;</line>
<line>                <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address+4,4] =  <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r]&lt;31:0&gt;;</line>
<line>            else</line>
<line>                <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,4] = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r]&lt;31:0&gt;;</line>
<line>                <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address+4,4] = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r]&lt;63:32&gt;;</line>
<line></line>
<line>            address = address+8;</line>
<line></line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = if add then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]+imm32 else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]-imm32;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="hlt.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="HLT" title="HLT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="HLT" />
  </docvars>
  <heading>HLT</heading>
  <desc>
    <brief>
      <para>Halting Breakpoint</para>
    </brief>
    <authored>
      <para>Halting breakpoint causes a software breakpoint to occur.</para>
      <para>Halting breakpoint is always unconditional, even inside an IT block.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="HLT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/HLT/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="HLT_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="HLT" />
        </docvars>
        <asmtemplate><text>HLT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a>{#}</a><a link="sa_imm_1" hover="16-bit unsigned immediate [0-65535] (field &quot;imm12:imm4&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/HLT/A1_A.txt" mylink="aarch32.instrs.HLT.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if EDSCR.HDE == '0' || !<a link="impl-shared.HaltingAllowed.0" file="shared_pseudocode.xml" hover="function: boolean HaltingAllowed()">HaltingAllowed</a>() then UNDEFINED;</line>
<line>if cond != '1110' then UNPREDICTABLE; // HLT must be encoded with AL condition</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNCOND" />
          <cu_type constraint="Constraint_COND" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="HLT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/HLT/T1_A.txt">
        <box hibit="31" width="10" settings="10">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
      </regdiagram>
      <encoding name="HLT_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="HLT" />
        </docvars>
        <asmtemplate><text>HLT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a>{#}</a><a link="sa_imm" hover="6-bit unsigned immediate [0-63] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/HLT/T1_A.txt" mylink="aarch32.instrs.HLT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if EDSCR.HDE == '0' || !<a link="impl-shared.HaltingAllowed.0" file="shared_pseudocode.xml" hover="function: boolean HaltingAllowed()">HaltingAllowed</a>() then UNDEFINED;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="HLT_A1, HLT_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. An <instruction>HLT</instruction> instruction must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="HLT_A1" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm12:imm4">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm12:imm4" field. This value is for assembly and disassembly only. It is ignored by the PE, but can be used by a debugger to store more information about the halting breakpoint.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="HLT_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm6">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is a 6-bit unsigned immediate, in the range 0 to 63, encoded in the "imm6" field. This value is for assembly and disassembly only. It is ignored by the PE, but can be used by a debugger to store more information about the halting breakpoint.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/HLT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations();</line>
<line>boolean is_async = FALSE;</line>
<line><a link="impl-shared.Halt.2" file="shared_pseudocode.xml" hover="function: Halt(bits(6) reason, boolean is_async)">Halt</a>(<a link="DebugHalt_HaltInstruction" file="shared_pseudocode.xml" hover="constant bits(6) DebugHalt_HaltInstruction = '101111'">DebugHalt_HaltInstruction</a>, is_async);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="hvc.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="HVC" title="HVC -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="HVC" />
  </docvars>
  <heading>HVC</heading>
  <desc>
    <brief>
      <para>Hypervisor Call</para>
    </brief>
    <authored>
      <para>Hypervisor Call causes a Hypervisor Call exception. For more information, see <xref linkend="BEIBEBHJ">Hypervisor Call (HVC) exception</xref>. Software executing at EL1 can use this instruction to call the hypervisor to request a service.</para>
      <para>The <instruction>HVC</instruction> instruction is <arm-defined-word>undefined</arm-defined-word>:</para>
      <list type="unordered">
        <listitem><content>When EL3 is implemented and using AArch64, and <xref linkend="AArch64.scr_el3">SCR_EL3</xref>.HCE is set to 0.</content></listitem>
        <listitem><content>In Non-secure EL1 modes when EL3 is implemented and using AArch32, and <xref linkend="AArch32.scr">SCR</xref>.HCE is set to 0.</content></listitem>
        <listitem><content>When EL3 is not implemented and either <xref linkend="AArch64.hcr_el2">HCR_EL2</xref>.HCD is set to 1 or <xref linkend="AArch32.hcr">HCR</xref>.HCD is set to 1.</content></listitem>
        <listitem><content>When EL2 is not implemented.</content></listitem>
        <listitem><content>In Secure state, if EL2 is not enabled in the current Security state.</content></listitem>
        <listitem><content>In User mode.</content></listitem>
      </list>
      <para>The <instruction>HVC</instruction> instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in Hyp mode when EL3 is implemented and using AArch32, and <xref linkend="AArch32.scr">SCR</xref>.HCE is set to 0.</para>
      <para>On executing an <instruction>HVC</instruction> instruction, the <xref linkend="AArch32.hsr">HSR, Hyp Syndrome Register</xref> reports the exception as a Hypervisor Call exception, using the EC value <hexnumber>0x12</hexnumber>, and captures the value of the immediate argument, see <xref linkend="BEIDBEAG">Use of the HSR</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="HVC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/HVC/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="HVC_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="HVC" />
        </docvars>
        <asmtemplate><text>HVC</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a>{#}</a><a link="sa_imm16_1" hover="16-bit unsigned immediate [0-65535] (field &quot;imm12:imm4&quot;)">&lt;imm16&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/HVC/A1_A.txt" mylink="aarch32.instrs.HVC.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if cond != '1110' then UNPREDICTABLE;</line>
<line>imm16 = imm12:imm4;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNCOND" />
          <cu_type constraint="Constraint_COND" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="HVC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/HVC/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="HVC_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="HVC" />
        </docvars>
        <asmtemplate><text>HVC</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a>{#}</a><a link="sa_imm16" hover="16-bit unsigned immediate [0-65535] (field &quot;imm4:imm12&quot;)">&lt;imm16&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/HVC/T1_A.txt" mylink="aarch32.instrs.HVC.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>imm16 = imm4:imm12;</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="HVC_A1, HVC_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. An <instruction>HVC</instruction> instruction must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="HVC_A1" symboldefcount="1">
      <symbol link="sa_imm16_1">&lt;imm16&gt;</symbol>
      <account encodedin="imm12:imm4">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm12:imm4" field. This value is for assembly and disassembly only. It is reported in the HSR but otherwise is ignored by hardware. An HVC handler might interpret imm16, for example to determine the required service.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="HVC_T1" symboldefcount="2">
      <symbol link="sa_imm16">&lt;imm16&gt;</symbol>
      <account encodedin="imm4:imm12">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm4:imm12" field. This value is for assembly and disassembly only. It is reported in the HSR but otherwise is ignored by hardware. An HVC handler might interpret imm16, for example to determine the required service.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/HVC/Op_AS.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations();</line>
<line>if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>} || !<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>    UNDEFINED;</line>
<line></line>
<line>bit hvc_enable;</line>
<line>if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>    if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR.HCE == '0' &amp;&amp; PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>        UNPREDICTABLE;</line>
<line>    else</line>
<line>        hvc_enable = <a link="impl-shared.SCR_GEN.read.0" file="shared_pseudocode.xml" hover="accessor: SCRType SCR_GEN[]">SCR_GEN</a>[].HCE;</line>
<line>else</line>
<line>    hvc_enable = if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then NOT(HCR.HCD) else NOT(HCR_EL2.HCD);</line>
<line></line>
<line>if hvc_enable == '0' then</line>
<line>    UNDEFINED;</line>
<line>else</line>
<line>    <a link="AArch32.CallHypervisor.1" file="shared_pseudocode.xml" hover="function: AArch32.CallHypervisor(bits(16) immediate)">AArch32.CallHypervisor</a>(imm16);</line>
</pstext>
    </ps>
  </ps_section>
  <constrained_unpredictables ps_block="Operation">
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>ELUsingAArch32(EL3) &amp;&amp; SCR.HCE == '0' &amp;&amp; PSTATE.EL == EL2</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
    </cu_case>
  </constrained_unpredictables>
</instructionsection>
</file>
<file type="instructionsection" file="isb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ISB" title="ISB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="ISB" />
  </docvars>
  <heading>ISB</heading>
  <desc>
    <brief>
      <para>Instruction Synchronization Barrier</para>
    </brief>
    <authored>
      <para>Instruction Synchronization Barrier flushes the pipeline in the PE and is a context synchronization event. For more information, see <xref linkend="AA32CHDHFJFC">Instruction Synchronization Barrier (ISB)</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="ISB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/ISB/A1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" name="opcode" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="option" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ISB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ISB" />
        </docvars>
        <asmtemplate><text>ISB</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_option" hover="Specifies an optional limitation on the barrier operation">&lt;option&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ISB/A1_A.txt" mylink="aarch32.instrs.ISB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ISB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/ISB/T1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="option" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ISB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ISB" />
        </docvars>
        <asmtemplate><text>ISB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_option" hover="Specifies an optional limitation on the barrier operation">&lt;option&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ISB/T1_A.txt" mylink="aarch32.instrs.ISB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ISB_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. Must be <value>AL</value> or omitted.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ISB_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ISB_A1, ISB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ISB_A1, ISB_T1" symboldefcount="1">
      <symbol link="sa_option">&lt;option&gt;</symbol>
      <account encodedin="option">
        <intro>
          <para>Specifies an optional limitation on the barrier operation. Values are:</para>
          <list type="param">
            <listitem>
              <param>SY</param><content>Full system barrier operation, encoded as option = <binarynumber>0b1111</binarynumber>. Can be omitted.</content>
            </listitem>
          </list>
          <para>All other encodings of option are reserved. The corresponding instructions execute as full system barrier operations, but must not be relied upon by software.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/ISB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-shared.InstructionSynchronizationBarrier.0" file="shared_pseudocode.xml" hover="function: InstructionSynchronizationBarrier()">InstructionSynchronizationBarrier</a>();</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="it.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="IT" title="IT -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="T1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="T32" />
    <docvar key="mnemonic" value="IT" />
  </docvars>
  <heading>IT</heading>
  <desc>
    <brief>
      <para>If-Then</para>
    </brief>
    <authored>
      <para>If-Then makes up to four following instructions (the IT block) conditional. The conditions for the instructions in the IT block are the same as, or the inverse of, the condition the <instruction>IT</instruction> instruction specifies for the first instruction in the block.</para>
      <para>The <instruction>IT</instruction> instruction itself does not affect the condition flags, but the execution of the instructions in the IT block can change the condition flags.</para>
      <para>16-bit instructions in the IT block, other than <instruction>CMP</instruction>, <instruction>CMN</instruction> and <instruction>TST</instruction>, do not set the condition flags. An <instruction>IT</instruction> instruction with the <value>AL</value> condition can change the behavior without conditional execution.</para>
      <para>The architecture permits exception return to an instruction in the IT block only if the restoration of the <xref linkend="CIHJBHJA">CPSR</xref> restores <xref linkend="BEIDIGBH">PSTATE</xref>.IT to a state consistent with the conditions specified by the <instruction>IT</instruction> instruction.  Any other exception return to an instruction in an IT block is <arm-defined-word>unpredictable</arm-defined-word>. Any branch to a target instruction in an IT block is not permitted, and if such a branch is made it is <arm-defined-word>unpredictable</arm-defined-word> what condition is used when executing that target instruction and any subsequent instruction in the IT block.</para>
      <para>Many uses of the IT instruction are deprecated for performance reasons, and an implementation might include ITD controls that can disable those uses of IT, making them <arm-defined-word>undefined</arm-defined-word>.</para>
      <para>For more information see <xref linkend="BABGABFG">Conditional execution</xref> and <xref linkend="BABHIJHI">Conditional instructions</xref>. The first of these sections includes more information about the ITD controls.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
      <para>Related encodings: <xref linkend="T32.encoding_index.misc16">Miscellaneous 16-bit instructions</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>The conditions specified in an <instruction>IT</instruction> instruction must match those specified in the syntax of the instructions in its IT block. When assembling to A32 code, assemblers check <instruction>IT</instruction> instruction syntax for validity but do not generate assembled instructions for them. See <xref linkend="BABHIJHI">Conditional instructions</xref>.</para>
    </syntaxnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="T1" oneof="1" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="IT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/IT/T1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" width="4" name="firstcond" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="19" width="4" name="mask" usename="1" settings="4" constraint="!= 0000">
          <c colspan="4">!= 0000</c>
        </box>
      </regdiagram>
      <encoding name="IT_T1" oneofinclass="1" oneof="1" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="IT" />
        </docvars>
        <asmtemplate><text>IT</text><text>{</text><a link="sa_x" hover="The condition for second instruction in the IT block (field &quot;mask[3]&quot;)">&lt;x&gt;</a><text>{</text><a link="sa_y" hover="The condition for third instruction in the IT block (field &quot;mask[2]&quot;)">&lt;y&gt;</a><text>{</text><a link="sa_z" hover="The condition for fourth instruction in the IT block (field &quot;mask[1]&quot;)">&lt;z&gt;</a><text>}</text><text>}</text><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_cond" hover="The condition for first instruction in the IT block (field &quot;firstcond&quot;)">&lt;cond&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/IT/T1_A.txt" mylink="aarch32.instrs.IT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if mask == '0000' then SEE "Related encodings";</line>
<line>if firstcond == '1111' || (firstcond == '1110' &amp;&amp; <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(mask) != 1) then UNPREDICTABLE;</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>firstcond == '1111' || (firstcond == '1110' &amp;&amp; BitCount(mask) != 1)</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The '1111' condition is treated as being the same as the '1110' condition, meaning always, and the ITSTATE state machine is progressed in the same way as for any other cond_base value.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="IT_T1" symboldefcount="1">
      <symbol link="sa_x">&lt;x&gt;</symbol>
      <account encodedin="mask[3]">
        <intro>
          <para>The condition for the second instruction in the IT block. If omitted, the "mask" field is set to <binarynumber>0b1000</binarynumber>. If present it is encoded in the "mask[3]" field:</para>
          <list type="param">
            <listitem>
              <param>T</param><content>firstcond[0]</content>
            </listitem>
            <listitem>
              <param>E</param><content>NOT firstcond[0]</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="IT_T1" symboldefcount="1">
      <symbol link="sa_y">&lt;y&gt;</symbol>
      <account encodedin="mask[2]">
        <intro>
          <para>The condition for the third instruction in the IT block. If omitted and <syntax>&lt;x&gt;</syntax> is present, the "mask[2:0]" field is set to <binarynumber>0b100</binarynumber>. If <syntax>&lt;y&gt;</syntax> is present it is encoded in the "mask[2]" field:</para>
          <list type="param">
            <listitem>
              <param>T</param><content>firstcond[0]</content>
            </listitem>
            <listitem>
              <param>E</param><content>NOT firstcond[0]</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="IT_T1" symboldefcount="1">
      <symbol link="sa_z">&lt;z&gt;</symbol>
      <account encodedin="mask[1]">
        <intro>
          <para>The condition for the fourth instruction in the IT block. If omitted and <syntax>&lt;y&gt;</syntax> is present, the "mask[1:0]" field is set to <binarynumber>0b10</binarynumber>. If <syntax>&lt;z&gt;</syntax> is present, the "mask[0]" field is set to 1, and it is encoded in the "mask[1]" field:</para>
          <list type="param">
            <listitem>
              <param>T</param><content>firstcond[0]</content>
            </listitem>
            <listitem>
              <param>E</param><content>NOT firstcond[0]</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="IT_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="IT_T1" symboldefcount="1">
      <symbol link="sa_cond">&lt;cond&gt;</symbol>
      <account encodedin="firstcond">
        <intro>
          <para>The condition for the first instruction in the IT block, encoded in the "firstcond" field. See <xref linkend="Chdcgdjb">Condition codes</xref> for the range of conditions available, and the encodings.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/IT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations();</line>
<line><a link="AArch32.CheckITEnabled.1" file="shared_pseudocode.xml" hover="function: AArch32.CheckITEnabled(bits(4) mask)">AArch32.CheckITEnabled</a>(mask);</line>
<line>PSTATE.IT&lt;7:0&gt; = firstcond:mask;</line>
<line>ShouldAdvanceIT = FALSE;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="lda.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDA" title="LDA -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDA" />
  </docvars>
  <heading>LDA</heading>
  <desc>
    <brief>
      <para>Load-Acquire Word</para>
    </brief>
    <authored>
      <para>Load-Acquire Word loads a word from memory and writes it to a register. The instruction also has memory ordering semantics as described in <xref linkend="AA32CHDBDIDF">Load-Acquire, Store-Release</xref></para>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDA" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDA/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="xRt" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDA_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDA" />
        </docvars>
        <asmtemplate><text>LDA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDA/A1_A.txt" mylink="aarch32.instrs.LDA.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDA" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDA/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="sz" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rd" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDA_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDA" />
        </docvars>
        <asmtemplate><text>LDA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDA/T1_A.txt" mylink="aarch32.instrs.LDA.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDA_A1, LDA_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDA_A1, LDA_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDA_A1, LDA_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDA_A1, LDA_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-aarch32.MemO.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemO[bits(32) address, integer size]">MemO</a>[address, 4];</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldab.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDAB" title="LDAB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDAB" />
  </docvars>
  <heading>LDAB</heading>
  <desc>
    <brief>
      <para>Load-Acquire Byte</para>
    </brief>
    <authored>
      <para>Load-Acquire Byte loads a byte from memory, zero-extends it to form a 32-bit word and writes it to a register. The instruction also has memory ordering semantics as described in <xref linkend="AA32CHDBDIDF">Load-Acquire, Store-Release</xref>.</para>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDAB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDAB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="xRt" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDAB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDAB" />
        </docvars>
        <asmtemplate><text>LDAB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDAB/A1_A.txt" mylink="aarch32.instrs.LDAB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDAB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDAB/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="sz" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rd" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDAB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDAB" />
        </docvars>
        <asmtemplate><text>LDAB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDAB/T1_A.txt" mylink="aarch32.instrs.LDAB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDAB_A1, LDAB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDAB_A1, LDAB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDAB_A1, LDAB_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDAB_A1, LDAB_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDAB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-aarch32.MemO.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemO[bits(32) address, integer size]">MemO</a>[address, 1], 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldaex.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDAEX" title="LDAEX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDAEX" />
  </docvars>
  <heading>LDAEX</heading>
  <desc>
    <brief>
      <para>Load-Acquire Exclusive Word</para>
    </brief>
    <authored>
      <para>Load-Acquire Exclusive Word loads a word from memory, writes it to a register and:</para>
      <list type="unordered">
        <listitem><content>If the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing PE in a global monitor.</content></listitem>
        <listitem><content>Causes the executing PE to indicate an active exclusive access in the local monitor.</content></listitem>
      </list>
      <para>The instruction also has memory ordering semantics as described in <xref linkend="AA32CHDBDIDF">Load-Acquire, Store-Release</xref>.</para>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDAEX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDAEX/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="xRt" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDAEX_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDAEX" />
        </docvars>
        <asmtemplate><text>LDAEX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDAEX/A1_A.txt" mylink="aarch32.instrs.LDAEX.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDAEX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDAEX/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" width="2" name="sz" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rd" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDAEX_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDAEX" />
        </docvars>
        <asmtemplate><text>LDAEX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDAEX/T1_A.txt" mylink="aarch32.instrs.LDAEX.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDAEX_A1, LDAEX_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDAEX_A1, LDAEX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDAEX_A1, LDAEX_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDAEX_A1, LDAEX_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDAEX/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    <a link="AArch32.SetExclusiveMonitors.2" file="shared_pseudocode.xml" hover="function: AArch32.SetExclusiveMonitors(bits(32) address, integer size)">AArch32.SetExclusiveMonitors</a>(address, 4);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-aarch32.MemO.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemO[bits(32) address, integer size]">MemO</a>[address, 4];</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldaexb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDAEXB" title="LDAEXB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDAEXB" />
  </docvars>
  <heading>LDAEXB</heading>
  <desc>
    <brief>
      <para>Load-Acquire Exclusive Byte</para>
    </brief>
    <authored>
      <para>Load-Acquire Exclusive Byte loads a byte from memory, zero-extends it to form a 32-bit word, writes it to a register and:</para>
      <list type="unordered">
        <listitem><content>If the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing PE in a global monitor.</content></listitem>
        <listitem><content>Causes the executing PE to indicate an active exclusive access in the local monitor.</content></listitem>
      </list>
      <para>The instruction also has memory ordering semantics as described in <xref linkend="AA32CHDBDIDF">Load-Acquire, Store-Release</xref>.</para>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDAEXB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDAEXB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="xRt" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDAEXB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDAEXB" />
        </docvars>
        <asmtemplate><text>LDAEXB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDAEXB/A1_A.txt" mylink="aarch32.instrs.LDAEXB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDAEXB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDAEXB/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" width="2" name="sz" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rd" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDAEXB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDAEXB" />
        </docvars>
        <asmtemplate><text>LDAEXB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDAEXB/T1_A.txt" mylink="aarch32.instrs.LDAEXB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDAEXB_A1, LDAEXB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDAEXB_A1, LDAEXB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDAEXB_A1, LDAEXB_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDAEXB_A1, LDAEXB_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDAEXB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    <a link="AArch32.SetExclusiveMonitors.2" file="shared_pseudocode.xml" hover="function: AArch32.SetExclusiveMonitors(bits(32) address, integer size)">AArch32.SetExclusiveMonitors</a>(address, 1);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-aarch32.MemO.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemO[bits(32) address, integer size]">MemO</a>[address, 1], 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldaexd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDAEXD" title="LDAEXD -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDAEXD" />
  </docvars>
  <heading>LDAEXD</heading>
  <desc>
    <brief>
      <para>Load-Acquire Exclusive Doubleword</para>
    </brief>
    <authored>
      <para>Load-Acquire Exclusive Doubleword loads a doubleword from memory, writes it to two registers and:</para>
      <list type="unordered">
        <listitem><content>If the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing PE in a global monitor</content></listitem>
        <listitem><content>Causes the executing PE to indicate an active exclusive access in the local monitor.</content></listitem>
      </list>
      <para>The instruction also acts as a barrier instruction with the ordering requirements described in <xref linkend="AA32CHDBDIDF">Load-Acquire, Store-Release</xref>.</para>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDAEXD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDAEXD/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="xRt" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDAEXD_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDAEXD" />
        </docvars>
        <asmtemplate><text>LDAEXD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2_1" hover="Second general-purpose register to be transferred">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDAEXD/A1_A.txt" mylink="aarch32.instrs.LDAEXD.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = t + 1;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if Rt&lt;0&gt; == '1' || t2 == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>Rt&lt;0&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="t&lt;0&gt; = '0'" />
          </cu_type>
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="t2 = t" />
          </cu_type>
          <cu_type constraint="Constraint_NONE" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>Rt == '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDAEXD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDAEXD/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" width="2" name="sz" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rd" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDAEXD_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDAEXD" />
        </docvars>
        <asmtemplate><text>LDAEXD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDAEXD/T1_A.txt" mylink="aarch32.instrs.LDAEXD.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || t2 == 15 || t == t2 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == t2</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_LDUNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDAEXD_A1, LDAEXD_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDAEXD_A1, LDAEXD_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDAEXD_A1" symboldefcount="1">
      <symbol link="sa_rt_1">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the first general-purpose register to be transferred, encoded in the "Rt" field. <syntax>&lt;Rt&gt;</syntax> must be even-numbered and not R14.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDAEXD_T1" symboldefcount="2">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the first general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDAEXD_A1" symboldefcount="1">
      <symbol link="sa_rt2_1">&lt;Rt2&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the second general-purpose register to be transferred. <syntax>&lt;Rt2&gt;</syntax> must be <syntax>&lt;R(t+1)&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDAEXD_T1" symboldefcount="2">
      <symbol link="sa_rt2">&lt;Rt2&gt;</symbol>
      <account encodedin="Rt2">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the second general-purpose register to be transferred, encoded in the "Rt2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDAEXD_A1, LDAEXD_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDAEXD/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    <a link="AArch32.SetExclusiveMonitors.2" file="shared_pseudocode.xml" hover="function: AArch32.SetExclusiveMonitors(bits(32) address, integer size)">AArch32.SetExclusiveMonitors</a>(address, 8);</line>
<line>    value = <a link="impl-aarch32.MemO.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemO[bits(32) address, integer size]">MemO</a>[address, 8];</line>
<line>    // Extract words from 64-bit loaded value such that R[t] is</line>
<line>    // loaded from address and R[t2] from address+4.</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t]  = if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>) then value&lt;63:32&gt; else value&lt;31:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t2] = if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>) then value&lt;31:0&gt;  else value&lt;63:32&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldaexh.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDAEXH" title="LDAEXH -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDAEXH" />
  </docvars>
  <heading>LDAEXH</heading>
  <desc>
    <brief>
      <para>Load-Acquire Exclusive Halfword</para>
    </brief>
    <authored>
      <para>Load-Acquire Exclusive Halfword loads a halfword from memory, zero-extends it to form a 32-bit word, writes it to a register and:</para>
      <list type="unordered">
        <listitem><content>If the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing PE in a global monitor.</content></listitem>
        <listitem><content>Causes the executing PE to indicate an active exclusive access in the local monitor.</content></listitem>
      </list>
      <para>The instruction also has memory ordering semantics as described in <xref linkend="AA32CHDBDIDF">Load-Acquire, Store-Release</xref>.</para>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDAEXH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDAEXH/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="xRt" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDAEXH_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDAEXH" />
        </docvars>
        <asmtemplate><text>LDAEXH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDAEXH/A1_A.txt" mylink="aarch32.instrs.LDAEXH.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDAEXH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDAEXH/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" width="2" name="sz" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rd" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDAEXH_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDAEXH" />
        </docvars>
        <asmtemplate><text>LDAEXH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDAEXH/T1_A.txt" mylink="aarch32.instrs.LDAEXH.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDAEXH_A1, LDAEXH_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDAEXH_A1, LDAEXH_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDAEXH_A1, LDAEXH_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDAEXH_A1, LDAEXH_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDAEXH/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    <a link="AArch32.SetExclusiveMonitors.2" file="shared_pseudocode.xml" hover="function: AArch32.SetExclusiveMonitors(bits(32) address, integer size)">AArch32.SetExclusiveMonitors</a>(address, 2);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-aarch32.MemO.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemO[bits(32) address, integer size]">MemO</a>[address, 2], 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldah.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDAH" title="LDAH -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDAH" />
  </docvars>
  <heading>LDAH</heading>
  <desc>
    <brief>
      <para>Load-Acquire Halfword</para>
    </brief>
    <authored>
      <para>Load-Acquire Halfword loads a halfword from memory, zero-extends it to form a 32-bit word and writes it to a register. The instruction also has memory ordering semantics as described in <xref linkend="AA32CHDBDIDF">Load-Acquire, Store-Release</xref>.</para>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDAH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDAH/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="xRt" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDAH_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDAH" />
        </docvars>
        <asmtemplate><text>LDAH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDAH/A1_A.txt" mylink="aarch32.instrs.LDAH.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDAH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDAH/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="sz" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rd" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDAH_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDAH" />
        </docvars>
        <asmtemplate><text>LDAH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDAH/T1_A.txt" mylink="aarch32.instrs.LDAH.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDAH_A1, LDAH_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDAH_A1, LDAH_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDAH_A1, LDAH_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDAH_A1, LDAH_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDAH/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-aarch32.MemO.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemO[bits(32) address, integer size]">MemO</a>[address, 2], 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldc_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDC_i" title="LDC (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDC" />
  </docvars>
  <heading>LDC (immediate)</heading>
  <desc>
    <brief>
      <para>Load data to System register (immediate)</para>
    </brief>
    <authored>
      <para>Load data to System register (immediate) calculates an address from a base register value and an immediate offset, loads a word from memory, and writes it to the <xref linkend="AArch32.dbgdtrtxint">DBGDTRTXint</xref> System register. It can use offset, post-indexed, pre-indexed, or unindexed addressing. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
      <para>In an implementation that includes EL2, the permitted <instruction>LDC</instruction> access to <xref linkend="AArch32.dbgdtrtxint">DBGDTRTXint</xref> can be trapped to Hyp mode, meaning that an attempt to execute an <instruction>LDC</instruction> instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception.  For more information, see <xref linkend="BEICAABI">Trapping general Non-secure System register accesses to debug registers</xref>.</para>
      <para>For simplicity, the <instruction>LDC</instruction> pseudocode does not show this possible trap to Hyp mode.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDC" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDC_i/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="CRd" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" name="cp15" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="LDC_i_A1_off" oneofinclass="4" oneof="8" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDC" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> p14, c5, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="Immediate offset used for forming the address (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDC_i_A1_post" oneofinclass="4" oneof="8" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDC" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> p14, c5, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="Immediate offset used for forming the address (field &quot;imm8&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="LDC_i_A1_pre" oneofinclass="4" oneof="8" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDC" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> p14, c5, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="Immediate offset used for forming the address (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="LDC_i_A1_unind" oneofinclass="4" oneof="8" label="Unindexed" bitdiffs="P == 0 &amp;&amp; U == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="unindexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDC" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> p14, c5, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa_option" hover="8-bit immediate [0-255 enclosed in { }] (field &quot;imm8&quot;)">&lt;option&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDC_i/T1A1_A.txt" mylink="aarch32.instrs.LDC_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "LDC (literal)";</line>
<line>if P == '0' &amp;&amp; U == '0' &amp;&amp; W == '0' then UNDEFINED;</line>
<line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  cp = 14;</line>
<line>imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);  index = (P == '1');  add = (U == '1');  wback = (W == '1');</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDC" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDC_i/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="CRd" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" name="cp15" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="LDC_i_T1_off" oneofinclass="4" oneof="8" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDC" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> p14, c5, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="Immediate offset used for forming the address (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDC_i_T1_post" oneofinclass="4" oneof="8" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDC" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> p14, c5, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="Immediate offset used for forming the address (field &quot;imm8&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="LDC_i_T1_pre" oneofinclass="4" oneof="8" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDC" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> p14, c5, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="Immediate offset used for forming the address (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="LDC_i_T1_unind" oneofinclass="4" oneof="8" label="Unindexed" bitdiffs="P == 0 &amp;&amp; U == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="unindexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDC" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> p14, c5, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa_option" hover="8-bit immediate [0-255 enclosed in { }] (field &quot;imm8&quot;)">&lt;option&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDC_i/T1A1_A.txt" mylink="aarch32.instrs.LDC_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "LDC (literal)";</line>
<line>if P == '0' &amp;&amp; U == '0' &amp;&amp; W == '0' then UNDEFINED;</line>
<line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  cp = 14;</line>
<line>imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);  index = (P == '1');  add = (U == '1');  wback = (W == '1');</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDC_i_A1_off, LDC_i_T1_off" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDC_i_A1_off, LDC_i_T1_off" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDC_i_A1_off, LDC_i_T1_off" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field. If the PC is used, see <xref linkend="A32T32-base.instructions.LDC_l">LDC (literal)</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDC_i_A1_unind, LDC_i_T1_unind" symboldefcount="1">
      <symbol link="sa_option">&lt;option&gt;</symbol>
      <account encodedin="imm8">
        <intro>
          <para>Is an 8-bit immediate, in the range 0 to 255 enclosed in { }, encoded in the "imm8" field. The value of this field is ignored when executing this instruction.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDC_i_A1_off, LDC_i_T1_off" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDC_i_A1_off, LDC_i_T1_off" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <intro>
          <para>Is the immediate offset used for forming the address, a multiple of 4 in the range 0-1020, defaulting to 0 and encoded in the "imm8" field, as &lt;imm&gt;/4.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDC_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);</line>
<line>    address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line></line>
<line>    // System register write to DBGDTRTXint.</line>
<line>    <a link="AArch32.SysRegWriteM.3" file="shared_pseudocode.xml" hover="function: AArch32.SysRegWriteM(integer cp_num, bits(32) instr, bits(32) address)">AArch32.SysRegWriteM</a>(cp, <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>(), address);</line>
<line></line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldc_l.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDC_l" title="LDC (literal) -- AArch32" type="instruction">
  <docvars>
    <docvar key="address-form" value="literal" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDC" />
  </docvars>
  <heading>LDC (literal)</heading>
  <desc>
    <brief>
      <para>Load data to System register (literal)</para>
    </brief>
    <authored>
      <para>Load data to System register (literal) calculates an address from the PC value and an immediate offset, loads a word from memory, and writes it to the <xref linkend="AArch32.dbgdtrtxint">DBGDTRTXint</xref> System register. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
      <para>In an implementation that includes EL2, the permitted <instruction>LDC</instruction> access to <xref linkend="AArch32.dbgdtrtxint">DBGDTRTXint</xref> can be trapped to Hyp mode, meaning that an attempt to execute an <instruction>LDC</instruction> instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception.  For more information, see <xref linkend="BEICAABI">Trapping general Non-secure System register accesses to debug registers</xref>.</para>
      <para>For simplicity, the <instruction>LDC</instruction> pseudocode does not show this possible trap to Hyp mode.</para>
    </authored>
    <syntaxnotes>
      <para>The alternative syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see <xref linkend="BABGCIBA">Use of labels in UAL instruction syntax</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="address-form" value="literal" />
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDC_l/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="CRd" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" name="cp15" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="LDC_l_A1" oneofinclass="1" oneof="2" label="A1" bitdiffs="!(P == 0 &amp;&amp; U == 0 &amp;&amp; W == 0)">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDC" />
        </docvars>
        <box hibit="24" width="4" name="P:U:W">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
        </box>
        <asmtemplate><text>LDC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> p14, c5, </text><a link="sa_label" hover="The label of literal data item that is to be loaded into {syntax{&lt;Rt&gt;}}">&lt;label&gt;</a></asmtemplate>
        <asmtemplate><text>LDC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> p14, c5, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="Immediate offset used for forming the address (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
        <asmtemplate><text>LDC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> p14, c5, [PC], </text><a link="sa_option" hover="8-bit immediate [0-255 enclosed in { }] (field &quot;imm8&quot;)">&lt;option&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDC_l/T1A1_A.txt" mylink="aarch32.instrs.LDC_l.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; U == '0' &amp;&amp; W == '0' then UNDEFINED;</line>
<line>index = (P == '1');  add = (U == '1');  cp = 14;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
<line>if W == '1' || (P == '0' &amp;&amp; <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>W == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_WBSUPPRESS" />
          <cu_type>
            <cu_type_text>The instruction uses the addressing mode described in the equivalent immediate offset instruction.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="literal" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDC_l/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="CRd" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" name="cp15" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="LDC_l_T1" oneofinclass="1" oneof="2" label="T1" bitdiffs="!(P == 0 &amp;&amp; U == 0 &amp;&amp; W == 0)">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDC" />
        </docvars>
        <box hibit="24" width="4" name="P:U:W">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
        </box>
        <asmtemplate><text>LDC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> p14, c5, </text><a link="sa_label" hover="The label of literal data item that is to be loaded into {syntax{&lt;Rt&gt;}}">&lt;label&gt;</a></asmtemplate>
        <asmtemplate><text>LDC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> p14, c5, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="Immediate offset used for forming the address (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDC_l/T1A1_A.txt" mylink="aarch32.instrs.LDC_l.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; U == '0' &amp;&amp; W == '0' then UNDEFINED;</line>
<line>index = (P == '1');  add = (U == '1');  cp = 14;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
<line>if W == '1' || (P == '0' &amp;&amp; <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>W == '1' || P == '0'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_WBSUPPRESS" />
          <cu_type>
            <cu_type_text>The instruction executes as <instruction>LDC</instruction> (immediate) with writeback to the PC. The instruction is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDC_l_A1, LDC_l_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDC_l_A1, LDC_l_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDC_l_A1" symboldefcount="1">
      <symbol link="sa_option">&lt;option&gt;</symbol>
      <account encodedin="imm8">
        <intro>
          <para>Is an 8-bit immediate, in the range 0 to 255 enclosed in { }, encoded in the "imm8" field. The value of this field is ignored when executing this instruction.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDC_l_A1, LDC_l_T1" symboldefcount="1">
      <symbol link="sa_label">&lt;label&gt;</symbol>
      <account encodedin="imm8">
        <intro>
          <para>The label of the literal data item that is to be loaded into <syntax>&lt;Rt&gt;</syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the instruction to this label. Permitted values of the offset are multiples of 4 in the range -1020 to 1020.</para>
          <para>If the offset is zero or positive, <field>imm32</field> is equal to the offset and <field>add</field> == <enumvalue>TRUE</enumvalue> (encoded as U == 1).</para>
          <para>If the offset is negative, <field>imm32</field> is equal to minus the offset and <field>add</field> == <enumvalue>FALSE (encoded as U == 0)</enumvalue>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDC_l_A1, LDC_l_T1" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDC_l_A1, LDC_l_T1" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <intro>
          <para>Is the immediate offset used for forming the address, a multiple of 4 in the range 0-1020, defaulting to 0 and encoded in the "imm8" field, as &lt;imm&gt;/4.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDC_l/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    offset_addr = if add then (<a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4) + imm32) else (<a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4) - imm32);</line>
<line>    address = if index then offset_addr else <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4);</line>
<line></line>
<line>    // System register write to DBGDTRTXint.</line>
<line>    <a link="AArch32.SysRegWriteM.3" file="shared_pseudocode.xml" hover="function: AArch32.SysRegWriteM(integer cp_num, bits(32) instr, bits(32) address)">AArch32.SysRegWriteM</a>(cp, <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>(), address);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldm.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDM" title="LDM, LDMIA, LDMFD -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDM" />
  </docvars>
  <heading>LDM, LDMIA, LDMFD</heading>
  <desc>
    <brief>
      <para>Load Multiple (Increment After, Full Descending)</para>
    </brief>
    <authored>
      <para>Load Multiple (Increment After, Full Descending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations start at this address, and the address just above the highest of those locations can optionally be written back to the base register.</para>
      <para>The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register from the highest memory address. See also <xref linkend="CHDDBEDG">Encoding of lists of general-purpose registers and the PC</xref>.</para>
      <para>Armv8.2 permits the deprecation of some Load Multiple ordering behaviors in AArch32 state, for more information see <xref linkend="v8.2.LSMAOC">FEAT_LSMAOC</xref>. The registers loaded can include the PC, causing a branch to a loaded address. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>. Related system instructions are <xref linkend="A32T32-base.instructions.LDM_u">LDM (User registers)</xref> and <xref linkend="A32T32-base.instructions.LDM_e">LDM (exception return)</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="1">
    <alias_list_intro>This instruction is used by the alias </alias_list_intro>
    <aliasref aliaspageid="POP_LDM" aliasfile="pop_ldm.xml" hover="Pop Multiple Registers from Stack" punct=".">
      <text>POP (multiple registers)</text>
      <aliaspref labels="T2">W == '1' &amp;&amp; Rn == '1101' &amp;&amp; <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(P:M:register_list) &gt; 1</aliaspref>
      <aliaspref labels="A1">W == '1' &amp;&amp; Rn == '1101' &amp;&amp; <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(register_list) &gt; 1</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink />
      <text> below for details of when the alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDM/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="16" name="register_list" usename="1">
          <c colspan="16"></c>
        </box>
      </regdiagram>
      <encoding name="LDM_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDM" />
        </docvars>
        <asmtemplate comment="Preferred syntax"><text>LDM</text><a link="sa_ia" hover="Optional suffix for Increment After form">{IA}</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33_1" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers_2" hover="List of one or more registers to be loaded">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate comment="Alternate syntax, Full Descending stack"><text>LDMFD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33_1" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers_2" hover="List of one or more registers to be loaded">&lt;registers&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDM/A1_A.txt" mylink="aarch32.instrs.LDM.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  registers = register_list;  wback = (W == '1');</line>
<line>if n == 15 || <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) &lt; 1 then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; registers&lt;n&gt; == '1' then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>BitCount(registers) &lt; 1</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction executes as <instruction>LDM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers loaded.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; registers&lt;n&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/LDM/T1_A.txt">
        <box hibit="31" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="27" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="26" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="23" width="8" name="register_list" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="LDM_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDM" />
        </docvars>
        <asmtemplate comment="Preferred syntax"><text>LDM</text><a link="sa_ia" hover="Optional suffix for Increment After form">{IA}</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register">{!}</a><text>, </text><a link="sa_registers" hover="List of one or more registers to be loaded (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate comment="Alternate syntax, Full Descending stack"><text>LDMFD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register">{!}</a><text>, </text><a link="sa_registers" hover="List of one or more registers to be loaded (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDM/T1_A.txt" mylink="aarch32.instrs.LDM.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  registers = '00000000':register_list;  wback = (registers&lt;n&gt; == '0');</line>
<line>if <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) &lt; 1 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>BitCount(registers) &lt; 1</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction executes as <instruction>LDM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers loaded.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDM/T2_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="14" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="13" width="14" name="register_list" usename="1">
          <c colspan="14"></c>
        </box>
      </regdiagram>
      <encoding name="LDM_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDM" />
        </docvars>
        <asmtemplate comment="Preferred syntax, if &lt;Rn&gt;, '!' and &lt;registers&gt; can be represented in T1"><text>LDM</text><a link="sa_ia" hover="Optional suffix for Increment After form">{IA}</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33_1" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers_1" hover="List of one or more registers to be loaded (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate comment="Alternate syntax, Full Descending stack, if &lt;Rn&gt;, '!' and &lt;registers&gt; can be represented in T1"><text>LDMFD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33_1" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers_1" hover="List of one or more registers to be loaded (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate comment="Preferred syntax"><text>LDM</text><a link="sa_ia" hover="Optional suffix for Increment After form">{IA}</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33_1" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers_1" hover="List of one or more registers to be loaded (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate comment="Alternate syntax, Full Descending stack"><text>LDMFD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33_1" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers_1" hover="List of one or more registers to be loaded (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDM/T2_A.txt" mylink="aarch32.instrs.LDM.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  registers = P:M:register_list;  wback = (W == '1');</line>
<line>if n == 15 || <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) &lt; 2 || (P == '1' &amp;&amp; M == '1') then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; registers&lt;n&gt; == '1' then UNPREDICTABLE;</line>
<line>if registers&lt;13&gt; == '1' then UNPREDICTABLE;</line>
<line>if registers&lt;15&gt; == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>BitCount(registers) &lt; 1</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction executes as <instruction>LDM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers loaded.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; registers&lt;n&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>BitCount(registers) == 1</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction loads a single register using the specified addressing modes.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as <instruction>LDM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>registers&lt;13&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode, but R13 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>P == '1' &amp;&amp; M == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction loads the register list and either R14 or R15, both R14 and R15, or neither of these registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDM_A1, LDM_T1, LDM_T2" symboldefcount="1">
      <symbol link="sa_ia">IA</symbol>
      <account encodedin="">
        <intro>
          <para>Is an optional suffix for the Increment After form.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDM_A1, LDM_T1, LDM_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDM_A1, LDM_T1, LDM_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDM_A1, LDM_T1, LDM_T2" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDM_A1, LDM_T2" symboldefcount="1">
      <symbol link="sa_0d33_1">!</symbol>
      <account encodedin="W">
        <intro>
          <para>For encoding A1 and T2: the address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDM_T1" symboldefcount="2">
      <symbol link="sa_0d33">!</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: the address adjusted by the size of the data loaded is written back to the base register. It is omitted if <syntax>&lt;Rn&gt;</syntax> is included in <syntax>&lt;registers&gt;</syntax>, otherwise it must be present.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDM_A1" symboldefcount="1">
      <symbol link="sa_registers_2">&lt;registers&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is a list of one or more registers to be loaded, separated by commas and surrounded by { and }.</para>
          <para>The PC can be in the list.</para>
          <para>Arm deprecates using these instructions with both the LR and the PC in the list.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDM_T1" symboldefcount="2">
      <symbol link="sa_registers">&lt;registers&gt;</symbol>
      <account encodedin="register_list">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is a list of one or more registers to be loaded, separated by commas and surrounded by { and }. The registers in the list must be in the range R0-R7, encoded in the "register_list" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDM_T2" symboldefcount="3">
      <symbol link="sa_registers_1">&lt;registers&gt;</symbol>
      <account encodedin="register_list">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is a list of one or more registers to be loaded, separated by commas and surrounded by { and }. The registers in the list must be in the range R0-R12, encoded in the "register_list" field, and can optionally contain one of  the LR or the PC. If the LR is in the list, the "M" field is set to 1, otherwise it defaults to 0. If the PC is in the list, the "P" field is set to 1, otherwise it defaults to 0.</para>
          <para>If the PC is in the list:</para>
          <list type="unordered">
            <listitem><content>The LR must not be in the list.</content></listitem>
            <listitem><content>The instruction must be either outside any IT block, or the last instruction in an IT block.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDM/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    for i = 0 to 14</line>
<line>        if registers&lt;i&gt; == '1' then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[i] = <a link="impl-aarch32.MemS.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemS[bits(32) address, integer size]">MemS</a>[address,4];  address = address + 4;</line>
<line>    if registers&lt;15&gt; == '1' then</line>
<line>        <a link="impl-aarch32.LoadWritePC.1" file="shared_pseudocode.xml" hover="function: LoadWritePC(bits(32) address)">LoadWritePC</a>(<a link="impl-aarch32.MemS.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemS[bits(32) address, integer size]">MemS</a>[address,4]);</line>
<line>    if wback &amp;&amp; registers&lt;n&gt; == '0' then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 4*<a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers);</line>
<line>    if wback &amp;&amp; registers&lt;n&gt; == '1' then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = bits(32) UNKNOWN;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldm_e.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDM_e" title="LDM (exception return) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
    <docvar key="mnemonic" value="LDM" />
  </docvars>
  <heading>LDM (exception return)</heading>
  <desc>
    <brief>
      <para>Load Multiple (exception return)</para>
    </brief>
    <authored>
      <para>Load Multiple (exception return) loads multiple registers from consecutive memory locations using an address from a base register. The <xref linkend="CHDDAABB">SPSR</xref> of the current mode is copied to the <xref linkend="CIHJBHJA">CPSR</xref>. An address adjusted by the size of the data loaded can optionally be written back to the base register.</para>
      <para>The registers loaded include the PC. The word loaded for the PC is treated as an address and a branch occurs to that address.</para>
      <para>The PE checks the encoding that is copied to the <xref linkend="CIHJBHJA">CPSR</xref> for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</para>
      <para>Load Multiple (exception return) is:</para>
      <list type="unordered">
        <listitem><content><arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem>
        <listitem><content><arm-defined-word>unpredictable</arm-defined-word> in debug state, and in User mode and System mode.</content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>Instructions with similar syntax but without the PC included in the registers list are described in <xref linkend="A32T32-base.instructions.LDM_u">LDM (User registers)</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDM_e/A1_AS.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>1</c>
        </box>
        <box hibit="14" width="15" name="register_list" usename="1">
          <c colspan="15"></c>
        </box>
      </regdiagram>
      <encoding name="LDM_e_A1_AS" oneofinclass="1" oneof="1" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDM" />
        </docvars>
        <asmtemplate><text>LDM</text><text>{</text><a link="sa_amode" hover="One of:&#10;$DA: Decrement After">&lt;amode&gt;</a><text>}</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers_with_pc" hover="List of one or more registers, separated by commas and surrounded by { and }">&lt;registers_with_pc&gt;</a><text>^</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDM_e/A1_AS.txt" mylink="aarch32.instrs.LDM_e.A1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  registers = register_list;</line>
<line>wback = (W == '1');  increment = (U == '1');  wordhigher = (P == U);</line>
<line>if n == 15 then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; registers&lt;n&gt; == '1' then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; registers&lt;n&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all the loads using the specified addressing mode and the content of the register being written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during the execution of this instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDM_e_A1_AS" symboldefcount="1">
      <symbol link="sa_amode">&lt;amode&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>is one of:</para>
          <list type="param">
            <listitem>
              <param>DA</param><content>Decrement After. The consecutive memory addresses end at the address in the base register. Encoded as P = 0, U = 0.</content>
            </listitem>
            <listitem>
              <param>FA</param><content>Full Ascending. For this instruction, a synonym for <value>DA</value>.</content>
            </listitem>
            <listitem>
              <param>DB</param><content>Decrement Before. The consecutive memory addresses end one word below the address in the base register. Encoded as P = 1, U = 0.</content>
            </listitem>
            <listitem>
              <param>EA</param><content>Empty Ascending. For this instruction, a synonym for <value>DB</value>.</content>
            </listitem>
            <listitem>
              <param>IA</param><content>Increment After. The consecutive memory addresses start at the address in the base register. This is the default. Encoded as P = 0, U = 1.</content>
            </listitem>
            <listitem>
              <param>FD</param><content>Full Descending. For this instruction, a synonym for <value>IA</value>.</content>
            </listitem>
            <listitem>
              <param>IB</param><content>Increment Before. The consecutive memory addresses start one word above the address in the base register. Encoded as P = 1, U = 1.</content>
            </listitem>
            <listitem>
              <param>ED</param><content>Empty Descending. For this instruction, a synonym for <value>IB</value>.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDM_e_A1_AS" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDM_e_A1_AS" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDM_e_A1_AS" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDM_e_A1_AS" symboldefcount="1">
      <symbol link="sa_0d33">!</symbol>
      <account encodedin="W">
        <intro>
          <para>The address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDM_e_A1_AS" symboldefcount="1">
      <symbol link="sa_registers_with_pc">&lt;registers_with_pc&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is a list of one or more registers, separated by commas and surrounded by { and }. It specifies the set of registers to be loaded. The registers are loaded with the lowest-numbered register from the lowest memory address, through to the highest-numbered register from the highest memory address. The PC must be specified in the register list, and the instruction causes a branch to the address (data) loaded into the PC. See also <xref linkend="CHDDBEDG">Encoding of lists of general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDM_e/Op_AS.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>        UNDEFINED;</line>
<line>    elsif PSTATE.M IN {<a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a>,<a link="M32_System" file="shared_pseudocode.xml" hover="constant bits(5) M32_System = '11111'">M32_System</a>} then</line>
<line>        UNPREDICTABLE;                        // UNDEFINED or NOP</line>
<line>    else</line>
<line>        length = 4*<a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) + 4;</line>
<line>        address = if increment then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]-length;</line>
<line>        if wordhigher then address = address+4;</line>
<line></line>
<line>        for i = 0 to 14</line>
<line>            if registers&lt;i&gt; == '1' then</line>
<line>                <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[i] = <a link="impl-aarch32.MemS.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemS[bits(32) address, integer size]">MemS</a>[address,4];  address = address + 4;</line>
<line>        new_pc_value = <a link="impl-aarch32.MemS.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemS[bits(32) address, integer size]">MemS</a>[address,4];</line>
<line></line>
<line>        if wback &amp;&amp; registers&lt;n&gt; == '0' then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = if increment then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]+length else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]-length;</line>
<line>        if wback &amp;&amp; registers&lt;n&gt; == '1' then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = bits(32) UNKNOWN;</line>
<line></line>
<line>        <a link="AArch32.ExceptionReturn.2" file="shared_pseudocode.xml" hover="function: AArch32.ExceptionReturn(bits(32) new_pc_in, bits(32) spsr)">AArch32.ExceptionReturn</a>(new_pc_value, <a link="impl-shared.SPSR.read.0" file="shared_pseudocode.xml" hover="accessor: bits(N) SPSR[]">SPSR</a>[]);</line>
</pstext>
    </ps>
  </ps_section>
  <constrained_unpredictables ps_block="Operation">
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>PSTATE.M IN {M32_User,M32_System}</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
    </cu_case>
  </constrained_unpredictables>
</instructionsection>
</file>
<file type="instructionsection" file="ldm_u.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDM_u" title="LDM (User registers) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
    <docvar key="mnemonic" value="LDM" />
  </docvars>
  <heading>LDM (User registers)</heading>
  <desc>
    <brief>
      <para>Load Multiple (User registers)</para>
    </brief>
    <authored>
      <para>In an EL1 mode other than System mode, Load Multiple (User registers) loads multiple User mode registers from consecutive memory locations using an address from a base register. The registers loaded cannot include the PC. The PE reads the base register value normally, using the current mode to determine the correct Banked version of the register. This instruction cannot writeback to the base register.</para>
      <para>Load Multiple (User registers) is <arm-defined-word>undefined</arm-defined-word> in Hyp mode, and <arm-defined-word>unpredictable</arm-defined-word> in User and System modes.</para>
      <para>Armv8.2 permits the deprecation of some Load Multiple ordering behaviors in AArch32 state, for more information see <xref linkend="v8.2.LSMAOC">FEAT_LSMAOC</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>Instructions with similar syntax but with the PC included in <syntax>&lt;registers_without_pc&gt;</syntax> are described in <xref linkend="A32T32-base.instructions.LDM_e">LDM (exception return)</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDM_u/A1_AS.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="15" name="register_list" usename="1">
          <c colspan="15"></c>
        </box>
      </regdiagram>
      <encoding name="LDM_u_A1_AS" oneofinclass="1" oneof="1" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDM" />
        </docvars>
        <asmtemplate><text>LDM</text><text>{</text><a link="sa_amode" hover="One of:&#10;$DA: Decrement After">&lt;amode&gt;</a><text>}</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_registers_without_pc" hover="List of one or more registers, separated by commas and surrounded by { and }">&lt;registers_without_pc&gt;</a><text>^</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDM_u/A1_AS.txt" mylink="aarch32.instrs.LDM_u.A1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  registers = register_list;  increment = (U == '1');  wordhigher = (P == U);</line>
<line>if n == 15 || <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) &lt; 1 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>BitCount(registers) &lt; 1</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction operates as an <instruction>LDM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDM_u_A1_AS" symboldefcount="1">
      <symbol link="sa_amode">&lt;amode&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>is one of:</para>
          <list type="param">
            <listitem>
              <param>DA</param><content>Decrement After. The consecutive memory addresses end at the address in the base register. Encoded as P = 0, U = 0.</content>
            </listitem>
            <listitem>
              <param>FA</param><content>Full Ascending. For this instruction, a synonym for <value>DA</value>.</content>
            </listitem>
            <listitem>
              <param>DB</param><content>Decrement Before. The consecutive memory addresses end one word below the address in the base register. Encoded as P = 1, U = 0.</content>
            </listitem>
            <listitem>
              <param>EA</param><content>Empty Ascending. For this instruction, a synonym for <value>DB</value>.</content>
            </listitem>
            <listitem>
              <param>IA</param><content>Increment After. The consecutive memory addresses start at the address in the base register. This is the default. Encoded as P = 0, U = 1.</content>
            </listitem>
            <listitem>
              <param>FD</param><content>Full Descending. For this instruction, a synonym for <value>IA</value>.</content>
            </listitem>
            <listitem>
              <param>IB</param><content>Increment Before. The consecutive memory addresses start one word above the address in the base register. Encoded as P = 1, U = 1.</content>
            </listitem>
            <listitem>
              <param>ED</param><content>Empty Descending. For this instruction, a synonym for <value>IB</value>.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDM_u_A1_AS" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDM_u_A1_AS" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDM_u_A1_AS" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDM_u_A1_AS" symboldefcount="1">
      <symbol link="sa_registers_without_pc">&lt;registers_without_pc&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is a list of one or more registers, separated by commas and surrounded by { and }. It specifies the set of registers to be loaded by the <instruction>LDM</instruction> instruction. The registers are loaded with the lowest-numbered register from the lowest memory address, through to the highest-numbered register from the highest memory address. The PC must not be in the register list. See also <xref linkend="CHDDBEDG">Encoding of lists of general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDM_u/Op_AS.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then UNDEFINED;</line>
<line>    elsif PSTATE.M IN {<a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a>,<a link="M32_System" file="shared_pseudocode.xml" hover="constant bits(5) M32_System = '11111'">M32_System</a>} then UNPREDICTABLE;</line>
<line>    else</line>
<line>        length = 4*<a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers);</line>
<line>        address = if increment then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]-length;</line>
<line>        if wordhigher then address = address+4;</line>
<line>        for i = 0 to 14</line>
<line>            if registers&lt;i&gt; == '1' then  // Load User mode register</line>
<line>                <a link="impl-aarch32.Rmode.write.2" file="shared_pseudocode.xml" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</a>[i, <a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a>] = <a link="impl-aarch32.MemS.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemS[bits(32) address, integer size]">MemS</a>[address,4];  address = address + 4;</line>
</pstext>
    </ps>
  </ps_section>
  <constrained_unpredictables ps_block="Operation">
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>PSTATE.M IN {M32_User,M32_System}</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
      <cu_type>
        <cu_type_text>The instruction operates as an <instruction>LDM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15.</cu_type_text>
      </cu_type>
    </cu_case>
  </constrained_unpredictables>
</instructionsection>
</file>
<file type="instructionsection" file="ldmda.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDMDA" title="LDMDA, LDMFA -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
    <docvar key="mnemonic" value="LDM" />
  </docvars>
  <heading>LDMDA, LDMFA</heading>
  <desc>
    <brief>
      <para>Load Multiple Decrement After (Full Ascending)</para>
    </brief>
    <authored>
      <para>Load Multiple Decrement After (Full Ascending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations end at this address, and the address just below the lowest of those locations can optionally be written back to the base register.</para>
      <para>The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register from the highest memory address. See also <xref linkend="CHDDBEDG">Encoding of lists of general-purpose registers and the PC</xref>.</para>
      <para>Armv8.2 permits the deprecation of some Load Multiple ordering behaviors in AArch32 state, for more information see <xref linkend="v8.2.LSMAOC">FEAT_LSMAOC</xref>. The registers loaded can include the PC, causing a branch to a loaded address. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>. Related system instructions are <xref linkend="A32T32-base.instructions.LDM_u">LDM (User registers)</xref> and <xref linkend="A32T32-base.instructions.LDM_e">LDM (exception return)</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDMDA/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="16" name="register_list" usename="1">
          <c colspan="16"></c>
        </box>
      </regdiagram>
      <encoding name="LDMDA_A1" oneofinclass="1" oneof="1" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDM" />
        </docvars>
        <asmtemplate comment="Preferred syntax"><text>LDMDA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers" hover="List of one or more registers to be loaded">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate comment="Alternate syntax, Full Ascending stack"><text>LDMFA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers" hover="List of one or more registers to be loaded">&lt;registers&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDMDA/A1_A.txt" mylink="aarch32.instrs.LDMDA.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  registers = register_list;  wback = (W == '1');</line>
<line>if n == 15 || <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) &lt; 1 then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; registers&lt;n&gt; == '1' then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>BitCount(registers) &lt; 1</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction operates as an <instruction>LDM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers loaded.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; registers&lt;n&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDMDA_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDMDA_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDMDA_A1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDMDA_A1" symboldefcount="1">
      <symbol link="sa_0d33">!</symbol>
      <account encodedin="W">
        <intro>
          <para>The address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDMDA_A1" symboldefcount="1">
      <symbol link="sa_registers">&lt;registers&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is a list of one or more registers to be loaded, separated by commas and surrounded by { and }.</para>
          <para>The PC can be in the list.</para>
          <para>Arm deprecates using these instructions with both the LR and the PC in the list.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDMDA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - 4*<a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) + 4;</line>
<line>    for i = 0 to 14</line>
<line>        if registers&lt;i&gt; == '1' then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[i] = <a link="impl-aarch32.MemS.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemS[bits(32) address, integer size]">MemS</a>[address,4];  address = address + 4;</line>
<line>    if registers&lt;15&gt; == '1' then</line>
<line>        <a link="impl-aarch32.LoadWritePC.1" file="shared_pseudocode.xml" hover="function: LoadWritePC(bits(32) address)">LoadWritePC</a>(<a link="impl-aarch32.MemS.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemS[bits(32) address, integer size]">MemS</a>[address,4]);</line>
<line>    if wback &amp;&amp; registers&lt;n&gt; == '0' then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - 4*<a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers);</line>
<line>    if wback &amp;&amp; registers&lt;n&gt; == '1' then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = bits(32) UNKNOWN;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldmdb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDMDB" title="LDMDB, LDMEA -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDM" />
  </docvars>
  <heading>LDMDB, LDMEA</heading>
  <desc>
    <brief>
      <para>Load Multiple Decrement Before (Empty Ascending)</para>
    </brief>
    <authored>
      <para>Load Multiple Decrement Before (Empty Ascending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations end just below this address, and the address of the lowest of those locations can optionally be written back to the base register.</para>
      <para>The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register from the highest memory address. See also <xref linkend="CHDDBEDG">Encoding of lists of general-purpose registers and the PC</xref>.</para>
      <para>Armv8.2 permits the deprecation of some Load Multiple ordering behaviors in AArch32 state, for more information see <xref linkend="v8.2.LSMAOC">FEAT_LSMAOC</xref>. The registers loaded can include the PC, causing a branch to a loaded address. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>. Related system instructions are <xref linkend="A32T32-base.instructions.LDM_u">LDM (User registers)</xref> and <xref linkend="A32T32-base.instructions.LDM_e">LDM (exception return)</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDMDB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="16" name="register_list" usename="1">
          <c colspan="16"></c>
        </box>
      </regdiagram>
      <encoding name="LDMDB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDM" />
        </docvars>
        <asmtemplate comment="Preferred syntax"><text>LDMDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers_1" hover="List of one or more registers to be loaded">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate comment="Alternate syntax, Empty Ascending stack"><text>LDMEA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers_1" hover="List of one or more registers to be loaded">&lt;registers&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDMDB/A1_A.txt" mylink="aarch32.instrs.LDMDB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  registers = register_list;  wback = (W == '1');</line>
<line>if n == 15 || <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) &lt; 1 then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; registers&lt;n&gt; == '1' then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; registers&lt;n&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>BitCount(registers) &lt; 1</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction executes as <instruction>LDM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers loaded.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDMDB/T1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="opc" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="14" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="13" width="14" name="register_list" usename="1">
          <c colspan="14"></c>
        </box>
      </regdiagram>
      <encoding name="LDMDB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDM" />
        </docvars>
        <asmtemplate comment="Preferred syntax"><text>LDMDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers" hover="List of one or more registers to be loaded (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate comment="Alternate syntax, Empty Ascending stack"><text>LDMEA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers" hover="List of one or more registers to be loaded (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDMDB/T1_A.txt" mylink="aarch32.instrs.LDMDB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  registers = P:M:register_list;  wback = (W == '1');</line>
<line>if n == 15 || <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) &lt; 2 || (P == '1' &amp;&amp; M == '1') then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; registers&lt;n&gt; == '1' then UNPREDICTABLE;</line>
<line>if registers&lt;13&gt; == '1' then UNPREDICTABLE;</line>
<line>if registers&lt;15&gt; == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; registers&lt;n&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>BitCount(registers) &lt; 1</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction executes as <instruction>LDM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers loaded.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>BitCount(registers) == 1</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction loads a single register using the specified addressing modes.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as <instruction>LDM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>registers&lt;13&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode, but R13 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>P == '1' &amp;&amp; M == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction loads the register list and either R14 or R15, both R14 and R15, or neither of these registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDMDB_A1, LDMDB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDMDB_A1, LDMDB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDMDB_A1, LDMDB_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDMDB_A1, LDMDB_T1" symboldefcount="1">
      <symbol link="sa_0d33">!</symbol>
      <account encodedin="W">
        <intro>
          <para>The address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDMDB_A1" symboldefcount="1">
      <symbol link="sa_registers_1">&lt;registers&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is a list of one or more registers to be loaded, separated by commas and surrounded by { and }.</para>
          <para>The PC can be in the list.</para>
          <para>Arm deprecates using these instructions with both the LR and the PC in the list.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDMDB_T1" symboldefcount="2">
      <symbol link="sa_registers">&lt;registers&gt;</symbol>
      <account encodedin="register_list">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is a list of one or more registers to be loaded, separated by commas and surrounded by { and }. The registers in the list must be in the range R0-R12, encoded in the "register_list" field, and can optionally contain one of  the LR or the PC. If the LR is in the list, the "M" field is set to 1, otherwise it defaults to 0. If the PC is in the list, the "P" field is set to 1, otherwise it defaults to 0.</para>
          <para>If the PC is in the list:</para>
          <list type="unordered">
            <listitem><content>The LR must not be in the list.</content></listitem>
            <listitem><content>The instruction must be either outside any IT block, or the last instruction in an IT block.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDMDB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - 4*<a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers);</line>
<line>    for i = 0 to 14</line>
<line>        if registers&lt;i&gt; == '1' then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[i] = <a link="impl-aarch32.MemS.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemS[bits(32) address, integer size]">MemS</a>[address,4];  address = address + 4;</line>
<line>    if registers&lt;15&gt; == '1' then</line>
<line>        <a link="impl-aarch32.LoadWritePC.1" file="shared_pseudocode.xml" hover="function: LoadWritePC(bits(32) address)">LoadWritePC</a>(<a link="impl-aarch32.MemS.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemS[bits(32) address, integer size]">MemS</a>[address,4]);</line>
<line>    if wback &amp;&amp; registers&lt;n&gt; == '0' then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - 4*<a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers);</line>
<line>    if wback &amp;&amp; registers&lt;n&gt; == '1' then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = bits(32) UNKNOWN;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldmib.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDMIB" title="LDMIB, LDMED -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
    <docvar key="mnemonic" value="LDM" />
  </docvars>
  <heading>LDMIB, LDMED</heading>
  <desc>
    <brief>
      <para>Load Multiple Increment Before (Empty Descending)</para>
    </brief>
    <authored>
      <para>Load Multiple Increment Before (Empty Descending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations start just above this address, and the address of the last of those locations can optionally be written back to the base register.</para>
      <para>The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register from the highest memory address. See also <xref linkend="CHDDBEDG">Encoding of lists of general-purpose registers and the PC</xref>.</para>
      <para>Armv8.2 permits the deprecation of some Load Multiple ordering behaviors in AArch32 state, for more information see <xref linkend="v8.2.LSMAOC">FEAT_LSMAOC</xref>. The registers loaded can include the PC, causing a branch to a loaded address. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>. Related system instructions are <xref linkend="A32T32-base.instructions.LDM_u">LDM (User registers)</xref> and <xref linkend="A32T32-base.instructions.LDM_e">LDM (exception return)</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDMIB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="16" name="register_list" usename="1">
          <c colspan="16"></c>
        </box>
      </regdiagram>
      <encoding name="LDMIB_A1" oneofinclass="1" oneof="1" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDM" />
        </docvars>
        <asmtemplate comment="Preferred syntax"><text>LDMIB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers" hover="List of one or more registers to be loaded">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate comment="Alternate syntax, Empty Descending stack"><text>LDMED</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers" hover="List of one or more registers to be loaded">&lt;registers&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDMIB/A1_A.txt" mylink="aarch32.instrs.LDMIB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  registers = register_list;  wback = (W == '1');</line>
<line>if n == 15 || <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) &lt; 1 then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; registers&lt;n&gt; == '1' then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>BitCount(registers) &lt; 1</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction operates as an <instruction>LDM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers loaded.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; registers&lt;n&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDMIB_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDMIB_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDMIB_A1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDMIB_A1" symboldefcount="1">
      <symbol link="sa_0d33">!</symbol>
      <account encodedin="W">
        <intro>
          <para>The address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDMIB_A1" symboldefcount="1">
      <symbol link="sa_registers">&lt;registers&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is a list of one or more registers to be loaded, separated by commas and surrounded by { and }.</para>
          <para>The PC can be in the list.</para>
          <para>Arm deprecates using these instructions with both the LR and the PC in the list.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDMIB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 4;</line>
<line>    for i = 0 to 14</line>
<line>        if registers&lt;i&gt; == '1' then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[i] = <a link="impl-aarch32.MemS.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemS[bits(32) address, integer size]">MemS</a>[address,4];  address = address + 4;</line>
<line>    if registers&lt;15&gt; == '1' then</line>
<line>        <a link="impl-aarch32.LoadWritePC.1" file="shared_pseudocode.xml" hover="function: LoadWritePC(bits(32) address)">LoadWritePC</a>(<a link="impl-aarch32.MemS.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemS[bits(32) address, integer size]">MemS</a>[address,4]);</line>
<line>    if wback &amp;&amp; registers&lt;n&gt; == '0' then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 4*<a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers);</line>
<line>    if wback &amp;&amp; registers&lt;n&gt; == '1' then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = bits(32) UNKNOWN;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldr_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDR_i" title="LDR (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDR" />
  </docvars>
  <heading>LDR (immediate)</heading>
  <desc>
    <brief>
      <para>Load Register (immediate)</para>
    </brief>
    <authored>
      <para>Load Register (immediate) calculates an address from a base register value and an immediate offset, loads a word from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="1">
    <alias_list_intro>This instruction is used by the alias </alias_list_intro>
    <aliasref aliaspageid="POP_LDR_i" aliasfile="pop_ldr_i.xml" hover="Pop Single Register from Stack" punct=".">
      <text>POP (single register)</text>
      <aliaspref labels="A1 (post-indexed)">P == '0' &amp;&amp; U == '1' &amp;&amp; W == '0' &amp;&amp; Rn == '1101' &amp;&amp; imm12 == '000000000100'</aliaspref>
      <aliaspref labels="T4 (post-indexed)">Rn == '1101' &amp;&amp; P == '0' &amp;&amp; U == '1' &amp;&amp; W == '1' &amp;&amp; imm8 == '00000100'</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink />
      <text> below for details of when the alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <classesintro count="5">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt>, </txt>
      <a href="#iclass_t3">T3</a>
      <txt> and </txt>
      <a href="#iclass_t4">T4</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="5" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDR" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDR_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="LDR_i_A1_off" oneofinclass="3" oneof="9" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDR" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_2" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_4" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDR_i_A1_post" oneofinclass="3" oneof="9" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDR" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_2" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_4" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="LDR_i_A1_pre" oneofinclass="3" oneof="9" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDR" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_2" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_4" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDR_i/A1_A.txt" mylink="aarch32.instrs.LDR_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "LDR (literal)";</line>
<line>if P == '0' &amp;&amp; W == '1' then SEE "LDRT";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>if wback &amp;&amp; n == t then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="5" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/LDR_i/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="26" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="21" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rt" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="LDR_i_T1" oneofinclass="1" oneof="9" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDR" />
        </docvars>
        <asmtemplate><text>LDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional positive unsigned immediate byte offset (field &quot;imm5&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDR_i/T1_A.txt" mylink="aarch32.instrs.LDR_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm5:'00', 32);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="5" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/LDR_i/T2_A.txt">
        <box hibit="31" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="27" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="26" width="3" name="Rt" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="23" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="LDR_i_T2" oneofinclass="1" oneof="9" label="T2">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDR" />
        </docvars>
        <asmtemplate><text>LDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [SP</text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm_1" hover="Optional positive unsigned immediate byte offset (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDR_i/T2_A.txt" mylink="aarch32.instrs.LDR_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = 13;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T3" oneof="5" id="iclass_t3" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDR_i/T3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="LDR_i_T3" oneofinclass="1" oneof="9" label="T3">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDR" />
        </docvars>
        <asmtemplate comment="&lt;Rt&gt;, &lt;Rn&gt;, &lt;imm&gt; can be represented in T1 or T2"><text>LDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm_2" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
        <asmtemplate><text>LDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm_2" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDR_i/T3_A.txt" mylink="aarch32.instrs.LDR_i.T3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "LDR (literal)";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32); index = TRUE;  add = TRUE;</line>
<line>wback = FALSE; if t == 15 &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T4" oneof="5" id="iclass_t4" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T4" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDR" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDR_i/T4_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="9" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="8" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="LDR_i_T4_off" oneofinclass="3" oneof="9" label="Offset" bitdiffs="P == 1 &amp;&amp; U == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDR" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="9" width="1" name="U">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #-</text><a link="sa_imm_3" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDR_i_T4_post" oneofinclass="3" oneof="9" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDR" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_3" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="LDR_i_T4_pre" oneofinclass="3" oneof="9" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDR" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_3" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDR_i/T4_A.txt" mylink="aarch32.instrs.LDR_i.T4_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "LDR (literal)";</line>
<line>if P == '1' &amp;&amp; U == '1' &amp;&amp; W == '0' then SEE "LDRT";</line>
<line>if P == '0' &amp;&amp; W == '0' then UNDEFINED;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32); index = (P == '1');  add = (U == '1');  wback = (W == '1');</line>
<line>if (wback &amp;&amp; n == t) || (t == 15 &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>()) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T4" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDR_i_A1_off, LDR_i_T1, LDR_i_T2, LDR_i_T3, LDR_i_T4_pre" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_i_A1_off, LDR_i_T1, LDR_i_T2, LDR_i_T3, LDR_i_T4_pre" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_i_A1_off" symboldefcount="1">
      <symbol link="sa_rt_2">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used. If the PC is used, the instruction branches to the address (data) loaded to the PC. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_i_T1, LDR_i_T2" symboldefcount="2">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_i_T3, LDR_i_T4_pre" symboldefcount="3">
      <symbol link="sa_rt_1">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3 and T4: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used, provided the instruction is either outside an IT block or the last instruction of an IT block. If the PC is used, the instruction branches to the address (data) loaded to the PC. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_i_A1_off, LDR_i_T3, LDR_i_T4_pre" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>For encoding A1, T3 and T4: is the general-purpose base register, encoded in the "Rn" field. For PC use see <xref linkend="A32T32-base.instructions.LDR_l">LDR (literal)</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_i_T1" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_i_A1_off, LDR_i_T4_pre" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDR_i_T1, LDR_i_T2, LDR_i_T3" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the offset is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_i_A1_off" symboldefcount="1">
      <symbol link="sa_imm_4">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 if omitted, and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_i_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the optional positive unsigned immediate byte offset, a multiple of 4, in the range 0 to 124, defaulting to 0 and encoded in the "imm5" field as &lt;imm&gt;/4.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_i_T2" symboldefcount="3">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the optional positive unsigned immediate byte offset, a multiple of 4, in the range 0 to 1020, defaulting to 0 and encoded in the "imm8" field as &lt;imm&gt;/4.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_i_T3" symboldefcount="4">
      <symbol link="sa_imm_2">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_i_T4_pre" symboldefcount="5">
      <symbol link="sa_imm_3">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T4: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDR_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then</line>
<line>    if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>        EncodingSpecificOperations();</line>
<line>        offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);</line>
<line>        address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>        data = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,4];</line>
<line>        if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
<line>        if t == 15 then</line>
<line>            if address&lt;1:0&gt; == '00' then</line>
<line>                <a link="impl-aarch32.LoadWritePC.1" file="shared_pseudocode.xml" hover="function: LoadWritePC(bits(32) address)">LoadWritePC</a>(data);</line>
<line>            else</line>
<line>                UNPREDICTABLE;</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = data;</line>
<line>else</line>
<line>    if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>        EncodingSpecificOperations();</line>
<line>        offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);</line>
<line>        address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>        data = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,4];</line>
<line>        if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
<line>        if t == 15 then</line>
<line>            if address&lt;1:0&gt; == '00' then</line>
<line>                <a link="impl-aarch32.LoadWritePC.1" file="shared_pseudocode.xml" hover="function: LoadWritePC(bits(32) address)">LoadWritePC</a>(data);</line>
<line>            else</line>
<line>                UNPREDICTABLE;</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = data;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldr_l.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDR_l" title="LDR (literal) -- AArch32" type="instruction">
  <docvars>
    <docvar key="address-form" value="literal" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDR" />
  </docvars>
  <heading>LDR (literal)</heading>
  <desc>
    <brief>
      <para>Load Register (literal)</para>
    </brief>
    <authored>
      <para>Load Register (literal) calculates an address from the PC value and an immediate offset, loads a word from memory, and writes it to a register. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>The alternative syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see <xref linkend="BABGCIBA">Use of labels in UAL instruction syntax</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="address-form" value="literal" />
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDR_l/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="LDR_l_A1" oneofinclass="1" oneof="3" label="A1" bitdiffs="!(P == 0 &amp;&amp; W == 1)">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDR" />
        </docvars>
        <box hibit="24" width="4" name="P:W">
          <c>Z</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Normal form"><text>LDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_2" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_label_1" hover="The label of literal data item that is to be loaded into {syntax{&lt;Rt&gt;}}">&lt;label&gt;</a></asmtemplate>
        <asmtemplate comment="Alternative form"><text>LDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_2" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDR_l/A1_A.txt" mylink="aarch32.instrs.LDR_l.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; W == '1' then SEE "LDRT";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);</line>
<line>add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>if wback then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="wback = FALSE;" />
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction treats bit[24] as the P bit, and bit[21] as the writeback (W) bit, and uses the same addressing mode as described in <xref linkend="A32T32-base.instructions.LDR_i">LDR (immediate)</xref>. The instruction uses post-indexed addressing when P == '0' and uses pre-indexed addressing otherwise. The instruction is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="literal" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/LDR_l/T1_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="26" width="3" name="Rt" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="23" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="LDR_l_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDR" />
        </docvars>
        <asmtemplate comment="Normal form"><text>LDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_label" hover="The label of literal data item that is to be loaded into {syntax{&lt;Rt&gt;}}">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDR_l/T1_A.txt" mylink="aarch32.instrs.LDR_l.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);  add = TRUE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="literal" />
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDR_l/T2_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="LDR_l_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDR" />
        </docvars>
        <asmtemplate comment="Preferred syntax, and &lt;Rt&gt;, &lt;label&gt; can be represented in T1"><text>LDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_label_1" hover="The label of literal data item that is to be loaded into {syntax{&lt;Rt&gt;}}">&lt;label&gt;</a></asmtemplate>
        <asmtemplate comment="Preferred syntax"><text>LDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_label_1" hover="The label of literal data item that is to be loaded into {syntax{&lt;Rt&gt;}}">&lt;label&gt;</a></asmtemplate>
        <asmtemplate comment="Alternative syntax"><text>LDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDR_l/T2_A.txt" mylink="aarch32.instrs.LDR_l.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);  add = (U == '1');</line>
<line>if t == 15 &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDR_l_A1, LDR_l_T1, LDR_l_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_l_A1, LDR_l_T1, LDR_l_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_l_A1" symboldefcount="1">
      <symbol link="sa_rt_2">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used. If the PC is used, the instruction branches to the address (data) loaded to the PC. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_l_T1" symboldefcount="2">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_l_T2" symboldefcount="3">
      <symbol link="sa_rt_1">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the general-purpose register to be transferred, encoded in the "Rt" field. The SP can be used. The PC can be used, provided the instruction is either outside an IT block or the last instruction of an IT block. If the PC is used, the instruction branches to the address (data) loaded to the PC. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_l_A1, LDR_l_T2" symboldefcount="1">
      <symbol link="sa_label_1">&lt;label&gt;</symbol>
      <account encodedin="imm12">
        <intro>
          <para>For encoding A1 and T2: the label of the literal data item that is to be loaded into <syntax>&lt;Rt&gt;</syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the instruction to this label. Permitted values of the offset are -4095 to 4095.</para>
          <para>If the offset is zero or positive, <field>imm32</field> is equal to the offset and <field>add</field> == <enumvalue>TRUE</enumvalue>, encoded as U == 1.</para>
          <para>If the offset is negative, <field>imm32</field> is equal to minus the offset and <field>add</field> == <enumvalue>FALSE</enumvalue>, encoded as U == 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_l_T1" symboldefcount="2">
      <symbol link="sa_label">&lt;label&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: the label of the literal data item that is to be loaded into <syntax>&lt;Rt&gt;</syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the instruction to this label. Permitted values of the offset are Multiples of four in the range 0 to 1020.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_l_A1, LDR_l_T2" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDR_l_A1" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 if omitted, and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_l_T2" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is a 12-bit unsigned immediate byte offset, in the range 0 to 4095, encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDR_l/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    base = <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4);</line>
<line>    address = if add then (base + imm32) else (base - imm32);</line>
<line>    data = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,4];</line>
<line>    if t == 15 then</line>
<line>        if address&lt;1:0&gt; == '00' then</line>
<line>            <a link="impl-aarch32.LoadWritePC.1" file="shared_pseudocode.xml" hover="function: LoadWritePC(bits(32) address)">LoadWritePC</a>(data);</line>
<line>        else</line>
<line>            UNPREDICTABLE;</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = data;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldr_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDR_r" title="LDR (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDR" />
  </docvars>
  <heading>LDR (register)</heading>
  <desc>
    <brief>
      <para>Load Register (register)</para>
    </brief>
    <authored>
      <para>Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
      <para>The T32 form of <instruction>LDR</instruction> (register) does not support register writeback.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDR" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDR_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDR_r_A1_off" oneofinclass="3" oneof="5" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDR" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_2" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, </text><a link="sa_shift" hover="The shift to apply to the value read from {syntax{&lt;Rm&gt;}}">&lt;shift&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDR_r_A1_post" oneofinclass="3" oneof="5" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDR" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_2" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, </text><a link="sa_shift" hover="The shift to apply to the value read from {syntax{&lt;Rm&gt;}}">&lt;shift&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="LDR_r_A1_pre" oneofinclass="3" oneof="5" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDR" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_2" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, </text><a link="sa_shift" hover="The shift to apply to the value read from {syntax{&lt;Rm&gt;}}">&lt;shift&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDR_r/A1_A.txt" mylink="aarch32.instrs.LDR_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; W == '1' then SEE "LDRT";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
<line>if m == 15 then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; (n == 15 || n == t) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/LDR_r/T1_A.txt">
        <box hibit="31" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="27" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="26" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="25" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="21" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rt" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="LDR_r_T1" oneofinclass="1" oneof="5" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDR" />
        </docvars>
        <asmtemplate><text>LDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDR_r/T1_A.txt" mylink="aarch32.instrs.LDR_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="register-offset" />
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDR_r/T2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="6" settings="6">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDR_r_T2" oneofinclass="1" oneof="5" label="T2">
        <docvars>
          <docvar key="address-form" value="register-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDR" />
        </docvars>
        <asmtemplate comment="&lt;Rt&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>LDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
        <asmtemplate><text>LDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, LSL #</text><a link="sa_imm" hover="If present, the size of left shift to apply to the value from {syntax{&lt;Rm&gt;}}, in the range 1-3">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDR_r/T2_A.txt" mylink="aarch32.instrs.LDR_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "LDR (literal)";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm2));</line>
<line>if m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
<line>if t == 15 &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDR_r_A1_off, LDR_r_T1, LDR_r_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_r_A1_off, LDR_r_T1, LDR_r_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_r_A1_off" symboldefcount="1">
      <symbol link="sa_rt_2">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used. If the PC is used, the instruction branches to the address (data) loaded to the PC. This branch is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_r_T1" symboldefcount="2">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_r_T2" symboldefcount="3">
      <symbol link="sa_rt_1">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="address-form" value="register-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used, provided the instruction is either outside an IT block or the last instruction of an IT block. If the PC is used, the instruction branches to the address (data) loaded to the PC. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_r_A1_off" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_r_T1, LDR_r_T2" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_r_A1_off" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDR_r_T1, LDR_r_T2" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the index register is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_r_A1_off, LDR_r_T1, LDR_r_T2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_r_A1_off" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The shift to apply to the value read from <syntax>&lt;Rm&gt;</syntax>. If absent, no shift is applied. Otherwise, see <xref linkend="Chdibjii">Shifts applied to a register</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDR_r_T2" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>If present, the size of the left shift to apply to the value from <syntax>&lt;Rm&gt;</syntax>, in the range 1-3. <syntax>&lt;imm&gt;</syntax> is encoded in imm2. If absent, no shift is specified and imm2 is encoded as <binarynumber>0b00</binarynumber>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDR_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then</line>
<line>    if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>        EncodingSpecificOperations();</line>
<line>        offset = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>        offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + offset) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - offset);</line>
<line>        address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>        data = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,4];</line>
<line>        if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
<line>        if t == 15 then</line>
<line>            if address&lt;1:0&gt; == '00' then</line>
<line>                <a link="impl-aarch32.LoadWritePC.1" file="shared_pseudocode.xml" hover="function: LoadWritePC(bits(32) address)">LoadWritePC</a>(data);</line>
<line>            else</line>
<line>                UNPREDICTABLE;</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = data;</line>
<line>else</line>
<line>    if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>        EncodingSpecificOperations();</line>
<line>        offset = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>        offset_addr = (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + offset);</line>
<line>        address = offset_addr;</line>
<line>        data = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,4];</line>
<line>        if t == 15 then</line>
<line>            if address&lt;1:0&gt; == '00' then</line>
<line>                <a link="impl-aarch32.LoadWritePC.1" file="shared_pseudocode.xml" hover="function: LoadWritePC(bits(32) address)">LoadWritePC</a>(data);</line>
<line>            else</line>
<line>                UNPREDICTABLE;</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = data;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldrb_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDRB_i" title="LDRB (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDRB" />
  </docvars>
  <heading>LDRB (immediate)</heading>
  <desc>
    <brief>
      <para>Load Register Byte (immediate)</para>
    </brief>
    <authored>
      <para>Load Register Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing.  For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRB" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRB_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="LDRB_i_A1_off" oneofinclass="3" oneof="8" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRB" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_3" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDRB_i_A1_post" oneofinclass="3" oneof="8" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRB" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_3" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="LDRB_i_A1_pre" oneofinclass="3" oneof="8" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRB" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_3" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRB_i/A1_A.txt" mylink="aarch32.instrs.LDRB_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "LDRB (literal)";</line>
<line>if P == '0' &amp;&amp; W == '1' then SEE "LDRBT";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>if t == 15 || (wback &amp;&amp; n == t) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/LDRB_i/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="B" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="26" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="21" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rt" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="LDRB_i_T1" oneofinclass="1" oneof="8" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRB" />
        </docvars>
        <asmtemplate><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional 5-bit unsigned immediate byte offset [0-31], default 0 (field &quot;imm5&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRB_i/T1_A.txt" mylink="aarch32.instrs.LDRB_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm5, 32);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRB_i/T2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="LDRB_i_T2" oneofinclass="1" oneof="8" label="T2">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRB" />
        </docvars>
        <asmtemplate comment="&lt;Rt&gt;, &lt;Rn&gt;, &lt;imm&gt; can be represented in T1"><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm_1" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
        <asmtemplate><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm_1" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRB_i/T2_A.txt" mylink="aarch32.instrs.LDRB_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rt == '1111' then SEE "PLD";</line>
<line>if Rn == '1111' then SEE "LDRB (literal)";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T3" oneof="4" id="iclass_t3" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRB" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRB_i/T3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="9" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="8" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="LDRB_i_T3_off" oneofinclass="3" oneof="8" label="Offset" bitdiffs="Rt != 1111 &amp;&amp; P == 1 &amp;&amp; U == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRB" />
        </docvars>
        <box hibit="15" width="4" name="Rt">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <box hibit="10" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="9" width="1" name="U">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #-</text><a link="sa_imm_2" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDRB_i_T3_post" oneofinclass="3" oneof="8" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRB" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_2" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="LDRB_i_T3_pre" oneofinclass="3" oneof="8" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRB" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_2" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRB_i/T3_A.txt" mylink="aarch32.instrs.LDRB_i.T3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rt == '1111' &amp;&amp; P == '1' &amp;&amp; U == '0' &amp;&amp; W == '0' then SEE "PLD, PLDW (immediate)";</line>
<line>if Rn == '1111' then SEE "LDRB (literal)";</line>
<line>if P == '1' &amp;&amp; U == '1' &amp;&amp; W == '0' then SEE "LDRBT";</line>
<line>if P == '0' &amp;&amp; W == '0' then UNDEFINED;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (W == '1');</line>
<line>if  (t == 15 &amp;&amp;  W == '1') || (wback &amp;&amp; n == t) then UNPREDICTABLE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDRB_i_A1_off, LDRB_i_T1, LDRB_i_T2, LDRB_i_T3_pre" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRB_i_A1_off, LDRB_i_T1, LDRB_i_T2, LDRB_i_T3_pre" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRB_i_A1_off, LDRB_i_T1, LDRB_i_T2, LDRB_i_T3_pre" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRB_i_A1_off, LDRB_i_T2, LDRB_i_T3_pre" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>For encoding A1, T2 and T3: is the general-purpose base register, encoded in the "Rn" field. For PC use see <xref linkend="A32T32-base.instructions.LDRB_l">LDRB (literal)</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRB_i_T1" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRB_i_A1_off, LDRB_i_T3_pre" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRB_i_T1, LDRB_i_T2" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the offset is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRB_i_A1_off" symboldefcount="1">
      <symbol link="sa_imm_3">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 if omitted, and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRB_i_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is an optional 5-bit unsigned immediate byte offset, in the range 0 to 31, defaulting to 0 and encoded in the "imm5" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRB_i_T2" symboldefcount="3">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRB_i_T3_pre" symboldefcount="4">
      <symbol link="sa_imm_2">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDRB_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then</line>
<line>    if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>        EncodingSpecificOperations();</line>
<line>        offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);</line>
<line>        address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,1], 32);</line>
<line>        if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
<line>else</line>
<line>    if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>        EncodingSpecificOperations();</line>
<line>        offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);</line>
<line>        address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,1], 32);</line>
<line>        if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldrb_l.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDRB_l" title="LDRB (literal) -- AArch32" type="instruction">
  <docvars>
    <docvar key="address-form" value="literal" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDRB" />
  </docvars>
  <heading>LDRB (literal)</heading>
  <desc>
    <brief>
      <para>Load Register Byte (literal)</para>
    </brief>
    <authored>
      <para>Load Register Byte (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>The alternative syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see <xref linkend="BABGCIBA">Use of labels in UAL instruction syntax</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="address-form" value="literal" />
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRB_l/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="LDRB_l_A1" oneofinclass="1" oneof="2" label="A1" bitdiffs="!(P == 0 &amp;&amp; W == 1)">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRB" />
        </docvars>
        <box hibit="24" width="4" name="P:W">
          <c>Z</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Normal form"><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_label" hover="The label of literal data item that is to be loaded into {syntax{&lt;Rt&gt;}}">&lt;label&gt;</a></asmtemplate>
        <asmtemplate comment="Alternative form"><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRB_l/A1_A.txt" mylink="aarch32.instrs.LDRB_l.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; W == '1' then SEE "LDRBT";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);</line>
<line>add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>if t == 15 || wback then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="wback = FALSE;" />
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction treats bit[24] as the P bit, and bit[21] as the writeback (W) bit, and uses the same addressing mode as described in <xref linkend="A32T32-base.instructions.LDRB_i">LDRB (immediate)</xref>. The instruction uses post-indexed addressing when P == '0' and uses pre-indexed addressing otherwise. The instruction is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="literal" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRB_l/T1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="LDRB_l_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRB" />
        </docvars>
        <asmtemplate comment="Preferred syntax"><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_label" hover="The label of literal data item that is to be loaded into {syntax{&lt;Rt&gt;}}">&lt;label&gt;</a></asmtemplate>
        <asmtemplate comment="Alternative syntax"><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRB_l/T1_A.txt" mylink="aarch32.instrs.LDRB_l.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rt == '1111' then SEE "PLD";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);  add = (U == '1');</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDRB_l_A1, LDRB_l_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRB_l_A1, LDRB_l_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRB_l_A1, LDRB_l_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRB_l_A1, LDRB_l_T1" symboldefcount="1">
      <symbol link="sa_label">&lt;label&gt;</symbol>
      <account encodedin="imm12">
        <intro>
          <para>The label of the literal data item that is to be loaded into <syntax>&lt;Rt&gt;</syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the instruction to this label. Permitted values of the offset are -4095 to 4095.</para>
          <para>If the offset is zero or positive, <field>imm32</field> is equal to the offset and <field>add</field> == <enumvalue>TRUE</enumvalue>, encoded as U == 1.</para>
          <para>If the offset is negative, <field>imm32</field> is equal to minus the offset and <field>add</field> == <enumvalue>FALSE</enumvalue>, encoded as U == 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRB_l_A1, LDRB_l_T1" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRB_l_A1" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 if omitted, and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRB_l_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is a 12-bit unsigned immediate byte offset, in the range 0 to 4095, encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDRB_l/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    base = <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4);</line>
<line>    address = if add then (base + imm32) else (base - imm32);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,1], 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldrb_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDRB_r" title="LDRB (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDRB" />
  </docvars>
  <heading>LDRB (register)</heading>
  <desc>
    <brief>
      <para>Load Register Byte (register)</para>
    </brief>
    <authored>
      <para>Load Register Byte (register) calculates an address from a base register value and an offset register value, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can optionally be shifted.  For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRB" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRB_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRB_r_A1_off" oneofinclass="3" oneof="5" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRB" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, </text><a link="sa_shift" hover="The shift to apply to the value read from {syntax{&lt;Rm&gt;}}">&lt;shift&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDRB_r_A1_post" oneofinclass="3" oneof="5" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRB" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, </text><a link="sa_shift" hover="The shift to apply to the value read from {syntax{&lt;Rm&gt;}}">&lt;shift&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="LDRB_r_A1_pre" oneofinclass="3" oneof="5" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRB" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, </text><a link="sa_shift" hover="The shift to apply to the value read from {syntax{&lt;Rm&gt;}}">&lt;shift&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRB_r/A1_A.txt" mylink="aarch32.instrs.LDRB_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; W == '1' then SEE "LDRBT";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
<line>if t == 15 || m == 15 then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; (n == 15 || n == t) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/LDRB_r/T1_A.txt">
        <box hibit="31" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="27" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="26" name="B" settings="1">
          <c>1</c>
        </box>
        <box hibit="25" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="21" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rt" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="LDRB_r_T1" oneofinclass="1" oneof="5" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRB" />
        </docvars>
        <asmtemplate><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRB_r/T1_A.txt" mylink="aarch32.instrs.LDRB_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="register-offset" />
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRB_r/T2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="6" settings="6">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRB_r_T2" oneofinclass="1" oneof="5" label="T2">
        <docvars>
          <docvar key="address-form" value="register-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRB" />
        </docvars>
        <asmtemplate comment="&lt;Rt&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
        <asmtemplate><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, LSL #</text><a link="sa_imm" hover="If present, the size of left shift to apply to the value from {syntax{&lt;Rm&gt;}}, in the range 1-3">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRB_r/T2_A.txt" mylink="aarch32.instrs.LDRB_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rt == '1111' then SEE "PLD";</line>
<line>if Rn == '1111' then SEE "LDRB (literal)";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm2));</line>
<line>if m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDRB_r_A1_off, LDRB_r_T1, LDRB_r_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRB_r_A1_off, LDRB_r_T1, LDRB_r_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRB_r_A1_off, LDRB_r_T1, LDRB_r_T2" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRB_r_A1_off" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRB_r_T1, LDRB_r_T2" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRB_r_A1_off" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRB_r_T1, LDRB_r_T2" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the index register is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRB_r_A1_off, LDRB_r_T1, LDRB_r_T2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRB_r_A1_off" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The shift to apply to the value read from <syntax>&lt;Rm&gt;</syntax>. If absent, no shift is applied. Otherwise, see <xref linkend="Chdibjii">Shifts applied to a register</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRB_r_T2" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>If present, the size of the left shift to apply to the value from <syntax>&lt;Rm&gt;</syntax>, in the range 1-3. <syntax>&lt;imm&gt;</syntax> is encoded in imm2. If absent, no shift is specified and imm2 is encoded as <binarynumber>0b00</binarynumber>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDRB_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    offset = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + offset) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - offset);</line>
<line>    address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,1],32);</line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldrbt.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDRBT" title="LDRBT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDRBT" />
  </docvars>
  <heading>LDRBT</heading>
  <desc>
    <brief>
      <para>Load Register Byte Unprivileged</para>
    </brief>
    <authored>
      <para>Load Register Byte Unprivileged loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
      <para>The memory access is restricted as if the PE were running in User mode. This makes no difference if the PE is actually running in User mode.</para>
      <para><instruction>LDRBT</instruction> is <arm-defined-word>unpredictable</arm-defined-word> in Hyp mode.</para>
      <para>The T32 instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged.</para>
      <para>The A32 instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRBT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRBT/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="LDRBT_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRBT" />
        </docvars>
        <asmtemplate><text>LDRBT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>] </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRBT/A1_A.txt" mylink="aarch32.instrs.LDRBT.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  postindex = TRUE;  add = (U == '1');</line>
<line>register_form = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);</line>
<line>if t == 15 || n == 15 || n == t then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction uses post-indexed addressing with the base register as PC. This is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction uses immediate offset addressing with the base register as PC, without writeback.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == t &amp;&amp; n != 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A2" oneof="3" id="iclass_a2" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="address-form" value="post-indexed" />
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRBT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRBT/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRBT_A2" oneofinclass="1" oneof="3" label="A2">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRBT" />
        </docvars>
        <asmtemplate><text>LDRBT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa__plusminus__1" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, </text><a link="sa_shift" hover="The shift to apply to the value read from {syntax{&lt;Rm&gt;}}">&lt;shift&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRBT/A2_A.txt" mylink="aarch32.instrs.LDRBT.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  postindex = TRUE;  add = (U == '1');</line>
<line>register_form = TRUE;  (shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
<line>if t == 15 || n == 15 || n == t || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == t &amp;&amp; n != 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRBT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRBT/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="LDRBT_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRBT" />
        </docvars>
        <asmtemplate><text>LDRBT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional 8-bit unsigned immediate byte offset [0-255], default 0 (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRBT/T1_A.txt" mylink="aarch32.instrs.LDRBT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "LDRB (literal)";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  postindex = FALSE;  add = TRUE;</line>
<line>register_form = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);</line>
<line>if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDRBT_A1, LDRBT_A2, LDRBT_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRBT_A1, LDRBT_A2, LDRBT_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRBT_A1" symboldefcount="1">
      <symbol link="sa_rt_1">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRBT_A2, LDRBT_T1" symboldefcount="2">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>For encoding A2 and T1: is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRBT_A1, LDRBT_A2, LDRBT_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRBT_A1" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>For encoding A1: specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRBT_A2" symboldefcount="2">
      <symbol link="sa__plusminus__1">+/-</symbol>
      <definition encodedin="U">
        <intro>For encoding A2: specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRBT_A2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRBT_A2" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The shift to apply to the value read from <syntax>&lt;Rm&gt;</syntax>. If absent, no shift is applied. Otherwise, see <xref linkend="Chdibjii">Shifts applied to a register</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRBT_T1" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the offset is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRBT_A1" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 if omitted, and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRBT_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is an optional 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 and encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDRBT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then UNPREDICTABLE;               // Hyp mode</line>
<line>    offset = if register_form then <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C) else imm32;</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + offset) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - offset);</line>
<line>    address = if postindex then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] else offset_addr;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-aarch32.MemU_unpriv.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU_unpriv[bits(32) address, integer size]">MemU_unpriv</a>[address,1],32);</line>
<line>    if postindex then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
</pstext>
    </ps>
  </ps_section>
  <constrained_unpredictables ps_block="Operation">
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>PSTATE.EL == EL2</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
      <cu_type>
        <cu_type_text>The instruction executes as <instruction>LDRB</instruction> (immediate).</cu_type_text>
      </cu_type>
    </cu_case>
  </constrained_unpredictables>
</instructionsection>
</file>
<file type="instructionsection" file="ldrd_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDRD_i" title="LDRD (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDRD" />
  </docvars>
  <heading>LDRD (immediate)</heading>
  <desc>
    <brief>
      <para>Load Register Dual (immediate)</para>
    </brief>
    <authored>
      <para>Load Register Dual (immediate) calculates an address from a base register value and an immediate offset, loads two words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
      <para>Related encodings: <xref linkend="T32.encoding_index.dstd">Load/store dual, load/store exclusive, table branch</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRD" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRD_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="imm4H" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4L" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRD_i_A1_off" oneofinclass="3" oneof="6" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRD" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2_1" hover="Second general-purpose register to be transferred">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDRD_i_A1_post" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRD" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2_1" hover="Second general-purpose register to be transferred">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="LDRD_i_A1_pre" oneofinclass="3" oneof="6" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRD" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2_1" hover="Second general-purpose register to be transferred">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRD_i/A1_A.txt" mylink="aarch32.instrs.LDRD_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "LDRD (literal)";</line>
<line>if Rt&lt;0&gt; == '1' then UNPREDICTABLE;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = t+1;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm4H:imm4L, 32);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>if P == '0' &amp;&amp; W == '1' then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; (n == t || n == t2) then UNPREDICTABLE;</line>
<line>if t2 == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; (n == t || n == t2)</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>P == '0' &amp;&amp; W == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction executes as an <instruction>LDRD</instruction> using one of offset, post-indexed, or pre-indexed addressing.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>Rt&lt;0&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="t&lt;0&gt; = '0'" />
          </cu_type>
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="t2 = t" />
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as described, with no change to its behavior and no additional side-effects. This does not apply when Rt == '1111'.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRD" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRD_i/T1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="LDRD_i_T1_off" oneofinclass="3" oneof="6" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRD" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="Unsigned immediate byte offset, multiple of 4 [0-1020], default 0 if omitted (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDRD_i_T1_post" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRD" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="Unsigned immediate byte offset, multiple of 4 [0-1020], default 0 if omitted (field &quot;imm8&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="LDRD_i_T1_pre" oneofinclass="3" oneof="6" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRD" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="Unsigned immediate byte offset, multiple of 4 [0-1020], default 0 if omitted (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRD_i/T1_A.txt" mylink="aarch32.instrs.LDRD_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; W == '0' then SEE "Related encodings";</line>
<line>if Rn == '1111' then SEE "LDRD (literal)";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (W == '1');</line>
<line>if wback &amp;&amp; (n == t || n == t2) then UNPREDICTABLE;</line>
<line>if t == 15 || t2 == 15 || t == t2 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; (n == t || n == t2)</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == t2</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_LDUNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDRD_i_A1_off, LDRD_i_T1_off" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRD_i_A1_off, LDRD_i_T1_off" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRD_i_A1_off" symboldefcount="1">
      <symbol link="sa_rt_1">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the first general-purpose register to be transferred, encoded in the "Rt" field. This register must be even-numbered and not R14.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRD_i_T1_off" symboldefcount="2">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the first general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRD_i_A1_off" symboldefcount="1">
      <symbol link="sa_rt2_1">&lt;Rt2&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the second general-purpose register to be transferred. This register must be <syntax>&lt;R(t+1)&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRD_i_T1_off" symboldefcount="2">
      <symbol link="sa_rt2">&lt;Rt2&gt;</symbol>
      <account encodedin="Rt2">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the second general-purpose register to be transferred, encoded in the "Rt2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRD_i_A1_off, LDRD_i_T1_off" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field. For PC use see <xref linkend="A32T32-base.instructions.LDRD_l">LDRD (literal)</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRD_i_A1_off, LDRD_i_T1_off" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRD_i_A1_off" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm4H:imm4L">
        <docvars>
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRD_i_T1_off" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the unsigned immediate byte offset, a multiple of 4, in the range 0 to 1020, defaulting to 0 if omitted, and encoded in the "imm8" field as &lt;imm&gt;/4.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDRD_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);</line>
<line>    address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    if <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, 8) then</line>
<line>        data = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,8];</line>
<line>        if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>)  then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = data&lt;63:32&gt;;</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t2] = data&lt;31:0&gt;;</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = data&lt;31:0&gt;;</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t2] = data&lt;63:32&gt;;</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,4];</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t2] = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address+4,4];</line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldrd_l.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDRD_l" title="LDRD (literal) -- AArch32" type="instruction">
  <docvars>
    <docvar key="address-form" value="literal" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDRD" />
  </docvars>
  <heading>LDRD (literal)</heading>
  <desc>
    <brief>
      <para>Load Register Dual (literal)</para>
    </brief>
    <authored>
      <para>Load Register Dual (literal) calculates an address from the PC value and an immediate offset, loads two words from memory, and writes them to two registers. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
      <para>Related encodings: <xref linkend="T32.encoding_index.dstd">Load/Store dual, Load/Store-Exclusive, Load-Acquire/Store-Release, table branch</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>The alternative syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see <xref linkend="BABGCIBA">Use of labels in UAL instruction syntax</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="address-form" value="literal" />
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRD_l/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="imm4H" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4L" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRD_l_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRD" />
        </docvars>
        <asmtemplate comment="Normal form"><text>LDRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2_1" hover="Second general-purpose register to be transferred">&lt;Rt2&gt;</a><text>, </text><a link="sa_label_1" hover="The label of literal data item that is to be loaded into {syntax{&lt;Rt&gt;}}">&lt;label&gt;</a></asmtemplate>
        <asmtemplate comment="Alternative form"><text>LDRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2_1" hover="Second general-purpose register to be transferred">&lt;Rt2&gt;</a><text>, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRD_l/A1_A.txt" mylink="aarch32.instrs.LDRD_l.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rt&lt;0&gt; == '1' then UNPREDICTABLE;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = t+1;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm4H:imm4L, 32);  add = (U == '1');</line>
<line>if t2 == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>Rt&lt;0&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="t&lt;0&gt; = '0';" />
          </cu_type>
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="t2 = t;" />
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as described, with no change to its behavior and no additional side-effects. This does not apply when Rt == '1111'.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>P == '0' || W == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction executes as if P == 1 and W == 0.'</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="literal" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRD_l/T1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="LDRD_l_T1" oneofinclass="1" oneof="2" label="T1" bitdiffs="!(P == 0 &amp;&amp; W == 0)">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRD" />
        </docvars>
        <box hibit="24" width="4" name="P:W">
          <c>Z</c>
          <c>Z</c>
        </box>
        <asmtemplate comment="Normal form"><text>LDRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a><text>, </text><a link="sa_label" hover="The label of literal data item that is to be loaded into {syntax{&lt;Rt&gt;}}">&lt;label&gt;</a></asmtemplate>
        <asmtemplate comment="Alternative form"><text>LDRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a><text>, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="Optional 8-bit unsigned immediate byte offset [0-255], default 0 (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRD_l/T1_A.txt" mylink="aarch32.instrs.LDRD_l.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; W == '0' then SEE "Related encodings";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2);</line>
<line>imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);  add = (U == '1');</line>
<line>if t == 15 || t2 == 15 || t == t2 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
<line>if W == '1' then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == t2</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_LDUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>W == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_WBSUPPRESS" />
          <cu_type>
            <cu_type_text>The instruction uses post-indexed addressing when P == '0' and uses pre-indexed addressing otherwise. The instruction is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDRD_l_A1, LDRD_l_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRD_l_A1, LDRD_l_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRD_l_A1" symboldefcount="1">
      <symbol link="sa_rt_1">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the first general-purpose register to be transferred, encoded in the "Rt" field. This register must be even-numbered and not R14.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRD_l_T1" symboldefcount="2">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the first general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRD_l_A1" symboldefcount="1">
      <symbol link="sa_rt2_1">&lt;Rt2&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the second general-purpose register to be transferred. This register must be <syntax>&lt;R(t+1)&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRD_l_T1" symboldefcount="2">
      <symbol link="sa_rt2">&lt;Rt2&gt;</symbol>
      <account encodedin="Rt2">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the second general-purpose register to be transferred, encoded in the "Rt2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRD_l_A1" symboldefcount="1">
      <symbol link="sa_label_1">&lt;label&gt;</symbol>
      <account encodedin="imm4H:imm4L">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: the label of the literal data item that is to be loaded into <syntax>&lt;Rt&gt;</syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the instruction to this label. Any value in the range -255 to 255 is permitted.</para>
          <para>If the offset is zero or positive, <field>imm32</field> is equal to the offset and <field>add</field> == <enumvalue>TRUE</enumvalue>, encoded as U == 1. If the offset is negative, <field>imm32</field> is equal to minus the offset and <field>add</field> == <enumvalue>FALSE</enumvalue>, encoded as U == 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRD_l_T1" symboldefcount="2">
      <symbol link="sa_label">&lt;label&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: the label of the literal data item that is to be loaded into <syntax>&lt;Rt&gt;</syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the instruction to this label. Permitted values of the offset are multiples of 4 in the range -1020 to 1020.</para>
          <para>If the offset is zero or positive, <field>imm32</field> is equal to the offset and <field>add</field> == <enumvalue>TRUE</enumvalue>, encoded as U == 1.</para>
          <para>If the offset is negative, <field>imm32</field> is equal to minus the offset and <field>add</field> == <enumvalue>FALSE</enumvalue>, encoded as U == 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRD_l_A1, LDRD_l_T1" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRD_l_A1" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm4H:imm4L">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRD_l_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the optional 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 and encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDRD_l/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = if add then (<a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4) + imm32) else (<a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4) - imm32);</line>
<line>    if <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, 8) then</line>
<line>        data = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,8];</line>
<line>        if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>) then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = data&lt;63:32&gt;;</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t2] = data&lt;31:0&gt;;</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = data&lt;31:0&gt;;</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t2] = data&lt;63:32&gt;;</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,4];</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t2] = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address+4,4];</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldrd_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDRD_r" title="LDRD (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
    <docvar key="mnemonic" value="LDRD" />
  </docvars>
  <heading>LDRD (register)</heading>
  <desc>
    <brief>
      <para>Load Register Dual (register)</para>
    </brief>
    <authored>
      <para>Load Register Dual (register) calculates an address from a base register value and a register offset, loads two words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRD" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRD_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRD_r_A1_off" oneofinclass="3" oneof="3" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRD" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDRD_r_A1_post" oneofinclass="3" oneof="3" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRD" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="LDRD_r_A1_pre" oneofinclass="3" oneof="3" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRD" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRD_r/A1_A.txt" mylink="aarch32.instrs.LDRD_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rt&lt;0&gt; == '1' then UNPREDICTABLE;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = t+1;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>if P == '0' &amp;&amp; W == '1' then UNPREDICTABLE;</line>
<line>if t2 == 15 || m == 15 || m == t || m == t2 then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; (n == 15 || n == t || n == t2) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; (n == t || n == t2)</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>P == '0' &amp;&amp; W == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction executes as an <instruction>LDRD</instruction> using one of offset, post-indexed, or pre-indexed addressing.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>m == t || m == t2</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction loads register Rm with an <arm-defined-word>unknown</arm-defined-word> value.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>Rt&lt;0&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="t&lt;0&gt; = '0'" />
          </cu_type>
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="t2 = t" />
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as described, with no change to its behavior and no additional side-effects. This does not apply when Rt == '1111'.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDRD_r_A1_off" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRD_r_A1_off" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRD_r_A1_off" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the first general-purpose register to be transferred, encoded in the "Rt" field. This register must be even-numbered and not R14.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRD_r_A1_off" symboldefcount="1">
      <symbol link="sa_rt2">&lt;Rt2&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the second general-purpose register to be transferred. This register must be <syntax>&lt;R(t+1)&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRD_r_A1_off" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRD_r_A1_off" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRD_r_A1_off" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDRD_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]);</line>
<line>    address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    if <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, 8) then</line>
<line>        data = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,8];</line>
<line>        if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>) then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = data&lt;63:32&gt;;</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t2] = data&lt;31:0&gt;;</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = data&lt;31:0&gt;;</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t2] = data&lt;63:32&gt;;</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,4];</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t2] = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address+4,4];</line>
<line></line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldrex.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDREX" title="LDREX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDREX" />
  </docvars>
  <heading>LDREX</heading>
  <desc>
    <brief>
      <para>Load Register Exclusive</para>
    </brief>
    <authored>
      <para>Load Register Exclusive calculates an address from a base register value and an immediate offset, loads a word from memory, writes it to a register and:</para>
      <list type="unordered">
        <listitem><content>If the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing PE in a global monitor.</content></listitem>
        <listitem><content>Causes the executing PE to indicate an active exclusive access in the local monitor.</content></listitem>
      </list>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDREX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDREX/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="xRt" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDREX_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDREX" />
        </docvars>
        <asmtemplate><text>LDREX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, </text><a>{#}</a><a link="sa_imm_1" hover="The immediate offset added to the value of {syntax{&lt;Rn&gt;}} to calculate the address">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDREX/A1_A.txt" mylink="aarch32.instrs.LDREX.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32); // Zero offset</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDREX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDREX/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rd" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="LDREX_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDREX" />
        </docvars>
        <asmtemplate><text>LDREX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa_imm" hover="The immediate offset added to the value of {syntax{&lt;Rn&gt;}} to calculate the address">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDREX/T1_A.txt" mylink="aarch32.instrs.LDREX.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDREX_A1, LDREX_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDREX_A1, LDREX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDREX_A1, LDREX_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDREX_A1, LDREX_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDREX_A1" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: the immediate offset added to the value of <syntax>&lt;Rn&gt;</syntax> to calculate the address. <syntax>&lt;imm&gt;</syntax> can only be 0 or omitted.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDREX_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: the immediate offset added to the value of <syntax>&lt;Rn&gt;</syntax> to calculate the address. <syntax>&lt;imm&gt;</syntax> can be omitted, meaning an offset of 0. Values are multiples of 4 in the range 0-1020.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDREX/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32;</line>
<line>    <a link="AArch32.SetExclusiveMonitors.2" file="shared_pseudocode.xml" hover="function: AArch32.SetExclusiveMonitors(bits(32) address, integer size)">AArch32.SetExclusiveMonitors</a>(address,4);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,4];</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldrexb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDREXB" title="LDREXB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDREXB" />
  </docvars>
  <heading>LDREXB</heading>
  <desc>
    <brief>
      <para>Load Register Exclusive Byte</para>
    </brief>
    <authored>
      <para>Load Register Exclusive Byte derives an address from a base register value, loads a byte from memory, zero-extends it to form a 32-bit word, writes it to a register and:</para>
      <list type="unordered">
        <listitem><content>If the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing PE in a global monitor.</content></listitem>
        <listitem><content>Causes the executing PE to indicate an active exclusive access in the local monitor.</content></listitem>
      </list>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDREXB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDREXB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="xRt" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDREXB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDREXB" />
        </docvars>
        <asmtemplate><text>LDREXB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDREXB/A1_A.txt" mylink="aarch32.instrs.LDREXB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDREXB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDREXB/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="5" width="2" name="sz" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rd" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDREXB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDREXB" />
        </docvars>
        <asmtemplate><text>LDREXB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDREXB/T1_A.txt" mylink="aarch32.instrs.LDREXB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDREXB_A1, LDREXB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDREXB_A1, LDREXB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDREXB_A1, LDREXB_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDREXB_A1, LDREXB_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDREXB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    <a link="AArch32.SetExclusiveMonitors.2" file="shared_pseudocode.xml" hover="function: AArch32.SetExclusiveMonitors(bits(32) address, integer size)">AArch32.SetExclusiveMonitors</a>(address,1);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,1], 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldrexd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDREXD" title="LDREXD -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDREXD" />
  </docvars>
  <heading>LDREXD</heading>
  <desc>
    <brief>
      <para>Load Register Exclusive Doubleword</para>
    </brief>
    <authored>
      <para>Load Register Exclusive Doubleword derives an address from a base register value, loads a 64-bit doubleword from memory, writes it to two registers and:</para>
      <list type="unordered">
        <listitem><content>If the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing PE in a global monitor.</content></listitem>
        <listitem><content>Causes the executing PE to indicate an active exclusive access in the local monitor.</content></listitem>
      </list>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDREXD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDREXD/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="xRt" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDREXD_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDREXD" />
        </docvars>
        <asmtemplate><text>LDREXD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2_1" hover="Second general-purpose register to be transferred">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDREXD/A1_A.txt" mylink="aarch32.instrs.LDREXD.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = t + 1;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if Rt&lt;0&gt; == '1' || t2 == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>Rt&lt;0&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="t&lt;0&gt; = '0'" />
          </cu_type>
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="t2 = t" />
          </cu_type>
          <cu_type constraint="Constraint_NONE" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>Rt == '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDREXD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDREXD/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="5" width="2" name="sz" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rd" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDREXD_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDREXD" />
        </docvars>
        <asmtemplate><text>LDREXD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDREXD/T1_A.txt" mylink="aarch32.instrs.LDREXD.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || t2 == 15 || t == t2 || n == 15 then UNPREDICTABLE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == t2</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_LDUNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDREXD_A1, LDREXD_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDREXD_A1, LDREXD_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDREXD_A1" symboldefcount="1">
      <symbol link="sa_rt_1">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the first general-purpose register to be transferred, encoded in the "Rt" field. <syntax>&lt;Rt&gt;</syntax> must be even-numbered and not R14.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDREXD_T1" symboldefcount="2">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the first general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDREXD_A1" symboldefcount="1">
      <symbol link="sa_rt2_1">&lt;Rt2&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the second general-purpose register to be transferred. <syntax>&lt;Rt2&gt;</syntax> must be <syntax>&lt;R(t+1)&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDREXD_T1" symboldefcount="2">
      <symbol link="sa_rt2">&lt;Rt2&gt;</symbol>
      <account encodedin="Rt2">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the second general-purpose register to be transferred, encoded in the "Rt2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDREXD_A1, LDREXD_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDREXD/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    <a link="AArch32.SetExclusiveMonitors.2" file="shared_pseudocode.xml" hover="function: AArch32.SetExclusiveMonitors(bits(32) address, integer size)">AArch32.SetExclusiveMonitors</a>(address,8);</line>
<line>    value = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,8];</line>
<line></line>
<line>    // Extract words from 64-bit loaded value such that R[t] is</line>
<line>    // loaded from address and R[t2] from address+4.</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t]  = if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>) then value&lt;63:32&gt; else value&lt;31:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t2] = if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>) then value&lt;31:0&gt; else value&lt;63:32&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldrexh.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDREXH" title="LDREXH -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDREXH" />
  </docvars>
  <heading>LDREXH</heading>
  <desc>
    <brief>
      <para>Load Register Exclusive Halfword</para>
    </brief>
    <authored>
      <para>Load Register Exclusive Halfword derives an address from a base register value, loads a halfword from memory, zero-extends it to form a 32-bit word, writes it to a register and:</para>
      <list type="unordered">
        <listitem><content>If the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing PE in a global monitor.</content></listitem>
        <listitem><content>Causes the executing PE to indicate an active exclusive access in the local monitor.</content></listitem>
      </list>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDREXH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDREXH/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="xRt" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDREXH_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDREXH" />
        </docvars>
        <asmtemplate><text>LDREXH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDREXH/A1_A.txt" mylink="aarch32.instrs.LDREXH.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDREXH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDREXH/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="5" width="2" name="sz" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rd" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="LDREXH_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDREXH" />
        </docvars>
        <asmtemplate><text>LDREXH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDREXH/T1_A.txt" mylink="aarch32.instrs.LDREXH.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDREXH_A1, LDREXH_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDREXH_A1, LDREXH_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDREXH_A1, LDREXH_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDREXH_A1, LDREXH_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDREXH/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    <a link="AArch32.SetExclusiveMonitors.2" file="shared_pseudocode.xml" hover="function: AArch32.SetExclusiveMonitors(bits(32) address, integer size)">AArch32.SetExclusiveMonitors</a>(address,2);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,2], 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldrh_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<instructionsection id="LDRH_i" title="LDRH (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDRH" />
  </docvars>
  <heading>LDRH (immediate)</heading>
  <desc>
    <brief>
      <para>Load Register Halfword (immediate)</para>
    </brief>
    <authored>
      <para>Load Register Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing.  For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRH" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRH_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="imm4H" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4L" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRH_i_A1_off" oneofinclass="3" oneof="8" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRH" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_3" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDRH_i_A1_post" oneofinclass="3" oneof="8" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRH" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_3" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="LDRH_i_A1_pre" oneofinclass="3" oneof="8" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRH" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_3" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRH_i/A1_A.txt" mylink="aarch32.instrs.LDRH_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "LDRH (literal)";</line>
<line>if P == '0' &amp;&amp; W == '1' then SEE "LDRHT";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm4H:imm4L, 32);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>if t == 15 || (wback &amp;&amp; n == t) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is UNKNOWN. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/LDRH_i/T1_A.txt">
        <box hibit="31" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="27" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="26" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="21" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rt" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="LDRH_i_T1" oneofinclass="1" oneof="8" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRH" />
        </docvars>
        <asmtemplate><text>LDRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional positive unsigned immediate byte offset (field &quot;imm5&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRH_i/T1_A.txt" mylink="aarch32.instrs.LDRH_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm5:'0', 32);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRH_i/T2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="LDRH_i_T2" oneofinclass="1" oneof="8" label="T2">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRH" />
        </docvars>
        <asmtemplate comment="&lt;Rt&gt;, &lt;Rn&gt;, &lt;imm&gt; can be represented in T1"><text>LDRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm_1" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
        <asmtemplate><text>LDRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm_1" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRH_i/T2_A.txt" mylink="aarch32.instrs.LDRH_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rt == '1111' then SEE "PLD (immediate)";</line>
<line>if Rn == '1111' then SEE "LDRH (literal)";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T3" oneof="4" id="iclass_t3" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRH" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRH_i/T3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="9" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="8" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="LDRH_i_T3_off" oneofinclass="3" oneof="8" label="Offset" bitdiffs="Rt != 1111 &amp;&amp; P == 1 &amp;&amp; U == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRH" />
        </docvars>
        <box hibit="15" width="4" name="Rt">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <box hibit="10" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="9" width="1" name="U">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #-</text><a link="sa_imm_2" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDRH_i_T3_post" oneofinclass="3" oneof="8" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRH" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_2" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="LDRH_i_T3_pre" oneofinclass="3" oneof="8" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRH" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_2" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRH_i/T3_A.txt" mylink="aarch32.instrs.LDRH_i.T3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "LDRH (literal)";</line>
<line>if Rt == '1111' &amp;&amp; P == '1' &amp;&amp; U == '0' &amp;&amp; W == '0' then SEE "PLDW (immediate)";</line>
<line>if P == '1' &amp;&amp; U == '1' &amp;&amp; W == '0' then SEE "LDRHT";</line>
<line>if P == '0' &amp;&amp; W == '0' then UNDEFINED;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (W == '1');</line>
<line>if (t == 15 &amp;&amp; W == '1') || (wback &amp;&amp; n == t) then UNPREDICTABLE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is UNKNOWN. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDRH_i_A1_off, LDRH_i_T1, LDRH_i_T2, LDRH_i_T3_pre" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRH_i_A1_off, LDRH_i_T1, LDRH_i_T2, LDRH_i_T3_pre" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRH_i_A1_off, LDRH_i_T1, LDRH_i_T2, LDRH_i_T3_pre" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRH_i_A1_off, LDRH_i_T2, LDRH_i_T3_pre" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>For encoding A1, T2 and T3: is the general-purpose base register, encoded in the "Rn" field. For PC use see <xref linkend="A32T32-base.instructions.LDRH_l">LDRH (literal)</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRH_i_T1" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRH_i_A1_off, LDRH_i_T3_pre" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRH_i_T1, LDRH_i_T2" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the offset is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRH_i_A1_off" symboldefcount="1">
      <symbol link="sa_imm_3">&lt;imm&gt;</symbol>
      <account encodedin="imm4H:imm4L">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRH_i_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the optional positive unsigned immediate byte offset, a multiple of 2, in the range 0 to 62, defaulting to 0 and encoded in the "imm5" field as &lt;imm&gt;/2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRH_i_T2" symboldefcount="3">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRH_i_T3_pre" symboldefcount="4">
      <symbol link="sa_imm_2">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDRH_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then</line>
<line>    if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>        EncodingSpecificOperations();</line>
<line>        offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);</line>
<line>        address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>        data = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,2];</line>
<line>        if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(data, 32);</line>
<line>else</line>
<line>    if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>        EncodingSpecificOperations();</line>
<line>        offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);</line>
<line>        address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>        data = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,2];</line>
<line>        if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(data, 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldrh_l.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDRH_l" title="LDRH (literal) -- AArch32" type="instruction">
  <docvars>
    <docvar key="address-form" value="literal" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDRH" />
  </docvars>
  <heading>LDRH (literal)</heading>
  <desc>
    <brief>
      <para>Load Register Halfword (literal)</para>
    </brief>
    <authored>
      <para>Load Register Halfword (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>The alternative syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see <xref linkend="BABGCIBA">Use of labels in UAL instruction syntax</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="address-form" value="literal" />
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRH_l/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="imm4H" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4L" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRH_l_A1" oneofinclass="1" oneof="2" label="A1" bitdiffs="!(P == 0 &amp;&amp; W == 1)">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRH" />
        </docvars>
        <box hibit="24" width="4" name="P:W">
          <c>Z</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Normal form"><text>LDRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_label_1" hover="The label of literal data item that is to be loaded into {syntax{&lt;Rt&gt;}}">&lt;label&gt;</a></asmtemplate>
        <asmtemplate comment="Alternative form"><text>LDRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRH_l/A1_A.txt" mylink="aarch32.instrs.LDRH_l.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; W == '1' then SEE "LDRHT";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm4H:imm4L, 32);</line>
<line>add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>if t == 15 || wback then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="wback = FALSE;" />
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction treats bit[24] as the P bit, and bit[21] as the writeback (W) bit, and uses the same addressing mode as described in <xref linkend="A32T32-base.instructions.LDRH_i">LDRH (immediate)</xref>. The instruction uses post-indexed addressing when P == '0' and uses pre-indexed addressing otherwise. The instruction is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="literal" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRH_l/T1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="LDRH_l_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRH" />
        </docvars>
        <asmtemplate comment="Preferred syntax"><text>LDRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_label" hover="The label of literal data item that is to be loaded into {syntax{&lt;Rt&gt;}}">&lt;label&gt;</a></asmtemplate>
        <asmtemplate comment="Alternative syntax"><text>LDRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRH_l/T1_A.txt" mylink="aarch32.instrs.LDRH_l.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rt == '1111' then SEE "PLD (literal)";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);  add = (U == '1');</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDRH_l_A1, LDRH_l_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRH_l_A1, LDRH_l_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRH_l_A1, LDRH_l_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRH_l_A1" symboldefcount="1">
      <symbol link="sa_label_1">&lt;label&gt;</symbol>
      <account encodedin="imm4H:imm4L">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: the label of the literal data item that is to be loaded into <syntax>&lt;Rt&gt;</syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the instruction to this label. Any value in the range -255 to 255 is permitted.</para>
          <para>If the offset is zero or positive, <field>imm32</field> is equal to the offset and <field>add</field> == <enumvalue>TRUE</enumvalue>, encoded as U == 1. If the offset is negative, <field>imm32</field> is equal to minus the offset and <field>add</field> == <enumvalue>FALSE</enumvalue>, encoded as U == 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRH_l_T1" symboldefcount="2">
      <symbol link="sa_label">&lt;label&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: the label of the literal data item that is to be loaded into <syntax>&lt;Rt&gt;</syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the instruction to this label. Permitted values of the offset are -4095 to 4095.</para>
          <para>If the offset is zero or positive, <field>imm32</field> is equal to the offset and <field>add</field> == <enumvalue>TRUE</enumvalue>, encoded as U == 1.</para>
          <para>If the offset is negative, <field>imm32</field> is equal to minus the offset and <field>add</field> == <enumvalue>FALSE</enumvalue>, encoded as U == 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRH_l_A1, LDRH_l_T1" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRH_l_A1" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm4H:imm4L">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRH_l_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is a 12-bit unsigned immediate byte offset, in the range 0 to 4095, encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDRH_l/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    base = <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4);</line>
<line>    address = if add then (base + imm32) else (base - imm32);</line>
<line>    data = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,2];</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(data, 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldrh_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDRH_r" title="LDRH (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDRH" />
  </docvars>
  <heading>LDRH (register)</heading>
  <desc>
    <brief>
      <para>Load Register Halfword (register)</para>
    </brief>
    <authored>
      <para>Load Register Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRH" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRH_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRH_r_A1_off" oneofinclass="3" oneof="5" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRH" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDRH_r_A1_post" oneofinclass="3" oneof="5" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRH" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="LDRH_r_A1_pre" oneofinclass="3" oneof="5" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRH" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRH_r/A1_A.txt" mylink="aarch32.instrs.LDRH_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; W == '1' then SEE "LDRHT";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
<line>if t == 15 || m == 15 then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; (n == 15 || n == t) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is UNKNOWN. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/LDRH_r/T1_A.txt">
        <box hibit="31" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="27" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="26" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="25" name="H" settings="1">
          <c>1</c>
        </box>
        <box hibit="24" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="21" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rt" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="LDRH_r_T1" oneofinclass="1" oneof="5" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRH" />
        </docvars>
        <asmtemplate><text>LDRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRH_r/T1_A.txt" mylink="aarch32.instrs.LDRH_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="register-offset" />
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRH_r/T2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="6" settings="6">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRH_r_T2" oneofinclass="1" oneof="5" label="T2">
        <docvars>
          <docvar key="address-form" value="register-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRH" />
        </docvars>
        <asmtemplate comment="&lt;Rt&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>LDRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
        <asmtemplate><text>LDRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, LSL #</text><a link="sa_imm" hover="If present, the size of left shift to apply to the value from {syntax{&lt;Rm&gt;}}, in the range 1-3">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRH_r/T2_A.txt" mylink="aarch32.instrs.LDRH_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "LDRH (literal)";</line>
<line>if Rt == '1111' then SEE "PLDW (register)";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm2));</line>
<line>if m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDRH_r_A1_off, LDRH_r_T1, LDRH_r_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRH_r_A1_off, LDRH_r_T1, LDRH_r_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRH_r_A1_off, LDRH_r_T1, LDRH_r_T2" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRH_r_A1_off" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRH_r_T1, LDRH_r_T2" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRH_r_A1_off" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRH_r_T1, LDRH_r_T2" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the index register is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRH_r_A1_off, LDRH_r_T1, LDRH_r_T2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRH_r_T2" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>If present, the size of the left shift to apply to the value from <syntax>&lt;Rm&gt;</syntax>, in the range 1-3. <syntax>&lt;imm&gt;</syntax> is encoded in imm2. If absent, no shift is specified and imm2 is encoded as <binarynumber>0b00</binarynumber>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDRH_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    offset = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + offset) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - offset);</line>
<line>    address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    data = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,2];</line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(data, 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldrht.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDRHT" title="LDRHT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDRHT" />
  </docvars>
  <heading>LDRHT</heading>
  <desc>
    <brief>
      <para>Load Register Halfword Unprivileged</para>
    </brief>
    <authored>
      <para>Load Register Halfword Unprivileged loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
      <para>The memory access is restricted as if the PE were running in User mode. This makes no difference if the PE is actually running in User mode.</para>
      <para><instruction>LDRHT</instruction> is <arm-defined-word>unpredictable</arm-defined-word> in Hyp mode.</para>
      <para>The T32 instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged.</para>
      <para>The A32 instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRHT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRHT/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="imm4H" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4L" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRHT_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRHT" />
        </docvars>
        <asmtemplate><text>LDRHT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>] </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRHT/A1_A.txt" mylink="aarch32.instrs.LDRHT.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  postindex = TRUE;  add = (U == '1');</line>
<line>register_form = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm4H:imm4L, 32);</line>
<line>if t == 15 || n == 15 || n == t then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction uses post-indexed addressing with the base register as PC. This is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction is treated as if bit[24] == '1' and bit[21] == '0'. The instruction uses immediate offset addressing with the base register as PC, without writeback.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == t &amp;&amp; n != 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A2" oneof="3" id="iclass_a2" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="address-form" value="post-indexed" />
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRHT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRHT/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRHT_A2" oneofinclass="1" oneof="3" label="A2">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRHT" />
        </docvars>
        <asmtemplate><text>LDRHT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa__plusminus__1" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRHT/A2_A.txt" mylink="aarch32.instrs.LDRHT.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  postindex = TRUE;  add = (U == '1');</line>
<line>register_form = TRUE;</line>
<line>if t == 15 || n == 15 || n == t || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == t &amp;&amp; n != 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRHT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRHT/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="LDRHT_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRHT" />
        </docvars>
        <asmtemplate><text>LDRHT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional 8-bit unsigned immediate byte offset [0-255], default 0 (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRHT/T1_A.txt" mylink="aarch32.instrs.LDRHT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "LDRH (literal)";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  postindex = FALSE;  add = TRUE;</line>
<line>register_form = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);</line>
<line>if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDRHT_A1, LDRHT_A2, LDRHT_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRHT_A1, LDRHT_A2, LDRHT_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRHT_A1, LDRHT_A2, LDRHT_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRHT_A1, LDRHT_A2, LDRHT_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRHT_A1" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>For encoding A1: specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRHT_A2" symboldefcount="2">
      <symbol link="sa__plusminus__1">+/-</symbol>
      <definition encodedin="U">
        <intro>For encoding A2: specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRHT_A2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRHT_T1" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the offset is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRHT_A1" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm4H:imm4L">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRHT_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is an optional 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 and encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDRHT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then UNPREDICTABLE;               // Hyp mode</line>
<line>    offset = if register_form then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m] else imm32;</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + offset) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - offset);</line>
<line>    address = if postindex then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] else offset_addr;</line>
<line>    data = <a link="impl-aarch32.MemU_unpriv.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU_unpriv[bits(32) address, integer size]">MemU_unpriv</a>[address,2];</line>
<line>    if postindex then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(data, 32);</line>
</pstext>
    </ps>
  </ps_section>
  <constrained_unpredictables ps_block="Operation">
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>PSTATE.EL == EL2</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
      <cu_type>
        <cu_type_text>The instruction executes as <instruction>LDRH</instruction> (immediate).</cu_type_text>
      </cu_type>
    </cu_case>
  </constrained_unpredictables>
</instructionsection>
</file>
<file type="instructionsection" file="ldrsb_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDRSB_i" title="LDRSB (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDRSB" />
  </docvars>
  <heading>LDRSB (immediate)</heading>
  <desc>
    <brief>
      <para>Load Register Signed Byte (immediate)</para>
    </brief>
    <authored>
      <para>Load Register Signed Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing.  For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRSB" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRSB_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="imm4H" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4L" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRSB_i_A1_off" oneofinclass="3" oneof="7" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRSB" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_2" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDRSB_i_A1_post" oneofinclass="3" oneof="7" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRSB" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_2" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="LDRSB_i_A1_pre" oneofinclass="3" oneof="7" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRSB" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDRSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_2" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRSB_i/A1_A.txt" mylink="aarch32.instrs.LDRSB_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "LDRSB (literal)";</line>
<line>if P == '0' &amp;&amp; W == '1' then SEE "LDRSBT";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm4H:imm4L, 32);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>if t == 15 || (wback &amp;&amp; n == t) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is UNKNOWN. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRSB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRSB_i/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="LDRSB_i_T1" oneofinclass="1" oneof="7" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRSB" />
        </docvars>
        <asmtemplate><text>LDRSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRSB_i/T1_A.txt" mylink="aarch32.instrs.LDRSB_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rt == '1111' then SEE "PLI";</line>
<line>if Rn == '1111' then SEE "LDRSB (literal)";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRSB" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRSB_i/T2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="9" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="8" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="LDRSB_i_T2_off" oneofinclass="3" oneof="7" label="Offset" bitdiffs="Rt != 1111 &amp;&amp; P == 1 &amp;&amp; U == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRSB" />
        </docvars>
        <box hibit="15" width="4" name="Rt">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <box hibit="10" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="9" width="1" name="U">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #-</text><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDRSB_i_T2_post" oneofinclass="3" oneof="7" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRSB" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDRSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="LDRSB_i_T2_pre" oneofinclass="3" oneof="7" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRSB" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDRSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRSB_i/T2_A.txt" mylink="aarch32.instrs.LDRSB_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rt == '1111' &amp;&amp; P == '1' &amp;&amp; U == '0' &amp;&amp; W == '0' then SEE "PLI";</line>
<line>if Rn == '1111' then SEE "LDRSB (literal)";</line>
<line>if P == '1' &amp;&amp; U == '1' &amp;&amp; W == '0' then SEE "LDRSBT";</line>
<line>if P == '0' &amp;&amp; W == '0' then UNDEFINED;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (W == '1');</line>
<line>if (t == 15 &amp;&amp; W == '1') || (wback &amp;&amp; n == t) then UNPREDICTABLE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is UNKNOWN. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDRSB_i_A1_off, LDRSB_i_T1, LDRSB_i_T2_pre" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSB_i_A1_off, LDRSB_i_T1, LDRSB_i_T2_pre" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSB_i_A1_off, LDRSB_i_T1, LDRSB_i_T2_pre" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSB_i_A1_off, LDRSB_i_T1, LDRSB_i_T2_pre" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field. For PC use see <xref linkend="A32T32-base.instructions.LDRSB_l">LDRSB (literal)</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSB_i_A1_off, LDRSB_i_T2_pre" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRSB_i_T1" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the offset is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSB_i_A1_off" symboldefcount="1">
      <symbol link="sa_imm_2">&lt;imm&gt;</symbol>
      <account encodedin="imm4H:imm4L">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSB_i_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSB_i_T2_pre" symboldefcount="3">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDRSB_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);</line>
<line>    address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(<a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,1], 32);</line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldrsb_l.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDRSB_l" title="LDRSB (literal) -- AArch32" type="instruction">
  <docvars>
    <docvar key="address-form" value="literal" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDRSB" />
  </docvars>
  <heading>LDRSB (literal)</heading>
  <desc>
    <brief>
      <para>Load Register Signed Byte (literal)</para>
    </brief>
    <authored>
      <para>Load Register Signed Byte (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>The alternative syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see <xref linkend="BABGCIBA">Use of labels in UAL instruction syntax</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="address-form" value="literal" />
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRSB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRSB_l/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="imm4H" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4L" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRSB_l_A1" oneofinclass="1" oneof="2" label="A1" bitdiffs="!(P == 0 &amp;&amp; W == 1)">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRSB" />
        </docvars>
        <box hibit="24" width="4" name="P:W">
          <c>Z</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Normal form"><text>LDRSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_label_1" hover="The label of literal data item that is to be loaded into {syntax{&lt;Rt&gt;}}">&lt;label&gt;</a></asmtemplate>
        <asmtemplate comment="Alternative form"><text>LDRSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRSB_l/A1_A.txt" mylink="aarch32.instrs.LDRSB_l.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; W == '1' then SEE "LDRSBT";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm4H:imm4L, 32);</line>
<line>add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>if t == 15 || wback then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="wback = FALSE;" />
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction treats bit[24] as the P bit, and bit[21] as the writeback (W) bit, and uses the same addressing mode as described in <xref linkend="A32T32-base.instructions.LDRSB_i">LDRSB (immediate)</xref>. The instruction uses post-indexed addressing when P == '0' and uses pre-indexed addressing otherwise. The instruction is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="literal" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRSB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRSB_l/T1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="LDRSB_l_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRSB" />
        </docvars>
        <asmtemplate comment="Preferred syntax"><text>LDRSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_label" hover="The label of literal data item that is to be loaded into {syntax{&lt;Rt&gt;}}">&lt;label&gt;</a></asmtemplate>
        <asmtemplate comment="Alternative syntax"><text>LDRSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRSB_l/T1_A.txt" mylink="aarch32.instrs.LDRSB_l.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rt == '1111' then SEE "PLI";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);  add = (U == '1');</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDRSB_l_A1, LDRSB_l_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSB_l_A1, LDRSB_l_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSB_l_A1, LDRSB_l_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSB_l_A1" symboldefcount="1">
      <symbol link="sa_label_1">&lt;label&gt;</symbol>
      <account encodedin="imm4H:imm4L">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: the label of the literal data item that is to be loaded into <syntax>&lt;Rt&gt;</syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the instruction to this label. Any value in the range -255 to 255 is permitted.</para>
          <para>If the offset is zero or positive, <field>imm32</field> is equal to the offset and <field>add</field> == <enumvalue>TRUE</enumvalue>, encoded as U == 1. If the offset is negative, <field>imm32</field> is equal to minus the offset and <field>add</field> == <enumvalue>FALSE</enumvalue>, encoded as U == 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSB_l_T1" symboldefcount="2">
      <symbol link="sa_label">&lt;label&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: the label of the literal data item that is to be loaded into <syntax>&lt;Rt&gt;</syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the instruction to this label. Permitted values of the offset are -4095 to 4095.</para>
          <para>If the offset is zero or positive, <field>imm32</field> is equal to the offset and <field>add</field> == <enumvalue>TRUE</enumvalue>, encoded as U == 1.</para>
          <para>If the offset is negative, <field>imm32</field> is equal to minus the offset and <field>add</field> == <enumvalue>FALSE</enumvalue>, encoded as U == 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSB_l_A1, LDRSB_l_T1" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRSB_l_A1" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm4H:imm4L">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSB_l_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is a 12-bit unsigned immediate byte offset, in the range 0 to 4095, encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDRSB_l/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    base = <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4);</line>
<line>    address = if add then (base + imm32) else (base - imm32);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(<a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,1], 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldrsb_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDRSB_r" title="LDRSB (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDRSB" />
  </docvars>
  <heading>LDRSB (register)</heading>
  <desc>
    <brief>
      <para>Load Register Signed Byte (register)</para>
    </brief>
    <authored>
      <para>Load Register Signed Byte (register) calculates an address from a base register value and an offset register value, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRSB" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRSB_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRSB_r_A1_off" oneofinclass="3" oneof="5" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRSB" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDRSB_r_A1_post" oneofinclass="3" oneof="5" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRSB" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="LDRSB_r_A1_pre" oneofinclass="3" oneof="5" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRSB" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDRSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRSB_r/A1_A.txt" mylink="aarch32.instrs.LDRSB_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; W == '1' then SEE "LDRSBT";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
<line>if t == 15 || m == 15 then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; (n == 15 || n == t) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is UNKNOWN. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRSB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/LDRSB_r/T1_A.txt">
        <box hibit="31" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="27" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="26" name="B" settings="1">
          <c>1</c>
        </box>
        <box hibit="25" name="H" settings="1">
          <c>1</c>
        </box>
        <box hibit="24" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="21" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rt" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="LDRSB_r_T1" oneofinclass="1" oneof="5" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRSB" />
        </docvars>
        <asmtemplate><text>LDRSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRSB_r/T1_A.txt" mylink="aarch32.instrs.LDRSB_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="register-offset" />
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRSB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRSB_r/T2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="6" settings="6">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRSB_r_T2" oneofinclass="1" oneof="5" label="T2">
        <docvars>
          <docvar key="address-form" value="register-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRSB" />
        </docvars>
        <asmtemplate comment="&lt;Rt&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>LDRSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
        <asmtemplate><text>LDRSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, LSL #</text><a link="sa_imm" hover="If present, the size of left shift to apply to the value from {syntax{&lt;Rm&gt;}}, in the range 1-3">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRSB_r/T2_A.txt" mylink="aarch32.instrs.LDRSB_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rt == '1111' then SEE "PLI";</line>
<line>if Rn == '1111' then SEE "LDRSB (literal)";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm2));</line>
<line>if m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDRSB_r_A1_off, LDRSB_r_T1, LDRSB_r_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSB_r_A1_off, LDRSB_r_T1, LDRSB_r_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSB_r_A1_off, LDRSB_r_T1, LDRSB_r_T2" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSB_r_A1_off" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSB_r_T1, LDRSB_r_T2" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSB_r_A1_off" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRSB_r_T1, LDRSB_r_T2" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the index register is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSB_r_A1_off, LDRSB_r_T1, LDRSB_r_T2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSB_r_T2" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>If present, the size of the left shift to apply to the value from <syntax>&lt;Rm&gt;</syntax>, in the range 1-3. <syntax>&lt;imm&gt;</syntax> is encoded in imm2. If absent, no shift is specified and imm2 is encoded as <binarynumber>0b00</binarynumber>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDRSB_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    offset = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + offset) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - offset);</line>
<line>    address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(<a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,1], 32);</line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldrsbt.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDRSBT" title="LDRSBT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDRSBT" />
  </docvars>
  <heading>LDRSBT</heading>
  <desc>
    <brief>
      <para>Load Register Signed Byte Unprivileged</para>
    </brief>
    <authored>
      <para>Load Register Signed Byte Unprivileged loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
      <para>The memory access is restricted as if the PE were running in User mode. This makes no difference if the PE is actually running in User mode.</para>
      <para><instruction>LDRSBT</instruction> is <arm-defined-word>unpredictable</arm-defined-word> in Hyp mode.</para>
      <para>The T32 instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged.</para>
      <para>The A32 instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRSBT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRSBT/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="imm4H" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4L" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRSBT_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRSBT" />
        </docvars>
        <asmtemplate><text>LDRSBT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>] </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRSBT/A1_A.txt" mylink="aarch32.instrs.LDRSBT.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  postindex = TRUE;  add = (U == '1');</line>
<line>register_form = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm4H:imm4L, 32);</line>
<line>if t == 15 || n == 15 || n == t then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction uses post-indexed addressing with the base register as PC. This is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction is treated as if bit[24] == '1' and bit[21] == '0'. The instruction uses immediate offset addressing with the base register as PC, without writeback.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == t &amp;&amp; n != 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A2" oneof="3" id="iclass_a2" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="address-form" value="post-indexed" />
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRSBT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRSBT/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRSBT_A2" oneofinclass="1" oneof="3" label="A2">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRSBT" />
        </docvars>
        <asmtemplate><text>LDRSBT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa__plusminus__1" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRSBT/A2_A.txt" mylink="aarch32.instrs.LDRSBT.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  postindex = TRUE;  add = (U == '1');</line>
<line>register_form = TRUE;</line>
<line>if t == 15 || n == 15 || n == t || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == t &amp;&amp; n != 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRSBT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRSBT/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="LDRSBT_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRSBT" />
        </docvars>
        <asmtemplate><text>LDRSBT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional 8-bit unsigned immediate byte offset [0-255], default 0 (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRSBT/T1_A.txt" mylink="aarch32.instrs.LDRSBT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "LDRSB (literal)";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  postindex = FALSE;  add = TRUE;</line>
<line>register_form = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);</line>
<line>if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDRSBT_A1, LDRSBT_A2, LDRSBT_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSBT_A1, LDRSBT_A2, LDRSBT_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSBT_A1, LDRSBT_A2, LDRSBT_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSBT_A1, LDRSBT_A2, LDRSBT_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSBT_A1" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>For encoding A1: specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRSBT_A2" symboldefcount="2">
      <symbol link="sa__plusminus__1">+/-</symbol>
      <definition encodedin="U">
        <intro>For encoding A2: specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRSBT_A2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSBT_T1" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the offset is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSBT_A1" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm4H:imm4L">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSBT_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is an optional 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 and encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDRSBT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then UNPREDICTABLE;               // Hyp mode</line>
<line>    offset = if register_form then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m] else imm32;</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + offset) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - offset);</line>
<line>    address = if postindex then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] else offset_addr;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(<a link="impl-aarch32.MemU_unpriv.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU_unpriv[bits(32) address, integer size]">MemU_unpriv</a>[address,1], 32);</line>
<line>    if postindex then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
</pstext>
    </ps>
  </ps_section>
  <constrained_unpredictables ps_block="Operation">
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>PSTATE.EL == EL2</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
      <cu_type>
        <cu_type_text>The instruction executes as <instruction>LDRSB</instruction> (immediate).</cu_type_text>
      </cu_type>
    </cu_case>
  </constrained_unpredictables>
</instructionsection>
</file>
<file type="instructionsection" file="ldrsh_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDRSH_i" title="LDRSH (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDRSH" />
  </docvars>
  <heading>LDRSH (immediate)</heading>
  <desc>
    <brief>
      <para>Load Register Signed Halfword (immediate)</para>
    </brief>
    <authored>
      <para>Load Register Signed Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing.  For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
      <para>Related instructions: <xref linkend="T32.encoding_index.ldst">Load/store single</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRSH" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRSH_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="imm4H" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4L" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRSH_i_A1_off" oneofinclass="3" oneof="7" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRSH" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_2" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDRSH_i_A1_post" oneofinclass="3" oneof="7" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRSH" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_2" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="LDRSH_i_A1_pre" oneofinclass="3" oneof="7" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRSH" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_2" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRSH_i/A1_A.txt" mylink="aarch32.instrs.LDRSH_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "LDRSH (literal)";</line>
<line>if P == '0' &amp;&amp; W == '1' then SEE "LDRSHT";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm4H:imm4L, 32);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>if t == 15 || (wback &amp;&amp; n == t) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRSH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRSH_i/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="LDRSH_i_T1" oneofinclass="1" oneof="7" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRSH" />
        </docvars>
        <asmtemplate><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRSH_i/T1_A.txt" mylink="aarch32.instrs.LDRSH_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "LDRSH (literal)";</line>
<line>if Rt == '1111' then SEE "Related instructions";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRSH" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRSH_i/T2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="9" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="8" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="LDRSH_i_T2_off" oneofinclass="3" oneof="7" label="Offset" bitdiffs="Rt != 1111 &amp;&amp; P == 1 &amp;&amp; U == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRSH" />
        </docvars>
        <box hibit="15" width="4" name="Rt">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <box hibit="10" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="9" width="1" name="U">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #-</text><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDRSH_i_T2_post" oneofinclass="3" oneof="7" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRSH" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="LDRSH_i_T2_pre" oneofinclass="3" oneof="7" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRSH" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRSH_i/T2_A.txt" mylink="aarch32.instrs.LDRSH_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "LDRSH (literal)";</line>
<line>if Rt == '1111' &amp;&amp; P == '1' &amp;&amp; U == '0' &amp;&amp; W == '0' then SEE "Related instructions";</line>
<line>if P == '1' &amp;&amp; U == '1' &amp;&amp; W == '0' then SEE "LDRSHT";</line>
<line>if P == '0' &amp;&amp; W == '0' then UNDEFINED;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (W == '1');</line>
<line>if (t == 15 &amp;&amp; W == '1') || (wback &amp;&amp; n == t) then UNPREDICTABLE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such an instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDRSH_i_A1_off, LDRSH_i_T1, LDRSH_i_T2_pre" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSH_i_A1_off, LDRSH_i_T1, LDRSH_i_T2_pre" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSH_i_A1_off, LDRSH_i_T1, LDRSH_i_T2_pre" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSH_i_A1_off, LDRSH_i_T1, LDRSH_i_T2_pre" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field. For PC use see <xref linkend="A32T32-base.instructions.LDRSH_l">LDRSH (literal)</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSH_i_A1_off, LDRSH_i_T2_pre" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRSH_i_T1" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the offset is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSH_i_A1_off" symboldefcount="1">
      <symbol link="sa_imm_2">&lt;imm&gt;</symbol>
      <account encodedin="imm4H:imm4L">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSH_i_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSH_i_T2_pre" symboldefcount="3">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDRSH_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);</line>
<line>    address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    data = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,2];</line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(data, 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldrsh_l.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDRSH_l" title="LDRSH (literal) -- AArch32" type="instruction">
  <docvars>
    <docvar key="address-form" value="literal" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDRSH" />
  </docvars>
  <heading>LDRSH (literal)</heading>
  <desc>
    <brief>
      <para>Load Register Signed Halfword (literal)</para>
    </brief>
    <authored>
      <para>Load Register Signed Halfword (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
      <para>Related instructions: <xref linkend="T32.encoding_index.ldlit_signed">Load, signed (literal)</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>The alternative syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see <xref linkend="BABGCIBA">Use of labels in UAL instruction syntax</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="address-form" value="literal" />
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRSH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRSH_l/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="imm4H" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4L" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRSH_l_A1" oneofinclass="1" oneof="2" label="A1" bitdiffs="!(P == 0 &amp;&amp; W == 1)">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRSH" />
        </docvars>
        <box hibit="24" width="4" name="P:W">
          <c>Z</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Normal form"><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_label_1" hover="The label of literal data item that is to be loaded into {syntax{&lt;Rt&gt;}}">&lt;label&gt;</a></asmtemplate>
        <asmtemplate comment="Alternative form"><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRSH_l/A1_A.txt" mylink="aarch32.instrs.LDRSH_l.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; W == '1' then SEE "LDRSHT";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm4H:imm4L, 32);</line>
<line>add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>if t == 15 || wback then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="wback = FALSE;" />
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction treats bit[24] as the P bit, and bit[21] as the writeback (W) bit, and uses the same addressing mode as described in <xref linkend="A32T32-base.instructions.LDRSH_i">LDRSH (immediate)</xref>. The instruction uses post-indexed addressing when P == '0' and uses pre-indexed addressing otherwise. The instruction is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="literal" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRSH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRSH_l/T1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="LDRSH_l_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRSH" />
        </docvars>
        <asmtemplate comment="Preferred syntax"><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_label" hover="The label of literal data item that is to be loaded into {syntax{&lt;Rt&gt;}}">&lt;label&gt;</a></asmtemplate>
        <asmtemplate comment="Alternative syntax"><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRSH_l/T1_A.txt" mylink="aarch32.instrs.LDRSH_l.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rt == '1111' then SEE "Related instructions";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);  add = (U == '1');</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDRSH_l_A1, LDRSH_l_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSH_l_A1, LDRSH_l_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSH_l_A1, LDRSH_l_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSH_l_A1" symboldefcount="1">
      <symbol link="sa_label_1">&lt;label&gt;</symbol>
      <account encodedin="imm4H:imm4L">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: the label of the literal data item that is to be loaded into <syntax>&lt;Rt&gt;</syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the instruction to this label. Any value in the range -255 to 255 is permitted.</para>
          <para>If the offset is zero or positive, <field>imm32</field> is equal to the offset and <field>add</field> == <enumvalue>TRUE</enumvalue>, encoded as U == 1. If the offset is negative, <field>imm32</field> is equal to minus the offset and <field>add</field> == <enumvalue>FALSE</enumvalue>, encoded as U == 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSH_l_T1" symboldefcount="2">
      <symbol link="sa_label">&lt;label&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: the label of the literal data item that is to be loaded into <syntax>&lt;Rt&gt;</syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the instruction to this label. Permitted values of the offset are -4095 to 4095.</para>
          <para>If the offset is zero or positive, <field>imm32</field> is equal to the offset and <field>add</field> == <enumvalue>TRUE</enumvalue>, encoded as U == 1.</para>
          <para>If the offset is negative, <field>imm32</field> is equal to minus the offset and <field>add</field> == <enumvalue>FALSE</enumvalue>, encoded as U == 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSH_l_A1, LDRSH_l_T1" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRSH_l_A1" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm4H:imm4L">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSH_l_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is a 12-bit unsigned immediate byte offset, in the range 0 to 4095, encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDRSH_l/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    base = <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4);</line>
<line>    address = if add then (base + imm32) else (base - imm32);</line>
<line>    data = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,2];</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(data, 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldrsh_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDRSH_r" title="LDRSH (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDRSH" />
  </docvars>
  <heading>LDRSH (register)</heading>
  <desc>
    <brief>
      <para>Load Register Signed Halfword (register)</para>
    </brief>
    <authored>
      <para>Load Register Signed Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
      <para>Related instructions: <xref linkend="T32.encoding_index.ldst_signed_reg">Load/store, signed (register offset)</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRSH" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRSH_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRSH_r_A1_off" oneofinclass="3" oneof="5" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRSH" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="LDRSH_r_A1_post" oneofinclass="3" oneof="5" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRSH" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="LDRSH_r_A1_pre" oneofinclass="3" oneof="5" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRSH" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRSH_r/A1_A.txt" mylink="aarch32.instrs.LDRSH_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; W == '1' then SEE "LDRSHT";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
<line>if t == 15 || m == 15 then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; (n == 15 || n == t) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is &lt;arm-defined-word&gt;unknown&lt;/arm-defined-word&gt;. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRSH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/LDRSH_r/T1_A.txt">
        <box hibit="31" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="27" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="26" name="B" settings="1">
          <c>1</c>
        </box>
        <box hibit="25" name="H" settings="1">
          <c>1</c>
        </box>
        <box hibit="24" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="21" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rt" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="LDRSH_r_T1" oneofinclass="1" oneof="5" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRSH" />
        </docvars>
        <asmtemplate><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRSH_r/T1_A.txt" mylink="aarch32.instrs.LDRSH_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="register-offset" />
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRSH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRSH_r/T2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="6" settings="6">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRSH_r_T2" oneofinclass="1" oneof="5" label="T2">
        <docvars>
          <docvar key="address-form" value="register-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRSH" />
        </docvars>
        <asmtemplate comment="&lt;Rt&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
        <asmtemplate><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, LSL #</text><a link="sa_imm" hover="If present, the size of left shift to apply to the value from {syntax{&lt;Rm&gt;}}, in the range 1-3">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRSH_r/T2_A.txt" mylink="aarch32.instrs.LDRSH_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "LDRSH (literal)";</line>
<line>if Rt == '1111' then SEE "Related instructions";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm2));</line>
<line>if m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDRSH_r_A1_off, LDRSH_r_T1, LDRSH_r_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSH_r_A1_off, LDRSH_r_T1, LDRSH_r_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSH_r_A1_off, LDRSH_r_T1, LDRSH_r_T2" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSH_r_A1_off" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSH_r_T1, LDRSH_r_T2" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSH_r_A1_off" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRSH_r_T1, LDRSH_r_T2" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the index register is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSH_r_A1_off, LDRSH_r_T1, LDRSH_r_T2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSH_r_T2" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>If present, the size of the left shift to apply to the value from <syntax>&lt;Rm&gt;</syntax>, in the range 1-3. <syntax>&lt;imm&gt;</syntax> is encoded in imm2. If absent, no shift is specified and imm2 is encoded as <binarynumber>0b00</binarynumber>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDRSH_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    offset = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + offset) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - offset);</line>
<line>    address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    data = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,2];</line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(data, 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ldrsht.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDRSHT" title="LDRSHT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDRSHT" />
  </docvars>
  <heading>LDRSHT</heading>
  <desc>
    <brief>
      <para>Load Register Signed Halfword Unprivileged</para>
    </brief>
    <authored>
      <para>Load Register Signed Halfword Unprivileged loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
      <para>The memory access is restricted as if the PE were running in User mode. This makes no difference if the PE is actually running in User mode.</para>
      <para><instruction>LDRSHT</instruction> is <arm-defined-word>unpredictable</arm-defined-word> in Hyp mode.</para>
      <para>The T32 instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged.</para>
      <para>The A32 instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRSHT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRSHT/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="imm4H" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4L" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRSHT_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRSHT" />
        </docvars>
        <asmtemplate><text>LDRSHT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>] </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRSHT/A1_A.txt" mylink="aarch32.instrs.LDRSHT.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  postindex = TRUE;  add = (U == '1');</line>
<line>register_form = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm4H:imm4L, 32);</line>
<line>if t == 15 || n == 15 || n == t then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction uses post-indexed addressing with the base register as PC. This is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction is treated as if bit[24] == '1' and bit[21] == '0'. The instruction uses immediate offset addressing with the base register as PC, without writeback.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == t &amp;&amp; n != 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A2" oneof="3" id="iclass_a2" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="address-form" value="post-indexed" />
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRSHT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRSHT/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRSHT_A2" oneofinclass="1" oneof="3" label="A2">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRSHT" />
        </docvars>
        <asmtemplate><text>LDRSHT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa__plusminus__1" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRSHT/A2_A.txt" mylink="aarch32.instrs.LDRSHT.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  postindex = TRUE;  add = (U == '1');</line>
<line>register_form = TRUE;</line>
<line>if t == 15 || n == 15 || n == t || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == t &amp;&amp; n != 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRSHT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRSHT/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="LDRSHT_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRSHT" />
        </docvars>
        <asmtemplate><text>LDRSHT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional 8-bit unsigned immediate byte offset [0-255], default 0 (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRSHT/T1_A.txt" mylink="aarch32.instrs.LDRSHT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "LDRSH (literal)";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  postindex = FALSE;  add = TRUE;</line>
<line>register_form = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);</line>
<line>if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDRSHT_A1, LDRSHT_A2, LDRSHT_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSHT_A1, LDRSHT_A2, LDRSHT_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSHT_A1, LDRSHT_A2, LDRSHT_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSHT_A1, LDRSHT_A2, LDRSHT_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSHT_A1" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>For encoding A1: specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRSHT_A2" symboldefcount="2">
      <symbol link="sa__plusminus__1">+/-</symbol>
      <definition encodedin="U">
        <intro>For encoding A2: specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRSHT_A2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSHT_T1" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the offset is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSHT_A1" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm4H:imm4L">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSHT_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is an optional 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 and encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDRSHT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then UNPREDICTABLE;               // Hyp mode</line>
<line>    offset = if register_form then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m] else imm32;</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + offset) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - offset);</line>
<line>    address = if postindex then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] else offset_addr;</line>
<line>    data = <a link="impl-aarch32.MemU_unpriv.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU_unpriv[bits(32) address, integer size]">MemU_unpriv</a>[address,2];</line>
<line>    if postindex then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(data, 32);</line>
</pstext>
    </ps>
  </ps_section>
  <constrained_unpredictables ps_block="Operation">
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>PSTATE.EL == EL2</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
      <cu_type>
        <cu_type_text>The instruction executes as <instruction>LDRSH</instruction> (immediate).</cu_type_text>
      </cu_type>
    </cu_case>
  </constrained_unpredictables>
</instructionsection>
</file>
<file type="instructionsection" file="ldrt.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LDRT" title="LDRT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDRT" />
  </docvars>
  <heading>LDRT</heading>
  <desc>
    <brief>
      <para>Load Register Unprivileged</para>
    </brief>
    <authored>
      <para>Load Register Unprivileged loads a word from memory, and writes it to a register. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
      <para>The memory access is restricted as if the PE were running in User mode. This makes no difference if the PE is actually running in User mode.</para>
      <para><instruction>LDRT</instruction> is <arm-defined-word>unpredictable</arm-defined-word> in Hyp mode.</para>
      <para>The T32 instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged.</para>
      <para>The A32 instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRT/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="LDRT_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRT" />
        </docvars>
        <asmtemplate><text>LDRT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>] </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRT/A1_A.txt" mylink="aarch32.instrs.LDRT.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  postindex = TRUE;  add = (U == '1');</line>
<line>register_form = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);</line>
<line>if t == 15 || n == 15 || n == t then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction uses post-indexed addressing with the base register as PC. This is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction is treated as if bit[24] == '1' and bit[21] == '0'. The instruction uses immediate offset addressing with the base register as PC, without writeback.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == t &amp;&amp; n != 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A2" oneof="3" id="iclass_a2" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="address-form" value="post-indexed" />
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDRT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/LDRT/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LDRT_A2" oneofinclass="1" oneof="3" label="A2">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDRT" />
        </docvars>
        <asmtemplate><text>LDRT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa__plusminus__1" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, </text><a link="sa_shift" hover="The shift to apply to the value read from {syntax{&lt;Rm&gt;}}">&lt;shift&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRT/A2_A.txt" mylink="aarch32.instrs.LDRT.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  postindex = TRUE;  add = (U == '1');</line>
<line>register_form = TRUE;  (shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
<line>if t == 15 || n == 15 || n == t || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == t &amp;&amp; n != 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDRT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/LDRT/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="LDRT_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDRT" />
        </docvars>
        <asmtemplate><text>LDRT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional 8-bit unsigned immediate byte offset [0-255], default 0 (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/LDRT/T1_A.txt" mylink="aarch32.instrs.LDRT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "LDR (literal)";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  postindex = FALSE;  add = TRUE;</line>
<line>register_form = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);</line>
<line>if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDRT_A1, LDRT_A2, LDRT_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRT_A1, LDRT_A2, LDRT_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRT_A1" symboldefcount="1">
      <symbol link="sa_rt_1">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRT_A2, LDRT_T1" symboldefcount="2">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>For encoding A2 and T1: is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRT_A1, LDRT_A2, LDRT_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRT_A1" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>For encoding A1: specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRT_A2" symboldefcount="2">
      <symbol link="sa__plusminus__1">+/-</symbol>
      <definition encodedin="U">
        <intro>For encoding A2: specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="LDRT_A2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRT_A2" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The shift to apply to the value read from <syntax>&lt;Rm&gt;</syntax>. If absent, no shift is applied. Otherwise, see <xref linkend="Chdibjii">Shifts applied to a register</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRT_T1" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the offset is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRT_A1" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 if omitted, and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRT_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is an optional 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 and encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/LDRT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then UNPREDICTABLE;               // Hyp mode</line>
<line>    offset = if register_form then <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C) else imm32;</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + offset) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - offset);</line>
<line>    address = if postindex then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] else offset_addr;</line>
<line>    data = <a link="impl-aarch32.MemU_unpriv.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU_unpriv[bits(32) address, integer size]">MemU_unpriv</a>[address,4];</line>
<line>    if postindex then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = data;</line>
</pstext>
    </ps>
  </ps_section>
  <constrained_unpredictables ps_block="Operation">
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>PSTATE.EL == EL2</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
      <cu_type>
        <cu_type_text>The instruction executes as <instruction>LDR</instruction> (immediate).</cu_type_text>
      </cu_type>
    </cu_case>
  </constrained_unpredictables>
</instructionsection>
</file>
<file type="instructionsection" file="lsl_mov_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LSL_MOV_r" title="LSL (immediate) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="LSL" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MOV" />
  </docvars>
  <heading>LSL (immediate)</heading>
  <desc>
    <brief>
      <para>Logical Shift Left (immediate)</para>
    </brief>
    <authored>
      <para>Logical Shift Left (immediate) shifts a register value left by an immediate number of bits, shifting in zeros, and writes the result to the destination register.</para>
    </authored>
  </desc>
  <aliasto refiform="mov_r.xml" iformid="MOV_r">MOV, MOVS (register)</aliasto>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1" settings="5" constraint="!= 00000">
          <c colspan="5">!= 00000</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LSL_MOV_r_A1" oneofinclass="1" oneof="3" label="MOV, shift or rotate by value">
        <docvars>
          <docvar key="alias_mnemonic" value="LSL" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <asmtemplate><text>LSL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_3" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_2" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_5" hover="Shift amount [0-31] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOV_r_A1">MOV</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_3" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_2" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, LSL #</text><a link="sa_imm_5" hover="Shift amount [0-31] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MOV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="28" width="2" name="op" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="26" width="5" name="imm5" usename="1" settings="5" constraint="!= 00000">
          <c colspan="5">!= 00000</c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="LSL_MOV_r_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="alias_mnemonic" value="LSL" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
        </docvars>
        <asmtemplate comment="Inside IT block"><text>LSL</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm" hover="Shift amount [1-31] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOV_r_T2">MOV</a><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, LSL #</text><a link="sa_imm" hover="Shift amount [1-31] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
          <aliascond><a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T3" oneof="3" id="iclass_t3" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LSL_MOV_r_T3" oneofinclass="1" oneof="3" label="MOV, shift or rotate by value">
        <docvars>
          <docvar key="alias_mnemonic" value="LSL" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <asmtemplate comment="Inside IT block, and &lt;Rd&gt;, &lt;Rm&gt;, &lt;imm&gt; can be represented in T2"><text>LSL</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_3" hover="Shift amount [0-31] (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a></asmtemplate>
        <asmtemplate><text>LSL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_3" hover="Shift amount [0-31] (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOV_r_T3">MOV</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, LSL #</text><a link="sa_imm_3" hover="Shift amount [0-31] (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LSL_MOV_r_A1, LSL_MOV_r_T2, LSL_MOV_r_T3" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSL_MOV_r_A1, LSL_MOV_r_T2, LSL_MOV_r_T3" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSL_MOV_r_A1" symboldefcount="1">
      <symbol link="sa_rd_3">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. Arm deprecates using the PC as the destination register, but if the PC is used, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSL_MOV_r_T2, LSL_MOV_r_T3" symboldefcount="2">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>For encoding T2 and T3: is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSL_MOV_r_A1" symboldefcount="1">
      <symbol link="sa_rm_2">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSL_MOV_r_T2, LSL_MOV_r_T3" symboldefcount="2">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>For encoding T2 and T3: is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSL_MOV_r_A1" symboldefcount="1">
      <symbol link="sa_imm_5">&lt;imm&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 0 to 31, encoded in the "imm5" field as &lt;imm&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSL_MOV_r_T2" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="T2" />
        </docvars>
        <intro>
          <para>For encoding T2: is the shift amount, in the range 1 to 31, encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSL_MOV_r_T3" symboldefcount="3">
      <symbol link="sa_imm_3">&lt;imm&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding T3: is the shift amount, in the range 0 to 31,  encoded in the "imm3:imm2" field as &lt;imm&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="lsl_mov_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LSL_MOV_rr" title="LSL (register) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="LSL" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MOV" />
  </docvars>
  <heading>LSL (register)</heading>
  <desc>
    <brief>Logical Shift Left (register)</brief>
    <longer> shifts a register value left by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register</longer>
  </desc>
  <aliasto refiform="mov_rr.xml" iformid="MOV_rr">MOV, MOVS (register-shifted register)</aliasto>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LSL_MOV_rr_A1" oneofinclass="1" oneof="3" label="Not flag setting">
        <docvars>
          <docvar key="alias_mnemonic" value="LSL" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOV" />
        </docvars>
        <asmtemplate><text>LSL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOV_rr_A1">MOV</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, LSL </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MOV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="" tworows="1">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="4" name="op" usename="1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="21" width="3" name="Rs" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rdm" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="LSL_MOV_rr_T1_LSL" oneofinclass="1" oneof="3" label="Logical shift left">
        <docvars>
          <docvar key="alias_mnemonic" value="LSL" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-lsl" />
          <docvar key="shift-type" value="lsl" />
        </docvars>
        <asmtemplate comment="Inside IT block"><text>LSL</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOV_rr_T1_LSL">MOV</a><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, LSL </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond><a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="stype" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LSL_MOV_rr_T2" oneofinclass="1" oneof="3" label="Not flag setting">
        <docvars>
          <docvar key="alias_mnemonic" value="LSL" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
        </docvars>
        <asmtemplate comment="Inside IT block, and &lt;Rd&gt;, &lt;Rm&gt;, &lt;shift&gt;, &lt;Rs&gt; can be represented in T1"><text>LSL</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <asmtemplate><text>LSL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOV_rr_T2">MOV</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, LSL </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LSL_MOV_rr_A1, LSL_MOV_rr_T1_LSL, LSL_MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSL_MOV_rr_A1, LSL_MOV_rr_T1_LSL, LSL_MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSL_MOV_rr_T1_LSL" symboldefcount="1">
      <symbol link="sa_rdm_1">&lt;Rdm&gt;</symbol>
      <account encodedin="Rdm">
        <intro>
          <para>Is the first general-purpose source register and the destination register, encoded in the "Rdm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSL_MOV_rr_A1, LSL_MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSL_MOV_rr_A1, LSL_MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSL_MOV_rr_A1, LSL_MOV_rr_T1_LSL, LSL_MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_rs_1">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the second general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="lsls_mov_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LSLS_MOV_r" title="LSLS (immediate) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="LSLS" />
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>LSLS (immediate)</heading>
  <desc>
    <brief>
      <para>Logical Shift Left, setting flags (immediate)</para>
    </brief>
    <authored>
      <para>Logical Shift Left, setting flags (immediate) shifts a register value left by an immediate number of bits, shifting in zeros, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, this instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
        <listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem>
        <listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem>
        <listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem>
      </list>
    </authored>
  </desc>
  <aliasto refiform="mov_r.xml" iformid="MOV_r">MOV, MOVS (register)</aliasto>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1" settings="5" constraint="!= 00000">
          <c colspan="5">!= 00000</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LSLS_MOVS_r_A1" oneofinclass="1" oneof="3" label="MOVS, shift or rotate by value">
        <docvars>
          <docvar key="alias_mnemonic" value="LSLS" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOVS" />
          <docvar key="mnemonic-shift-type" value="MOVS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <asmtemplate><text>LSLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_4" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_2" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_5" hover="Shift amount [0-31] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOVS_r_A1">MOVS</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_4" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_2" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, LSL #</text><a link="sa_imm_5" hover="Shift amount [0-31] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MOV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="28" width="2" name="op" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="26" width="5" name="imm5" usename="1" settings="5" constraint="!= 00000">
          <c colspan="5">!= 00000</c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="LSLS_MOV_r_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="alias_mnemonic" value="LSLS" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
        </docvars>
        <asmtemplate comment="Outside IT block"><text>LSLS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm" hover="Shift amount [1-31] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOV_r_T2">MOVS</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, LSL #</text><a link="sa_imm" hover="Shift amount [1-31] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
          <aliascond>!<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T3" oneof="3" id="iclass_t3" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LSLS_MOVS_r_T3" oneofinclass="1" oneof="3" label="MOVS, shift or rotate by value">
        <docvars>
          <docvar key="alias_mnemonic" value="LSLS" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOVS" />
          <docvar key="mnemonic-shift-type" value="MOVS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <asmtemplate comment="Outside IT block, and &lt;Rd&gt;, &lt;Rm&gt;, &lt;imm&gt; can be represented in T2"><text>LSLS.W </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_3" hover="Shift amount [0-31] (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a></asmtemplate>
        <asmtemplate><text>LSLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_3" hover="Shift amount [0-31] (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOVS_r_T3">MOVS</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, LSL #</text><a link="sa_imm_3" hover="Shift amount [0-31] (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LSLS_MOVS_r_A1, LSLS_MOVS_r_T3" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSLS_MOVS_r_A1, LSLS_MOV_r_T2, LSLS_MOVS_r_T3" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSLS_MOVS_r_A1" symboldefcount="1">
      <symbol link="sa_rd_4">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. Arm deprecates using the PC as the destination register, but if the PC is used, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSLS_MOV_r_T2, LSLS_MOVS_r_T3" symboldefcount="2">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>For encoding T2 and T3: is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSLS_MOVS_r_A1" symboldefcount="1">
      <symbol link="sa_rm_2">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSLS_MOV_r_T2, LSLS_MOVS_r_T3" symboldefcount="2">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>For encoding T2 and T3: is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSLS_MOVS_r_A1" symboldefcount="1">
      <symbol link="sa_imm_5">&lt;imm&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 0 to 31, encoded in the "imm5" field as &lt;imm&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSLS_MOV_r_T2" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="T2" />
        </docvars>
        <intro>
          <para>For encoding T2: is the shift amount, in the range 1 to 31, encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSLS_MOVS_r_T3" symboldefcount="3">
      <symbol link="sa_imm_3">&lt;imm&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding T3: is the shift amount, in the range 0 to 31,  encoded in the "imm3:imm2" field as &lt;imm&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="lsls_mov_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LSLS_MOV_rr" title="LSLS (register) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="LSLS" />
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>LSLS (register)</heading>
  <desc>
    <brief>Logical Shift Left, setting flags (register)</brief>
    <longer> shifts a register value left by a variable number of bits, shifting in zeros, writes the result to the destination register, and updates the condition flags based on the result. The variable number of bits is read from the bottom byte of a register</longer>
  </desc>
  <aliasto refiform="mov_rr.xml" iformid="MOV_rr">MOV, MOVS (register-shifted register)</aliasto>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LSLS_MOVS_rr_A1" oneofinclass="1" oneof="3" label="Flag setting">
        <docvars>
          <docvar key="alias_mnemonic" value="LSLS" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOVS" />
        </docvars>
        <asmtemplate><text>LSLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOVS_rr_A1">MOVS</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, LSL </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MOV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="" tworows="1">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="4" name="op" usename="1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="21" width="3" name="Rs" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rdm" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="LSLS_MOV_rr_T1_LSL" oneofinclass="1" oneof="3" label="Logical shift left">
        <docvars>
          <docvar key="alias_mnemonic" value="LSLS" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-lsl" />
          <docvar key="shift-type" value="lsl" />
        </docvars>
        <asmtemplate comment="Outside IT block"><text>LSLS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOV_rr_T1_LSL">MOVS</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, LSL </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond>!<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="stype" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LSLS_MOVS_rr_T2" oneofinclass="1" oneof="3" label="Flag setting">
        <docvars>
          <docvar key="alias_mnemonic" value="LSLS" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOVS" />
        </docvars>
        <asmtemplate comment="Outside IT block, and &lt;Rd&gt;, &lt;Rm&gt;, &lt;shift&gt;, &lt;Rs&gt; can be represented in T1"><text>LSLS.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <asmtemplate><text>LSLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOVS_rr_T2">MOVS</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, LSL </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LSLS_MOVS_rr_A1, LSLS_MOVS_rr_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSLS_MOVS_rr_A1, LSLS_MOV_rr_T1_LSL, LSLS_MOVS_rr_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSLS_MOV_rr_T1_LSL" symboldefcount="1">
      <symbol link="sa_rdm_1">&lt;Rdm&gt;</symbol>
      <account encodedin="Rdm">
        <intro>
          <para>Is the first general-purpose source register and the destination register, encoded in the "Rdm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSLS_MOVS_rr_A1, LSLS_MOVS_rr_T2" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSLS_MOVS_rr_A1, LSLS_MOVS_rr_T2" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSLS_MOVS_rr_A1, LSLS_MOV_rr_T1_LSL, LSLS_MOVS_rr_T2" symboldefcount="1">
      <symbol link="sa_rs_1">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the second general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="lsr_mov_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LSR_MOV_r" title="LSR (immediate) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="LSR" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MOV" />
  </docvars>
  <heading>LSR (immediate)</heading>
  <desc>
    <brief>
      <para>Logical Shift Right (immediate)</para>
    </brief>
    <authored>
      <para>Logical Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in zeros, and writes the result to the destination register.</para>
    </authored>
  </desc>
  <aliasto refiform="mov_r.xml" iformid="MOV_r">MOV, MOVS (register)</aliasto>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LSR_MOV_r_A1" oneofinclass="1" oneof="3" label="MOV, shift or rotate by value">
        <docvars>
          <docvar key="alias_mnemonic" value="LSR" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <asmtemplate><text>LSR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_3" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_2" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_1" hover="Shift amount [1-32] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOV_r_A1">MOV</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_3" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_2" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, LSR #</text><a link="sa_imm_1" hover="Shift amount [1-32] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MOV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="28" width="2" name="op" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="26" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="LSR_MOV_r_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="alias_mnemonic" value="LSR" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
        </docvars>
        <asmtemplate comment="Inside IT block"><text>LSR</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_1" hover="Shift amount [1-32] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOV_r_T2">MOV</a><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, LSR #</text><a link="sa_imm_1" hover="Shift amount [1-32] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
          <aliascond><a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T3" oneof="3" id="iclass_t3" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LSR_MOV_r_T3" oneofinclass="1" oneof="3" label="MOV, shift or rotate by value">
        <docvars>
          <docvar key="alias_mnemonic" value="LSR" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <asmtemplate comment="Inside IT block, and &lt;Rd&gt;, &lt;Rm&gt;, &lt;imm&gt; can be represented in T2"><text>LSR</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_2" hover="Shift amount [1-32] (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a></asmtemplate>
        <asmtemplate><text>LSR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_2" hover="Shift amount [1-32] (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOV_r_T3">MOV</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, LSR #</text><a link="sa_imm_2" hover="Shift amount [1-32] (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LSR_MOV_r_A1, LSR_MOV_r_T2, LSR_MOV_r_T3" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSR_MOV_r_A1, LSR_MOV_r_T2, LSR_MOV_r_T3" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSR_MOV_r_A1" symboldefcount="1">
      <symbol link="sa_rd_3">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. Arm deprecates using the PC as the destination register, but if the PC is used, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSR_MOV_r_T2, LSR_MOV_r_T3" symboldefcount="2">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>For encoding T2 and T3: is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSR_MOV_r_A1" symboldefcount="1">
      <symbol link="sa_rm_2">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSR_MOV_r_T2, LSR_MOV_r_T3" symboldefcount="2">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>For encoding T2 and T3: is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSR_MOV_r_A1, LSR_MOV_r_T2" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm5">
        <intro>
          <para>For encoding A1 and T2: is the shift amount, in the range 1 to 32, encoded in the "imm5" field as &lt;imm&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSR_MOV_r_T3" symboldefcount="2">
      <symbol link="sa_imm_2">&lt;imm&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding T3: is the shift amount, in the range 1 to 32, encoded in the "imm3:imm2" field as &lt;imm&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="lsr_mov_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LSR_MOV_rr" title="LSR (register) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="LSR" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MOV" />
  </docvars>
  <heading>LSR (register)</heading>
  <desc>
    <brief>Logical Shift Right (register)</brief>
    <longer> shifts a register value right by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register</longer>
  </desc>
  <aliasto refiform="mov_rr.xml" iformid="MOV_rr">MOV, MOVS (register-shifted register)</aliasto>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LSR_MOV_rr_A1" oneofinclass="1" oneof="3" label="Not flag setting">
        <docvars>
          <docvar key="alias_mnemonic" value="LSR" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOV" />
        </docvars>
        <asmtemplate><text>LSR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOV_rr_A1">MOV</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, LSR </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MOV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="" tworows="1">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="4" name="op" usename="1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="21" width="3" name="Rs" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rdm" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="LSR_MOV_rr_T1_LSR" oneofinclass="1" oneof="3" label="Logical shift right">
        <docvars>
          <docvar key="alias_mnemonic" value="LSR" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-lsr" />
          <docvar key="shift-type" value="lsr" />
        </docvars>
        <asmtemplate comment="Inside IT block"><text>LSR</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOV_rr_T1_LSR">MOV</a><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, LSR </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond><a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="stype" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LSR_MOV_rr_T2" oneofinclass="1" oneof="3" label="Not flag setting">
        <docvars>
          <docvar key="alias_mnemonic" value="LSR" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
        </docvars>
        <asmtemplate comment="Inside IT block, and &lt;Rd&gt;, &lt;Rm&gt;, &lt;shift&gt;, &lt;Rs&gt; can be represented in T1"><text>LSR</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <asmtemplate><text>LSR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOV_rr_T2">MOV</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, LSR </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LSR_MOV_rr_A1, LSR_MOV_rr_T1_LSR, LSR_MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSR_MOV_rr_A1, LSR_MOV_rr_T1_LSR, LSR_MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSR_MOV_rr_T1_LSR" symboldefcount="1">
      <symbol link="sa_rdm_1">&lt;Rdm&gt;</symbol>
      <account encodedin="Rdm">
        <intro>
          <para>Is the first general-purpose source register and the destination register, encoded in the "Rdm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSR_MOV_rr_A1, LSR_MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSR_MOV_rr_A1, LSR_MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSR_MOV_rr_A1, LSR_MOV_rr_T1_LSR, LSR_MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_rs_1">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the second general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="lsrs_mov_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LSRS_MOV_r" title="LSRS (immediate) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="LSRS" />
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>LSRS (immediate)</heading>
  <desc>
    <brief>
      <para>Logical Shift Right, setting flags (immediate)</para>
    </brief>
    <authored>
      <para>Logical Shift Right, setting flags (immediate) shifts a register value right by an immediate number of bits, shifting in zeros, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, this instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
        <listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem>
        <listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem>
        <listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem>
      </list>
    </authored>
  </desc>
  <aliasto refiform="mov_r.xml" iformid="MOV_r">MOV, MOVS (register)</aliasto>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LSRS_MOVS_r_A1" oneofinclass="1" oneof="3" label="MOVS, shift or rotate by value">
        <docvars>
          <docvar key="alias_mnemonic" value="LSRS" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOVS" />
          <docvar key="mnemonic-shift-type" value="MOVS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <asmtemplate><text>LSRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_4" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_2" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_1" hover="Shift amount [1-32] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOVS_r_A1">MOVS</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_4" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_2" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, LSR #</text><a link="sa_imm_1" hover="Shift amount [1-32] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MOV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="28" width="2" name="op" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="26" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="LSRS_MOV_r_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="alias_mnemonic" value="LSRS" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
        </docvars>
        <asmtemplate comment="Outside IT block"><text>LSRS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_1" hover="Shift amount [1-32] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOV_r_T2">MOVS</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, LSR #</text><a link="sa_imm_1" hover="Shift amount [1-32] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
          <aliascond>!<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T3" oneof="3" id="iclass_t3" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LSRS_MOVS_r_T3" oneofinclass="1" oneof="3" label="MOVS, shift or rotate by value">
        <docvars>
          <docvar key="alias_mnemonic" value="LSRS" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOVS" />
          <docvar key="mnemonic-shift-type" value="MOVS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <asmtemplate comment="Outside IT block, and &lt;Rd&gt;, &lt;Rm&gt;, &lt;imm&gt; can be represented in T2"><text>LSRS.W </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_2" hover="Shift amount [1-32] (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a></asmtemplate>
        <asmtemplate><text>LSRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_2" hover="Shift amount [1-32] (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOVS_r_T3">MOVS</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, LSR #</text><a link="sa_imm_2" hover="Shift amount [1-32] (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LSRS_MOVS_r_A1, LSRS_MOVS_r_T3" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSRS_MOVS_r_A1, LSRS_MOV_r_T2, LSRS_MOVS_r_T3" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSRS_MOVS_r_A1" symboldefcount="1">
      <symbol link="sa_rd_4">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. Arm deprecates using the PC as the destination register, but if the PC is used, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSRS_MOV_r_T2, LSRS_MOVS_r_T3" symboldefcount="2">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>For encoding T2 and T3: is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSRS_MOVS_r_A1" symboldefcount="1">
      <symbol link="sa_rm_2">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSRS_MOV_r_T2, LSRS_MOVS_r_T3" symboldefcount="2">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>For encoding T2 and T3: is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSRS_MOVS_r_A1, LSRS_MOV_r_T2" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm5">
        <intro>
          <para>For encoding A1 and T2: is the shift amount, in the range 1 to 32, encoded in the "imm5" field as &lt;imm&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSRS_MOVS_r_T3" symboldefcount="2">
      <symbol link="sa_imm_2">&lt;imm&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding T3: is the shift amount, in the range 1 to 32, encoded in the "imm3:imm2" field as &lt;imm&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="lsrs_mov_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="LSRS_MOV_rr" title="LSRS (register) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="LSRS" />
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>LSRS (register)</heading>
  <desc>
    <brief>Logical Shift Right, setting flags (register)</brief>
    <longer> shifts a register value right by an immediate number of bits, shifting in zeros, writes the result to the destination register, and updates the condition flags based on the result. The variable number of bits is read from the bottom byte of a register</longer>
  </desc>
  <aliasto refiform="mov_rr.xml" iformid="MOV_rr">MOV, MOVS (register-shifted register)</aliasto>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LSRS_MOVS_rr_A1" oneofinclass="1" oneof="3" label="Flag setting">
        <docvars>
          <docvar key="alias_mnemonic" value="LSRS" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOVS" />
        </docvars>
        <asmtemplate><text>LSRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOVS_rr_A1">MOVS</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, LSR </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MOV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="" tworows="1">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="4" name="op" usename="1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="21" width="3" name="Rs" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rdm" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="LSRS_MOV_rr_T1_LSR" oneofinclass="1" oneof="3" label="Logical shift right">
        <docvars>
          <docvar key="alias_mnemonic" value="LSRS" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-lsr" />
          <docvar key="shift-type" value="lsr" />
        </docvars>
        <asmtemplate comment="Outside IT block"><text>LSRS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOV_rr_T1_LSR">MOVS</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, LSR </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond>!<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="stype" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="LSRS_MOVS_rr_T2" oneofinclass="1" oneof="3" label="Flag setting">
        <docvars>
          <docvar key="alias_mnemonic" value="LSRS" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOVS" />
        </docvars>
        <asmtemplate comment="Outside IT block, and &lt;Rd&gt;, &lt;Rm&gt;, &lt;shift&gt;, &lt;Rs&gt; can be represented in T1"><text>LSRS.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <asmtemplate><text>LSRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOVS_rr_T2">MOVS</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, LSR </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LSRS_MOVS_rr_A1, LSRS_MOVS_rr_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSRS_MOVS_rr_A1, LSRS_MOV_rr_T1_LSR, LSRS_MOVS_rr_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSRS_MOV_rr_T1_LSR" symboldefcount="1">
      <symbol link="sa_rdm_1">&lt;Rdm&gt;</symbol>
      <account encodedin="Rdm">
        <intro>
          <para>Is the first general-purpose source register and the destination register, encoded in the "Rdm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSRS_MOVS_rr_A1, LSRS_MOVS_rr_T2" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSRS_MOVS_rr_A1, LSRS_MOVS_rr_T2" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LSRS_MOVS_rr_A1, LSRS_MOV_rr_T1_LSR, LSRS_MOVS_rr_T2" symboldefcount="1">
      <symbol link="sa_rs_1">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the second general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="mcr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="MCR" title="MCR -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MCR" />
  </docvars>
  <heading>MCR</heading>
  <desc>
    <brief>
      <para>Move to System register from general-purpose register or execute a System instruction</para>
    </brief>
    <authored>
      <para>Move to System register from general-purpose register or execute a System instruction. This instruction copies the value of a general-purpose register to a System register, or executes a System instruction.</para>
      <para>The System register and System instruction descriptions identify valid encodings for this instruction. Other encodings are <arm-defined-word>undefined</arm-defined-word>. For more information see <xref linkend="CFIDGFBF">About the AArch32 System register interface</xref> and <xref linkend="BABDFCJB">General behavior of System registers</xref>.</para>
      <para>In an implementation that includes EL2, <instruction>MCR</instruction> accesses to System registers can be trapped to Hyp mode, meaning that an attempt to execute an <instruction>MCR</instruction> instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception.  For more information, see <xref linkend="BEIDFAFD">EL2 configurable instruction enables, disables, and traps</xref>.</para>
      <para>Because of the range of possible traps to Hyp mode, the <instruction>MCR</instruction> pseudocode does not show these possible traps.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>The possible values of { <syntax>&lt;coproc&gt;</syntax>, <syntax>&lt;opc1&gt;</syntax>, <syntax>&lt;CRn&gt;</syntax>, <syntax>&lt;CRm&gt;</syntax>, <syntax>&lt;opc2&gt;</syntax> } encode the entire System register and System instruction encoding space. Not all of this space is allocated, and the System register and System instruction descriptions identify the allocated encodings.</para>
    </syntaxnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="MCR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/MCR/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc1" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="CRn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" name="coproc&lt;3:1&gt;" usename="1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" name="coproc&lt;0&gt;" usename="1">
          <c></c>
        </box>
        <box hibit="7" width="3" name="opc2" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="CRm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MCR_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MCR" />
        </docvars>
        <asmtemplate><text>MCR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_coproc" hover="System register encoding space (field &quot;coproc&lt;0&gt;&quot;) [p14,p15]">&lt;coproc&gt;</a><text>, </text><a>{#}</a><a link="sa_opc1" hover="Opc1 parameter within the System register encoding space, in the range 0 to7 (field &quot;opc1&quot;)">&lt;opc1&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_crn" hover="CRn parameter within the System register encoding space [c0-c15] (field &quot;CRn&quot;)">&lt;CRn&gt;</a><text>, </text><a link="sa_crm" hover="CRm parameter within the System register encoding space [c0-c15] (field &quot;CRm&quot;)">&lt;CRm&gt;</a><text>{</text><text>, </text><a>{#}</a><a link="sa_opc2" hover="Opc2 parameter within the System register encoding space, in the range 0 to7 (field &quot;opc2&quot;)">&lt;opc2&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MCR/T1A1_A.txt" mylink="aarch32.instrs.MCR.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  cp = if coproc&lt;0&gt; == '0' then 14 else 15;</line>
<line>if t == 15  then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MCR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/MCR/T1A1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc1" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="CRn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" name="coproc&lt;3:1&gt;" usename="1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" name="coproc&lt;0&gt;" usename="1">
          <c></c>
        </box>
        <box hibit="7" width="3" name="opc2" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="CRm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MCR_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MCR" />
        </docvars>
        <asmtemplate><text>MCR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_coproc" hover="System register encoding space (field &quot;coproc&lt;0&gt;&quot;) [p14,p15]">&lt;coproc&gt;</a><text>, </text><a>{#}</a><a link="sa_opc1" hover="Opc1 parameter within the System register encoding space, in the range 0 to7 (field &quot;opc1&quot;)">&lt;opc1&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_crn" hover="CRn parameter within the System register encoding space [c0-c15] (field &quot;CRn&quot;)">&lt;CRn&gt;</a><text>, </text><a link="sa_crm" hover="CRm parameter within the System register encoding space [c0-c15] (field &quot;CRm&quot;)">&lt;CRm&gt;</a><text>{</text><text>, </text><a>{#}</a><a link="sa_opc2" hover="Opc2 parameter within the System register encoding space, in the range 0 to7 (field &quot;opc2&quot;)">&lt;opc2&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MCR/T1A1_A.txt" mylink="aarch32.instrs.MCR.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  cp = if coproc&lt;0&gt; == '0' then 14 else 15;</line>
<line>if t == 15  then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MCR_A1, MCR_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MCR_A1, MCR_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MCR_A1, MCR_T1" symboldefcount="1">
      <symbol link="sa_coproc">&lt;coproc&gt;</symbol>
      <definition encodedin="coproc&lt;0&gt;">
        <intro>Is the System register encoding space, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">coproc&lt;0&gt;</entry>
                <entry class="symbol">&lt;coproc&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">p14</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">p15</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="MCR_A1, MCR_T1" symboldefcount="1">
      <symbol link="sa_opc1">&lt;opc1&gt;</symbol>
      <account encodedin="opc1">
        <intro>
          <para>Is the opc1 parameter within the System register encoding space, in the range 0 to7, encoded in the "opc1" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MCR_A1, MCR_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MCR_A1, MCR_T1" symboldefcount="1">
      <symbol link="sa_crn">&lt;CRn&gt;</symbol>
      <account encodedin="CRn">
        <intro>
          <para>Is the CRn parameter within the System register encoding space, in the range c0 to c15, encoded in the "CRn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MCR_A1, MCR_T1" symboldefcount="1">
      <symbol link="sa_crm">&lt;CRm&gt;</symbol>
      <account encodedin="CRm">
        <intro>
          <para>Is the CRm parameter within the System register encoding space, in the range c0 to c15, encoded in the "CRm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MCR_A1, MCR_T1" symboldefcount="1">
      <symbol link="sa_opc2">&lt;opc2&gt;</symbol>
      <account encodedin="opc2">
        <intro>
          <para>Is the opc2 parameter within the System register encoding space, in the range 0 to7, encoded in the "opc2" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MCR/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="AArch32.SysRegWrite.3" file="shared_pseudocode.xml" hover="function: AArch32.SysRegWrite(integer cp_num, bits(32) instr, integer t)">AArch32.SysRegWrite</a>(cp, <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>(), t);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="mcrr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="MCRR" title="MCRR -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MCRR" />
  </docvars>
  <heading>MCRR</heading>
  <desc>
    <brief>
      <para>Move to System register from two general-purpose registers</para>
    </brief>
    <authored>
      <para>Move to System register from two general-purpose registers. This instruction copies the values of two general-purpose registers to a System register.</para>
      <para>The System register descriptions identify valid encodings for this instruction. Other encodings are <arm-defined-word>undefined</arm-defined-word>. For more information see <xref linkend="CFIDGFBF">About the AArch32 System register interface</xref> and <xref linkend="BABDFCJB">General behavior of System registers</xref>.</para>
      <para>In an implementation that includes EL2, <instruction>MCRR</instruction> accesses to System registers can be trapped to Hyp mode, meaning that an attempt to execute an <instruction>MCRR</instruction> instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception.  For more information, see <xref linkend="BEIDFAFD">EL2 configurable instruction enables, disables, and traps</xref>.</para>
      <para>Because of the range of possible traps to Hyp mode, the <instruction>MCRR</instruction> pseudocode does not show these possible traps.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>The possible values of { <syntax>&lt;coproc&gt;</syntax>, <syntax>&lt;opc1&gt;</syntax>, <syntax>&lt;CRm&gt;</syntax> } encode the entire System register encoding space. Not all of this space is allocated, and the System register descriptions identify the allocated encodings.</para>
      <para>For the permitted uses of these instructions, as described in this manual, <syntax>&lt;Rt2&gt;</syntax> transfers bits[63:32] of the selected System register, while <syntax>&lt;Rt&gt;</syntax> transfers bits[31:0].</para>
    </syntaxnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="MCRR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/MCRR/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rt2" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" name="coproc&lt;3:1&gt;" usename="1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" name="coproc&lt;0&gt;" usename="1">
          <c></c>
        </box>
        <box hibit="7" width="4" name="opc1" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="CRm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MCRR_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MCRR" />
        </docvars>
        <asmtemplate><text>MCRR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_coproc" hover="System register encoding space (field &quot;coproc&lt;0&gt;&quot;) [p14,p15]">&lt;coproc&gt;</a><text>, </text><a>{#}</a><a link="sa_opc1" hover="Opc1 parameter within the System register encoding space [0-15] (field &quot;opc1&quot;)">&lt;opc1&gt;</a><text>, </text><a link="sa_rt" hover="First general-purpose register that is transferred into (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register that is transferred into (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a><text>, </text><a link="sa_crm" hover="CRm parameter within the System register encoding space [c0-c15] (field &quot;CRm&quot;)">&lt;CRm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MCRR/T1A1_A.txt" mylink="aarch32.instrs.MCRR.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2);  cp = if coproc&lt;0&gt; == '0' then 14 else 15;</line>
<line>if t == 15 || t2 == 15 then UNPREDICTABLE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MCRR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/MCRR/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rt2" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" name="coproc&lt;3:1&gt;" usename="1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" name="coproc&lt;0&gt;" usename="1">
          <c></c>
        </box>
        <box hibit="7" width="4" name="opc1" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="CRm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MCRR_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MCRR" />
        </docvars>
        <asmtemplate><text>MCRR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_coproc" hover="System register encoding space (field &quot;coproc&lt;0&gt;&quot;) [p14,p15]">&lt;coproc&gt;</a><text>, </text><a>{#}</a><a link="sa_opc1" hover="Opc1 parameter within the System register encoding space [0-15] (field &quot;opc1&quot;)">&lt;opc1&gt;</a><text>, </text><a link="sa_rt" hover="First general-purpose register that is transferred into (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register that is transferred into (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a><text>, </text><a link="sa_crm" hover="CRm parameter within the System register encoding space [c0-c15] (field &quot;CRm&quot;)">&lt;CRm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MCRR/T1A1_A.txt" mylink="aarch32.instrs.MCRR.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2);  cp = if coproc&lt;0&gt; == '0' then 14 else 15;</line>
<line>if t == 15 || t2 == 15 then UNPREDICTABLE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MCRR_A1, MCRR_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MCRR_A1, MCRR_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MCRR_A1, MCRR_T1" symboldefcount="1">
      <symbol link="sa_coproc">&lt;coproc&gt;</symbol>
      <definition encodedin="coproc&lt;0&gt;">
        <intro>Is the System register encoding space, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">coproc&lt;0&gt;</entry>
                <entry class="symbol">&lt;coproc&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">p14</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">p15</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="MCRR_A1, MCRR_T1" symboldefcount="1">
      <symbol link="sa_opc1">&lt;opc1&gt;</symbol>
      <account encodedin="opc1">
        <intro>
          <para>Is the opc1 parameter within the System register encoding space, in the range 0 to 15, encoded in the "opc1" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MCRR_A1, MCRR_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the first general-purpose register that is transferred into, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MCRR_A1, MCRR_T1" symboldefcount="1">
      <symbol link="sa_rt2">&lt;Rt2&gt;</symbol>
      <account encodedin="Rt2">
        <intro>
          <para>Is the second general-purpose register that is transferred into, encoded in the "Rt2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MCRR_A1, MCRR_T1" symboldefcount="1">
      <symbol link="sa_crm">&lt;CRm&gt;</symbol>
      <account encodedin="CRm">
        <intro>
          <para>Is the CRm parameter within the System register encoding space, in the range c0 to c15, encoded in the "CRm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MCRR/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="AArch32.SysRegWrite64.4" file="shared_pseudocode.xml" hover="function: AArch32.SysRegWrite64(integer cp_num, bits(32) instr, integer t, integer t2)">AArch32.SysRegWrite64</a>(cp, <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>(), t, t2);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="mla.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="MLA" title="MLA, MLAS -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>MLA, MLAS</heading>
  <desc>
    <brief>
      <para>Multiply Accumulate</para>
    </brief>
    <authored>
      <para>Multiply Accumulate multiplies two register values, and adds a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values.</para>
      <para>In an A32 instruction, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many implementations.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/MLA/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MLAS_A1" oneofinclass="2" oneof="3" label="Flag setting" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MLAS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>MLAS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <encoding name="MLA_A1" oneofinclass="2" oneof="3" label="Not flag setting" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MLA" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>MLA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MLA/A1_A.txt" mylink="aarch32.instrs.MLA.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);  setflags = (S == '1');</line>
<line>if d == 15 || n == 15 || m == 15 || a == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MLA" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/MLA/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MLA_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MLA" />
        </docvars>
        <asmtemplate><text>MLA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MLA/T1_A.txt" mylink="aarch32.instrs.MLA.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Ra == '1111' then SEE "MUL";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);  setflags = FALSE;</line>
<line>if d == 15 || n == 15 || m  == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MLA_A1, MLA_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MLA_A1, MLA_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MLA_A1, MLA_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MLA_A1, MLA_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MLA_A1, MLA_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register holding the multiplier, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MLA_A1, MLA_T1" symboldefcount="1">
      <symbol link="sa_ra">&lt;Ra&gt;</symbol>
      <account encodedin="Ra">
        <intro>
          <para>Is the third general-purpose source register holding the addend, encoded in the "Ra" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MLA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    operand1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]);  // operand1 = UInt(R[n]) produces the same final results</line>
<line>    operand2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]);  // operand2 = UInt(R[m]) produces the same final results</line>
<line>    addend   = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[a]);  // addend   = UInt(R[a]) produces the same final results</line>
<line>    result = operand1 * operand2 + addend;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result&lt;31:0&gt;;</line>
<line>    if setflags then</line>
<line>        PSTATE.N = result&lt;31&gt;;</line>
<line>        PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result&lt;31:0&gt;);</line>
<line>        // PSTATE.C, PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="mls.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="MLS" title="MLS -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MLS" />
  </docvars>
  <heading>MLS</heading>
  <desc>
    <brief>
      <para>Multiply and Subtract</para>
    </brief>
    <authored>
      <para>Multiply and Subtract multiplies two register values, and subtracts the product from a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="MLS" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/MLS/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MLS_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MLS" />
        </docvars>
        <asmtemplate><text>MLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding minuend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MLS/A1_A.txt" mylink="aarch32.instrs.MLS.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);</line>
<line>if d == 15 || n == 15 || m == 15 || a == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MLS" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/MLS/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="op2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MLS_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MLS" />
        </docvars>
        <asmtemplate><text>MLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding minuend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MLS/T1_A.txt" mylink="aarch32.instrs.MLS.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);</line>
<line>if d == 15 || n == 15 || m == 15 || a == 15 then UNPREDICTABLE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MLS_A1, MLS_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MLS_A1, MLS_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MLS_A1, MLS_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MLS_A1, MLS_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MLS_A1, MLS_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register holding the multiplier, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MLS_A1, MLS_T1" symboldefcount="1">
      <symbol link="sa_ra">&lt;Ra&gt;</symbol>
      <account encodedin="Ra">
        <intro>
          <para>Is the third general-purpose source register holding the minuend, encoded in the "Ra" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MLS/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    operand1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]);  // operand1 = UInt(R[n]) produces the same final results</line>
<line>    operand2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]);  // operand2 = UInt(R[m]) produces the same final results</line>
<line>    addend   = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[a]);  // addend   = UInt(R[a]) produces the same final results</line>
<line>    result = addend - operand1 * operand2;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result&lt;31:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="mov_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="MOV_i" title="MOV, MOVS (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>MOV, MOVS (immediate)</heading>
  <desc>
    <brief>
      <para>Move (immediate)</para>
    </brief>
    <authored>
      <para>Move (immediate) writes an immediate value to the destination register.</para>
      <para>If the destination register is not the PC, the MOVS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The MOV variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The MOVS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="5">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="5" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/MOV_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="MOV_i_A1" oneofinclass="2" oneof="7" label="MOV" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOV" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>MOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="MOVS_i_A1" oneofinclass="2" oneof="7" label="MOVS" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOVS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>MOVS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MOV_i/A1_A.txt" mylink="aarch32.instrs.MOV_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  setflags = (S == '1');  (imm32, carry) = <a link="impl-aarch32.A32ExpandImm_C.2" file="shared_pseudocode.xml" hover="function: (bits(32), bit) A32ExpandImm_C(bits(12) imm12, bit carry_in)">A32ExpandImm_C</a>(imm12, PSTATE.C);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="5" id="iclass_a2" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="MOVW" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/MOV_i/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="MOV_i_A2" oneofinclass="1" oneof="7" label="A2">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOVW" />
        </docvars>
        <asmtemplate comment="&lt;imm16&gt; can not be represented in A1"><text>MOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_imm16_1" hover="16-bit unsigned immediate [0-65535] (field &quot;imm4:imm12&quot;)">&lt;imm16&gt;</a></asmtemplate>
        <asmtemplate comment="&lt;imm16&gt; can be represented in A1"><text>MOVW</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_imm16_1" hover="16-bit unsigned immediate [0-65535] (field &quot;imm4:imm12&quot;)">&lt;imm16&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MOV_i/A2_A.txt" mylink="aarch32.instrs.MOV_i.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  setflags = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm4:imm12, 32);</line>
<line>if d == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="5" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MOV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/MOV_i/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="28" width="2" name="op" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="26" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="23" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="MOV_i_T1" oneofinclass="1" oneof="7" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
        </docvars>
        <asmtemplate comment="Inside IT block"><text>MOV</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_imm8" hover="8-bit unsigned immediate [0-255] (field &quot;imm8&quot;)">&lt;imm8&gt;</a></asmtemplate>
        <asmtemplate comment="Outside IT block"><text>MOVS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_imm8" hover="8-bit unsigned immediate [0-255] (field &quot;imm8&quot;)">&lt;imm8&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MOV_i/T1_A.txt" mylink="aarch32.instrs.MOV_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  setflags = !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>();  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);  carry = PSTATE.C;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="5" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/MOV_i/T2_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="MOV_i_T2" oneofinclass="2" oneof="7" label="MOV" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate comment="Inside IT block, and &lt;Rd&gt;, &lt;const&gt; can be represented in T1"><text>MOV</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
        <asmtemplate><text>MOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="MOVS_i_T2" oneofinclass="2" oneof="7" label="MOVS" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOVS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate comment="Outside IT block, and &lt;Rd&gt;, &lt;const&gt; can be represented in T1"><text>MOVS.W </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
        <asmtemplate><text>MOVS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MOV_i/T2_A.txt" mylink="aarch32.instrs.MOV_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  setflags = (S == '1');  (imm32, carry) = <a link="impl-aarch32.T32ExpandImm_C.2" file="shared_pseudocode.xml" hover="function: (bits(32), bit) T32ExpandImm_C(bits(12) imm12, bit carry_in)">T32ExpandImm_C</a>(i:imm3:imm8, PSTATE.C);</line>
<line>if d == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T3" oneof="5" id="iclass_t3" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MOVW" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/MOV_i/T3_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="MOV_i_T3" oneofinclass="1" oneof="7" label="T3">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOVW" />
        </docvars>
        <asmtemplate comment="&lt;imm16&gt; cannot be represented in T1 or T2"><text>MOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_imm16" hover="16-bit unsigned immediate [0-65535] (field &quot;imm4:i:imm3:imm8&quot;)">&lt;imm16&gt;</a></asmtemplate>
        <asmtemplate comment="&lt;imm16&gt; can be represented in T1 or T2"><text>MOVW</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_imm16" hover="16-bit unsigned immediate [0-65535] (field &quot;imm4:i:imm3:imm8&quot;)">&lt;imm16&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MOV_i/T3_A.txt" mylink="aarch32.instrs.MOV_i.T3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  setflags = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm4:i:imm3:imm8, 32);</line>
<line>if d == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MOV_i_A1, MOV_i_A2, MOV_i_T1, MOV_i_T2, MOV_i_T3" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_i_A1, MOV_i_A2, MOV_i_T1, MOV_i_T2, MOV_i_T3" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_i_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOV" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the MOV variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the MOVS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_i_A2, MOV_i_T1, MOV_i_T2, MOV_i_T3" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>For encoding A2, T1, T2 and T3: is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_i_T1" symboldefcount="1">
      <symbol link="sa_imm8">&lt;imm8&gt;</symbol>
      <account encodedin="imm8">
        <intro>
          <para>Is a 8-bit unsigned immediate, in the range 0 to 255, encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_i_A2" symboldefcount="1">
      <symbol link="sa_imm16_1">&lt;imm16&gt;</symbol>
      <account encodedin="imm4:imm12">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A2: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm4:imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_i_T3" symboldefcount="2">
      <symbol link="sa_imm16">&lt;imm16&gt;</symbol>
      <account encodedin="imm4:i:imm3:imm8">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm4:i:imm3:imm8" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_i_A1" symboldefcount="1">
      <symbol link="sa_const_1">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: an immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_i_T2" symboldefcount="2">
      <symbol link="sa_const">&lt;const&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: an immediate value. See <xref linkend="BABGHAGA">Modified immediate constants in T32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MOV_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    result = imm32;</line>
<line>    if d == 15 then          // Can only occur for encoding A1</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.N = result&lt;31&gt;;</line>
<line>            PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>            PSTATE.C = carry;</line>
<line>            // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="mov_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="MOV_r" title="MOV, MOVS (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>MOV, MOVS (register)</heading>
  <desc>
    <brief>
      <para>Move (register)</para>
    </brief>
    <authored>
      <para>Move (register) copies a value from a register to the destination register.</para>
      <para>If the destination register is not the PC, the MOVS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. If the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The MOV variant of the instruction is a branch. In the T32 instruction set (encoding T1) this is a simple branch, and in the A32 instruction set it is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The MOVS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="10">
    <alias_list_intro>This instruction is used by the aliases </alias_list_intro>
    <aliasref aliaspageid="ASRS_MOV_r" aliasfile="asrs_mov_r.xml" hover="Arithmetic Shift Right" punct=", ">
      <text>ASRS (immediate)</text>
      <aliaspref labels="T3 (MOVS, shift or rotate by value), A1 (MOVS, shift or rotate by value)">S == '1' &amp;&amp; stype == '10'</aliaspref>
      <aliaspref labels="T2">op == '10' &amp;&amp; !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliaspref>
    </aliasref>
    <aliasref aliaspageid="ASR_MOV_r" aliasfile="asr_mov_r.xml" hover="Arithmetic Shift Right (immediate)" punct=", ">
      <text>ASR (immediate)</text>
      <aliaspref labels="T3 (MOV, shift or rotate by value), A1 (MOV, shift or rotate by value)">S == '0' &amp;&amp; stype == '10'</aliaspref>
      <aliaspref labels="T2">op == '10' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliaspref>
    </aliasref>
    <aliasref aliaspageid="LSLS_MOV_r" aliasfile="lsls_mov_r.xml" hover="Logical Shift Left" punct=", ">
      <text>LSLS (immediate)</text>
      <aliaspref labels="T3 (MOVS, shift or rotate by value)">S == '1' &amp;&amp; imm3:Rd:imm2 != '000xxxx00' &amp;&amp; stype == '00'</aliaspref>
      <aliaspref labels="A1 (MOVS, shift or rotate by value)">S == '1' &amp;&amp; imm5 != '00000' &amp;&amp; stype == '00'</aliaspref>
      <aliaspref labels="T2">op == '00' &amp;&amp; imm5 != '00000' &amp;&amp; !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliaspref>
    </aliasref>
    <aliasref aliaspageid="LSL_MOV_r" aliasfile="lsl_mov_r.xml" hover="Logical Shift Left (immediate)" punct=", ">
      <text>LSL (immediate)</text>
      <aliaspref labels="T3 (MOV, shift or rotate by value)">S == '0' &amp;&amp; imm3:Rd:imm2 != '000xxxx00' &amp;&amp; stype == '00'</aliaspref>
      <aliaspref labels="A1 (MOV, shift or rotate by value)">S == '0' &amp;&amp; imm5 != '00000' &amp;&amp; stype == '00'</aliaspref>
      <aliaspref labels="T2">op == '00' &amp;&amp; imm5 != '00000' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliaspref>
    </aliasref>
    <aliasref aliaspageid="LSRS_MOV_r" aliasfile="lsrs_mov_r.xml" hover="Logical Shift Right" punct=", ">
      <text>LSRS (immediate)</text>
      <aliaspref labels="T3 (MOVS, shift or rotate by value), A1 (MOVS, shift or rotate by value)">S == '1' &amp;&amp; stype == '01'</aliaspref>
      <aliaspref labels="T2">op == '01' &amp;&amp; !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliaspref>
    </aliasref>
    <aliasref aliaspageid="LSR_MOV_r" aliasfile="lsr_mov_r.xml" hover="Logical Shift Right (immediate)" punct=", ">
      <text>LSR (immediate)</text>
      <aliaspref labels="T3 (MOV, shift or rotate by value), A1 (MOV, shift or rotate by value)">S == '0' &amp;&amp; stype == '01'</aliaspref>
      <aliaspref labels="T2">op == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliaspref>
    </aliasref>
    <aliasref aliaspageid="RORS_MOV_r" aliasfile="rors_mov_r.xml" hover="Rotate Right" punct=", ">
      <text>RORS (immediate)</text>
      <aliaspref labels="T3 (MOVS, shift or rotate by value)">S == '1' &amp;&amp; imm3:Rd:imm2 != '000xxxx00' &amp;&amp; stype == '11'</aliaspref>
      <aliaspref labels="A1 (MOVS, shift or rotate by value)">S == '1' &amp;&amp; imm5 != '00000' &amp;&amp; stype == '11'</aliaspref>
    </aliasref>
    <aliasref aliaspageid="ROR_MOV_r" aliasfile="ror_mov_r.xml" hover="Rotate Right (immediate)" punct=", ">
      <text>ROR (immediate)</text>
      <aliaspref labels="T3 (MOV, shift or rotate by value)">S == '0' &amp;&amp; imm3:Rd:imm2 != '000xxxx00' &amp;&amp; stype == '11'</aliaspref>
      <aliaspref labels="A1 (MOV, shift or rotate by value)">S == '0' &amp;&amp; imm5 != '00000' &amp;&amp; stype == '11'</aliaspref>
    </aliasref>
    <aliasref aliaspageid="RRXS_MOV_r" aliasfile="rrxs_mov_r.xml" hover="Rotate Right with Extend" punct=" and ">
      <text>RRXS</text>
      <aliaspref labels="T3 (MOVS, rotate right with extend)">S == '1' &amp;&amp; imm3 == '000' &amp;&amp; imm2 == '00' &amp;&amp; stype == '11'</aliaspref>
      <aliaspref labels="A1 (MOVS, rotate right with extend)">S == '1' &amp;&amp; imm5 == '00000' &amp;&amp; stype == '11'</aliaspref>
    </aliasref>
    <aliasref aliaspageid="RRX_MOV_r" aliasfile="rrx_mov_r.xml" hover="Rotate Right with Extend" punct=".">
      <text>RRX</text>
      <aliaspref labels="T3 (MOV, rotate right with extend)">S == '0' &amp;&amp; imm3 == '000' &amp;&amp; imm2 == '00' &amp;&amp; stype == '11'</aliaspref>
      <aliaspref labels="A1 (MOV, rotate right with extend)">S == '0' &amp;&amp; imm5 == '00000' &amp;&amp; stype == '11'</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink />
      <text> below for details of when each alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/MOV_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MOV_r_A1_RRX" oneofinclass="4" oneof="10" label="MOV, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>MOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_2" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="MOV_r_A1" oneofinclass="4" oneof="10" label="MOV, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>MOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_2" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift_1" hover="Type of shift applied to source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_2" hover="Shift amount [0-31 (when &lt;shift&gt; = LSL)] (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="MOVS_r_A1_RRX" oneofinclass="4" oneof="10" label="MOVS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOVS" />
          <docvar key="mnemonic-shift-type" value="MOVS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>MOVS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_2" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="MOVS_r_A1" oneofinclass="4" oneof="10" label="MOVS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOVS" />
          <docvar key="mnemonic-shift-type" value="MOVS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>MOVS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_2" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift_1" hover="Type of shift applied to source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_2" hover="Shift amount [0-31 (when &lt;shift&gt; = LSL)] (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MOV_r/A1_A.txt" mylink="aarch32.instrs.MOV_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MOV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/MOV_r/T1_A.txt">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="25" width="2" name="op" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="22" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="18" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="MOV_r_T1" oneofinclass="1" oneof="10" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
        </docvars>
        <asmtemplate><text>MOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;D:Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MOV_r/T1_A.txt" mylink="aarch32.instrs.MOV_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = FALSE;</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
<line>if d == 15 &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MOV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/MOV_r/T2_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="28" width="2" name="op" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="26" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="MOV_r_T2" oneofinclass="1" oneof="10" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
        </docvars>
        <asmtemplate comment="Inside IT block"><text>MOV</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to source register (field &quot;op&quot;) [ASR,LSL,LSR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
        <asmtemplate comment="Outside IT block"><text>MOVS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to source register (field &quot;op&quot;) [ASR,LSL,LSR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MOV_r/T2_A.txt" mylink="aarch32.instrs.MOV_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>();</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(op, imm5);</line>
<line>if op == '00' &amp;&amp; imm5 == '00000' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>op == '00' &amp;&amp; imm5 == '00000' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passed its condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as <instruction>NOP</instruction>, as if it failed its condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as <instruction>MOV</instruction> Rd, Rm.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T3" oneof="4" id="iclass_t3" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/MOV_r/T3_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MOV_r_T3_RRX" oneofinclass="4" oneof="10" label="MOV, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>MOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="MOV_r_T3" oneofinclass="4" oneof="10" label="MOV, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="&lt;Rd&gt;, &lt;Rm&gt; can be represented in T1"><text>MOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> {, LSL #0}</text></asmtemplate>
        <asmtemplate comment="Inside IT block, and &lt;Rd&gt;, &lt;Rm&gt;, &lt;shift&gt;, &lt;amount&gt; can be represented in T2"><text>MOV</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift_1" hover="Type of shift applied to source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [0-31 (when &lt;shift&gt; = LSL) or 1 to 31 (when &lt;shift&gt; = ROR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
        <asmtemplate><text>MOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift_1" hover="Type of shift applied to source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [0-31 (when &lt;shift&gt; = LSL) or 1 to 31 (when &lt;shift&gt; = ROR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="MOVS_r_T3_RRX" oneofinclass="4" oneof="10" label="MOVS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOVS" />
          <docvar key="mnemonic-shift-type" value="MOVS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>MOVS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="MOVS_r_T3" oneofinclass="4" oneof="10" label="MOVS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOVS" />
          <docvar key="mnemonic-shift-type" value="MOVS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Outside IT block, and &lt;Rd&gt;, &lt;Rm&gt;, &lt;shift&gt;, &lt;amount&gt; can be represented in T1 or T2"><text>MOVS.W </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift_1" hover="Type of shift applied to source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [0-31 (when &lt;shift&gt; = LSL) or 1 to 31 (when &lt;shift&gt; = ROR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
        <asmtemplate><text>MOVS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift_1" hover="Type of shift applied to source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [0-31 (when &lt;shift&gt; = LSL) or 1 to 31 (when &lt;shift&gt; = ROR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MOV_r/T3_A.txt" mylink="aarch32.instrs.MOV_r.T3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm3:imm2);</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MOV_r_A1, MOV_r_T1, MOV_r_T2, MOV_r_T3" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_r_A1, MOV_r_T1, MOV_r_T2, MOV_r_T3" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_r_A1" symboldefcount="1">
      <symbol link="sa_rd_2">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="MOV-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the MOV variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>. Arm deprecates use of the instruction if <syntax>&lt;Rn&gt;</syntax> is the PC.</content></listitem>
            <listitem><content>For the MOVS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;. Arm deprecates use of the instruction if &lt;Rn&gt; is not the LR, or if the optional shift or <value>RRX</value> argument is specified.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_r_T1" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="D:Rd">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose destination register, encoded in the "D:Rd" field. If the PC is used:</para>
          <list type="unordered">
            <listitem><content>The instruction causes a branch to the address moved to the PC. This is a simple branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>The instruction must either be outside an IT block or the last instruction of an IT block.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_r_T2, MOV_r_T3" symboldefcount="3">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2 and T3: is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_r_A1, MOV_r_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>For encoding A1 and T1: is the general-purpose source register, encoded in the "Rm" field. The PC can be used. Arm deprecates use of the instruction if <syntax>&lt;Rd&gt;</syntax> is the PC.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_r_T2, MOV_r_T3" symboldefcount="2">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2 and T3: is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_r_A1, MOV_r_T3" symboldefcount="1">
      <symbol link="sa_shift_1">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>For encoding A1 and T3: is the type of shift to be applied to the source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="MOV_r_T2" symboldefcount="2">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="op">
        <intro>For encoding T2: is the type of shift to be applied to the source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">op</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="MOV_r_A1" symboldefcount="1">
      <symbol link="sa_amount_2">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="MOV-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 0 to 31 (when &lt;shift&gt; = LSL), or 1 to 31 (when &lt;shift&gt; = ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_r_T2" symboldefcount="2">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_r_T3" symboldefcount="3">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic-shift-type" value="MOV-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding T3: is the shift amount, in the range 0 to 31 (when &lt;shift&gt; = LSL) or 1 to 31 (when &lt;shift&gt; = ROR), or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm3:imm2" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MOV_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    (shifted, carry) = <a link="impl-aarch32.Shift_C.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift_C</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    result = shifted;</line>
<line>    if d == 15 then</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.N = result&lt;31&gt;;</line>
<line>            PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>            PSTATE.C = carry;</line>
<line>            // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="mov_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="MOV_rr" title="MOV, MOVS (register-shifted register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>MOV, MOVS (register-shifted register)</heading>
  <desc>
    <brief>
      <para>Move (register-shifted register)</para>
    </brief>
    <authored>
      <para>Move (register-shifted register) copies a register-shifted register value to the destination register. It can optionally update the condition flags based on the value.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: In encoding T1, for an <field>op</field> field value that is not described above, see <xref linkend="T32.encoding_index.dpint16_2l">Data-processing (two low registers)</xref>.</para>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="8">
    <alias_list_intro>This instruction is used by the aliases </alias_list_intro>
    <aliasref aliaspageid="ASRS_MOV_rr" aliasfile="asrs_mov_rr.xml" hover="Arithmetic Shift Right" punct=", ">
      <text>ASRS (register)</text>
      <aliaspref labels="A1 (flag setting)">S == '1' &amp;&amp; stype == '10'</aliaspref>
      <aliaspref labels="T1 (arithmetic shift right)">op == '0100' &amp;&amp; !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliaspref>
      <aliaspref labels="T2 (flag setting)">stype == '10' &amp;&amp; S == '1'</aliaspref>
    </aliasref>
    <aliasref aliaspageid="ASR_MOV_rr" aliasfile="asr_mov_rr.xml" hover="Arithmetic Shift Right (register)" punct=", ">
      <text>ASR (register)</text>
      <aliaspref labels="A1 (not flag setting)">S == '0' &amp;&amp; stype == '10'</aliaspref>
      <aliaspref labels="T1 (arithmetic shift right)">op == '0100' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliaspref>
      <aliaspref labels="T2 (not flag setting)">stype == '10' &amp;&amp; S == '0'</aliaspref>
    </aliasref>
    <aliasref aliaspageid="LSLS_MOV_rr" aliasfile="lsls_mov_rr.xml" hover="Logical Shift Left" punct=", ">
      <text>LSLS (register)</text>
      <aliaspref labels="A1 (flag setting)">S == '1' &amp;&amp; stype == '00'</aliaspref>
      <aliaspref labels="T1 (logical shift left)">op == '0010' &amp;&amp; !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliaspref>
      <aliaspref labels="T2 (flag setting)">stype == '00' &amp;&amp; S == '1'</aliaspref>
    </aliasref>
    <aliasref aliaspageid="LSL_MOV_rr" aliasfile="lsl_mov_rr.xml" hover="Logical Shift Left (register)" punct=", ">
      <text>LSL (register)</text>
      <aliaspref labels="A1 (not flag setting)">S == '0' &amp;&amp; stype == '00'</aliaspref>
      <aliaspref labels="T1 (logical shift left)">op == '0010' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliaspref>
      <aliaspref labels="T2 (not flag setting)">stype == '00' &amp;&amp; S == '0'</aliaspref>
    </aliasref>
    <aliasref aliaspageid="LSRS_MOV_rr" aliasfile="lsrs_mov_rr.xml" hover="Logical Shift Right" punct=", ">
      <text>LSRS (register)</text>
      <aliaspref labels="A1 (flag setting)">S == '1' &amp;&amp; stype == '01'</aliaspref>
      <aliaspref labels="T1 (logical shift right)">op == '0011' &amp;&amp; !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliaspref>
      <aliaspref labels="T2 (flag setting)">stype == '01' &amp;&amp; S == '1'</aliaspref>
    </aliasref>
    <aliasref aliaspageid="LSR_MOV_rr" aliasfile="lsr_mov_rr.xml" hover="Logical Shift Right (register)" punct=", ">
      <text>LSR (register)</text>
      <aliaspref labels="A1 (not flag setting)">S == '0' &amp;&amp; stype == '01'</aliaspref>
      <aliaspref labels="T1 (logical shift right)">op == '0011' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliaspref>
      <aliaspref labels="T2 (not flag setting)">stype == '01' &amp;&amp; S == '0'</aliaspref>
    </aliasref>
    <aliasref aliaspageid="RORS_MOV_rr" aliasfile="rors_mov_rr.xml" hover="Rotate Right" punct=" and ">
      <text>RORS (register)</text>
      <aliaspref labels="A1 (flag setting)">S == '1' &amp;&amp; stype == '11'</aliaspref>
      <aliaspref labels="T1 (rotate right)">op == '0111' &amp;&amp; !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliaspref>
      <aliaspref labels="T2 (flag setting)">stype == '11' &amp;&amp; S == '1'</aliaspref>
    </aliasref>
    <aliasref aliaspageid="ROR_MOV_rr" aliasfile="ror_mov_rr.xml" hover="Rotate Right (register)" punct=".">
      <text>ROR (register)</text>
      <aliaspref labels="A1 (not flag setting)">S == '0' &amp;&amp; stype == '11'</aliaspref>
      <aliaspref labels="T1 (rotate right)">op == '0111' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliaspref>
      <aliaspref labels="T2 (not flag setting)">stype == '11' &amp;&amp; S == '0'</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink />
      <text> below for details of when each alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/MOV_rr/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MOVS_rr_A1" oneofinclass="2" oneof="8" label="Flag setting" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOVS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>MOVS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <encoding name="MOV_rr_A1" oneofinclass="2" oneof="8" label="Not flag setting" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOV" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>MOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MOV_rr/A1_A.txt" mylink="aarch32.instrs.MOV_rr.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);</line>
<line>setflags = (S == '1');  shift_t = <a link="impl-aarch32.DecodeRegShift.1" file="shared_pseudocode.xml" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</a>(stype);</line>
<line>if d == 15 || m == 15 || s == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MOV" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/MOV_rr/T1_A.txt" tworows="1">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="4" name="op" usename="1" settings="1">
          <c>0</c>
          <c>x</c>
          <c>x</c>
          <c>x</c>
        </box>
        <box hibit="21" width="3" name="Rs" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rdm" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="MOV_rr_T1_ASR" oneofinclass="4" oneof="8" label="Arithmetic shift right" bitdiffs="op == 0100">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-asr" />
          <docvar key="shift-type" value="asr" />
        </docvars>
        <box hibit="25" width="" name="op">
          <c></c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <asmtemplate comment="Inside IT block"><text>MOV</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, ASR </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <asmtemplate comment="Outside IT block"><text>MOVS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, ASR </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <encoding name="MOV_rr_T1_LSL" oneofinclass="4" oneof="8" label="Logical shift left" bitdiffs="op == 0010">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-lsl" />
          <docvar key="shift-type" value="lsl" />
        </docvars>
        <box hibit="25" width="" name="op">
          <c></c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate comment="Inside IT block"><text>MOV</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, LSL </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <asmtemplate comment="Outside IT block"><text>MOVS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, LSL </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <encoding name="MOV_rr_T1_LSR" oneofinclass="4" oneof="8" label="Logical shift right" bitdiffs="op == 0011">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-lsr" />
          <docvar key="shift-type" value="lsr" />
        </docvars>
        <box hibit="25" width="" name="op">
          <c></c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Inside IT block"><text>MOV</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, LSR </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <asmtemplate comment="Outside IT block"><text>MOVS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, LSR </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <encoding name="MOV_rr_T1_ROR" oneofinclass="4" oneof="8" label="Rotate right" bitdiffs="op == 0111">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-ror" />
          <docvar key="shift-type" value="ror" />
        </docvars>
        <box hibit="25" width="" name="op">
          <c></c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Inside IT block"><text>MOV</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, ROR </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <asmtemplate comment="Outside IT block"><text>MOVS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, ROR </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MOV_rr/T1_A.txt" mylink="aarch32.instrs.MOV_rr.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !(op IN {'0010', '0011', '0100', '0111'}) then SEE "Related encodings";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdm);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdm);  s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);</line>
<line>setflags = !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>();  shift_t = <a link="impl-aarch32.DecodeRegShift.1" file="shared_pseudocode.xml" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</a>(op&lt;2&gt;:op&lt;0&gt;);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/MOV_rr/T2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MOVS_rr_T2" oneofinclass="2" oneof="8" label="Flag setting" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOVS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate comment="Outside IT block, and &lt;Rd&gt;, &lt;Rm&gt;, &lt;shift&gt;, &lt;Rs&gt; can be represented in T1"><text>MOVS.W </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <asmtemplate><text>MOVS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <encoding name="MOV_rr_T2" oneofinclass="2" oneof="8" label="Not flag setting" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate comment="Inside IT block, and &lt;Rd&gt;, &lt;Rm&gt;, &lt;shift&gt;, &lt;Rs&gt; can be represented in T1"><text>MOV</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <asmtemplate><text>MOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MOV_rr/T2_A.txt" mylink="aarch32.instrs.MOV_rr.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);</line>
<line>setflags = (S == '1');  shift_t = <a link="impl-aarch32.DecodeRegShift.1" file="shared_pseudocode.xml" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</a>(stype);</line>
<line>if d == 15 || m == 15 || s == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MOV_rr_A1, MOV_rr_T1_LSL, MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_rr_A1, MOV_rr_T1_LSL, MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_rr_T1_LSL" symboldefcount="1">
      <symbol link="sa_rdm">&lt;Rdm&gt;</symbol>
      <account encodedin="Rdm">
        <intro>
          <para>Is the general-purpose source register and the destination register, encoded in the "Rdm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_rr_A1, MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_rr_A1, MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOV_rr_A1, MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="MOV_rr_A1, MOV_rr_T1_LSL, MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_rs">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MOV_rr/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shift_n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[s]&lt;7:0&gt;);</line>
<line>    (result, carry) = <a link="impl-aarch32.Shift_C.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift_C</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>    if setflags then</line>
<line>        PSTATE.N = result&lt;31&gt;;</line>
<line>        PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>        PSTATE.C = carry;</line>
<line>        // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="movt.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="MOVT" title="MOVT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MOVT" />
  </docvars>
  <heading>MOVT</heading>
  <desc>
    <brief>
      <para>Move Top</para>
    </brief>
    <authored>
      <para>Move Top writes an immediate value to the top halfword of the destination register. It does not affect the contents of the bottom halfword.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="MOVT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/MOVT/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="H" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="MOVT_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOVT" />
        </docvars>
        <asmtemplate><text>MOVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_imm16_1" hover="16-bit unsigned immediate [0-65535] (field &quot;imm4:imm12&quot;)">&lt;imm16&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MOVT/A1_A.txt" mylink="aarch32.instrs.MOVT.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  imm16 = imm4:imm12;</line>
<line>if d == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MOVT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/MOVT/T1_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="MOVT_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOVT" />
        </docvars>
        <asmtemplate><text>MOVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_imm16" hover="16-bit unsigned immediate [0-65535] (field &quot;imm4:i:imm3:imm8&quot;)">&lt;imm16&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MOVT/T1_A.txt" mylink="aarch32.instrs.MOVT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  imm16 = imm4:i:imm3:imm8;</line>
<line>if d == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MOVT_A1, MOVT_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOVT_A1, MOVT_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOVT_A1, MOVT_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOVT_A1" symboldefcount="1">
      <symbol link="sa_imm16_1">&lt;imm16&gt;</symbol>
      <account encodedin="imm4:imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm4:imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MOVT_T1" symboldefcount="2">
      <symbol link="sa_imm16">&lt;imm16&gt;</symbol>
      <account encodedin="imm4:i:imm3:imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm4:i:imm3:imm8" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MOVT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = imm16;</line>
<line>    // R[d]&lt;15:0&gt; unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="mrc.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="MRC" title="MRC -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MRC" />
  </docvars>
  <heading>MRC</heading>
  <desc>
    <brief>
      <para>Move to general-purpose register from System register</para>
    </brief>
    <authored>
      <para>Move to general-purpose register from System register. This instruction copies the value of a System register to a general-purpose register.</para>
      <para>The System register descriptions identify valid encodings for this instruction. Other encodings are <arm-defined-word>undefined</arm-defined-word>. For more information see <xref linkend="CFIDGFBF">About the AArch32 System register interface</xref> and <xref linkend="BABDFCJB">General behavior of System registers</xref>.</para>
      <para>In an implementation that includes EL2, <instruction>MRC</instruction> accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an <instruction>MRC</instruction> instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception.  For more information, see <xref linkend="BEIDFAFD">EL2 configurable instruction enables, disables, and traps</xref>.</para>
      <para>Because of the range of possible traps to Hyp mode, the <instruction>MRC</instruction> pseudocode does not show these possible traps.</para>
    </authored>
    <syntaxnotes>
      <para>The possible values of { <syntax>&lt;coproc&gt;</syntax>, <syntax>&lt;opc1&gt;</syntax>, <syntax>&lt;CRn&gt;</syntax>, <syntax>&lt;CRm&gt;</syntax>, <syntax>&lt;opc2&gt;</syntax> } encode the entire System register and System instruction encoding space. Not all of this space is allocated, and the System register and System instruction descriptions identify the allocated encodings.</para>
    </syntaxnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="MRC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/MRC/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc1" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="CRn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" name="coproc&lt;3:1&gt;" usename="1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" name="coproc&lt;0&gt;" usename="1">
          <c></c>
        </box>
        <box hibit="7" width="3" name="opc2" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="CRm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MRC_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MRC" />
        </docvars>
        <asmtemplate><text>MRC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_coproc" hover="System register encoding space (field &quot;coproc&lt;0&gt;&quot;) [p14,p15]">&lt;coproc&gt;</a><text>, </text><a>{#}</a><a link="sa_opc1" hover="Opc1 parameter within the System register encoding space, in the range 0 to7 (field &quot;opc1&quot;)">&lt;opc1&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register to be transferred or {value{APSR_nzcv}} (encoded as {binarynumber{0b1111}}) (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_crn" hover="CRn parameter within the System register encoding space [c0-c15] (field &quot;CRn&quot;)">&lt;CRn&gt;</a><text>, </text><a link="sa_crm" hover="CRm parameter within the System register encoding space [c0-c15] (field &quot;CRm&quot;)">&lt;CRm&gt;</a><text>{</text><text>, </text><a>{#}</a><a link="sa_opc2" hover="Opc2 parameter within the System register encoding space, in the range 0 to7 (field &quot;opc2&quot;)">&lt;opc2&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MRC/T1A1_A.txt" mylink="aarch32.instrs.MRC.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  cp = if coproc&lt;0&gt; == '0' then 14 else 15;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MRC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/MRC/T1A1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc1" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="CRn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" name="coproc&lt;3:1&gt;" usename="1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" name="coproc&lt;0&gt;" usename="1">
          <c></c>
        </box>
        <box hibit="7" width="3" name="opc2" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="CRm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MRC_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MRC" />
        </docvars>
        <asmtemplate><text>MRC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_coproc" hover="System register encoding space (field &quot;coproc&lt;0&gt;&quot;) [p14,p15]">&lt;coproc&gt;</a><text>, </text><a>{#}</a><a link="sa_opc1" hover="Opc1 parameter within the System register encoding space, in the range 0 to7 (field &quot;opc1&quot;)">&lt;opc1&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register to be transferred or {value{APSR_nzcv}} (encoded as {binarynumber{0b1111}}) (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_crn" hover="CRn parameter within the System register encoding space [c0-c15] (field &quot;CRn&quot;)">&lt;CRn&gt;</a><text>, </text><a link="sa_crm" hover="CRm parameter within the System register encoding space [c0-c15] (field &quot;CRm&quot;)">&lt;CRm&gt;</a><text>{</text><text>, </text><a>{#}</a><a link="sa_opc2" hover="Opc2 parameter within the System register encoding space, in the range 0 to7 (field &quot;opc2&quot;)">&lt;opc2&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MRC/T1A1_A.txt" mylink="aarch32.instrs.MRC.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  cp = if coproc&lt;0&gt; == '0' then 14 else 15;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MRC_A1, MRC_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MRC_A1, MRC_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MRC_A1, MRC_T1" symboldefcount="1">
      <symbol link="sa_coproc">&lt;coproc&gt;</symbol>
      <definition encodedin="coproc&lt;0&gt;">
        <intro>Is the System register encoding space, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">coproc&lt;0&gt;</entry>
                <entry class="symbol">&lt;coproc&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">p14</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">p15</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="MRC_A1, MRC_T1" symboldefcount="1">
      <symbol link="sa_opc1">&lt;opc1&gt;</symbol>
      <account encodedin="opc1">
        <intro>
          <para>Is the opc1 parameter within the System register encoding space, in the range 0 to7, encoded in the "opc1" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MRC_A1, MRC_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred or <value>APSR_nzcv</value> (encoded as <binarynumber>0b1111</binarynumber>), encoded in the "Rt" field. If <value>APSR_nzcv</value> is used, bits [31:28] of the transferred value are written to the <xref linkend="BEIDIGBH">PSTATE</xref> condition flags.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MRC_A1, MRC_T1" symboldefcount="1">
      <symbol link="sa_crn">&lt;CRn&gt;</symbol>
      <account encodedin="CRn">
        <intro>
          <para>Is the CRn parameter within the System register encoding space, in the range c0 to c15, encoded in the "CRn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MRC_A1, MRC_T1" symboldefcount="1">
      <symbol link="sa_crm">&lt;CRm&gt;</symbol>
      <account encodedin="CRm">
        <intro>
          <para>Is the CRm parameter within the System register encoding space, in the range c0 to c15, encoded in the "CRm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MRC_A1, MRC_T1" symboldefcount="1">
      <symbol link="sa_opc2">&lt;opc2&gt;</symbol>
      <account encodedin="opc2">
        <intro>
          <para>Is the opc2 parameter within the System register encoding space, in the range 0 to7, encoded in the "opc2" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MRC/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line></line>
<line>    if t != 15 || <a link="AArch32.SysRegReadCanWriteAPSR.2" file="shared_pseudocode.xml" hover="function: boolean AArch32.SysRegReadCanWriteAPSR(integer cp_num, bits(32) instr)">AArch32.SysRegReadCanWriteAPSR</a>(cp, <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>()) then</line>
<line>        <a link="AArch32.SysRegRead.3" file="shared_pseudocode.xml" hover="function: AArch32.SysRegRead(integer cp_num, bits(32) instr, integer t)">AArch32.SysRegRead</a>(cp, <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>(), t);</line>
<line>    else</line>
<line>        UNPREDICTABLE;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="mrrc.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="MRRC" title="MRRC -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MRRC" />
  </docvars>
  <heading>MRRC</heading>
  <desc>
    <brief>
      <para>Move to two general-purpose registers from System register</para>
    </brief>
    <authored>
      <para>Move to two general-purpose registers from System register. This instruction copies the value of a System register to two general-purpose registers.</para>
      <para>The System register descriptions identify valid encodings for this instruction. Other encodings are <arm-defined-word>undefined</arm-defined-word>. For more information see <xref linkend="CFIDGFBF">About the AArch32 System register interface</xref> and <xref linkend="BABDFCJB">General behavior of System registers</xref>.</para>
      <para>In an implementation that includes EL2, <instruction>MRRC</instruction> accesses to System registers can be trapped to Hyp mode, meaning that an attempt to execute an <instruction>MRRC</instruction> instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception.  For more information, see <xref linkend="BEIDFAFD">EL2 configurable instruction enables, disables, and traps</xref>.</para>
      <para>Because of the range of possible traps to Hyp mode, the <instruction>MRRC</instruction> pseudocode does not show these possible traps.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>The possible values of { <syntax>&lt;coproc&gt;</syntax>, <syntax>&lt;opc1&gt;</syntax>, <syntax>&lt;CRm&gt;</syntax> } encode the entire System register encoding space. Not all of this space is allocated, and the System register descriptions identify the allocated encodings.</para>
      <para>For the permitted uses of these instructions, as described in this manual, <syntax>&lt;Rt2&gt;</syntax> transfers bits[63:32] of the selected System register, while <syntax>&lt;Rt&gt;</syntax> transfers bits[31:0].</para>
    </syntaxnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="MRRC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/MRRC/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rt2" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" name="coproc&lt;3:1&gt;" usename="1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" name="coproc&lt;0&gt;" usename="1">
          <c></c>
        </box>
        <box hibit="7" width="4" name="opc1" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="CRm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MRRC_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MRRC" />
        </docvars>
        <asmtemplate><text>MRRC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_coproc" hover="System register encoding space (field &quot;coproc&lt;0&gt;&quot;) [p14,p15]">&lt;coproc&gt;</a><text>, </text><a>{#}</a><a link="sa_opc1" hover="Opc1 parameter within the System register encoding space [0-15] (field &quot;opc1&quot;)">&lt;opc1&gt;</a><text>, </text><a link="sa_rt" hover="First general-purpose register that is transferred into (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register that is transferred into (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a><text>, </text><a link="sa_crm" hover="CRm parameter within the System register encoding space [c0-c15] (field &quot;CRm&quot;)">&lt;CRm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MRRC/T1A1_A.txt" mylink="aarch32.instrs.MRRC.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2);  cp = if coproc&lt;0&gt; == '0' then 14 else 15;</line>
<line>if t == 15 || t2 == 15 || t == t2 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == t2</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MRRC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/MRRC/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rt2" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" name="coproc&lt;3:1&gt;" usename="1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" name="coproc&lt;0&gt;" usename="1">
          <c></c>
        </box>
        <box hibit="7" width="4" name="opc1" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="CRm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MRRC_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MRRC" />
        </docvars>
        <asmtemplate><text>MRRC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_coproc" hover="System register encoding space (field &quot;coproc&lt;0&gt;&quot;) [p14,p15]">&lt;coproc&gt;</a><text>, </text><a>{#}</a><a link="sa_opc1" hover="Opc1 parameter within the System register encoding space [0-15] (field &quot;opc1&quot;)">&lt;opc1&gt;</a><text>, </text><a link="sa_rt" hover="First general-purpose register that is transferred into (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register that is transferred into (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a><text>, </text><a link="sa_crm" hover="CRm parameter within the System register encoding space [c0-c15] (field &quot;CRm&quot;)">&lt;CRm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MRRC/T1A1_A.txt" mylink="aarch32.instrs.MRRC.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2);  cp = if coproc&lt;0&gt; == '0' then 14 else 15;</line>
<line>if t == 15 || t2 == 15 || t == t2 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == t2</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MRRC_A1, MRRC_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MRRC_A1, MRRC_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MRRC_A1, MRRC_T1" symboldefcount="1">
      <symbol link="sa_coproc">&lt;coproc&gt;</symbol>
      <definition encodedin="coproc&lt;0&gt;">
        <intro>Is the System register encoding space, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">coproc&lt;0&gt;</entry>
                <entry class="symbol">&lt;coproc&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">p14</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">p15</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="MRRC_A1, MRRC_T1" symboldefcount="1">
      <symbol link="sa_opc1">&lt;opc1&gt;</symbol>
      <account encodedin="opc1">
        <intro>
          <para>Is the opc1 parameter within the System register encoding space, in the range 0 to 15, encoded in the "opc1" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MRRC_A1, MRRC_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the first general-purpose register that is transferred into, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MRRC_A1, MRRC_T1" symboldefcount="1">
      <symbol link="sa_rt2">&lt;Rt2&gt;</symbol>
      <account encodedin="Rt2">
        <intro>
          <para>Is the second general-purpose register that is transferred into, encoded in the "Rt2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MRRC_A1, MRRC_T1" symboldefcount="1">
      <symbol link="sa_crm">&lt;CRm&gt;</symbol>
      <account encodedin="CRm">
        <intro>
          <para>Is the CRm parameter within the System register encoding space, in the range c0 to c15, encoded in the "CRm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MRRC/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="AArch32.SysRegRead64.4" file="shared_pseudocode.xml" hover="function: AArch32.SysRegRead64(integer cp_num, bits(32) instr, integer t, integer t2)">AArch32.SysRegRead64</a>(cp, <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>(), t, t2);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="mrs.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="MRS" title="MRS -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MRS" />
  </docvars>
  <heading>MRS</heading>
  <desc>
    <brief>
      <para>Move Special register to general-purpose register</para>
    </brief>
    <authored>
      <para>Move Special register to general-purpose register moves the value of the <xref linkend="CJAGBHBH">APSR</xref>, <xref linkend="CIHJBHJA">CPSR</xref>, or <xref linkend="CHDDAABB">SPSR</xref>_&lt;current_mode&gt; into a general-purpose register.</para>
      <para>Arm recommends the <value>APSR</value> form when only the N, Z, C, V, Q, and GE[3:0] bits are being written. For more information, see <xref linkend="CJAGBHBH">APSR</xref>.</para>
      <para>An <instruction>MRS</instruction> that accesses the <xref linkend="CHDDAABB">SPSRs</xref> is <arm-defined-word>unpredictable</arm-defined-word> if executed in User mode or System mode.</para>
      <para>An <instruction>MRS</instruction> that is executed in User mode and accesses the <xref linkend="CIHJBHJA">CPSR</xref> returns an <arm-defined-word>unknown</arm-defined-word> value for the <xref linkend="CIHJBHJA">CPSR</xref>.{E, A, I, F, M} fields.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="MRS" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/MRS/A1_AS.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="R" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="mask" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="m" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="MRS_A1_AS" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MRS" />
        </docvars>
        <asmtemplate><text>MRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_spec_reg" hover="Special register to be accessed (field &quot;R&quot;) [APSR,CPSR,SPSR]">&lt;spec_reg&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MRS/A1_AS.txt" mylink="aarch32.instrs.MRS.A1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  read_spsr = (R == '1');</line>
<line>if d == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MRS" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/MRS/T1_AS.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="R" usename="1">
          <c></c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="MRS_T1_AS" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MRS" />
        </docvars>
        <asmtemplate><text>MRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_spec_reg" hover="Special register to be accessed (field &quot;R&quot;) [APSR,CPSR,SPSR]">&lt;spec_reg&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MRS/T1_AS.txt" mylink="aarch32.instrs.MRS.T1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  read_spsr = (R == '1');</line>
<line>if d == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MRS_A1_AS, MRS_T1_AS" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MRS_A1_AS, MRS_T1_AS" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MRS_A1_AS, MRS_T1_AS" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MRS_A1_AS, MRS_T1_AS" symboldefcount="1">
      <symbol link="sa_spec_reg">&lt;spec_reg&gt;</symbol>
      <definition encodedin="R">
        <intro>Is the special register to be accessed, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">R</entry>
                <entry class="symbol">&lt;spec_reg&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">CPSR|APSR</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">SPSR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MRS/Op_AS.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if read_spsr then</line>
<line>        if PSTATE.M IN {<a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a>,<a link="M32_System" file="shared_pseudocode.xml" hover="constant bits(5) M32_System = '11111'">M32_System</a>} then</line>
<line>            UNPREDICTABLE;</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.SPSR.read.0" file="shared_pseudocode.xml" hover="accessor: bits(N) SPSR[]">SPSR</a>[];</line>
<line>    else</line>
<line>        // CPSR has same bit assignments as SPSR, but with the IT, J, SS, IL, and T bits masked out.</line>
<line>        bits(32) mask = '11111000 11101111 00000011 11011111';</line>
<line>        psr_val = <a link="impl-shared.GetPSRFromPSTATE.2" file="shared_pseudocode.xml" hover="function: bits(N) GetPSRFromPSTATE(ExceptionalOccurrenceTargetState targetELState, integer N)">GetPSRFromPSTATE</a>(<a link="AArch32_NonDebugState" file="shared_pseudocode.xml" hover="enumeration ExceptionalOccurrenceTargetState { AArch32_NonDebugState, AArch64_NonDebugState, DebugState }">AArch32_NonDebugState</a>, 32) AND mask;</line>
<line>        if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>            // If accessed from User mode return UNKNOWN values for E, A, I, F bits, bits&lt;9:6&gt;,</line>
<line>            // and for the M field, bits&lt;4:0&gt;</line>
<line>            psr_val&lt;22&gt; = bits(1) UNKNOWN;</line>
<line>            psr_val&lt;9:6&gt; = bits(4) UNKNOWN;</line>
<line>            psr_val&lt;4:0&gt; = bits(5) UNKNOWN;</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = psr_val;</line>
</pstext>
    </ps>
  </ps_section>
  <constrained_unpredictables ps_block="Operation">
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>PSTATE.M IN {M32_User, M32_System} &amp;&amp; read_spsr</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
    </cu_case>
  </constrained_unpredictables>
</instructionsection>
</file>
<file type="instructionsection" file="mrs_br.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="MRS_br" title="MRS (Banked register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MRS" />
  </docvars>
  <heading>MRS (Banked register)</heading>
  <desc>
    <brief>
      <para>Move Banked or Special register to general-purpose register</para>
    </brief>
    <authored>
      <para>Move to Register from Banked or Special register moves the value from the Banked general-purpose register or <xref linkend="CHDDAABB">Saved Program Status Registers (SPSRs)</xref> of the specified mode, or the value of <xref linkend="BEIJHFCF">ELR_hyp</xref>, to a general-purpose register.</para>
      <para><instruction>MRS</instruction> (Banked register) is <arm-defined-word>unpredictable</arm-defined-word> if executed in User mode.</para>
      <para>When EL3 is using AArch64, if an MRS (Banked register) instruction that is executed in a Secure EL1 mode would access SPSR_mon, SP_mon, or LR_mon, it is trapped to EL3.</para>
      <para>The effect of using an <instruction>MRS</instruction> (Banked register) instruction with a register argument that is not valid for the current mode is <arm-defined-word>unpredictable</arm-defined-word>. For more information see <xref linkend="CHDFDJDA">Usage restrictions on the Banked register transfer instructions</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="MRS" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/MRS_br/A1_AS.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="R" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="M1" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" name="B" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="MRS_br_A1_AS" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MRS" />
        </docvars>
        <asmtemplate><text>MRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_banked_reg" hover="Banked register to be transferred to or from (field &quot;R:M:M1&quot;)">&lt;banked_reg&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MRS_br/A1_AS.txt" mylink="aarch32.instrs.MRS_br.A1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  read_spsr = (R == '1');</line>
<line>if d == 15 then UNPREDICTABLE;</line>
<line>SYSm = M:M1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MRS" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/MRS_br/T1_AS.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="R" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="M1" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="MRS_br_T1_AS" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MRS" />
        </docvars>
        <asmtemplate><text>MRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_banked_reg" hover="Banked register to be transferred to or from (field &quot;R:M:M1&quot;)">&lt;banked_reg&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MRS_br/T1_AS.txt" mylink="aarch32.instrs.MRS_br.T1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  read_spsr = (R == '1');</line>
<line>if d == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
<line>SYSm = M:M1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MRS_br_A1_AS, MRS_br_T1_AS" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MRS_br_A1_AS, MRS_br_T1_AS" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MRS_br_A1_AS, MRS_br_T1_AS" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MRS_br_A1_AS, MRS_br_T1_AS" symboldefcount="1">
      <symbol link="sa_banked_reg">&lt;banked_reg&gt;</symbol>
      <definition encodedin="R:M:M1">
        <intro>Is the name of the banked register to be transferred to or from, </intro>
        <table class="valuetable">
          <tgroup cols="4">
            <thead>
              <row>
                <entry class="bitfield">R</entry>
                <entry class="bitfield">M</entry>
                <entry class="bitfield">M1</entry>
                <entry class="symbol">&lt;banked_reg&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0000</entry>
                <entry class="symbol">R8_usr</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0001</entry>
                <entry class="symbol">R9_usr</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0010</entry>
                <entry class="symbol">R10_usr</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0011</entry>
                <entry class="symbol">R11_usr</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0100</entry>
                <entry class="symbol">R12_usr</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0101</entry>
                <entry class="symbol">SP_usr</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0110</entry>
                <entry class="symbol">LR_usr</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0111</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1000</entry>
                <entry class="symbol">R8_fiq</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1001</entry>
                <entry class="symbol">R9_fiq</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1010</entry>
                <entry class="symbol">R10_fiq</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1011</entry>
                <entry class="symbol">R11_fiq</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1100</entry>
                <entry class="symbol">R12_fiq</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1101</entry>
                <entry class="symbol">SP_fiq</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1110</entry>
                <entry class="symbol">LR_fiq</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1111</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0000</entry>
                <entry class="symbol">LR_irq</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0001</entry>
                <entry class="symbol">SP_irq</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0010</entry>
                <entry class="symbol">LR_svc</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0011</entry>
                <entry class="symbol">SP_svc</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0100</entry>
                <entry class="symbol">LR_abt</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0101</entry>
                <entry class="symbol">SP_abt</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0110</entry>
                <entry class="symbol">LR_und</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0111</entry>
                <entry class="symbol">SP_und</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10xx</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1100</entry>
                <entry class="symbol">LR_mon</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1101</entry>
                <entry class="symbol">SP_mon</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1110</entry>
                <entry class="symbol">ELR_hyp</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1111</entry>
                <entry class="symbol">SP_hyp</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0xxx</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10xx</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">110x</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1110</entry>
                <entry class="symbol">SPSR_fiq</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1111</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0000</entry>
                <entry class="symbol">SPSR_irq</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0001</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0010</entry>
                <entry class="symbol">SPSR_svc</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0011</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0100</entry>
                <entry class="symbol">SPSR_abt</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0101</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0110</entry>
                <entry class="symbol">SPSR_und</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0111</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10xx</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1100</entry>
                <entry class="symbol">SPSR_mon</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1101</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1110</entry>
                <entry class="symbol">SPSR_hyp</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1111</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MRS_br/Op_AS.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        UNPREDICTABLE;</line>
<line>    else</line>
<line>        mode = PSTATE.M;</line>
<line>        if read_spsr then</line>
<line>            <a link="impl-aarch32.SPSRaccessValid.2" file="shared_pseudocode.xml" hover="function: SPSRaccessValid(bits(5) SYSm, bits(5) mode)">SPSRaccessValid</a>(SYSm, mode);           // Check for UNPREDICTABLE cases</line>
<line>            case SYSm of</line>
<line>                when '01110'  <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = SPSR_fiq&lt;31:0&gt;;</line>
<line>                when '10000'  <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = SPSR_irq&lt;31:0&gt;;</line>
<line>                when '10010'  <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = SPSR_svc&lt;31:0&gt;;</line>
<line>                when '10100'  <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = SPSR_abt&lt;31:0&gt;;</line>
<line>                when '10110'  <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = SPSR_und&lt;31:0&gt;;</line>
<line>                when '11100'</line>
<line>                    if !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then <a link="AArch64.MonitorModeTrap.0" file="shared_pseudocode.xml" hover="function: AArch64.MonitorModeTrap()">AArch64.MonitorModeTrap</a>();</line>
<line>                    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = SPSR_mon;</line>
<line>                when '11110'  <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = SPSR_hyp&lt;31:0&gt;;</line>
<line>        else</line>
<line>            integer m;</line>
<line>            <a link="impl-aarch32.BankedRegisterAccessValid.2" file="shared_pseudocode.xml" hover="function: BankedRegisterAccessValid(bits(5) SYSm, bits(5) mode)">BankedRegisterAccessValid</a>(SYSm, mode); // Check for UNPREDICTABLE cases</line>
<line>            case SYSm of</line>
<line>                when '00xxx'                       // Access the User mode registers</line>
<line>                    m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(SYSm&lt;2:0&gt;) + 8;</line>
<line>                    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-aarch32.Rmode.read.2" file="shared_pseudocode.xml" hover="accessor: bits(32) Rmode[integer n, bits(5) mode]">Rmode</a>[m,<a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a>];</line>
<line>                when '01xxx'                       // Access the FIQ mode registers</line>
<line>                    m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(SYSm&lt;2:0&gt;) + 8;</line>
<line>                    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-aarch32.Rmode.read.2" file="shared_pseudocode.xml" hover="accessor: bits(32) Rmode[integer n, bits(5) mode]">Rmode</a>[m,<a link="M32_FIQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_FIQ = '10001'">M32_FIQ</a>];</line>
<line>                when '1000x'                       // Access the IRQ mode registers</line>
<line>                    m = 14 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(SYSm&lt;0&gt;);        // LR when SYSm&lt;0&gt; == 0, otherwise SP</line>
<line>                    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-aarch32.Rmode.read.2" file="shared_pseudocode.xml" hover="accessor: bits(32) Rmode[integer n, bits(5) mode]">Rmode</a>[m,<a link="M32_IRQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_IRQ = '10010'">M32_IRQ</a>];</line>
<line>                when '1001x'                       // Access the Supervisor mode registers</line>
<line>                    m = 14 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(SYSm&lt;0&gt;);        // LR when SYSm&lt;0&gt; == 0, otherwise SP</line>
<line>                    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-aarch32.Rmode.read.2" file="shared_pseudocode.xml" hover="accessor: bits(32) Rmode[integer n, bits(5) mode]">Rmode</a>[m,<a link="M32_Svc" file="shared_pseudocode.xml" hover="constant bits(5) M32_Svc = '10011'">M32_Svc</a>];</line>
<line>                when '1010x'                       // Access the Abort mode registers</line>
<line>                    m = 14 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(SYSm&lt;0&gt;);        // LR when SYSm&lt;0&gt; == 0, otherwise SP</line>
<line>                    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-aarch32.Rmode.read.2" file="shared_pseudocode.xml" hover="accessor: bits(32) Rmode[integer n, bits(5) mode]">Rmode</a>[m,<a link="M32_Abort" file="shared_pseudocode.xml" hover="constant bits(5) M32_Abort = '10111'">M32_Abort</a>];</line>
<line>                when '1011x'                       // Access the Undefined mode registers</line>
<line>                    m = 14 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(SYSm&lt;0&gt;);        // LR when SYSm&lt;0&gt; == 0, otherwise SP</line>
<line>                    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-aarch32.Rmode.read.2" file="shared_pseudocode.xml" hover="accessor: bits(32) Rmode[integer n, bits(5) mode]">Rmode</a>[m,<a link="M32_Undef" file="shared_pseudocode.xml" hover="constant bits(5) M32_Undef = '11011'">M32_Undef</a>];</line>
<line>                when '1110x'                       // Access Monitor registers</line>
<line>                    if !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then <a link="AArch64.MonitorModeTrap.0" file="shared_pseudocode.xml" hover="function: AArch64.MonitorModeTrap()">AArch64.MonitorModeTrap</a>();</line>
<line>                    m = 14 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(SYSm&lt;0&gt;);        // LR when SYSm&lt;0&gt; == 0, otherwise SP</line>
<line>                    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-aarch32.Rmode.read.2" file="shared_pseudocode.xml" hover="accessor: bits(32) Rmode[integer n, bits(5) mode]">Rmode</a>[m,<a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a>];</line>
<line>                when '11110'                       // Access ELR_hyp register</line>
<line>                    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = ELR_hyp;</line>
<line>                when '11111'                       // Access SP_hyp register</line>
<line>                    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-aarch32.Rmode.read.2" file="shared_pseudocode.xml" hover="accessor: bits(32) Rmode[integer n, bits(5) mode]">Rmode</a>[13,<a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a>];</line>
</pstext>
    </ps>
  </ps_section>
  <constrained_unpredictables ps_block="Operation">
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>PSTATE.EL == EL0</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
    </cu_case>
  </constrained_unpredictables>
</instructionsection>
</file>
<file type="instructionsection" file="msr_br.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="MSR_br" title="MSR (Banked register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MSR" />
  </docvars>
  <heading>MSR (Banked register)</heading>
  <desc>
    <brief>
      <para>Move general-purpose register to Banked or Special register</para>
    </brief>
    <authored>
      <para>Move to Banked or Special register from general-purpose register moves the value of a general-purpose register to the Banked general-purpose register or <xref linkend="CHDDAABB">Saved Program Status Registers (SPSRs)</xref> of the specified mode, or to <xref linkend="BEIJHFCF">ELR_hyp</xref>.</para>
      <para><instruction>MSR</instruction> (Banked register) is <arm-defined-word>unpredictable</arm-defined-word> if executed in User mode.</para>
      <para>When EL3 is using AArch64, if an MSR (Banked register) instruction that is executed in a Secure EL1 mode would access SPSR_mon, SP_mon, or LR_mon, it is trapped to EL3.</para>
      <para>The effect of using an <instruction>MSR</instruction> (Banked register) instruction with a register argument that is not valid for the current mode is <arm-defined-word>unpredictable</arm-defined-word>. For more information see <xref linkend="CHDFDJDA">Usage restrictions on the Banked register transfer instructions</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="MSR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/MSR_br/A1_AS.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="R" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="M1" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" name="B" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MSR_br_A1_AS" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MSR" />
        </docvars>
        <asmtemplate><text>MSR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_banked_reg" hover="Banked register to be transferred to or from (field &quot;R:M:M1&quot;)">&lt;banked_reg&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MSR_br/A1_AS.txt" mylink="aarch32.instrs.MSR_br.A1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  write_spsr = (R == '1');</line>
<line>if n == 15 then UNPREDICTABLE;</line>
<line>SYSm = M:M1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MSR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/MSR_br/T1_AS.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="R" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" width="4" name="M1" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="MSR_br_T1_AS" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MSR" />
        </docvars>
        <asmtemplate><text>MSR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_banked_reg" hover="Banked register to be transferred to or from (field &quot;R:M:M1&quot;)">&lt;banked_reg&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MSR_br/T1_AS.txt" mylink="aarch32.instrs.MSR_br.T1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  write_spsr = (R == '1');</line>
<line>if n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
<line>SYSm = M:M1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MSR_br_A1_AS, MSR_br_T1_AS" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MSR_br_A1_AS, MSR_br_T1_AS" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MSR_br_A1_AS, MSR_br_T1_AS" symboldefcount="1">
      <symbol link="sa_banked_reg">&lt;banked_reg&gt;</symbol>
      <definition encodedin="R:M:M1">
        <intro>Is the name of the banked register to be transferred to or from, </intro>
        <table class="valuetable">
          <tgroup cols="4">
            <thead>
              <row>
                <entry class="bitfield">R</entry>
                <entry class="bitfield">M</entry>
                <entry class="bitfield">M1</entry>
                <entry class="symbol">&lt;banked_reg&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0000</entry>
                <entry class="symbol">R8_usr</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0001</entry>
                <entry class="symbol">R9_usr</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0010</entry>
                <entry class="symbol">R10_usr</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0011</entry>
                <entry class="symbol">R11_usr</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0100</entry>
                <entry class="symbol">R12_usr</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0101</entry>
                <entry class="symbol">SP_usr</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0110</entry>
                <entry class="symbol">LR_usr</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0111</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1000</entry>
                <entry class="symbol">R8_fiq</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1001</entry>
                <entry class="symbol">R9_fiq</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1010</entry>
                <entry class="symbol">R10_fiq</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1011</entry>
                <entry class="symbol">R11_fiq</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1100</entry>
                <entry class="symbol">R12_fiq</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1101</entry>
                <entry class="symbol">SP_fiq</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1110</entry>
                <entry class="symbol">LR_fiq</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1111</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0000</entry>
                <entry class="symbol">LR_irq</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0001</entry>
                <entry class="symbol">SP_irq</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0010</entry>
                <entry class="symbol">LR_svc</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0011</entry>
                <entry class="symbol">SP_svc</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0100</entry>
                <entry class="symbol">LR_abt</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0101</entry>
                <entry class="symbol">SP_abt</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0110</entry>
                <entry class="symbol">LR_und</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0111</entry>
                <entry class="symbol">SP_und</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10xx</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1100</entry>
                <entry class="symbol">LR_mon</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1101</entry>
                <entry class="symbol">SP_mon</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1110</entry>
                <entry class="symbol">ELR_hyp</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1111</entry>
                <entry class="symbol">SP_hyp</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0xxx</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10xx</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">110x</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1110</entry>
                <entry class="symbol">SPSR_fiq</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1111</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0000</entry>
                <entry class="symbol">SPSR_irq</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0001</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0010</entry>
                <entry class="symbol">SPSR_svc</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0011</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0100</entry>
                <entry class="symbol">SPSR_abt</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0101</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0110</entry>
                <entry class="symbol">SPSR_und</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0111</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10xx</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1100</entry>
                <entry class="symbol">SPSR_mon</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1101</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1110</entry>
                <entry class="symbol">SPSR_hyp</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1111</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="MSR_br_A1_AS, MSR_br_T1_AS" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MSR_br/Op_AS.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        UNPREDICTABLE;</line>
<line>    else</line>
<line>        mode = PSTATE.M;</line>
<line>        if write_spsr then</line>
<line>            <a link="impl-aarch32.SPSRaccessValid.2" file="shared_pseudocode.xml" hover="function: SPSRaccessValid(bits(5) SYSm, bits(5) mode)">SPSRaccessValid</a>(SYSm, mode);             // Check for UNPREDICTABLE cases</line>
<line>            case SYSm of</line>
<line>                when '01110'  SPSR_fiq&lt;31:0&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>                when '10000'  SPSR_irq&lt;31:0&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>                when '10010'  SPSR_svc&lt;31:0&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>                when '10100'  SPSR_abt&lt;31:0&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>                when '10110'  SPSR_und&lt;31:0&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>                when '11100'</line>
<line>                    if !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then <a link="AArch64.MonitorModeTrap.0" file="shared_pseudocode.xml" hover="function: AArch64.MonitorModeTrap()">AArch64.MonitorModeTrap</a>();</line>
<line>                    SPSR_mon&lt;31:0&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>                when '11110'  SPSR_hyp&lt;31:0&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>        else</line>
<line>            integer m;</line>
<line>            <a link="impl-aarch32.BankedRegisterAccessValid.2" file="shared_pseudocode.xml" hover="function: BankedRegisterAccessValid(bits(5) SYSm, bits(5) mode)">BankedRegisterAccessValid</a>(SYSm, mode); // Check for UNPREDICTABLE cases</line>
<line>            case SYSm of</line>
<line>                when '00xxx'                       // Access the User mode registers</line>
<line>                    m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(SYSm&lt;2:0&gt;) + 8;</line>
<line>                    <a link="impl-aarch32.Rmode.write.2" file="shared_pseudocode.xml" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</a>[m,<a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a>] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>                when '01xxx'                       // Access the FIQ mode registers</line>
<line>                    m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(SYSm&lt;2:0&gt;) + 8;</line>
<line>                    <a link="impl-aarch32.Rmode.write.2" file="shared_pseudocode.xml" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</a>[m,<a link="M32_FIQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_FIQ = '10001'">M32_FIQ</a>] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>                when '1000x'                       // Access the IRQ mode registers</line>
<line>                    m = 14 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(SYSm&lt;0&gt;);        // LR when SYSm&lt;0&gt; == 0, otherwise SP</line>
<line>                    <a link="impl-aarch32.Rmode.write.2" file="shared_pseudocode.xml" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</a>[m,<a link="M32_IRQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_IRQ = '10010'">M32_IRQ</a>] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>                when '1001x'                       // Access the Supervisor mode registers</line>
<line>                    m = 14 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(SYSm&lt;0&gt;);        // LR when SYSm&lt;0&gt; == 0, otherwise SP</line>
<line>                    <a link="impl-aarch32.Rmode.write.2" file="shared_pseudocode.xml" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</a>[m,<a link="M32_Svc" file="shared_pseudocode.xml" hover="constant bits(5) M32_Svc = '10011'">M32_Svc</a>] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>                when '1010x'                       // Access the Abort mode registers</line>
<line>                    m = 14 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(SYSm&lt;0&gt;);        // LR when SYSm&lt;0&gt; == 0, otherwise SP</line>
<line>                    <a link="impl-aarch32.Rmode.write.2" file="shared_pseudocode.xml" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</a>[m,<a link="M32_Abort" file="shared_pseudocode.xml" hover="constant bits(5) M32_Abort = '10111'">M32_Abort</a>] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>                when '1011x'                       // Access the Undefined mode registers</line>
<line>                    m = 14 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(SYSm&lt;0&gt;);        // LR when SYSm&lt;0&gt; == 0, otherwise SP</line>
<line>                    <a link="impl-aarch32.Rmode.write.2" file="shared_pseudocode.xml" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</a>[m,<a link="M32_Undef" file="shared_pseudocode.xml" hover="constant bits(5) M32_Undef = '11011'">M32_Undef</a>] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>                when '1110x'                       // Access Monitor registers</line>
<line>                    if !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then <a link="AArch64.MonitorModeTrap.0" file="shared_pseudocode.xml" hover="function: AArch64.MonitorModeTrap()">AArch64.MonitorModeTrap</a>();</line>
<line>                    m = 14 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(SYSm&lt;0&gt;);        // LR when SYSm&lt;0&gt; == 0, otherwise SP</line>
<line>                    <a link="impl-aarch32.Rmode.write.2" file="shared_pseudocode.xml" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</a>[m,<a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a>] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>                when '11110'                       // Access ELR_hyp register</line>
<line>                    ELR_hyp = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>                when '11111'                       // Access SP_hyp register</line>
<line>                    <a link="impl-aarch32.Rmode.write.2" file="shared_pseudocode.xml" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</a>[13,<a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a>] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
</pstext>
    </ps>
  </ps_section>
  <constrained_unpredictables ps_block="Operation">
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>PSTATE.EL == EL0</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
    </cu_case>
  </constrained_unpredictables>
</instructionsection>
</file>
<file type="instructionsection" file="msr_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="MSR_i" title="MSR (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
    <docvar key="mnemonic" value="MSR" />
  </docvars>
  <heading>MSR (immediate)</heading>
  <desc>
    <brief>
      <para>Move immediate value to Special register</para>
    </brief>
    <authored>
      <para>Move immediate value to Special register moves selected bits of an immediate value to the corresponding bits in the <xref linkend="CJAGBHBH">APSR</xref>, <xref linkend="CIHJBHJA">CPSR</xref>, or <xref linkend="CHDDAABB">SPSR</xref>_&lt;current_mode&gt;.</para>
      <para>Because of the Do-Not-Modify nature of its reserved bits, the immediate form of <instruction>MSR</instruction> is normally only useful at the Application level for writing to <value>APSR_nzcvq</value> (<value>CPSR_f</value>).</para>
      <para>If an <instruction>MSR</instruction> (immediate) moves selected bits of an immediate value to the <xref linkend="CIHJBHJA">CPSR</xref>, the PE checks whether the value being written to <xref linkend="BEIDIGBH">PSTATE</xref>.M is legal. See <xref linkend="CHDDFIGE">Illegal changes to PSTATE.M</xref>.</para>
      <para>An <instruction>MSR</instruction> (immediate) executed in User mode:</para>
      <list type="unordered">
        <listitem><content>Is <arm-defined-word>constrained unpredictable</arm-defined-word> if it attempts to update the <xref linkend="CHDDAABB">SPSR</xref>.</content></listitem>
        <listitem><content>Otherwise, does not update any <xref linkend="CIHJBHJA">CPSR</xref> field that is accessible only at EL1 or higher,</content></listitem>
      </list>
      <para>An <instruction>MSR</instruction> (immediate) executed in System mode is <arm-defined-word>constrained unpredictable</arm-defined-word> if it attempts to update the <xref linkend="CHDDAABB">SPSR</xref>.</para>
      <para>The <xref linkend="CIHJBHJA">CPSR</xref>.E bit is writable from any mode using an <instruction>MSR</instruction> instruction.  Arm deprecates using this to change its value.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
      <para>Related encodings: <xref linkend="A32.encoding_index.movsr_hint_imm">Move Special Register and Hints (immediate)</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="MSR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/MSR_i/A1_AS.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="R" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="mask" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="MSR_i_A1_AS" oneofinclass="1" oneof="1" label="A1" bitdiffs="!(R == 0 &amp;&amp; mask == 0000)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MSR" />
        </docvars>
        <box hibit="22" width="7" name="R:mask">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
        </box>
        <asmtemplate><text>MSR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_spec_reg" hover="One of:&#10;* {value{APSR_&lt;bits&gt;}}">&lt;spec_reg&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MSR_i/A1_AS.txt" mylink="aarch32.instrs.MSR_i.A1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if mask == '0000' &amp;&amp; R == '0' then SEE "Related encodings";</line>
<line>imm32 = <a link="impl-aarch32.A32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) A32ExpandImm(bits(12) imm12)">A32ExpandImm</a>(imm12);  write_spsr = (R == '1');</line>
<line>if mask == '0000' then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>mask == '0000' &amp;&amp; R == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MSR_i_A1_AS" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MSR_i_A1_AS" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MSR_i_A1_AS" symboldefcount="1">
      <symbol link="sa_spec_reg">&lt;spec_reg&gt;</symbol>
      <account encodedin="mask">
        <intro>
          <para>Is one of:</para>
          <list type="unordered">
            <listitem><content><value>APSR_&lt;bits&gt;</value>.</content></listitem>
            <listitem><content><value>CPSR_&lt;fields&gt;</value>.</content></listitem>
            <listitem><content><value>SPSR_&lt;fields&gt;</value>.</content></listitem>
          </list>
          <para>For CPSR and SPSR, &lt;fields&gt; is a sequence of one or more of the following:</para>
          <list type="param">
            <listitem>
              <param>c</param><content>mask&lt;0&gt; = '1' to enable writing of bits&lt;7:0&gt; of the destination PSR.</content>
            </listitem>
            <listitem>
              <param>x</param><content>mask&lt;1&gt; = '1' to enable writing of bits&lt;15:8&gt; of the destination PSR.</content>
            </listitem>
            <listitem>
              <param>s</param><content>mask&lt;2&gt; = '1' to enable writing of bits&lt;23:16&gt; of the destination PSR.</content>
            </listitem>
            <listitem>
              <param>f</param><content>mask&lt;3&gt; = '1' to enable writing of bits&lt;31:24&gt; of the destination PSR.</content>
            </listitem>
          </list>
          <para>For APSR, &lt;bits&gt; is one of <value>nzcvq</value>, <value>g</value>, or <value>nzcvqg</value>. These map to the following CPSR_&lt;fields&gt; values:</para>
          <list type="unordered">
            <listitem><content><value>APSR_nzcvq</value> is the same as <value>CPSR_f</value> (mask== '1000').</content></listitem>
            <listitem><content><value>APSR_g</value> is the same as <value>CPSR_s</value> (mask == '0100').</content></listitem>
            <listitem><content><value>APSR_nzcvqg</value> is the same as <value>CPSR_fs</value> (mask == '1100').</content></listitem>
          </list>
          <para>Arm recommends the <value>APSR_&lt;bits&gt;</value> forms when only the N, Z, C, V, Q, and GE[3:0] bits are being written. For more information, see <xref linkend="CJAGBHBH">The Application Program Status Register, APSR</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MSR_i_A1_AS" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is an immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MSR_i/Op_AS.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if write_spsr then</line>
<line>        if PSTATE.M IN {<a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a>,<a link="M32_System" file="shared_pseudocode.xml" hover="constant bits(5) M32_System = '11111'">M32_System</a>} then</line>
<line>            UNPREDICTABLE;</line>
<line>        else</line>
<line>            <a link="impl-aarch32.SPSRWriteByInstr.2" file="shared_pseudocode.xml" hover="function: SPSRWriteByInstr(bits(32) value, bits(4) bytemask)">SPSRWriteByInstr</a>(imm32, mask);</line>
<line>    else</line>
<line>        // Attempts to change to an illegal mode will invoke the Illegal Execution state mechanism</line>
<line>        <a link="impl-aarch32.CPSRWriteByInstr.2" file="shared_pseudocode.xml" hover="function: CPSRWriteByInstr(bits(32) value, bits(4) bytemask)">CPSRWriteByInstr</a>(imm32, mask);</line>
</pstext>
    </ps>
  </ps_section>
  <constrained_unpredictables ps_block="Operation">
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>PSTATE.M IN {M32_User,M32_System} &amp;&amp; write_spsr</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
    </cu_case>
  </constrained_unpredictables>
</instructionsection>
</file>
<file type="instructionsection" file="msr_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="MSR_r" title="MSR (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MSR" />
  </docvars>
  <heading>MSR (register)</heading>
  <desc>
    <brief>
      <para>Move general-purpose register to Special register</para>
    </brief>
    <authored>
      <para>Move general-purpose register to Special register moves selected bits of a general-purpose register to the <xref linkend="CJAGBHBH">APSR</xref>, <xref linkend="CIHJBHJA">CPSR</xref> or <xref linkend="CHDDAABB">SPSR</xref>_&lt;current_mode&gt;.</para>
      <para>Because of the Do-Not-Modify nature of its reserved bits, a read-modify-write sequence is normally required when the <instruction>MSR</instruction> instruction is being used at Application level and its destination is not <value>APSR_nzcvq</value> (<value>CPSR_f</value>).</para>
      <para>If an <instruction>MSR</instruction> (register) moves selected bits of an immediate value to the <xref linkend="CIHJBHJA">CPSR</xref>, the PE checks whether the value being written to <xref linkend="BEIDIGBH">PSTATE</xref>.M is legal. See <xref linkend="CHDDFIGE">Illegal changes to PSTATE.M</xref>.</para>
      <para>An <instruction>MSR</instruction> (register) executed in User mode:</para>
      <list type="unordered">
        <listitem><content>Is <arm-defined-word>unpredictable</arm-defined-word> if it attempts to update the <xref linkend="CHDDAABB">SPSR</xref>.</content></listitem>
        <listitem><content>Otherwise, does not update any <xref linkend="CIHJBHJA">CPSR</xref> field that is accessible only at EL1 or higher.</content></listitem>
      </list>
      <para>An <instruction>MSR</instruction> (register) executed in System mode is <arm-defined-word>unpredictable</arm-defined-word> if it attempts to update the <xref linkend="CHDDAABB">SPSR</xref>.</para>
      <para>The <xref linkend="CIHJBHJA">CPSR</xref>.E bit is writable from any mode using an <instruction>MSR</instruction> instruction.  Arm deprecates using this to change its value.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="MSR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/MSR_r/A1_AS.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="R" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="mask" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="m" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MSR_r_A1_AS" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MSR" />
        </docvars>
        <asmtemplate><text>MSR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_spec_reg" hover="One of:&#10;* {value{APSR_&lt;bits&gt;}}">&lt;spec_reg&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MSR_r/A1_AS.txt" mylink="aarch32.instrs.MSR_r.A1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  write_spsr = (R == '1');</line>
<line>if mask == '0000' then UNPREDICTABLE;</line>
<line>if n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>mask == '0000'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MSR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/MSR_r/T1_AS.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="R" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" width="4" name="mask" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="MSR_r_T1_AS" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MSR" />
        </docvars>
        <asmtemplate><text>MSR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_spec_reg" hover="One of:&#10;* {value{APSR_&lt;bits&gt;}}">&lt;spec_reg&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MSR_r/T1_AS.txt" mylink="aarch32.instrs.MSR_r.T1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  write_spsr = (R == '1');</line>
<line>if mask == '0000' then UNPREDICTABLE;</line>
<line>if n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>mask == '0000'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MSR_r_A1_AS, MSR_r_T1_AS" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MSR_r_A1_AS, MSR_r_T1_AS" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MSR_r_A1_AS, MSR_r_T1_AS" symboldefcount="1">
      <symbol link="sa_spec_reg">&lt;spec_reg&gt;</symbol>
      <account encodedin="mask">
        <intro>
          <para>Is one of:</para>
          <list type="unordered">
            <listitem><content><value>APSR_&lt;bits&gt;</value>.</content></listitem>
            <listitem><content><value>CPSR_&lt;fields&gt;</value>.</content></listitem>
            <listitem><content><value>SPSR_&lt;fields&gt;</value>.</content></listitem>
          </list>
          <para>For CPSR and SPSR, &lt;fields&gt; is a sequence of one or more of the following:</para>
          <list type="param">
            <listitem>
              <param>c</param><content>mask&lt;0&gt; = '1' to enable writing of bits&lt;7:0&gt; of the destination PSR.</content>
            </listitem>
            <listitem>
              <param>x</param><content>mask&lt;1&gt; = '1' to enable writing of bits&lt;15:8&gt; of the destination PSR.</content>
            </listitem>
            <listitem>
              <param>s</param><content>mask&lt;2&gt; = '1' to enable writing of bits&lt;23:16&gt; of the destination PSR.</content>
            </listitem>
            <listitem>
              <param>f</param><content>mask&lt;3&gt; = '1' to enable writing of bits&lt;31:24&gt; of the destination PSR.</content>
            </listitem>
          </list>
          <para>For APSR, &lt;bits&gt; is one of <value>nzcvq</value>, <value>g</value>, or <value>nzcvqg</value>. These map to the following CPSR_&lt;fields&gt; values:</para>
          <list type="unordered">
            <listitem><content><value>APSR_nzcvq</value> is the same as <value>CPSR_f</value> (mask== '1000').</content></listitem>
            <listitem><content><value>APSR_g</value> is the same as <value>CPSR_s</value> (mask == '0100').</content></listitem>
            <listitem><content><value>APSR_nzcvqg</value> is the same as <value>CPSR_fs</value> (mask == '1100').</content></listitem>
          </list>
          <para>Arm recommends the <value>APSR_&lt;bits&gt;</value> forms when only the N, Z, C, V, Q, and GE[3:0] bits are being written. For more information, see <xref linkend="CJAGBHBH">The Application Program Status Register, APSR</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MSR_r_A1_AS, MSR_r_T1_AS" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MSR_r/Op_AS.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if write_spsr then</line>
<line>        if PSTATE.M IN {<a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a>,<a link="M32_System" file="shared_pseudocode.xml" hover="constant bits(5) M32_System = '11111'">M32_System</a>} then</line>
<line>            UNPREDICTABLE;</line>
<line>        else</line>
<line>            <a link="impl-aarch32.SPSRWriteByInstr.2" file="shared_pseudocode.xml" hover="function: SPSRWriteByInstr(bits(32) value, bits(4) bytemask)">SPSRWriteByInstr</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], mask);</line>
<line>    else</line>
<line>        // Attempts to change to an illegal mode will invoke the Illegal Execution state mechanism</line>
<line>        <a link="impl-aarch32.CPSRWriteByInstr.2" file="shared_pseudocode.xml" hover="function: CPSRWriteByInstr(bits(32) value, bits(4) bytemask)">CPSRWriteByInstr</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], mask);</line>
</pstext>
    </ps>
  </ps_section>
  <constrained_unpredictables ps_block="Operation">
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>write_spsr &amp;&amp; PSTATE.M IN {M32_User,M32_System}</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
    </cu_case>
  </constrained_unpredictables>
</instructionsection>
</file>
<file type="instructionsection" file="mul.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="MUL" title="MUL, MULS -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>MUL, MULS</heading>
  <desc>
    <brief>
      <para>Multiply</para>
    </brief>
    <authored>
      <para>Multiply multiplies two register values. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values.</para>
      <para>Optionally, it can update the condition flags based on the result. In the T32 instruction set, this option is limited to only a few forms of the instruction. Use of this option adversely affects performance on many implementations.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/MUL/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="RdLo" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MULS_A1" oneofinclass="2" oneof="4" label="Flag setting" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MULS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>MULS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="MUL_A1" oneofinclass="2" oneof="4" label="Not flag setting" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MUL" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>MUL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MUL/A1_A.txt" mylink="aarch32.instrs.MUL.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MUL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/MUL/T1_A.txt">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="4" name="op" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="21" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rdm" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="MUL_T1" oneofinclass="1" oneof="4" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MUL" />
        </docvars>
        <asmtemplate comment="Inside IT block"><text>MUL</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdm" hover="Second general-purpose source register holding multiplier and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>, </text><a link="sa_rdm" hover="Second general-purpose source register holding multiplier and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>}</text></asmtemplate>
        <asmtemplate comment="Outside IT block"><text>MULS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdm" hover="Second general-purpose source register holding multiplier and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>, </text><a link="sa_rdm" hover="Second general-purpose source register holding multiplier and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MUL/T1_A.txt" mylink="aarch32.instrs.MUL.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdm);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdm);  setflags = !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>();</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MUL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/MUL/T2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MUL_T2" oneofinclass="1" oneof="4" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MUL" />
        </docvars>
        <asmtemplate comment="Inside IT block, and &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>MUL</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>}</text></asmtemplate>
        <asmtemplate><text>MUL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MUL/T2_A.txt" mylink="aarch32.instrs.MUL.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = FALSE;</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MUL_A1, MUL_T1, MUL_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MUL_A1, MUL_T1, MUL_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MUL_T1" symboldefcount="1">
      <symbol link="sa_rdm">&lt;Rdm&gt;</symbol>
      <account encodedin="Rdm">
        <intro>
          <para>Is the second general-purpose source register holding the multiplier and the destination register, encoded in the "Rdm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MUL_A1, MUL_T2" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MUL_A1, MUL_T1, MUL_T2" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MUL_A1, MUL_T2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register holding the multiplier, encoded in the "Rm" field. If omitted, <syntax>&lt;Rd&gt;</syntax> is used.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MUL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    operand1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]);  // operand1 = UInt(R[n]) produces the same final results</line>
<line>    operand2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]);  // operand2 = UInt(R[m]) produces the same final results</line>
<line>    result = operand1 * operand2;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result&lt;31:0&gt;;</line>
<line>    if setflags then</line>
<line>        PSTATE.N = result&lt;31&gt;;</line>
<line>        PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result&lt;31:0&gt;);</line>
<line>        // PSTATE.C, PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="mvn_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="MVN_i" title="MVN, MVNS (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>MVN, MVNS (immediate)</heading>
  <desc>
    <brief>
      <para>Bitwise NOT (immediate)</para>
    </brief>
    <authored>
      <para>Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to the destination register.</para>
      <para>If the destination register is not the PC, the MVNS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. ARM deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The MVN variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The MVNS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/MVN_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="MVN_i_A1" oneofinclass="2" oneof="4" label="MVN" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MVN" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>MVN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="MVNS_i_A1" oneofinclass="2" oneof="4" label="MVNS" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MVNS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>MVNS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MVN_i/A1_A.txt" mylink="aarch32.instrs.MVN_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  setflags = (S == '1');</line>
<line>(imm32, carry) = <a link="impl-aarch32.A32ExpandImm_C.2" file="shared_pseudocode.xml" hover="function: (bits(32), bit) A32ExpandImm_C(bits(12) imm12, bit carry_in)">A32ExpandImm_C</a>(imm12, PSTATE.C);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/MVN_i/T1_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="MVN_i_T1" oneofinclass="2" oneof="4" label="MVN" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MVN" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>MVN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="MVNS_i_T1" oneofinclass="2" oneof="4" label="MVNS" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MVNS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>MVNS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MVN_i/T1_A.txt" mylink="aarch32.instrs.MVN_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  setflags = (S == '1');</line>
<line>(imm32, carry) = <a link="impl-aarch32.T32ExpandImm_C.2" file="shared_pseudocode.xml" hover="function: (bits(32), bit) T32ExpandImm_C(bits(12) imm12, bit carry_in)">T32ExpandImm_C</a>(i:imm3:imm8, PSTATE.C);</line>
<line>if d == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MVN_i_A1, MVN_i_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MVN_i_A1, MVN_i_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MVN_i_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the MVN variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the MVNS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MVN_i_T1" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MVN_i_A1" symboldefcount="1">
      <symbol link="sa_const_1">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: an immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MVN_i_T1" symboldefcount="2">
      <symbol link="sa_const">&lt;const&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: an immediate value. See <xref linkend="BABGHAGA">Modified immediate constants in T32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MVN_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    result = NOT(imm32);</line>
<line>    if d == 15 then          // Can only occur for A32 encoding</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.N = result&lt;31&gt;;</line>
<line>            PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>            PSTATE.C = carry;</line>
<line>            // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="mvn_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="MVN_r" title="MVN, MVNS (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>MVN, MVNS (register)</heading>
  <desc>
    <brief>
      <para>Bitwise NOT (register)</para>
    </brief>
    <authored>
      <para>Bitwise NOT (register) writes the bitwise inverse of a register value to the destination register.</para>
      <para>If the destination register is not the PC, the MVNS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. ARM deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The MVN variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The MVNS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/MVN_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MVN_r_A1_RRX" oneofinclass="4" oneof="9" label="MVN, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MVN" />
          <docvar key="mnemonic-shift-type" value="MVN-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>MVN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="MVN_r_A1" oneofinclass="4" oneof="9" label="MVN, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MVN" />
          <docvar key="mnemonic-shift-type" value="MVN-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>MVN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="MVNS_r_A1_RRX" oneofinclass="4" oneof="9" label="MVNS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MVNS" />
          <docvar key="mnemonic-shift-type" value="MVNS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>MVNS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="MVNS_r_A1" oneofinclass="4" oneof="9" label="MVNS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MVNS" />
          <docvar key="mnemonic-shift-type" value="MVNS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>MVNS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MVN_r/A1_A.txt" mylink="aarch32.instrs.MVN_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MVN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/MVN_r/T1_A.txt">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="4" name="op" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="MVN_r_T1" oneofinclass="1" oneof="9" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MVN" />
        </docvars>
        <asmtemplate comment="Inside IT block"><text>MVN</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate comment="Outside IT block"><text>MVNS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MVN_r/T1_A.txt" mylink="aarch32.instrs.MVN_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>();</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/MVN_r/T2_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MVN_r_T2_RRX" oneofinclass="4" oneof="9" label="MVN, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MVN" />
          <docvar key="mnemonic-shift-type" value="MVN-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>MVN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="MVN_r_T2" oneofinclass="4" oneof="9" label="MVN, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MVN" />
          <docvar key="mnemonic-shift-type" value="MVN-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Inside IT block, and &lt;Rd&gt;, &lt;Rm&gt; can be represented in T1"><text>MVN</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>MVN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="MVNS_r_T2_RRX" oneofinclass="4" oneof="9" label="MVNS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MVNS" />
          <docvar key="mnemonic-shift-type" value="MVNS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>MVNS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="MVNS_r_T2" oneofinclass="4" oneof="9" label="MVNS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MVNS" />
          <docvar key="mnemonic-shift-type" value="MVNS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Outside IT block, and &lt;Rd&gt;, &lt;Rm&gt; can be represented in T1"><text>MVNS.W </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>MVNS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MVN_r/T2_A.txt" mylink="aarch32.instrs.MVN_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm3:imm2);</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MVN_r_A1, MVN_r_T1, MVN_r_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MVN_r_A1, MVN_r_T1, MVN_r_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MVN_r_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="MVN-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the MVN variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the MVNS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MVN_r_T1, MVN_r_T2" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MVN_r_A1" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="MVN-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MVN_r_T1, MVN_r_T2" symboldefcount="2">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MVN_r_A1, MVN_r_T2" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="MVN_r_A1" symboldefcount="1">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MVN_r_T2" symboldefcount="2">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm3:imm2" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MVN_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    (shifted, carry) = <a link="impl-aarch32.Shift_C.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift_C</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    result = NOT(shifted);</line>
<line>    if d == 15 then          // Can only occur for A32 encoding</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.N = result&lt;31&gt;;</line>
<line>            PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>            PSTATE.C = carry;</line>
<line>            // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="mvn_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="MVN_rr" title="MVN, MVNS (register-shifted register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
  </docvars>
  <heading>MVN, MVNS (register-shifted register)</heading>
  <desc>
    <brief>
      <para>Bitwise NOT (register-shifted register)</para>
    </brief>
    <authored>
      <para>Bitwise NOT (register-shifted register) writes the bitwise inverse of a register-shifted register value to the destination register. It can optionally update the condition flags based on the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/MVN_rr/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MVNS_rr_A1" oneofinclass="2" oneof="2" label="Flag setting" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MVNS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>MVNS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <encoding name="MVN_rr_A1" oneofinclass="2" oneof="2" label="Not flag setting" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MVN" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>MVN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MVN_rr/A1_A.txt" mylink="aarch32.instrs.MVN_rr.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);</line>
<line>setflags = (S == '1');  shift_t = <a link="impl-aarch32.DecodeRegShift.1" file="shared_pseudocode.xml" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</a>(stype);</line>
<line>if d == 15 || m == 15 || s == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MVN_rr_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MVN_rr_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MVN_rr_A1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MVN_rr_A1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MVN_rr_A1" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="MVN_rr_A1" symboldefcount="1">
      <symbol link="sa_rs">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MVN_rr/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shift_n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[s]&lt;7:0&gt;);</line>
<line>    (shifted, carry) = <a link="impl-aarch32.Shift_C.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift_C</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    result = NOT(shifted);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>    if setflags then</line>
<line>        PSTATE.N = result&lt;31&gt;;</line>
<line>        PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>        PSTATE.C = carry;</line>
<line>        // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="nop.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="NOP" title="NOP -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="NOP" />
  </docvars>
  <heading>NOP</heading>
  <desc>
    <brief>
      <para>No Operation</para>
    </brief>
    <authored>
      <para>No Operation does nothing. This instruction can be used for instruction alignment purposes.</para>
      <note>
        <para>The timing effects of including a <instruction>NOP</instruction> instruction in a program are not guaranteed. It can increase execution time, leave it unchanged, or even reduce it. Therefore, <instruction>NOP</instruction> instructions are not suitable for timing loops.</para>
      </note>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="NOP" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/NOP/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="R" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="2" name="imm4&lt;3:2&gt;" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="17" width="2" name="imm4&lt;1:0&gt;" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" width="12" name="imm12" settings="12">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="NOP_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="NOP" />
        </docvars>
        <asmtemplate><text>NOP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/NOP/A1_A.txt" mylink="aarch32.instrs.NOP.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="NOP" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/NOP/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" width="4" name="hint" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="NOP_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="NOP" />
        </docvars>
        <asmtemplate><text>NOP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/NOP/T1_A.txt" mylink="aarch32.instrs.NOP.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="NOP" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/NOP/T2_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="hint" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="option" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="NOP_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="NOP" />
        </docvars>
        <asmtemplate><text>NOP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/NOP/T2_A.txt" mylink="aarch32.instrs.NOP.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="NOP_A1, NOP_T1, NOP_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="NOP_A1, NOP_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/NOP/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    // Do nothing</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="orn_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ORN_i" title="ORN, ORNS (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="T1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="T32" />
  </docvars>
  <heading>ORN, ORNS (immediate)</heading>
  <desc>
    <brief>
      <para>Bitwise OR NOT (immediate)</para>
    </brief>
    <authored>
      <para>Bitwise OR NOT (immediate) performs a bitwise (inclusive) OR of a register value and the complement of an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="T1" oneof="1" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/ORN_i/T1_A.txt" tworows="1">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="ORNS_i_T1" oneofinclass="2" oneof="2" label="Flag setting" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ORNS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>ORNS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="ORN_i_T1" oneofinclass="2" oneof="2" label="Not flag setting" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ORN" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>ORN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ORN_i/T1_A.txt" mylink="aarch32.instrs.ORN_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "MVN (immediate)";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = (S == '1');</line>
<line>(imm32, carry) = <a link="impl-aarch32.T32ExpandImm_C.2" file="shared_pseudocode.xml" hover="function: (bits(32), bit) T32ExpandImm_C(bits(12) imm12, bit carry_in)">T32ExpandImm_C</a>(i:imm3:imm8, PSTATE.C);</line>
<line>if d == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ORN_i_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORN_i_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORN_i_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORN_i_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORN_i_T1" symboldefcount="1">
      <symbol link="sa_const">&lt;const&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <intro>
          <para>An immediate value. See <xref linkend="BABGHAGA">Modified immediate constants in T32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/ORN_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    result = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] OR NOT(imm32);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>    if setflags then</line>
<line>        PSTATE.N = result&lt;31&gt;;</line>
<line>        PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>        PSTATE.C = carry;</line>
<line>        // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="orn_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ORN_r" title="ORN, ORNS (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="T1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="T32" />
  </docvars>
  <heading>ORN, ORNS (register)</heading>
  <desc>
    <brief>
      <para>Bitwise OR NOT (register)</para>
    </brief>
    <authored>
      <para>Bitwise OR NOT (register) performs a bitwise (inclusive) OR of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="T1" oneof="1" id="iclass_t1" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/ORN_r/T1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ORN_r_T1_RRX" oneofinclass="4" oneof="4" label="ORN, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ORN" />
          <docvar key="mnemonic-shift-type" value="ORN-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ORN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="ORN_r_T1" oneofinclass="4" oneof="4" label="ORN, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ORN" />
          <docvar key="mnemonic-shift-type" value="ORN-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>ORN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="ORNS_r_T1_RRX" oneofinclass="4" oneof="4" label="ORNS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ORNS" />
          <docvar key="mnemonic-shift-type" value="ORNS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ORNS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="ORNS_r_T1" oneofinclass="4" oneof="4" label="ORNS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ORNS" />
          <docvar key="mnemonic-shift-type" value="ORNS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>ORNS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ORN_r/T1_A.txt" mylink="aarch32.instrs.ORN_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "MVN (register)";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm3:imm2);</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ORN_r_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORN_r_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORN_r_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORN_r_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORN_r_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORN_r_T1" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="ORN_r_T1" symboldefcount="1">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <intro>
          <para>Is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm3:imm2" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/ORN_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    (shifted, carry) = <a link="impl-aarch32.Shift_C.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift_C</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    result = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] OR NOT(shifted);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>    if setflags then</line>
<line>        PSTATE.N = result&lt;31&gt;;</line>
<line>        PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>        PSTATE.C = carry;</line>
<line>        // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="orr_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ORR_i" title="ORR, ORRS (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>ORR, ORRS (immediate)</heading>
  <desc>
    <brief>
      <para>Bitwise OR (immediate)</para>
    </brief>
    <authored>
      <para>Bitwise OR (immediate) performs a bitwise (inclusive) OR of a register value and an immediate value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the ORRS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. ARM deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The ORR variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The ORRS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/ORR_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="ORR_i_A1" oneofinclass="2" oneof="4" label="ORR" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ORR" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>ORR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="ORRS_i_A1" oneofinclass="2" oneof="4" label="ORRS" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ORRS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>ORRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ORR_i/A1_A.txt" mylink="aarch32.instrs.ORR_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = (S == '1');</line>
<line>(imm32, carry) = <a link="impl-aarch32.A32ExpandImm_C.2" file="shared_pseudocode.xml" hover="function: (bits(32), bit) A32ExpandImm_C(bits(12) imm12, bit carry_in)">A32ExpandImm_C</a>(imm12, PSTATE.C);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/ORR_i/T1_A.txt" tworows="1">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="ORR_i_T1" oneofinclass="2" oneof="4" label="ORR" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ORR" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>ORR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="ORRS_i_T1" oneofinclass="2" oneof="4" label="ORRS" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ORRS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>ORRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ORR_i/T1_A.txt" mylink="aarch32.instrs.ORR_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "MOV (immediate)";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = (S == '1');</line>
<line>(imm32, carry) = <a link="impl-aarch32.T32ExpandImm_C.2" file="shared_pseudocode.xml" hover="function: (bits(32), bit) T32ExpandImm_C(bits(12) imm12, bit carry_in)">T32ExpandImm_C</a>(i:imm3:imm8, PSTATE.C);</line>
<line>if d == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ORR_i_A1, ORR_i_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORR_i_A1, ORR_i_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORR_i_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the ORR variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the ORRS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORR_i_T1" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORR_i_A1" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORR_i_T1" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORR_i_A1" symboldefcount="1">
      <symbol link="sa_const_1">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: an immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORR_i_T1" symboldefcount="2">
      <symbol link="sa_const">&lt;const&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: an immediate value. See <xref linkend="BABGHAGA">Modified immediate constants in T32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/ORR_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    result = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] OR imm32;</line>
<line>    if d == 15 then          // Can only occur for A32 encoding</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.N = result&lt;31&gt;;</line>
<line>            PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>            PSTATE.C = carry;</line>
<line>            // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="orr_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ORR_r" title="ORR, ORRS (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>ORR, ORRS (register)</heading>
  <desc>
    <brief>
      <para>Bitwise OR (register)</para>
    </brief>
    <authored>
      <para>Bitwise OR (register) performs a bitwise (inclusive) OR of a register value and an optionally-shifted register value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the ORRS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. ARM deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The ORR variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The ORRS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
      <para>Related encodings: <xref linkend="T32.encoding_index.dpint_shiftr">Data-processing (shifted register)</xref></para>
    </encodingnotes>
    <syntaxnotes>
      <para>In T32 assembly:</para>
      <list type="unordered">
        <listitem><content>Outside an IT block, if <syntax>ORRS &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rd&gt;</syntax> is written with <syntax>&lt;Rd&gt;</syntax> and <syntax>&lt;Rn&gt;</syntax> both in the range R0-R7, it is assembled using encoding T1 as though <syntax>ORRS &lt;Rd&gt;, &lt;Rn&gt;</syntax> had been written.</content></listitem>
        <listitem><content>Inside an IT block, if <syntax>ORR&lt;c&gt; &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rd&gt;</syntax> is written with <syntax>&lt;Rd&gt;</syntax> and <syntax>&lt;Rn&gt;</syntax> both in the range R0-R7, it is assembled using encoding T1 as though <syntax>ORR&lt;c&gt; &lt;Rd&gt;, &lt;Rn&gt;</syntax> had been written.</content></listitem>
      </list>
      <para>To prevent either of these happening, use the <syntax>.W</syntax> qualifier.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/ORR_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ORR_r_A1_RRX" oneofinclass="4" oneof="9" label="ORR, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ORR" />
          <docvar key="mnemonic-shift-type" value="ORR-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ORR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="ORR_r_A1" oneofinclass="4" oneof="9" label="ORR, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ORR" />
          <docvar key="mnemonic-shift-type" value="ORR-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>ORR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="ORRS_r_A1_RRX" oneofinclass="4" oneof="9" label="ORRS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ORRS" />
          <docvar key="mnemonic-shift-type" value="ORRS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ORRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="ORRS_r_A1" oneofinclass="4" oneof="9" label="ORRS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ORRS" />
          <docvar key="mnemonic-shift-type" value="ORRS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>ORRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ORR_r/A1_A.txt" mylink="aarch32.instrs.ORR_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ORR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/ORR_r/T1_A.txt">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="4" name="op" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rdn" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="ORR_r_T1" oneofinclass="1" oneof="9" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ORR" />
        </docvars>
        <asmtemplate comment="Inside IT block"><text>ORR</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate comment="Outside IT block"><text>ORRS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ORR_r/T1_A.txt" mylink="aarch32.instrs.ORR_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdn);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>();</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/ORR_r/T2_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ORR_r_T2_RRX" oneofinclass="4" oneof="9" label="ORR, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ORR" />
          <docvar key="mnemonic-shift-type" value="ORR-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ORR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="ORR_r_T2" oneofinclass="4" oneof="9" label="ORR, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ORR" />
          <docvar key="mnemonic-shift-type" value="ORR-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Inside IT block, and &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>ORR</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>ORR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="ORRS_r_T2_RRX" oneofinclass="4" oneof="9" label="ORRS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ORRS" />
          <docvar key="mnemonic-shift-type" value="ORRS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ORRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="ORRS_r_T2" oneofinclass="4" oneof="9" label="ORRS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ORRS" />
          <docvar key="mnemonic-shift-type" value="ORRS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Outside IT block, and &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>ORRS.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>ORRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ORR_r/T2_A.txt" mylink="aarch32.instrs.ORR_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "Related encodings";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm3:imm2);</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ORR_r_A1, ORR_r_T1, ORR_r_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORR_r_A1, ORR_r_T1, ORR_r_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORR_r_T1" symboldefcount="1">
      <symbol link="sa_rdn">&lt;Rdn&gt;</symbol>
      <account encodedin="Rdn">
        <intro>
          <para>Is the first general-purpose source register and the destination register, encoded in the "Rdn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORR_r_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the ORR variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the ORRS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORR_r_T2" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORR_r_A1" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORR_r_T2" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORR_r_A1" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="ORR-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORR_r_T1, ORR_r_T2" symboldefcount="2">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORR_r_A1, ORR_r_T2" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="ORR_r_A1" symboldefcount="1">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORR_r_T2" symboldefcount="2">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm3:imm2" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/ORR_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    (shifted, carry) = <a link="impl-aarch32.Shift_C.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift_C</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    result = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] OR shifted;</line>
<line>    if d == 15 then          // Can only occur for A32 encoding</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.N = result&lt;31&gt;;</line>
<line>            PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>            PSTATE.C = carry;</line>
<line>            // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="orr_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ORR_rr" title="ORR, ORRS (register-shifted register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
  </docvars>
  <heading>ORR, ORRS (register-shifted register)</heading>
  <desc>
    <brief>
      <para>Bitwise OR (register-shifted register)</para>
    </brief>
    <authored>
      <para>Bitwise OR (register-shifted register) performs a bitwise (inclusive) OR of a register value and a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/ORR_rr/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ORRS_rr_A1" oneofinclass="2" oneof="2" label="Flag setting" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ORRS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>ORRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <encoding name="ORR_rr_A1" oneofinclass="2" oneof="2" label="Not flag setting" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ORR" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>ORR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ORR_rr/A1_A.txt" mylink="aarch32.instrs.ORR_rr.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);</line>
<line>setflags = (S == '1');  shift_t = <a link="impl-aarch32.DecodeRegShift.1" file="shared_pseudocode.xml" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</a>(stype);</line>
<line>if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ORR_rr_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORR_rr_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORR_rr_A1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORR_rr_A1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORR_rr_A1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ORR_rr_A1" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="ORR_rr_A1" symboldefcount="1">
      <symbol link="sa_rs">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/ORR_rr/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shift_n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[s]&lt;7:0&gt;);</line>
<line>    (shifted, carry) = <a link="impl-aarch32.Shift_C.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift_C</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    result = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] OR shifted;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>    if setflags then</line>
<line>        PSTATE.N = result&lt;31&gt;;</line>
<line>        PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>        PSTATE.C = carry;</line>
<line>        // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="pkh.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="PKH" title="PKHBT, PKHTB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>PKHBT, PKHTB</heading>
  <desc>
    <brief>
      <para>Pack Halfword</para>
    </brief>
    <authored>
      <para>Pack Halfword combines one halfword of its first operand with the other halfword of its shifted second operand.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/PKH/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="8" settings="8">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" name="tb" usename="1">
          <c></c>
        </box>
        <box hibit="5" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="PKHBT_A1" oneofinclass="2" oneof="4" label="PKHBT" bitdiffs="tb == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="PKHBT" />
        </docvars>
        <box hibit="6" width="1" name="tb">
          <c>0</c>
        </box>
        <asmtemplate><text>PKHBT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, LSL #</text><a link="sa_imm_1" hover="The shift to apply to the value read from {syntax{&lt;Rm&gt;}} (field &quot;imm5&quot;)">&lt;imm&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="PKHTB_A1" oneofinclass="2" oneof="4" label="PKHTB" bitdiffs="tb == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="PKHTB" />
        </docvars>
        <box hibit="6" width="1" name="tb">
          <c>1</c>
        </box>
        <asmtemplate><text>PKHTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ASR #</text><a link="sa_imm_1" hover="The shift to apply to the value read from {syntax{&lt;Rm&gt;}} (field &quot;imm5&quot;)">&lt;imm&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/PKH/A1_A.txt" mylink="aarch32.instrs.PKH.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  tbform = (tb == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(tb:'0', imm5);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/PKH/T1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" name="tb" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="T" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="PKHBT_T1" oneofinclass="2" oneof="4" label="PKHBT" bitdiffs="tb == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="PKHBT" />
        </docvars>
        <box hibit="5" width="1" name="tb">
          <c>0</c>
        </box>
        <asmtemplate comment="tbform == FALSE"><text>PKHBT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, LSL #</text><a link="sa_imm" hover="The shift to apply to the value read from {syntax{&lt;Rm&gt;}} (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="PKHTB_T1" oneofinclass="2" oneof="4" label="PKHTB" bitdiffs="tb == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="PKHTB" />
        </docvars>
        <box hibit="5" width="1" name="tb">
          <c>1</c>
        </box>
        <asmtemplate comment="tbform == TRUE"><text>PKHTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ASR #</text><a link="sa_imm" hover="The shift to apply to the value read from {syntax{&lt;Rm&gt;}} (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/PKH/T1_A.txt" mylink="aarch32.instrs.PKH.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if S == '1' || T == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  tbform = (tb == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(tb:'0', imm3:imm2);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="PKHBT_A1, PKHBT_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PKHBT_A1, PKHBT_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PKHBT_A1, PKHBT_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PKHBT_A1, PKHBT_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PKHBT_A1, PKHBT_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PKHBT_A1" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: the shift to apply to the value read from <syntax>&lt;Rm&gt;</syntax>, encoded in the "imm5" field.</para>
          <para>For <instruction>PKHBT</instruction>, it is one of:</para>
          <list type="param">
            <listitem>
              <param>omitted</param><content>No shift, encoded as <binarynumber>0b00000</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>1-31</param><content>Left shift by specified number of bits, encoded as a binary number.</content>
            </listitem>
          </list>
          <para>For <instruction>PKHTB</instruction>, it is one of:</para>
          <list type="param">
            <listitem>
              <param>omitted</param><content>Instruction is a pseudo-instruction and is assembled as though <instruction>PKHBT{&lt;c&gt;}{&lt;q&gt;} &lt;Rd&gt;, &lt;Rm&gt;, &lt;Rn&gt;</instruction> had been written.</content>
            </listitem>
            <listitem>
              <param>1-32</param><content>Arithmetic right shift by specified number of bits. A shift by 32 bits is encoded as <binarynumber>0b00000</binarynumber>. Other shift amounts are encoded as binary numbers.</content>
            </listitem>
          </list>
          <note>
            <para>An assembler can permit <syntax>&lt;imm&gt;</syntax> = 0 to mean the same thing as omitting the shift, but this is not standard UAL and must not be used for disassembly.</para>
          </note>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PKHBT_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: the shift to apply to the value read from <syntax>&lt;Rm&gt;</syntax>, encoded in the "imm3:imm2" field.</para>
          <para>For <instruction>PKHBT</instruction>, it is one of:</para>
          <list type="param">
            <listitem>
              <param>omitted</param><content>No shift, encoded as <binarynumber>0b00000</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>1-31</param><content>Left shift by specified number of bits, encoded as a binary number.</content>
            </listitem>
          </list>
          <para>For <instruction>PKHTB</instruction>, it is one of:</para>
          <list type="param">
            <listitem>
              <param>omitted</param><content>Instruction is a pseudo-instruction and is assembled as though <instruction>PKHBT{&lt;c&gt;}{&lt;q&gt;} &lt;Rd&gt;, &lt;Rm&gt;, &lt;Rn&gt;</instruction> had been written.</content>
            </listitem>
            <listitem>
              <param>1-32</param><content>Arithmetic right shift by specified number of bits. A shift by 32 bits is encoded as <binarynumber>0b00000</binarynumber>. Other shift amounts are encoded as binary numbers.</content>
            </listitem>
          </list>
          <note>
            <para>An assembler can permit <syntax>&lt;imm&gt;</syntax> = 0 to mean the same thing as omitting the shift, but this is not standard UAL and must not be used for disassembly.</para>
          </note>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/PKH/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    operand2 = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);  // PSTATE.C ignored</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = if tbform then operand2&lt;15:0&gt; else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = if tbform then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;    else operand2&lt;31:16&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="pld_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="PLD_i" title="PLD, PLDW (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>PLD, PLDW (immediate)</heading>
  <desc>
    <brief>
      <para>Preload Data (immediate)</para>
    </brief>
    <authored>
      <para>Preload Data (immediate) signals the memory system that data memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as preloading the cache line containing the specified address into the data cache.</para>
      <para>The <instruction>PLD</instruction> instruction signals that the likely memory access is a read, and the <instruction>PLDW</instruction> instruction signals that it is a write.</para>
      <para>The effect of a <instruction>PLD</instruction> or <instruction>PLDW</instruction> instruction is <arm-defined-word>implementation defined</arm-defined-word>.  For more information, see <xref linkend="CEGJJFCA">Preloading caches</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/PLD_i/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="D" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="R" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="PLD_i_A1" oneofinclass="2" oneof="6" label="Preload read" bitdiffs="R == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="PLD" />
          <docvar key="preload-type" value="pld" />
        </docvars>
        <box hibit="22" width="1" name="R">
          <c>1</c>
        </box>
        <asmtemplate><text>PLD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_2" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="PLDW_i_A1" oneofinclass="2" oneof="6" label="Preload write" bitdiffs="R == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="PLDW" />
          <docvar key="preload-type" value="pldw" />
        </docvars>
        <box hibit="22" width="1" name="R">
          <c>0</c>
        </box>
        <asmtemplate><text>PLDW</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_2" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/PLD_i/A1_A.txt" mylink="aarch32.instrs.PLD_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "PLD (literal)";</line>
<line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);  add = (U == '1');  is_pldw = (R == '0');</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/PLD_i/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="PLD_i_T1" oneofinclass="2" oneof="6" label="Preload read" bitdiffs="W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="PLD" />
          <docvar key="preload-type" value="pld" />
        </docvars>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>PLD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="PLDW_i_T1" oneofinclass="2" oneof="6" label="Preload write" bitdiffs="W == 1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="PLDW" />
          <docvar key="preload-type" value="pldw" />
        </docvars>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>PLDW</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/PLD_i/T1_A.txt" mylink="aarch32.instrs.PLD_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "PLD (literal)";</line>
<line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);  add = TRUE;  is_pldw = (W == '1');</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/PLD_i/T2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="PLD_i_T2" oneofinclass="2" oneof="6" label="Preload read" bitdiffs="W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="PLD" />
          <docvar key="preload-type" value="pld" />
        </docvars>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>PLD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #-</text><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="PLDW_i_T2" oneofinclass="2" oneof="6" label="Preload write" bitdiffs="W == 1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="PLDW" />
          <docvar key="preload-type" value="pldw" />
        </docvars>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>PLDW</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #-</text><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/PLD_i/T2_A.txt" mylink="aarch32.instrs.PLD_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "PLD (literal)";</line>
<line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);  add = FALSE;  is_pldw = (W == '1');</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="PLD_i_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. Must be <value>AL</value> or omitted.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLD_i_T1, PLD_i_T2" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLD_i_A1, PLD_i_T1, PLD_i_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLD_i_A1, PLD_i_T1, PLD_i_T2" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field. If the PC is used, see <xref linkend="A32T32-base.instructions.PLD_l">PLD (literal)</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLD_i_A1" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="PLD_i_T1" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the offset is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLD_i_A1" symboldefcount="1">
      <symbol link="sa_imm_2">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLD_i_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLD_i_T2" symboldefcount="3">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/PLD_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);</line>
<line>    if is_pldw then</line>
<line>        <a link="impl-aarch32.Hint_PreloadDataForWrite.1" file="shared_pseudocode.xml" hover="function: Hint_PreloadDataForWrite(bits(32) address)">Hint_PreloadDataForWrite</a>(address);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.Hint_PreloadData.1" file="shared_pseudocode.xml" hover="function: Hint_PreloadData(bits(32) address)">Hint_PreloadData</a>(address);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="pld_l.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="PLD_l" title="PLD (literal) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="PLD" />
  </docvars>
  <heading>PLD (literal)</heading>
  <desc>
    <brief>
      <para>Preload Data (literal)</para>
    </brief>
    <authored>
      <para>Preload Data (literal) signals the memory system that data memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as preloading the cache line containing the specified address into the data cache.</para>
      <para>The effect of a <instruction>PLD</instruction> instruction is <arm-defined-word>implementation defined</arm-defined-word>.  For more information, see <xref linkend="CEGJJFCA">Preloading caches</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>The alternative syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see <xref linkend="BABGCIBA">Use of labels in UAL instruction syntax</xref>.</para>
    </syntaxnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="PLD" />
        <docvar key="preload-type" value="pld" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/PLD_l/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="D" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="R" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="PLD_l_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="PLD" />
          <docvar key="preload-type" value="pld" />
        </docvars>
        <asmtemplate comment="Normal form"><text>PLD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_label" hover="The label of literal data item that is likely to be accessed in the near future">&lt;label&gt;</a></asmtemplate>
        <asmtemplate comment="Alternative form"><text>PLD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/PLD_l/A1_A.txt" mylink="aarch32.instrs.PLD_l.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);  add = (U == '1');</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="literal" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="PLD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/PLD_l/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rt" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="PLD_l_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="PLD" />
        </docvars>
        <asmtemplate comment="Preferred syntax"><text>PLD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_label" hover="The label of literal data item that is likely to be accessed in the near future">&lt;label&gt;</a></asmtemplate>
        <asmtemplate comment="Alternative syntax"><text>PLD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/PLD_l/T1_A.txt" mylink="aarch32.instrs.PLD_l.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);  add = (U == '1');</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="PLD_l_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="preload-type" value="pld" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. Must be <value>AL</value> or omitted.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLD_l_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLD_l_A1, PLD_l_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLD_l_A1, PLD_l_T1" symboldefcount="1">
      <symbol link="sa_label">&lt;label&gt;</symbol>
      <account encodedin="imm12">
        <intro>
          <para>The label of the literal data item that is likely to be accessed in the near future. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the instruction to this label. The offset must be in the range –4095 to 4095.</para>
          <para>If the offset is zero or positive, <field>imm32</field> is equal to the offset and <field>add</field> == <enumvalue>TRUE</enumvalue>.</para>
          <para>If the offset is negative, <field>imm32</field> is equal to minus the offset and <field>add</field> == <enumvalue>FALSE</enumvalue>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLD_l_A1, PLD_l_T1" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="PLD_l_A1" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="preload-type" value="pld" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 12-bit unsigned immediate byte offset, in the range 0 to 4095, encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLD_l_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is a 12-bit unsigned immediate byte offset, in the range 0 to 4095, encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/PLD_l/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = if add then (<a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4) + imm32) else (<a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4) - imm32);</line>
<line>    <a link="impl-aarch32.Hint_PreloadData.1" file="shared_pseudocode.xml" hover="function: Hint_PreloadData(bits(32) address)">Hint_PreloadData</a>(address);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="pld_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="PLD_r" title="PLD, PLDW (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>PLD, PLDW (register)</heading>
  <desc>
    <brief>
      <para>Preload Data (register)</para>
    </brief>
    <authored>
      <para>Preload Data (register) signals the memory system that data memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as preloading the cache line containing the specified address into the data cache.</para>
      <para>The <instruction>PLD</instruction> instruction signals that the likely memory access is a read, and the <instruction>PLDW</instruction> instruction signals that it is a write.</para>
      <para>The effect of a <instruction>PLD</instruction> or <instruction>PLDW</instruction> instruction is <arm-defined-word>implementation defined</arm-defined-word>.  For more information, see <xref linkend="CEGJJFCA">Preloading caches</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/PLD_r/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="24" name="D" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="R" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="PLD_r_A1" oneofinclass="4" oneof="6" label="Preload read, optional shift or rotate" bitdiffs="R == 1 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="PLD" />
          <docvar key="preload-type-shift-type" value="pld-shift-no-rrx" />
        </docvars>
        <box hibit="22" width="1" name="R">
          <c>1</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>PLD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to index register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="PLD_r_A1_RRX" oneofinclass="4" oneof="6" label="Preload read, rotate right with extend" bitdiffs="R == 1 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="PLD" />
          <docvar key="preload-type-shift-type" value="pld-rrx" />
        </docvars>
        <box hibit="22" width="1" name="R">
          <c>1</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>PLD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> , RRX]</text></asmtemplate>
      </encoding>
      <encoding name="PLDW_r_A1" oneofinclass="4" oneof="6" label="Preload write, optional shift or rotate" bitdiffs="R == 0 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="PLDW" />
          <docvar key="preload-type-shift-type" value="pldw-shift-no-rrx" />
        </docvars>
        <box hibit="22" width="1" name="R">
          <c>0</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>PLDW</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to index register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="PLDW_r_A1_RRX" oneofinclass="4" oneof="6" label="Preload write, rotate right with extend" bitdiffs="R == 0 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="PLDW" />
          <docvar key="preload-type-shift-type" value="pldw-rrx" />
        </docvars>
        <box hibit="22" width="1" name="R">
          <c>0</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>PLDW</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> , RRX]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/PLD_r/A1_A.txt" mylink="aarch32.instrs.PLD_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  add = (U == '1');  is_pldw = (R == '0');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
<line>if m == 15 || (n == 15 &amp;&amp; is_pldw) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="address-form" value="register-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/PLD_r/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="6" settings="6">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="PLD_r_T1" oneofinclass="2" oneof="6" label="Preload read" bitdiffs="W == 0">
        <docvars>
          <docvar key="address-form" value="register-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="PLD" />
          <docvar key="preload-type" value="pld" />
        </docvars>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>PLD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, LSL #</text><a link="sa_amount" hover="Shift amount [0-3], default 0 (field &quot;imm2&quot;)">&lt;amount&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="PLDW_r_T1" oneofinclass="2" oneof="6" label="Preload write" bitdiffs="W == 1">
        <docvars>
          <docvar key="address-form" value="register-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="PLDW" />
          <docvar key="preload-type" value="pldw" />
        </docvars>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>PLDW</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, LSL #</text><a link="sa_amount" hover="Shift amount [0-3], default 0 (field &quot;imm2&quot;)">&lt;amount&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/PLD_r/T1_A.txt" mylink="aarch32.instrs.PLD_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "PLD (literal)";</line>
<line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  add = TRUE;  is_pldw = (W == '1');</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm2));</line>
<line>if m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="PLD_r_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="preload-type-shift-type" value="pld-shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. <syntax>&lt;c&gt;</syntax> must be <value>AL</value> or omitted.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLD_r_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="address-form" value="register-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
          <docvar key="preload-type" value="pld" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLD_r_A1, PLD_r_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLD_r_A1" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="preload-type-shift-type" value="pld-shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be used.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLD_r_T1" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="address-form" value="register-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
          <docvar key="preload-type" value="pld" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLD_r_A1" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="PLD_r_T1" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the index register is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLD_r_A1, PLD_r_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLD_r_A1" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the index register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="PLD_r_A1" symboldefcount="1">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="preload-type-shift-type" value="pld-shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLD_r_T1" symboldefcount="2">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm2">
        <docvars>
          <docvar key="address-form" value="register-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
          <docvar key="preload-type" value="pld" />
        </docvars>
        <intro>
          <para>For encoding T1: is the shift amount, in the range 0 to 3, defaulting to 0 and encoded in the "imm2" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/PLD_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    offset = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    address = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + offset) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - offset);</line>
<line>    if is_pldw then</line>
<line>        <a link="impl-aarch32.Hint_PreloadDataForWrite.1" file="shared_pseudocode.xml" hover="function: Hint_PreloadDataForWrite(bits(32) address)">Hint_PreloadDataForWrite</a>(address);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.Hint_PreloadData.1" file="shared_pseudocode.xml" hover="function: Hint_PreloadData(bits(32) address)">Hint_PreloadData</a>(address);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="pli_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="PLI_i" title="PLI (immediate, literal) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="PLI" />
  </docvars>
  <heading>PLI (immediate, literal)</heading>
  <desc>
    <brief>
      <para>Preload Instruction (immediate, literal)</para>
    </brief>
    <authored>
      <para>Preload Instruction signals the memory system that instruction memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as pre-loading the cache line containing the specified address into the instruction cache.</para>
      <para>The effect of a <instruction>PLI</instruction> instruction is <arm-defined-word>implementation defined</arm-defined-word>. For more information, see <xref linkend="CEGJJFCA">Preloading caches</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For the literal forms of the instruction, encoding T3 is used, or Rn is encoded as <binarynumber>0b1111</binarynumber> in encoding A1, to indicate that the PC is the base register.</para>
      <para>The alternative literal syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see <xref linkend="BABGCIBA">Use of labels in UAL instruction syntax</xref>.</para>
    </syntaxnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="PLI" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/PLI_i/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="D" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="R" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="PLI_i_A1" oneofinclass="1" oneof="4" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="PLI" />
        </docvars>
        <asmtemplate><text>PLI</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_3" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
        <asmtemplate comment="Normal form"><text>PLI</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_label" hover="The label of instruction that is likely to be accessed in the near future">&lt;label&gt;</a></asmtemplate>
        <asmtemplate comment="Alternative form"><text>PLI</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_3" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/PLI_i/A1_A.txt" mylink="aarch32.instrs.PLI_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);  add = (U == '1');</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="PLI" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/PLI_i/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="PLI_i_T1" oneofinclass="1" oneof="4" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="PLI" />
        </docvars>
        <asmtemplate><text>PLI</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/PLI_i/T1_A.txt" mylink="aarch32.instrs.PLI_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "encoding T3";</line>
<line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);  add = TRUE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="PLI" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/PLI_i/T2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="PLI_i_T2" oneofinclass="1" oneof="4" label="T2">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="PLI" />
        </docvars>
        <asmtemplate><text>PLI</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #-</text><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/PLI_i/T2_A.txt" mylink="aarch32.instrs.PLI_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "encoding T3";</line>
<line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);  add = FALSE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T3" oneof="4" id="iclass_t3" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="literal" />
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="PLI" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/PLI_i/T3_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rt" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="PLI_i_T3" oneofinclass="1" oneof="4" label="T3">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="PLI" />
        </docvars>
        <asmtemplate comment="Preferred syntax"><text>PLI</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_label" hover="The label of instruction that is likely to be accessed in the near future">&lt;label&gt;</a></asmtemplate>
        <asmtemplate comment="Alternative syntax"><text>PLI</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_2" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/PLI_i/T3_A.txt" mylink="aarch32.instrs.PLI_i.T3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = 15;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);  add = (U == '1');</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="PLI_i_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. Must be <value>AL</value> or omitted.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_i_T1, PLI_i_T2, PLI_i_T3" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1, T2 and T3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_i_A1, PLI_i_T1, PLI_i_T2, PLI_i_T3" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_i_A1, PLI_i_T3" symboldefcount="1">
      <symbol link="sa_label">&lt;label&gt;</symbol>
      <account encodedin="imm12">
        <intro>
          <para>The label of the instruction that is likely to be accessed in the near future. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the instruction to this label. The offset must be in the range –4095 to 4095.</para>
          <para>If the offset is zero or positive, <field>imm32</field> is equal to the offset and <field>add</field> == <enumvalue>TRUE</enumvalue>.</para>
          <para>If the offset is negative, <field>imm32</field> is equal to minus the offset and <field>add</field> == <enumvalue>FALSE</enumvalue>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_i_A1, PLI_i_T1, PLI_i_T2" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_i_A1, PLI_i_T3" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="PLI_i_T1" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the offset is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_i_A1" symboldefcount="1">
      <symbol link="sa_imm_3">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_i_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_i_T2" symboldefcount="3">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_i_T3" symboldefcount="4">
      <symbol link="sa_imm_2">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3: is a 12-bit unsigned immediate byte offset, in the range 0 to 4095, encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/PLI_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    base = if n == 15 then <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4) else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    address = if add then (base + imm32) else (base - imm32);</line>
<line>    <a link="impl-aarch32.Hint_PreloadInstr.1" file="shared_pseudocode.xml" hover="function: Hint_PreloadInstr(bits(32) address)">Hint_PreloadInstr</a>(address);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="pli_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="PLI_r" title="PLI (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="PLI" />
  </docvars>
  <heading>PLI (register)</heading>
  <desc>
    <brief>
      <para>Preload Instruction (register)</para>
    </brief>
    <authored>
      <para>Preload Instruction signals the memory system that instruction memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as pre-loading the cache line containing the specified address into the instruction cache.</para>
      <para>The effect of a <instruction>PLI</instruction> instruction is <arm-defined-word>implementation defined</arm-defined-word>. For more information, see <xref linkend="CEGJJFCA">Preloading caches</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="PLI" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/PLI_r/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="24" name="D" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="PLI_r_A1_RRX" oneofinclass="2" oneof="3" label="Rotate right with extend" bitdiffs="imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="PLI" />
          <docvar key="mnemonic-shift-type" value="PLI-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>PLI</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> , RRX]</text></asmtemplate>
      </encoding>
      <encoding name="PLI_r_A1" oneofinclass="2" oneof="3" label="Shift or rotate by value" bitdiffs="!(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="PLI" />
          <docvar key="mnemonic-shift-type" value="PLI-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>PLI</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to index register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/PLI_r/A1_A.txt" mylink="aarch32.instrs.PLI_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  add = (U == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
<line>if m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="register-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="PLI" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/PLI_r/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="6" settings="6">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="PLI_r_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="address-form" value="register-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="PLI" />
        </docvars>
        <asmtemplate><text>PLI</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, LSL #</text><a link="sa_amount" hover="Shift amount [0-3], default 0 (field &quot;imm2&quot;)">&lt;amount&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/PLI_r/T1_A.txt" mylink="aarch32.instrs.PLI_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "PLI (immediate, literal)";</line>
<line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  add = TRUE;</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm2));</line>
<line>if m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="PLI_r_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="PLI-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. <syntax>&lt;c&gt;</syntax> must be <value>AL</value> or omitted.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_r_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="address-form" value="register-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_r_A1, PLI_r_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_r_A1, PLI_r_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_r_A1" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="PLI_r_T1" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the index register is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_r_A1, PLI_r_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_r_A1" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the index register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="PLI_r_A1" symboldefcount="1">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="PLI-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_r_T1" symboldefcount="2">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm2">
        <docvars>
          <docvar key="address-form" value="register-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the shift amount, in the range 0 to 3, defaulting to 0 and encoded in the "imm2" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/PLI_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    offset = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    address = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + offset) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - offset);</line>
<line>    <a link="impl-aarch32.Hint_PreloadInstr.1" file="shared_pseudocode.xml" hover="function: Hint_PreloadInstr(bits(32) address)">Hint_PreloadInstr</a>(address);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="pop.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="POP" title="POP -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="T1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="T32" />
    <docvar key="mnemonic" value="POP" />
  </docvars>
  <heading>POP</heading>
  <desc>
    <brief>
      <para>Pop Multiple Registers from Stack</para>
    </brief>
    <authored>
      <para>Pop Multiple Registers from Stack loads multiple general-purpose registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data.</para>
      <para>The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register from the highest memory address. See also <xref linkend="CHDDBEDG">Encoding of lists of general-purpose registers and the PC</xref>.</para>
      <para>The registers loaded can include the PC, causing a branch to a loaded address. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="T1" oneof="1" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="POP" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/POP/T1_A.txt">
        <box hibit="31" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="27" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="26" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" width="8" name="register_list" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="POP_T1" oneofinclass="1" oneof="1" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="POP" />
        </docvars>
        <asmtemplate comment="Preferred syntax"><text>POP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_registers" hover="List of one or more registers to be loaded (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate comment="Alternate syntax"><text>LDM</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> SP!, </text><a link="sa_registers" hover="List of one or more registers to be loaded (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/POP/T1_A.txt" mylink="aarch32.instrs.POP.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>registers = P:'0000000':register_list;   UnalignedAllowed = FALSE;</line>
<line>if <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) &lt; 1 then UNPREDICTABLE;</line>
<line>if registers&lt;15&gt; == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>BitCount(registers) &lt; 1</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction targets an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers loaded.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="POP_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="POP_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="POP_T1" symboldefcount="1">
      <symbol link="sa_registers">&lt;registers&gt;</symbol>
      <account encodedin="register_list">
        <intro>
          <para>Is a list of one or more registers to be loaded, separated by commas and surrounded by { and }.</para>
          <para>The registers in the list must be in the range R0-R7, encoded in the "register_list" field, and can optionally include the PC. If the PC is in the list, the "P" field is set to 1, otherwise this field defaults to 0.</para>
          <para>If the PC is in the list, the instruction must be either outside any IT block, or the last instruction in an IT block.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/POP/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[13];</line>
<line>    for i = 0 to 14</line>
<line>        if registers&lt;i&gt; == '1' then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[i] = if UnalignedAllowed then <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,4] else <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,4];</line>
<line>            address = address + 4;</line>
<line>    if registers&lt;15&gt; == '1' then</line>
<line>        if UnalignedAllowed then</line>
<line>            if address&lt;1:0&gt; == '00' then</line>
<line>                <a link="impl-aarch32.LoadWritePC.1" file="shared_pseudocode.xml" hover="function: LoadWritePC(bits(32) address)">LoadWritePC</a>(<a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,4]);</line>
<line>            else</line>
<line>                UNPREDICTABLE;</line>
<line>        else</line>
<line>            <a link="impl-aarch32.LoadWritePC.1" file="shared_pseudocode.xml" hover="function: LoadWritePC(bits(32) address)">LoadWritePC</a>(<a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,4]);</line>
<line>    if registers&lt;13&gt; == '0' then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[13] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[13] + 4*<a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers);</line>
<line>    if registers&lt;13&gt; == '1' then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[13] = bits(32) UNKNOWN;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="pop_ldm.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="POP_LDM" title="POP (multiple registers) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="POP" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDM" />
  </docvars>
  <heading>POP (multiple registers)</heading>
  <desc>
    <brief>Pop Multiple Registers from Stack</brief>
    <longer> loads multiple general-purpose registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data</longer>
  </desc>
  <aliasto refiform="ldm.xml" iformid="LDM">LDM, LDMIA, LDMFD</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1" settings="1" psbits="1">
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="16" name="register_list" usename="1">
          <c colspan="16"></c>
        </box>
      </regdiagram>
      <encoding name="POP_LDM_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="alias_mnemonic" value="POP" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDM" />
        </docvars>
        <asmtemplate><text>POP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_registers_4" hover="List of two or more registers to be loaded">&lt;registers&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="ldm.xml#LDM_A1">LDM</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> SP!, </text><a link="sa_registers_4" hover="List of two or more registers to be loaded">&lt;registers&gt;</a></asmtemplate>
          <aliascond><a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(register_list) &gt; 1</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="2" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1" settings="1" psbits="1">
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="14" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="13" width="14" name="register_list" usename="1">
          <c colspan="14"></c>
        </box>
      </regdiagram>
      <encoding name="POP_LDM_T2" oneofinclass="1" oneof="2" label="T2">
        <docvars>
          <docvar key="alias_mnemonic" value="POP" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDM" />
        </docvars>
        <asmtemplate comment="All registers in R0-R7, PC"><text>POP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_registers_3" hover="List of two or more registers to be loaded (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate><text>POP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_registers_3" hover="List of two or more registers to be loaded (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="ldm.xml#LDM_T2">LDM</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> SP!, </text><a link="sa_registers_3" hover="List of two or more registers to be loaded (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
          <aliascond><a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(P:M:register_list) &gt; 1</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="POP_LDM_A1, POP_LDM_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="POP_LDM_A1, POP_LDM_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="POP_LDM_A1" symboldefcount="1">
      <symbol link="sa_registers_4">&lt;registers&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: is a list of two or more registers to be loaded, separated by commas and surrounded by { and }. The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register from the highest memory address. See also <xref linkend="CHDDBEDG">Encoding of lists of general-purpose registers and the PC</xref>.</para>
          <para>If the SP is in the list, the value of the SP after such an instruction is <arm-defined-word>unknown</arm-defined-word>.</para>
          <para>The PC can be in the list. If it is, the instruction branches to the address loaded to the PC. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
          <para>Arm deprecates the use of this instruction with both the LR and the PC in the list.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="POP_LDM_T2" symboldefcount="2">
      <symbol link="sa_registers_3">&lt;registers&gt;</symbol>
      <account encodedin="register_list">
        <docvars>
          <docvar key="armarmheading" value="T2" />
        </docvars>
        <intro>
          <para>For encoding T2: is a list of two or more registers to be loaded, separated by commas and surrounded by { and }. The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register from the highest memory address. See also <xref linkend="CHDDBEDG">Encoding of lists of general-purpose registers and the PC</xref>.</para>
          <para>The registers in the list must be in the range R0-R12, encoded in the "register_list" field, and can optionally contain one of  the LR or the PC. If the LR is in the list, the "M" field is set to 1, otherwise it defaults to 0. If the PC is in the list, the "P" field is set to 1, otherwise it defaults to 0.</para>
          <para>The PC can be in the list. If it is, the instruction branches to the address loaded to the PC. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>. If the PC is in the list:</para>
          <list type="unordered">
            <listitem><content>The LR must not be in the list.</content></listitem>
            <listitem><content>The instruction must be either outside any IT block, or the last instruction in an IT block.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="pop_ldr_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="POP_LDR_i" title="POP (single register) -- AArch32" type="alias">
  <docvars>
    <docvar key="address-form" value="post-indexed" />
    <docvar key="alias_mnemonic" value="POP" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="LDR" />
  </docvars>
  <heading>POP (single register)</heading>
  <desc>
    <brief>Pop Single Register from Stack</brief>
    <longer> loads a single general-purpose register from the stack, loading from the address in SP, and updates SP to point just above the loaded data</longer>
  </desc>
  <aliasto refiform="ldr_i.xml" iformid="LDR_i">LDR (immediate)</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t4">T4</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="LDR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1" settings="12">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="POP_LDR_i_A1_post" oneofinclass="1" oneof="2" label="Post-indexed">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="alias_mnemonic" value="POP" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="LDR" />
        </docvars>
        <asmtemplate><text>POP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_single_register_list" hover="General-purpose register {syntax{&lt;Rt&gt;}} to be loaded surrounded by { and }">&lt;single_register_list&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="ldr_i.xml#LDR_i_A1_post">LDR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_2" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [SP], #4</text></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T4" oneof="2" id="iclass_t4" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T4" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="LDR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="P" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" name="U" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="W" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1" settings="8">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="POP_LDR_i_T4_post" oneofinclass="1" oneof="2" label="Post-indexed">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="alias_mnemonic" value="POP" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="LDR" />
        </docvars>
        <asmtemplate><text>POP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_single_register_list" hover="General-purpose register {syntax{&lt;Rt&gt;}} to be loaded surrounded by { and }">&lt;single_register_list&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="ldr_i.xml#LDR_i_T4_post">LDR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [SP], #4</text></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="POP_LDR_i_A1_post, POP_LDR_i_T4_post" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="POP_LDR_i_A1_post, POP_LDR_i_T4_post" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="POP_LDR_i_A1_post, POP_LDR_i_T4_post" symboldefcount="1">
      <symbol link="sa_single_register_list">&lt;single_register_list&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the general-purpose register <syntax>&lt;Rt&gt;</syntax> to be loaded surrounded by { and }.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="POP_LDR_i_A1_post" symboldefcount="1">
      <symbol link="sa_rt_2">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used. If the PC is used, the instruction branches to the address (data) loaded to the PC. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="POP_LDR_i_T4_post" symboldefcount="2">
      <symbol link="sa_rt_1">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="armarmheading" value="T4" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T4: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used, provided the instruction is either outside an IT block or the last instruction of an IT block. If the PC is used, the instruction branches to the address (data) loaded to the PC. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="pssbb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="PSSBB" title="PSSBB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="PSSBB" />
  </docvars>
  <heading>PSSBB</heading>
  <desc>
    <brief>
      <para>Physical Speculative Store Bypass Barrier</para>
    </brief>
    <authored>
      <para>Physical Speculative Store Bypass Barrier is a memory barrier which prevents speculative loads from bypassing earlier stores to the same physical address.</para>
      <para>The semantics of the Physical Speculative Store Bypass Barrier are:</para>
      <list type="unordered">
        <listitem><content>When a load to a location appears in program order after the PSSBB, then the load does not speculatively read an entry earlier in the coherence order for that location than the entry generated by the latest store satisfying all of the following conditions:<list type="unordered"><listitem><content>The store is to the same location as the load.</content></listitem><listitem><content>The store appears in program order before the PSSBB.</content></listitem></list></content></listitem>
        <listitem><content>When a load to a location appears in program order before the PSSBB, then the load does not speculatively read data from any store satisfying all of the following conditions:<list type="unordered"><listitem><content>The store is to the same location as the load.</content></listitem><listitem><content>The store appears in program order after the PSSBB.</content></listitem></list></content></listitem>
      </list>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="PSSBB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/PSSBB/A1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" name="opcode" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="option" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="PSSBB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="PSSBB" />
        </docvars>
        <asmtemplate><text>PSSBB</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/PSSBB/A1_A.txt" mylink="aarch32.instrs.PSSBB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="PSSBB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/PSSBB/T1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="option" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="PSSBB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="PSSBB" />
        </docvars>
        <asmtemplate><text>PSSBB</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/PSSBB/T1_A.txt" mylink="aarch32.instrs.PSSBB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="PSSBB_A1, PSSBB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/PSSBB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-shared.SpeculativeStoreBypassBarrierToPA.0" file="shared_pseudocode.xml" hover="function: SpeculativeStoreBypassBarrierToPA()">SpeculativeStoreBypassBarrierToPA</a>();</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="push.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="PUSH" title="PUSH -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="T1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="T32" />
    <docvar key="mnemonic" value="PUSH" />
  </docvars>
  <heading>PUSH</heading>
  <desc>
    <brief>
      <para>Push Multiple Registers to Stack</para>
    </brief>
    <authored>
      <para>Push Multiple Registers to Stack stores multiple general-purpose registers to the stack, storing to consecutive memory locations ending just below the address in SP, and updates SP to point to the start of the stored data.</para>
      <para>The lowest-numbered register is stored to the lowest memory address, through to the highest-numbered register to the highest memory address. See also <xref linkend="CHDDBEDG">Encoding of lists of general-purpose registers and the PC</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="T1" oneof="1" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="PUSH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/PUSH/T1_A.txt">
        <box hibit="31" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="27" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="26" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="23" width="8" name="register_list" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="PUSH_T1" oneofinclass="1" oneof="1" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="PUSH" />
        </docvars>
        <asmtemplate comment="Preferred syntax"><text>PUSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_registers" hover="List of one or more registers to be stored (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate comment="Alternate syntax"><text>STMDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> SP!, </text><a link="sa_registers" hover="List of one or more registers to be stored (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/PUSH/T1_A.txt" mylink="aarch32.instrs.PUSH.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>registers = '0':M:'000000':register_list;  UnalignedAllowed = FALSE;</line>
<line>if <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) &lt; 1 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>BitCount(registers) &lt; 1</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction targets an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers loaded.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="PUSH_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PUSH_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PUSH_T1" symboldefcount="1">
      <symbol link="sa_registers">&lt;registers&gt;</symbol>
      <account encodedin="register_list">
        <intro>
          <para>Is a list of one or more registers to be stored, separated by commas and surrounded by { and }.</para>
          <para>The registers in the list must be in the range R0-R7, encoded in the "register_list" field, and can optionally include the LR. If the LR is in the list, the "M" field is set to 1, otherwise this field defaults to 0.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/PUSH/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[13] - 4*<a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers);</line>
<line>    for i = 0 to 14</line>
<line>        if registers&lt;i&gt; == '1' then</line>
<line>            if i == 13 &amp;&amp; i != <a link="impl-shared.LowestSetBit.1" file="shared_pseudocode.xml" hover="function: integer LowestSetBit(bits(N) x)">LowestSetBit</a>(registers) then  // Only possible for encoding A1</line>
<line>                <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,4] = bits(32) UNKNOWN;</line>
<line>            else</line>
<line>                if UnalignedAllowed then</line>
<line>                    <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,4] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[i];</line>
<line>                else</line>
<line>                    <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,4] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[i];</line>
<line>            address = address + 4;</line>
<line>    if registers&lt;15&gt; == '1' then  // Only possible for encoding A1 or A2</line>
<line>        if UnalignedAllowed then</line>
<line>            <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,4] = <a link="impl-aarch32.PCStoreValue.0" file="shared_pseudocode.xml" hover="function: bits(32) PCStoreValue()">PCStoreValue</a>();</line>
<line>        else</line>
<line>            <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,4] = <a link="impl-aarch32.PCStoreValue.0" file="shared_pseudocode.xml" hover="function: bits(32) PCStoreValue()">PCStoreValue</a>();</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[13] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[13] - 4*<a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="push_stmdb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="PUSH_STMDB" title="PUSH (multiple registers) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="PUSH" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STM" />
  </docvars>
  <heading>PUSH (multiple registers)</heading>
  <desc>
    <brief>Push multiple registers to Stack</brief>
    <longer> stores multiple general-purpose registers to the stack, storing to consecutive memory locations ending just below the address in SP, and updates SP to point to the start of the stored data</longer>
  </desc>
  <aliasto refiform="stmdb.xml" iformid="STMDB">STMDB, STMFD</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1" settings="1" psbits="1">
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="16" name="register_list" usename="1">
          <c colspan="16"></c>
        </box>
      </regdiagram>
      <encoding name="PUSH_STMDB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="alias_mnemonic" value="PUSH" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STM" />
        </docvars>
        <asmtemplate><text>PUSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_registers_3" hover="List of two or more registers to be stored">&lt;registers&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="stmdb.xml#STMDB_A1">STMDB</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> SP!, </text><a link="sa_registers_3" hover="List of two or more registers to be stored">&lt;registers&gt;</a></asmtemplate>
          <aliascond><a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(register_list) &gt; 1</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="opc" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1" settings="1" psbits="1">
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" name="P" usename="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="13" width="14" name="register_list" usename="1">
          <c colspan="14"></c>
        </box>
      </regdiagram>
      <encoding name="PUSH_STMDB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="alias_mnemonic" value="PUSH" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STM" />
        </docvars>
        <asmtemplate comment="All registers in R0-R7, LR"><text>PUSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_registers_2" hover="List of one or more registers to be stored (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate><text>PUSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_registers_2" hover="List of one or more registers to be stored (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="stmdb.xml#STMDB_T1">STMDB</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> SP!, </text><a link="sa_registers_2" hover="List of one or more registers to be stored (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
          <aliascond><a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(M:register_list) &gt; 1</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="PUSH_STMDB_A1, PUSH_STMDB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PUSH_STMDB_A1, PUSH_STMDB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PUSH_STMDB_A1" symboldefcount="1">
      <symbol link="sa_registers_3">&lt;registers&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: is a list of two or more registers to be stored, separated by commas and surrounded by { and }. The lowest-numbered register is stored to the lowest memory address, through to the highest-numbered register to the highest memory address. See also <xref linkend="CHDDBEDG">Encoding of lists of general-purpose registers and the PC</xref>.</para>
          <para>The SP and PC can be in the list. However:</para>
          <list type="unordered">
            <listitem><content>Arm deprecates the use of instructions that include the PC in the list.</content></listitem>
            <listitem><content>If the SP is in the list, and it is not the lowest-numbered register in the list, the instruction stores an <arm-defined-word>unknown</arm-defined-word> value for the SP.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PUSH_STMDB_T1" symboldefcount="2">
      <symbol link="sa_registers_2">&lt;registers&gt;</symbol>
      <account encodedin="register_list">
        <docvars>
          <docvar key="armarmheading" value="T1" />
        </docvars>
        <intro>
          <para>For encoding T1: is a list of one or more registers to be stored, separated by commas and surrounded by { and }. The lowest-numbered register is stored to the lowest memory address, through to the highest-numbered register to the highest memory address. See also <xref linkend="CHDDBEDG">Encoding of lists of general-purpose registers and the PC</xref>.</para>
          <para>The registers in the list must be in the range R0-R12, encoded in the "register_list" field, and can optionally contain the LR. If the LR is in the list, the "M" field is set to 1, otherwise it defaults to 0.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="push_str_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="PUSH_STR_i" title="PUSH (single register) -- AArch32" type="alias">
  <docvars>
    <docvar key="address-form" value="pre-indexed" />
    <docvar key="alias_mnemonic" value="PUSH" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STR" />
  </docvars>
  <heading>PUSH (single register)</heading>
  <desc>
    <brief>Push Single Register to Stack</brief>
    <longer> stores a single general-purpose register to the stack, storing to the 32-bit word below the address in SP, and updates SP to point to the start of the stored data</longer>
  </desc>
  <aliasto refiform="str_i.xml" iformid="STR_i">STR (immediate)</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t4">T4</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1" settings="12">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="PUSH_STR_i_A1_pre" oneofinclass="1" oneof="2" label="Pre-indexed">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="alias_mnemonic" value="PUSH" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <asmtemplate><text>PUSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_single_register_list" hover="General-purpose register {syntax{&lt;Rt&gt;}} to be stored surrounded by { and }">&lt;single_register_list&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="str_i.xml#STR_i_A1_pre">STR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [SP, #-4]!</text></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T4" oneof="2" id="iclass_t4" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T4" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="P" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="W" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1" settings="8">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="PUSH_STR_i_T4_pre" oneofinclass="1" oneof="2" label="Pre-indexed">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="alias_mnemonic" value="PUSH" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <asmtemplate comment="Standard syntax"><text>PUSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_single_register_list" hover="General-purpose register {syntax{&lt;Rt&gt;}} to be stored surrounded by { and }">&lt;single_register_list&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="str_i.xml#STR_i_T4_pre">STR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [SP, #-4]!</text></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="PUSH_STR_i_A1_pre, PUSH_STR_i_T4_pre" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PUSH_STR_i_A1_pre, PUSH_STR_i_T4_pre" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PUSH_STR_i_A1_pre, PUSH_STR_i_T4_pre" symboldefcount="1">
      <symbol link="sa_single_register_list">&lt;single_register_list&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the general-purpose register <syntax>&lt;Rt&gt;</syntax> to be stored surrounded by { and }.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PUSH_STR_i_A1_pre" symboldefcount="1">
      <symbol link="sa_rt_1">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PUSH_STR_i_T4_pre" symboldefcount="2">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="armarmheading" value="T4" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T4: is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="qadd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="QADD" title="QADD -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="QADD" />
  </docvars>
  <heading>QADD</heading>
  <desc>
    <brief>
      <para>Saturating Add</para>
    </brief>
    <authored>
      <para>Saturating Add adds two register values, saturates the result to the 32-bit signed integer range -2<sup>31</sup> to (2<sup>31</sup> - 1), and writes the result to the destination register. If saturation occurs, it sets <xref linkend="BEIDIGBH">PSTATE</xref>.Q to 1.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="QADD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/QADD/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="QADD_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="QADD" />
        </docvars>
        <asmtemplate><text>QADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rn" hover="Second general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/QADD/A1_A.txt" mylink="aarch32.instrs.QADD.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="QADD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/QADD/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="QADD_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="QADD" />
        </docvars>
        <asmtemplate><text>QADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rn" hover="Second general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/QADD/T1_A.txt" mylink="aarch32.instrs.QADD.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="QADD_A1, QADD_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QADD_A1, QADD_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QADD_A1, QADD_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QADD_A1, QADD_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QADD_A1, QADD_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/QADD/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    boolean sat;</line>
<line>    (<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d], sat) = <a link="impl-shared.SignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]), 32);</line>
<line>    if sat then</line>
<line>        PSTATE.Q = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="qadd16.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="QADD16" title="QADD16 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="QADD16" />
  </docvars>
  <heading>QADD16</heading>
  <desc>
    <brief>
      <para>Saturating Add 16</para>
    </brief>
    <authored>
      <para>Saturating Add 16 performs two 16-bit integer additions, saturates the results to the 16-bit signed integer range -2<sup>15</sup> &lt;= x &lt;= 2<sup>15</sup> - 1, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="QADD16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/QADD16/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="QADD16_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="QADD16" />
        </docvars>
        <asmtemplate><text>QADD16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/QADD16/A1_A.txt" mylink="aarch32.instrs.QADD16.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="QADD16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/QADD16/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="QADD16_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="QADD16" />
        </docvars>
        <asmtemplate><text>QADD16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/QADD16/T1_A.txt" mylink="aarch32.instrs.QADD16.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="QADD16_A1, QADD16_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QADD16_A1, QADD16_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QADD16_A1, QADD16_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QADD16_A1, QADD16_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QADD16_A1, QADD16_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/QADD16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    sum1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    sum2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = <a link="impl-aarch32.SignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) SignedSat(integer i, integer N)">SignedSat</a>(sum1, 16);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = <a link="impl-aarch32.SignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) SignedSat(integer i, integer N)">SignedSat</a>(sum2, 16);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="qadd8.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="QADD8" title="QADD8 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="QADD8" />
  </docvars>
  <heading>QADD8</heading>
  <desc>
    <brief>
      <para>Saturating Add 8</para>
    </brief>
    <authored>
      <para>Saturating Add 8 performs four 8-bit integer additions, saturates the results to the 8-bit signed integer range -2<sup>7</sup> &lt;= x &lt;= 2<sup>7</sup> - 1, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="QADD8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/QADD8/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="QADD8_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="QADD8" />
        </docvars>
        <asmtemplate><text>QADD8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/QADD8/A1_A.txt" mylink="aarch32.instrs.QADD8.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="QADD8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/QADD8/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="QADD8_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="QADD8" />
        </docvars>
        <asmtemplate><text>QADD8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/QADD8/T1_A.txt" mylink="aarch32.instrs.QADD8.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="QADD8_A1, QADD8_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QADD8_A1, QADD8_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QADD8_A1, QADD8_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QADD8_A1, QADD8_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QADD8_A1, QADD8_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/QADD8/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    sum1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;7:0&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;7:0&gt;);</line>
<line>    sum2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:8&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:8&gt;);</line>
<line>    sum3 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;23:16&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;23:16&gt;);</line>
<line>    sum4 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:24&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:24&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;7:0&gt;   = <a link="impl-aarch32.SignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) SignedSat(integer i, integer N)">SignedSat</a>(sum1, 8);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:8&gt;  = <a link="impl-aarch32.SignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) SignedSat(integer i, integer N)">SignedSat</a>(sum2, 8);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;23:16&gt; = <a link="impl-aarch32.SignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) SignedSat(integer i, integer N)">SignedSat</a>(sum3, 8);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:24&gt; = <a link="impl-aarch32.SignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) SignedSat(integer i, integer N)">SignedSat</a>(sum4, 8);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="qasx.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="QASX" title="QASX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="QASX" />
  </docvars>
  <heading>QASX</heading>
  <desc>
    <brief>
      <para>Saturating Add and Subtract with Exchange</para>
    </brief>
    <authored>
      <para>Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer addition and one 16-bit subtraction, saturates the results to the 16-bit signed integer range -2<sup>15</sup> &lt;= x &lt;= 2<sup>15</sup> - 1, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="QASX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/QASX/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="QASX_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="QASX" />
        </docvars>
        <asmtemplate><text>QASX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/QASX/A1_A.txt" mylink="aarch32.instrs.QASX.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="QASX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/QASX/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="QASX_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="QASX" />
        </docvars>
        <asmtemplate><text>QASX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/QASX/T1_A.txt" mylink="aarch32.instrs.QASX.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="QASX_A1, QASX_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QASX_A1, QASX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QASX_A1, QASX_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QASX_A1, QASX_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QASX_A1, QASX_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/QASX/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    diff = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    sum  = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = <a link="impl-aarch32.SignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) SignedSat(integer i, integer N)">SignedSat</a>(diff, 16);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = <a link="impl-aarch32.SignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) SignedSat(integer i, integer N)">SignedSat</a>(sum, 16);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="qdadd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="QDADD" title="QDADD -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="QDADD" />
  </docvars>
  <heading>QDADD</heading>
  <desc>
    <brief>
      <para>Saturating Double and Add</para>
    </brief>
    <authored>
      <para>Saturating Double and Add adds a doubled register value to another register value, and writes the result to the destination register. Both the doubling and the addition have their results saturated to the 32-bit signed integer range -2<sup>31</sup> &lt;= x &lt;= 2<sup>31</sup> - 1. If saturation occurs in either operation, it sets <xref linkend="BEIDIGBH">PSTATE</xref>.Q to 1.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="QDADD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/QDADD/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="QDADD_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="QDADD" />
        </docvars>
        <asmtemplate><text>QDADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rn" hover="Second general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/QDADD/A1_A.txt" mylink="aarch32.instrs.QDADD.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="QDADD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/QDADD/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="op2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="QDADD_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="QDADD" />
        </docvars>
        <asmtemplate><text>QDADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rn" hover="Second general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/QDADD/T1_A.txt" mylink="aarch32.instrs.QDADD.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="QDADD_A1, QDADD_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QDADD_A1, QDADD_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QDADD_A1, QDADD_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QDADD_A1, QDADD_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QDADD_A1, QDADD_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/QDADD/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    (doubled, sat1) = <a link="impl-shared.SignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]), 32);</line>
<line>    boolean sat2;</line>
<line>    (<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d], sat2)  = <a link="impl-shared.SignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(doubled), 32);</line>
<line>    if sat1 || sat2 then</line>
<line>        PSTATE.Q = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="qdsub.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="QDSUB" title="QDSUB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="QDSUB" />
  </docvars>
  <heading>QDSUB</heading>
  <desc>
    <brief>
      <para>Saturating Double and Subtract</para>
    </brief>
    <authored>
      <para>Saturating Double and Subtract subtracts a doubled register value from another register value, and writes the result to the destination register. Both the doubling and the subtraction have their results saturated to the 32-bit signed integer range -2<sup>31</sup> &lt;= x &lt;= 2<sup>31</sup> - 1. If saturation occurs in either operation, it sets <xref linkend="BEIDIGBH">PSTATE</xref>.Q to 1.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="QDSUB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/QDSUB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="QDSUB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="QDSUB" />
        </docvars>
        <asmtemplate><text>QDSUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rn" hover="Second general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/QDSUB/A1_A.txt" mylink="aarch32.instrs.QDSUB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="QDSUB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/QDSUB/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="QDSUB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="QDSUB" />
        </docvars>
        <asmtemplate><text>QDSUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rn" hover="Second general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/QDSUB/T1_A.txt" mylink="aarch32.instrs.QDSUB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="QDSUB_A1, QDSUB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QDSUB_A1, QDSUB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QDSUB_A1, QDSUB_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QDSUB_A1, QDSUB_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QDSUB_A1, QDSUB_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/QDSUB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    (doubled, sat1) = <a link="impl-shared.SignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2 * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]), 32);</line>
<line>    boolean sat2;</line>
<line>    (<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d], sat2)  = <a link="impl-shared.SignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(doubled), 32);</line>
<line>    if sat1 || sat2 then</line>
<line>        PSTATE.Q = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="qsax.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="QSAX" title="QSAX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="QSAX" />
  </docvars>
  <heading>QSAX</heading>
  <desc>
    <brief>
      <para>Saturating Subtract and Add with Exchange</para>
    </brief>
    <authored>
      <para>Saturating Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer subtraction and one 16-bit addition, saturates the results to the 16-bit signed integer range -2<sup>15</sup> &lt;= x &lt;= 2<sup>15</sup> - 1, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="QSAX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/QSAX/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="QSAX_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="QSAX" />
        </docvars>
        <asmtemplate><text>QSAX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/QSAX/A1_A.txt" mylink="aarch32.instrs.QSAX.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="QSAX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/QSAX/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="QSAX_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="QSAX" />
        </docvars>
        <asmtemplate><text>QSAX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/QSAX/T1_A.txt" mylink="aarch32.instrs.QSAX.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="QSAX_A1, QSAX_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QSAX_A1, QSAX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QSAX_A1, QSAX_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QSAX_A1, QSAX_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QSAX_A1, QSAX_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/QSAX/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    sum  = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    diff = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = <a link="impl-aarch32.SignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) SignedSat(integer i, integer N)">SignedSat</a>(sum, 16);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = <a link="impl-aarch32.SignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) SignedSat(integer i, integer N)">SignedSat</a>(diff, 16);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="qsub.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="QSUB" title="QSUB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="QSUB" />
  </docvars>
  <heading>QSUB</heading>
  <desc>
    <brief>
      <para>Saturating Subtract</para>
    </brief>
    <authored>
      <para>Saturating Subtract subtracts one register value from another register value, saturates the result to the 32-bit signed integer range -2<sup>31</sup> &lt;= x &lt;= 2<sup>31</sup> - 1, and writes the result to the destination register. If saturation occurs, it sets <xref linkend="BEIDIGBH">PSTATE</xref>.Q to 1.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="QSUB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/QSUB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="QSUB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="QSUB" />
        </docvars>
        <asmtemplate><text>QSUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rn" hover="Second general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/QSUB/A1_A.txt" mylink="aarch32.instrs.QSUB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="QSUB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/QSUB/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="QSUB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="QSUB" />
        </docvars>
        <asmtemplate><text>QSUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rn" hover="Second general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/QSUB/T1_A.txt" mylink="aarch32.instrs.QSUB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="QSUB_A1, QSUB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QSUB_A1, QSUB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QSUB_A1, QSUB_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QSUB_A1, QSUB_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QSUB_A1, QSUB_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/QSUB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    boolean sat;</line>
<line>    (<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d], sat) = <a link="impl-shared.SignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]), 32);</line>
<line>    if sat then</line>
<line>        PSTATE.Q = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="qsub16.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="QSUB16" title="QSUB16 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="QSUB16" />
  </docvars>
  <heading>QSUB16</heading>
  <desc>
    <brief>
      <para>Saturating Subtract 16</para>
    </brief>
    <authored>
      <para>Saturating Subtract 16 performs two 16-bit integer subtractions, saturates the results to the 16-bit signed integer range -2<sup>15</sup> &lt;= x &lt;= 2<sup>15</sup> - 1, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="QSUB16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/QSUB16/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="QSUB16_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="QSUB16" />
        </docvars>
        <asmtemplate><text>QSUB16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/QSUB16/A1_A.txt" mylink="aarch32.instrs.QSUB16.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="QSUB16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/QSUB16/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="QSUB16_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="QSUB16" />
        </docvars>
        <asmtemplate><text>QSUB16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/QSUB16/T1_A.txt" mylink="aarch32.instrs.QSUB16.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="QSUB16_A1, QSUB16_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QSUB16_A1, QSUB16_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QSUB16_A1, QSUB16_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QSUB16_A1, QSUB16_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QSUB16_A1, QSUB16_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/QSUB16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    diff1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    diff2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = <a link="impl-aarch32.SignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) SignedSat(integer i, integer N)">SignedSat</a>(diff1, 16);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = <a link="impl-aarch32.SignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) SignedSat(integer i, integer N)">SignedSat</a>(diff2, 16);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="qsub8.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="QSUB8" title="QSUB8 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="QSUB8" />
  </docvars>
  <heading>QSUB8</heading>
  <desc>
    <brief>
      <para>Saturating Subtract 8</para>
    </brief>
    <authored>
      <para>Saturating Subtract 8 performs four 8-bit integer subtractions, saturates the results to the 8-bit signed integer range -2<sup>7</sup> &lt;= x &lt;= 2<sup>7</sup> - 1, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="QSUB8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/QSUB8/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="QSUB8_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="QSUB8" />
        </docvars>
        <asmtemplate><text>QSUB8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/QSUB8/A1_A.txt" mylink="aarch32.instrs.QSUB8.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="QSUB8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/QSUB8/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="QSUB8_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="QSUB8" />
        </docvars>
        <asmtemplate><text>QSUB8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/QSUB8/T1_A.txt" mylink="aarch32.instrs.QSUB8.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="QSUB8_A1, QSUB8_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QSUB8_A1, QSUB8_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QSUB8_A1, QSUB8_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QSUB8_A1, QSUB8_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="QSUB8_A1, QSUB8_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/QSUB8/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    diff1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;7:0&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;7:0&gt;);</line>
<line>    diff2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:8&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:8&gt;);</line>
<line>    diff3 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;23:16&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;23:16&gt;);</line>
<line>    diff4 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:24&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:24&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;7:0&gt;   = <a link="impl-aarch32.SignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) SignedSat(integer i, integer N)">SignedSat</a>(diff1, 8);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:8&gt;  = <a link="impl-aarch32.SignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) SignedSat(integer i, integer N)">SignedSat</a>(diff2, 8);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;23:16&gt; = <a link="impl-aarch32.SignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) SignedSat(integer i, integer N)">SignedSat</a>(diff3, 8);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:24&gt; = <a link="impl-aarch32.SignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) SignedSat(integer i, integer N)">SignedSat</a>(diff4, 8);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="rbit.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="RBIT" title="RBIT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="RBIT" />
  </docvars>
  <heading>RBIT</heading>
  <desc>
    <brief>
      <para>Reverse Bits</para>
    </brief>
    <authored>
      <para>Reverse Bits reverses the bit order in a 32-bit register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="RBIT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/RBIT/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="RBIT_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RBIT" />
        </docvars>
        <asmtemplate><text>RBIT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/RBIT/A1_A.txt" mylink="aarch32.instrs.RBIT.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="RBIT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/RBIT/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="RBIT_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="RBIT" />
        </docvars>
        <asmtemplate><text>RBIT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/RBIT/T1_A.txt" mylink="aarch32.instrs.RBIT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if m != n || d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>m != n</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="m = UInt(Rn);" />
          </cu_type>
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="m = UInt(Rm);" />
          </cu_type>
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="RBIT_A1, RBIT_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RBIT_A1, RBIT_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RBIT_A1, RBIT_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RBIT_A1" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RBIT_T1" symboldefcount="2">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose source register, encoded in the "Rm" field. It must be encoded with an identical value in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/RBIT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    bits(32) result;</line>
<line>    for i = 0 to 31</line>
<line>        result&lt;31-i&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;i&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="rev.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="REV" title="REV -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="REV" />
  </docvars>
  <heading>REV</heading>
  <desc>
    <brief>
      <para>Byte-Reverse Word</para>
    </brief>
    <authored>
      <para>Byte-Reverse Word reverses the byte order in a 32-bit register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="REV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/REV/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="REV_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="REV" />
        </docvars>
        <asmtemplate><text>REV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/REV/A1_A.txt" mylink="aarch32.instrs.REV.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="REV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/REV/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="2" name="op" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="REV_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="REV" />
        </docvars>
        <asmtemplate><text>REV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/REV/T1_A.txt" mylink="aarch32.instrs.REV.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="REV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/REV/T2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="REV_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="REV" />
        </docvars>
        <asmtemplate comment="&lt;Rd&gt;, &lt;Rm&gt; can be represented in T1"><text>REV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>REV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/REV/T2_A.txt" mylink="aarch32.instrs.REV.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if m != n || d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>m != n</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="m = UInt(Rn);" />
          </cu_type>
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="m = UInt(Rm);" />
          </cu_type>
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="REV_A1, REV_T1, REV_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="REV_A1, REV_T1, REV_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="REV_A1, REV_T1, REV_T2" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="REV_A1, REV_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>For encoding A1 and T1: is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="REV_T2" symboldefcount="2">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the general-purpose source register, encoded in the "Rm" field. It must be encoded with an identical value in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/REV/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    bits(32) result;</line>
<line>    result&lt;31:24&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;7:0&gt;;</line>
<line>    result&lt;23:16&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:8&gt;;</line>
<line>    result&lt;15:8&gt;  = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;23:16&gt;;</line>
<line>    result&lt;7:0&gt;   = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:24&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="rev16.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="REV16" title="REV16 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="REV16" />
  </docvars>
  <heading>REV16</heading>
  <desc>
    <brief>
      <para>Byte-Reverse Packed Halfword</para>
    </brief>
    <authored>
      <para>Byte-Reverse Packed Halfword reverses the byte order in each16-bit halfword of a 32-bit register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="REV16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/REV16/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="REV16_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="REV16" />
        </docvars>
        <asmtemplate><text>REV16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/REV16/A1_A.txt" mylink="aarch32.instrs.REV16.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="REV16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/REV16/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="2" name="op" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="REV16_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="REV16" />
        </docvars>
        <asmtemplate><text>REV16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/REV16/T1_A.txt" mylink="aarch32.instrs.REV16.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="REV16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/REV16/T2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="op2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="REV16_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="REV16" />
        </docvars>
        <asmtemplate comment="&lt;Rd&gt;, &lt;Rm&gt; can be represented in T1"><text>REV16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>REV16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/REV16/T2_A.txt" mylink="aarch32.instrs.REV16.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if m != n || d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>m != n</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="m = UInt(Rn);" />
          </cu_type>
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="m = UInt(Rm);" />
          </cu_type>
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="REV16_A1, REV16_T1, REV16_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="REV16_A1, REV16_T1, REV16_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="REV16_A1, REV16_T1, REV16_T2" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="REV16_A1, REV16_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>For encoding A1 and T1: is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="REV16_T2" symboldefcount="2">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the general-purpose source register, encoded in the "Rm" field. It must be encoded with an identical value in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/REV16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    bits(32) result;</line>
<line>    result&lt;31:24&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;23:16&gt;;</line>
<line>    result&lt;23:16&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:24&gt;;</line>
<line>    result&lt;15:8&gt;  = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;7:0&gt;;</line>
<line>    result&lt;7:0&gt;   = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:8&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="revsh.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="REVSH" title="REVSH -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="REVSH" />
  </docvars>
  <heading>REVSH</heading>
  <desc>
    <brief>
      <para>Byte-Reverse Signed Halfword</para>
    </brief>
    <authored>
      <para>Byte-Reverse Signed Halfword reverses the byte order in the lower 16-bit halfword of a 32-bit register, and sign-extends the result to 32 bits.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="REVSH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/REVSH/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="REVSH_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="REVSH" />
        </docvars>
        <asmtemplate><text>REVSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/REVSH/A1_A.txt" mylink="aarch32.instrs.REVSH.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="REVSH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/REVSH/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="2" name="op" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="REVSH_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="REVSH" />
        </docvars>
        <asmtemplate><text>REVSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/REVSH/T1_A.txt" mylink="aarch32.instrs.REVSH.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="REVSH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/REVSH/T2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="REVSH_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="REVSH" />
        </docvars>
        <asmtemplate comment="&lt;Rd&gt;, &lt;Rm&gt; can be represented in T1"><text>REVSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>REVSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/REVSH/T2_A.txt" mylink="aarch32.instrs.REVSH.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if m != n || d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>m != n</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="m = UInt(Rn);" />
          </cu_type>
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="m = UInt(Rm);" />
          </cu_type>
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="REVSH_A1, REVSH_T1, REVSH_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="REVSH_A1, REVSH_T1, REVSH_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="REVSH_A1, REVSH_T1, REVSH_T2" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="REVSH_A1, REVSH_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>For encoding A1 and T1: is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="REVSH_T2" symboldefcount="2">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the general-purpose source register, encoded in the "Rm" field. It must be encoded with an identical value in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/REVSH/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    bits(32) result;</line>
<line>    result&lt;31:8&gt;  = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;7:0&gt;, 24);</line>
<line>    result&lt;7:0&gt;   = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:8&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="rfe.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="RFE" title="RFE, RFEDA, RFEDB, RFEIA, RFEIB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="RFE" />
  </docvars>
  <heading>RFE, RFEDA, RFEDB, RFEIA, RFEIB</heading>
  <desc>
    <brief>
      <para>Return From Exception</para>
    </brief>
    <authored>
      <para>Return From Exception loads two consecutive memory locations using an address in a base register:</para>
      <list type="unordered">
        <listitem><content>The word loaded from the lower address is treated as an instruction address. The PE branches to it.</content></listitem>
        <listitem><content>The word loaded from the higher address is used to restore <xref linkend="BEIDIGBH">PSTATE</xref>. This word must be in the format of an SPSR.</content></listitem>
      </list>
      <para>An address adjusted by the size of the data loaded can optionally be written back to the base register.</para>
      <para>The PE checks the value of the word loaded from the higher address for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</para>
      <para><instruction>RFE</instruction> is <arm-defined-word>undefined</arm-defined-word> in Hyp mode and <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para><instruction>RFEFA</instruction>, <instruction>RFEEA</instruction>, <instruction>RFEFD</instruction>, and <instruction>RFEED</instruction> are pseudo-instructions for <instruction>RFEDA</instruction>, <instruction>RFEDB</instruction>, <instruction>RFEIA</instruction>, and <instruction>RFEIB</instruction> respectively, referring to their use for popping data from Full Ascending, Empty Ascending, Full Descending, and Empty Descending stacks.</para>
    </syntaxnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="RFE" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/RFE/A1_AS.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="11" name="op" settings="11">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(1)</c>
          <c>(0)</c>
          <c>(1)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="4" width="5" name="mode" settings="5">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="RFEDA_A1_AS" oneofinclass="4" oneof="6" label="Decrement After" bitdiffs="P == 0 &amp;&amp; U == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="dec-after" />
          <docvar key="mnemonic" value="RFE" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>0</c>
        </box>
        <asmtemplate comment="Preferred syntax"><text>RFEDA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a></asmtemplate>
        <asmtemplate comment="Alternate syntax, Full Ascending stack"><text>RFEFA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a></asmtemplate>
      </encoding>
      <encoding name="RFEDB_A1_AS" oneofinclass="4" oneof="6" label="Decrement Before" bitdiffs="P == 1 &amp;&amp; U == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="RFE" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>0</c>
        </box>
        <asmtemplate comment="Preferred syntax"><text>RFEDB</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a></asmtemplate>
        <asmtemplate comment="Alternate syntax, Empty Ascending stack"><text>RFEEA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a></asmtemplate>
      </encoding>
      <encoding name="RFEIA_A1_AS" oneofinclass="4" oneof="6" label="Increment After" bitdiffs="P == 0 &amp;&amp; U == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="inc-after" />
          <docvar key="mnemonic" value="RFE" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>1</c>
        </box>
        <asmtemplate comment="Preferred syntax"><text>RFE</text><a link="sa_ia_1" hover="Optional suffix to indicate the Increment After variant">{IA}</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a></asmtemplate>
        <asmtemplate comment="Alternate syntax, Full Descending stack"><text>RFEFD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a></asmtemplate>
      </encoding>
      <encoding name="RFEIB_A1_AS" oneofinclass="4" oneof="6" label="Increment Before" bitdiffs="P == 1 &amp;&amp; U == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="inc-before" />
          <docvar key="mnemonic" value="RFE" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>1</c>
        </box>
        <asmtemplate comment="Preferred syntax"><text>RFEIB</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a></asmtemplate>
        <asmtemplate comment="Alternate syntax, Empty Descending stack"><text>RFEED</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/RFE/A1_AS.txt" mylink="aarch32.instrs.RFE.A1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>wback = (W == '1');  increment = (U == '1');  wordhigher = (P == U);</line>
<line>if n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="ldmstm-mode" value="dec-before" />
        <docvar key="mnemonic" value="RFE" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/RFE/T1_AS.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="opc" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" name="P" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" name="M" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" width="14" name="register_list" settings="14">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="RFE_T1_AS" oneofinclass="1" oneof="6" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="RFE" />
        </docvars>
        <asmtemplate comment="Outside or last in IT block, preferred syntax"><text>RFEDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a></asmtemplate>
        <asmtemplate comment="Outside or last in IT block, alternate syntax, Full Ascending stack"><text>RFEFA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/RFE/T1_AS.txt" mylink="aarch32.instrs.RFE.T1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  wback = (W == '1');  increment = FALSE;  wordhigher = FALSE;</line>
<line>if n == 15 then UNPREDICTABLE;</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="ldmstm-mode" value="inc-after" />
        <docvar key="mnemonic" value="RFE" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/RFE/T2_AS.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="opc" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" name="P" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" name="M" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" width="14" name="register_list" settings="14">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="RFE_T2_AS" oneofinclass="1" oneof="6" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="ldmstm-mode" value="inc-after" />
          <docvar key="mnemonic" value="RFE" />
        </docvars>
        <asmtemplate comment="Outside or last in IT block, preferred syntax"><text>RFE</text><a link="sa_ia" hover="Optional suffix for Increment After form">{IA}</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a></asmtemplate>
        <asmtemplate comment="Outside or last in IT block, alternate syntax, Full Descending stack"><text>RFEFD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/RFE/T2_AS.txt" mylink="aarch32.instrs.RFE.T2_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  wback = (W == '1');  increment = TRUE;  wordhigher = FALSE;</line>
<line>if n == 15 then UNPREDICTABLE;</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="RFEIA_A1_AS" symboldefcount="1">
      <symbol link="sa_ia_1">IA</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is an optional suffix to indicate the Increment After variant.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RFE_T2_AS" symboldefcount="2">
      <symbol link="sa_ia">IA</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is an optional suffix for the Increment After form.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RFEDA_A1_AS" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="dec-after" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. <syntax>&lt;c&gt;</syntax> must be <value>AL</value> or omitted.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RFE_T1_AS, RFE_T2_AS" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RFEDA_A1_AS, RFE_T1_AS, RFE_T2_AS" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RFEDA_A1_AS, RFE_T1_AS, RFE_T2_AS" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RFEDA_A1_AS, RFE_T1_AS, RFE_T2_AS" symboldefcount="1">
      <symbol link="sa_0d33">!</symbol>
      <account encodedin="W">
        <intro>
          <para>The address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/RFE/Op_AS.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>        UNDEFINED;</line>
<line>    elsif PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        UNPREDICTABLE;                        // UNDEFINED or NOP</line>
<line>    else</line>
<line>        address = if increment then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]-8;</line>
<line>        if wordhigher then address = address+4;</line>
<line>        new_pc_value = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,4];</line>
<line>        spsr = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address+4,4];</line>
<line>        if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = if increment then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]+8 else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]-8;</line>
<line>        <a link="AArch32.ExceptionReturn.2" file="shared_pseudocode.xml" hover="function: AArch32.ExceptionReturn(bits(32) new_pc_in, bits(32) spsr)">AArch32.ExceptionReturn</a>(new_pc_value, spsr);</line>
</pstext>
    </ps>
  </ps_section>
  <constrained_unpredictables ps_block="Operation">
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>PSTATE.EL == EL0</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
    </cu_case>
  </constrained_unpredictables>
</instructionsection>
</file>
<file type="instructionsection" file="ror_mov_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ROR_MOV_r" title="ROR (immediate) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="ROR" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MOV" />
    <docvar key="mnemonic-shift-type" value="MOV-shift-no-rrx" />
    <docvar key="shift-type" value="shift-no-rrx" />
  </docvars>
  <heading>ROR (immediate)</heading>
  <desc>
    <brief>
      <para>Rotate Right (immediate)</para>
    </brief>
    <authored>
      <para>Rotate Right (immediate) provides the value of the contents of a register rotated by a constant value. The bits that are rotated off the right end are inserted into the vacated bit positions on the left.</para>
    </authored>
  </desc>
  <aliasto refiform="mov_r.xml" iformid="MOV_r">MOV, MOVS (register)</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1" settings="5" constraint="!= 00000">
          <c colspan="5">!= 00000</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ROR_MOV_r_A1" oneofinclass="1" oneof="2" label="MOV, shift or rotate by value">
        <docvars>
          <docvar key="alias_mnemonic" value="ROR" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <asmtemplate><text>ROR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_3" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_2" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_6" hover="Shift amount [1-31] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOV_r_A1">MOV</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_3" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_2" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, ROR #</text><a link="sa_imm_6" hover="Shift amount [1-31] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T3" oneof="2" id="iclass_t3" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ROR_MOV_r_T3" oneofinclass="1" oneof="2" label="MOV, shift or rotate by value" bitdiffs="!(imm3 == 000 &amp;&amp; imm2 == 00)">
        <docvars>
          <docvar key="alias_mnemonic" value="ROR" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="14" width="9" name="imm3:imm2">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
        </box>
        <asmtemplate><text>ROR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_4" hover="Shift amount [1-31] (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOV_r_T3">MOV</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, ROR #</text><a link="sa_imm_4" hover="Shift amount [1-31] (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ROR_MOV_r_A1, ROR_MOV_r_T3" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ROR_MOV_r_A1, ROR_MOV_r_T3" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ROR_MOV_r_A1" symboldefcount="1">
      <symbol link="sa_rd_3">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. Arm deprecates using the PC as the destination register, but if the PC is used, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ROR_MOV_r_T3" symboldefcount="2">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T3" />
        </docvars>
        <intro>
          <para>For encoding T3: is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ROR_MOV_r_A1" symboldefcount="1">
      <symbol link="sa_rm_2">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ROR_MOV_r_T3" symboldefcount="2">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="T3" />
        </docvars>
        <intro>
          <para>For encoding T3: is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ROR_MOV_r_A1" symboldefcount="1">
      <symbol link="sa_imm_6">&lt;imm&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 31, encoded in the "imm5" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ROR_MOV_r_T3" symboldefcount="2">
      <symbol link="sa_imm_4">&lt;imm&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T3" />
        </docvars>
        <intro>
          <para>For encoding T3: is the shift amount, in the range 1 to 31, encoded in the "imm3:imm2" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="ror_mov_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="ROR_MOV_rr" title="ROR (register) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="ROR" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MOV" />
  </docvars>
  <heading>ROR (register)</heading>
  <desc>
    <brief>Rotate Right (register)</brief>
    <longer> provides the value of the contents of a register rotated by a variable number of bits. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. The variable number of bits is read from the bottom byte of a register</longer>
  </desc>
  <aliasto refiform="mov_rr.xml" iformid="MOV_rr">MOV, MOVS (register-shifted register)</aliasto>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ROR_MOV_rr_A1" oneofinclass="1" oneof="3" label="Not flag setting">
        <docvars>
          <docvar key="alias_mnemonic" value="ROR" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOV" />
        </docvars>
        <asmtemplate><text>ROR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_2" hover="Second general-purpose source register holding a rotate amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOV_rr_A1">MOV</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, ROR </text><a link="sa_rs_2" hover="Second general-purpose source register holding a rotate amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MOV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="" tworows="1">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="4" name="op" usename="1" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="21" width="3" name="Rs" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rdm" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="ROR_MOV_rr_T1_ROR" oneofinclass="1" oneof="3" label="Rotate right">
        <docvars>
          <docvar key="alias_mnemonic" value="ROR" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-ror" />
          <docvar key="shift-type" value="ror" />
        </docvars>
        <asmtemplate comment="Inside IT block"><text>ROR</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rs_2" hover="Second general-purpose source register holding a rotate amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOV_rr_T1_ROR">MOV</a><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, ROR </text><a link="sa_rs_2" hover="Second general-purpose source register holding a rotate amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond><a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="stype" usename="1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ROR_MOV_rr_T2" oneofinclass="1" oneof="3" label="Not flag setting">
        <docvars>
          <docvar key="alias_mnemonic" value="ROR" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
        </docvars>
        <asmtemplate comment="Inside IT block, and &lt;Rd&gt;, &lt;Rm&gt;, &lt;shift&gt;, &lt;Rs&gt; can be represented in T1"><text>ROR</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_2" hover="Second general-purpose source register holding a rotate amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <asmtemplate><text>ROR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_2" hover="Second general-purpose source register holding a rotate amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOV_rr_T2">MOV</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, ROR </text><a link="sa_rs_2" hover="Second general-purpose source register holding a rotate amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ROR_MOV_rr_A1, ROR_MOV_rr_T1_ROR, ROR_MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ROR_MOV_rr_A1, ROR_MOV_rr_T1_ROR, ROR_MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ROR_MOV_rr_T1_ROR" symboldefcount="1">
      <symbol link="sa_rdm_1">&lt;Rdm&gt;</symbol>
      <account encodedin="Rdm">
        <intro>
          <para>Is the first general-purpose source register and the destination register, encoded in the "Rdm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ROR_MOV_rr_A1, ROR_MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ROR_MOV_rr_A1, ROR_MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ROR_MOV_rr_A1, ROR_MOV_rr_T1_ROR, ROR_MOV_rr_T2" symboldefcount="1">
      <symbol link="sa_rs_2">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the second general-purpose source register holding a rotate amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="rors_mov_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="RORS_MOV_r" title="RORS (immediate) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="RORS" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MOVS" />
    <docvar key="mnemonic-shift-type" value="MOVS-shift-no-rrx" />
    <docvar key="shift-type" value="shift-no-rrx" />
  </docvars>
  <heading>RORS (immediate)</heading>
  <desc>
    <brief>
      <para>Rotate Right, setting flags (immediate)</para>
    </brief>
    <authored>
      <para>Rotate Right, setting flags (immediate) provides the value of the contents of a register rotated by a constant value. The bits that are rotated off the right end are inserted into the vacated bit positions on the left.</para>
      <para>If the destination register is not the PC, this instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
        <listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem>
        <listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem>
        <listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem>
      </list>
    </authored>
  </desc>
  <aliasto refiform="mov_r.xml" iformid="MOV_r">MOV, MOVS (register)</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1" settings="5" constraint="!= 00000">
          <c colspan="5">!= 00000</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="RORS_MOVS_r_A1" oneofinclass="1" oneof="2" label="MOVS, shift or rotate by value">
        <docvars>
          <docvar key="alias_mnemonic" value="RORS" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOVS" />
          <docvar key="mnemonic-shift-type" value="MOVS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <asmtemplate><text>RORS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_4" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_2" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_6" hover="Shift amount [1-31] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOVS_r_A1">MOVS</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_4" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_2" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, ROR #</text><a link="sa_imm_6" hover="Shift amount [1-31] (field &quot;imm5&quot;)">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T3" oneof="2" id="iclass_t3" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="RORS_MOVS_r_T3" oneofinclass="1" oneof="2" label="MOVS, shift or rotate by value" bitdiffs="!(imm3 == 000 &amp;&amp; imm2 == 00)">
        <docvars>
          <docvar key="alias_mnemonic" value="RORS" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOVS" />
          <docvar key="mnemonic-shift-type" value="MOVS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="14" width="9" name="imm3:imm2">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
        </box>
        <asmtemplate><text>RORS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, #</text><a link="sa_imm_4" hover="Shift amount [1-31] (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOVS_r_T3">MOVS</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, ROR #</text><a link="sa_imm_4" hover="Shift amount [1-31] (field &quot;imm3:imm2&quot;)">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="RORS_MOVS_r_A1, RORS_MOVS_r_T3" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RORS_MOVS_r_A1, RORS_MOVS_r_T3" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RORS_MOVS_r_A1" symboldefcount="1">
      <symbol link="sa_rd_4">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. Arm deprecates using the PC as the destination register, but if the PC is used, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RORS_MOVS_r_T3" symboldefcount="2">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T3" />
        </docvars>
        <intro>
          <para>For encoding T3: is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RORS_MOVS_r_A1" symboldefcount="1">
      <symbol link="sa_rm_2">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RORS_MOVS_r_T3" symboldefcount="2">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="T3" />
        </docvars>
        <intro>
          <para>For encoding T3: is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RORS_MOVS_r_A1" symboldefcount="1">
      <symbol link="sa_imm_6">&lt;imm&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 31, encoded in the "imm5" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RORS_MOVS_r_T3" symboldefcount="2">
      <symbol link="sa_imm_4">&lt;imm&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T3" />
        </docvars>
        <intro>
          <para>For encoding T3: is the shift amount, in the range 1 to 31, encoded in the "imm3:imm2" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="rors_mov_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="RORS_MOV_rr" title="RORS (register) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="RORS" />
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>RORS (register)</heading>
  <desc>
    <brief>Rotate Right, setting flags (register)</brief>
    <longer> provides the value of the contents of a register rotated by a variable number of bits, and updates the condition flags based on the result. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. The variable number of bits is read from the bottom byte of a register</longer>
  </desc>
  <aliasto refiform="mov_rr.xml" iformid="MOV_rr">MOV, MOVS (register-shifted register)</aliasto>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="RORS_MOVS_rr_A1" oneofinclass="1" oneof="3" label="Flag setting">
        <docvars>
          <docvar key="alias_mnemonic" value="RORS" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOVS" />
        </docvars>
        <asmtemplate><text>RORS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_2" hover="Second general-purpose source register holding a rotate amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOVS_rr_A1">MOVS</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, ROR </text><a link="sa_rs_2" hover="Second general-purpose source register holding a rotate amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MOV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="" tworows="1">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="4" name="op" usename="1" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="21" width="3" name="Rs" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rdm" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="RORS_MOV_rr_T1_ROR" oneofinclass="1" oneof="3" label="Rotate right">
        <docvars>
          <docvar key="alias_mnemonic" value="RORS" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-ror" />
          <docvar key="shift-type" value="ror" />
        </docvars>
        <asmtemplate comment="Outside IT block"><text>RORS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rs_2" hover="Second general-purpose source register holding a rotate amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOV_rr_T1_ROR">MOVS</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>, ROR </text><a link="sa_rs_2" hover="Second general-purpose source register holding a rotate amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond>!<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="stype" usename="1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="RORS_MOVS_rr_T2" oneofinclass="1" oneof="3" label="Flag setting">
        <docvars>
          <docvar key="alias_mnemonic" value="RORS" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOVS" />
        </docvars>
        <asmtemplate comment="Outside IT block, and &lt;Rd&gt;, &lt;Rm&gt;, &lt;shift&gt;, &lt;Rs&gt; can be represented in T1"><text>RORS.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_2" hover="Second general-purpose source register holding a rotate amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <asmtemplate><text>RORS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_rs_2" hover="Second general-purpose source register holding a rotate amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_rr.xml#MOVS_rr_T2">MOVS</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="First general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, ROR </text><a link="sa_rs_2" hover="Second general-purpose source register holding a rotate amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="RORS_MOVS_rr_A1, RORS_MOVS_rr_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RORS_MOVS_rr_A1, RORS_MOV_rr_T1_ROR, RORS_MOVS_rr_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RORS_MOV_rr_T1_ROR" symboldefcount="1">
      <symbol link="sa_rdm_1">&lt;Rdm&gt;</symbol>
      <account encodedin="Rdm">
        <intro>
          <para>Is the first general-purpose source register and the destination register, encoded in the "Rdm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RORS_MOVS_rr_A1, RORS_MOVS_rr_T2" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RORS_MOVS_rr_A1, RORS_MOVS_rr_T2" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RORS_MOVS_rr_A1, RORS_MOV_rr_T1_ROR, RORS_MOVS_rr_T2" symboldefcount="1">
      <symbol link="sa_rs_2">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the second general-purpose source register holding a rotate amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="rrx_mov_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="RRX_MOV_r" title="RRX -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="RRX" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MOV" />
    <docvar key="mnemonic-shift-type" value="MOV-rrx" />
    <docvar key="shift-type" value="rrx" />
  </docvars>
  <heading>RRX</heading>
  <desc>
    <brief>
      <para>Rotate Right with Extend</para>
    </brief>
    <authored>
      <para>Rotate Right with Extend provides the value of the contents of a register shifted right by one place, with the Carry flag shifted into bit[31].</para>
    </authored>
  </desc>
  <aliasto refiform="mov_r.xml" iformid="MOV_r">MOV, MOVS (register)</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="RRX_MOV_r_A1_RRX" oneofinclass="1" oneof="2" label="MOV, rotate right with extend">
        <docvars>
          <docvar key="alias_mnemonic" value="RRX" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <asmtemplate><text>RRX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_3" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_2" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOV_r_A1_RRX">MOV</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_3" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_2" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T3" oneof="2" id="iclass_t3" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="RRX_MOV_r_T3_RRX" oneofinclass="1" oneof="2" label="MOV, rotate right with extend">
        <docvars>
          <docvar key="alias_mnemonic" value="RRX" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOV" />
          <docvar key="mnemonic-shift-type" value="MOV-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <asmtemplate><text>RRX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOV_r_T3_RRX">MOV</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="RRX_MOV_r_A1_RRX, RRX_MOV_r_T3_RRX" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RRX_MOV_r_A1_RRX, RRX_MOV_r_T3_RRX" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RRX_MOV_r_A1_RRX" symboldefcount="1">
      <symbol link="sa_rd_3">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. Arm deprecates using the PC as the destination register, but if the PC is used, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RRX_MOV_r_T3_RRX" symboldefcount="2">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T3" />
        </docvars>
        <intro>
          <para>For encoding T3: is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RRX_MOV_r_A1_RRX" symboldefcount="1">
      <symbol link="sa_rm_2">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RRX_MOV_r_T3_RRX" symboldefcount="2">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="T3" />
        </docvars>
        <intro>
          <para>For encoding T3: is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="rrxs_mov_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="RRXS_MOV_r" title="RRXS -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="RRXS" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MOVS" />
    <docvar key="mnemonic-shift-type" value="MOVS-rrx" />
    <docvar key="shift-type" value="rrx" />
  </docvars>
  <heading>RRXS</heading>
  <desc>
    <brief>
      <para>Rotate Right with Extend, setting flags</para>
    </brief>
    <authored>
      <para>Rotate Right with Extend, setting flags provides the value of the contents of a register shifted right by one place, with the Carry flag shifted into bit[31].</para>
      <para>If the destination register is not the PC, this instruction updates the condition flags based on the result, and bit[0] is shifted into the Carry flag.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
        <listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem>
        <listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem>
        <listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem>
      </list>
    </authored>
  </desc>
  <aliasto refiform="mov_r.xml" iformid="MOV_r">MOV, MOVS (register)</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="RRXS_MOVS_r_A1_RRX" oneofinclass="1" oneof="2" label="MOVS, rotate right with extend">
        <docvars>
          <docvar key="alias_mnemonic" value="RRXS" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MOVS" />
          <docvar key="mnemonic-shift-type" value="MOVS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <asmtemplate><text>RRXS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_4" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_2" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOVS_r_A1_RRX">MOVS</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_4" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_2" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T3" oneof="2" id="iclass_t3" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="RRXS_MOVS_r_T3_RRX" oneofinclass="1" oneof="2" label="MOVS, rotate right with extend">
        <docvars>
          <docvar key="alias_mnemonic" value="RRXS" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MOVS" />
          <docvar key="mnemonic-shift-type" value="MOVS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <asmtemplate><text>RRXS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="mov_r.xml#MOVS_r_T3_RRX">MOVS</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="RRXS_MOVS_r_A1_RRX, RRXS_MOVS_r_T3_RRX" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RRXS_MOVS_r_A1_RRX, RRXS_MOVS_r_T3_RRX" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RRXS_MOVS_r_A1_RRX" symboldefcount="1">
      <symbol link="sa_rd_4">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. Arm deprecates using the PC as the destination register, but if the PC is used, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RRXS_MOVS_r_T3_RRX" symboldefcount="2">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T3" />
        </docvars>
        <intro>
          <para>For encoding T3: is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RRXS_MOVS_r_A1_RRX" symboldefcount="1">
      <symbol link="sa_rm_2">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RRXS_MOVS_r_T3_RRX" symboldefcount="2">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="T3" />
        </docvars>
        <intro>
          <para>For encoding T3: is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="rsb_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="RSB_i" title="RSB, RSBS (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>RSB, RSBS (immediate)</heading>
  <desc>
    <brief>
      <para>Reverse Subtract (immediate)</para>
    </brief>
    <authored>
      <para>Reverse Subtract (immediate) subtracts a register value from an immediate value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the RSBS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. ARM deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The RSB variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The RSBS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/RSB_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="RSB_i_A1" oneofinclass="2" oneof="5" label="RSB" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RSB" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>RSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="RSBS_i_A1" oneofinclass="2" oneof="5" label="RSBS" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RSBS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>RSBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/RSB_i/A1_A.txt" mylink="aarch32.instrs.RSB_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = (S == '1');  imm32 = <a link="impl-aarch32.A32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) A32ExpandImm(bits(12) imm12)">A32ExpandImm</a>(imm12);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="RSB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/RSB_i/T1_A.txt">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="4" name="op" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="21" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="RSB_i_T1" oneofinclass="1" oneof="5" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="RSB" />
        </docvars>
        <asmtemplate comment="Inside IT block"><text>RSB</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><text>}</text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #0</text></asmtemplate>
        <asmtemplate comment="Outside IT block"><text>RSBS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><text>}</text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #0</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/RSB_i/T1_A.txt" mylink="aarch32.instrs.RSB_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>();  imm32 = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32); // immediate = #0</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/RSB_i/T2_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="RSB_i_T2" oneofinclass="2" oneof="5" label="RSB" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="RSB" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate comment="Inside IT block"><text>RSB</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #0</text></asmtemplate>
        <asmtemplate><text>RSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="RSBS_i_T2" oneofinclass="2" oneof="5" label="RSBS" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="RSBS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate comment="Outside IT block"><text>RSBS.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #0</text></asmtemplate>
        <asmtemplate><text>RSBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/RSB_i/T2_A.txt" mylink="aarch32.instrs.RSB_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = (S == '1');  imm32 = <a link="impl-aarch32.T32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) T32ExpandImm(bits(12) imm12)">T32ExpandImm</a>(i:imm3:imm8);</line>
<line>if d == 15 || n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="RSB_i_A1, RSB_i_T1, RSB_i_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_i_A1, RSB_i_T1, RSB_i_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_i_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the RSB variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the RSBS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_i_T1, RSB_i_T2" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_i_A1" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_i_T1, RSB_i_T2" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_i_A1" symboldefcount="1">
      <symbol link="sa_const_1">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: an immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_i_T2" symboldefcount="2">
      <symbol link="sa_const">&lt;const&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: an immediate value. See <xref linkend="BABGHAGA">Modified immediate constants in T32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/RSB_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(NOT(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]), imm32, '1');</line>
<line>    if d == 15 then          // Can only occur for A32 encoding</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="rsb_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="RSB_r" title="RSB, RSBS (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>RSB, RSBS (register)</heading>
  <desc>
    <brief>
      <para>Reverse Subtract (register)</para>
    </brief>
    <authored>
      <para>Reverse Subtract (register) subtracts a register value from an optionally-shifted register value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the RSBS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. ARM deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The RSB variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The RSBS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/RSB_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="RSB_r_A1_RRX" oneofinclass="4" oneof="8" label="RSB, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RSB" />
          <docvar key="mnemonic-shift-type" value="RSB-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>RSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="RSB_r_A1" oneofinclass="4" oneof="8" label="RSB, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RSB" />
          <docvar key="mnemonic-shift-type" value="RSB-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>RSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="RSBS_r_A1_RRX" oneofinclass="4" oneof="8" label="RSBS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RSBS" />
          <docvar key="mnemonic-shift-type" value="RSBS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>RSBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="RSBS_r_A1" oneofinclass="4" oneof="8" label="RSBS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RSBS" />
          <docvar key="mnemonic-shift-type" value="RSBS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>RSBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/RSB_r/A1_A.txt" mylink="aarch32.instrs.RSB_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/RSB_r/T1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="RSB_r_T1_RRX" oneofinclass="4" oneof="8" label="RSB, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="RSB" />
          <docvar key="mnemonic-shift-type" value="RSB-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>RSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="RSB_r_T1" oneofinclass="4" oneof="8" label="RSB, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="RSB" />
          <docvar key="mnemonic-shift-type" value="RSB-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>RSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="RSBS_r_T1_RRX" oneofinclass="4" oneof="8" label="RSBS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="RSBS" />
          <docvar key="mnemonic-shift-type" value="RSBS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>RSBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="RSBS_r_T1" oneofinclass="4" oneof="8" label="RSBS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="RSBS" />
          <docvar key="mnemonic-shift-type" value="RSBS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>RSBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/RSB_r/T1_A.txt" mylink="aarch32.instrs.RSB_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm3:imm2);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="RSB_r_A1, RSB_r_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_r_A1, RSB_r_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_r_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the RSB variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the RSBS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_r_T1" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_r_A1" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_r_T1" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_r_A1" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_r_T1" symboldefcount="2">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_r_A1, RSB_r_T1" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="RSB_r_A1" symboldefcount="1">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_r_T1" symboldefcount="2">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm3:imm2" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/RSB_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(NOT(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]), shifted, '1');</line>
<line>    if d == 15 then          // Can only occur for A32 encoding</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="rsb_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="RSB_rr" title="RSB, RSBS (register-shifted register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
  </docvars>
  <heading>RSB, RSBS (register-shifted register)</heading>
  <desc>
    <brief>
      <para>Reverse Subtract (register-shifted register)</para>
    </brief>
    <authored>
      <para>Reverse Subtract (register-shifted register) subtracts a register value from a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/RSB_rr/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="RSBS_rr_A1" oneofinclass="2" oneof="2" label="Flag setting" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RSBS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>RSBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="Third general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <encoding name="RSB_rr_A1" oneofinclass="2" oneof="2" label="Not flag setting" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RSB" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>RSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="Third general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/RSB_rr/A1_A.txt" mylink="aarch32.instrs.RSB_rr.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);</line>
<line>setflags = (S == '1');  shift_t = <a link="impl-aarch32.DecodeRegShift.1" file="shared_pseudocode.xml" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</a>(stype);</line>
<line>if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="RSB_rr_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_rr_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_rr_A1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_rr_A1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_rr_A1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_rr_A1" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="RSB_rr_A1" symboldefcount="1">
      <symbol link="sa_rs">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the third general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/RSB_rr/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shift_n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[s]&lt;7:0&gt;);</line>
<line>    shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(NOT(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]), shifted, '1');</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>    if setflags then</line>
<line>        PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="rsc_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="RSC_i" title="RSC, RSCS (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
  </docvars>
  <heading>RSC, RSCS (immediate)</heading>
  <desc>
    <brief>
      <para>Reverse Subtract with Carry (immediate)</para>
    </brief>
    <authored>
      <para>Reverse Subtract with Carry (immediate) subtracts a register value and the value of NOT (Carry flag) from an immediate value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the RSCS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. ARM deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The RSC variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The RSCS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/RSC_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="RSC_i_A1" oneofinclass="2" oneof="2" label="RSC" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RSC" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>RSC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="RSCS_i_A1" oneofinclass="2" oneof="2" label="RSCS" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RSCS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>RSCS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/RSC_i/A1_A.txt" mylink="aarch32.instrs.RSC_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = (S == '1');  imm32 = <a link="impl-aarch32.A32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) A32ExpandImm(bits(12) imm12)">A32ExpandImm</a>(imm12);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="RSC_i_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_i_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_i_A1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the RSC variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the RSCS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_i_A1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_i_A1" symboldefcount="1">
      <symbol link="sa_const">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <intro>
          <para>An immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/RSC_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(NOT(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]), imm32, PSTATE.C);</line>
<line>    if d == 15 then</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="rsc_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="RSC_r" title="RSC, RSCS (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
  </docvars>
  <heading>RSC, RSCS (register)</heading>
  <desc>
    <brief>
      <para>Reverse Subtract with Carry (register)</para>
    </brief>
    <authored>
      <para>Reverse Subtract with Carry (register) subtracts a register value and the value of NOT (Carry flag) from an optionally-shifted register value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the RSCS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. ARM deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The RSC variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The RSCS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/RSC_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="RSC_r_A1_RRX" oneofinclass="4" oneof="4" label="RSC, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RSC" />
          <docvar key="mnemonic-shift-type" value="RSC-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>RSC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="RSC_r_A1" oneofinclass="4" oneof="4" label="RSC, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RSC" />
          <docvar key="mnemonic-shift-type" value="RSC-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>RSC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="RSCS_r_A1_RRX" oneofinclass="4" oneof="4" label="RSCS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RSCS" />
          <docvar key="mnemonic-shift-type" value="RSCS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>RSCS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="RSCS_r_A1" oneofinclass="4" oneof="4" label="RSCS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RSCS" />
          <docvar key="mnemonic-shift-type" value="RSCS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>RSCS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/RSC_r/A1_A.txt" mylink="aarch32.instrs.RSC_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="RSC_r_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_r_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_r_A1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the RSC variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the RSCS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_r_A1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_r_A1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_r_A1" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="RSC_r_A1" symboldefcount="1">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <intro>
          <para>Is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/RSC_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(NOT(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]), shifted, PSTATE.C);</line>
<line>    if d == 15 then</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="rsc_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="RSC_rr" title="RSC, RSCS (register-shifted register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
  </docvars>
  <heading>RSC, RSCS (register-shifted register)</heading>
  <desc>
    <brief>
      <para>Reverse Subtract (register-shifted register)</para>
    </brief>
    <authored>
      <para>Reverse Subtract (register-shifted register) subtracts a register value and the value of NOT (Carry flag) from a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/RSC_rr/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="RSCS_rr_A1" oneofinclass="2" oneof="2" label="Flag setting" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RSCS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>RSCS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="Third general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <encoding name="RSC_rr_A1" oneofinclass="2" oneof="2" label="Not flag setting" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RSC" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>RSC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="Third general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/RSC_rr/A1_A.txt" mylink="aarch32.instrs.RSC_rr.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);</line>
<line>setflags = (S == '1');  shift_t = <a link="impl-aarch32.DecodeRegShift.1" file="shared_pseudocode.xml" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</a>(stype);</line>
<line>if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="RSC_rr_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_rr_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_rr_A1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_rr_A1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_rr_A1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_rr_A1" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="RSC_rr_A1" symboldefcount="1">
      <symbol link="sa_rs">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the third general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/RSC_rr/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shift_n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[s]&lt;7:0&gt;);</line>
<line>    shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(NOT(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]), shifted, PSTATE.C);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>    if setflags then</line>
<line>        PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sadd16.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SADD16" title="SADD16 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SADD16" />
  </docvars>
  <heading>SADD16</heading>
  <desc>
    <brief>
      <para>Signed Add 16</para>
    </brief>
    <authored>
      <para>Signed Add 16 performs two 16-bit signed integer additions, and writes the results to the destination register. It sets <xref linkend="BEIDIGBH">PSTATE</xref>.GE according to the results of the additions.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SADD16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SADD16/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SADD16_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SADD16" />
        </docvars>
        <asmtemplate><text>SADD16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SADD16/A1_A.txt" mylink="aarch32.instrs.SADD16.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SADD16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SADD16/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SADD16_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SADD16" />
        </docvars>
        <asmtemplate><text>SADD16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SADD16/T1_A.txt" mylink="aarch32.instrs.SADD16.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SADD16_A1, SADD16_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SADD16_A1, SADD16_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SADD16_A1, SADD16_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SADD16_A1, SADD16_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SADD16_A1, SADD16_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SADD16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    sum1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    sum2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = sum1&lt;15:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = sum2&lt;15:0&gt;;</line>
<line>    PSTATE.GE&lt;1:0&gt; = if sum1 &gt;= 0 then '11' else '00';</line>
<line>    PSTATE.GE&lt;3:2&gt; = if sum2 &gt;= 0 then '11' else '00';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sadd8.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SADD8" title="SADD8 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SADD8" />
  </docvars>
  <heading>SADD8</heading>
  <desc>
    <brief>
      <para>Signed Add 8</para>
    </brief>
    <authored>
      <para>Signed Add 8 performs four 8-bit signed integer additions, and writes the results to the destination register. It sets <xref linkend="BEIDIGBH">PSTATE</xref>.GE according to the results of the additions.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SADD8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SADD8/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SADD8_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SADD8" />
        </docvars>
        <asmtemplate><text>SADD8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SADD8/A1_A.txt" mylink="aarch32.instrs.SADD8.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SADD8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SADD8/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SADD8_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SADD8" />
        </docvars>
        <asmtemplate><text>SADD8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SADD8/T1_A.txt" mylink="aarch32.instrs.SADD8.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SADD8_A1, SADD8_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SADD8_A1, SADD8_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SADD8_A1, SADD8_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SADD8_A1, SADD8_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SADD8_A1, SADD8_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SADD8/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    sum1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;7:0&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;7:0&gt;);</line>
<line>    sum2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:8&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:8&gt;);</line>
<line>    sum3 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;23:16&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;23:16&gt;);</line>
<line>    sum4 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:24&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:24&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;7:0&gt;   = sum1&lt;7:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:8&gt;  = sum2&lt;7:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;23:16&gt; = sum3&lt;7:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:24&gt; = sum4&lt;7:0&gt;;</line>
<line>    PSTATE.GE&lt;0&gt;  = if sum1 &gt;= 0 then '1' else '0';</line>
<line>    PSTATE.GE&lt;1&gt;  = if sum2 &gt;= 0 then '1' else '0';</line>
<line>    PSTATE.GE&lt;2&gt;  = if sum3 &gt;= 0 then '1' else '0';</line>
<line>    PSTATE.GE&lt;3&gt;  = if sum4 &gt;= 0 then '1' else '0';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sasx.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SASX" title="SASX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SASX" />
  </docvars>
  <heading>SASX</heading>
  <desc>
    <brief>
      <para>Signed Add and Subtract with Exchange</para>
    </brief>
    <authored>
      <para>Signed Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer addition and one 16-bit subtraction, and writes the results to the destination register. It sets <xref linkend="BEIDIGBH">PSTATE</xref>.GE according to the results.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SASX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SASX/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SASX_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SASX" />
        </docvars>
        <asmtemplate><text>SASX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SASX/A1_A.txt" mylink="aarch32.instrs.SASX.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SASX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SASX/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SASX_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SASX" />
        </docvars>
        <asmtemplate><text>SASX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SASX/T1_A.txt" mylink="aarch32.instrs.SASX.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SASX_A1, SASX_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SASX_A1, SASX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SASX_A1, SASX_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SASX_A1, SASX_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SASX_A1, SASX_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SASX/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    diff = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    sum  = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = diff&lt;15:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = sum&lt;15:0&gt;;</line>
<line>    PSTATE.GE&lt;1:0&gt; = if diff &gt;= 0 then '11' else '00';</line>
<line>    PSTATE.GE&lt;3:2&gt; = if sum  &gt;= 0 then '11' else '00';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SB" title="SB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SB" />
  </docvars>
  <heading>SB</heading>
  <desc>
    <brief>
      <para>Speculation Barrier</para>
    </brief>
    <authored>
      <para>Speculation Barrier is a barrier that controls speculation.</para>
      <para>The semantics of the Speculation Barrier are that the execution, until the barrier completes, of any instruction that appears later in the program order than the barrier:</para>
      <list type="unordered">
        <listitem><content>Cannot be performed speculatively to the extent that such speculation can be observed through side-channels as a result of control flow speculation or data value speculation.</content></listitem>
        <listitem><content>Can be speculatively executed as a result of predicting that a potentially exception generating instruction has not generated an exception.</content></listitem>
      </list>
      <para>In particular, any instruction that appears later in the program order than the barrier cannot cause a speculative allocation into any caching structure where the allocation of that entry could be indicative of any data value present in memory or in the registers.</para>
      <para>The SB instruction:</para>
      <list type="unordered">
        <listitem><content>Cannot be speculatively executed as a result of control flow speculation or data value speculation.</content></listitem>
        <listitem><content>Can be speculatively executed as a result of predicting that a potentially exception generating instruction has not generated an exception. The potentially exception generating instruction can complete once it is known not to be speculative, and all data values generated by instructions appearing in program order before the SB instruction have their predicted values confirmed.</content></listitem>
      </list>
      <para>When the prediction of the instruction stream is not informed by data taken from the register outputs of the speculative execution of instructions appearing in program order after an uncompleted SB instruction, the SB instruction has no effect on the use of prediction resources to predict the instruction stream that is being fetched.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.5" feature="FEAT_SB" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/SB/A1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" name="opcode" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="option" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="SB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SB" />
        </docvars>
        <asmtemplate><text>SB</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SB/A1_A.txt" mylink="aarch32.instrs.SB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.5" feature="FEAT_SB" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/SB/T1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="option" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="SB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SB" />
        </docvars>
        <asmtemplate><text>SB</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SB/T1_A.txt" mylink="aarch32.instrs.SB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SB_A1, SB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-shared.SpeculationBarrier.0" file="shared_pseudocode.xml" hover="function: SpeculationBarrier()">SpeculationBarrier</a>();</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sbc_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SBC_i" title="SBC, SBCS (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SBC, SBCS (immediate)</heading>
  <desc>
    <brief>
      <para>Subtract with Carry (immediate)</para>
    </brief>
    <authored>
      <para>Subtract with Carry (immediate) subtracts an immediate value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the SBCS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. ARM deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The SBC variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The SBCS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SBC_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="SBC_i_A1" oneofinclass="2" oneof="4" label="SBC" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SBC" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>SBC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SBCS_i_A1" oneofinclass="2" oneof="4" label="SBCS" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SBCS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>SBCS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SBC_i/A1_A.txt" mylink="aarch32.instrs.SBC_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = (S == '1');  imm32 = <a link="impl-aarch32.A32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) A32ExpandImm(bits(12) imm12)">A32ExpandImm</a>(imm12);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SBC_i/T1_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="SBC_i_T1" oneofinclass="2" oneof="4" label="SBC" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SBC" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>SBC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SBCS_i_T1" oneofinclass="2" oneof="4" label="SBCS" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SBCS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>SBCS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SBC_i/T1_A.txt" mylink="aarch32.instrs.SBC_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = (S == '1');  imm32 = <a link="impl-aarch32.T32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) T32ExpandImm(bits(12) imm12)">T32ExpandImm</a>(i:imm3:imm8);</line>
<line>if d == 15 || n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SBC_i_A1, SBC_i_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBC_i_A1, SBC_i_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBC_i_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the SBC variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the SBCS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBC_i_T1" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBC_i_A1" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBC_i_T1" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBC_i_A1" symboldefcount="1">
      <symbol link="sa_const_1">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: an immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBC_i_T1" symboldefcount="2">
      <symbol link="sa_const">&lt;const&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: an immediate value. See <xref linkend="BABGHAGA">Modified immediate constants in T32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SBC_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], NOT(imm32), PSTATE.C);</line>
<line>    if d == 15 then          // Can only occur for A32 encoding</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sbc_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SBC_r" title="SBC, SBCS (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SBC, SBCS (register)</heading>
  <desc>
    <brief>
      <para>Subtract with Carry (register)</para>
    </brief>
    <authored>
      <para>Subtract with Carry (register) subtracts an optionally-shifted register value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the SBCS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. ARM deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The SBC variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The SBCS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SBC_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SBC_r_A1_RRX" oneofinclass="4" oneof="9" label="SBC, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SBC" />
          <docvar key="mnemonic-shift-type" value="SBC-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>SBC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="SBC_r_A1" oneofinclass="4" oneof="9" label="SBC, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SBC" />
          <docvar key="mnemonic-shift-type" value="SBC-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>SBC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="SBCS_r_A1_RRX" oneofinclass="4" oneof="9" label="SBCS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SBCS" />
          <docvar key="mnemonic-shift-type" value="SBCS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>SBCS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="SBCS_r_A1" oneofinclass="4" oneof="9" label="SBCS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SBCS" />
          <docvar key="mnemonic-shift-type" value="SBCS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>SBCS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SBC_r/A1_A.txt" mylink="aarch32.instrs.SBC_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SBC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/SBC_r/T1_A.txt">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="4" name="op" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rdn" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="SBC_r_T1" oneofinclass="1" oneof="9" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SBC" />
        </docvars>
        <asmtemplate comment="Inside IT block"><text>SBC</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate comment="Outside IT block"><text>SBCS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdn" hover="First general-purpose source register and the destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SBC_r/T1_A.txt" mylink="aarch32.instrs.SBC_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdn);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>();</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SBC_r/T2_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SBC_r_T2_RRX" oneofinclass="4" oneof="9" label="SBC, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SBC" />
          <docvar key="mnemonic-shift-type" value="SBC-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>SBC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="SBC_r_T2" oneofinclass="4" oneof="9" label="SBC, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SBC" />
          <docvar key="mnemonic-shift-type" value="SBC-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Inside IT block, and &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>SBC</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>SBC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="SBCS_r_T2_RRX" oneofinclass="4" oneof="9" label="SBCS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SBCS" />
          <docvar key="mnemonic-shift-type" value="SBCS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>SBCS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="SBCS_r_T2" oneofinclass="4" oneof="9" label="SBCS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SBCS" />
          <docvar key="mnemonic-shift-type" value="SBCS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Outside IT block, and &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>SBCS.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>SBCS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SBC_r/T2_A.txt" mylink="aarch32.instrs.SBC_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm3:imm2);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SBC_r_A1, SBC_r_T1, SBC_r_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBC_r_A1, SBC_r_T1, SBC_r_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBC_r_T1" symboldefcount="1">
      <symbol link="sa_rdn">&lt;Rdn&gt;</symbol>
      <account encodedin="Rdn">
        <intro>
          <para>Is the first general-purpose source register and the destination register, encoded in the "Rdn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBC_r_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the SBC variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the SBCS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBC_r_T2" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBC_r_A1" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBC_r_T2" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBC_r_A1" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="SBC-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBC_r_T1, SBC_r_T2" symboldefcount="2">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBC_r_A1, SBC_r_T2" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="SBC_r_A1" symboldefcount="1">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBC_r_T2" symboldefcount="2">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm3:imm2" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SBC_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], NOT(shifted), PSTATE.C);</line>
<line>    if d == 15 then          // Can only occur for A32 encoding</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sbc_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SBC_rr" title="SBC, SBCS (register-shifted register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
  </docvars>
  <heading>SBC, SBCS (register-shifted register)</heading>
  <desc>
    <brief>
      <para>Subtract with Carry (register-shifted register)</para>
    </brief>
    <authored>
      <para>Subtract with Carry (register-shifted register) subtracts a register-shifted register value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SBC_rr/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SBCS_rr_A1" oneofinclass="2" oneof="2" label="Flag setting" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SBCS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>SBCS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="Third general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SBC_rr_A1" oneofinclass="2" oneof="2" label="Not flag setting" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SBC" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>SBC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="Third general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SBC_rr/A1_A.txt" mylink="aarch32.instrs.SBC_rr.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);</line>
<line>setflags = (S == '1');  shift_t = <a link="impl-aarch32.DecodeRegShift.1" file="shared_pseudocode.xml" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</a>(stype);</line>
<line>if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SBC_rr_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBC_rr_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBC_rr_A1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBC_rr_A1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBC_rr_A1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBC_rr_A1" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="SBC_rr_A1" symboldefcount="1">
      <symbol link="sa_rs">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the third general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SBC_rr/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shift_n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[s]&lt;7:0&gt;);</line>
<line>    shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], NOT(shifted), PSTATE.C);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>    if setflags then</line>
<line>        PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sbfx.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SBFX" title="SBFX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SBFX" />
  </docvars>
  <heading>SBFX</heading>
  <desc>
    <brief>
      <para>Signed Bit Field Extract</para>
    </brief>
    <authored>
      <para>Signed Bit Field Extract extracts any number of adjacent bits at any position from a register, sign-extends them to 32 bits, and writes the result to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SBFX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SBFX/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="widthm1" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="lsb" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SBFX_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SBFX" />
        </docvars>
        <asmtemplate><text>SBFX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_lsb_1" hover="Bit number of least significant bit in the field [0-31] (field &quot;lsb&quot;)">&lt;lsb&gt;</a><text>, #</text><a link="sa_width" hover="Width of field [1-32-&lt;lsb&gt;] (field &quot;widthm1&quot;)">&lt;width&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SBFX/A1_A.txt" mylink="aarch32.instrs.SBFX.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>lsbit = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(lsb);  widthminus1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(widthm1);</line>
<line>msbit = lsbit + widthminus1;</line>
<line>if d == 15 || n == 15 then UNPREDICTABLE;</line>
<line>if msbit &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>msbit &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SBFX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SBFX/T1_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" width="2" name="op1&lt;2:1&gt;" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="21" name="op1&lt;0&gt;" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" width="5" name="widthm1" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="SBFX_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SBFX" />
        </docvars>
        <asmtemplate><text>SBFX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_lsb" hover="Bit number of least significant bit in the field [0-31] (field &quot;imm3:imm2&quot;)">&lt;lsb&gt;</a><text>, #</text><a link="sa_width" hover="Width of field [1-32-&lt;lsb&gt;] (field &quot;widthm1&quot;)">&lt;width&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SBFX/T1_A.txt" mylink="aarch32.instrs.SBFX.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>lsbit = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm3:imm2);  widthminus1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(widthm1);</line>
<line>msbit = lsbit + widthminus1;</line>
<line>if d == 15 || n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
<line>if msbit &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>msbit &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SBFX_A1, SBFX_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBFX_A1, SBFX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBFX_A1, SBFX_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBFX_A1, SBFX_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBFX_A1" symboldefcount="1">
      <symbol link="sa_lsb_1">&lt;lsb&gt;</symbol>
      <account encodedin="lsb">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the bit number of the least significant bit in the field, in the range 0 to 31, encoded in the "lsb" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBFX_T1" symboldefcount="2">
      <symbol link="sa_lsb">&lt;lsb&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the bit number of the least significant bit in the field, in the range 0 to 31, encoded in the "imm3:imm2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SBFX_A1, SBFX_T1" symboldefcount="1">
      <symbol link="sa_width">&lt;width&gt;</symbol>
      <account encodedin="widthm1">
        <intro>
          <para>Is the width of the field, in the range 1 to 32-&lt;lsb&gt;, encoded in the "widthm1" field as &lt;width&gt;-1.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SBFX/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;msbit:lsbit&gt;, 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sdiv.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SDIV" title="SDIV -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SDIV" />
  </docvars>
  <heading>SDIV</heading>
  <desc>
    <brief>
      <para>Signed Divide</para>
    </brief>
    <authored>
      <para>Signed Divide divides a 32-bit signed integer register value by a 32-bit signed integer register value, and writes the result to the destination register. The condition flags are not affected.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>Overflow</para>
      <para>If the signed integer division <hexnumber>0x80000000</hexnumber> / <hexnumber>0xFFFFFFFF</hexnumber> is performed, the pseudocode produces the intermediate integer result +2<sup>31</sup>, that overflows the 32-bit signed integer range. No indication of this overflow case is produced, and the 32-bit result written to <syntax>&lt;Rd&gt;</syntax> must be the bottom 32 bits of the binary representation of +2<sup>31</sup>. So the result of the division is <hexnumber>0x80000000</hexnumber>.</para>
    </syntaxnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SDIV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SDIV/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="3" name="op2" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SDIV_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SDIV" />
        </docvars>
        <asmtemplate><text>SDIV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register holding dividend (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding divisor (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SDIV/A1_A.txt" mylink="aarch32.instrs.SDIV.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);</line>
<line>if d == 15 || n == 15 || m == 15 || a != 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>Ra != '1111'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_NONE" />
          <cu_type>
            <cu_type_text>The instruction executes as described, and the register specified by Ra becomes <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SDIV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SDIV/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" name="op2" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SDIV_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SDIV" />
        </docvars>
        <asmtemplate><text>SDIV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register holding dividend (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding divisor (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SDIV/T1_A.txt" mylink="aarch32.instrs.SDIV.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
<line>if d == 15 || n == 15 || m == 15 || a != 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>Ra != '1111'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_NONE" />
          <cu_type>
            <cu_type_text>The instruction executes as described, and the register specified by Ra becomes <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SDIV_A1, SDIV_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SDIV_A1, SDIV_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SDIV_A1, SDIV_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SDIV_A1, SDIV_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register holding the dividend, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SDIV_A1, SDIV_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register holding the divisor, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SDIV/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    integer result;</line>
<line>    if <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]) == 0 then</line>
<line>        result = 0;</line>
<line>    else</line>
<line>        result = <a link="impl-shared.RoundTowardsZero.1" file="shared_pseudocode.xml" hover="function: integer RoundTowardsZero(real x)">RoundTowardsZero</a>(Real(<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n])) / Real(<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m])));</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result&lt;31:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sel.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SEL" title="SEL -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SEL" />
  </docvars>
  <heading>SEL</heading>
  <desc>
    <brief>
      <para>Select Bytes</para>
    </brief>
    <authored>
      <para>Select Bytes selects each byte of its result from either its first operand or its second operand, according to the values of the <xref linkend="BEIDIGBH">PSTATE</xref>.GE flags.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SEL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SEL/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="8" settings="8">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SEL_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SEL" />
        </docvars>
        <asmtemplate><text>SEL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SEL/A1_A.txt" mylink="aarch32.instrs.SEL.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SEL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SEL/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SEL_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SEL" />
        </docvars>
        <asmtemplate><text>SEL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SEL/T1_A.txt" mylink="aarch32.instrs.SEL.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SEL_A1, SEL_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SEL_A1, SEL_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SEL_A1, SEL_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SEL_A1, SEL_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SEL_A1, SEL_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SEL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;7:0&gt;   = if PSTATE.GE&lt;0&gt; == '1' then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;7:0&gt;   else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;7:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:8&gt;  = if PSTATE.GE&lt;1&gt; == '1' then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:8&gt;  else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:8&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;23:16&gt; = if PSTATE.GE&lt;2&gt; == '1' then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;23:16&gt; else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;23:16&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:24&gt; = if PSTATE.GE&lt;3&gt; == '1' then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:24&gt; else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:24&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="setend.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SETEND" title="SETEND -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SETEND" />
  </docvars>
  <heading>SETEND</heading>
  <desc>
    <brief>
      <para>Set Endianness</para>
    </brief>
    <authored>
      <para>Set Endianness writes a new value to <xref linkend="BEIDIGBH">PSTATE</xref>.E.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SETEND" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SETEND/A1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="2" name="imod" settings="2">
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="17" name="M" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="16" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" name="E" usename="1">
          <c></c>
        </box>
        <box hibit="8" name="A" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" name="I" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="F" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" width="5" name="mode" settings="5">
          <c>0</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="SETEND_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SETEND" />
        </docvars>
        <asmtemplate comment="Cannot be conditional"><text>SETEND</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_endian_specifier" hover="Endianness to be selected, and the value to be set in PSTATE (field &quot;E&quot;)">&lt;endian_specifier&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SETEND/A1_A.txt" mylink="aarch32.instrs.SETEND.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>set_bigend = (E == '1');</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SETEND" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/SETEND/T1_A.txt">
        <box hibit="31" width="10" settings="10">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="21" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="19" name="E" usename="1">
          <c></c>
        </box>
        <box hibit="18" width="3" settings="3">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="SETEND_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SETEND" />
        </docvars>
        <asmtemplate comment="Not permitted in IT block"><text>SETEND</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_endian_specifier" hover="Endianness to be selected, and the value to be set in PSTATE (field &quot;E&quot;)">&lt;endian_specifier&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SETEND/T1_A.txt" mylink="aarch32.instrs.SETEND.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>set_bigend = (E == '1');</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SETEND_A1, SETEND_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SETEND_A1, SETEND_T1" symboldefcount="1">
      <symbol link="sa_endian_specifier">&lt;endian_specifier&gt;</symbol>
      <definition encodedin="E">
        <intro>Is the endianness to be selected, and the value to be set in PSTATE.E, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">E</entry>
                <entry class="symbol">&lt;endian_specifier&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">LE</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">BE</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SETEND/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations();</line>
<line><a link="AArch32.CheckSETENDEnabled.0" file="shared_pseudocode.xml" hover="function: AArch32.CheckSETENDEnabled()">AArch32.CheckSETENDEnabled</a>();</line>
<line>PSTATE.E = if set_bigend then '1' else '0';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="setpan.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SETPAN" title="SETPAN -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SETPAN" />
  </docvars>
  <heading>SETPAN</heading>
  <desc>
    <brief>
      <para>Set Privileged Access Never</para>
    </brief>
    <authored>
      <para>Set Privileged Access Never writes a new value to <xref linkend="BEIDIGBH">PSTATE</xref>.PAN.</para>
      <para>This instruction is available only in privileged mode and it is a NOP when executed in User mode.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SETPAN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.1" feature="FEAT_PAN" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/SETPAN/A1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" name="imm1" usename="1">
          <c></c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="SETPAN_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SETPAN" />
        </docvars>
        <asmtemplate comment="Cannot be conditional"><text>SETPAN</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> #</text><a link="sa_imm" hover="Unsigned immediate 0 or 1 (field &quot;imm1&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SETPAN/A1_A.txt" mylink="aarch32.instrs.SETPAN.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HavePANExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePANExt()">HavePANExt</a>() then UNDEFINED;</line>
<line>value = imm1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SETPAN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.1" feature="FEAT_PAN" />
      </arch_variants>
      <regdiagram form="16" psname="aarch32/instrs/SETPAN/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="19" name="imm1" usename="1">
          <c></c>
        </box>
        <box hibit="18" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="SETPAN_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SETPAN" />
        </docvars>
        <asmtemplate comment="Not permitted in IT block"><text>SETPAN</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> #</text><a link="sa_imm" hover="Unsigned immediate 0 or 1 (field &quot;imm1&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SETPAN/T1_A.txt" mylink="aarch32.instrs.SETPAN.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HavePANExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePANExt()">HavePANExt</a>() then UNDEFINED;</line>
<line>value = imm1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SETPAN_A1, SETPAN_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SETPAN_A1, SETPAN_T1" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm1">
        <intro>
          <para>Is the unsigned immediate 0 or 1, encoded in the "imm1" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SETPAN/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations();</line>
<line>if PSTATE.EL != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>    PSTATE.PAN = value;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sev.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SEV" title="SEV -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SEV" />
  </docvars>
  <heading>SEV</heading>
  <desc>
    <brief>
      <para>Send Event</para>
    </brief>
    <authored>
      <para>Send Event is a hint instruction. It causes an event to be signaled to all PEs in the multiprocessor system. For more information, see <xref linkend="CFIJIIHE">Wait For Event and Send Event</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SEV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SEV/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="R" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="2" name="imm4&lt;3:2&gt;" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="17" width="2" name="imm4&lt;1:0&gt;" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" width="12" name="imm12" settings="12">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="SEV_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SEV" />
        </docvars>
        <asmtemplate><text>SEV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SEV/A1_A.txt" mylink="aarch32.instrs.SEV.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SEV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/SEV/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" width="4" name="hint" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="SEV_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SEV" />
        </docvars>
        <asmtemplate><text>SEV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SEV/T1_A.txt" mylink="aarch32.instrs.SEV.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SEV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SEV/T2_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="hint" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="option" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="SEV_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SEV" />
        </docvars>
        <asmtemplate><text>SEV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SEV/T2_A.txt" mylink="aarch32.instrs.SEV.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SEV_A1, SEV_T1, SEV_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SEV_A1, SEV_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SEV/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-shared.SendEvent.0" file="shared_pseudocode.xml" hover="function: SendEvent()">SendEvent</a>();</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sevl.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SEVL" title="SEVL -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SEVL" />
  </docvars>
  <heading>SEVL</heading>
  <desc>
    <brief>
      <para>Send Event Local</para>
    </brief>
    <authored>
      <para>Send Event Local is a hint instruction that causes an event to be signaled locally without requiring the event to be signaled to other PEs in the multiprocessor system. It can prime a wait-loop which starts with a <instruction>WFE</instruction> instruction.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SEVL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SEVL/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="R" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="2" name="imm4&lt;3:2&gt;" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="17" width="2" name="imm4&lt;1:0&gt;" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" width="12" name="imm12" settings="12">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="SEVL_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SEVL" />
        </docvars>
        <asmtemplate><text>SEVL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SEVL/A1_A.txt" mylink="aarch32.instrs.SEVL.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SEVL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/SEVL/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" width="4" name="hint" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="SEVL_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SEVL" />
        </docvars>
        <asmtemplate><text>SEVL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SEVL/T1_A.txt" mylink="aarch32.instrs.SEVL.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SEVL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SEVL/T2_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="hint" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="option" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="SEVL_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SEVL" />
        </docvars>
        <asmtemplate><text>SEVL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SEVL/T2_A.txt" mylink="aarch32.instrs.SEVL.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SEVL_A1, SEVL_T1, SEVL_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SEVL_A1, SEVL_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SEVL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-shared.SendEventLocal.0" file="shared_pseudocode.xml" hover="function: SendEventLocal()">SendEventLocal</a>();</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sha1c.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SHA1C" title="SHA1C -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="SHA1C" />
  </docvars>
  <heading>SHA1C</heading>
  <desc>
    <brief>
      <para>SHA1 hash update (choose)</para>
    </brief>
    <authored>
      <para>SHA1 hash update (choose).</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SHA1C" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_SHA1" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/SHA1C/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHA1C_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SHA1C" />
        </docvars>
        <asmtemplate><text>SHA1C.32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHA1C/A1_A.txt" mylink="aarch32.instrs.SHA1C.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveSHA1Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA1Ext()">HaveSHA1Ext</a>() then UNDEFINED;</line>
<line>if Q != '1' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SHA1C" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_SHA1" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/SHA1C/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHA1C_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SHA1C" />
        </docvars>
        <asmtemplate><text>SHA1C.32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHA1C/T1_A.txt" mylink="aarch32.instrs.SHA1C.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveSHA1Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA1Ext()">HaveSHA1Ext</a>() then UNDEFINED;</line>
<line>if Q != '1' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SHA1C_A1, SHA1C_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHA1C_A1, SHA1C_T1" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHA1C_A1, SHA1C_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SHA1C/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations(); <a link="impl-aarch32.CheckCryptoEnabled32.0" file="shared_pseudocode.xml" hover="function: CheckCryptoEnabled32()">CheckCryptoEnabled32</a>();</line>
<line>    x = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[d&gt;&gt;1];</line>
<line>    y = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[n&gt;&gt;1]&lt;31:0&gt;; // Note: 32 bits wide</line>
<line>    w = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1];</line>
<line>    for e = 0 to 3</line>
<line>        t = <a link="impl-shared.SHAchoose.3" file="shared_pseudocode.xml" hover="function: bits(32) SHAchoose(bits(32) x, bits(32) y, bits(32) z)">SHAchoose</a>(x&lt;63:32&gt;, x&lt;95:64&gt;, x&lt;127:96&gt;);</line>
<line>        y = y + <a link="impl-shared.ROL.2" file="shared_pseudocode.xml" hover="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(x&lt;31:0&gt;, 5) + t + <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[w, e, 32];</line>
<line>        x&lt;63:32&gt; = <a link="impl-shared.ROL.2" file="shared_pseudocode.xml" hover="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(x&lt;63:32&gt;, 30);</line>
<line>        &lt;y, x&gt; = <a link="impl-shared.ROL.2" file="shared_pseudocode.xml" hover="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(y:x, 32);</line>
<line>    <a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = x;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sha1h.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SHA1H" title="SHA1H -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="SHA1H" />
  </docvars>
  <heading>SHA1H</heading>
  <desc>
    <brief>
      <para>SHA1 fixed rotate</para>
    </brief>
    <authored>
      <para>SHA1 fixed rotate.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SHA1H" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_SHA1" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/SHA1H/A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHA1H_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SHA1H" />
        </docvars>
        <asmtemplate><text>SHA1H.32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHA1H/A1_A.txt" mylink="aarch32.instrs.SHA1H.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveSHA1Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA1Ext()">HaveSHA1Ext</a>() then UNDEFINED;</line>
<line>if size != '10' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SHA1H" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_SHA1" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/SHA1H/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHA1H_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SHA1H" />
        </docvars>
        <asmtemplate><text>SHA1H.32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHA1H/T1_A.txt" mylink="aarch32.instrs.SHA1H.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveSHA1Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA1Ext()">HaveSHA1Ext</a>() then UNDEFINED;</line>
<line>if size != '10' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SHA1H_A1, SHA1H_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHA1H_A1, SHA1H_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SHA1H/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations(); <a link="impl-aarch32.CheckCryptoEnabled32.0" file="shared_pseudocode.xml" hover="function: CheckCryptoEnabled32()">CheckCryptoEnabled32</a>();</line>
<line>    <a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-shared.ROL.2" file="shared_pseudocode.xml" hover="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(<a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1]&lt;31:0&gt;, 30), 128);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sha1m.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SHA1M" title="SHA1M -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="SHA1M" />
  </docvars>
  <heading>SHA1M</heading>
  <desc>
    <brief>
      <para>SHA1 hash update (majority)</para>
    </brief>
    <authored>
      <para>SHA1 hash update (majority).</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SHA1M" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_SHA1" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/SHA1M/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHA1M_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SHA1M" />
        </docvars>
        <asmtemplate><text>SHA1M.32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHA1M/A1_A.txt" mylink="aarch32.instrs.SHA1M.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveSHA1Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA1Ext()">HaveSHA1Ext</a>() then UNDEFINED;</line>
<line>if Q != '1' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SHA1M" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_SHA1" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/SHA1M/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHA1M_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SHA1M" />
        </docvars>
        <asmtemplate><text>SHA1M.32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHA1M/T1_A.txt" mylink="aarch32.instrs.SHA1M.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveSHA1Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA1Ext()">HaveSHA1Ext</a>() then UNDEFINED;</line>
<line>if Q != '1' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SHA1M_A1, SHA1M_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHA1M_A1, SHA1M_T1" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHA1M_A1, SHA1M_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SHA1M/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations(); <a link="impl-aarch32.CheckCryptoEnabled32.0" file="shared_pseudocode.xml" hover="function: CheckCryptoEnabled32()">CheckCryptoEnabled32</a>();</line>
<line>    x = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[d&gt;&gt;1];</line>
<line>    y = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[n&gt;&gt;1]&lt;31:0&gt;; // Note: 32 bits wide</line>
<line>    w = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1];</line>
<line>    for e = 0 to 3</line>
<line>        t = <a link="impl-shared.SHAmajority.3" file="shared_pseudocode.xml" hover="function: bits(32) SHAmajority(bits(32) x, bits(32) y, bits(32) z)">SHAmajority</a>(x&lt;63:32&gt;, x&lt;95:64&gt;, x&lt;127:96&gt;);</line>
<line>        y = y + <a link="impl-shared.ROL.2" file="shared_pseudocode.xml" hover="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(x&lt;31:0&gt;, 5) + t + <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[w, e, 32];</line>
<line>        x&lt;63:32&gt; = <a link="impl-shared.ROL.2" file="shared_pseudocode.xml" hover="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(x&lt;63:32&gt;, 30);</line>
<line>        &lt;y, x&gt; = <a link="impl-shared.ROL.2" file="shared_pseudocode.xml" hover="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(y:x, 32);</line>
<line>    <a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = x;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sha1p.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SHA1P" title="SHA1P -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="SHA1P" />
  </docvars>
  <heading>SHA1P</heading>
  <desc>
    <brief>
      <para>SHA1 hash update (parity)</para>
    </brief>
    <authored>
      <para>SHA1 hash update (parity).</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SHA1P" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_SHA1" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/SHA1P/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHA1P_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SHA1P" />
        </docvars>
        <asmtemplate><text>SHA1P.32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHA1P/A1_A.txt" mylink="aarch32.instrs.SHA1P.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveSHA1Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA1Ext()">HaveSHA1Ext</a>() then UNDEFINED;</line>
<line>if Q != '1' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SHA1P" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_SHA1" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/SHA1P/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHA1P_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SHA1P" />
        </docvars>
        <asmtemplate><text>SHA1P.32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHA1P/T1_A.txt" mylink="aarch32.instrs.SHA1P.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveSHA1Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA1Ext()">HaveSHA1Ext</a>() then UNDEFINED;</line>
<line>if Q != '1' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SHA1P_A1, SHA1P_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHA1P_A1, SHA1P_T1" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHA1P_A1, SHA1P_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SHA1P/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations(); <a link="impl-aarch32.CheckCryptoEnabled32.0" file="shared_pseudocode.xml" hover="function: CheckCryptoEnabled32()">CheckCryptoEnabled32</a>();</line>
<line>    x = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[d&gt;&gt;1];</line>
<line>    y = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[n&gt;&gt;1]&lt;31:0&gt;; // Note: 32 bits wide</line>
<line>    w = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1];</line>
<line>    for e = 0 to 3</line>
<line>        t = <a link="impl-shared.SHAparity.3" file="shared_pseudocode.xml" hover="function: bits(32) SHAparity(bits(32) x, bits(32) y, bits(32) z)">SHAparity</a>(x&lt;63:32&gt;, x&lt;95:64&gt;, x&lt;127:96&gt;);</line>
<line>        y = y + <a link="impl-shared.ROL.2" file="shared_pseudocode.xml" hover="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(x&lt;31:0&gt;, 5) + t + <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[w, e, 32];</line>
<line>        x&lt;63:32&gt; = <a link="impl-shared.ROL.2" file="shared_pseudocode.xml" hover="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(x&lt;63:32&gt;, 30);</line>
<line>        &lt;y, x&gt; = <a link="impl-shared.ROL.2" file="shared_pseudocode.xml" hover="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(y:x, 32);</line>
<line>    <a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = x;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sha1su0.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SHA1SU0" title="SHA1SU0 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="SHA1SU0" />
  </docvars>
  <heading>SHA1SU0</heading>
  <desc>
    <brief>
      <para>SHA1 schedule update 0</para>
    </brief>
    <authored>
      <para>SHA1 schedule update 0.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SHA1SU0" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_SHA1" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/SHA1SU0/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHA1SU0_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SHA1SU0" />
        </docvars>
        <asmtemplate><text>SHA1SU0.32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHA1SU0/A1_A.txt" mylink="aarch32.instrs.SHA1SU0.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveSHA1Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA1Ext()">HaveSHA1Ext</a>() then UNDEFINED;</line>
<line>if Q != '1' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SHA1SU0" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_SHA1" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/SHA1SU0/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHA1SU0_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SHA1SU0" />
        </docvars>
        <asmtemplate><text>SHA1SU0.32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHA1SU0/T1_A.txt" mylink="aarch32.instrs.SHA1SU0.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveSHA1Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA1Ext()">HaveSHA1Ext</a>() then UNDEFINED;</line>
<line>if Q != '1' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SHA1SU0_A1, SHA1SU0_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHA1SU0_A1, SHA1SU0_T1" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHA1SU0_A1, SHA1SU0_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SHA1SU0/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations(); <a link="impl-aarch32.CheckCryptoEnabled32.0" file="shared_pseudocode.xml" hover="function: CheckCryptoEnabled32()">CheckCryptoEnabled32</a>();</line>
<line>    op1 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[d&gt;&gt;1]; op2 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[n&gt;&gt;1]; op3 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1];</line>
<line>    op2 = op2&lt;63:0&gt; : op1&lt;127:64&gt;;</line>
<line>    <a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = op1 EOR op2 EOR op3;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sha1su1.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SHA1SU1" title="SHA1SU1 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="SHA1SU1" />
  </docvars>
  <heading>SHA1SU1</heading>
  <desc>
    <brief>
      <para>SHA1 schedule update 1</para>
    </brief>
    <authored>
      <para>SHA1 schedule update 1.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SHA1SU1" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_SHA1" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/SHA1SU1/A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHA1SU1_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SHA1SU1" />
        </docvars>
        <asmtemplate><text>SHA1SU1.32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHA1SU1/A1_A.txt" mylink="aarch32.instrs.SHA1SU1.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveSHA1Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA1Ext()">HaveSHA1Ext</a>() then UNDEFINED;</line>
<line>if size != '10' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SHA1SU1" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_SHA1" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/SHA1SU1/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHA1SU1_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SHA1SU1" />
        </docvars>
        <asmtemplate><text>SHA1SU1.32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHA1SU1/T1_A.txt" mylink="aarch32.instrs.SHA1SU1.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveSHA1Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA1Ext()">HaveSHA1Ext</a>() then UNDEFINED;</line>
<line>if size != '10' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SHA1SU1_A1, SHA1SU1_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHA1SU1_A1, SHA1SU1_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SHA1SU1/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations(); <a link="impl-aarch32.CheckCryptoEnabled32.0" file="shared_pseudocode.xml" hover="function: CheckCryptoEnabled32()">CheckCryptoEnabled32</a>();</line>
<line>    X = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[d&gt;&gt;1]; Y = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1];</line>
<line>    T = X EOR <a link="impl-shared.LSR.2" file="shared_pseudocode.xml" hover="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(Y, 32);</line>
<line>    W0 = <a link="impl-shared.ROL.2" file="shared_pseudocode.xml" hover="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(T&lt;31:0&gt;, 1);</line>
<line>    W1 = <a link="impl-shared.ROL.2" file="shared_pseudocode.xml" hover="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(T&lt;63:32&gt;, 1);</line>
<line>    W2 = <a link="impl-shared.ROL.2" file="shared_pseudocode.xml" hover="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(T&lt;95:64&gt;, 1);</line>
<line>    W3 = <a link="impl-shared.ROL.2" file="shared_pseudocode.xml" hover="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(T&lt;127:96&gt;, 1) EOR <a link="impl-shared.ROL.2" file="shared_pseudocode.xml" hover="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(T&lt;31:0&gt;, 2);</line>
<line>    <a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = W3:W2:W1:W0;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sha256h.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SHA256H" title="SHA256H -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="SHA256H" />
  </docvars>
  <heading>SHA256H</heading>
  <desc>
    <brief>
      <para>SHA256 hash update part 1</para>
    </brief>
    <authored>
      <para>SHA256 hash update part 1.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SHA256H" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_SHA256" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/SHA256H/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHA256H_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SHA256H" />
        </docvars>
        <asmtemplate><text>SHA256H.32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHA256H/A1_A.txt" mylink="aarch32.instrs.SHA256H.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveSHA256Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA256Ext()">HaveSHA256Ext</a>() then UNDEFINED;</line>
<line>if Q != '1' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SHA256H" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_SHA256" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/SHA256H/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHA256H_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SHA256H" />
        </docvars>
        <asmtemplate><text>SHA256H.32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHA256H/T1_A.txt" mylink="aarch32.instrs.SHA256H.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveSHA256Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA256Ext()">HaveSHA256Ext</a>() then UNDEFINED;</line>
<line>if Q != '1' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SHA256H_A1, SHA256H_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHA256H_A1, SHA256H_T1" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHA256H_A1, SHA256H_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SHA256H/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations(); <a link="impl-aarch32.CheckCryptoEnabled32.0" file="shared_pseudocode.xml" hover="function: CheckCryptoEnabled32()">CheckCryptoEnabled32</a>();</line>
<line>    X = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[d&gt;&gt;1]; Y = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[n&gt;&gt;1]; W = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1]; part1 = TRUE;</line>
<line>    <a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = <a link="impl-shared.SHA256hash.4" file="shared_pseudocode.xml" hover="function: bits(128) SHA256hash(bits (128) x_in, bits(128) y_in, bits(128) w, boolean part1)">SHA256hash</a>(X, Y, W, part1);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sha256h2.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SHA256H2" title="SHA256H2 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="SHA256H2" />
  </docvars>
  <heading>SHA256H2</heading>
  <desc>
    <brief>
      <para>SHA256 hash update part 2</para>
    </brief>
    <authored>
      <para>SHA256 hash update part 2.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SHA256H2" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_SHA256" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/SHA256H2/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHA256H2_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SHA256H2" />
        </docvars>
        <asmtemplate><text>SHA256H2.32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHA256H2/A1_A.txt" mylink="aarch32.instrs.SHA256H2.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveSHA256Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA256Ext()">HaveSHA256Ext</a>() then UNDEFINED;</line>
<line>if Q != '1' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SHA256H2" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_SHA256" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/SHA256H2/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHA256H2_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SHA256H2" />
        </docvars>
        <asmtemplate><text>SHA256H2.32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHA256H2/T1_A.txt" mylink="aarch32.instrs.SHA256H2.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveSHA256Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA256Ext()">HaveSHA256Ext</a>() then UNDEFINED;</line>
<line>if Q != '1' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SHA256H2_A1, SHA256H2_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHA256H2_A1, SHA256H2_T1" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHA256H2_A1, SHA256H2_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SHA256H2/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations(); <a link="impl-aarch32.CheckCryptoEnabled32.0" file="shared_pseudocode.xml" hover="function: CheckCryptoEnabled32()">CheckCryptoEnabled32</a>();</line>
<line>    X = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[n&gt;&gt;1]; Y = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[d&gt;&gt;1]; W = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1]; part1 = FALSE;</line>
<line>    <a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = <a link="impl-shared.SHA256hash.4" file="shared_pseudocode.xml" hover="function: bits(128) SHA256hash(bits (128) x_in, bits(128) y_in, bits(128) w, boolean part1)">SHA256hash</a>(X, Y, W, part1);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sha256su0.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SHA256SU0" title="SHA256SU0 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="SHA256SU0" />
  </docvars>
  <heading>SHA256SU0</heading>
  <desc>
    <brief>
      <para>SHA256 schedule update 0</para>
    </brief>
    <authored>
      <para>SHA256 schedule update 0.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SHA256SU0" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_SHA256" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/SHA256SU0/A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHA256SU0_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SHA256SU0" />
        </docvars>
        <asmtemplate><text>SHA256SU0.32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHA256SU0/A1_A.txt" mylink="aarch32.instrs.SHA256SU0.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveSHA256Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA256Ext()">HaveSHA256Ext</a>() then UNDEFINED;</line>
<line>if size != '10' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SHA256SU0" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_SHA256" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/SHA256SU0/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHA256SU0_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SHA256SU0" />
        </docvars>
        <asmtemplate><text>SHA256SU0.32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHA256SU0/T1_A.txt" mylink="aarch32.instrs.SHA256SU0.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveSHA256Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA256Ext()">HaveSHA256Ext</a>() then UNDEFINED;</line>
<line>if size != '10' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SHA256SU0_A1, SHA256SU0_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHA256SU0_A1, SHA256SU0_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SHA256SU0/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    bits(128) result;</line>
<line>    EncodingSpecificOperations(); <a link="impl-aarch32.CheckCryptoEnabled32.0" file="shared_pseudocode.xml" hover="function: CheckCryptoEnabled32()">CheckCryptoEnabled32</a>();</line>
<line>    x = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[d&gt;&gt;1]; y = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1];</line>
<line>    t = y&lt;31:0&gt; : x&lt;127:32&gt;;</line>
<line>    for e = 0 to 3</line>
<line>        elt = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[t, e, 32];</line>
<line>        elt = <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(elt, 7) EOR <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(elt, 18) EOR <a link="impl-shared.LSR.2" file="shared_pseudocode.xml" hover="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(elt, 3);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = elt + <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[x, e, 32];</line>
<line>    <a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sha256su1.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SHA256SU1" title="SHA256SU1 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="SHA256SU1" />
  </docvars>
  <heading>SHA256SU1</heading>
  <desc>
    <brief>
      <para>SHA256 schedule update 1</para>
    </brief>
    <authored>
      <para>SHA256 schedule update 1.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SHA256SU1" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_SHA256" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/SHA256SU1/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHA256SU1_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SHA256SU1" />
        </docvars>
        <asmtemplate><text>SHA256SU1.32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHA256SU1/A1_A.txt" mylink="aarch32.instrs.SHA256SU1.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveSHA256Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA256Ext()">HaveSHA256Ext</a>() then UNDEFINED;</line>
<line>if Q != '1' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SHA256SU1" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.0" feature="FEAT_SHA256" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/SHA256SU1/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHA256SU1_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SHA256SU1" />
        </docvars>
        <asmtemplate><text>SHA256SU1.32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHA256SU1/T1_A.txt" mylink="aarch32.instrs.SHA256SU1.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveSHA256Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA256Ext()">HaveSHA256Ext</a>() then UNDEFINED;</line>
<line>if Q != '1' then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SHA256SU1_A1, SHA256SU1_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHA256SU1_A1, SHA256SU1_T1" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHA256SU1_A1, SHA256SU1_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SHA256SU1/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations(); <a link="impl-aarch32.CheckCryptoEnabled32.0" file="shared_pseudocode.xml" hover="function: CheckCryptoEnabled32()">CheckCryptoEnabled32</a>();</line>
<line>    bits(32) elt;</line>
<line>    bits(128) result;</line>
<line>    x = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[d&gt;&gt;1]; y = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[n&gt;&gt;1]; z = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1];</line>
<line>    T0 = z&lt;31:0&gt; : y&lt;127:32&gt;;</line>
<line></line>
<line>    T1 = z&lt;127:64&gt;;</line>
<line>    for e = 0 to 1</line>
<line>        elt = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[T1, e, 32];</line>
<line>        elt = <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(elt, 17) EOR <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(elt, 19) EOR <a link="impl-shared.LSR.2" file="shared_pseudocode.xml" hover="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(elt, 10);</line>
<line>        elt = elt + <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[x, e, 32] + <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[T0, e, 32];</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = elt;</line>
<line></line>
<line>    T1 = result&lt;63:0&gt;;</line>
<line>    for e = 2 to 3</line>
<line>        elt = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[T1, e - 2, 32];</line>
<line>        elt = <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(elt, 17) EOR <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(elt, 19) EOR <a link="impl-shared.LSR.2" file="shared_pseudocode.xml" hover="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(elt, 10);</line>
<line>        elt = elt + <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[x, e, 32] + <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[T0, e, 32];</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = elt;</line>
<line></line>
<line>    <a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="shadd16.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SHADD16" title="SHADD16 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SHADD16" />
  </docvars>
  <heading>SHADD16</heading>
  <desc>
    <brief>
      <para>Signed Halving Add 16</para>
    </brief>
    <authored>
      <para>Signed Halving Add 16 performs two signed 16-bit integer additions, halves the results, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SHADD16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SHADD16/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHADD16_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SHADD16" />
        </docvars>
        <asmtemplate><text>SHADD16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHADD16/A1_A.txt" mylink="aarch32.instrs.SHADD16.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SHADD16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SHADD16/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHADD16_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SHADD16" />
        </docvars>
        <asmtemplate><text>SHADD16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHADD16/T1_A.txt" mylink="aarch32.instrs.SHADD16.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SHADD16_A1, SHADD16_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHADD16_A1, SHADD16_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHADD16_A1, SHADD16_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHADD16_A1, SHADD16_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHADD16_A1, SHADD16_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SHADD16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    sum1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    sum2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = sum1&lt;16:1&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = sum2&lt;16:1&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="shadd8.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SHADD8" title="SHADD8 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SHADD8" />
  </docvars>
  <heading>SHADD8</heading>
  <desc>
    <brief>
      <para>Signed Halving Add 8</para>
    </brief>
    <authored>
      <para>Signed Halving Add 8 performs four signed 8-bit integer additions, halves the results, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SHADD8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SHADD8/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHADD8_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SHADD8" />
        </docvars>
        <asmtemplate><text>SHADD8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHADD8/A1_A.txt" mylink="aarch32.instrs.SHADD8.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SHADD8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SHADD8/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHADD8_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SHADD8" />
        </docvars>
        <asmtemplate><text>SHADD8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHADD8/T1_A.txt" mylink="aarch32.instrs.SHADD8.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SHADD8_A1, SHADD8_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHADD8_A1, SHADD8_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHADD8_A1, SHADD8_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHADD8_A1, SHADD8_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHADD8_A1, SHADD8_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SHADD8/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    sum1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;7:0&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;7:0&gt;);</line>
<line>    sum2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:8&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:8&gt;);</line>
<line>    sum3 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;23:16&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;23:16&gt;);</line>
<line>    sum4 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:24&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:24&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;7:0&gt;   = sum1&lt;8:1&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:8&gt;  = sum2&lt;8:1&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;23:16&gt; = sum3&lt;8:1&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:24&gt; = sum4&lt;8:1&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="shasx.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SHASX" title="SHASX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SHASX" />
  </docvars>
  <heading>SHASX</heading>
  <desc>
    <brief>
      <para>Signed Halving Add and Subtract with Exchange</para>
    </brief>
    <authored>
      <para>Signed Halving Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one signed 16-bit integer addition and one signed 16-bit subtraction, halves the results, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SHASX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SHASX/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHASX_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SHASX" />
        </docvars>
        <asmtemplate><text>SHASX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHASX/A1_A.txt" mylink="aarch32.instrs.SHASX.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SHASX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SHASX/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHASX_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SHASX" />
        </docvars>
        <asmtemplate><text>SHASX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHASX/T1_A.txt" mylink="aarch32.instrs.SHASX.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SHASX_A1, SHASX_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHASX_A1, SHASX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHASX_A1, SHASX_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHASX_A1, SHASX_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHASX_A1, SHASX_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SHASX/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    diff = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    sum  = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = diff&lt;16:1&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = sum&lt;16:1&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="shsax.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SHSAX" title="SHSAX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SHSAX" />
  </docvars>
  <heading>SHSAX</heading>
  <desc>
    <brief>
      <para>Signed Halving Subtract and Add with Exchange</para>
    </brief>
    <authored>
      <para>Signed Halving Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one signed 16-bit integer subtraction and one signed 16-bit addition, halves the results, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SHSAX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SHSAX/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHSAX_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SHSAX" />
        </docvars>
        <asmtemplate><text>SHSAX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHSAX/A1_A.txt" mylink="aarch32.instrs.SHSAX.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SHSAX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SHSAX/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHSAX_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SHSAX" />
        </docvars>
        <asmtemplate><text>SHSAX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHSAX/T1_A.txt" mylink="aarch32.instrs.SHSAX.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SHSAX_A1, SHSAX_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHSAX_A1, SHSAX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHSAX_A1, SHSAX_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHSAX_A1, SHSAX_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHSAX_A1, SHSAX_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SHSAX/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    sum  = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    diff = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = sum&lt;16:1&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = diff&lt;16:1&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="shsub16.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SHSUB16" title="SHSUB16 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SHSUB16" />
  </docvars>
  <heading>SHSUB16</heading>
  <desc>
    <brief>
      <para>Signed Halving Subtract 16</para>
    </brief>
    <authored>
      <para>Signed Halving Subtract 16 performs two signed 16-bit integer subtractions, halves the results, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SHSUB16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SHSUB16/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHSUB16_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SHSUB16" />
        </docvars>
        <asmtemplate><text>SHSUB16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHSUB16/A1_A.txt" mylink="aarch32.instrs.SHSUB16.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SHSUB16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SHSUB16/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHSUB16_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SHSUB16" />
        </docvars>
        <asmtemplate><text>SHSUB16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHSUB16/T1_A.txt" mylink="aarch32.instrs.SHSUB16.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SHSUB16_A1, SHSUB16_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHSUB16_A1, SHSUB16_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHSUB16_A1, SHSUB16_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHSUB16_A1, SHSUB16_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHSUB16_A1, SHSUB16_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SHSUB16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    diff1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    diff2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = diff1&lt;16:1&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = diff2&lt;16:1&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="shsub8.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SHSUB8" title="SHSUB8 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SHSUB8" />
  </docvars>
  <heading>SHSUB8</heading>
  <desc>
    <brief>
      <para>Signed Halving Subtract 8</para>
    </brief>
    <authored>
      <para>Signed Halving Subtract 8 performs four signed 8-bit integer subtractions, halves the results, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SHSUB8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SHSUB8/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHSUB8_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SHSUB8" />
        </docvars>
        <asmtemplate><text>SHSUB8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHSUB8/A1_A.txt" mylink="aarch32.instrs.SHSUB8.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SHSUB8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SHSUB8/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SHSUB8_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SHSUB8" />
        </docvars>
        <asmtemplate><text>SHSUB8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SHSUB8/T1_A.txt" mylink="aarch32.instrs.SHSUB8.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SHSUB8_A1, SHSUB8_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHSUB8_A1, SHSUB8_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHSUB8_A1, SHSUB8_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHSUB8_A1, SHSUB8_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHSUB8_A1, SHSUB8_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SHSUB8/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    diff1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;7:0&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;7:0&gt;);</line>
<line>    diff2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:8&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:8&gt;);</line>
<line>    diff3 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;23:16&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;23:16&gt;);</line>
<line>    diff4 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:24&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:24&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;7:0&gt;   = diff1&lt;8:1&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:8&gt;  = diff2&lt;8:1&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;23:16&gt; = diff3&lt;8:1&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:24&gt; = diff4&lt;8:1&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="smc.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SMC" title="SMC -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SMC" />
  </docvars>
  <heading>SMC</heading>
  <desc>
    <brief>
      <para>Secure Monitor Call</para>
    </brief>
    <authored>
      <para>Secure Monitor Call causes a Secure Monitor Call exception.  For more information see <xref linkend="CIHEHJBH">Secure Monitor Call (SMC) exception</xref>.</para>
      <para><instruction>SMC</instruction> is available only for software executing at EL1 or higher. It is <arm-defined-word>undefined</arm-defined-word> in User mode.</para>
      <para>If the values of <xref linkend="CEGFDIFJ">HCR</xref>.TSC and <xref linkend="CEGCEECB">SCR</xref>.SCD are both 0, execution of an <instruction>SMC</instruction> instruction at EL1 or higher generates a Secure Monitor Call exception that is taken to EL3. When EL3 is using AArch32 this exception is taken to Monitor mode. When EL3 is using AArch64, it is the <xref linkend="AArch64.scr_el3">SCR_EL3</xref>.SMD bit, rather than the <xref linkend="CEGCEECB">SCR</xref>.SCD bit, that can change the effect of executing an SMC instruction.</para>
      <para>If the value of <xref linkend="CEGFDIFJ">HCR</xref>.TSC is 1, execution of an <instruction>SMC</instruction> instruction in a Non-secure EL1 mode generates an exception that is taken to EL2, regardless of the value of <xref linkend="CEGCEECB">SCR</xref>.SCD. When EL2 is using AArch32, this is a Hyp Trap exception that is taken to Hyp mode. For more information see <xref linkend="CHDBHAEI">Traps to Hyp mode of Non-secure EL1 execution of SMC instructions</xref>.</para>
      <para>If the value of <xref linkend="CEGFDIFJ">HCR</xref>.TSC is 0 and the value of <xref linkend="CEGCEECB">SCR</xref>.SCD is 1, the SMC instruction is:</para>
      <list type="unordered">
        <listitem><content><arm-defined-word>undefined</arm-defined-word> in Non-secure state.</content></listitem>
        <listitem><content><arm-defined-word>constrained unpredictable</arm-defined-word> if executed in Secure state at EL1 or higher.</content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SMC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SMC/A1_AS.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="12" name="imm12" settings="12">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMC_A1_AS" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMC" />
        </docvars>
        <asmtemplate><text>SMC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a>{#}</a><a link="sa_imm4" hover="4-bit unsigned immediate value [0-15] (field &quot;imm4&quot;)">&lt;imm4&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMC/A1_AS.txt" mylink="aarch32.instrs.SMC.A1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// imm4 is for assembly/disassembly only and is ignored by hardware</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SMC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SMC/T1_AS.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" width="12" name="imm12" settings="12">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="SMC_T1_AS" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMC" />
        </docvars>
        <asmtemplate><text>SMC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a>{#}</a><a link="sa_imm4" hover="4-bit unsigned immediate value [0-15] (field &quot;imm4&quot;)">&lt;imm4&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMC/T1_AS.txt" mylink="aarch32.instrs.SMC.T1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// imm4 is for assembly/disassembly only and is ignored by hardware</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SMC_A1_AS, SMC_T1_AS" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMC_A1_AS, SMC_T1_AS" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMC_A1_AS, SMC_T1_AS" symboldefcount="1">
      <symbol link="sa_imm4">&lt;imm4&gt;</symbol>
      <account encodedin="imm4">
        <intro>
          <para>Is a 4-bit unsigned immediate value, in the range 0 to 15, encoded in the "imm4" field. This is ignored by the PE. The Secure Monitor Call exception handler (Secure Monitor code) can use this value to determine what service is being requested, but Arm does not recommend this.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SMC/Op_AS.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line></line>
<line>    <a link="AArch32.CheckForSMCUndefOrTrap.0" file="shared_pseudocode.xml" hover="function: AArch32.CheckForSMCUndefOrTrap()">AArch32.CheckForSMCUndefOrTrap</a>();</line>
<line></line>
<line>    if !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        if SCR_EL3.SMD == '1' then</line>
<line>            // SMC disabled.</line>
<line>            UNDEFINED;</line>
<line>    else</line>
<line>        if SCR.SCD == '1' then</line>
<line>            // SMC disabled</line>
<line>            if <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>                // Executes either as a NOP or UNALLOCATED.</line>
<line>                c = <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_SMD" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_SMD</a>);</line>
<line>                assert c IN {<a link="Constraint_NOP" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NOP</a>, <a link="Constraint_UNDEF" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNDEF</a>};</line>
<line>                if c == <a link="Constraint_NOP" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NOP</a> then <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
<line>            UNDEFINED;</line>
<line></line>
<line>    if !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        <a link="AArch64.CallSecureMonitor.1" file="shared_pseudocode.xml" hover="function: AArch64.CallSecureMonitor(bits(16) immediate)">AArch64.CallSecureMonitor</a>(<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16));</line>
<line>    else</line>
<line>        <a link="AArch32.TakeSMCException.0" file="shared_pseudocode.xml" hover="function: AArch32.TakeSMCException()">AArch32.TakeSMCException</a>();</line>
</pstext>
    </ps>
  </ps_section>
  <constrained_unpredictables ps_block="Operation">
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>SCR.SCD == '1' &amp;&amp; CurrentSecurityState() == SS_Secure</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
    </cu_case>
  </constrained_unpredictables>
</instructionsection>
</file>
<file type="instructionsection" file="smlabb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SMLABB" title="SMLABB, SMLABT, SMLATB, SMLATT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SMLABB, SMLABT, SMLATB, SMLATT</heading>
  <desc>
    <brief>
      <para>Signed Multiply Accumulate (halfwords)</para>
    </brief>
    <authored>
      <para>Signed Multiply Accumulate (halfwords) performs a signed multiply accumulate operation. The multiply acts on two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The other halves of these source registers are ignored.  The 32-bit product is added to a 32-bit accumulate value and the result is written to the destination register.</para>
      <para>If overflow occurs during the addition of the accumulate value, the instruction sets <xref linkend="BEIDIGBH">PSTATE</xref>.Q to 1. It is not possible for overflow to occur during the multiplication.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SMLABB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMLABB_A1" oneofinclass="4" oneof="8" label="SMLABB" bitdiffs="M == 0 &amp;&amp; N == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMLABB" />
        </docvars>
        <box hibit="6" width="1" name="M">
          <c>0</c>
        </box>
        <box hibit="5" width="1" name="N">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLABB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by {syntax{&lt;x&gt;}}) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLABT_A1" oneofinclass="4" oneof="8" label="SMLABT" bitdiffs="M == 1 &amp;&amp; N == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMLABT" />
        </docvars>
        <box hibit="6" width="1" name="M">
          <c>1</c>
        </box>
        <box hibit="5" width="1" name="N">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLABT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by {syntax{&lt;x&gt;}}) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLATB_A1" oneofinclass="4" oneof="8" label="SMLATB" bitdiffs="M == 0 &amp;&amp; N == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMLATB" />
        </docvars>
        <box hibit="6" width="1" name="M">
          <c>0</c>
        </box>
        <box hibit="5" width="1" name="N">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLATB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by {syntax{&lt;x&gt;}}) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLATT_A1" oneofinclass="4" oneof="8" label="SMLATT" bitdiffs="M == 1 &amp;&amp; N == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMLATT" />
        </docvars>
        <box hibit="6" width="1" name="M">
          <c>1</c>
        </box>
        <box hibit="5" width="1" name="N">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLATT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by {syntax{&lt;x&gt;}}) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMLABB/A1_A.txt" mylink="aarch32.instrs.SMLABB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);</line>
<line>n_high = (N == '1');  m_high = (M == '1');</line>
<line>if d == 15 || n == 15 || m == 15 || a == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SMLABB/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMLABB_T1" oneofinclass="4" oneof="8" label="SMLABB" bitdiffs="N == 0 &amp;&amp; M == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMLABB" />
        </docvars>
        <box hibit="5" width="1" name="N">
          <c>0</c>
        </box>
        <box hibit="4" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLABB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by {syntax{&lt;x&gt;}}) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLABT_T1" oneofinclass="4" oneof="8" label="SMLABT" bitdiffs="N == 0 &amp;&amp; M == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMLABT" />
        </docvars>
        <box hibit="5" width="1" name="N">
          <c>0</c>
        </box>
        <box hibit="4" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLABT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by {syntax{&lt;x&gt;}}) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLATB_T1" oneofinclass="4" oneof="8" label="SMLATB" bitdiffs="N == 1 &amp;&amp; M == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMLATB" />
        </docvars>
        <box hibit="5" width="1" name="N">
          <c>1</c>
        </box>
        <box hibit="4" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLATB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by {syntax{&lt;x&gt;}}) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLATT_T1" oneofinclass="4" oneof="8" label="SMLATT" bitdiffs="N == 1 &amp;&amp; M == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMLATT" />
        </docvars>
        <box hibit="5" width="1" name="N">
          <c>1</c>
        </box>
        <box hibit="4" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLATT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by {syntax{&lt;x&gt;}}) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMLABB/T1_A.txt" mylink="aarch32.instrs.SMLABB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Ra == '1111' then SEE "SMULBB, SMULBT, SMULTB, SMULTT";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);</line>
<line>n_high = (N == '1');  m_high = (M == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SMLABB_A1, SMLABB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLABB_A1, SMLABB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLABB_A1, SMLABB_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLABB_A1, SMLABB_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register holding the multiplicand in the bottom or top half (selected by <syntax>&lt;x&gt;</syntax>), encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLABB_A1, SMLABB_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register holding the multiplier in the bottom or top half (selected by <syntax>&lt;y&gt;</syntax>), encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLABB_A1, SMLABB_T1" symboldefcount="1">
      <symbol link="sa_ra">&lt;Ra&gt;</symbol>
      <account encodedin="Ra">
        <intro>
          <para>Is the third general-purpose source register holding the addend, encoded in the "Ra" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SMLABB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    operand1 = if n_high then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt; else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;;</line>
<line>    operand2 = if m_high then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt; else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;;</line>
<line>    result = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand1) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand2) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[a]);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result&lt;31:0&gt;;</line>
<line>    if result != <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(result&lt;31:0&gt;) then  // Signed overflow</line>
<line>        PSTATE.Q = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="smlad.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SMLAD" title="SMLAD, SMLADX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SMLAD, SMLADX</heading>
  <desc>
    <brief>
      <para>Signed Multiply Accumulate Dual</para>
    </brief>
    <authored>
      <para>Signed Multiply Accumulate Dual performs two signed 16 x 16-bit multiplications. It adds the products to a 32-bit accumulate operand.</para>
      <para>Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top x bottom and bottom x top multiplication.</para>
      <para>This instruction sets <xref linkend="BEIDIGBH">PSTATE</xref>.Q to 1 if the accumulate operation overflows. Overflow cannot occur during the multiplications.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SMLAD/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMLAD_A1" oneofinclass="2" oneof="4" label="SMLAD" bitdiffs="M == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMLAD" />
        </docvars>
        <box hibit="5" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLAD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLADX_A1" oneofinclass="2" oneof="4" label="SMLADX" bitdiffs="M == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMLADX" />
        </docvars>
        <box hibit="5" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLADX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMLAD/A1_A.txt" mylink="aarch32.instrs.SMLAD.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Ra == '1111' then SEE "SMUAD";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);</line>
<line>m_swap = (M == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SMLAD/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMLAD_T1" oneofinclass="2" oneof="4" label="SMLAD" bitdiffs="M == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMLAD" />
        </docvars>
        <box hibit="4" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLAD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLADX_T1" oneofinclass="2" oneof="4" label="SMLADX" bitdiffs="M == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMLADX" />
        </docvars>
        <box hibit="4" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLADX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMLAD/T1_A.txt" mylink="aarch32.instrs.SMLAD.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Ra == '1111' then SEE "SMUAD";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);</line>
<line>m_swap = (M == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SMLAD_A1, SMLAD_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLAD_A1, SMLAD_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLAD_A1, SMLAD_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLAD_A1, SMLAD_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLAD_A1, SMLAD_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLAD_A1, SMLAD_T1" symboldefcount="1">
      <symbol link="sa_ra">&lt;Ra&gt;</symbol>
      <account encodedin="Ra">
        <intro>
          <para>Is the third general-purpose source register holding the addend, encoded in the "Ra" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SMLAD/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    operand2 = if m_swap then <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m],16) else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>    product1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand2&lt;15:0&gt;);</line>
<line>    product2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand2&lt;31:16&gt;);</line>
<line>    result = product1 + product2 + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[a]);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result&lt;31:0&gt;;</line>
<line>    if result != <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(result&lt;31:0&gt;) then  // Signed overflow</line>
<line>        PSTATE.Q = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="smlal.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SMLAL" title="SMLAL, SMLALS -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SMLAL, SMLALS</heading>
  <desc>
    <brief>
      <para>Signed Multiply Accumulate Long</para>
    </brief>
    <authored>
      <para>Signed Multiply Accumulate Long multiplies two signed 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value.</para>
      <para>In A32 instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many implementations.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SMLAL/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="RdHi" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="RdLo" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMLALS_A1" oneofinclass="2" oneof="3" label="Flag setting" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMLALS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLALS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLAL_A1" oneofinclass="2" oneof="3" label="Not flag setting" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMLAL" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLAL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMLAL/A1_A.txt" mylink="aarch32.instrs.SMLAL.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>dLo = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdLo);  dHi = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdHi);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>if dHi == dLo then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>dHi == dLo</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SMLAL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SMLAL/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="RdLo" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="RdHi" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" name="op2" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMLAL_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMLAL" />
        </docvars>
        <asmtemplate><text>SMLAL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMLAL/T1_A.txt" mylink="aarch32.instrs.SMLAL.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>dLo = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdLo);  dHi = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdHi);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = FALSE;</line>
<line>if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
<line>if dHi == dLo then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>dHi == dLo</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SMLAL_A1, SMLAL_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLAL_A1, SMLAL_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLAL_A1, SMLAL_T1" symboldefcount="1">
      <symbol link="sa_rdlo">&lt;RdLo&gt;</symbol>
      <account encodedin="RdLo">
        <intro>
          <para>Is the general-purpose source register holding the lower 32 bits of the addend, and the destination register for the lower 32 bits of the result, encoded in the "RdLo" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLAL_A1, SMLAL_T1" symboldefcount="1">
      <symbol link="sa_rdhi">&lt;RdHi&gt;</symbol>
      <account encodedin="RdHi">
        <intro>
          <para>Is the general-purpose source register holding the upper 32 bits of the addend, and the destination register for the upper 32 bits of the result, encoded in the "RdHi" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLAL_A1, SMLAL_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLAL_A1, SMLAL_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register holding the multiplier, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SMLAL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    result = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[dHi]:<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[dLo]);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[dHi] = result&lt;63:32&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[dLo] = result&lt;31:0&gt;;</line>
<line>    if setflags then</line>
<line>        PSTATE.N = result&lt;63&gt;;</line>
<line>        PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result&lt;63:0&gt;);</line>
<line>        // PSTATE.C, PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="smlalbb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SMLALBB" title="SMLALBB, SMLALBT, SMLALTB, SMLALTT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SMLALBB, SMLALBT, SMLALTB, SMLALTT</heading>
  <desc>
    <brief>
      <para>Signed Multiply Accumulate Long (halfwords)</para>
    </brief>
    <authored>
      <para>Signed Multiply Accumulate Long (halfwords) multiplies two signed 16-bit values to produce a 32-bit value, and accumulates this with a 64-bit value. The multiply acts on two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The other halves of these source registers are ignored. The 32-bit product is sign-extended and accumulated with a 64-bit accumulate value.</para>
      <para>Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 2<sup>64</sup>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SMLALBB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="RdHi" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="RdLo" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMLALBB_A1" oneofinclass="4" oneof="8" label="SMLALBB" bitdiffs="M == 0 &amp;&amp; N == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMLALBB" />
        </docvars>
        <box hibit="6" width="1" name="M">
          <c>0</c>
        </box>
        <box hibit="5" width="1" name="N">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLALBB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn_1" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by {syntax{&lt;x&gt;}}) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLALBT_A1" oneofinclass="4" oneof="8" label="SMLALBT" bitdiffs="M == 1 &amp;&amp; N == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMLALBT" />
        </docvars>
        <box hibit="6" width="1" name="M">
          <c>1</c>
        </box>
        <box hibit="5" width="1" name="N">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLALBT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn_1" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by {syntax{&lt;x&gt;}}) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLALTB_A1" oneofinclass="4" oneof="8" label="SMLALTB" bitdiffs="M == 0 &amp;&amp; N == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMLALTB" />
        </docvars>
        <box hibit="6" width="1" name="M">
          <c>0</c>
        </box>
        <box hibit="5" width="1" name="N">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLALTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn_1" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by {syntax{&lt;x&gt;}}) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLALTT_A1" oneofinclass="4" oneof="8" label="SMLALTT" bitdiffs="M == 1 &amp;&amp; N == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMLALTT" />
        </docvars>
        <box hibit="6" width="1" name="M">
          <c>1</c>
        </box>
        <box hibit="5" width="1" name="N">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLALTT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn_1" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by {syntax{&lt;x&gt;}}) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMLALBB/A1_A.txt" mylink="aarch32.instrs.SMLALBB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>dLo = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdLo);  dHi = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdHi);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>n_high = (N == '1');  m_high = (M == '1');</line>
<line>if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>if dHi == dLo then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>dHi == dLo</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SMLALBB/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="RdLo" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="RdHi" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="5" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMLALBB_T1" oneofinclass="4" oneof="8" label="SMLALBB" bitdiffs="N == 0 &amp;&amp; M == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMLALBB" />
        </docvars>
        <box hibit="5" width="1" name="N">
          <c>0</c>
        </box>
        <box hibit="4" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLALBB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by &lt;x&gt;) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by &lt;x&gt;) (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLALBT_T1" oneofinclass="4" oneof="8" label="SMLALBT" bitdiffs="N == 0 &amp;&amp; M == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMLALBT" />
        </docvars>
        <box hibit="5" width="1" name="N">
          <c>0</c>
        </box>
        <box hibit="4" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLALBT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by &lt;x&gt;) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by &lt;x&gt;) (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLALTB_T1" oneofinclass="4" oneof="8" label="SMLALTB" bitdiffs="N == 1 &amp;&amp; M == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMLALTB" />
        </docvars>
        <box hibit="5" width="1" name="N">
          <c>1</c>
        </box>
        <box hibit="4" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLALTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by &lt;x&gt;) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by &lt;x&gt;) (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLALTT_T1" oneofinclass="4" oneof="8" label="SMLALTT" bitdiffs="N == 1 &amp;&amp; M == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMLALTT" />
        </docvars>
        <box hibit="5" width="1" name="N">
          <c>1</c>
        </box>
        <box hibit="4" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLALTT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by &lt;x&gt;) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by &lt;x&gt;) (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMLALBB/T1_A.txt" mylink="aarch32.instrs.SMLALBB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>dLo = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdLo);  dHi = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdHi);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>n_high = (N == '1');  m_high = (M == '1');</line>
<line>if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
<line>if dHi == dLo then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>dHi == dLo</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SMLALBB_A1, SMLALBB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLALBB_A1, SMLALBB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLALBB_A1, SMLALBB_T1" symboldefcount="1">
      <symbol link="sa_rdlo">&lt;RdLo&gt;</symbol>
      <account encodedin="RdLo">
        <intro>
          <para>Is the general-purpose source register holding the lower 32 bits of the addend, and the destination register for the lower 32 bits of the result, encoded in the "RdLo" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLALBB_A1, SMLALBB_T1" symboldefcount="1">
      <symbol link="sa_rdhi">&lt;RdHi&gt;</symbol>
      <account encodedin="RdHi">
        <intro>
          <para>Is the general-purpose source register holding the upper 32 bits of the addend, and the destination register for the upper 32 bits of the result, encoded in the "RdHi" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLALBB_A1" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the first general-purpose source register holding the multiplicand in the bottom or top half (selected by <syntax>&lt;x&gt;</syntax>), encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLALBB_T1" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the first general-purpose source register holding the multiplicand in the bottom or top half (selected by &lt;x&gt;), encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLALBB_A1" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the second general-purpose source register holding the multiplier in the bottom or top half (selected by <syntax>&lt;y&gt;</syntax>), encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLALBB_T1" symboldefcount="2">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the second general-purpose source register holding the multiplier in the bottom or top half (selected by &lt;x&gt;), encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SMLALBB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    operand1 = if n_high then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt; else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;;</line>
<line>    operand2 = if m_high then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt; else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;;</line>
<line>    result = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand1) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand2) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[dHi]:<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[dLo]);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[dHi] = result&lt;63:32&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[dLo] = result&lt;31:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="smlald.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SMLALD" title="SMLALD, SMLALDX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SMLALD, SMLALDX</heading>
  <desc>
    <brief>
      <para>Signed Multiply Accumulate Long Dual</para>
    </brief>
    <authored>
      <para>Signed Multiply Accumulate Long Dual performs two signed 16 x 16-bit multiplications. It adds the products to a 64-bit accumulate operand.</para>
      <para>Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top x bottom and bottom x top multiplication.</para>
      <para>Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 2<sup>64</sup>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SMLALD/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="RdHi" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="RdLo" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMLALD_A1" oneofinclass="2" oneof="4" label="SMLALD" bitdiffs="M == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMLALD" />
        </docvars>
        <box hibit="5" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLALD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLALDX_A1" oneofinclass="2" oneof="4" label="SMLALDX" bitdiffs="M == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMLALDX" />
        </docvars>
        <box hibit="5" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLALDX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMLALD/A1_A.txt" mylink="aarch32.instrs.SMLALD.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>dLo = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdLo);  dHi = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdHi);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  m_swap = (M == '1');</line>
<line>if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>if dHi == dLo then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>dHi == dLo</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SMLALD/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="RdLo" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="RdHi" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMLALD_T1" oneofinclass="2" oneof="4" label="SMLALD" bitdiffs="M == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMLALD" />
        </docvars>
        <box hibit="4" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLALD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLALDX_T1" oneofinclass="2" oneof="4" label="SMLALDX" bitdiffs="M == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMLALDX" />
        </docvars>
        <box hibit="4" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLALDX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMLALD/T1_A.txt" mylink="aarch32.instrs.SMLALD.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>dLo = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdLo);  dHi = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdHi);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  m_swap = (M == '1');</line>
<line>if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
<line>if dHi == dLo then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>dHi == dLo</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SMLALD_A1, SMLALD_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLALD_A1, SMLALD_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLALD_A1, SMLALD_T1" symboldefcount="1">
      <symbol link="sa_rdlo">&lt;RdLo&gt;</symbol>
      <account encodedin="RdLo">
        <intro>
          <para>Is the general-purpose source register holding the lower 32 bits of the addend, and the destination register for the lower 32 bits of the result, encoded in the "RdLo" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLALD_A1, SMLALD_T1" symboldefcount="1">
      <symbol link="sa_rdhi">&lt;RdHi&gt;</symbol>
      <account encodedin="RdHi">
        <intro>
          <para>Is the general-purpose source register holding the upper 32 bits of the addend, and the destination register for the upper 32 bits of the result, encoded in the "RdHi" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLALD_A1, SMLALD_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLALD_A1, SMLALD_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SMLALD/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    operand2 = if m_swap then <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m],16) else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>    product1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand2&lt;15:0&gt;);</line>
<line>    product2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand2&lt;31:16&gt;);</line>
<line>    result = product1 + product2 + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[dHi]:<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[dLo]);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[dHi] = result&lt;63:32&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[dLo] = result&lt;31:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="smlawb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SMLAWB" title="SMLAWB, SMLAWT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SMLAWB, SMLAWT</heading>
  <desc>
    <brief>
      <para>Signed Multiply Accumulate (word by halfword)</para>
    </brief>
    <authored>
      <para>Signed Multiply Accumulate (word by halfword) performs a signed multiply accumulate operation. The multiply acts on a signed 32-bit quantity and a signed 16-bit quantity. The signed 16-bit quantity is taken from either the bottom or the top half of its source register. The other half of the second source register is ignored. The top 32 bits of the 48-bit product are added to a 32-bit accumulate value and the result is written to the destination register. The bottom 16 bits of the 48-bit product are ignored.</para>
      <para>If overflow occurs during the addition of the accumulate value, the instruction sets <xref linkend="BEIDIGBH">PSTATE</xref>.Q to 1. No overflow can occur during the multiplication.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SMLAWB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="N" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMLAWB_A1" oneofinclass="2" oneof="4" label="SMLAWB" bitdiffs="M == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMLAWB" />
        </docvars>
        <box hibit="6" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLAWB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLAWT_A1" oneofinclass="2" oneof="4" label="SMLAWT" bitdiffs="M == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMLAWT" />
        </docvars>
        <box hibit="6" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLAWT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMLAWB/A1_A.txt" mylink="aarch32.instrs.SMLAWB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);  m_high = (M == '1');</line>
<line>if d == 15 || n == 15 || m == 15 || a == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SMLAWB/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMLAWB_T1" oneofinclass="2" oneof="4" label="SMLAWB" bitdiffs="M == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMLAWB" />
        </docvars>
        <box hibit="4" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLAWB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLAWT_T1" oneofinclass="2" oneof="4" label="SMLAWT" bitdiffs="M == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMLAWT" />
        </docvars>
        <box hibit="4" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLAWT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMLAWB/T1_A.txt" mylink="aarch32.instrs.SMLAWB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Ra == '1111' then SEE "SMULWB, SMULWT";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);  m_high = (M == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SMLAWB_A1, SMLAWB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLAWB_A1, SMLAWB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLAWB_A1, SMLAWB_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLAWB_A1, SMLAWB_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLAWB_A1, SMLAWB_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register holding the multiplier in the bottom or top half (selected by <syntax>&lt;y&gt;</syntax>), encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLAWB_A1, SMLAWB_T1" symboldefcount="1">
      <symbol link="sa_ra">&lt;Ra&gt;</symbol>
      <account encodedin="Ra">
        <intro>
          <para>Is the third general-purpose source register holding the addend, encoded in the "Ra" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SMLAWB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    operand2 = if m_high then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt; else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;;</line>
<line>    result = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand2) + (<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[a]) &lt;&lt; 16);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result&lt;47:16&gt;;</line>
<line>    if (result &gt;&gt; 16) != <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[d]) then  // Signed overflow</line>
<line>        PSTATE.Q = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="smlsd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SMLSD" title="SMLSD, SMLSDX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SMLSD, SMLSDX</heading>
  <desc>
    <brief>
      <para>Signed Multiply Subtract Dual</para>
    </brief>
    <authored>
      <para>Signed Multiply Subtract Dual performs two signed 16 x 16-bit multiplications. It adds the difference of the products to a 32-bit accumulate operand.</para>
      <para>Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top x bottom and bottom x top multiplication.</para>
      <para>This instruction sets <xref linkend="BEIDIGBH">PSTATE</xref>.Q to 1 if the accumulate operation overflows. Overflow cannot occur during the multiplications or subtraction.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SMLSD/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMLSD_A1" oneofinclass="2" oneof="4" label="SMLSD" bitdiffs="M == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMLSD" />
        </docvars>
        <box hibit="5" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLSD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLSDX_A1" oneofinclass="2" oneof="4" label="SMLSDX" bitdiffs="M == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMLSDX" />
        </docvars>
        <box hibit="5" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLSDX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMLSD/A1_A.txt" mylink="aarch32.instrs.SMLSD.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Ra == '1111' then SEE "SMUSD";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);  m_swap = (M == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SMLSD/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMLSD_T1" oneofinclass="2" oneof="4" label="SMLSD" bitdiffs="M == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMLSD" />
        </docvars>
        <box hibit="4" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLSD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLSDX_T1" oneofinclass="2" oneof="4" label="SMLSDX" bitdiffs="M == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMLSDX" />
        </docvars>
        <box hibit="4" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLSDX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMLSD/T1_A.txt" mylink="aarch32.instrs.SMLSD.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Ra == '1111' then SEE "SMUSD";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);  m_swap = (M == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SMLSD_A1, SMLSD_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLSD_A1, SMLSD_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLSD_A1, SMLSD_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLSD_A1, SMLSD_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLSD_A1, SMLSD_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLSD_A1, SMLSD_T1" symboldefcount="1">
      <symbol link="sa_ra">&lt;Ra&gt;</symbol>
      <account encodedin="Ra">
        <intro>
          <para>Is the third general-purpose source register holding the addend, encoded in the "Ra" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SMLSD/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    operand2 = if m_swap then <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m],16) else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>    product1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand2&lt;15:0&gt;);</line>
<line>    product2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand2&lt;31:16&gt;);</line>
<line>    result = (product1 - product2) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[a]);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result&lt;31:0&gt;;</line>
<line>    if result != <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(result&lt;31:0&gt;) then  // Signed overflow</line>
<line>        PSTATE.Q = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="smlsld.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SMLSLD" title="SMLSLD, SMLSLDX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SMLSLD, SMLSLDX</heading>
  <desc>
    <brief>
      <para>Signed Multiply Subtract Long Dual</para>
    </brief>
    <authored>
      <para>Signed Multiply Subtract Long Dual performs two signed 16 x 16-bit multiplications. It adds the difference of the products to a 64-bit accumulate operand.</para>
      <para>Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top x bottom and bottom x top multiplication.</para>
      <para>Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 2<sup>64</sup>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SMLSLD/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="RdHi" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="RdLo" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMLSLD_A1" oneofinclass="2" oneof="4" label="SMLSLD" bitdiffs="M == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMLSLD" />
        </docvars>
        <box hibit="5" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLSLD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLSLDX_A1" oneofinclass="2" oneof="4" label="SMLSLDX" bitdiffs="M == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMLSLDX" />
        </docvars>
        <box hibit="5" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLSLDX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMLSLD/A1_A.txt" mylink="aarch32.instrs.SMLSLD.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>dLo = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdLo);  dHi = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdHi);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  m_swap = (M == '1');</line>
<line>if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>if dHi == dLo then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>dHi == dLo</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SMLSLD/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="RdLo" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="RdHi" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMLSLD_T1" oneofinclass="2" oneof="4" label="SMLSLD" bitdiffs="M == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMLSLD" />
        </docvars>
        <box hibit="4" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLSLD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLSLDX_T1" oneofinclass="2" oneof="4" label="SMLSLDX" bitdiffs="M == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMLSLDX" />
        </docvars>
        <box hibit="4" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLSLDX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMLSLD/T1_A.txt" mylink="aarch32.instrs.SMLSLD.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>dLo = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdLo);  dHi = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdHi);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  m_swap = (M == '1');</line>
<line>if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>// Armv8-A removes UPREDICTABLE for R13</line>
<line>if dHi == dLo then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>dHi == dLo</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SMLSLD_A1, SMLSLD_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLSLD_A1, SMLSLD_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLSLD_A1, SMLSLD_T1" symboldefcount="1">
      <symbol link="sa_rdlo">&lt;RdLo&gt;</symbol>
      <account encodedin="RdLo">
        <intro>
          <para>Is the general-purpose source register holding the lower 32 bits of the addend, and the destination register for the lower 32 bits of the result, encoded in the "RdLo" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLSLD_A1, SMLSLD_T1" symboldefcount="1">
      <symbol link="sa_rdhi">&lt;RdHi&gt;</symbol>
      <account encodedin="RdHi">
        <intro>
          <para>Is the general-purpose source register holding the upper 32 bits of the addend, and the destination register for the upper 32 bits of the result, encoded in the "RdHi" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLSLD_A1, SMLSLD_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLSLD_A1, SMLSLD_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SMLSLD/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    operand2 = if m_swap then <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m],16) else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>    product1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand2&lt;15:0&gt;);</line>
<line>    product2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand2&lt;31:16&gt;);</line>
<line>    result = (product1 - product2) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[dHi]:<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[dLo]);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[dHi] = result&lt;63:32&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[dLo] = result&lt;31:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="smmla.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SMMLA" title="SMMLA, SMMLAR -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SMMLA, SMMLAR</heading>
  <desc>
    <brief>
      <para>Signed Most Significant Word Multiply Accumulate</para>
    </brief>
    <authored>
      <para>Signed Most Significant Word Multiply Accumulate multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and adds an accumulate value.</para>
      <para>Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant <hexnumber>0x80000000</hexnumber> is added to the product before the high word is extracted.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SMMLA/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" name="R" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMMLA_A1" oneofinclass="2" oneof="4" label="SMMLA" bitdiffs="R == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMMLA" />
        </docvars>
        <box hibit="5" width="1" name="R">
          <c>0</c>
        </box>
        <asmtemplate><text>SMMLA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMMLAR_A1" oneofinclass="2" oneof="4" label="SMMLAR" bitdiffs="R == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMMLAR" />
        </docvars>
        <box hibit="5" width="1" name="R">
          <c>1</c>
        </box>
        <asmtemplate><text>SMMLAR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMMLA/A1_A.txt" mylink="aarch32.instrs.SMMLA.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Ra == '1111' then SEE "SMMUL";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);  round = (R == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SMMLA/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="R" usename="1">
          <c></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMMLA_T1" oneofinclass="2" oneof="4" label="SMMLA" bitdiffs="R == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMMLA" />
        </docvars>
        <box hibit="4" width="1" name="R">
          <c>0</c>
        </box>
        <asmtemplate><text>SMMLA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMMLAR_T1" oneofinclass="2" oneof="4" label="SMMLAR" bitdiffs="R == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMMLAR" />
        </docvars>
        <box hibit="4" width="1" name="R">
          <c>1</c>
        </box>
        <asmtemplate><text>SMMLAR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMMLA/T1_A.txt" mylink="aarch32.instrs.SMMLA.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Ra == '1111' then SEE "SMMUL";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);  round = (R == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SMMLA_A1, SMMLA_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMMLA_A1, SMMLA_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMMLA_A1, SMMLA_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMMLA_A1, SMMLA_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMMLA_A1, SMMLA_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register holding the multiplier, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMMLA_A1, SMMLA_T1" symboldefcount="1">
      <symbol link="sa_ra">&lt;Ra&gt;</symbol>
      <account encodedin="Ra">
        <intro>
          <para>Is the third general-purpose source register holding the addend, encoded in the "Ra" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SMMLA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    result = (<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[a]) &lt;&lt; 32) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]);</line>
<line>    if round then result = result + 0x80000000;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result&lt;63:32&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="smmls.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SMMLS" title="SMMLS, SMMLSR -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SMMLS, SMMLSR</heading>
  <desc>
    <brief>
      <para>Signed Most Significant Word Multiply Subtract</para>
    </brief>
    <authored>
      <para>Signed Most Significant Word Multiply Subtract multiplies two signed 32-bit values, subtracts the result from a 32-bit accumulate value that is shifted left by 32 bits, and extracts the most significant 32 bits of the result of that subtraction.</para>
      <para>Optionally, the instruction can specify that the result of the instruction is rounded instead of being truncated. In this case, the constant <hexnumber>0x80000000</hexnumber> is added to the result of the subtraction before the high word is extracted.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SMMLS/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="5" name="R" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMMLS_A1" oneofinclass="2" oneof="4" label="SMMLS" bitdiffs="R == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMMLS" />
        </docvars>
        <box hibit="5" width="1" name="R">
          <c>0</c>
        </box>
        <asmtemplate><text>SMMLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMMLSR_A1" oneofinclass="2" oneof="4" label="SMMLSR" bitdiffs="R == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMMLSR" />
        </docvars>
        <box hibit="5" width="1" name="R">
          <c>1</c>
        </box>
        <asmtemplate><text>SMMLSR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMMLS/A1_A.txt" mylink="aarch32.instrs.SMMLS.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);  round = (R == '1');</line>
<line>if d == 15 || n == 15 || m == 15 || a == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SMMLS/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="R" usename="1">
          <c></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMMLS_T1" oneofinclass="2" oneof="4" label="SMMLS" bitdiffs="R == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMMLS" />
        </docvars>
        <box hibit="4" width="1" name="R">
          <c>0</c>
        </box>
        <asmtemplate><text>SMMLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMMLSR_T1" oneofinclass="2" oneof="4" label="SMMLSR" bitdiffs="R == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMMLSR" />
        </docvars>
        <box hibit="4" width="1" name="R">
          <c>1</c>
        </box>
        <asmtemplate><text>SMMLSR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMMLS/T1_A.txt" mylink="aarch32.instrs.SMMLS.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);  round = (R == '1');</line>
<line>if d == 15 || n == 15 || m == 15 || a == 15 then UNPREDICTABLE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SMMLS_A1, SMMLS_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMMLS_A1, SMMLS_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMMLS_A1, SMMLS_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMMLS_A1, SMMLS_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMMLS_A1, SMMLS_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register holding the multiplier, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMMLS_A1, SMMLS_T1" symboldefcount="1">
      <symbol link="sa_ra">&lt;Ra&gt;</symbol>
      <account encodedin="Ra">
        <intro>
          <para>Is the third general-purpose source register holding the addend, encoded in the "Ra" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SMMLS/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    result = (<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[a]) &lt;&lt; 32) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]);</line>
<line>    if round then result = result + 0x80000000;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result&lt;63:32&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="smmul.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SMMUL" title="SMMUL, SMMULR -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SMMUL, SMMULR</heading>
  <desc>
    <brief>
      <para>Signed Most Significant Word Multiply</para>
    </brief>
    <authored>
      <para>Signed Most Significant Word Multiply multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and writes those bits to the destination register.</para>
      <para>Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant <hexnumber>0x80000000</hexnumber> is added to the product before the high word is extracted.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SMMUL/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" name="R" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMMUL_A1" oneofinclass="2" oneof="4" label="SMMUL" bitdiffs="R == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMMUL" />
        </docvars>
        <box hibit="5" width="1" name="R">
          <c>0</c>
        </box>
        <asmtemplate><text>SMMUL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMMULR_A1" oneofinclass="2" oneof="4" label="SMMULR" bitdiffs="R == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMMULR" />
        </docvars>
        <box hibit="5" width="1" name="R">
          <c>1</c>
        </box>
        <asmtemplate><text>SMMULR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMMUL/A1_A.txt" mylink="aarch32.instrs.SMMUL.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  round = (R == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SMMUL/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="R" usename="1">
          <c></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMMUL_T1" oneofinclass="2" oneof="4" label="SMMUL" bitdiffs="R == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMMUL" />
        </docvars>
        <box hibit="4" width="1" name="R">
          <c>0</c>
        </box>
        <asmtemplate><text>SMMUL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMMULR_T1" oneofinclass="2" oneof="4" label="SMMULR" bitdiffs="R == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMMULR" />
        </docvars>
        <box hibit="4" width="1" name="R">
          <c>1</c>
        </box>
        <asmtemplate><text>SMMULR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMMUL/T1_A.txt" mylink="aarch32.instrs.SMMUL.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  round = (R == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SMMUL_A1, SMMUL_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMMUL_A1, SMMUL_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMMUL_A1, SMMUL_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMMUL_A1, SMMUL_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMMUL_A1, SMMUL_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SMMUL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    result = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]);</line>
<line>    if round then result = result + 0x80000000;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result&lt;63:32&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="smuad.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SMUAD" title="SMUAD, SMUADX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SMUAD, SMUADX</heading>
  <desc>
    <brief>
      <para>Signed Dual Multiply Add</para>
    </brief>
    <authored>
      <para>Signed Dual Multiply Add performs two signed 16 x 16-bit multiplications. It adds the products together, and writes the result to the destination register.</para>
      <para>Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top x bottom and bottom x top multiplication.</para>
      <para>This instruction sets <xref linkend="BEIDIGBH">PSTATE</xref>.Q to 1 if the addition overflows. The multiplications cannot overflow.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SMUAD/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMUAD_A1" oneofinclass="2" oneof="4" label="SMUAD" bitdiffs="M == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMUAD" />
        </docvars>
        <box hibit="5" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMUAD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMUADX_A1" oneofinclass="2" oneof="4" label="SMUADX" bitdiffs="M == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMUADX" />
        </docvars>
        <box hibit="5" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMUADX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMUAD/A1_A.txt" mylink="aarch32.instrs.SMUAD.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  m_swap = (M == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SMUAD/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMUAD_T1" oneofinclass="2" oneof="4" label="SMUAD" bitdiffs="M == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMUAD" />
        </docvars>
        <box hibit="4" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMUAD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMUADX_T1" oneofinclass="2" oneof="4" label="SMUADX" bitdiffs="M == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMUADX" />
        </docvars>
        <box hibit="4" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMUADX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMUAD/T1_A.txt" mylink="aarch32.instrs.SMUAD.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  m_swap = (M == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SMUAD_A1, SMUAD_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMUAD_A1, SMUAD_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMUAD_A1, SMUAD_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMUAD_A1, SMUAD_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMUAD_A1, SMUAD_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SMUAD/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    operand2 = if m_swap then <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m],16) else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>    product1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand2&lt;15:0&gt;);</line>
<line>    product2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand2&lt;31:16&gt;);</line>
<line>    result = product1 + product2;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result&lt;31:0&gt;;</line>
<line>    if result != <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(result&lt;31:0&gt;) then  // Signed overflow</line>
<line>        PSTATE.Q = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="smulbb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SMULBB" title="SMULBB, SMULBT, SMULTB, SMULTT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SMULBB, SMULBT, SMULTB, SMULTT</heading>
  <desc>
    <brief>
      <para>Signed Multiply (halfwords)</para>
    </brief>
    <authored>
      <para>Signed Multiply (halfwords) multiplies two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The other halves of these source registers are ignored. The 32-bit product is written to the destination register. No overflow is possible during this instruction.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SMULBB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMULBB_A1" oneofinclass="4" oneof="8" label="SMULBB" bitdiffs="M == 0 &amp;&amp; N == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMULBB" />
        </docvars>
        <box hibit="6" width="1" name="M">
          <c>0</c>
        </box>
        <box hibit="5" width="1" name="N">
          <c>0</c>
        </box>
        <asmtemplate><text>SMULBB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by {syntax{&lt;x&gt;}}) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMULBT_A1" oneofinclass="4" oneof="8" label="SMULBT" bitdiffs="M == 1 &amp;&amp; N == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMULBT" />
        </docvars>
        <box hibit="6" width="1" name="M">
          <c>1</c>
        </box>
        <box hibit="5" width="1" name="N">
          <c>0</c>
        </box>
        <asmtemplate><text>SMULBT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by {syntax{&lt;x&gt;}}) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMULTB_A1" oneofinclass="4" oneof="8" label="SMULTB" bitdiffs="M == 0 &amp;&amp; N == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMULTB" />
        </docvars>
        <box hibit="6" width="1" name="M">
          <c>0</c>
        </box>
        <box hibit="5" width="1" name="N">
          <c>1</c>
        </box>
        <asmtemplate><text>SMULTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by {syntax{&lt;x&gt;}}) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMULTT_A1" oneofinclass="4" oneof="8" label="SMULTT" bitdiffs="M == 1 &amp;&amp; N == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMULTT" />
        </docvars>
        <box hibit="6" width="1" name="M">
          <c>1</c>
        </box>
        <box hibit="5" width="1" name="N">
          <c>1</c>
        </box>
        <asmtemplate><text>SMULTT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by {syntax{&lt;x&gt;}}) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMULBB/A1_A.txt" mylink="aarch32.instrs.SMULBB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>n_high = (N == '1');  m_high = (M == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SMULBB/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMULBB_T1" oneofinclass="4" oneof="8" label="SMULBB" bitdiffs="N == 0 &amp;&amp; M == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMULBB" />
        </docvars>
        <box hibit="5" width="1" name="N">
          <c>0</c>
        </box>
        <box hibit="4" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMULBB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by {syntax{&lt;x&gt;}}) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMULBT_T1" oneofinclass="4" oneof="8" label="SMULBT" bitdiffs="N == 0 &amp;&amp; M == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMULBT" />
        </docvars>
        <box hibit="5" width="1" name="N">
          <c>0</c>
        </box>
        <box hibit="4" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMULBT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by {syntax{&lt;x&gt;}}) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMULTB_T1" oneofinclass="4" oneof="8" label="SMULTB" bitdiffs="N == 1 &amp;&amp; M == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMULTB" />
        </docvars>
        <box hibit="5" width="1" name="N">
          <c>1</c>
        </box>
        <box hibit="4" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMULTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by {syntax{&lt;x&gt;}}) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMULTT_T1" oneofinclass="4" oneof="8" label="SMULTT" bitdiffs="N == 1 &amp;&amp; M == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMULTT" />
        </docvars>
        <box hibit="5" width="1" name="N">
          <c>1</c>
        </box>
        <box hibit="4" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMULTT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand in the bottom or top half (selected by {syntax{&lt;x&gt;}}) (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMULBB/T1_A.txt" mylink="aarch32.instrs.SMULBB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>n_high = (N == '1');  m_high = (M == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SMULBB_A1, SMULBB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMULBB_A1, SMULBB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMULBB_A1, SMULBB_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMULBB_A1, SMULBB_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register holding the multiplicand in the bottom or top half (selected by <syntax>&lt;x&gt;</syntax>), encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMULBB_A1, SMULBB_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register holding the multiplier in the bottom or top half (selected by <syntax>&lt;y&gt;</syntax>), encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SMULBB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    operand1 = if n_high then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt; else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;;</line>
<line>    operand2 = if m_high then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt; else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;;</line>
<line>    result = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand1) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand2);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result&lt;31:0&gt;;</line>
<line>    // Signed overflow cannot occur</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="smull.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SMULL" title="SMULL, SMULLS -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SMULL, SMULLS</heading>
  <desc>
    <brief>
      <para>Signed Multiply Long</para>
    </brief>
    <authored>
      <para>Signed Multiply Long multiplies two 32-bit signed values to produce a 64-bit result.</para>
      <para>In A32 instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many implementations.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SMULL/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="RdHi" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="RdLo" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMULLS_A1" oneofinclass="2" oneof="3" label="Flag setting" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMULLS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>SMULLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose destination register for lower 32 bits of result (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose destination register for upper 32 bits of result (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMULL_A1" oneofinclass="2" oneof="3" label="Not flag setting" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMULL" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>SMULL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose destination register for lower 32 bits of result (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose destination register for upper 32 bits of result (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMULL/A1_A.txt" mylink="aarch32.instrs.SMULL.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>dLo = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdLo);  dHi = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdHi);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>if dHi == dLo then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>dHi == dLo</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SMULL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SMULL/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="RdLo" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="RdHi" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" name="op2" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMULL_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMULL" />
        </docvars>
        <asmtemplate><text>SMULL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose destination register for lower 32 bits of result (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose destination register for upper 32 bits of result (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMULL/T1_A.txt" mylink="aarch32.instrs.SMULL.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>dLo = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdLo);  dHi = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdHi);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = FALSE;</line>
<line>if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
<line>if dHi == dLo then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>dHi == dLo</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SMULL_A1, SMULL_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMULL_A1, SMULL_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMULL_A1, SMULL_T1" symboldefcount="1">
      <symbol link="sa_rdlo">&lt;RdLo&gt;</symbol>
      <account encodedin="RdLo">
        <intro>
          <para>Is the general-purpose destination register for the lower 32 bits of the result, encoded in the "RdLo" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMULL_A1, SMULL_T1" symboldefcount="1">
      <symbol link="sa_rdhi">&lt;RdHi&gt;</symbol>
      <account encodedin="RdHi">
        <intro>
          <para>Is the general-purpose destination register for the upper 32 bits of the result, encoded in the "RdHi" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMULL_A1, SMULL_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMULL_A1, SMULL_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register holding the multiplier, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SMULL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    result = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[dHi] = result&lt;63:32&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[dLo] = result&lt;31:0&gt;;</line>
<line>    if setflags then</line>
<line>        PSTATE.N = result&lt;63&gt;;</line>
<line>        PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result&lt;63:0&gt;);</line>
<line>        // PSTATE.C, PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="smulwb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SMULWB" title="SMULWB, SMULWT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SMULWB, SMULWT</heading>
  <desc>
    <brief>
      <para>Signed Multiply (word by halfword)</para>
    </brief>
    <authored>
      <para>Signed Multiply (word by halfword) multiplies a signed 32-bit quantity and a signed 16-bit quantity. The signed 16-bit quantity is taken from either the bottom or the top half of its source register. The other half of the second source register is ignored. The top 32 bits of the 48-bit product are written to the destination register. The bottom 16 bits of the 48-bit product are ignored. No overflow is possible during this instruction.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SMULWB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="N" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMULWB_A1" oneofinclass="2" oneof="4" label="SMULWB" bitdiffs="M == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMULWB" />
        </docvars>
        <box hibit="6" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMULWB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMULWT_A1" oneofinclass="2" oneof="4" label="SMULWT" bitdiffs="M == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMULWT" />
        </docvars>
        <box hibit="6" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMULWT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMULWB/A1_A.txt" mylink="aarch32.instrs.SMULWB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  m_high = (M == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SMULWB/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMULWB_T1" oneofinclass="2" oneof="4" label="SMULWB" bitdiffs="M == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMULWB" />
        </docvars>
        <box hibit="4" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMULWB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMULWT_T1" oneofinclass="2" oneof="4" label="SMULWT" bitdiffs="M == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMULWT" />
        </docvars>
        <box hibit="4" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMULWT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier in the bottom or top half (selected by {syntax{&lt;y&gt;}}) (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMULWB/T1_A.txt" mylink="aarch32.instrs.SMULWB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  m_high = (M == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SMULWB_A1, SMULWB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMULWB_A1, SMULWB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMULWB_A1, SMULWB_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMULWB_A1, SMULWB_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMULWB_A1, SMULWB_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register holding the multiplier in the bottom or top half (selected by <syntax>&lt;y&gt;</syntax>), encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SMULWB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    operand2 = if m_high then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt; else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;;</line>
<line>    product = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand2);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = product&lt;47:16&gt;;</line>
<line>    // Signed overflow cannot occur</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="smusd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SMUSD" title="SMUSD, SMUSDX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SMUSD, SMUSDX</heading>
  <desc>
    <brief>
      <para>Signed Multiply Subtract Dual</para>
    </brief>
    <authored>
      <para>Signed Multiply Subtract Dual performs two signed 16 x 16-bit multiplications. It subtracts one of the products from the other, and writes the result to the destination register.</para>
      <para>Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top x bottom and bottom x top multiplication.</para>
      <para>Overflow cannot occur.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SMUSD/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMUSD_A1" oneofinclass="2" oneof="4" label="SMUSD" bitdiffs="M == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMUSD" />
        </docvars>
        <box hibit="5" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMUSD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMUSDX_A1" oneofinclass="2" oneof="4" label="SMUSDX" bitdiffs="M == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMUSDX" />
        </docvars>
        <box hibit="5" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMUSDX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMUSD/A1_A.txt" mylink="aarch32.instrs.SMUSD.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  m_swap = (M == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SMUSD/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMUSD_T1" oneofinclass="2" oneof="4" label="SMUSD" bitdiffs="M == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMUSD" />
        </docvars>
        <box hibit="4" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMUSD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMUSDX_T1" oneofinclass="2" oneof="4" label="SMUSDX" bitdiffs="M == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMUSDX" />
        </docvars>
        <box hibit="4" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMUSDX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMUSD/T1_A.txt" mylink="aarch32.instrs.SMUSD.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  m_swap = (M == '1');</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SMUSD_A1, SMUSD_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMUSD_A1, SMUSD_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMUSD_A1, SMUSD_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMUSD_A1, SMUSD_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMUSD_A1, SMUSD_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SMUSD/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    operand2 = if m_swap then <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m],16) else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>    product1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand2&lt;15:0&gt;);</line>
<line>    product2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand2&lt;31:16&gt;);</line>
<line>    result = product1 - product2;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result&lt;31:0&gt;;</line>
<line>    // Signed overflow cannot occur</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="srs.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SRS" title="SRS, SRSDA, SRSDB, SRSIA, SRSIB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SRS, SRSDA, SRSDB, SRSIA, SRSIB</heading>
  <desc>
    <brief>
      <para>Store Return State</para>
    </brief>
    <authored>
      <para>Store Return State stores the LR_&lt;current_mode&gt; and <xref linkend="CHDDAABB">SPSR</xref>_&lt;current_mode&gt; to the stack of a specified mode. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
      <para><instruction>SRS</instruction> is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</para>
      <para><instruction>SRS</instruction> is <arm-defined-word>constrained unpredictable</arm-defined-word> if it is executed in User or System mode, or if the specified mode is any of the following:</para>
      <list type="unordered">
        <listitem><content>Not implemented.</content></listitem>
        <listitem><content>A mode that <xref linkend="CIHGHDGI">Table G1-5</xref> does not show.</content></listitem>
        <listitem><content>Hyp mode.</content></listitem>
        <listitem><content>Monitor mode, if the <instruction>SRS</instruction> instruction is executed in Non-secure state.</content></listitem>
      </list>
      <para>If EL3 is using AArch64 and an <instruction>SRS</instruction> instruction that is executed in a Secure EL1 mode specifies Monitor mode, it is trapped to EL3.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGDFDHJ">SRS (T32)</xref> and <xref linkend="CEGJIFIF">SRS (A32)</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para><instruction>SRSFA</instruction>, <instruction>SRSEA</instruction>, <instruction>SRSFD</instruction>, and <instruction>SRSED</instruction> are pseudo-instructions for <instruction>SRSIB</instruction>, <instruction>SRSIA</instruction>, <instruction>SRSDB</instruction>, and <instruction>SRSDA</instruction> respectively, referring to their use for pushing data onto Full Ascending, Empty Ascending, Full Descending, and Empty Descending stacks.</para>
    </syntaxnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SRS/A1_AS.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(0)</c>
          <c>(1)</c>
        </box>
        <box hibit="15" width="11" name="op" settings="11">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(1)</c>
          <c>(0)</c>
          <c>(1)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="4" width="5" name="mode" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="SRSDA_A1_AS" oneofinclass="4" oneof="6" label="Decrement After" bitdiffs="P == 0 &amp;&amp; U == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="dec-after" />
          <docvar key="mnemonic" value="SRSDA" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>0</c>
        </box>
        <asmtemplate><text>SRSDA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> SP</text><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, #</text><a link="sa_mode" hover="Mode whose Banked SP is used as the base register number (field &quot;mode&quot;)">&lt;mode&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SRSDB_A1_AS" oneofinclass="4" oneof="6" label="Decrement Before" bitdiffs="P == 1 &amp;&amp; U == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="SRSDB" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>0</c>
        </box>
        <asmtemplate><text>SRSDB</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> SP</text><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, #</text><a link="sa_mode" hover="Mode whose Banked SP is used as the base register number (field &quot;mode&quot;)">&lt;mode&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SRSIA_A1_AS" oneofinclass="4" oneof="6" label="Increment After" bitdiffs="P == 0 &amp;&amp; U == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="inc-after" />
          <docvar key="mnemonic" value="SRS{IA}" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>1</c>
        </box>
        <asmtemplate><text>SRS</text><a link="sa_ia_1" hover="Optional suffix to indicate the Increment After variant">{IA}</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> SP</text><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, #</text><a link="sa_mode" hover="Mode whose Banked SP is used as the base register number (field &quot;mode&quot;)">&lt;mode&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SRSIB_A1_AS" oneofinclass="4" oneof="6" label="Increment Before" bitdiffs="P == 1 &amp;&amp; U == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="inc-before" />
          <docvar key="mnemonic" value="SRSIB" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>1</c>
        </box>
        <asmtemplate><text>SRSIB</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> SP</text><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, #</text><a link="sa_mode" hover="Mode whose Banked SP is used as the base register number (field &quot;mode&quot;)">&lt;mode&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SRS/A1_AS.txt" mylink="aarch32.instrs.SRS.A1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>wback = (W == '1');  increment = (U == '1');  wordhigher = (P == U);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="ldmstm-mode" value="dec-before" />
        <docvar key="mnemonic" value="SRSDB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SRS/T1_AS.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="opc" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(0)</c>
          <c>(1)</c>
        </box>
        <box hibit="15" name="P" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" name="M" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" width="9" settings="9">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="4" width="5" name="mode" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="SRS_T1_AS" oneofinclass="1" oneof="6" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="SRSDB" />
        </docvars>
        <asmtemplate><text>SRSDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> SP</text><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, #</text><a link="sa_mode" hover="Mode whose Banked SP is used as the base register number (field &quot;mode&quot;)">&lt;mode&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SRS/T1_AS.txt" mylink="aarch32.instrs.SRS.T1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>wback = (W == '1');  increment = FALSE;  wordhigher = FALSE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="ldmstm-mode" value="inc-after" />
        <docvar key="mnemonic" value="SRS{IA}" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SRS/T2_AS.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="opc" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(0)</c>
          <c>(1)</c>
        </box>
        <box hibit="15" name="P" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" name="M" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" width="9" settings="9">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
        <box hibit="4" width="5" name="mode" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="SRS_T2_AS" oneofinclass="1" oneof="6" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="ldmstm-mode" value="inc-after" />
          <docvar key="mnemonic" value="SRS{IA}" />
        </docvars>
        <asmtemplate><text>SRS</text><a link="sa_ia" hover="Optional suffix for Increment After form">{IA}</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> SP</text><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, #</text><a link="sa_mode" hover="Mode whose Banked SP is used as the base register number (field &quot;mode&quot;)">&lt;mode&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SRS/T2_AS.txt" mylink="aarch32.instrs.SRS.T2_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>wback = (W == '1');  increment = TRUE;  wordhigher = FALSE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SRSIA_A1_AS" symboldefcount="1">
      <symbol link="sa_ia_1">IA</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is an optional suffix to indicate the Increment After variant.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SRS_T2_AS" symboldefcount="2">
      <symbol link="sa_ia">IA</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is an optional suffix for the Increment After form.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SRSDA_A1_AS" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="dec-after" />
          <docvar key="mnemonic" value="SRSDA" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. <syntax>&lt;c&gt;</syntax> must be <value>AL</value> or omitted.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SRS_T1_AS, SRS_T2_AS" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SRSDA_A1_AS, SRS_T1_AS, SRS_T2_AS" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SRSDA_A1_AS, SRS_T1_AS, SRS_T2_AS" symboldefcount="1">
      <symbol link="sa_0d33">!</symbol>
      <account encodedin="W">
        <intro>
          <para>The address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SRSDA_A1_AS, SRS_T1_AS, SRS_T2_AS" symboldefcount="1">
      <symbol link="sa_mode">&lt;mode&gt;</symbol>
      <account encodedin="mode">
        <intro>
          <para>Is the number of the mode whose Banked SP is used as the base register, encoded in the "mode" field. For details of PE modes and their numbers see <xref linkend="CIHEDADE">AArch32 PE mode descriptions</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SRS/Op_AS.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then</line>
<line>    if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>        EncodingSpecificOperations();</line>
<line>        if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then          // UNDEFINED at EL2</line>
<line>            UNDEFINED;</line>
<line>    </line>
<line>        // Check for UNPREDICTABLE cases. The definition of UNPREDICTABLE does not permit these</line>
<line>        // to be security holes</line>
<line>        if PSTATE.M IN {<a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a>,<a link="M32_System" file="shared_pseudocode.xml" hover="constant bits(5) M32_System = '11111'">M32_System</a>} then</line>
<line>            UNPREDICTABLE;</line>
<line>        elsif mode == <a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a> then        // Check for attempt to access Hyp mode SP</line>
<line>            UNPREDICTABLE;</line>
<line>        elsif mode == <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a> then    // Check for attempt to access Monitor mode SP</line>
<line>            if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) || <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() != <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>                UNPREDICTABLE;</line>
<line>            elsif !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>                <a link="AArch64.MonitorModeTrap.0" file="shared_pseudocode.xml" hover="function: AArch64.MonitorModeTrap()">AArch64.MonitorModeTrap</a>();</line>
<line>        elsif <a link="impl-aarch32.BadMode.1" file="shared_pseudocode.xml" hover="function: boolean BadMode(bits(5) mode)">BadMode</a>(mode) then</line>
<line>            UNPREDICTABLE;</line>
<line>    </line>
<line>        base = <a link="impl-aarch32.Rmode.read.2" file="shared_pseudocode.xml" hover="accessor: bits(32) Rmode[integer n, bits(5) mode]">Rmode</a>[13,mode];</line>
<line>        address = if increment then base else base-8;</line>
<line>        if wordhigher then address = address+4;</line>
<line>        <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,4]   = <a link="impl-aarch32.LR.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) LR">LR</a>;</line>
<line>        <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address+4,4] = <a link="impl-shared.SPSR.read.0" file="shared_pseudocode.xml" hover="accessor: bits(N) SPSR[]">SPSR</a>[];</line>
<line>        if wback then <a link="impl-aarch32.Rmode.write.2" file="shared_pseudocode.xml" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</a>[13,mode] = if increment then base+8 else base-8;</line>
<line>else</line>
<line>    if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>        EncodingSpecificOperations();</line>
<line>        if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then          // UNDEFINED at EL2</line>
<line>            UNDEFINED;</line>
<line>    </line>
<line>        // Check for UNPREDICTABLE cases. The definition of UNPREDICTABLE does not permit these</line>
<line>        // to be security holes</line>
<line>        if PSTATE.M IN {<a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a>,<a link="M32_System" file="shared_pseudocode.xml" hover="constant bits(5) M32_System = '11111'">M32_System</a>} then</line>
<line>            UNPREDICTABLE;</line>
<line>        elsif mode == <a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a> then        // Check for attempt to access Hyp mode SP</line>
<line>            UNPREDICTABLE;</line>
<line>        elsif mode == <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a> then    // Check for attempt to access Monitor mode SP</line>
<line>            if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) || <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() != <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>                UNPREDICTABLE;</line>
<line>            elsif !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>                <a link="AArch64.MonitorModeTrap.0" file="shared_pseudocode.xml" hover="function: AArch64.MonitorModeTrap()">AArch64.MonitorModeTrap</a>();</line>
<line>        elsif <a link="impl-aarch32.BadMode.1" file="shared_pseudocode.xml" hover="function: boolean BadMode(bits(5) mode)">BadMode</a>(mode) then</line>
<line>            UNPREDICTABLE;</line>
<line>    </line>
<line>        base = <a link="impl-aarch32.Rmode.read.2" file="shared_pseudocode.xml" hover="accessor: bits(32) Rmode[integer n, bits(5) mode]">Rmode</a>[13,mode];</line>
<line>        address = if increment then base else base-8;</line>
<line>        if wordhigher then address = address+4;</line>
<line>        <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,4]   = <a link="impl-aarch32.LR.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) LR">LR</a>;</line>
<line>        <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address+4,4] = <a link="impl-shared.SPSR.read.0" file="shared_pseudocode.xml" hover="accessor: bits(N) SPSR[]">SPSR</a>[];</line>
<line>        if wback then <a link="impl-aarch32.Rmode.write.2" file="shared_pseudocode.xml" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</a>[13,mode] = if increment then base+8 else base-8;</line>
</pstext>
    </ps>
  </ps_section>
  <constrained_unpredictables ps_block="Operation">
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>PSTATE.M IN {M32_User,M32_System}</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
    </cu_case>
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>mode == M32_Hyp</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
    </cu_case>
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>mode == M32_Monitor &amp;&amp; (!HaveEL(EL3) || CurrentSecurityState() != SS_Secure)</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
    </cu_case>
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>BadMode(mode)</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
      <cu_type>
        <cu_type_text>The instruction stores to the stack of the mode in which it is executed.</cu_type_text>
      </cu_type>
      <cu_type>
        <cu_type_text>The instruction stores to an <arm-defined-word>unknown</arm-defined-word> address, and if the instruction specifies writeback then any general-purpose register that can be accessed from the current Exception level without a privilege violation becomes <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
      </cu_type>
    </cu_case>
  </constrained_unpredictables>
</instructionsection>
</file>
<file type="instructionsection" file="ssat.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SSAT" title="SSAT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SSAT" />
  </docvars>
  <heading>SSAT</heading>
  <desc>
    <brief>
      <para>Signed Saturate</para>
    </brief>
    <authored>
      <para>Signed Saturate saturates an optionally-shifted signed value to a selectable signed range.</para>
      <para>This instruction sets <xref linkend="BEIDIGBH">PSTATE</xref>.Q to 1 if the operation saturates.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SSAT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SSAT/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="sat_imm" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" name="sh" usename="1">
          <c></c>
        </box>
        <box hibit="5" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SSAT_A1_ASR" oneofinclass="2" oneof="4" label="Arithmetic shift right" bitdiffs="sh == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SSAT" />
          <docvar key="mnemonic-shift-type" value="SSAT-asr" />
          <docvar key="shift-type" value="asr" />
        </docvars>
        <box hibit="6" width="1" name="sh">
          <c>1</c>
        </box>
        <asmtemplate><text>SSAT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_imm" hover="Bit position for saturation [1-32] (field &quot;sat_imm&quot;)">&lt;imm&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, ASR #</text><a link="sa_amount_3" hover="Shift amount [1-32 (field &quot;imm5&quot;)">&lt;amount&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SSAT_A1_LSL" oneofinclass="2" oneof="4" label="Logical shift left" bitdiffs="sh == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SSAT" />
          <docvar key="mnemonic-shift-type" value="SSAT-lsl" />
          <docvar key="shift-type" value="lsl" />
        </docvars>
        <box hibit="6" width="1" name="sh">
          <c>0</c>
        </box>
        <asmtemplate><text>SSAT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_imm" hover="Bit position for saturation [1-32] (field &quot;sat_imm&quot;)">&lt;imm&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, LSL #</text><a link="sa_amount_2" hover="Optional shift amount [0-31], default 0 (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SSAT/A1_A.txt" mylink="aarch32.instrs.SSAT.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  saturate_to = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sat_imm)+1;</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(sh:'0', imm5);</line>
<line>if d == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SSAT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SSAT/T1_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="21" name="sh" usename="1">
          <c></c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" width="5" name="sat_imm" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="SSAT_T1_ASR" oneofinclass="2" oneof="4" label="Arithmetic shift right" bitdiffs="sh == 1 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00)">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SSAT" />
          <docvar key="mnemonic-shift-type" value="SSAT-asr" />
          <docvar key="shift-type" value="asr" />
        </docvars>
        <box hibit="21" width="1" name="sh">
          <c>1</c>
        </box>
        <box hibit="14" width="9" name="imm3:imm2">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
        </box>
        <asmtemplate><text>SSAT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_imm" hover="Bit position for saturation [1-32] (field &quot;sat_imm&quot;)">&lt;imm&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, ASR #</text><a link="sa_amount_1" hover="Shift amount [1-31 (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SSAT_T1_LSL" oneofinclass="2" oneof="4" label="Logical shift left" bitdiffs="sh == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SSAT" />
          <docvar key="mnemonic-shift-type" value="SSAT-lsl" />
          <docvar key="shift-type" value="lsl" />
        </docvars>
        <box hibit="21" width="1" name="sh">
          <c>0</c>
        </box>
        <asmtemplate><text>SSAT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_imm" hover="Bit position for saturation [1-32] (field &quot;sat_imm&quot;)">&lt;imm&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, LSL #</text><a link="sa_amount" hover="Optional shift amount [0-31], default 0 (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SSAT/T1_A.txt" mylink="aarch32.instrs.SSAT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if sh == '1' &amp;&amp; (imm3:imm2) == '00000' then SEE "SSAT16";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  saturate_to = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sat_imm)+1;</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(sh:'0', imm3:imm2);</line>
<line>if d == 15 || n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SSAT_A1_LSL, SSAT_T1_LSL" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSAT_A1_LSL, SSAT_T1_LSL" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSAT_A1_LSL, SSAT_T1_LSL" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSAT_A1_LSL, SSAT_T1_LSL" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="sat_imm">
        <intro>
          <para>Is the bit position for saturation, in the range 1 to 32, encoded in the "sat_imm" field as &lt;imm&gt;-1.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSAT_A1_LSL, SSAT_T1_LSL" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSAT_A1_LSL" symboldefcount="1">
      <symbol link="sa_amount_2">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="SSAT-lsl" />
          <docvar key="shift-type" value="lsl" />
        </docvars>
        <intro>
          <para>For encoding A1: is the optional shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm5" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSAT_A1_ASR" symboldefcount="2">
      <symbol link="sa_amount_3">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="SSAT-asr" />
          <docvar key="shift-type" value="asr" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 32 encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSAT_T1_LSL" symboldefcount="3">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic-shift-type" value="SSAT-lsl" />
          <docvar key="shift-type" value="lsl" />
        </docvars>
        <intro>
          <para>For encoding T1: is the optional shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm3:imm2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSAT_T1_ASR" symboldefcount="4">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic-shift-type" value="SSAT-asr" />
          <docvar key="shift-type" value="asr" />
        </docvars>
        <intro>
          <para>For encoding T1: is the shift amount, in the range 1 to 31 encoded in the "imm3:imm2" field as &lt;amount&gt;.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SSAT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    operand = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], shift_t, shift_n, PSTATE.C);  // PSTATE.C ignored</line>
<line>    (result, sat) = <a link="impl-shared.SignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand), saturate_to);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(result, 32);</line>
<line>    if sat then</line>
<line>        PSTATE.Q = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ssat16.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SSAT16" title="SSAT16 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SSAT16" />
  </docvars>
  <heading>SSAT16</heading>
  <desc>
    <brief>
      <para>Signed Saturate 16</para>
    </brief>
    <authored>
      <para>Signed Saturate 16 saturates two signed 16-bit values to a selected signed range.</para>
      <para>This instruction sets <xref linkend="BEIDIGBH">PSTATE</xref>.Q to 1 if the operation saturates.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SSAT16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SSAT16/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="sat_imm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SSAT16_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SSAT16" />
        </docvars>
        <asmtemplate><text>SSAT16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_imm" hover="Bit position for saturation [1-16] (field &quot;sat_imm&quot;)">&lt;imm&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SSAT16/A1_A.txt" mylink="aarch32.instrs.SSAT16.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  saturate_to = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sat_imm)+1;</line>
<line>if d == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SSAT16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SSAT16/T1_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" width="2" name="op1&lt;2:1&gt;" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="21" name="op1&lt;0&gt;" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="3" width="4" name="sat_imm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SSAT16_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SSAT16" />
        </docvars>
        <asmtemplate><text>SSAT16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_imm" hover="Bit position for saturation [1-16] (field &quot;sat_imm&quot;)">&lt;imm&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SSAT16/T1_A.txt" mylink="aarch32.instrs.SSAT16.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  saturate_to = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sat_imm)+1;</line>
<line>if d == 15 || n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SSAT16_A1, SSAT16_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSAT16_A1, SSAT16_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSAT16_A1, SSAT16_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSAT16_A1, SSAT16_T1" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="sat_imm">
        <intro>
          <para>Is the bit position for saturation, in the range 1 to 16, encoded in the "sat_imm" field as &lt;imm&gt;-1.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSAT16_A1, SSAT16_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SSAT16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    (result1, sat1) = <a link="impl-shared.SignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;), saturate_to);</line>
<line>    (result2, sat2) = <a link="impl-shared.SignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;), saturate_to);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt; = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(result1, 16);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(result2, 16);</line>
<line>    if sat1 || sat2 then</line>
<line>        PSTATE.Q = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ssax.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SSAX" title="SSAX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SSAX" />
  </docvars>
  <heading>SSAX</heading>
  <desc>
    <brief>
      <para>Signed Subtract and Add with Exchange</para>
    </brief>
    <authored>
      <para>Signed Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer subtraction and one 16-bit addition, and writes the results to the destination register. It sets <xref linkend="BEIDIGBH">PSTATE</xref>.GE according to the results.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SSAX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SSAX/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SSAX_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SSAX" />
        </docvars>
        <asmtemplate><text>SSAX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SSAX/A1_A.txt" mylink="aarch32.instrs.SSAX.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SSAX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SSAX/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SSAX_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SSAX" />
        </docvars>
        <asmtemplate><text>SSAX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SSAX/T1_A.txt" mylink="aarch32.instrs.SSAX.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SSAX_A1, SSAX_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSAX_A1, SSAX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSAX_A1, SSAX_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSAX_A1, SSAX_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSAX_A1, SSAX_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SSAX/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    sum  = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    diff = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = sum&lt;15:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = diff&lt;15:0&gt;;</line>
<line>    PSTATE.GE&lt;1:0&gt; = if sum  &gt;= 0 then '11' else '00';</line>
<line>    PSTATE.GE&lt;3:2&gt; = if diff &gt;= 0 then '11' else '00';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ssbb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SSBB" title="SSBB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SSBB" />
  </docvars>
  <heading>SSBB</heading>
  <desc>
    <brief>
      <para>Speculative Store Bypass Barrier</para>
    </brief>
    <authored>
      <para>Speculative Store Bypass Barrier is a memory barrier which prevents speculative loads from bypassing earlier stores to the same virtual address under certain conditions.</para>
      <para>The semantics of the Speculative Store Bypass Barrier are:</para>
      <list type="unordered">
        <listitem><content>When a load to a location appears in program order after the SSBB, then the load does not speculatively read an entry earlier in the coherence order for that location than the entry generated by the latest store satisfying all of the following conditions:<list type="unordered"><listitem><content>The store is to the same location as the load.</content></listitem><listitem><content>The store uses the same virtual address as the load.</content></listitem><listitem><content>The store appears in program order before the SSBB.</content></listitem></list></content></listitem>
        <listitem><content>When a load to a location appears in program order before the SSBB, then the load does not speculatively read data from any store satisfying all of the following conditions:<list type="unordered"><listitem><content>The store is to the same location as the load.</content></listitem><listitem><content>The store uses the same virtual address as the load.</content></listitem><listitem><content>The store appears in program order after the SSBB.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SSBB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SSBB/A1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" name="opcode" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="option" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="SSBB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SSBB" />
        </docvars>
        <asmtemplate><text>SSBB</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SSBB/A1_A.txt" mylink="aarch32.instrs.SSBB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SSBB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SSBB/T1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="option" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="SSBB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SSBB" />
        </docvars>
        <asmtemplate><text>SSBB</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SSBB/T1_A.txt" mylink="aarch32.instrs.SSBB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SSBB_A1, SSBB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SSBB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-shared.SpeculativeStoreBypassBarrierToVA.0" file="shared_pseudocode.xml" hover="function: SpeculativeStoreBypassBarrierToVA()">SpeculativeStoreBypassBarrierToVA</a>();</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ssub16.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SSUB16" title="SSUB16 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SSUB16" />
  </docvars>
  <heading>SSUB16</heading>
  <desc>
    <brief>
      <para>Signed Subtract 16</para>
    </brief>
    <authored>
      <para>Signed Subtract 16 performs two 16-bit signed integer subtractions, and writes the results to the destination register. It sets <xref linkend="BEIDIGBH">PSTATE</xref>.GE according to the results of the subtractions.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SSUB16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SSUB16/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SSUB16_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SSUB16" />
        </docvars>
        <asmtemplate><text>SSUB16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SSUB16/A1_A.txt" mylink="aarch32.instrs.SSUB16.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SSUB16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SSUB16/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SSUB16_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SSUB16" />
        </docvars>
        <asmtemplate><text>SSUB16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SSUB16/T1_A.txt" mylink="aarch32.instrs.SSUB16.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SSUB16_A1, SSUB16_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSUB16_A1, SSUB16_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSUB16_A1, SSUB16_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSUB16_A1, SSUB16_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSUB16_A1, SSUB16_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SSUB16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    diff1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    diff2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = diff1&lt;15:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = diff2&lt;15:0&gt;;</line>
<line>    PSTATE.GE&lt;1:0&gt; = if diff1 &gt;= 0 then '11' else '00';</line>
<line>    PSTATE.GE&lt;3:2&gt; = if diff2 &gt;= 0 then '11' else '00';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ssub8.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SSUB8" title="SSUB8 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SSUB8" />
  </docvars>
  <heading>SSUB8</heading>
  <desc>
    <brief>
      <para>Signed Subtract 8</para>
    </brief>
    <authored>
      <para>Signed Subtract 8 performs four 8-bit signed integer subtractions, and writes the results to the destination register. It sets <xref linkend="BEIDIGBH">PSTATE</xref>.GE according to the results of the subtractions.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SSUB8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SSUB8/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SSUB8_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SSUB8" />
        </docvars>
        <asmtemplate><text>SSUB8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SSUB8/A1_A.txt" mylink="aarch32.instrs.SSUB8.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SSUB8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SSUB8/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SSUB8_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SSUB8" />
        </docvars>
        <asmtemplate><text>SSUB8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SSUB8/T1_A.txt" mylink="aarch32.instrs.SSUB8.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SSUB8_A1, SSUB8_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSUB8_A1, SSUB8_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSUB8_A1, SSUB8_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSUB8_A1, SSUB8_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SSUB8_A1, SSUB8_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SSUB8/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    diff1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;7:0&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;7:0&gt;);</line>
<line>    diff2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:8&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:8&gt;);</line>
<line>    diff3 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;23:16&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;23:16&gt;);</line>
<line>    diff4 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:24&gt;) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:24&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;7:0&gt;   = diff1&lt;7:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:8&gt;  = diff2&lt;7:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;23:16&gt; = diff3&lt;7:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:24&gt; = diff4&lt;7:0&gt;;</line>
<line>    PSTATE.GE&lt;0&gt;  = if diff1 &gt;= 0 then '1' else '0';</line>
<line>    PSTATE.GE&lt;1&gt;  = if diff2 &gt;= 0 then '1' else '0';</line>
<line>    PSTATE.GE&lt;2&gt;  = if diff3 &gt;= 0 then '1' else '0';</line>
<line>    PSTATE.GE&lt;3&gt;  = if diff4 &gt;= 0 then '1' else '0';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="stc.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STC" title="STC -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STC" />
  </docvars>
  <heading>STC</heading>
  <desc>
    <brief>
      <para>Store data to System register</para>
    </brief>
    <authored>
      <para>Store data to System register calculates an address from a base register value and an immediate offset, and stores a word from the <xref linkend="AArch32.dbgdtrrxint">DBGDTRRXint</xref> System register to memory. It can use offset, post-indexed, pre-indexed, or unindexed addressing. For information about memory accesses, see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
      <para>In an implementation that includes EL2, the permitted <instruction>STC</instruction> access to <xref linkend="AArch32.dbgdtrrxint">DBGDTRRXint</xref> can be trapped to Hyp mode, meaning that an attempt to execute an <instruction>STC</instruction> instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see <xref linkend="BEICAABI">Trapping general Non-secure System register accesses to debug registers</xref>.</para>
      <para>For simplicity, the <instruction>STC</instruction> pseudocode does not show this possible trap to Hyp mode.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STC" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STC/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="CRd" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" name="cp15" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="STC_A1_off" oneofinclass="4" oneof="8" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STC" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> p14, c5, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="Immediate offset used for forming the address (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="STC_A1_post" oneofinclass="4" oneof="8" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STC" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> p14, c5, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="Immediate offset used for forming the address (field &quot;imm8&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="STC_A1_pre" oneofinclass="4" oneof="8" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STC" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> p14, c5, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="Immediate offset used for forming the address (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="STC_A1_unind" oneofinclass="4" oneof="8" label="Unindexed" bitdiffs="P == 0 &amp;&amp; U == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="unindexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STC" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> p14, c5, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa_option" hover="8-bit immediate [0-255 enclosed in { }] (field &quot;imm8&quot;)">&lt;option&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STC/T1A1_A.txt" mylink="aarch32.instrs.STC.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; U == '0' &amp;&amp; W == '0' then UNDEFINED;</line>
<line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  cp = 14;</line>
<line>imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);  index = (P == '1');  add = (U == '1');  wback = (W == '1');</line>
<line>if n == 15 &amp;&amp; (wback || <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == 15 &amp;&amp; wback</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_WBSUPPRESS" />
          <cu_type>
            <cu_type_text>The instruction executes with writeback to the PC. The instruction is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STC" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STC/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="CRd" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" name="cp15" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="STC_T1_off" oneofinclass="4" oneof="8" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STC" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> p14, c5, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="Immediate offset used for forming the address (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="STC_T1_post" oneofinclass="4" oneof="8" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STC" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> p14, c5, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="Immediate offset used for forming the address (field &quot;imm8&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="STC_T1_pre" oneofinclass="4" oneof="8" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STC" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> p14, c5, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="Immediate offset used for forming the address (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="STC_T1_unind" oneofinclass="4" oneof="8" label="Unindexed" bitdiffs="P == 0 &amp;&amp; U == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="unindexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STC" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> p14, c5, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa_option" hover="8-bit immediate [0-255 enclosed in { }] (field &quot;imm8&quot;)">&lt;option&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STC/T1A1_A.txt" mylink="aarch32.instrs.STC.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; U == '0' &amp;&amp; W == '0' then UNDEFINED;</line>
<line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  cp = 14;</line>
<line>imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);  index = (P == '1');  add = (U == '1');  wback = (W == '1');</line>
<line>if n == 15 &amp;&amp; (wback || <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_WBSUPPRESS" />
          <cu_type>
            <cu_type_text>The instruction executes with writeback to the PC. The instruction is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STC_A1_off, STC_T1_off" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STC_A1_off, STC_T1_off" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STC_A1_off, STC_A1_unind" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For the offset or unindexed variant: is the general-purpose base register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STC_A1_pre, STC_A1_post, STC_T1_off" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>For the offset, post-indexed or pre-indexed variant: is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STC_A1_unind, STC_T1_unind" symboldefcount="1">
      <symbol link="sa_option">&lt;option&gt;</symbol>
      <account encodedin="imm8">
        <intro>
          <para>Is an 8-bit immediate, in the range 0 to 255 enclosed in { }, encoded in the "imm8" field. The value of this field is ignored when executing this instruction.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STC_A1_off, STC_T1_off" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="STC_A1_off, STC_T1_off" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <intro>
          <para>Is the immediate offset used for forming the address, a multiple of 4 in the range 0-1020, defaulting to 0 and encoded in the "imm8" field, as &lt;imm&gt;/4.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STC/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);</line>
<line>    address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line></line>
<line>    // System register read from DBGDTRRXint.</line>
<line>    <a link="AArch32.SysRegRead.3" file="shared_pseudocode.xml" hover="function: AArch32.SysRegRead(integer cp_num, bits(32) instr, integer t)">AArch32.SysRegRead</a>(cp, <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>(), address&lt;31:0&gt;);</line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="stl.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STL" title="STL -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STL" />
  </docvars>
  <heading>STL</heading>
  <desc>
    <brief>
      <para>Store-Release Word</para>
    </brief>
    <authored>
      <para>Store-Release Word stores a word from a register to memory.  The instruction also has memory ordering semantics as described in <xref linkend="AA32CHDBDIDF">Load-Acquire, Store-Release</xref>.</para>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STL/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="xRd" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STL_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STL" />
        </docvars>
        <asmtemplate><text>STL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STL/A1_A.txt" mylink="aarch32.instrs.STL.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STL/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="sz" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rd" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="STL_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STL" />
        </docvars>
        <asmtemplate><text>STL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STL/T1_A.txt" mylink="aarch32.instrs.STL.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STL_A1, STL_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STL_A1, STL_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STL_A1, STL_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STL_A1, STL_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    <a link="impl-aarch32.MemO.write.2" file="shared_pseudocode.xml" hover="accessor: MemO[bits(32) address, integer size] = bits(8*size) value">MemO</a>[address, 4] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="stlb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STLB" title="STLB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STLB" />
  </docvars>
  <heading>STLB</heading>
  <desc>
    <brief>
      <para>Store-Release Byte</para>
    </brief>
    <authored>
      <para>Store-Release Byte stores a byte from a register to memory.  The instruction also has memory ordering semantics as described in <xref linkend="AA32CHDBDIDF">Load-Acquire, Store-Release</xref>.</para>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STLB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STLB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="xRd" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STLB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STLB" />
        </docvars>
        <asmtemplate><text>STLB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STLB/A1_A.txt" mylink="aarch32.instrs.STLB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STLB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STLB/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="sz" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rd" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="STLB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STLB" />
        </docvars>
        <asmtemplate><text>STLB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STLB/T1_A.txt" mylink="aarch32.instrs.STLB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STLB_A1, STLB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLB_A1, STLB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLB_A1, STLB_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLB_A1, STLB_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STLB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    <a link="impl-aarch32.MemO.write.2" file="shared_pseudocode.xml" hover="accessor: MemO[bits(32) address, integer size] = bits(8*size) value">MemO</a>[address, 1] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]&lt;7:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="stlex.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STLEX" title="STLEX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STLEX" />
  </docvars>
  <heading>STLEX</heading>
  <desc>
    <brief>
      <para>Store-Release Exclusive Word</para>
    </brief>
    <authored>
      <para>Store-Release Exclusive Word stores a word from a register to memory if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed.</para>
      <para>The instruction also has memory ordering semantics as described in <xref linkend="AA32CHDBDIDF">Load-Acquire, Store-Release</xref>.</para>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>Aborts and alignment</para>
      <para>If a synchronous Data Abort exception is generated by the execution of this instruction:</para>
      <list type="unordered">
        <listitem><content>Memory is not updated.</content></listitem>
        <listitem><content><syntax>&lt;Rd&gt;</syntax> is not updated.</content></listitem>
      </list>
      <para>A non word-aligned memory address causes an Alignment fault Data Abort exception to be generated, subject to the following rules:</para>
      <list type="unordered">
        <listitem><content>If <function>AArch32.ExclusiveMonitorsPass()</function> returns <enumvalue>TRUE</enumvalue>, the exception is generated.</content></listitem>
        <listitem><content>Otherwise, it is <arm-defined-word>implementation defined</arm-defined-word> whether the exception is generated.</content></listitem>
      </list>
      <para>If <function>AArch32.ExclusiveMonitorsPass()</function> returns <enumvalue>FALSE</enumvalue> and the memory address, if accessed, would generate a synchronous Data Abort exception, it is <arm-defined-word>implementation defined</arm-defined-word> whether the exception is generated.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STLEX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STLEX/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STLEX_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STLEX" />
        </docvars>
        <asmtemplate><text>STLEX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="Destination general-purpose register into which the status result of store exclusive is written (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STLEX/A1_A.txt" mylink="aarch32.instrs.STLEX.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;</line>
<line>if d == n || d == t then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == n</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs the store to an <arm-defined-word>unknown</arm-defined-word> address.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STLEX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STLEX/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" width="2" name="sz" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STLEX_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STLEX" />
        </docvars>
        <asmtemplate><text>STLEX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="Destination general-purpose register into which the status result of store exclusive is written (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STLEX/T1_A.txt" mylink="aarch32.instrs.STLEX.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;</line>
<line>if d == n || d == t then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == n</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs the store to an <arm-defined-word>unknown</arm-defined-word> address.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STLEX_A1, STLEX_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEX_A1, STLEX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEX_A1, STLEX_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the destination general-purpose register into which the status result of the store exclusive is written, encoded in the "Rd" field. The value returned is:</para>
          <list type="param">
            <listitem>
              <param>0</param><content>If the operation updates memory.</content>
            </listitem>
            <listitem>
              <param>1</param><content>If the operation fails to update memory.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEX_A1, STLEX_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEX_A1, STLEX_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STLEX/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    if <a link="AArch32.ExclusiveMonitorsPass.2" file="shared_pseudocode.xml" hover="function: boolean AArch32.ExclusiveMonitorsPass(bits(32) address, integer size)">AArch32.ExclusiveMonitorsPass</a>(address,4) then</line>
<line>        <a link="impl-aarch32.MemO.write.2" file="shared_pseudocode.xml" hover="accessor: MemO[bits(32) address, integer size] = bits(8*size) value">MemO</a>[address, 4] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('0', 32);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('1', 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="stlexb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STLEXB" title="STLEXB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STLEXB" />
  </docvars>
  <heading>STLEXB</heading>
  <desc>
    <brief>
      <para>Store-Release Exclusive Byte</para>
    </brief>
    <authored>
      <para>Store-Release Exclusive Byte stores a byte from a register to memory if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed.</para>
      <para>The instruction also has memory ordering semantics as described in <xref linkend="AA32CHDBDIDF">Load-Acquire, Store-Release</xref>.</para>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>Aborts</para>
      <para>If a synchronous Data Abort exception is generated by the execution of this instruction:</para>
      <list type="unordered">
        <listitem><content>Memory is not updated.</content></listitem>
        <listitem><content><syntax>&lt;Rd&gt;</syntax> is not updated.</content></listitem>
      </list>
      <para>If <function>AArch32.ExclusiveMonitorsPass()</function> returns <enumvalue>FALSE</enumvalue> and the memory address, if accessed, would generate a synchronous Data Abort exception, it is <arm-defined-word>implementation defined</arm-defined-word> whether the exception is generated.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STLEXB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STLEXB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STLEXB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STLEXB" />
        </docvars>
        <asmtemplate><text>STLEXB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="Destination general-purpose register into which the status result of store exclusive is written (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STLEXB/A1_A.txt" mylink="aarch32.instrs.STLEXB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;</line>
<line>if d == n || d == t then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == n</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs the store to an <arm-defined-word>unknown</arm-defined-word> address.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STLEXB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STLEXB/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" width="2" name="sz" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STLEXB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STLEXB" />
        </docvars>
        <asmtemplate><text>STLEXB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="Destination general-purpose register into which the status result of store exclusive is written (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STLEXB/T1_A.txt" mylink="aarch32.instrs.STLEXB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;</line>
<line>if d == n || d == t then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == n</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs the store to an <arm-defined-word>unknown</arm-defined-word> address.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STLEXB_A1, STLEXB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEXB_A1, STLEXB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEXB_A1, STLEXB_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the destination general-purpose register into which the status result of the store exclusive is written, encoded in the "Rd" field. The value returned is:</para>
          <list type="param">
            <listitem>
              <param>0</param><content>If the operation updates memory.</content>
            </listitem>
            <listitem>
              <param>1</param><content>If the operation fails to update memory.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEXB_A1, STLEXB_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEXB_A1, STLEXB_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STLEXB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    if <a link="AArch32.ExclusiveMonitorsPass.2" file="shared_pseudocode.xml" hover="function: boolean AArch32.ExclusiveMonitorsPass(bits(32) address, integer size)">AArch32.ExclusiveMonitorsPass</a>(address,1) then</line>
<line>        <a link="impl-aarch32.MemO.write.2" file="shared_pseudocode.xml" hover="accessor: MemO[bits(32) address, integer size] = bits(8*size) value">MemO</a>[address, 1] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]&lt;7:0&gt;;</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('0', 32);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('1', 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="stlexd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STLEXD" title="STLEXD -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STLEXD" />
  </docvars>
  <heading>STLEXD</heading>
  <desc>
    <brief>
      <para>Store-Release Exclusive Doubleword</para>
    </brief>
    <authored>
      <para>Store-Release Exclusive Doubleword stores a doubleword from two registers to memory if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed.</para>
      <para>The instruction also has memory ordering semantics as described in <xref linkend="AA32CHDBDIDF">Load-Acquire, Store-Release</xref>.</para>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>Aborts and alignment</para>
      <para>If a synchronous Data Abort exception is generated by the execution of this instruction:</para>
      <list type="unordered">
        <listitem><content>Memory is not updated.</content></listitem>
        <listitem><content><syntax>&lt;Rd&gt;</syntax> is not updated.</content></listitem>
      </list>
      <para>A non word-aligned memory address causes an Alignment fault Data Abort exception to be generated, subject to the following rules:</para>
      <list type="unordered">
        <listitem><content>If <function>AArch32.ExclusiveMonitorsPass()</function> returns <enumvalue>TRUE</enumvalue>, the exception is generated.</content></listitem>
        <listitem><content>Otherwise, it is <arm-defined-word>implementation defined</arm-defined-word> whether the exception is generated.</content></listitem>
      </list>
      <para>If <function>AArch32.ExclusiveMonitorsPass()</function> returns <enumvalue>FALSE</enumvalue> and the memory address, if accessed, would generate a synchronous Data Abort exception, it is <arm-defined-word>implementation defined</arm-defined-word> whether the exception is generated.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STLEXD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STLEXD/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STLEXD_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STLEXD" />
        </docvars>
        <asmtemplate><text>STLEXD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="Destination general-purpose register into which the status result of store exclusive is written (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rt_1" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2_1" hover="Second general-purpose register to be transferred">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STLEXD/A1_A.txt" mylink="aarch32.instrs.STLEXD.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = t+1;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if d == 15 || Rt&lt;0&gt; == '1' || t2 == 15 || n == 15 then UNPREDICTABLE;</line>
<line>if d == n || d == t || d == t2 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == n</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs the store to an <arm-defined-word>unknown</arm-defined-word> address.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>Rt&lt;0&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="Rt&lt;0&gt; = '0'" />
          </cu_type>
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="t2 = t" />
          </cu_type>
          <cu_type constraint="Constraint_NONE" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>Rt == '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STLEXD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STLEXD/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" width="2" name="sz" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STLEXD_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STLEXD" />
        </docvars>
        <asmtemplate><text>STLEXD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="Destination general-purpose register into which the status result of store exclusive is written (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rt" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STLEXD/T1_A.txt" mylink="aarch32.instrs.STLEXD.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if d == 15 || t == 15 || t2 == 15 || n == 15 then UNPREDICTABLE;</line>
<line>if d == n || d == t || d == t2 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == n</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs the store to an <arm-defined-word>unknown</arm-defined-word> address.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STLEXD_A1, STLEXD_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEXD_A1, STLEXD_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEXD_A1, STLEXD_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the destination general-purpose register into which the status result of the store exclusive is written, encoded in the "Rd" field. The value returned is:</para>
          <list type="param">
            <listitem>
              <param>0</param><content>If the operation updates memory.</content>
            </listitem>
            <listitem>
              <param>1</param><content>If the operation fails to update memory.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEXD_A1" symboldefcount="1">
      <symbol link="sa_rt_1">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the first general-purpose register to be transferred, encoded in the "Rt" field. <syntax>&lt;Rt&gt;</syntax> must be even-numbered and not R14.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEXD_T1" symboldefcount="2">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the first general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEXD_A1" symboldefcount="1">
      <symbol link="sa_rt2_1">&lt;Rt2&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the second general-purpose register to be transferred. <syntax>&lt;Rt2&gt;</syntax> must be <syntax>&lt;R(t+1)&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEXD_T1" symboldefcount="2">
      <symbol link="sa_rt2">&lt;Rt2&gt;</symbol>
      <account encodedin="Rt2">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the second general-purpose register to be transferred, encoded in the "Rt2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEXD_A1, STLEXD_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STLEXD/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    // Create doubleword to store such that R[t] will be stored at address and R[t2] at address+4.</line>
<line>    value = if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>) then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]:<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t2] else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t2]:<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];</line>
<line>    if <a link="AArch32.ExclusiveMonitorsPass.2" file="shared_pseudocode.xml" hover="function: boolean AArch32.ExclusiveMonitorsPass(bits(32) address, integer size)">AArch32.ExclusiveMonitorsPass</a>(address, 8) then</line>
<line>        <a link="impl-aarch32.MemO.write.2" file="shared_pseudocode.xml" hover="accessor: MemO[bits(32) address, integer size] = bits(8*size) value">MemO</a>[address, 8] = value;</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('0', 32);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('1', 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="stlexh.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STLEXH" title="STLEXH -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STLEXH" />
  </docvars>
  <heading>STLEXH</heading>
  <desc>
    <brief>
      <para>Store-Release Exclusive Halfword</para>
    </brief>
    <authored>
      <para>Store-Release Exclusive Halfword stores a halfword from a register to memory if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed.</para>
      <para>The instruction also has memory ordering semantics as described in <xref linkend="AA32CHDBDIDF">Load-Acquire, Store-Release</xref>.</para>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>Aborts and alignment</para>
      <para>If a synchronous Data Abort exception is generated by the execution of this instruction:</para>
      <list type="unordered">
        <listitem><content>Memory is not updated</content></listitem>
        <listitem><content><syntax>&lt;Rd&gt;</syntax> is not updated.</content></listitem>
      </list>
      <para>A non word-aligned memory address causes an Alignment fault Data Abort exception to be generated, subject to the following rules:</para>
      <list type="unordered">
        <listitem><content>If <function>AArch32.ExclusiveMonitorsPass()</function> returns <enumvalue>TRUE</enumvalue>, the exception is generated.</content></listitem>
        <listitem><content>Otherwise, it is <arm-defined-word>implementation defined</arm-defined-word> whether the exception is generated.</content></listitem>
      </list>
      <para>If <function>AArch32.ExclusiveMonitorsPass()</function> returns <enumvalue>FALSE</enumvalue> and the memory address, if accessed, would generate a synchronous Data Abort exception, it is <arm-defined-word>implementation defined</arm-defined-word> whether the exception is generated.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STLEXH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STLEXH/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STLEXH_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STLEXH" />
        </docvars>
        <asmtemplate><text>STLEXH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="Destination general-purpose register into which the status result of store exclusive is written (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STLEXH/A1_A.txt" mylink="aarch32.instrs.STLEXH.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;</line>
<line>if d == n || d == t then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == n</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs the store to an <arm-defined-word>unknown</arm-defined-word> address.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STLEXH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STLEXH/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" width="2" name="sz" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STLEXH_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STLEXH" />
        </docvars>
        <asmtemplate><text>STLEXH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="Destination general-purpose register into which the status result of store exclusive is written (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STLEXH/T1_A.txt" mylink="aarch32.instrs.STLEXH.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;</line>
<line>if d == n || d == t then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == n</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs the store to an <arm-defined-word>unknown</arm-defined-word> address.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STLEXH_A1, STLEXH_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEXH_A1, STLEXH_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEXH_A1, STLEXH_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the destination general-purpose register into which the status result of the store exclusive is written, encoded in the "Rd" field. The value returned is:</para>
          <list type="param">
            <listitem>
              <param>0</param><content>If the operation updates memory.</content>
            </listitem>
            <listitem>
              <param>1</param><content>If the operation fails to update memory.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEXH_A1, STLEXH_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEXH_A1, STLEXH_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STLEXH/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    if <a link="AArch32.ExclusiveMonitorsPass.2" file="shared_pseudocode.xml" hover="function: boolean AArch32.ExclusiveMonitorsPass(bits(32) address, integer size)">AArch32.ExclusiveMonitorsPass</a>(address,2) then</line>
<line>        <a link="impl-aarch32.MemO.write.2" file="shared_pseudocode.xml" hover="accessor: MemO[bits(32) address, integer size] = bits(8*size) value">MemO</a>[address, 2] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]&lt;15:0&gt;;</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('0', 32);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('1', 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="stlh.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STLH" title="STLH -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STLH" />
  </docvars>
  <heading>STLH</heading>
  <desc>
    <brief>
      <para>Store-Release Halfword</para>
    </brief>
    <authored>
      <para>Store-Release Halfword stores a halfword from a register to memory. The instruction also has memory ordering semantics as described in <xref linkend="AA32CHDBDIDF">Load-Acquire, Store-Release</xref>.</para>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STLH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STLH/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="xRd" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STLH_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STLH" />
        </docvars>
        <asmtemplate><text>STLH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STLH/A1_A.txt" mylink="aarch32.instrs.STLH.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STLH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STLH/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="sz" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rd" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
      </regdiagram>
      <encoding name="STLH_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STLH" />
        </docvars>
        <asmtemplate><text>STLH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STLH/T1_A.txt" mylink="aarch32.instrs.STLH.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if t == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STLH_A1, STLH_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLH_A1, STLH_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLH_A1, STLH_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLH_A1, STLH_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STLH/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    <a link="impl-aarch32.MemO.write.2" file="shared_pseudocode.xml" hover="accessor: MemO[bits(32) address, integer size] = bits(8*size) value">MemO</a>[address, 2] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]&lt;15:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="stm.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STM" title="STM, STMIA, STMEA -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STM" />
  </docvars>
  <heading>STM, STMIA, STMEA</heading>
  <desc>
    <brief>
      <para>Store Multiple (Increment After, Empty Ascending)</para>
    </brief>
    <authored>
      <para>Store Multiple (Increment After, Empty Ascending) stores multiple registers to consecutive memory locations using an address from a base register. The consecutive memory locations start at this address, and the address just above the last of those locations can optionally be written back to the base register.</para>
      <para>The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register from the highest memory address. See also <xref linkend="CHDDBEDG">Encoding of lists of general-purpose registers and the PC</xref>.</para>
      <para>Armv8.2 permits the deprecation of some Store Multiple ordering behaviors in AArch32 state, for more information see <xref linkend="v8.2.LSMAOC">FEAT_LSMAOC</xref>. For details of related system instructions see <xref linkend="A32T32-base.instructions.STM_u">STM (User registers)</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STM/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="16" name="register_list" usename="1">
          <c colspan="16"></c>
        </box>
      </regdiagram>
      <encoding name="STM_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STM" />
        </docvars>
        <asmtemplate comment="Preferred syntax"><text>STM</text><a link="sa_ia" hover="Optional suffix for Increment After form">{IA}</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers_2" hover="List of one or more registers to be stored">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate comment="Alternate syntax, Empty Ascending stack"><text>STMEA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers_2" hover="List of one or more registers to be stored">&lt;registers&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STM/A1_A.txt" mylink="aarch32.instrs.STM.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  registers = register_list;  wback = (W == '1');</line>
<line>if n == 15 || <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) &lt; 1 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>BitCount(registers) &lt; 1</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction operates as an <instruction>STM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers stored.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == 15 &amp;&amp; wback</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_WBSUPPRESS" />
          <cu_type>
            <cu_type_text>The instruction executes with writeback to the PC. The instruction is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/STM/T1_A.txt">
        <box hibit="31" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="27" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="26" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="23" width="8" name="register_list" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="STM_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STM" />
        </docvars>
        <asmtemplate comment="Preferred syntax"><text>STM</text><a link="sa_ia" hover="Optional suffix for Increment After form">{IA}</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>!, </text><a link="sa_registers" hover="List of one or more registers to be stored (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate comment="Alternate syntax, Empty Ascending stack"><text>STMEA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>!, </text><a link="sa_registers" hover="List of one or more registers to be stored (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STM/T1_A.txt" mylink="aarch32.instrs.STM.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  registers = '00000000':register_list;  wback = TRUE;</line>
<line>if <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) &lt; 1 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>BitCount(registers) &lt; 1</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction operates as an <instruction>STM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers stored.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == 15 &amp;&amp; wback</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_WBSUPPRESS" />
          <cu_type>
            <cu_type_text>The instruction executes with writeback to the PC. The instruction is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STM/T2_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" name="P" usename="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="13" width="14" name="register_list" usename="1">
          <c colspan="14"></c>
        </box>
      </regdiagram>
      <encoding name="STM_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STM" />
        </docvars>
        <asmtemplate comment="Preferred syntax, if &lt;Rn&gt;, '!' and &lt;registers&gt; can be represented in T1"><text>STM</text><a link="sa_ia" hover="Optional suffix for Increment After form">{IA}</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers_1" hover="List of one or more registers to be stored (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate comment="Alternate syntax, Empty Ascending stack, if &lt;Rn&gt;, '!' and &lt;registers&gt; can be represented in T1"><text>STMEA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers_1" hover="List of one or more registers to be stored (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate comment="Preferred syntax"><text>STM</text><a link="sa_ia" hover="Optional suffix for Increment After form">{IA}</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers_1" hover="List of one or more registers to be stored (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate comment="Alternate syntax, Empty Ascending stack"><text>STMEA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers_1" hover="List of one or more registers to be stored (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STM/T2_A.txt" mylink="aarch32.instrs.STM.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  registers = P:M:register_list;  wback = (W == '1');</line>
<line>if n == 15 || <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) &lt; 2 then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; registers&lt;n&gt; == '1' then UNPREDICTABLE;</line>
<line>if registers&lt;13&gt; == '1' then UNPREDICTABLE;</line>
<line>if registers&lt;15&gt; == '1' then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>BitCount(registers) &lt; 1</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction operates as an <instruction>STM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers stored.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>BitCount(registers) == 1</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_NONE" />
          <cu_type>
            <cu_type_text>The instruction operates as an <instruction>STM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; registers&lt;n&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_BASEUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>registers&lt;13&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs all of the stores using the specified addressing mode but the value of R13 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>registers&lt;15&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs all of the stores using the specified addressing mode but the value of R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == 15 &amp;&amp; wback</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_WBSUPPRESS" />
          <cu_type>
            <cu_type_text>The instruction executes with writeback to the PC. The instruction is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STM_A1, STM_T1, STM_T2" symboldefcount="1">
      <symbol link="sa_ia">IA</symbol>
      <account encodedin="">
        <intro>
          <para>Is an optional suffix for the Increment After form.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STM_A1, STM_T1, STM_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STM_A1, STM_T1, STM_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STM_A1, STM_T1, STM_T2" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STM_A1, STM_T2" symboldefcount="1">
      <symbol link="sa_0d33">!</symbol>
      <account encodedin="W">
        <intro>
          <para>The address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STM_A1" symboldefcount="1">
      <symbol link="sa_registers_2">&lt;registers&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is a list of one or more registers to be stored, separated by commas and surrounded by { and }.</para>
          <para>The PC can be in the list. However, Arm deprecates the use of instructions that include the PC in the list.</para>
          <para>If base register writeback is specified, and the base register is not the lowest-numbered register in the list, such an instruction stores an <arm-defined-word>unknown</arm-defined-word> value for the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STM_T1" symboldefcount="2">
      <symbol link="sa_registers">&lt;registers&gt;</symbol>
      <account encodedin="register_list">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is a list of one or more registers to be stored, separated by commas and surrounded by { and }. The registers in the list must be in the range R0-R7, encoded in the "register_list" field. If the base register is not the lowest-numbered register in the list, such an instruction stores an <arm-defined-word>unknown</arm-defined-word> value for the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STM_T2" symboldefcount="3">
      <symbol link="sa_registers_1">&lt;registers&gt;</symbol>
      <account encodedin="register_list">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is a list of one or more registers to be stored, separated by commas and surrounded by { and }.</para>
          <para>The registers in the list must be in the range R0-R12, encoded in the "register_list" field, and can optionally contain the LR. If the LR is in the list, the "M" field is set to 1, otherwise it defaults to 0.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STM/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    for i = 0 to 14</line>
<line>        if registers&lt;i&gt; == '1' then</line>
<line>            if i == n &amp;&amp; wback &amp;&amp; i != <a link="impl-shared.LowestSetBit.1" file="shared_pseudocode.xml" hover="function: integer LowestSetBit(bits(N) x)">LowestSetBit</a>(registers) then</line>
<line>                <a link="impl-aarch32.MemS.write.2" file="shared_pseudocode.xml" hover="accessor: MemS[bits(32) address, integer size] = bits(8*size) value">MemS</a>[address,4] = bits(32) UNKNOWN;  // Only possible for encodings T1 and A1</line>
<line>            else</line>
<line>                <a link="impl-aarch32.MemS.write.2" file="shared_pseudocode.xml" hover="accessor: MemS[bits(32) address, integer size] = bits(8*size) value">MemS</a>[address,4] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[i];</line>
<line>            address = address + 4;</line>
<line>    if registers&lt;15&gt; == '1' then  // Only possible for encoding A1</line>
<line>        <a link="impl-aarch32.MemS.write.2" file="shared_pseudocode.xml" hover="accessor: MemS[bits(32) address, integer size] = bits(8*size) value">MemS</a>[address,4] = <a link="impl-aarch32.PCStoreValue.0" file="shared_pseudocode.xml" hover="function: bits(32) PCStoreValue()">PCStoreValue</a>();</line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 4*<a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="stm_u.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STM_u" title="STM (User registers) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
    <docvar key="mnemonic" value="STM" />
  </docvars>
  <heading>STM (User registers)</heading>
  <desc>
    <brief>
      <para>Store Multiple (User registers)</para>
    </brief>
    <authored>
      <para>In an EL1 mode other than System mode, Store Multiple (User registers) stores multiple User mode registers to consecutive memory locations using an address from a base register. The PE reads the base register value normally, using the current mode to determine the correct Banked version of the register. This instruction cannot writeback to the base register.</para>
      <para>Store Multiple (User registers) is <arm-defined-word>undefined</arm-defined-word> in Hyp mode, and <arm-defined-word>constrained unpredictable</arm-defined-word> in User or System modes.</para>
      <para>Armv8.2 permits the deprecation of some Store Multiple ordering behaviors in AArch32 state, for more information see <xref linkend="v8.2.LSMAOC">FEAT_LSMAOC</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STM_u/A1_AS.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="16" name="register_list" usename="1">
          <c colspan="16"></c>
        </box>
      </regdiagram>
      <encoding name="STM_u_A1_AS" oneofinclass="1" oneof="1" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STM" />
        </docvars>
        <asmtemplate><text>STM</text><text>{</text><a link="sa_amode" hover="One of:&#10;$DA: Decrement After">&lt;amode&gt;</a><text>}</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_registers" hover="List of one or more registers, separated by commas and surrounded by { and }">&lt;registers&gt;</a><text>^</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STM_u/A1_AS.txt" mylink="aarch32.instrs.STM_u.A1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  registers = register_list;  increment = (U == '1');  wordhigher = (P == U);</line>
<line>if n == 15 || <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) &lt; 1 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>BitCount(registers) &lt; 1</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction operates as an <instruction>STM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STM_u_A1_AS" symboldefcount="1">
      <symbol link="sa_amode">&lt;amode&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>is one of:</para>
          <list type="param">
            <listitem>
              <param>DA</param><content>Decrement After. The consecutive memory addresses end at the address in the base register. Encoded as P = 0, U = 0.</content>
            </listitem>
            <listitem>
              <param>ED</param><content>Empty Descending. For this instruction, a synonym for <value>DA</value>.</content>
            </listitem>
            <listitem>
              <param>DB</param><content>Decrement Before. The consecutive memory addresses end one word below the address in the base register. Encoded as P = 1, U = 0.</content>
            </listitem>
            <listitem>
              <param>FD</param><content>Full Descending. For this instruction, a synonym for <value>DB</value>.</content>
            </listitem>
            <listitem>
              <param>IA</param><content>Increment After. The consecutive memory addresses start at the address in the base register. This is the default. Encoded as P = 0, U = 1.</content>
            </listitem>
            <listitem>
              <param>EA</param><content>Empty Ascending. For this instruction, a synonym for <value>IA</value>.</content>
            </listitem>
            <listitem>
              <param>IB</param><content>Increment Before. The consecutive memory addresses start one word above the address in the base register. Encoded as P = 1, U = 1.</content>
            </listitem>
            <listitem>
              <param>FA</param><content>Full Ascending. For this instruction, a synonym for <value>IB</value>.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STM_u_A1_AS" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STM_u_A1_AS" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STM_u_A1_AS" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STM_u_A1_AS" symboldefcount="1">
      <symbol link="sa_registers">&lt;registers&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is a list of one or more registers, separated by commas and surrounded by { and }. It specifies the set of registers to be stored by the <instruction>STM</instruction> instruction. The registers are stored with the lowest-numbered register to the lowest memory address, through to the highest-numbered register to the highest memory address. See also <xref linkend="CHDDBEDG">Encoding of lists of general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STM_u/Op_AS.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>        UNDEFINED;</line>
<line>    elsif PSTATE.M IN {<a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a>,<a link="M32_System" file="shared_pseudocode.xml" hover="constant bits(5) M32_System = '11111'">M32_System</a>} then</line>
<line>        UNPREDICTABLE;</line>
<line>    else</line>
<line>        length = 4*<a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers);</line>
<line>        address = if increment then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]-length;</line>
<line>        if wordhigher then address = address+4;</line>
<line>        for i = 0 to 14</line>
<line>            if registers&lt;i&gt; == '1' then  // Store User mode register</line>
<line>                <a link="impl-aarch32.MemS.write.2" file="shared_pseudocode.xml" hover="accessor: MemS[bits(32) address, integer size] = bits(8*size) value">MemS</a>[address,4] = <a link="impl-aarch32.Rmode.read.2" file="shared_pseudocode.xml" hover="accessor: bits(32) Rmode[integer n, bits(5) mode]">Rmode</a>[i, <a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a>];</line>
<line>                address = address + 4;</line>
<line>        if registers&lt;15&gt; == '1' then</line>
<line>            <a link="impl-aarch32.MemS.write.2" file="shared_pseudocode.xml" hover="accessor: MemS[bits(32) address, integer size] = bits(8*size) value">MemS</a>[address,4] = <a link="impl-aarch32.PCStoreValue.0" file="shared_pseudocode.xml" hover="function: bits(32) PCStoreValue()">PCStoreValue</a>();</line>
</pstext>
    </ps>
  </ps_section>
  <constrained_unpredictables ps_block="Operation">
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>PSTATE.M IN {M32_User,M32_System}</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
      <cu_type>
        <cu_type_text>The instruction operates as an <instruction>STM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15.</cu_type_text>
      </cu_type>
    </cu_case>
  </constrained_unpredictables>
</instructionsection>
</file>
<file type="instructionsection" file="stmda.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STMDA" title="STMDA, STMED -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
    <docvar key="mnemonic" value="STM" />
  </docvars>
  <heading>STMDA, STMED</heading>
  <desc>
    <brief>
      <para>Store Multiple Decrement After (Empty Descending)</para>
    </brief>
    <authored>
      <para>Store Multiple Decrement After (Empty Descending) stores multiple registers to consecutive memory locations using an address from a base register. The consecutive memory locations end at this address, and the address just below the lowest of those locations can optionally be written back to the base register.</para>
      <para>The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register from the highest memory address. See also <xref linkend="CHDDBEDG">Encoding of lists of general-purpose registers and the PC</xref>.</para>
      <para>Armv8.2 permits the deprecation of some Store Multiple ordering behaviors in AArch32 state, for more information see <xref linkend="v8.2.LSMAOC">FEAT_LSMAOC</xref>. For details of related system instructions see <xref linkend="A32T32-base.instructions.STM_u">STM (User registers)</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STMDA/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="16" name="register_list" usename="1">
          <c colspan="16"></c>
        </box>
      </regdiagram>
      <encoding name="STMDA_A1" oneofinclass="1" oneof="1" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STM" />
        </docvars>
        <asmtemplate comment="Preferred syntax"><text>STMDA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers" hover="List of one or more registers to be stored">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate comment="Alternate syntax, Empty Descending stack"><text>STMED</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers" hover="List of one or more registers to be stored">&lt;registers&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STMDA/A1_A.txt" mylink="aarch32.instrs.STMDA.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  registers = register_list;  wback = (W == '1');</line>
<line>if n == 15 || <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) &lt; 1 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>BitCount(registers) &lt; 1</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction targets an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers stored.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == 15 &amp;&amp; wback</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_WBSUPPRESS" />
          <cu_type>
            <cu_type_text>The instruction uses the addressing mode described in the equivalent immediate offset instruction.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STMDA_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STMDA_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STMDA_A1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STMDA_A1" symboldefcount="1">
      <symbol link="sa_0d33">!</symbol>
      <account encodedin="W">
        <intro>
          <para>The address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STMDA_A1" symboldefcount="1">
      <symbol link="sa_registers">&lt;registers&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is a list of one or more registers to be stored, separated by commas and surrounded by { and }.</para>
          <para>The PC can be in the list. However, Arm deprecates the use of instructions that include the PC in the list.</para>
          <para>If base register writeback is specified, and the base register is not the lowest-numbered register in the list, such an instruction stores an <arm-defined-word>unknown</arm-defined-word> value for the base register.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STMDA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - 4*<a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) + 4;</line>
<line>    for i = 0 to 14</line>
<line>        if registers&lt;i&gt; == '1' then</line>
<line>            if i == n &amp;&amp; wback &amp;&amp; i != <a link="impl-shared.LowestSetBit.1" file="shared_pseudocode.xml" hover="function: integer LowestSetBit(bits(N) x)">LowestSetBit</a>(registers) then</line>
<line>                <a link="impl-aarch32.MemS.write.2" file="shared_pseudocode.xml" hover="accessor: MemS[bits(32) address, integer size] = bits(8*size) value">MemS</a>[address,4] = bits(32) UNKNOWN;</line>
<line>            else</line>
<line>                <a link="impl-aarch32.MemS.write.2" file="shared_pseudocode.xml" hover="accessor: MemS[bits(32) address, integer size] = bits(8*size) value">MemS</a>[address,4] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[i];</line>
<line>            address = address + 4;</line>
<line>    if registers&lt;15&gt; == '1' then</line>
<line>        <a link="impl-aarch32.MemS.write.2" file="shared_pseudocode.xml" hover="accessor: MemS[bits(32) address, integer size] = bits(8*size) value">MemS</a>[address,4] = <a link="impl-aarch32.PCStoreValue.0" file="shared_pseudocode.xml" hover="function: bits(32) PCStoreValue()">PCStoreValue</a>();</line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - 4*<a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="stmdb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STMDB" title="STMDB, STMFD -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STM" />
  </docvars>
  <heading>STMDB, STMFD</heading>
  <desc>
    <brief>
      <para>Store Multiple Decrement Before (Full Descending)</para>
    </brief>
    <authored>
      <para>Store Multiple Decrement Before (Full Descending) stores multiple registers to consecutive memory locations using an address from a base register. The consecutive memory locations end just below this address, and the address of the first of those locations can optionally be written back to the base register.</para>
      <para>The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register from the highest memory address. See also <xref linkend="CHDDBEDG">Encoding of lists of general-purpose registers and the PC</xref>.</para>
      <para>Armv8.2 permits the deprecation of some Store Multiple ordering behaviors in AArch32 state, for more information see <xref linkend="v8.2.LSMAOC">FEAT_LSMAOC</xref>. For details of related system instructions see <xref linkend="A32T32-base.instructions.STM_u">STM (User registers)</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="1">
    <alias_list_intro>This instruction is used by the alias </alias_list_intro>
    <aliasref aliaspageid="PUSH_STMDB" aliasfile="push_stmdb.xml" hover="Push multiple registers to Stack" punct=".">
      <text>PUSH (multiple registers)</text>
      <aliaspref labels="T1">W == '1' &amp;&amp; Rn == '1101' &amp;&amp; <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(M:register_list) &gt; 1</aliaspref>
      <aliaspref labels="A1">W == '1' &amp;&amp; Rn == '1101' &amp;&amp; <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(register_list) &gt; 1</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink />
      <text> below for details of when the alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STMDB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="16" name="register_list" usename="1">
          <c colspan="16"></c>
        </box>
      </regdiagram>
      <encoding name="STMDB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STM" />
        </docvars>
        <asmtemplate comment="Preferred syntax"><text>STMDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers_1" hover="List of one or more registers to be stored">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate comment="Alternate syntax, Full Descending stack"><text>STMFD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers_1" hover="List of one or more registers to be stored">&lt;registers&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STMDB/A1_A.txt" mylink="aarch32.instrs.STMDB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  registers = register_list;  wback = (W == '1');</line>
<line>if n == 15 || <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) &lt; 1 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>BitCount(registers) &lt; 1</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction operates as an <instruction>STM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers stored.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STMDB/T1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="opc" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" name="P" usename="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="13" width="14" name="register_list" usename="1">
          <c colspan="14"></c>
        </box>
      </regdiagram>
      <encoding name="STMDB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STM" />
        </docvars>
        <asmtemplate comment="Preferred syntax"><text>STMDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers" hover="List of one or more registers to be stored (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate comment="Alternate syntax, Full Descending stack"><text>STMFD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers" hover="List of one or more registers to be stored (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STMDB/T1_A.txt" mylink="aarch32.instrs.STMDB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  registers = P:M:register_list;  wback = (W == '1');</line>
<line>if n == 15 || <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) &lt; 2 then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; registers&lt;n&gt; == '1' then UNPREDICTABLE;</line>
<line>if registers&lt;13&gt; == '1' then UNPREDICTABLE;</line>
<line>if registers&lt;15&gt; == '1' then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>BitCount(registers) &lt; 1</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction operates as an <instruction>STM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers stored.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; registers&lt;n&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_BASEUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>BitCount(registers) == 1</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_NONE" />
          <cu_type>
            <cu_type_text>The instruction operates as an <instruction>STM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>registers&lt;13&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_NONE" />
          <cu_type>
            <cu_type_text>The store instruction performs all of the stores using the specified addressing mode but the value of R13 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>registers&lt;15&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs all of the stores using the specified addressing mode but the value of R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STMDB_A1, STMDB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STMDB_A1, STMDB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STMDB_A1, STMDB_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STMDB_A1, STMDB_T1" symboldefcount="1">
      <symbol link="sa_0d33">!</symbol>
      <account encodedin="W">
        <intro>
          <para>The address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STMDB_A1" symboldefcount="1">
      <symbol link="sa_registers_1">&lt;registers&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is a list of one or more registers to be stored, separated by commas and surrounded by { and }.</para>
          <para>The PC can be in the list. However, Arm deprecates the use of instructions that include the PC in the list.</para>
          <para>If base register writeback is specified, and the base register is not the lowest-numbered register in the list, such an instruction stores an <arm-defined-word>unknown</arm-defined-word> value for the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STMDB_T1" symboldefcount="2">
      <symbol link="sa_registers">&lt;registers&gt;</symbol>
      <account encodedin="register_list">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is a list of one or more registers to be stored, separated by commas and surrounded by { and }.</para>
          <para>The registers in the list must be in the range R0-R12, encoded in the "register_list" field, and can optionally contain the LR. If the LR is in the list, the "M" field is set to 1, otherwise it defaults to 0.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STMDB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - 4*<a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers);</line>
<line>    for i = 0 to 14</line>
<line>        if registers&lt;i&gt; == '1' then</line>
<line>            if i == n &amp;&amp; wback &amp;&amp; i != <a link="impl-shared.LowestSetBit.1" file="shared_pseudocode.xml" hover="function: integer LowestSetBit(bits(N) x)">LowestSetBit</a>(registers) then</line>
<line>                <a link="impl-aarch32.MemS.write.2" file="shared_pseudocode.xml" hover="accessor: MemS[bits(32) address, integer size] = bits(8*size) value">MemS</a>[address,4] = bits(32) UNKNOWN;  // Only possible for encoding A1</line>
<line>            else</line>
<line>                <a link="impl-aarch32.MemS.write.2" file="shared_pseudocode.xml" hover="accessor: MemS[bits(32) address, integer size] = bits(8*size) value">MemS</a>[address,4] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[i];</line>
<line>            address = address + 4;</line>
<line>    if registers&lt;15&gt; == '1' then  // Only possible for encoding A1</line>
<line>        <a link="impl-aarch32.MemS.write.2" file="shared_pseudocode.xml" hover="accessor: MemS[bits(32) address, integer size] = bits(8*size) value">MemS</a>[address,4] = <a link="impl-aarch32.PCStoreValue.0" file="shared_pseudocode.xml" hover="function: bits(32) PCStoreValue()">PCStoreValue</a>();</line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - 4*<a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="stmib.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STMIB" title="STMIB, STMFA -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
    <docvar key="mnemonic" value="STM" />
  </docvars>
  <heading>STMIB, STMFA</heading>
  <desc>
    <brief>
      <para>Store Multiple Increment Before (Full Ascending)</para>
    </brief>
    <authored>
      <para>Store Multiple Increment Before (Full Ascending) stores multiple registers to consecutive memory locations using an address from a base register. The consecutive memory locations start just above this address, and the address of the last of those locations can optionally be written back to the base register.</para>
      <para>The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register from the highest memory address. See also <xref linkend="CHDDBEDG">Encoding of lists of general-purpose registers and the PC</xref>.</para>
      <para>Armv8.2 permits the deprecation of some Store Multiple ordering behaviors in AArch32 state, for more information see <xref linkend="v8.2.LSMAOC">FEAT_LSMAOC</xref>. For details of related system instructions see <xref linkend="A32T32-base.instructions.STM_u">STM (User registers)</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STMIB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="16" name="register_list" usename="1">
          <c colspan="16"></c>
        </box>
      </regdiagram>
      <encoding name="STMIB_A1" oneofinclass="1" oneof="1" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STM" />
        </docvars>
        <asmtemplate comment="Preferred syntax"><text>STMIB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers" hover="List of one or more registers to be stored">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate comment="Alternate syntax, Full Ascending stack"><text>STMFA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_registers" hover="List of one or more registers to be stored">&lt;registers&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STMIB/A1_A.txt" mylink="aarch32.instrs.STMIB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  registers = register_list;  wback = (W == '1');</line>
<line>if n == 15 || <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers) &lt; 1 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>BitCount(registers) &lt; 1</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction operates as an <instruction>STM</instruction> with the same addressing mode but targeting an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers stored.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == 15 &amp;&amp; wback</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_WBSUPPRESS" />
          <cu_type>
            <cu_type_text>The instruction uses the addressing mode described in the equivalent immediate offset instruction.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STMIB_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STMIB_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STMIB_A1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STMIB_A1" symboldefcount="1">
      <symbol link="sa_0d33">!</symbol>
      <account encodedin="W">
        <intro>
          <para>The address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STMIB_A1" symboldefcount="1">
      <symbol link="sa_registers">&lt;registers&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is a list of one or more registers to be stored, separated by commas and surrounded by { and }.</para>
          <para>The PC can be in the list. However, Arm deprecates the use of instructions that include the PC in the list.</para>
          <para>If base register writeback is specified, and the base register is not the lowest-numbered register in the list, such an instruction stores an <arm-defined-word>unknown</arm-defined-word> value for the base register.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STMIB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 4;</line>
<line>    for i = 0 to 14</line>
<line>        if registers&lt;i&gt; == '1' then</line>
<line>            if i == n &amp;&amp; wback &amp;&amp; i != <a link="impl-shared.LowestSetBit.1" file="shared_pseudocode.xml" hover="function: integer LowestSetBit(bits(N) x)">LowestSetBit</a>(registers) then</line>
<line>                <a link="impl-aarch32.MemS.write.2" file="shared_pseudocode.xml" hover="accessor: MemS[bits(32) address, integer size] = bits(8*size) value">MemS</a>[address,4] = bits(32) UNKNOWN;</line>
<line>            else</line>
<line>                <a link="impl-aarch32.MemS.write.2" file="shared_pseudocode.xml" hover="accessor: MemS[bits(32) address, integer size] = bits(8*size) value">MemS</a>[address,4] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[i];</line>
<line>            address = address + 4;</line>
<line>    if registers&lt;15&gt; == '1' then</line>
<line>        <a link="impl-aarch32.MemS.write.2" file="shared_pseudocode.xml" hover="accessor: MemS[bits(32) address, integer size] = bits(8*size) value">MemS</a>[address,4] = <a link="impl-aarch32.PCStoreValue.0" file="shared_pseudocode.xml" hover="function: bits(32) PCStoreValue()">PCStoreValue</a>();</line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 4*<a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(registers);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="str_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STR_i" title="STR (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STR" />
  </docvars>
  <heading>STR (immediate)</heading>
  <desc>
    <brief>
      <para>Store Register (immediate)</para>
    </brief>
    <authored>
      <para>Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="1">
    <alias_list_intro>This instruction is used by the alias </alias_list_intro>
    <aliasref aliaspageid="PUSH_STR_i" aliasfile="push_str_i.xml" hover="Push Single Register to Stack" punct=".">
      <text>PUSH (single register)</text>
      <aliaspref labels="A1 (pre-indexed)">P == '1' &amp;&amp; U == '0' &amp;&amp; W == '1' &amp;&amp; Rn == '1101' &amp;&amp; imm12 == '000000000100'</aliaspref>
      <aliaspref labels="T4 (pre-indexed)">Rn == '1101' &amp;&amp; P == '1' &amp;&amp; U == '0' &amp;&amp; W == '1' &amp;&amp; imm8 == '00000100'</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink />
      <text> below for details of when the alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <classesintro count="5">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt>, </txt>
      <a href="#iclass_t3">T3</a>
      <txt> and </txt>
      <a href="#iclass_t4">T4</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="5" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STR" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STR_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="STR_i_A1_off" oneofinclass="3" oneof="9" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_4" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="STR_i_A1_post" oneofinclass="3" oneof="9" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_4" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="STR_i_A1_pre" oneofinclass="3" oneof="9" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_4" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STR_i/A1_A.txt" mylink="aarch32.instrs.STR_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; W == '1' then SEE "STRT";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>if wback &amp;&amp; (n == 15 || n == t) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_WBSUPPRESS" />
          <cu_type>
            <cu_type_text>The instruction uses the addressing mode described in the equivalent immediate offset instruction.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="5" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/STR_i/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="26" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="21" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rt" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="STR_i_T1" oneofinclass="1" oneof="9" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional positive unsigned immediate byte offset (field &quot;imm5&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STR_i/T1_A.txt" mylink="aarch32.instrs.STR_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm5:'00', 32);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="5" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/STR_i/T2_A.txt">
        <box hibit="31" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="27" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="26" width="3" name="Rt" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="23" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="STR_i_T2" oneofinclass="1" oneof="9" label="T2">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [SP</text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm_1" hover="Optional positive unsigned immediate byte offset (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STR_i/T2_A.txt" mylink="aarch32.instrs.STR_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = 13;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T3" oneof="5" id="iclass_t3" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STR_i/T3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="STR_i_T3" oneofinclass="1" oneof="9" label="T3">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <asmtemplate comment="&lt;Rt&gt;, &lt;Rn&gt;, &lt;imm&gt; can be represented in T1 or T2"><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm_2" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm_2" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STR_i/T3_A.txt" mylink="aarch32.instrs.STR_i.T3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then UNDEFINED;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
<line>if t == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T4" oneof="5" id="iclass_t4" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T4" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STR" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STR_i/T4_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="9" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="8" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="STR_i_T4_off" oneofinclass="3" oneof="9" label="Offset" bitdiffs="P == 1 &amp;&amp; U == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="9" width="1" name="U">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #-</text><a link="sa_imm_3" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="STR_i_T4_post" oneofinclass="3" oneof="9" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_3" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="STR_i_T4_pre" oneofinclass="3" oneof="9" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_3" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STR_i/T4_A.txt" mylink="aarch32.instrs.STR_i.T4_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '1' &amp;&amp; U == '1' &amp;&amp; W == '0' then SEE "STRT";</line>
<line>if Rn == '1111' || (P == '0' &amp;&amp; W == '0') then UNDEFINED;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (W == '1');</line>
<line>if t == 15 || (wback &amp;&amp; n == t) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T4" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STR_i_A1_off, STR_i_T1, STR_i_T2, STR_i_T3, STR_i_T4_pre" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_i_A1_off, STR_i_T1, STR_i_T2, STR_i_T3, STR_i_T4_pre" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_i_A1_off" symboldefcount="1">
      <symbol link="sa_rt_1">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_i_T1, STR_i_T2, STR_i_T3, STR_i_T4_pre" symboldefcount="2">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1, T2, T3 and T4: is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_i_A1_off" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_i_T1, STR_i_T3, STR_i_T4_pre" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1, T3 and T4: is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_i_A1_off, STR_i_T4_pre" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="STR_i_T1, STR_i_T2, STR_i_T3" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the offset is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_i_A1_off" symboldefcount="1">
      <symbol link="sa_imm_4">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 if omitted, and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_i_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the optional positive unsigned immediate byte offset, a multiple of 4, in the range 0 to 124, defaulting to 0 and encoded in the "imm5" field as &lt;imm&gt;/4.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_i_T2" symboldefcount="3">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the optional positive unsigned immediate byte offset, a multiple of 4, in the range 0 to 1020, defaulting to 0 and encoded in the "imm8" field as &lt;imm&gt;/4.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_i_T3" symboldefcount="4">
      <symbol link="sa_imm_2">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_i_T4_pre" symboldefcount="5">
      <symbol link="sa_imm_3">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T4: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STR_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then</line>
<line>    if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>        EncodingSpecificOperations();</line>
<line>        offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);</line>
<line>        address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>        <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,4] = if t == 15 then <a link="impl-aarch32.PCStoreValue.0" file="shared_pseudocode.xml" hover="function: bits(32) PCStoreValue()">PCStoreValue</a>() else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];</line>
<line>        if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
<line>else</line>
<line>    if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>        EncodingSpecificOperations();</line>
<line>        offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);</line>
<line>        address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>        <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,4] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];</line>
<line>        if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="str_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STR_r" title="STR (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STR" />
  </docvars>
  <heading>STR (register)</heading>
  <desc>
    <brief>
      <para>Store Register (register)</para>
    </brief>
    <authored>
      <para>Store Register (register) calculates an address from a base register value and an offset register value, stores a word from a register to memory. The offset register value can optionally be shifted. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STR" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STR_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STR_r_A1_off" oneofinclass="3" oneof="5" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, </text><a link="sa_shift" hover="The shift to apply to the value read from {syntax{&lt;Rm&gt;}}">&lt;shift&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="STR_r_A1_post" oneofinclass="3" oneof="5" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, </text><a link="sa_shift" hover="The shift to apply to the value read from {syntax{&lt;Rm&gt;}}">&lt;shift&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="STR_r_A1_pre" oneofinclass="3" oneof="5" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, </text><a link="sa_shift" hover="The shift to apply to the value read from {syntax{&lt;Rm&gt;}}">&lt;shift&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STR_r/A1_A.txt" mylink="aarch32.instrs.STR_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; W == '1' then SEE "STRT";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
<line>if m == 15 then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; (n == 15 || n == t) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_WBSUPPRESS" />
          <cu_type>
            <cu_type_text>The instruction uses the addressing mode described in the equivalent immediate offset instruction.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/STR_r/T1_A.txt">
        <box hibit="31" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="27" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="26" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="25" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="21" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rt" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="STR_r_T1" oneofinclass="1" oneof="5" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STR_r/T1_A.txt" mylink="aarch32.instrs.STR_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="register-offset" />
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STR_r/T2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="6" settings="6">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STR_r_T2" oneofinclass="1" oneof="5" label="T2">
        <docvars>
          <docvar key="address-form" value="register-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <asmtemplate comment="&lt;Rt&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, LSL #</text><a link="sa_imm" hover="If present, the size of left shift to apply to the value from {syntax{&lt;Rm&gt;}}, in the range 1-3">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STR_r/T2_A.txt" mylink="aarch32.instrs.STR_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then UNDEFINED;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm2));</line>
<line>if t == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STR_r_A1_off, STR_r_T1, STR_r_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_r_A1_off, STR_r_T1, STR_r_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_r_A1_off" symboldefcount="1">
      <symbol link="sa_rt_1">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_r_T1, STR_r_T2" symboldefcount="2">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_r_A1_off" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_r_T1, STR_r_T2" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_r_A1_off" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="STR_r_T1, STR_r_T2" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the index register is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_r_A1_off, STR_r_T1, STR_r_T2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_r_A1_off" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The shift to apply to the value read from <syntax>&lt;Rm&gt;</syntax>. If absent, no shift is applied. Otherwise, see <xref linkend="Chdibjii">Shifts applied to a register</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_r_T2" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>If present, the size of the left shift to apply to the value from <syntax>&lt;Rm&gt;</syntax>, in the range 1-3. <syntax>&lt;imm&gt;</syntax> is encoded in imm2. If absent, no shift is specified and imm2 is encoded as <binarynumber>0b00</binarynumber>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STR_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    offset = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + offset) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - offset);</line>
<line>    address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    bits(32) data;</line>
<line>    if t == 15 then  // Only possible for encoding A1</line>
<line>        data = <a link="impl-aarch32.PCStoreValue.0" file="shared_pseudocode.xml" hover="function: bits(32) PCStoreValue()">PCStoreValue</a>();</line>
<line>    else</line>
<line>        data = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];</line>
<line>    <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,4] = data;</line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="strb_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STRB_i" title="STRB (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STRB" />
  </docvars>
  <heading>STRB (immediate)</heading>
  <desc>
    <brief>
      <para>Store Register Byte (immediate)</para>
    </brief>
    <authored>
      <para>Store Register Byte (immediate) calculates an address from a base register value and an immediate offset, and stores a byte from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STRB" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STRB_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="STRB_i_A1_off" oneofinclass="3" oneof="8" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRB" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_3" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="STRB_i_A1_post" oneofinclass="3" oneof="8" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRB" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_3" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="STRB_i_A1_pre" oneofinclass="3" oneof="8" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRB" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_3" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRB_i/A1_A.txt" mylink="aarch32.instrs.STRB_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; W == '1' then SEE "STRBT";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>if t == 15 then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; (n == 15 || n == t) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_WBSUPPRESS" />
          <cu_type>
            <cu_type_text>The instruction uses the addressing mode described in the equivalent immediate offset instruction.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STRB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/STRB_i/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="B" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="26" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="21" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rt" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="STRB_i_T1" oneofinclass="1" oneof="8" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STRB" />
        </docvars>
        <asmtemplate><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional 5-bit unsigned immediate byte offset [0-31], default 0 (field &quot;imm5&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRB_i/T1_A.txt" mylink="aarch32.instrs.STRB_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm5, 32);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STRB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STRB_i/T2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="STRB_i_T2" oneofinclass="1" oneof="8" label="T2">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STRB" />
        </docvars>
        <asmtemplate comment="&lt;Rt&gt;, &lt;Rn&gt;, &lt;imm&gt; can be represented in T1"><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm_1" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
        <asmtemplate><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm_1" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRB_i/T2_A.txt" mylink="aarch32.instrs.STRB_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then UNDEFINED;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
<line>if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T3" oneof="4" id="iclass_t3" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STRB" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STRB_i/T3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="9" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="8" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="STRB_i_T3_offn" oneofinclass="3" oneof="8" label="Offset" bitdiffs="P == 1 &amp;&amp; U == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STRB" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="9" width="1" name="U">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #-</text><a link="sa_imm_2" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="STRB_i_T3_post" oneofinclass="3" oneof="8" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STRB" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_2" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="STRB_i_T3_pre" oneofinclass="3" oneof="8" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STRB" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_2" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRB_i/T3_A.txt" mylink="aarch32.instrs.STRB_i.T3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '1' &amp;&amp; U == '1' &amp;&amp; W == '0' then SEE "STRBT";</line>
<line>if Rn == '1111' || (P == '0' &amp;&amp; W == '0') then UNDEFINED;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (W == '1');</line>
<line>if t == 15 || (wback &amp;&amp; n == t) then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STRB_i_A1_off, STRB_i_T1, STRB_i_T2, STRB_i_T3_pre" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRB_i_A1_off, STRB_i_T1, STRB_i_T2, STRB_i_T3_pre" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRB_i_A1_off, STRB_i_T1, STRB_i_T2, STRB_i_T3_pre" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRB_i_A1_off" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRB_i_T1, STRB_i_T2, STRB_i_T3_pre" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1, T2 and T3: is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRB_i_A1_off, STRB_i_T3_pre" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="STRB_i_T1, STRB_i_T2" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the offset is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRB_i_A1_off" symboldefcount="1">
      <symbol link="sa_imm_3">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 if omitted, and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRB_i_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is an optional 5-bit unsigned immediate byte offset, in the range 0 to 31, defaulting to 0 and encoded in the "imm5" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRB_i_T2" symboldefcount="3">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRB_i_T3_pre" symboldefcount="4">
      <symbol link="sa_imm_2">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STRB_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then</line>
<line>    if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>        EncodingSpecificOperations();</line>
<line>        offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);</line>
<line>        address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>        <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,1] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]&lt;7:0&gt;;</line>
<line>        if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
<line>else</line>
<line>    if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>        EncodingSpecificOperations();</line>
<line>        offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);</line>
<line>        address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>        <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,1] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]&lt;7:0&gt;;</line>
<line>        if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="strb_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STRB_r" title="STRB (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STRB" />
  </docvars>
  <heading>STRB (register)</heading>
  <desc>
    <brief>
      <para>Store Register Byte (register)</para>
    </brief>
    <authored>
      <para>Store Register Byte (register) calculates an address from a base register value and an offset register value, and stores a byte from a register to memory. The offset register value can optionally be shifted. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STRB" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STRB_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STRB_r_A1_off" oneofinclass="3" oneof="5" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRB" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, </text><a link="sa_shift" hover="The shift to apply to the value read from {syntax{&lt;Rm&gt;}}">&lt;shift&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="STRB_r_A1_post" oneofinclass="3" oneof="5" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRB" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, </text><a link="sa_shift" hover="The shift to apply to the value read from {syntax{&lt;Rm&gt;}}">&lt;shift&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="STRB_r_A1_pre" oneofinclass="3" oneof="5" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRB" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, </text><a link="sa_shift" hover="The shift to apply to the value read from {syntax{&lt;Rm&gt;}}">&lt;shift&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRB_r/A1_A.txt" mylink="aarch32.instrs.STRB_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; W == '1' then SEE "STRBT";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
<line>if t == 15 || m == 15 then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; (n == 15 || n == t) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_WBSUPPRESS" />
          <cu_type>
            <cu_type_text>The instruction uses the addressing mode described in the equivalent immediate offset instruction.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STRB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/STRB_r/T1_A.txt">
        <box hibit="31" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="27" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="26" name="B" settings="1">
          <c>1</c>
        </box>
        <box hibit="25" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="21" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rt" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="STRB_r_T1" oneofinclass="1" oneof="5" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STRB" />
        </docvars>
        <asmtemplate><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRB_r/T1_A.txt" mylink="aarch32.instrs.STRB_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="register-offset" />
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STRB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STRB_r/T2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="6" settings="6">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STRB_r_T2" oneofinclass="1" oneof="5" label="T2">
        <docvars>
          <docvar key="address-form" value="register-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STRB" />
        </docvars>
        <asmtemplate comment="&lt;Rt&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
        <asmtemplate><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, LSL #</text><a link="sa_imm" hover="If present, the size of left shift to apply to the value from {syntax{&lt;Rm&gt;}}, in the range 1-3">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRB_r/T2_A.txt" mylink="aarch32.instrs.STRB_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then UNDEFINED;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm2));</line>
<line>if t == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STRB_r_A1_off, STRB_r_T1, STRB_r_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRB_r_A1_off, STRB_r_T1, STRB_r_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRB_r_A1_off, STRB_r_T1, STRB_r_T2" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRB_r_A1_off" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRB_r_T1, STRB_r_T2" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRB_r_A1_off" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="STRB_r_T1, STRB_r_T2" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the index register is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRB_r_A1_off, STRB_r_T1, STRB_r_T2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRB_r_A1_off" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The shift to apply to the value read from <syntax>&lt;Rm&gt;</syntax>. If absent, no shift is applied. Otherwise, see <xref linkend="Chdibjii">Shifts applied to a register</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRB_r_T2" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>If present, the size of the left shift to apply to the value from <syntax>&lt;Rm&gt;</syntax>, in the range 1-3. <syntax>&lt;imm&gt;</syntax> is encoded in imm2. If absent, no shift is specified and imm2 is encoded as <binarynumber>0b00</binarynumber>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STRB_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    offset = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + offset) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - offset);</line>
<line>    address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,1] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]&lt;7:0&gt;;</line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="strbt.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STRBT" title="STRBT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STRBT" />
  </docvars>
  <heading>STRBT</heading>
  <desc>
    <brief>
      <para>Store Register Byte Unprivileged</para>
    </brief>
    <authored>
      <para>Store Register Byte Unprivileged stores a byte from a register to memory. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
      <para>The memory access is restricted as if the PE were running in User mode. This makes no difference if the PE is actually running in User mode.</para>
      <para><instruction>STRBT</instruction> is <arm-defined-word>unpredictable</arm-defined-word> in Hyp mode.</para>
      <para>The T32 instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged.</para>
      <para>The A32 instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STRBT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STRBT/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="STRBT_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRBT" />
        </docvars>
        <asmtemplate><text>STRBT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>] </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRBT/A1_A.txt" mylink="aarch32.instrs.STRBT.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  postindex = TRUE;  add = (U == '1');</line>
<line>register_form = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);</line>
<line>if t == 15 || n == 15 || n == t then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction uses post-indexed addressing with the base register as PC. This is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction is treated as if bit[24] == 1 and bit[21] == 0. The instruction uses immediate offset addressing with the base register as PC, without writeback.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A2" oneof="3" id="iclass_a2" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="address-form" value="post-indexed" />
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STRBT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STRBT/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STRBT_A2" oneofinclass="1" oneof="3" label="A2">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRBT" />
        </docvars>
        <asmtemplate><text>STRBT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa__plusminus__1" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, </text><a link="sa_shift" hover="The shift to apply to the value read from {syntax{&lt;Rm&gt;}}">&lt;shift&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRBT/A2_A.txt" mylink="aarch32.instrs.STRBT.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  postindex = TRUE;  add = (U == '1');</line>
<line>register_form = TRUE;  (shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
<line>if t == 15 || n == 15 || n == t || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction uses post-indexed addressing with the base register as PC. This is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction is treated as if bit[24] == 1 and bit[21] == 0. The instruction uses immediate offset addressing with the base register as PC, without writeback.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STRBT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STRBT/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="STRBT_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STRBT" />
        </docvars>
        <asmtemplate><text>STRBT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional 8-bit unsigned immediate byte offset [0-255], default 0 (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRBT/T1_A.txt" mylink="aarch32.instrs.STRBT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then UNDEFINED;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  postindex = FALSE;  add = TRUE;</line>
<line>register_form = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);</line>
<line>if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STRBT_A1, STRBT_A2, STRBT_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRBT_A1, STRBT_A2, STRBT_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRBT_A1" symboldefcount="1">
      <symbol link="sa_rt_1">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRBT_A2, STRBT_T1" symboldefcount="2">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>For encoding A2 and T1: is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRBT_A1, STRBT_A2, STRBT_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRBT_A1" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>For encoding A1: specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="STRBT_A2" symboldefcount="2">
      <symbol link="sa__plusminus__1">+/-</symbol>
      <definition encodedin="U">
        <intro>For encoding A2: specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="STRBT_A2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRBT_A2" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The shift to apply to the value read from <syntax>&lt;Rm&gt;</syntax>. If absent, no shift is applied. Otherwise, see <xref linkend="Chdibjii">Shifts applied to a register</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRBT_T1" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the offset is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRBT_A1" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 if omitted, and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRBT_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is an optional 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 and encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STRBT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then UNPREDICTABLE;               // Hyp mode</line>
<line>    offset = if register_form then <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C) else imm32;</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + offset) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - offset);</line>
<line>    address = if postindex then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] else offset_addr;</line>
<line>    <a link="impl-aarch32.MemU_unpriv.write.2" file="shared_pseudocode.xml" hover="accessor: MemU_unpriv[bits(32) address, integer size] = bits(8*size) value">MemU_unpriv</a>[address,1] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]&lt;7:0&gt;;</line>
<line>    if postindex then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
</pstext>
    </ps>
  </ps_section>
  <constrained_unpredictables ps_block="Operation">
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>PSTATE.EL == EL2</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
      <cu_type>
        <cu_type_text>The instruction executes as <instruction>STRB</instruction> (immediate).</cu_type_text>
      </cu_type>
    </cu_case>
  </constrained_unpredictables>
</instructionsection>
</file>
<file type="instructionsection" file="strd_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STRD_i" title="STRD (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STRD" />
  </docvars>
  <heading>STRD (immediate)</heading>
  <desc>
    <brief>
      <para>Store Register Dual (immediate)</para>
    </brief>
    <authored>
      <para>Store Register Dual (immediate) calculates an address from a base register value and an immediate offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
      <para>Related encodings: <xref linkend="T32.encoding_index.dstd">Load/store dual, load/store exclusive, table branch</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STRD" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STRD_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="imm4H" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4L" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STRD_i_A1_off" oneofinclass="3" oneof="6" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRD" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2_1" hover="Second general-purpose register to be transferred">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="STRD_i_A1_post" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRD" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2_1" hover="Second general-purpose register to be transferred">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="STRD_i_A1_pre" oneofinclass="3" oneof="6" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRD" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2_1" hover="Second general-purpose register to be transferred">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRD_i/A1_A.txt" mylink="aarch32.instrs.STRD_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rt&lt;0&gt; == '1' then UNPREDICTABLE;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = t+1;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm4H:imm4L, 32);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>if P == '0' &amp;&amp; W == '1' then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; (n == 15 || n == t || n == t2) then UNPREDICTABLE;</line>
<line>if t2 == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15 || t2 == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; (n == t || n == t2)</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_WBSUPPRESS" />
          <cu_type>
            <cu_type_text>The instruction uses the addressing mode described in the equivalent immediate offset instruction.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>Rt&lt;0&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="t&lt;0&gt; = '0'" />
          </cu_type>
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="t2 = t" />
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as described, with no change to its behavior and no additional side-effects. This does not apply when Rt == '1111'.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>P == '0' &amp;&amp; W == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction executes as an <instruction>LDRD</instruction> using one of offset, post-indexed, or pre-indexed addressing.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STRD" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STRD_i/T1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="STRD_i_T1_off" oneofinclass="3" oneof="6" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STRD" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="Unsigned immediate byte offset, multiple of 4 [0-1020], default 0 if omitted (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="STRD_i_T1_post" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STRD" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="Unsigned immediate byte offset, multiple of 4 [0-1020], default 0 if omitted (field &quot;imm8&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="STRD_i_T1_pre" oneofinclass="3" oneof="6" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STRD" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="Unsigned immediate byte offset, multiple of 4 [0-1020], default 0 if omitted (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRD_i/T1_A.txt" mylink="aarch32.instrs.STRD_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; W == '0' then SEE "Related encodings";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (W == '1');</line>
<line>if wback &amp;&amp; (n == t || n == t2) then UNPREDICTABLE;</line>
<line>if n == 15 || t == 15 || t2 == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15 || t2 == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; (n == t || n == t2)</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_WBSUPPRESS" />
          <cu_type>
            <cu_type_text>The instruction uses the addressing mode described in the equivalent immediate offset instruction.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STRD_i_A1_off, STRD_i_T1_off" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRD_i_A1_off, STRD_i_T1_off" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRD_i_A1_off" symboldefcount="1">
      <symbol link="sa_rt_1">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the first general-purpose register to be transferred, encoded in the "Rt" field. This register must be even-numbered and not R14.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRD_i_T1_off" symboldefcount="2">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the first general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRD_i_A1_off" symboldefcount="1">
      <symbol link="sa_rt2_1">&lt;Rt2&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the second general-purpose register to be transferred. This register must be <syntax>&lt;R(t+1)&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRD_i_T1_off" symboldefcount="2">
      <symbol link="sa_rt2">&lt;Rt2&gt;</symbol>
      <account encodedin="Rt2">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the second general-purpose register to be transferred, encoded in the "Rt2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRD_i_A1_off" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRD_i_T1_off" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRD_i_A1_off, STRD_i_T1_off" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="STRD_i_A1_off" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm4H:imm4L">
        <docvars>
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRD_i_T1_off" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the unsigned immediate byte offset, a multiple of 4, in the range 0 to 1020, defaulting to 0 if omitted, and encoded in the "imm8" field as &lt;imm&gt;/4.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STRD_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);</line>
<line>    address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    if <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, 8) then</line>
<line>        bits(64) data;</line>
<line>        if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>) then</line>
<line>            data&lt;63:32&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];</line>
<line>            data&lt;31:0&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t2];</line>
<line>        else</line>
<line>            data&lt;31:0&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];</line>
<line>            data&lt;63:32&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t2];</line>
<line>        <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,8] = data;</line>
<line>    else</line>
<line>        <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,4] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];</line>
<line>        <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address+4,4] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t2];</line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="strd_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STRD_r" title="STRD (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
    <docvar key="mnemonic" value="STRD" />
  </docvars>
  <heading>STRD (register)</heading>
  <desc>
    <brief>
      <para>Store Register Dual (register)</para>
    </brief>
    <authored>
      <para>Store Register Dual (register) calculates an address from a base register value and a register offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STRD" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STRD_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STRD_r_A1_off" oneofinclass="3" oneof="3" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRD" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="STRD_r_A1_post" oneofinclass="3" oneof="3" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRD" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="STRD_r_A1_pre" oneofinclass="3" oneof="3" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRD" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRD_r/A1_A.txt" mylink="aarch32.instrs.STRD_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rt&lt;0&gt; == '1' then UNPREDICTABLE;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = t+1;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>if P == '0' &amp;&amp; W == '1' then UNPREDICTABLE;</line>
<line>if t2 == 15 || m == 15 then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; (n == 15 || n == t || n == t2) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15 || t2 == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; (n == t || n == t2)</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_WBSUPPRESS" />
          <cu_type>
            <cu_type_text>The instruction uses the addressing mode described in the equivalent immediate offset instruction.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>Rt&lt;0&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="t&lt;0&gt; = '0'" />
          </cu_type>
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="t2 = t" />
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as described, with no change to its behavior and no additional side-effects. This does not apply when Rt == '1111'.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>P == '0' &amp;&amp; W == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="P = '1'; W = '0'" />
          </cu_type>
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="P = '1'; W = '1'" />
          </cu_type>
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="P = '0'; W = '0'" />
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STRD_r_A1_off" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRD_r_A1_off" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRD_r_A1_off" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the first general-purpose register to be transferred, encoded in the "Rt" field. This register must be even-numbered and not R14.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRD_r_A1_off" symboldefcount="1">
      <symbol link="sa_rt2">&lt;Rt2&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the second general-purpose register to be transferred. This register must be <syntax>&lt;R(t+1)&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRD_r_A1_off" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRD_r_A1_off" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="STRD_r_A1_off" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STRD_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]);</line>
<line>    address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    if <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, 8) then</line>
<line>        bits(64) data;</line>
<line>        if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>) then</line>
<line>            data&lt;63:32&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];</line>
<line>            data&lt;31:0&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t2];</line>
<line>        else</line>
<line>            data&lt;31:0&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];</line>
<line>            data&lt;63:32&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t2];</line>
<line>        <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,8] = data;</line>
<line>    else</line>
<line>        <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,4] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];</line>
<line>        <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address+4,4] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t2];</line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="strex.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STREX" title="STREX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STREX" />
  </docvars>
  <heading>STREX</heading>
  <desc>
    <brief>
      <para>Store Register Exclusive</para>
    </brief>
    <authored>
      <para>Store Register Exclusive calculates an address from a base register value and an immediate offset, stores a word from a register to the calculated address if the PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed.</para>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>Aborts and alignment</para>
      <para>If a synchronous Data Abort exception is generated by the execution of this instruction:</para>
      <list type="unordered">
        <listitem><content>Memory is not updated.</content></listitem>
        <listitem><content><syntax>&lt;Rd&gt;</syntax> is not updated.</content></listitem>
      </list>
      <para>A non word-aligned memory address causes an Alignment fault Data Abort exception to be generated, subject to the following rules:</para>
      <list type="unordered">
        <listitem><content>If <function>AArch32.ExclusiveMonitorsPass()</function> returns <enumvalue>TRUE</enumvalue>, the exception is generated.</content></listitem>
        <listitem><content>Otherwise, it is <arm-defined-word>implementation defined</arm-defined-word> whether the exception is generated.</content></listitem>
      </list>
      <para>If <function>AArch32.ExclusiveMonitorsPass()</function> returns <enumvalue>FALSE</enumvalue> and the memory address, if accessed, would generate a synchronous Data Abort exception, it is <arm-defined-word>implementation defined</arm-defined-word> whether the exception is generated.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STREX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STREX/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STREX_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STREX" />
        </docvars>
        <asmtemplate><text>STREX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="Destination general-purpose register into which the status result of store exclusive is written (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, </text><a>{#}</a><a link="sa_imm_1" hover="The immediate offset added to the value of {syntax{&lt;Rn&gt;}} to calculate the address">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STREX/A1_A.txt" mylink="aarch32.instrs.STREX.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32); // Zero offset</line>
<line>if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;</line>
<line>if d == n || d == t then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == n</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs the store to an <arm-defined-word>unknown</arm-defined-word> address.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STREX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STREX/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="STREX_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STREX" />
        </docvars>
        <asmtemplate><text>STREX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="Destination general-purpose register into which the status result of store exclusive is written (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa_imm" hover="The immediate offset added to the value of {syntax{&lt;Rn&gt;}} to calculate the address">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STREX/T1_A.txt" mylink="aarch32.instrs.STREX.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
<line>if d == 15 || t == 15 || n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
<line>if d == n || d == t then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == n</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs the store to an <arm-defined-word>unknown</arm-defined-word> address.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STREX_A1, STREX_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STREX_A1, STREX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STREX_A1, STREX_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the destination general-purpose register into which the status result of the store exclusive is written, encoded in the "Rd" field. The value returned is:</para>
          <list type="param">
            <listitem>
              <param>0</param><content>If the operation updates memory.</content>
            </listitem>
            <listitem>
              <param>1</param><content>If the operation fails to update memory.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STREX_A1, STREX_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STREX_A1, STREX_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STREX_A1" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: the immediate offset added to the value of <syntax>&lt;Rn&gt;</syntax> to calculate the address. <syntax>&lt;imm&gt;</syntax> can only be 0 or omitted.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STREX_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: the immediate offset added to the value of <syntax>&lt;Rn&gt;</syntax> to calculate the address. <syntax>&lt;imm&gt;</syntax> can be omitted, meaning an offset of 0. Values are multiples of 4 in the range 0-1020.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STREX/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32;</line>
<line>    if <a link="AArch32.ExclusiveMonitorsPass.2" file="shared_pseudocode.xml" hover="function: boolean AArch32.ExclusiveMonitorsPass(bits(32) address, integer size)">AArch32.ExclusiveMonitorsPass</a>(address,4) then</line>
<line>        <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,4] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('0', 32);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('1', 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="strexb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STREXB" title="STREXB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STREXB" />
  </docvars>
  <heading>STREXB</heading>
  <desc>
    <brief>
      <para>Store Register Exclusive Byte</para>
    </brief>
    <authored>
      <para>Store Register Exclusive Byte derives an address from a base register value, stores a byte from a register to the derived address if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed.</para>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>Aborts</para>
      <para>If a synchronous Data Abort exception is generated by the execution of this instruction:</para>
      <list type="unordered">
        <listitem><content>Memory is not updated.</content></listitem>
        <listitem><content><syntax>&lt;Rd&gt;</syntax> is not updated.</content></listitem>
      </list>
      <para>If <function>AArch32.ExclusiveMonitorsPass()</function> returns <enumvalue>FALSE</enumvalue> and the memory address, if accessed, would generate a synchronous Data Abort exception, it is <arm-defined-word>implementation defined</arm-defined-word> whether the exception is generated.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STREXB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STREXB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STREXB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STREXB" />
        </docvars>
        <asmtemplate><text>STREXB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="Destination general-purpose register into which the status result of store exclusive is written (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STREXB/A1_A.txt" mylink="aarch32.instrs.STREXB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;</line>
<line>if d == n || d == t then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == n</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs the store to an <arm-defined-word>unknown</arm-defined-word> address.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STREXB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STREXB/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="5" width="2" name="sz" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STREXB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STREXB" />
        </docvars>
        <asmtemplate><text>STREXB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="Destination general-purpose register into which the status result of store exclusive is written (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STREXB/T1_A.txt" mylink="aarch32.instrs.STREXB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if d == 15 || t == 15 || n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
<line>if d == n || d == t then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == n</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs the store to an <arm-defined-word>unknown</arm-defined-word> address.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STREXB_A1, STREXB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STREXB_A1, STREXB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STREXB_A1, STREXB_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the destination general-purpose register into which the status result of the store exclusive is written, encoded in the "Rd" field. The value returned is:</para>
          <list type="param">
            <listitem>
              <param>0</param><content>If the operation updates memory.</content>
            </listitem>
            <listitem>
              <param>1</param><content>If the operation fails to update memory.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STREXB_A1, STREXB_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STREXB_A1, STREXB_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STREXB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    if <a link="AArch32.ExclusiveMonitorsPass.2" file="shared_pseudocode.xml" hover="function: boolean AArch32.ExclusiveMonitorsPass(bits(32) address, integer size)">AArch32.ExclusiveMonitorsPass</a>(address,1) then</line>
<line>        <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,1] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]&lt;7:0&gt;;</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('0', 32);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('1', 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="strexd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STREXD" title="STREXD -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STREXD" />
  </docvars>
  <heading>STREXD</heading>
  <desc>
    <brief>
      <para>Store Register Exclusive Doubleword</para>
    </brief>
    <authored>
      <para>Store Register Exclusive Doubleword derives an address from a base register value, stores a 64-bit doubleword from two registers to the derived address if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed.</para>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>Aborts and alignment</para>
      <para>If a synchronous Data Abort exception is generated by the execution of this instruction:</para>
      <list type="unordered">
        <listitem><content>Memory is not updated.</content></listitem>
        <listitem><content><syntax>&lt;Rd&gt;</syntax> is not updated.</content></listitem>
      </list>
      <para>A non doubleword-aligned memory address causes an Alignment fault Data Abort exception to be generated, subject to the following rules:</para>
      <list type="unordered">
        <listitem><content>If <function>AArch32.ExclusiveMonitorsPass()</function> returns <enumvalue>TRUE</enumvalue>, the exception is generated.</content></listitem>
        <listitem><content>Otherwise, it is <arm-defined-word>implementation defined</arm-defined-word> whether the exception is generated.</content></listitem>
      </list>
      <para>If <function>AArch32.ExclusiveMonitorsPass()</function> returns <enumvalue>FALSE</enumvalue> and the memory address, if accessed, would generate a synchronous Data Abort exception, it is <arm-defined-word>implementation defined</arm-defined-word> whether the exception is generated.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STREXD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STREXD/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STREXD_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STREXD" />
        </docvars>
        <asmtemplate><text>STREXD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="Destination general-purpose register into which the status result of store exclusive is written (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rt_1" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2_1" hover="Second general-purpose register to be transferred">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STREXD/A1_A.txt" mylink="aarch32.instrs.STREXD.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = t+1;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if d == 15 || Rt&lt;0&gt; == '1' || t2 == 15 || n == 15 then UNPREDICTABLE;</line>
<line>if d == n || d == t || d == t2 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == n</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs the store to an <arm-defined-word>unknown</arm-defined-word> address.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>Rt&lt;0&gt; == '1'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="Rt&lt;0&gt; = '0'" />
          </cu_type>
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="t2 = t" />
          </cu_type>
          <cu_type constraint="Constraint_NONE" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>Rt == '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STREXD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STREXD/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="5" width="2" name="sz" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STREXD_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STREXD" />
        </docvars>
        <asmtemplate><text>STREXD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="Destination general-purpose register into which the status result of store exclusive is written (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rt" hover="First general-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STREXD/T1_A.txt" mylink="aarch32.instrs.STREXD.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if d == 15 || t == 15 || t2 == 15 || n == 15 then UNPREDICTABLE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
<line>if d == n || d == t || d == t2 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == n</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs the store to an <arm-defined-word>unknown</arm-defined-word> address.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STREXD_A1, STREXD_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STREXD_A1, STREXD_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STREXD_A1, STREXD_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the destination general-purpose register into which the status result of the store exclusive is written, encoded in the "Rd" field. The value returned is:</para>
          <list type="param">
            <listitem>
              <param>0</param><content>If the operation updates memory.</content>
            </listitem>
            <listitem>
              <param>1</param><content>If the operation fails to update memory.</content>
            </listitem>
          </list>
          <para><syntax>&lt;Rd&gt;</syntax> must not be the same as <syntax>&lt;Rn&gt;</syntax>, <syntax>&lt;Rt&gt;</syntax>, or <syntax>&lt;Rt2&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STREXD_A1" symboldefcount="1">
      <symbol link="sa_rt_1">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the first general-purpose register to be transferred, encoded in the "Rt" field. <syntax>&lt;Rt&gt;</syntax> must be even-numbered and not R14.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STREXD_T1" symboldefcount="2">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the first general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STREXD_A1" symboldefcount="1">
      <symbol link="sa_rt2_1">&lt;Rt2&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the second general-purpose register to be transferred. <syntax>&lt;Rt2&gt;</syntax> must be <syntax>&lt;R(t+1)&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STREXD_T1" symboldefcount="2">
      <symbol link="sa_rt2">&lt;Rt2&gt;</symbol>
      <account encodedin="Rt2">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the second general-purpose register to be transferred, encoded in the "Rt2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STREXD_A1, STREXD_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STREXD/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line></line>
<line>    // Create doubleword to store such that R[t] will be stored at address and R[t2] at address+4.</line>
<line>    value = if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>) then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]:<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t2] else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t2]:<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];</line>
<line></line>
<line>    if <a link="AArch32.ExclusiveMonitorsPass.2" file="shared_pseudocode.xml" hover="function: boolean AArch32.ExclusiveMonitorsPass(bits(32) address, integer size)">AArch32.ExclusiveMonitorsPass</a>(address,8) then</line>
<line>        <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,8] = value;</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('0', 32);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('1', 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="strexh.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STREXH" title="STREXH -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STREXH" />
  </docvars>
  <heading>STREXH</heading>
  <desc>
    <brief>
      <para>Store Register Exclusive Halfword</para>
    </brief>
    <authored>
      <para>Store Register Exclusive Halfword derives an address from a base register value, stores a halfword from a register to the derived address if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed.</para>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>Aborts and alignment</para>
      <para>If a synchronous Data Abort exception is generated by the execution of this instruction:</para>
      <list type="unordered">
        <listitem><content>Memory is not updated.</content></listitem>
        <listitem><content><syntax>&lt;Rd&gt;</syntax> is not updated.</content></listitem>
      </list>
      <para>A non halfword-aligned memory address causes an Alignment fault Data Abort exception to be generated, subject to the following rules:</para>
      <list type="unordered">
        <listitem><content>If <function>AArch32.ExclusiveMonitorsPass()</function> returns <enumvalue>TRUE</enumvalue>, the exception is generated.</content></listitem>
        <listitem><content>Otherwise, it is <arm-defined-word>implementation defined</arm-defined-word> whether the exception is generated.</content></listitem>
      </list>
      <para>If <function>AArch32.ExclusiveMonitorsPass()</function> returns <enumvalue>FALSE</enumvalue> and the memory address, if accessed, would generate a synchronous Data Abort exception, it is <arm-defined-word>implementation defined</arm-defined-word> whether the exception is generated.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STREXH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STREXH/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STREXH_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STREXH" />
        </docvars>
        <asmtemplate><text>STREXH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="Destination general-purpose register into which the status result of store exclusive is written (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STREXH/A1_A.txt" mylink="aarch32.instrs.STREXH.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;</line>
<line>if d == n || d == t then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == n</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs the store to an <arm-defined-word>unknown</arm-defined-word> address.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STREXH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STREXH/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="5" width="2" name="sz" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STREXH_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STREXH" />
        </docvars>
        <asmtemplate><text>STREXH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="Destination general-purpose register into which the status result of store exclusive is written (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STREXH/T1_A.txt" mylink="aarch32.instrs.STREXH.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if d == 15 || t == 15 || n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
<line>if d == n || d == t then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d == n</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs the store to an <arm-defined-word>unknown</arm-defined-word> address.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STREXH_A1, STREXH_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STREXH_A1, STREXH_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STREXH_A1, STREXH_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the destination general-purpose register into which the status result of the store exclusive is written, encoded in the "Rd" field. The value returned is:</para>
          <list type="param">
            <listitem>
              <param>0</param><content>If the operation updates memory.</content>
            </listitem>
            <listitem>
              <param>1</param><content>If the operation fails to update memory.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STREXH_A1, STREXH_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STREXH_A1, STREXH_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STREXH/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    if <a link="AArch32.ExclusiveMonitorsPass.2" file="shared_pseudocode.xml" hover="function: boolean AArch32.ExclusiveMonitorsPass(bits(32) address, integer size)">AArch32.ExclusiveMonitorsPass</a>(address,2) then</line>
<line>        <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,2] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]&lt;15:0&gt;;</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('0', 32);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('1', 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="strh_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STRH_i" title="STRH (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STRH" />
  </docvars>
  <heading>STRH (immediate)</heading>
  <desc>
    <brief>
      <para>Store Register Halfword (immediate)</para>
    </brief>
    <authored>
      <para>Store Register Halfword (immediate) calculates an address from a base register value and an immediate offset, and stores a halfword from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STRH" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STRH_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="imm4H" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4L" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STRH_i_A1_off" oneofinclass="3" oneof="8" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRH" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_3" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="STRH_i_A1_post" oneofinclass="3" oneof="8" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRH" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_3" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="STRH_i_A1_pre" oneofinclass="3" oneof="8" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRH" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_3" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRH_i/A1_A.txt" mylink="aarch32.instrs.STRH_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; W == '1' then SEE "STRHT";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm4H:imm4L, 32);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>if t == 15 then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; (n == 15 || n == t) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_WBSUPPRESS" />
          <cu_type>
            <cu_type_text>The instruction uses the addressing mode described in the equivalent immediate offset instruction.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STRH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/STRH_i/T1_A.txt">
        <box hibit="31" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="27" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="26" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="21" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rt" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="STRH_i_T1" oneofinclass="1" oneof="8" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STRH" />
        </docvars>
        <asmtemplate><text>STRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional positive unsigned immediate byte offset (field &quot;imm5&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRH_i/T1_A.txt" mylink="aarch32.instrs.STRH_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm5:'0', 32);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STRH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STRH_i/T2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="STRH_i_T2" oneofinclass="1" oneof="8" label="T2">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STRH" />
        </docvars>
        <asmtemplate comment="&lt;Rt&gt;, &lt;Rn&gt;, &lt;imm&gt; can be represented in T1"><text>STRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm_1" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
        <asmtemplate><text>STRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm_1" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRH_i/T2_A.txt" mylink="aarch32.instrs.STRH_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then UNDEFINED;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
<line>if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T3" oneof="4" id="iclass_t3" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STRH" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STRH_i/T3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="9" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="8" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="STRH_i_T3_offn" oneofinclass="3" oneof="8" label="Offset" bitdiffs="P == 1 &amp;&amp; U == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STRH" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="9" width="1" name="U">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #-</text><a link="sa_imm_2" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="STRH_i_T3_post" oneofinclass="3" oneof="8" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STRH" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_2" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="STRH_i_T3_pre" oneofinclass="3" oneof="8" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STRH" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_2" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRH_i/T3_A.txt" mylink="aarch32.instrs.STRH_i.T3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '1' &amp;&amp; U == '1' &amp;&amp; W == '0' then SEE "STRHT";</line>
<line>if Rn == '1111' || (P == '0' &amp;&amp; W == '0') then UNDEFINED;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (W == '1');</line>
<line>if t == 15 || (wback &amp;&amp; n == t) then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STRH_i_A1_off, STRH_i_T1, STRH_i_T2, STRH_i_T3_pre" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRH_i_A1_off, STRH_i_T1, STRH_i_T2, STRH_i_T3_pre" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRH_i_A1_off, STRH_i_T1, STRH_i_T2, STRH_i_T3_pre" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRH_i_A1_off" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRH_i_A1_pre, STRH_i_A1_post, STRH_i_T1, STRH_i_T2, STRH_i_T3_pre" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>For encoding A1, T1, T2, T3: is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRH_i_A1_off, STRH_i_T3_pre" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="STRH_i_T1, STRH_i_T2" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the offset is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRH_i_A1_off" symboldefcount="1">
      <symbol link="sa_imm_3">&lt;imm&gt;</symbol>
      <account encodedin="imm4H:imm4L">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRH_i_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the optional positive unsigned immediate byte offset, a multiple of 2, in the range 0 to 62, defaulting to 0 and encoded in the "imm5" field as &lt;imm&gt;/2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRH_i_T2" symboldefcount="3">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRH_i_T3_pre" symboldefcount="4">
      <symbol link="sa_imm_2">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STRH_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then</line>
<line>    if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>        EncodingSpecificOperations();</line>
<line>        offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);</line>
<line>        address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>        <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,2] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]&lt;15:0&gt;;</line>
<line>        if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
<line>else</line>
<line>    if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>        EncodingSpecificOperations();</line>
<line>        offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);</line>
<line>        address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>        <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,2] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]&lt;15:0&gt;;</line>
<line>        if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="strh_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STRH_r" title="STRH (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STRH" />
  </docvars>
  <heading>STRH (register)</heading>
  <desc>
    <brief>
      <para>Store Register Halfword (register)</para>
    </brief>
    <authored>
      <para>Store Register Halfword (register) calculates an address from a base register value and an offset register value, and stores a halfword from a register to memory. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STRH" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STRH_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STRH_r_A1_off" oneofinclass="3" oneof="5" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRH" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="STRH_r_A1_post" oneofinclass="3" oneof="5" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRH" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="STRH_r_A1_pre" oneofinclass="3" oneof="5" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRH" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRH_r/A1_A.txt" mylink="aarch32.instrs.STRH_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; W == '1' then SEE "STRHT";</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = (P == '1');  add = (U == '1');  wback = (P == '0') || (W == '1');</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
<line>if t == 15 || m == 15 then UNPREDICTABLE;</line>
<line>if wback &amp;&amp; (n == 15 || n == t) then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>wback &amp;&amp; n == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_WBSUPPRESS" />
          <cu_type>
            <cu_type_text>The instruction uses the addressing mode described in the equivalent immediate offset instruction.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STRH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/STRH_r/T1_A.txt">
        <box hibit="31" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="27" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="26" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="25" name="H" settings="1">
          <c>1</c>
        </box>
        <box hibit="24" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="21" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rt" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="STRH_r_T1" oneofinclass="1" oneof="5" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STRH" />
        </docvars>
        <asmtemplate><text>STRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRH_r/T1_A.txt" mylink="aarch32.instrs.STRH_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="register-offset" />
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STRH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STRH_r/T2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="6" settings="6">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STRH_r_T2" oneofinclass="1" oneof="5" label="T2">
        <docvars>
          <docvar key="address-form" value="register-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STRH" />
        </docvars>
        <asmtemplate comment="&lt;Rt&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>STRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
        <asmtemplate><text>STRH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, LSL #</text><a link="sa_imm" hover="If present, the size of left shift to apply to the value from {syntax{&lt;Rm&gt;}}, in the range 1-3">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRH_r/T2_A.txt" mylink="aarch32.instrs.STRH_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then UNDEFINED;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>index = TRUE;  add = TRUE;  wback = FALSE;</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm2));</line>
<line>if t == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STRH_r_A1_off, STRH_r_T1, STRH_r_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRH_r_A1_off, STRH_r_T1, STRH_r_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRH_r_A1_off, STRH_r_T1, STRH_r_T2" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRH_r_A1_off" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRH_r_T1, STRH_r_T2" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRH_r_A1_off" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="STRH_r_T1, STRH_r_T2" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the index register is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRH_r_A1_off, STRH_r_T1, STRH_r_T2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRH_r_T2" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>If present, the size of the left shift to apply to the value from <syntax>&lt;Rm&gt;</syntax>, in the range 1-3. <syntax>&lt;imm&gt;</syntax> is encoded in imm2. If absent, no shift is specified and imm2 is encoded as <binarynumber>0b00</binarynumber>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STRH_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    offset = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + offset) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - offset);</line>
<line>    address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,2] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]&lt;15:0&gt;;</line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="strht.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STRHT" title="STRHT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STRHT" />
  </docvars>
  <heading>STRHT</heading>
  <desc>
    <brief>
      <para>Store Register Halfword Unprivileged</para>
    </brief>
    <authored>
      <para>Store Register Halfword Unprivileged stores a halfword from a register to memory. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
      <para>The memory access is restricted as if the PE were running in User mode. This makes no difference if the PE is actually running in User mode.</para>
      <para><instruction>STRHT</instruction> is <arm-defined-word>unpredictable</arm-defined-word> in Hyp mode.</para>
      <para>The T32 instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged.</para>
      <para>The A32 instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STRHT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STRHT/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="imm4H" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4L" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STRHT_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRHT" />
        </docvars>
        <asmtemplate><text>STRHT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>] </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRHT/A1_A.txt" mylink="aarch32.instrs.STRHT.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  postindex = TRUE;  add = (U == '1');</line>
<line>register_form = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm4H:imm4L, 32);</line>
<line>if t == 15 || n == 15 || n == t then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction uses post-indexed addressing with the base register as PC. This is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction is treated as if bit[24] == 1 and bit[21] == 0. The instruction uses immediate offset addressing with the base register as PC, without writeback.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A2" oneof="3" id="iclass_a2" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="address-form" value="post-indexed" />
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STRHT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STRHT/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STRHT_A2" oneofinclass="1" oneof="3" label="A2">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRHT" />
        </docvars>
        <asmtemplate><text>STRHT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa__plusminus__1" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRHT/A2_A.txt" mylink="aarch32.instrs.STRHT.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  postindex = TRUE;  add = (U == '1');</line>
<line>register_form = TRUE;</line>
<line>if t == 15 || n == 15 || n == t || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction uses post-indexed addressing with the base register as PC. This is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction is treated as if bit[24] == 1 and bit[21] == 0. The instruction uses immediate offset addressing with the base register as PC, without writeback.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STRHT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STRHT/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="STRHT_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STRHT" />
        </docvars>
        <asmtemplate><text>STRHT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional 8-bit unsigned immediate byte offset [0-255], default 0 (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRHT/T1_A.txt" mylink="aarch32.instrs.STRHT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then UNDEFINED;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  postindex = FALSE;  add = TRUE;</line>
<line>register_form = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);</line>
<line>if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STRHT_A1, STRHT_A2, STRHT_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRHT_A1, STRHT_A2, STRHT_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRHT_A1, STRHT_A2, STRHT_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRHT_A1, STRHT_A2, STRHT_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRHT_A1" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>For encoding A1: specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="STRHT_A2" symboldefcount="2">
      <symbol link="sa__plusminus__1">+/-</symbol>
      <definition encodedin="U">
        <intro>For encoding A2: specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="STRHT_A2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRHT_T1" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the offset is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRHT_A1" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm4H:imm4L">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRHT_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is an optional 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 and encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STRHT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then UNPREDICTABLE;               // Hyp mode</line>
<line>    offset = if register_form then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m] else imm32;</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + offset) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - offset);</line>
<line>    address = if postindex then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] else offset_addr;</line>
<line>    <a link="impl-aarch32.MemU_unpriv.write.2" file="shared_pseudocode.xml" hover="accessor: MemU_unpriv[bits(32) address, integer size] = bits(8*size) value">MemU_unpriv</a>[address,2] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]&lt;15:0&gt;;</line>
<line>    if postindex then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
</pstext>
    </ps>
  </ps_section>
  <constrained_unpredictables ps_block="Operation">
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>PSTATE.EL == EL2</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
      <cu_type>
        <cu_type_text>The instruction executes as <instruction>STRH</instruction> (immediate).</cu_type_text>
      </cu_type>
    </cu_case>
  </constrained_unpredictables>
</instructionsection>
</file>
<file type="instructionsection" file="strt.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STRT" title="STRT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STRT" />
  </docvars>
  <heading>STRT</heading>
  <desc>
    <brief>
      <para>Store Register Unprivileged</para>
    </brief>
    <authored>
      <para>Store Register Unprivileged stores a word from a register to memory. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
      <para>The memory access is restricted as if the PE were running in User mode. This makes no difference if the PE is actually running in User mode.</para>
      <para><instruction>STRT</instruction> is <arm-defined-word>unpredictable</arm-defined-word> in Hyp mode.</para>
      <para>The T32 instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged.</para>
      <para>The A32 instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STRT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STRT/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="STRT_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRT" />
        </docvars>
        <asmtemplate><text>STRT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>] </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_1" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRT/A1_A.txt" mylink="aarch32.instrs.STRT.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  postindex = TRUE;  add = (U == '1');</line>
<line>register_form = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);</line>
<line>if n == 15 || n == t then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction uses post-indexed addressing with the base register as PC. This is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction is treated as if bit[24] == 1 and bit[21] == 0. The instruction uses immediate offset addressing with the base register as PC, without writeback.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A2" oneof="3" id="iclass_a2" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="address-form" value="post-indexed" />
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STRT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STRT/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STRT_A2" oneofinclass="1" oneof="3" label="A2">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STRT" />
        </docvars>
        <asmtemplate><text>STRT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa__plusminus__1" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>{</text><text>, </text><a link="sa_shift" hover="The shift to apply to the value read from {syntax{&lt;Rm&gt;}}">&lt;shift&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRT/A2_A.txt" mylink="aarch32.instrs.STRT.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  postindex = TRUE;  add = (U == '1');</line>
<line>register_form = TRUE;  (shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
<line>if n == 15 || n == t || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == t</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction uses post-indexed addressing with the base register as PC. This is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction is treated as if bit[24] == 1 and bit[21] == 0. The instruction uses immediate offset addressing with the base register as PC, without writeback.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STRT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STRT/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="STRT_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STRT" />
        </docvars>
        <asmtemplate><text>STRT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional 8-bit unsigned immediate byte offset [0-255], default 0 (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STRT/T1_A.txt" mylink="aarch32.instrs.STRT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then UNDEFINED;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  postindex = FALSE;  add = TRUE;</line>
<line>register_form = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);</line>
<line>if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>t == 15</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STRT_A1, STRT_A2, STRT_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRT_A1, STRT_A2, STRT_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRT_A1, STRT_A2" symboldefcount="1">
      <symbol link="sa_rt_1">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1 and A2: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRT_T1" symboldefcount="2">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRT_A1, STRT_A2, STRT_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRT_A1" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>For encoding A1: specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="STRT_A2" symboldefcount="2">
      <symbol link="sa__plusminus__1">+/-</symbol>
      <definition encodedin="U">
        <intro>For encoding A2: specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="STRT_A2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRT_A2" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The shift to apply to the value read from <syntax>&lt;Rm&gt;</syntax>. If absent, no shift is applied. Otherwise, see <xref linkend="Chdibjii">Shifts applied to a register</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRT_T1" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the offset is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRT_A1" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 if omitted, and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STRT_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is an optional 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 and encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STRT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then UNPREDICTABLE;               // Hyp mode</line>
<line>    offset = if register_form then <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C) else imm32;</line>
<line>    offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + offset) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - offset);</line>
<line>    address = if postindex then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] else offset_addr;</line>
<line>    bits(32) data;</line>
<line>    if t == 15 then  // Only possible for encodings A1 and A2</line>
<line>        data = <a link="impl-aarch32.PCStoreValue.0" file="shared_pseudocode.xml" hover="function: bits(32) PCStoreValue()">PCStoreValue</a>();</line>
<line>    else</line>
<line>        data = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];</line>
<line>    <a link="impl-aarch32.MemU_unpriv.write.2" file="shared_pseudocode.xml" hover="accessor: MemU_unpriv[bits(32) address, integer size] = bits(8*size) value">MemU_unpriv</a>[address,4] = data;</line>
<line>    if postindex then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</line>
</pstext>
    </ps>
  </ps_section>
  <constrained_unpredictables ps_block="Operation">
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1"><line>PSTATE.EL == EL2</line>
</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
      <cu_type>
        <cu_type_text>The instruction executes as <instruction>STR</instruction> (immediate).</cu_type_text>
      </cu_type>
    </cu_case>
  </constrained_unpredictables>
</instructionsection>
</file>
<file type="instructionsection" file="sub_adr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SUB_ADR" title="SUB (immediate, from PC) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="SUB" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="ADR" />
  </docvars>
  <heading>SUB (immediate, from PC)</heading>
  <desc>
    <brief>Subtract from PC</brief>
    <longer> subtracts an immediate value from the Align(PC, 4) value to form a PC-relative address, and writes the result to the destination register.  Arm recommends that, where possible, software avoids using this alias</longer>
  </desc>
  <aliasto refiform="adr.xml" iformid="ADR">ADR</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A2" oneof="2" id="iclass_a2" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="ADR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="SUB_ADR_A2" oneofinclass="1" oneof="2" label="A2">
        <docvars>
          <docvar key="alias_mnemonic" value="SUB" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADR" />
        </docvars>
        <asmtemplate><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, PC, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="adr.xml#ADR_A2">ADR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_label_2" hover="The label of an instruction or literal data item whose address is to be loaded into {syntax{&lt;Rd&gt;}}">&lt;label&gt;</a></asmtemplate>
          <aliascond>imm12 == '000000000000'</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="2" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ADR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="SUB_ADR_T2" oneofinclass="1" oneof="2" label="T2">
        <docvars>
          <docvar key="alias_mnemonic" value="SUB" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADR" />
        </docvars>
        <asmtemplate><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, PC, #</text><a link="sa_imm12" hover="12-bit unsigned immediate [0-4095] (field &quot;i:imm3:imm8&quot;)">&lt;imm12&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="adr.xml#ADR_T2">ADR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_label_1" hover="The label of an instruction or literal data item whose address is to be loaded into {syntax{&lt;Rd&gt;}}">&lt;label&gt;</a></asmtemplate>
          <aliascond>i:imm3:imm8 == '000000000000'</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SUB_ADR_A2, SUB_ADR_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_ADR_A2, SUB_ADR_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_ADR_A2" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A2" />
        </docvars>
        <intro>
          <para>For encoding A2: is the general-purpose destination register, encoded in the "Rd" field. If the PC is used, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_ADR_T2" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T2" />
        </docvars>
        <intro>
          <para>For encoding T2: is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_ADR_A2" symboldefcount="1">
      <symbol link="sa_label_2">&lt;label&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A2: the label of an instruction or literal data item whose address is to be loaded into <syntax>&lt;Rd&gt;</syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the <instruction>ADR</instruction> instruction to this label.</para>
          <para>If the offset is zero or positive, encoding A1 is used, with <field>imm32</field> equal to the offset.</para>
          <para>If the offset is negative, encoding A2 is used, with <field>imm32</field> equal to the size of the offset. That is, the use of encoding A2 indicates that the required offset is minus the value of <field>imm32</field>.</para>
          <para>Permitted values of the size of the offset are any of the constants described in <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_ADR_T2" symboldefcount="2">
      <symbol link="sa_label_1">&lt;label&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: the label of an instruction or literal data item whose address is to be loaded into <syntax>&lt;Rd&gt;</syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the <instruction>ADR</instruction> instruction to this label.</para>
          <para>If the offset is zero or positive, encoding T3 is used, with <field>imm32</field> equal to the offset.</para>
          <para>If the offset is negative, encoding T2 is used, with <field>imm32</field> equal to the size of the offset. That is, the use of encoding T2 indicates that the required offset is minus the value of <field>imm32</field>.</para>
          <para>Permitted values of the size of the offset are 0-4095.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_ADR_T2" symboldefcount="1">
      <symbol link="sa_imm12">&lt;imm12&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <intro>
          <para>Is a 12-bit unsigned immediate, in the range 0 to 4095, encoded in the "i:imm3:imm8" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_ADR_A2" symboldefcount="1">
      <symbol link="sa_const">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <intro>
          <para>An immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="sub_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SUB_i" title="SUB, SUBS (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SUB, SUBS (immediate)</heading>
  <desc>
    <brief>
      <para>Subtract (immediate)</para>
    </brief>
    <authored>
      <para>Subtract (immediate) subtracts an immediate value from a register value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the SUBS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. If the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The SUB variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The SUBS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode, except for encoding T5 with <syntax>&lt;imm8&gt;</syntax> set to zero, which is the encoding for the <instruction>ERET</instruction> instruction, see <xref linkend="A32T32-base.instructions.ERET">ERET</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGCDCGA">SUBS PC. LR and related instructions (A32)</xref> and <xref linkend="CEGDJHBD">SUBS PC, LR and related instructions (T32)</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>In the T32 instruction set, <syntax>MOVS{&lt;c&gt;}{&lt;q&gt;} PC, LR</syntax> is a pseudo-instruction for <syntax>SUBS{&lt;c&gt;}{&lt;q&gt;} PC, LR, #0</syntax>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="6">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt>, </txt>
      <a href="#iclass_t3">T3</a>
      <txt>, </txt>
      <a href="#iclass_t4">T4</a>
      <txt> and </txt>
      <a href="#iclass_t5">T5</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="6" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SUB_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="SUB_i_A1" oneofinclass="2" oneof="8" label="SUB" bitdiffs="S == 0 &amp;&amp; Rn != 11x1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SUB" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_2" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SUBS_i_A1" oneofinclass="2" oneof="8" label="SUBS" bitdiffs="S == 1 &amp;&amp; Rn != 1101">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SUBS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn">
          <c>N</c>
          <c>N</c>
          <c>Z</c>
          <c>N</c>
        </box>
        <asmtemplate><text>SUBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_2" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SUB_i/A1_A.txt" mylink="aarch32.instrs.SUB_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' &amp;&amp; S == '0' then SEE "ADR";</line>
<line>if Rn == '1101' then SEE "SUB (SP minus immediate)";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = (S == '1');  imm32 = <a link="impl-aarch32.A32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) A32ExpandImm(bits(12) imm12)">A32ExpandImm</a>(imm12);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="6" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SUB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/SUB_i/T1_A.txt">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="25" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="24" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="21" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="SUB_i_T1" oneofinclass="1" oneof="8" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SUB" />
        </docvars>
        <asmtemplate comment="Inside IT block"><text>SUB</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_imm3" hover="3-bit unsigned immediate [0-7] (field &quot;imm3&quot;)">&lt;imm3&gt;</a></asmtemplate>
        <asmtemplate comment="Outside IT block"><text>SUBS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_imm3" hover="3-bit unsigned immediate [0-7] (field &quot;imm3&quot;)">&lt;imm3&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SUB_i/T1_A.txt" mylink="aarch32.instrs.SUB_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>();  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm3, 32);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="6" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SUB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/SUB_i/T2_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="28" width="2" name="op" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="26" width="3" name="Rdn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="23" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="SUB_i_T2" oneofinclass="1" oneof="8" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SUB" />
        </docvars>
        <asmtemplate comment="Inside IT block, and &lt;Rdn&gt;, &lt;imm8&gt; can be represented in T1"><text>SUB</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdn" hover="General-purpose source and destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>, #</text><a link="sa_imm8" hover="8-bit unsigned immediate [0-255] (field &quot;imm8&quot;)">&lt;imm8&gt;</a></asmtemplate>
        <asmtemplate comment="Inside IT block, and &lt;Rdn&gt;, &lt;imm8&gt; cannot be represented in T1"><text>SUB</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdn" hover="General-purpose source and destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdn" hover="General-purpose source and destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>, #</text><a link="sa_imm8" hover="8-bit unsigned immediate [0-255] (field &quot;imm8&quot;)">&lt;imm8&gt;</a></asmtemplate>
        <asmtemplate comment="Outside IT block, and &lt;Rdn&gt;, &lt;imm8&gt; can be represented in T1"><text>SUBS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdn" hover="General-purpose source and destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>, #</text><a link="sa_imm8" hover="8-bit unsigned immediate [0-255] (field &quot;imm8&quot;)">&lt;imm8&gt;</a></asmtemplate>
        <asmtemplate comment="Outside IT block, and &lt;Rdn&gt;, &lt;imm8&gt; cannot be represented in T1"><text>SUBS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdn" hover="General-purpose source and destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rdn" hover="General-purpose source and destination register (field &quot;Rdn&quot;)">&lt;Rdn&gt;</a><text>, #</text><a link="sa_imm8" hover="8-bit unsigned immediate [0-255] (field &quot;imm8&quot;)">&lt;imm8&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SUB_i/T2_A.txt" mylink="aarch32.instrs.SUB_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdn);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdn);  setflags = !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>();  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T3" oneof="6" id="iclass_t3" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SUB_i/T3_A.txt" tworows="1">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1101">
          <c colspan="4">!= 1101</c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="SUB_i_T3" oneofinclass="2" oneof="8" label="SUB" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SUB" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate comment="Inside IT block, and &lt;Rd&gt;, &lt;Rn&gt;, &lt;const&gt; can be represented in T1 or T2"><text>SUB</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
        <asmtemplate><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SUBS_i_T3" oneofinclass="2" oneof="8" label="SUBS" bitdiffs="S == 1 &amp;&amp; Rd != 1111">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SUBS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Outside IT block, and &lt;Rd&gt;, &lt;Rn&gt;, &lt;const&gt; can be represented in T1 or T2"><text>SUBS.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
        <asmtemplate><text>SUBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SUB_i/T3_A.txt" mylink="aarch32.instrs.SUB_i.T3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rd == '1111' &amp;&amp; S == '1' then SEE "CMP (immediate)";</line>
<line>if Rn == '1101' then SEE "SUB (SP minus immediate)";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = (S == '1');  imm32 = <a link="impl-aarch32.T32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) T32ExpandImm(bits(12) imm12)">T32ExpandImm</a>(i:imm3:imm8);</line>
<line>if (d == 15 &amp;&amp; !setflags) || n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T4" oneof="6" id="iclass_t4" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T4" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SUBW" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SUB_i/T4_A.txt" tworows="1">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 11x1">
          <c colspan="4">!= 11x1</c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="SUB_i_T4" oneofinclass="1" oneof="8" label="T4">
        <docvars>
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SUBW" />
        </docvars>
        <asmtemplate comment="&lt;imm12&gt; cannot be represented in T1, T2, or T3"><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_2" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_imm12" hover="12-bit unsigned immediate [0-4095] (field &quot;i:imm3:imm8&quot;)">&lt;imm12&gt;</a></asmtemplate>
        <asmtemplate comment="&lt;imm12&gt; can be represented in T1, T2, or T3"><text>SUBW</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_2" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_imm12" hover="12-bit unsigned immediate [0-4095] (field &quot;i:imm3:imm8&quot;)">&lt;imm12&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SUB_i/T4_A.txt" mylink="aarch32.instrs.SUB_i.T4_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "ADR";</line>
<line>if Rn == '1101' then SEE "SUB (SP minus immediate)";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(i:imm3:imm8, 32);</line>
<line>if d == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T5" oneof="6" id="iclass_t5" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T5" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SUBS" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SUB_i/T5_AS.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="SUBS_PC_T5_AS" oneofinclass="1" oneof="8" label="T5" bitdiffs="!(Rn == 1110 &amp;&amp; imm8 == 00000000)">
        <docvars>
          <docvar key="armarmheading" value="T5" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SUBS" />
        </docvars>
        <box hibit="19" width="20" name="Rn:imm8">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
        </box>
        <asmtemplate><text>SUBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> PC, LR, #</text><a link="sa_imm8_1" hover="8-bit unsigned immediate [0-255] (field &quot;imm8&quot;)">&lt;imm8&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SUB_i/T5_AS.txt" mylink="aarch32.instrs.SUB_i.T5_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1110' &amp;&amp; <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(imm8) then SEE "ERET";</line>
<line>d = 15;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  setflags = TRUE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);</line>
<line>if n != 14 then UNPREDICTABLE;</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SUB_i_A1, SUB_i_T1, SUB_i_T2, SUB_i_T3, SUB_i_T4, SUBS_PC_T5_AS" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_i_A1, SUB_i_T1, SUB_i_T2, SUB_i_T3, SUB_i_T4, SUBS_PC_T5_AS" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_i_T2" symboldefcount="1">
      <symbol link="sa_rdn">&lt;Rdn&gt;</symbol>
      <account encodedin="Rdn">
        <intro>
          <para>Is the general-purpose source and destination register, encoded in the "Rdn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_i_T2" symboldefcount="1">
      <symbol link="sa_imm8">&lt;imm8&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="mnemonic" value="SUB" />
        </docvars>
        <intro>
          <para>For encoding T2: is a 8-bit unsigned immediate, in the range 0 to 255, encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUBS_PC_T5_AS" symboldefcount="2">
      <symbol link="sa_imm8_1">&lt;imm8&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="armarmheading" value="T5" />
          <docvar key="mnemonic" value="SUBS" />
        </docvars>
        <intro>
          <para>For encoding T5: is a 8-bit unsigned immediate, in the range 0 to 255, encoded in the "imm8" field. If <syntax>&lt;Rn&gt;</syntax> is the LR, and zero is used, see <xref linkend="A32T32-base.instructions.ERET">ERET</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_i_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SUB" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>. If the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the SUB variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the SUBS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;. Arm deprecates use of this instruction unless <syntax>&lt;Rn&gt;</syntax> is the LR.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_i_T1, SUB_i_T3, SUB_i_T4" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1, T3 and T4: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_i_A1, SUB_i_T4" symboldefcount="1">
      <symbol link="sa_rn_2">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>For encoding A1 and T4: is the general-purpose source register, encoded in the "Rn" field. If the SP is used, see <xref linkend="A32T32-base.instructions.SUB_SP_i">SUB (SP minus immediate)</xref>. If the PC is used, see <xref linkend="A32T32-base.instructions.ADR">ADR</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_i_T1" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SUB" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_i_T3" symboldefcount="3">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SUB" />
        </docvars>
        <intro>
          <para>For encoding T3: is the general-purpose source register, encoded in the "Rn" field. If the SP is used, see <xref linkend="A32T32-base.instructions.SUB_SP_i">SUB (SP minus immediate)</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_i_T1" symboldefcount="1">
      <symbol link="sa_imm3">&lt;imm3&gt;</symbol>
      <account encodedin="imm3">
        <intro>
          <para>Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "imm3" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_i_T4" symboldefcount="1">
      <symbol link="sa_imm12">&lt;imm12&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <intro>
          <para>Is a 12-bit unsigned immediate, in the range 0 to 4095, encoded in the "i:imm3:imm8" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_i_A1" symboldefcount="1">
      <symbol link="sa_const_1">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: an immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_i_T3" symboldefcount="2">
      <symbol link="sa_const">&lt;const&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3: an immediate value. See <xref linkend="BABGHAGA">Modified immediate constants in T32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SUB_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], NOT(imm32), '1');</line>
<line>    if d == 15 then</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sub_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SUB_r" title="SUB, SUBS (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SUB, SUBS (register)</heading>
  <desc>
    <brief>
      <para>Subtract (register)</para>
    </brief>
    <authored>
      <para>Subtract (register) subtracts an optionally-shifted register value from a register value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the SUBS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The SUB variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The SUBS variant of the instruction performs an exception return without the use of the stack. Arm deprecates use of this instruction. However, in this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SUB_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1101">
          <c colspan="4">!= 1101</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SUB_r_A1_RRX" oneofinclass="4" oneof="9" label="SUB, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SUB" />
          <docvar key="mnemonic-shift-type" value="SUB-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_2" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="SUB_r_A1" oneofinclass="4" oneof="9" label="SUB, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SUB" />
          <docvar key="mnemonic-shift-type" value="SUB-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_2" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="SUBS_r_A1_RRX" oneofinclass="4" oneof="9" label="SUBS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SUBS" />
          <docvar key="mnemonic-shift-type" value="SUBS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>SUBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_2" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="SUBS_r_A1" oneofinclass="4" oneof="9" label="SUBS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SUBS" />
          <docvar key="mnemonic-shift-type" value="SUBS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>SUBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_2" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SUB_r/A1_A.txt" mylink="aarch32.instrs.SUB_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1101' then SEE "SUB (SP minus register)";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SUB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/SUB_r/T1_A.txt">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="25" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="24" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="21" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="SUB_r_T1" oneofinclass="1" oneof="9" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SUB" />
        </docvars>
        <asmtemplate comment="Inside IT block"><text>SUB</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate comment="Outside IT block"><text>SUBS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SUB_r/T1_A.txt" mylink="aarch32.instrs.SUB_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>();</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SUB_r/T2_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1101">
          <c colspan="4">!= 1101</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SUB_r_T2_RRX" oneofinclass="4" oneof="9" label="SUB, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SUB" />
          <docvar key="mnemonic-shift-type" value="SUB-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="SUB_r_T2" oneofinclass="4" oneof="9" label="SUB, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SUB" />
          <docvar key="mnemonic-shift-type" value="SUB-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Inside IT block, and &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>SUB</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="SUBS_r_T2_RRX" oneofinclass="4" oneof="9" label="SUBS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm3 == 000 &amp;&amp; Rd != 1111 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SUBS" />
          <docvar key="mnemonic-shift-type" value="SUBS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="11" width="4" name="Rd">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>SUBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="SUBS_r_T2" oneofinclass="4" oneof="9" label="SUBS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11) &amp;&amp; Rd != 1111">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SUBS" />
          <docvar key="mnemonic-shift-type" value="SUBS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <box hibit="11" width="4" name="Rd">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="Outside IT block, and &lt;Rd&gt;, &lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>SUBS.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>SUBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SUB_r/T2_A.txt" mylink="aarch32.instrs.SUB_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rd == '1111' &amp;&amp; S == '1' then SEE "CMP (register)";</line>
<line>if Rn == '1101' then SEE "SUB (SP minus register)";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm3:imm2);</line>
<line>if (d == 15 &amp;&amp; !setflags) || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SUB_r_A1, SUB_r_T1, SUB_r_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_r_A1, SUB_r_T1, SUB_r_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_r_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="SUB-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the SUB variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the SUBS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_r_T1, SUB_r_T2" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_r_A1" symboldefcount="1">
      <symbol link="sa_rn_2">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="SUB-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated. If the SP is used, see <xref linkend="A32T32-base.instructions.SUB_SP_r">SUB (SP minus register)</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_r_T1" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_r_T2" symboldefcount="3">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic-shift-type" value="SUB-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding T2: is the first general-purpose source register, encoded in the "Rn" field. If the SP is used, see <xref linkend="A32T32-base.instructions.SUB_SP_r">SUB (SP minus register)</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_r_A1" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="SUB-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_r_T1, SUB_r_T2" symboldefcount="2">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_r_A1, SUB_r_T2" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="SUB_r_A1" symboldefcount="1">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_r_T2" symboldefcount="2">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm3:imm2" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SUB_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], NOT(shifted), '1');</line>
<line>    if d == 15 then          // Can only occur for A32 encoding</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sub_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SUB_rr" title="SUB, SUBS (register-shifted register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
  </docvars>
  <heading>SUB, SUBS (register-shifted register)</heading>
  <desc>
    <brief>
      <para>Subtract (register-shifted register)</para>
    </brief>
    <authored>
      <para>Subtract (register-shifted register) subtracts a register-shifted register value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SUB_rr/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SUBS_rr_A1" oneofinclass="2" oneof="2" label="Flag setting" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SUBS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>SUBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="Third general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SUB_rr_A1" oneofinclass="2" oneof="2" label="Not flag setting" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SUB" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="Third general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SUB_rr/A1_A.txt" mylink="aarch32.instrs.SUB_rr.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);</line>
<line>setflags = (S == '1');  shift_t = <a link="impl-aarch32.DecodeRegShift.1" file="shared_pseudocode.xml" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</a>(stype);</line>
<line>if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SUB_rr_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_rr_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_rr_A1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_rr_A1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_rr_A1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_rr_A1" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="SUB_rr_A1" symboldefcount="1">
      <symbol link="sa_rs">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the third general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SUB_rr/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shift_n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[s]&lt;7:0&gt;);</line>
<line>    shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], NOT(shifted), '1');</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>    if setflags then</line>
<line>        PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sub_sp_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SUB_SP_i" title="SUB, SUBS (SP minus immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SUB, SUBS (SP minus immediate)</heading>
  <desc>
    <brief>
      <para>Subtract from SP (immediate)</para>
    </brief>
    <authored>
      <para>Subtract from SP (immediate) subtracts an immediate value from the SP value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the SUBS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. If the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The SUB variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The SUBS variant of the instruction performs an exception return without the use of the stack. Arm deprecates use of this instruction. However, in this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SUB_SP_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="SUB_SP_i_A1" oneofinclass="2" oneof="6" label="SUB" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SUB" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SUBS_SP_i_A1" oneofinclass="2" oneof="6" label="SUBS" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SUBS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>SUBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SUB_SP_i/A1_A.txt" mylink="aarch32.instrs.SUB_SP_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  setflags = (S == '1');  imm32 = <a link="impl-aarch32.A32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) A32ExpandImm(bits(12) imm12)">A32ExpandImm</a>(imm12);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SUB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/SUB_SP_i/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" width="7" name="imm7" usename="1">
          <c colspan="7"></c>
        </box>
      </regdiagram>
      <encoding name="SUB_SP_i_T1" oneofinclass="1" oneof="6" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SUB" />
        </docvars>
        <asmtemplate><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_sp" hover="Stack pointer">{SP,}</a><text> SP, #</text><a link="sa_imm7" hover="Unsigned immediate, multiple of 4 [0-508] (field &quot;imm7&quot;)">&lt;imm7&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SUB_SP_i/T1_A.txt" mylink="aarch32.instrs.SUB_SP_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = 13;  setflags = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm7:'00', 32);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SUB_SP_i/T2_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="SUB_SP_i_T2" oneofinclass="2" oneof="6" label="SUB" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SUB" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate comment="&lt;Rd&gt;, &lt;const&gt; can be represented in T1"><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
        <asmtemplate><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SUBS_SP_i_T2" oneofinclass="2" oneof="6" label="SUBS" bitdiffs="S == 1 &amp;&amp; Rd != 1111">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SUBS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>SUBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SUB_SP_i/T2_A.txt" mylink="aarch32.instrs.SUB_SP_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rd == '1111' &amp;&amp; S == '1' then SEE "CMP (immediate)";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  setflags = (S == '1');  imm32 = <a link="impl-aarch32.T32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) T32ExpandImm(bits(12) imm12)">T32ExpandImm</a>(i:imm3:imm8);</line>
<line>if d == 15 &amp;&amp; !setflags then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T3" oneof="4" id="iclass_t3" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SUBW" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SUB_SP_i/T3_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="SUB_SP_i_T3" oneofinclass="1" oneof="6" label="T3">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SUBW" />
        </docvars>
        <asmtemplate comment="&lt;imm12&gt; cannot be represented in T1, T2, or T3"><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, #</text><a link="sa_imm12" hover="12-bit unsigned immediate [0-4095] (field &quot;i:imm3:imm8&quot;)">&lt;imm12&gt;</a></asmtemplate>
        <asmtemplate comment="&lt;imm12&gt; can be represented in T1, T2, or T3"><text>SUBW</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, #</text><a link="sa_imm12" hover="12-bit unsigned immediate [0-4095] (field &quot;i:imm3:imm8&quot;)">&lt;imm12&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SUB_SP_i/T3_A.txt" mylink="aarch32.instrs.SUB_SP_i.T3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  setflags = FALSE;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(i:imm3:imm8, 32);</line>
<line>if d == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SUB_SP_i_A1, SUB_SP_i_T1, SUB_SP_i_T2, SUB_SP_i_T3" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_SP_i_A1, SUB_SP_i_T1, SUB_SP_i_T2, SUB_SP_i_T3" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_SP_i_T1" symboldefcount="1">
      <symbol link="sa_sp">SP,</symbol>
      <account encodedin="">
        <intro>
          <para>Is the stack pointer.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_SP_i_T1" symboldefcount="1">
      <symbol link="sa_imm7">&lt;imm7&gt;</symbol>
      <account encodedin="imm7">
        <intro>
          <para>Is the unsigned immediate, a multiple of 4, in the range 0 to 508, encoded in the "imm7" field as &lt;imm7&gt;/4.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_SP_i_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SUB" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the SP. If the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the SUB variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the SUBS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;. Arm deprecates use of this instruction unless <syntax>&lt;Rn&gt;</syntax> is the LR.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_SP_i_T2, SUB_SP_i_T3" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2 and T3: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the SP.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_SP_i_T3" symboldefcount="1">
      <symbol link="sa_imm12">&lt;imm12&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <intro>
          <para>Is a 12-bit unsigned immediate, in the range 0 to 4095, encoded in the "i:imm3:imm8" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_SP_i_A1" symboldefcount="1">
      <symbol link="sa_const_1">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: an immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_SP_i_T2" symboldefcount="2">
      <symbol link="sa_const">&lt;const&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: an immediate value. See <xref linkend="BABGHAGA">Modified immediate constants in T32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SUB_SP_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[13], NOT(imm32), '1');</line>
<line>    if d == 15 then          // Can only occur for A32 encoding</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sub_sp_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SUB_SP_r" title="SUB, SUBS (SP minus register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SUB, SUBS (SP minus register)</heading>
  <desc>
    <brief>
      <para>Subtract from SP (register)</para>
    </brief>
    <authored>
      <para>Subtract from SP (register) subtracts an optionally-shifted register value from the SP value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the SUBS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. If the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The SUB variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The SUBS variant of the instruction performs an exception return without the use of the stack. Arm deprecates use of this instruction. However, in this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SUB_SP_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SUB_SP_r_A1_RRX" oneofinclass="4" oneof="8" label="SUB, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SUB" />
          <docvar key="mnemonic-shift-type" value="SUB-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> , RRX</text></asmtemplate>
      </encoding>
      <encoding name="SUB_SP_r_A1" oneofinclass="4" oneof="8" label="SUB, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SUB" />
          <docvar key="mnemonic-shift-type" value="SUB-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="SUBS_SP_r_A1_RRX" oneofinclass="4" oneof="8" label="SUBS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SUBS" />
          <docvar key="mnemonic-shift-type" value="SUBS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>SUBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> , RRX</text></asmtemplate>
      </encoding>
      <encoding name="SUBS_SP_r_A1" oneofinclass="4" oneof="8" label="SUBS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SUBS" />
          <docvar key="mnemonic-shift-type" value="SUBS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>SUBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SUB_SP_r/A1_A.txt" mylink="aarch32.instrs.SUB_SP_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SUB_SP_r/T1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SUB_SP_r_T1_RRX" oneofinclass="4" oneof="8" label="SUB, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SUB" />
          <docvar key="mnemonic-shift-type" value="SUB-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="SUB_SP_r_T1" oneofinclass="4" oneof="8" label="SUB, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SUB" />
          <docvar key="mnemonic-shift-type" value="SUB-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="&lt;Rd&gt;, &lt;Rm&gt; can be represented in T1 or T2"><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="SUBS_SP_r_T1_RRX" oneofinclass="4" oneof="8" label="SUBS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm3 == 000 &amp;&amp; Rd != 1111 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SUBS" />
          <docvar key="mnemonic-shift-type" value="SUBS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="11" width="4" name="Rd">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>SUBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="SUBS_SP_r_T1" oneofinclass="4" oneof="8" label="SUBS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11) &amp;&amp; Rd != 1111">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SUBS" />
          <docvar key="mnemonic-shift-type" value="SUBS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <box hibit="11" width="4" name="Rd">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>SUBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SUB_SP_r/T1_A.txt" mylink="aarch32.instrs.SUB_SP_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rd == '1111' &amp;&amp; S == '1' then SEE "CMP (register)";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm3:imm2);</line>
<line>if (d == 15 &amp;&amp; !setflags) || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SUB_SP_r_A1, SUB_SP_r_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_SP_r_A1, SUB_SP_r_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_SP_r_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the SP. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the SUB variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the SUBS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_SP_r_T1" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the SP.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_SP_r_A1" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_SP_r_T1" symboldefcount="2">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_SP_r_A1, SUB_SP_r_T1" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="SUB_SP_r_A1" symboldefcount="1">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_SP_r_T1" symboldefcount="2">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm3:imm2" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SUB_SP_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[13], NOT(shifted), '1');</line>
<line>    if d == 15 then          // Can only occur for A32 encoding</line>
<line>        if setflags then</line>
<line>            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;</line>
<line>        if setflags then</line>
<line>            PSTATE.&lt;N,Z,C,V&gt; = nzcv;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="svc.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SVC" title="SVC -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SVC" />
  </docvars>
  <heading>SVC</heading>
  <desc>
    <brief>
      <para>Supervisor Call</para>
    </brief>
    <authored>
      <para>Supervisor Call causes a Supervisor Call exception. For more information, see <xref linkend="CIHFBAIJ">Supervisor Call (SVC) exception</xref>.</para>
      <note>
        <para><instruction>SVC</instruction> was previously called <instruction>SWI</instruction>, Software Interrupt, and this name is still found in some documentation.</para>
      </note>
      <para>Software can use this instruction as a call to an operating system to provide a service.</para>
      <para>In the following cases, the Supervisor Call exception generated by the <instruction>SVC</instruction> instruction is taken to Hyp mode:</para>
      <list type="unordered">
        <listitem><content>If the <instruction>SVC</instruction> is executed in Hyp mode.</content></listitem>
        <listitem><content>If <xref linkend="AArch32.hcr">HCR</xref>.TGE is set to 1, and the <instruction>SVC</instruction> is executed in Non-secure User mode. For more information, see <xref linkend="BEIJJBDG">Supervisor Call exception, when HCR.TGE is set to 1</xref></content></listitem>
      </list>
      <para>In these cases, the <xref linkend="AArch32.hsr">HSR, Hyp Syndrome Register</xref> identifies that the exception entry was caused by a Supervisor Call exception, EC value <hexnumber>0x11</hexnumber>, see <xref linkend="BEIDBEAG">Use of the HSR</xref>. The immediate field in the <xref linkend="AArch32.hsr">HSR</xref>:</para>
      <list type="unordered">
        <listitem><content>If the <instruction>SVC</instruction> is unconditional:<list type="unordered"><listitem><content>For the T32 instruction, is the zero-extended value of the <field>imm8</field> field.</content></listitem><listitem><content>For the A32 instruction, is the least-significant 16 bits the <field>imm24</field> field.</content></listitem></list></content></listitem>
        <listitem><content>If the <instruction>SVC</instruction> is conditional, is <arm-defined-word>unknown</arm-defined-word>.</content></listitem>
      </list>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SVC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SVC/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" width="24" name="imm24" usename="1">
          <c colspan="24"></c>
        </box>
      </regdiagram>
      <encoding name="SVC_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SVC" />
        </docvars>
        <asmtemplate><text>SVC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a>{#}</a><a link="sa_imm_1" hover="24-bit unsigned immediate [0-16777215] (field &quot;imm24&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SVC/A1_A.txt" mylink="aarch32.instrs.SVC.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm24, 32);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SVC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/SVC/T1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="24" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="SVC_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SVC" />
        </docvars>
        <asmtemplate><text>SVC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a>{#}</a><a link="sa_imm" hover="8-bit unsigned immediate [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SVC/T1_A.txt" mylink="aarch32.instrs.SVC.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SVC_A1, SVC_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SVC_A1, SVC_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SVC_A1" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm24">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is a 24-bit unsigned immediate, in the range 0 to 16777215, encoded in the "imm24" field. This value is for assembly and disassembly only. SVC handlers in some systems interpret imm24 in software, for example to determine the required service.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SVC_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is a 8-bit unsigned immediate, in the range 0 to 255, encoded in the "imm8" field. This value is for assembly and disassembly only. SVC handlers in some systems interpret imm8 in software, for example to determine the required service.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SVC/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="AArch32.CheckForSVCTrap.1" file="shared_pseudocode.xml" hover="function: AArch32.CheckForSVCTrap(bits(16) immediate)">AArch32.CheckForSVCTrap</a>(imm32&lt;15:0&gt;);</line>
<line>    <a link="AArch32.CallSupervisor.1" file="shared_pseudocode.xml" hover="function: AArch32.CallSupervisor(bits(16) immediate_in)">AArch32.CallSupervisor</a>(imm32&lt;15:0&gt;);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sxtab.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SXTAB" title="SXTAB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SXTAB" />
  </docvars>
  <heading>SXTAB</heading>
  <desc>
    <brief>
      <para>Signed Extend and Add Byte</para>
    </brief>
    <authored>
      <para>Signed Extend and Add Byte extracts an 8-bit value from a register, sign-extends it to 32 bits, adds the result to the value in another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SXTAB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SXTAB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="2" name="op" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SXTAB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SXTAB" />
        </docvars>
        <asmtemplate><text>SXTAB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SXTAB/A1_A.txt" mylink="aarch32.instrs.SXTAB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "SXTB";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SXTAB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SXTAB/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="op1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SXTAB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SXTAB" />
        </docvars>
        <asmtemplate><text>SXTAB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SXTAB/T1_A.txt" mylink="aarch32.instrs.SXTAB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "SXTB";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SXTAB_A1, SXTAB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTAB_A1, SXTAB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTAB_A1, SXTAB_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTAB_A1, SXTAB_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTAB_A1, SXTAB_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTAB_A1, SXTAB_T1" symboldefcount="1">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <definition encodedin="rotate">
        <intro>Is the rotate amount, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">rotate</entry>
                <entry class="symbol">&lt;amount&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">(omitted)</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">24</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SXTAB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    rotated = <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], rotation);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(rotated&lt;7:0&gt;, 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sxtab16.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SXTAB16" title="SXTAB16 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SXTAB16" />
  </docvars>
  <heading>SXTAB16</heading>
  <desc>
    <brief>
      <para>Signed Extend and Add Byte 16</para>
    </brief>
    <authored>
      <para>Signed Extend and Add Byte 16 extracts two 8-bit values from a register, sign-extends them to 16 bits each, adds the results to two 16-bit values from another register, and writes the final results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SXTAB16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SXTAB16/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="2" name="op" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SXTAB16_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SXTAB16" />
        </docvars>
        <asmtemplate><text>SXTAB16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SXTAB16/A1_A.txt" mylink="aarch32.instrs.SXTAB16.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "SXTB16";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SXTAB16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SXTAB16/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="op1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SXTAB16_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SXTAB16" />
        </docvars>
        <asmtemplate><text>SXTAB16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SXTAB16/T1_A.txt" mylink="aarch32.instrs.SXTAB16.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "SXTB16";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SXTAB16_A1, SXTAB16_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTAB16_A1, SXTAB16_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTAB16_A1, SXTAB16_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTAB16_A1, SXTAB16_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTAB16_A1, SXTAB16_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTAB16_A1, SXTAB16_T1" symboldefcount="1">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <definition encodedin="rotate">
        <intro>Is the rotate amount, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">rotate</entry>
                <entry class="symbol">&lt;amount&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">(omitted)</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">24</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SXTAB16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    rotated = <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], rotation);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt; + <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(rotated&lt;7:0&gt;, 16);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt; + <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(rotated&lt;23:16&gt;, 16);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sxtah.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SXTAH" title="SXTAH -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SXTAH" />
  </docvars>
  <heading>SXTAH</heading>
  <desc>
    <brief>
      <para>Signed Extend and Add Halfword</para>
    </brief>
    <authored>
      <para>Signed Extend and Add Halfword extracts a 16-bit value from a register, sign-extends it to 32 bits, adds the result to a value from another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SXTAH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SXTAH/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="2" name="op" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SXTAH_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SXTAH" />
        </docvars>
        <asmtemplate><text>SXTAH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SXTAH/A1_A.txt" mylink="aarch32.instrs.SXTAH.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "SXTH";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SXTAH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SXTAH/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="op1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SXTAH_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SXTAH" />
        </docvars>
        <asmtemplate><text>SXTAH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SXTAH/T1_A.txt" mylink="aarch32.instrs.SXTAH.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "SXTH";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SXTAH_A1, SXTAH_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTAH_A1, SXTAH_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTAH_A1, SXTAH_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTAH_A1, SXTAH_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTAH_A1, SXTAH_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTAH_A1, SXTAH_T1" symboldefcount="1">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <definition encodedin="rotate">
        <intro>Is the rotate amount, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">rotate</entry>
                <entry class="symbol">&lt;amount&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">(omitted)</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">24</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SXTAH/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    rotated = <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], rotation);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(rotated&lt;15:0&gt;, 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sxtb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SXTB" title="SXTB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SXTB" />
  </docvars>
  <heading>SXTB</heading>
  <desc>
    <brief>
      <para>Signed Extend Byte</para>
    </brief>
    <authored>
      <para>Signed Extend Byte extracts an 8-bit value from a register, sign-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SXTB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SXTB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="2" name="op" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SXTB_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SXTB" />
        </docvars>
        <asmtemplate><text>SXTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SXTB/A1_A.txt" mylink="aarch32.instrs.SXTB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SXTB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/SXTB/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="B" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="SXTB_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SXTB" />
        </docvars>
        <asmtemplate><text>SXTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SXTB/T1_A.txt" mylink="aarch32.instrs.SXTB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = 0;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SXTB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SXTB/T2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="op1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SXTB_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SXTB" />
        </docvars>
        <asmtemplate comment="&lt;Rd&gt;, &lt;Rm&gt; can be represented in T1"><text>SXTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>SXTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SXTB/T2_A.txt" mylink="aarch32.instrs.SXTB.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SXTB_A1, SXTB_T1, SXTB_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTB_A1, SXTB_T1, SXTB_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTB_A1, SXTB_T1, SXTB_T2" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTB_A1, SXTB_T1, SXTB_T2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTB_A1, SXTB_T2" symboldefcount="1">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <definition encodedin="rotate">
        <intro>Is the rotate amount, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">rotate</entry>
                <entry class="symbol">&lt;amount&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">(omitted)</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">24</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SXTB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    rotated = <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], rotation);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(rotated&lt;7:0&gt;, 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sxtb16.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SXTB16" title="SXTB16 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SXTB16" />
  </docvars>
  <heading>SXTB16</heading>
  <desc>
    <brief>
      <para>Signed Extend Byte 16</para>
    </brief>
    <authored>
      <para>Signed Extend Byte 16 extracts two 8-bit values from a register, sign-extends them to 16 bits each, and writes the results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SXTB16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SXTB16/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="2" name="op" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SXTB16_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SXTB16" />
        </docvars>
        <asmtemplate><text>SXTB16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SXTB16/A1_A.txt" mylink="aarch32.instrs.SXTB16.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SXTB16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SXTB16/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="op1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SXTB16_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SXTB16" />
        </docvars>
        <asmtemplate><text>SXTB16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SXTB16/T1_A.txt" mylink="aarch32.instrs.SXTB16.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SXTB16_A1, SXTB16_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTB16_A1, SXTB16_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTB16_A1, SXTB16_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTB16_A1, SXTB16_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTB16_A1, SXTB16_T1" symboldefcount="1">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <definition encodedin="rotate">
        <intro>Is the rotate amount, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">rotate</entry>
                <entry class="symbol">&lt;amount&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">(omitted)</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">24</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SXTB16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    rotated = <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], rotation);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(rotated&lt;7:0&gt;, 16);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(rotated&lt;23:16&gt;, 16);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="sxth.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="SXTH" title="SXTH -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SXTH" />
  </docvars>
  <heading>SXTH</heading>
  <desc>
    <brief>
      <para>Signed Extend Halfword</para>
    </brief>
    <authored>
      <para>Signed Extend Halfword extracts a 16-bit value from a register, sign-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SXTH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SXTH/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="2" name="op" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SXTH_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SXTH" />
        </docvars>
        <asmtemplate><text>SXTH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SXTH/A1_A.txt" mylink="aarch32.instrs.SXTH.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SXTH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/SXTH/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="SXTH_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SXTH" />
        </docvars>
        <asmtemplate><text>SXTH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SXTH/T1_A.txt" mylink="aarch32.instrs.SXTH.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = 0;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SXTH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SXTH/T2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="op1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SXTH_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SXTH" />
        </docvars>
        <asmtemplate comment="&lt;Rd&gt;, &lt;Rm&gt; can be represented in T1"><text>SXTH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>SXTH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SXTH/T2_A.txt" mylink="aarch32.instrs.SXTH.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SXTH_A1, SXTH_T1, SXTH_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTH_A1, SXTH_T1, SXTH_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTH_A1, SXTH_T1, SXTH_T2" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTH_A1, SXTH_T1, SXTH_T2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SXTH_A1, SXTH_T2" symboldefcount="1">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <definition encodedin="rotate">
        <intro>Is the rotate amount, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">rotate</entry>
                <entry class="symbol">&lt;amount&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">(omitted)</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">24</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SXTH/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    rotated = <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], rotation);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(rotated&lt;15:0&gt;, 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="tbb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="TBB" title="TBB, TBH -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="T1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="T32" />
  </docvars>
  <heading>TBB, TBH</heading>
  <desc>
    <brief>
      <para>Table Branch Byte or Halfword</para>
    </brief>
    <authored>
      <para>Table Branch Byte or Halfword causes a PC-relative forward branch using a table of single byte or halfword offsets. A base register provides a pointer to the table, and a second register supplies an index into the table. The branch length is twice the value returned from the table.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="T1" oneof="1" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/TBB/T1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" name="H" usename="1">
          <c></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="TBB_T1" oneofinclass="2" oneof="2" label="Byte" bitdiffs="H == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="loadstore-size" value="ls-byte" />
          <docvar key="mnemonic" value="TBB" />
        </docvars>
        <box hibit="4" width="1" name="H">
          <c>0</c>
        </box>
        <asmtemplate comment="Outside or last in IT block"><text>TBB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register holding address of table of branch lengths (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="TBH_T1" oneofinclass="2" oneof="2" label="Halfword" bitdiffs="H == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="loadstore-size" value="ls-halfword" />
          <docvar key="mnemonic" value="TBH" />
        </docvars>
        <box hibit="4" width="1" name="H">
          <c>1</c>
        </box>
        <asmtemplate comment="Outside or last in IT block"><text>TBH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register holding address of table of branch lengths (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, LSL #1]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/TBB/T1_A.txt" mylink="aarch32.instrs.TBB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  is_tbh = (H == '1');</line>
<line>if m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="TBB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TBB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TBB_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register holding the address of the table of branch lengths, encoded in the "Rn" field. The PC can be used. If it is, the table immediately follows this instruction.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TBB_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="loadstore-size" value="ls-byte" />
          <docvar key="mnemonic" value="TBB" />
        </docvars>
        <intro>
          <para>For the byte variant: is the general-purpose index register, encoded in the "Rm" field. This register contains an integer pointing to a single byte in the table. The offset in the table is the value of the index.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TBH_T1" symboldefcount="2">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="loadstore-size" value="ls-halfword" />
          <docvar key="mnemonic" value="TBH" />
        </docvars>
        <intro>
          <para>For the halfword variant: is the general-purpose index register, encoded in the "Rm" field. This register contains an integer pointing to a halfword in the table. The offset in the table is twice the value of the index.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/TBB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    integer halfwords;</line>
<line>    if is_tbh then</line>
<line>        halfwords = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]+<a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m],1), 2]);</line>
<line>    else</line>
<line>        halfwords = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]+<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], 1]);</line>
<line>    <a link="impl-aarch32.BranchWritePC.2" file="shared_pseudocode.xml" hover="function: BranchWritePC(bits(32) address_in, BranchType branch_type)">BranchWritePC</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a> + 2*halfwords, <a link="BranchType_INDIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDIR</a>);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="teq_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="TEQ_i" title="TEQ (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="TEQ" />
  </docvars>
  <heading>TEQ (immediate)</heading>
  <desc>
    <brief>
      <para>Test Equivalence (immediate)</para>
    </brief>
    <authored>
      <para>Test Equivalence (immediate) performs a bitwise exclusive OR operation on a register value and an immediate value. It updates the condition flags based on the result, and discards the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="TEQ" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/TEQ_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="TEQ_i_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="TEQ" />
        </docvars>
        <asmtemplate><text>TEQ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/TEQ_i/A1_A.txt" mylink="aarch32.instrs.TEQ_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>(imm32, carry) = <a link="impl-aarch32.A32ExpandImm_C.2" file="shared_pseudocode.xml" hover="function: (bits(32), bit) A32ExpandImm_C(bits(12) imm12, bit carry_in)">A32ExpandImm_C</a>(imm12, PSTATE.C);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="TEQ" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/TEQ_i/T1_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="TEQ_i_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="TEQ" />
        </docvars>
        <asmtemplate><text>TEQ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/TEQ_i/T1_A.txt" mylink="aarch32.instrs.TEQ_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>(imm32, carry) = <a link="impl-aarch32.T32ExpandImm_C.2" file="shared_pseudocode.xml" hover="function: (bits(32), bit) T32ExpandImm_C(bits(12) imm12, bit carry_in)">T32ExpandImm_C</a>(i:imm3:imm8, PSTATE.C);</line>
<line>if n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="TEQ_i_A1, TEQ_i_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TEQ_i_A1, TEQ_i_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TEQ_i_A1" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TEQ_i_T1" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TEQ_i_A1" symboldefcount="1">
      <symbol link="sa_const_1">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: an immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TEQ_i_T1" symboldefcount="2">
      <symbol link="sa_const">&lt;const&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: an immediate value. See <xref linkend="BABGHAGA">Modified immediate constants in T32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/TEQ_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    result = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] EOR imm32;</line>
<line>    PSTATE.N = result&lt;31&gt;;</line>
<line>    PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>    PSTATE.C = carry;</line>
<line>    // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="teq_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="TEQ_r" title="TEQ (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="TEQ" />
  </docvars>
  <heading>TEQ (register)</heading>
  <desc>
    <brief>
      <para>Test Equivalence (register)</para>
    </brief>
    <authored>
      <para>Test Equivalence (register) performs a bitwise exclusive-OR operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="TEQ" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/TEQ_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="TEQ_r_A1_RRX" oneofinclass="2" oneof="4" label="Rotate right with extend" bitdiffs="imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="TEQ" />
          <docvar key="mnemonic-shift-type" value="TEQ-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>TEQ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="TEQ_r_A1" oneofinclass="2" oneof="4" label="Shift or rotate by value" bitdiffs="!(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="TEQ" />
          <docvar key="mnemonic-shift-type" value="TEQ-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>TEQ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/TEQ_r/A1_A.txt" mylink="aarch32.instrs.TEQ_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="TEQ" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/TEQ_r/T1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="TEQ_r_T1_RRX" oneofinclass="2" oneof="4" label="Rotate right with extend" bitdiffs="imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="TEQ" />
          <docvar key="mnemonic-shift-type" value="TEQ-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>TEQ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="TEQ_r_T1" oneofinclass="2" oneof="4" label="Shift or rotate by value" bitdiffs="!(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="TEQ" />
          <docvar key="mnemonic-shift-type" value="TEQ-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>TEQ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/TEQ_r/T1_A.txt" mylink="aarch32.instrs.TEQ_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm3:imm2);</line>
<line>if n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="TEQ_r_A1, TEQ_r_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TEQ_r_A1, TEQ_r_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TEQ_r_A1" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TEQ_r_T1" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TEQ_r_A1" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TEQ_r_T1" symboldefcount="2">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TEQ_r_A1, TEQ_r_T1" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="TEQ_r_A1" symboldefcount="1">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TEQ_r_T1" symboldefcount="2">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm3:imm2" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/TEQ_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    (shifted, carry) = <a link="impl-aarch32.Shift_C.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift_C</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    result = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] EOR shifted;</line>
<line>    PSTATE.N = result&lt;31&gt;;</line>
<line>    PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>    PSTATE.C = carry;</line>
<line>    // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="teq_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="TEQ_rr" title="TEQ (register-shifted register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
    <docvar key="mnemonic" value="TEQ" />
  </docvars>
  <heading>TEQ (register-shifted register)</heading>
  <desc>
    <brief>
      <para>Test Equivalence (register-shifted register)</para>
    </brief>
    <authored>
      <para>Test Equivalence (register-shifted register) performs a bitwise exclusive-OR operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="TEQ" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/TEQ_rr/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="TEQ_rr_A1" oneofinclass="1" oneof="1" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="TEQ" />
        </docvars>
        <asmtemplate><text>TEQ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_type" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;type&gt;</a><text> </text><a link="sa_rs" hover="Third general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/TEQ_rr/A1_A.txt" mylink="aarch32.instrs.TEQ_rr.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);</line>
<line>shift_t = <a link="impl-aarch32.DecodeRegShift.1" file="shared_pseudocode.xml" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</a>(stype);</line>
<line>if n == 15 || m == 15 || s == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="TEQ_rr_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TEQ_rr_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TEQ_rr_A1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TEQ_rr_A1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TEQ_rr_A1" symboldefcount="1">
      <symbol link="sa_type">&lt;type&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;type&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="TEQ_rr_A1" symboldefcount="1">
      <symbol link="sa_rs">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the third general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/TEQ_rr/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shift_n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[s]&lt;7:0&gt;);</line>
<line>    (shifted, carry) = <a link="impl-aarch32.Shift_C.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift_C</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    result = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] EOR shifted;</line>
<line>    PSTATE.N = result&lt;31&gt;;</line>
<line>    PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>    PSTATE.C = carry;</line>
<line>    // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="tsb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="TSB" title="TSB CSYNC -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="TSB" />
  </docvars>
  <heading>TSB CSYNC</heading>
  <desc>
    <brief>
      <para>Trace Synchronization Barrier</para>
    </brief>
    <authored>
      <para>Trace Synchronization Barrier. This instruction is a barrier that synchronizes the trace operations of instructions.</para>
      <para>If <xref linkend="v8.4.Trace">FEAT_TRF</xref> is not implemented, this instruction executes as a <instruction>NOP</instruction>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="TSB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.4" feature="FEAT_TRF" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/TSB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="R" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="imm4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" width="12" name="imm12" settings="12">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="TSB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="TSB" />
        </docvars>
        <asmtemplate><text>TSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> CSYNC</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/TSB/A1_A.txt" mylink="aarch32.instrs.TSB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveSelfHostedTrace.0" file="shared_pseudocode.xml" hover="function: boolean HaveSelfHostedTrace()">HaveSelfHostedTrace</a>() then <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP</line>
<line>if cond != '1110' then UNPREDICTABLE;              // TSB must be encoded with AL condition</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNCOND" />
          <cu_type constraint="Constraint_COND" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="TSB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.4" feature="FEAT_TRF" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/TSB/T1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="hint" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="option" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="TSB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="TSB" />
        </docvars>
        <asmtemplate><text>TSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> CSYNC</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/TSB/T1_A.txt" mylink="aarch32.instrs.TSB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveSelfHostedTrace.0" file="shared_pseudocode.xml" hover="function: boolean HaveSelfHostedTrace()">HaveSelfHostedTrace</a>() then <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNCOND" />
          <cu_type constraint="Constraint_COND" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="TSB_A1, TSB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TSB_A1, TSB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/TSB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-shared.TraceSynchronizationBarrier.0" file="shared_pseudocode.xml" hover="function: TraceSynchronizationBarrier()">TraceSynchronizationBarrier</a>();</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="tst_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="TST_i" title="TST (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="TST" />
  </docvars>
  <heading>TST (immediate)</heading>
  <desc>
    <brief>
      <para>Test (immediate)</para>
    </brief>
    <authored>
      <para>Test (immediate) performs a bitwise AND operation on a register value and an immediate value. It updates the condition flags based on the result, and discards the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="TST" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/TST_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="TST_i_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="TST" />
        </docvars>
        <asmtemplate><text>TST</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn_1" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const_1" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/TST_i/A1_A.txt" mylink="aarch32.instrs.TST_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>(imm32, carry) = <a link="impl-aarch32.A32ExpandImm_C.2" file="shared_pseudocode.xml" hover="function: (bits(32), bit) A32ExpandImm_C(bits(12) imm12, bit carry_in)">A32ExpandImm_C</a>(imm12, PSTATE.C);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="TST" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/TST_i/T1_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="TST_i_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="TST" />
        </docvars>
        <asmtemplate><text>TST</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/TST_i/T1_A.txt" mylink="aarch32.instrs.TST_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>(imm32, carry) = <a link="impl-aarch32.T32ExpandImm_C.2" file="shared_pseudocode.xml" hover="function: (bits(32), bit) T32ExpandImm_C(bits(12) imm12, bit carry_in)">T32ExpandImm_C</a>(i:imm3:imm8, PSTATE.C);</line>
<line>if n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="TST_i_A1, TST_i_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TST_i_A1, TST_i_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TST_i_A1" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TST_i_T1" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TST_i_A1" symboldefcount="1">
      <symbol link="sa_const_1">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: an immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TST_i_T1" symboldefcount="2">
      <symbol link="sa_const">&lt;const&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: an immediate value. See <xref linkend="BABGHAGA">Modified immediate constants in T32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/TST_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    result = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] AND imm32;</line>
<line>    PSTATE.N = result&lt;31&gt;;</line>
<line>    PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>    PSTATE.C = carry;</line>
<line>    // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="tst_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="TST_r" title="TST (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="TST" />
  </docvars>
  <heading>TST (register)</heading>
  <desc>
    <brief>
      <para>Test (register)</para>
    </brief>
    <authored>
      <para>Test (register) performs a bitwise AND operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="TST" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/TST_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="TST_r_A1_RRX" oneofinclass="2" oneof="5" label="Rotate right with extend" bitdiffs="imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="TST" />
          <docvar key="mnemonic-shift-type" value="TST-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>TST</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="TST_r_A1" oneofinclass="2" oneof="5" label="Shift or rotate by value" bitdiffs="!(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="TST" />
          <docvar key="mnemonic-shift-type" value="TST-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>TST</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn_1" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/TST_r/A1_A.txt" mylink="aarch32.instrs.TST_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="TST" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/TST_r/T1_A.txt">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="25" width="4" name="op" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="TST_r_T1" oneofinclass="1" oneof="5" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="TST" />
        </docvars>
        <asmtemplate><text>TST</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/TST_r/T1_A.txt" mylink="aarch32.instrs.TST_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="TST" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/TST_r/T2_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="TST_r_T2_RRX" oneofinclass="2" oneof="5" label="Rotate right with extend" bitdiffs="imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="TST" />
          <docvar key="mnemonic-shift-type" value="TST-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>TST</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="TST_r_T2" oneofinclass="2" oneof="5" label="Shift or rotate by value" bitdiffs="!(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="TST" />
          <docvar key="mnemonic-shift-type" value="TST-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="&lt;Rn&gt;, &lt;Rm&gt; can be represented in T1"><text>TST</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>TST</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/TST_r/T2_A.txt" mylink="aarch32.instrs.TST_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm3:imm2);</line>
<line>if n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="TST_r_A1, TST_r_T1, TST_r_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TST_r_A1, TST_r_T1, TST_r_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TST_r_A1" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="TST-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TST_r_T1, TST_r_T2" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TST_r_A1" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="TST-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TST_r_T1, TST_r_T2" symboldefcount="2">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TST_r_A1, TST_r_T2" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="TST_r_A1" symboldefcount="1">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TST_r_T2" symboldefcount="2">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm3:imm2" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/TST_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    (shifted, carry) = <a link="impl-aarch32.Shift_C.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift_C</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    result = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] AND shifted;</line>
<line>    PSTATE.N = result&lt;31&gt;;</line>
<line>    PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>    PSTATE.C = carry;</line>
<line>    // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="tst_rr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="TST_rr" title="TST (register-shifted register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
    <docvar key="mnemonic" value="TST" />
  </docvars>
  <heading>TST (register-shifted register)</heading>
  <desc>
    <brief>
      <para>Test (register-shifted register)</para>
    </brief>
    <authored>
      <para>Test (register-shifted register) performs a bitwise AND operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="TST" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/TST_rr/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="TST_rr_A1" oneofinclass="1" oneof="1" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="TST" />
        </docvars>
        <asmtemplate><text>TST</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_type" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;type&gt;</a><text> </text><a link="sa_rs" hover="Third general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/TST_rr/A1_A.txt" mylink="aarch32.instrs.TST_rr.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);</line>
<line>shift_t = <a link="impl-aarch32.DecodeRegShift.1" file="shared_pseudocode.xml" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</a>(stype);</line>
<line>if n == 15 || m == 15 || s == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="TST_rr_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TST_rr_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TST_rr_A1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TST_rr_A1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TST_rr_A1" symboldefcount="1">
      <symbol link="sa_type">&lt;type&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;type&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="TST_rr_A1" symboldefcount="1">
      <symbol link="sa_rs">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the third general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/TST_rr/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    shift_n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[s]&lt;7:0&gt;);</line>
<line>    (shifted, carry) = <a link="impl-aarch32.Shift_C.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift_C</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);</line>
<line>    result = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] AND shifted;</line>
<line>    PSTATE.N = result&lt;31&gt;;</line>
<line>    PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);</line>
<line>    PSTATE.C = carry;</line>
<line>    // PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="uadd16.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UADD16" title="UADD16 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UADD16" />
  </docvars>
  <heading>UADD16</heading>
  <desc>
    <brief>
      <para>Unsigned Add 16</para>
    </brief>
    <authored>
      <para>Unsigned Add 16 performs two 16-bit unsigned integer additions, and writes the results to the destination register. It sets <xref linkend="BEIDIGBH">PSTATE</xref>.GE according to the results of the additions.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UADD16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UADD16/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UADD16_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UADD16" />
        </docvars>
        <asmtemplate><text>UADD16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UADD16/A1_A.txt" mylink="aarch32.instrs.UADD16.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UADD16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UADD16/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UADD16_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UADD16" />
        </docvars>
        <asmtemplate><text>UADD16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UADD16/T1_A.txt" mylink="aarch32.instrs.UADD16.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UADD16_A1, UADD16_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UADD16_A1, UADD16_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UADD16_A1, UADD16_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UADD16_A1, UADD16_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UADD16_A1, UADD16_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UADD16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    sum1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    sum2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = sum1&lt;15:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = sum2&lt;15:0&gt;;</line>
<line>    PSTATE.GE&lt;1:0&gt; = if sum1 &gt;= 0x10000 then '11' else '00';</line>
<line>    PSTATE.GE&lt;3:2&gt; = if sum2 &gt;= 0x10000 then '11' else '00';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="uadd8.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UADD8" title="UADD8 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UADD8" />
  </docvars>
  <heading>UADD8</heading>
  <desc>
    <brief>
      <para>Unsigned Add 8</para>
    </brief>
    <authored>
      <para>Unsigned Add 8 performs four unsigned 8-bit integer additions, and writes the results to the destination register. It sets <xref linkend="BEIDIGBH">PSTATE</xref>.GE according to the results of the additions.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UADD8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UADD8/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UADD8_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UADD8" />
        </docvars>
        <asmtemplate><text>UADD8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UADD8/A1_A.txt" mylink="aarch32.instrs.UADD8.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UADD8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UADD8/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UADD8_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UADD8" />
        </docvars>
        <asmtemplate><text>UADD8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UADD8/T1_A.txt" mylink="aarch32.instrs.UADD8.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m  == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UADD8_A1, UADD8_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UADD8_A1, UADD8_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UADD8_A1, UADD8_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UADD8_A1, UADD8_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UADD8_A1, UADD8_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UADD8/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    sum1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;7:0&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;7:0&gt;);</line>
<line>    sum2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:8&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:8&gt;);</line>
<line>    sum3 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;23:16&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;23:16&gt;);</line>
<line>    sum4 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:24&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:24&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;7:0&gt;   = sum1&lt;7:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:8&gt;  = sum2&lt;7:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;23:16&gt; = sum3&lt;7:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:24&gt; = sum4&lt;7:0&gt;;</line>
<line>    PSTATE.GE&lt;0&gt;  = if sum1 &gt;= 0x100 then '1' else '0';</line>
<line>    PSTATE.GE&lt;1&gt;  = if sum2 &gt;= 0x100 then '1' else '0';</line>
<line>    PSTATE.GE&lt;2&gt;  = if sum3 &gt;= 0x100 then '1' else '0';</line>
<line>    PSTATE.GE&lt;3&gt;  = if sum4 &gt;= 0x100 then '1' else '0';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="uasx.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UASX" title="UASX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UASX" />
  </docvars>
  <heading>UASX</heading>
  <desc>
    <brief>
      <para>Unsigned Add and Subtract with Exchange</para>
    </brief>
    <authored>
      <para>Unsigned Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, and writes the results to the destination register. It sets <xref linkend="BEIDIGBH">PSTATE</xref>.GE according to the results.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UASX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UASX/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UASX_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UASX" />
        </docvars>
        <asmtemplate><text>UASX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UASX/A1_A.txt" mylink="aarch32.instrs.UASX.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UASX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UASX/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UASX_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UASX" />
        </docvars>
        <asmtemplate><text>UASX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UASX/T1_A.txt" mylink="aarch32.instrs.UASX.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UASX_A1, UASX_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UASX_A1, UASX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UASX_A1, UASX_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UASX_A1, UASX_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UASX_A1, UASX_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UASX/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    diff = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    sum  = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = diff&lt;15:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = sum&lt;15:0&gt;;</line>
<line>    PSTATE.GE&lt;1:0&gt; = if diff &gt;= 0 then '11' else '00';</line>
<line>    PSTATE.GE&lt;3:2&gt; = if sum  &gt;= 0x10000 then '11' else '00';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="ubfx.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UBFX" title="UBFX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UBFX" />
  </docvars>
  <heading>UBFX</heading>
  <desc>
    <brief>
      <para>Unsigned Bit Field Extract</para>
    </brief>
    <authored>
      <para>Unsigned Bit Field Extract extracts any number of adjacent bits at any position from a register, zero-extends them to 32 bits, and writes the result to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UBFX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UBFX/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="widthm1" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="lsb" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UBFX_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UBFX" />
        </docvars>
        <asmtemplate><text>UBFX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_lsb_1" hover="Bit number of least significant bit in the field [0-31] (field &quot;lsb&quot;)">&lt;lsb&gt;</a><text>, #</text><a link="sa_width" hover="Width of field [1-32-&lt;lsb&gt;] (field &quot;widthm1&quot;)">&lt;width&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UBFX/A1_A.txt" mylink="aarch32.instrs.UBFX.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>lsbit = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(lsb);  widthminus1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(widthm1);</line>
<line>msbit = lsbit + widthminus1;</line>
<line>if d == 15 || n == 15 then UNPREDICTABLE;</line>
<line>if msbit &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>msbit &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UBFX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UBFX/T1_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" width="2" name="op1&lt;2:1&gt;" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="21" name="op1&lt;0&gt;" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" width="5" name="widthm1" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="UBFX_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UBFX" />
        </docvars>
        <asmtemplate><text>UBFX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa_lsb" hover="Bit number of least significant bit in the field [0-31] (field &quot;imm3:imm2&quot;)">&lt;lsb&gt;</a><text>, #</text><a link="sa_width" hover="Width of field [1-32-&lt;lsb&gt;] (field &quot;widthm1&quot;)">&lt;width&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UBFX/T1_A.txt" mylink="aarch32.instrs.UBFX.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>lsbit = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm3:imm2);  widthminus1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(widthm1);</line>
<line>msbit = lsbit + widthminus1;</line>
<line>if d == 15 || n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
<line>if msbit &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>msbit &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UBFX_A1, UBFX_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UBFX_A1, UBFX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UBFX_A1, UBFX_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UBFX_A1, UBFX_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UBFX_A1" symboldefcount="1">
      <symbol link="sa_lsb_1">&lt;lsb&gt;</symbol>
      <account encodedin="lsb">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the bit number of the least significant bit in the field, in the range 0 to 31, encoded in the "lsb" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UBFX_T1" symboldefcount="2">
      <symbol link="sa_lsb">&lt;lsb&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the bit number of the least significant bit in the field, in the range 0 to 31, encoded in the "imm3:imm2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UBFX_A1, UBFX_T1" symboldefcount="1">
      <symbol link="sa_width">&lt;width&gt;</symbol>
      <account encodedin="widthm1">
        <intro>
          <para>Is the width of the field, in the range 1 to 32-&lt;lsb&gt;, encoded in the "widthm1" field as &lt;width&gt;-1.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UBFX/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;msbit:lsbit&gt;, 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="udf.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UDF" title="UDF -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UDF" />
  </docvars>
  <heading>UDF</heading>
  <desc>
    <brief>
      <para>Permanently Undefined</para>
    </brief>
    <authored>
      <para>Permanently Undefined generates an Undefined Instruction exception.</para>
      <para>The encodings for <instruction>UDF</instruction> used in this section are defined as permanently <arm-defined-word>undefined</arm-defined-word>. However:</para>
      <list type="unordered">
        <listitem><content>With the T32 instruction set, Arm deprecates using the <instruction>UDF</instruction> instruction in an IT block.</content></listitem>
        <listitem><content>In the A32 instruction set, <instruction>UDF</instruction> is not conditional.</content></listitem>
      </list>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UDF" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UDF/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="27" width="8" settings="8">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UDF_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UDF" />
        </docvars>
        <asmtemplate><text>UDF</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a>{#}</a><a link="sa_imm_2" hover="16-bit unsigned immediate [0-65535] (field &quot;imm12:imm4&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UDF/A1_A.txt" mylink="aarch32.instrs.UDF.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12:imm4, 32);</line>
<line>// imm32 is for assembly and disassembly only, and is ignored by hardware.</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UDF" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/UDF/T1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="24" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="UDF_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UDF" />
        </docvars>
        <asmtemplate><text>UDF</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a>{#}</a><a link="sa_imm" hover="8-bit unsigned immediate [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UDF/T1_A.txt" mylink="aarch32.instrs.UDF.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);</line>
<line>// imm32 is for assembly and disassembly only, and is ignored by hardware.</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UDF" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UDF/T2_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="UDF_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UDF" />
        </docvars>
        <asmtemplate comment="&lt;imm&gt; can be represented in T1"><text>UDF</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a>{#}</a><a link="sa_imm_1" hover="16-bit unsigned immediate [0-65535] (field &quot;imm4:imm12&quot;)">&lt;imm&gt;</a></asmtemplate>
        <asmtemplate><text>UDF</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a>{#}</a><a link="sa_imm_1" hover="16-bit unsigned immediate [0-65535] (field &quot;imm4:imm12&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UDF/T2_A.txt" mylink="aarch32.instrs.UDF.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm4:imm12, 32);</line>
<line>// imm32 is for assembly and disassembly only, and is ignored by hardware.</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UDF_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. <syntax>&lt;c&gt;</syntax> must be <value>AL</value> or omitted.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UDF_T1, UDF_T2" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. Arm deprecates using any <syntax>&lt;c&gt;</syntax> value other than <value>AL</value>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UDF_A1, UDF_T1, UDF_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UDF_A1" symboldefcount="1">
      <symbol link="sa_imm_2">&lt;imm&gt;</symbol>
      <account encodedin="imm12:imm4">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm12:imm4" field. The PE ignores the value of this constant.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UDF_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is a 8-bit unsigned immediate, in the range 0 to 255, encoded in the "imm8" field. The PE ignores the value of this constant.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UDF_T2" symboldefcount="3">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm4:imm12">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the "imm4:imm12" field. The PE ignores the value of this constant.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UDF/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    UNDEFINED;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="udiv.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UDIV" title="UDIV -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UDIV" />
  </docvars>
  <heading>UDIV</heading>
  <desc>
    <brief>
      <para>Unsigned Divide</para>
    </brief>
    <authored>
      <para>Unsigned Divide divides a 32-bit unsigned integer register value by a 32-bit unsigned integer register value, and writes the result to the destination register. The condition flags are not affected.</para>
      <para>See <xref linkend="CFIBGHCC">Divide instructions</xref> for more information about this instruction.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UDIV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UDIV/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="3" name="op2" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UDIV_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UDIV" />
        </docvars>
        <asmtemplate><text>UDIV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register holding dividend (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding divisor (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UDIV/A1_A.txt" mylink="aarch32.instrs.UDIV.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);</line>
<line>if d == 15 || n == 15 || m == 15 || a != 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>Ra != '1111'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_NONE" />
          <cu_type>
            <cu_type_text>The instruction performs a divide and the register specified by Ra becomes <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UDIV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UDIV/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" name="op2" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UDIV_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UDIV" />
        </docvars>
        <asmtemplate><text>UDIV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register holding dividend (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding divisor (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UDIV/T1_A.txt" mylink="aarch32.instrs.UDIV.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
<line>if d == 15 || n == 15 || m == 15 || a != 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>Ra != '1111'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_NONE" />
          <cu_type>
            <cu_type_text>The instruction performs a divide and the register specified by Ra becomes <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UDIV_A1, UDIV_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UDIV_A1, UDIV_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UDIV_A1, UDIV_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UDIV_A1, UDIV_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register holding the dividend, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UDIV_A1, UDIV_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register holding the divisor, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UDIV/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    integer result;</line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]) == 0 then</line>
<line>        result = 0;</line>
<line>    else</line>
<line>        result = <a link="impl-shared.RoundTowardsZero.1" file="shared_pseudocode.xml" hover="function: integer RoundTowardsZero(real x)">RoundTowardsZero</a>(Real(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n])) / Real(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m])));</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result&lt;31:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="uhadd16.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UHADD16" title="UHADD16 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UHADD16" />
  </docvars>
  <heading>UHADD16</heading>
  <desc>
    <brief>
      <para>Unsigned Halving Add 16</para>
    </brief>
    <authored>
      <para>Unsigned Halving Add 16 performs two unsigned 16-bit integer additions, halves the results, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UHADD16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UHADD16/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UHADD16_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UHADD16" />
        </docvars>
        <asmtemplate><text>UHADD16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UHADD16/A1_A.txt" mylink="aarch32.instrs.UHADD16.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UHADD16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UHADD16/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UHADD16_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UHADD16" />
        </docvars>
        <asmtemplate><text>UHADD16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UHADD16/T1_A.txt" mylink="aarch32.instrs.UHADD16.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UHADD16_A1, UHADD16_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHADD16_A1, UHADD16_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHADD16_A1, UHADD16_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHADD16_A1, UHADD16_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHADD16_A1, UHADD16_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UHADD16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    sum1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    sum2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = sum1&lt;16:1&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = sum2&lt;16:1&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="uhadd8.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UHADD8" title="UHADD8 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UHADD8" />
  </docvars>
  <heading>UHADD8</heading>
  <desc>
    <brief>
      <para>Unsigned Halving Add 8</para>
    </brief>
    <authored>
      <para>Unsigned Halving Add 8 performs four unsigned 8-bit integer additions, halves the results, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UHADD8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UHADD8/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UHADD8_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UHADD8" />
        </docvars>
        <asmtemplate><text>UHADD8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UHADD8/A1_A.txt" mylink="aarch32.instrs.UHADD8.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UHADD8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UHADD8/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UHADD8_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UHADD8" />
        </docvars>
        <asmtemplate><text>UHADD8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UHADD8/T1_A.txt" mylink="aarch32.instrs.UHADD8.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UHADD8_A1, UHADD8_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHADD8_A1, UHADD8_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHADD8_A1, UHADD8_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHADD8_A1, UHADD8_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHADD8_A1, UHADD8_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UHADD8/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    sum1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;7:0&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;7:0&gt;);</line>
<line>    sum2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:8&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:8&gt;);</line>
<line>    sum3 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;23:16&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;23:16&gt;);</line>
<line>    sum4 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:24&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:24&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;7:0&gt;   = sum1&lt;8:1&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:8&gt;  = sum2&lt;8:1&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;23:16&gt; = sum3&lt;8:1&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:24&gt; = sum4&lt;8:1&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="uhasx.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UHASX" title="UHASX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UHASX" />
  </docvars>
  <heading>UHASX</heading>
  <desc>
    <brief>
      <para>Unsigned Halving Add and Subtract with Exchange</para>
    </brief>
    <authored>
      <para>Unsigned Halving Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, halves the results, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UHASX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UHASX/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UHASX_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UHASX" />
        </docvars>
        <asmtemplate><text>UHASX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UHASX/A1_A.txt" mylink="aarch32.instrs.UHASX.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UHASX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UHASX/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UHASX_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UHASX" />
        </docvars>
        <asmtemplate><text>UHASX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UHASX/T1_A.txt" mylink="aarch32.instrs.UHASX.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UHASX_A1, UHASX_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHASX_A1, UHASX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHASX_A1, UHASX_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHASX_A1, UHASX_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHASX_A1, UHASX_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UHASX/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    diff = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    sum  = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = diff&lt;16:1&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = sum&lt;16:1&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="uhsax.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UHSAX" title="UHSAX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UHSAX" />
  </docvars>
  <heading>UHSAX</heading>
  <desc>
    <brief>
      <para>Unsigned Halving Subtract and Add with Exchange</para>
    </brief>
    <authored>
      <para>Unsigned Halving Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, halves the results, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UHSAX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UHSAX/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UHSAX_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UHSAX" />
        </docvars>
        <asmtemplate><text>UHSAX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UHSAX/A1_A.txt" mylink="aarch32.instrs.UHSAX.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UHSAX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UHSAX/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UHSAX_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UHSAX" />
        </docvars>
        <asmtemplate><text>UHSAX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UHSAX/T1_A.txt" mylink="aarch32.instrs.UHSAX.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UHSAX_A1, UHSAX_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHSAX_A1, UHSAX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHSAX_A1, UHSAX_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHSAX_A1, UHSAX_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHSAX_A1, UHSAX_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UHSAX/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    sum  = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    diff = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = sum&lt;16:1&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = diff&lt;16:1&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="uhsub16.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UHSUB16" title="UHSUB16 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UHSUB16" />
  </docvars>
  <heading>UHSUB16</heading>
  <desc>
    <brief>
      <para>Unsigned Halving Subtract 16</para>
    </brief>
    <authored>
      <para>Unsigned Halving Subtract 16 performs two unsigned 16-bit integer subtractions, halves the results, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UHSUB16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UHSUB16/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UHSUB16_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UHSUB16" />
        </docvars>
        <asmtemplate><text>UHSUB16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UHSUB16/A1_A.txt" mylink="aarch32.instrs.UHSUB16.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UHSUB16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UHSUB16/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UHSUB16_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UHSUB16" />
        </docvars>
        <asmtemplate><text>UHSUB16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UHSUB16/T1_A.txt" mylink="aarch32.instrs.UHSUB16.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UHSUB16_A1, UHSUB16_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHSUB16_A1, UHSUB16_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHSUB16_A1, UHSUB16_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHSUB16_A1, UHSUB16_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHSUB16_A1, UHSUB16_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UHSUB16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    diff1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    diff2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = diff1&lt;16:1&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = diff2&lt;16:1&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="uhsub8.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UHSUB8" title="UHSUB8 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UHSUB8" />
  </docvars>
  <heading>UHSUB8</heading>
  <desc>
    <brief>
      <para>Unsigned Halving Subtract 8</para>
    </brief>
    <authored>
      <para>Unsigned Halving Subtract 8 performs four unsigned 8-bit integer subtractions, halves the results, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UHSUB8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UHSUB8/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UHSUB8_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UHSUB8" />
        </docvars>
        <asmtemplate><text>UHSUB8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UHSUB8/A1_A.txt" mylink="aarch32.instrs.UHSUB8.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UHSUB8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UHSUB8/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UHSUB8_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UHSUB8" />
        </docvars>
        <asmtemplate><text>UHSUB8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UHSUB8/T1_A.txt" mylink="aarch32.instrs.UHSUB8.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UHSUB8_A1, UHSUB8_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHSUB8_A1, UHSUB8_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHSUB8_A1, UHSUB8_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHSUB8_A1, UHSUB8_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UHSUB8_A1, UHSUB8_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UHSUB8/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    diff1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;7:0&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;7:0&gt;);</line>
<line>    diff2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:8&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:8&gt;);</line>
<line>    diff3 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;23:16&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;23:16&gt;);</line>
<line>    diff4 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:24&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:24&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;7:0&gt;   = diff1&lt;8:1&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:8&gt;  = diff2&lt;8:1&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;23:16&gt; = diff3&lt;8:1&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:24&gt; = diff4&lt;8:1&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="umaal.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UMAAL" title="UMAAL -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UMAAL" />
  </docvars>
  <heading>UMAAL</heading>
  <desc>
    <brief>
      <para>Unsigned Multiply Accumulate Accumulate Long</para>
    </brief>
    <authored>
      <para>Unsigned Multiply Accumulate Accumulate Long multiplies two unsigned 32-bit values to produce a 64-bit value, adds two unsigned 32-bit values, and writes the 64-bit result to two registers.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UMAAL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UMAAL/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="RdHi" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="RdLo" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UMAAL_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UMAAL" />
        </docvars>
        <asmtemplate><text>UMAAL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding first addend and the destination register for lower 32 bits of result (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding second addend and the destination register for upper 32 bits of result (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UMAAL/A1_A.txt" mylink="aarch32.instrs.UMAAL.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>dLo = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdLo);  dHi = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdHi);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>if dHi == dLo then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>dHi == dLo</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UMAAL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UMAAL/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="RdLo" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="RdHi" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" name="op2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UMAAL_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UMAAL" />
        </docvars>
        <asmtemplate><text>UMAAL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding first addend and the destination register for lower 32 bits of result (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding second addend and the destination register for upper 32 bits of result (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UMAAL/T1_A.txt" mylink="aarch32.instrs.UMAAL.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>dLo = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdLo);  dHi = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdHi);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
<line>if dHi == dLo then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>dHi == dLo</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UMAAL_A1, UMAAL_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UMAAL_A1, UMAAL_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UMAAL_A1, UMAAL_T1" symboldefcount="1">
      <symbol link="sa_rdlo">&lt;RdLo&gt;</symbol>
      <account encodedin="RdLo">
        <intro>
          <para>Is the general-purpose source register holding the first addend and the destination register for the lower 32 bits of the result, encoded in the "RdLo" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UMAAL_A1, UMAAL_T1" symboldefcount="1">
      <symbol link="sa_rdhi">&lt;RdHi&gt;</symbol>
      <account encodedin="RdHi">
        <intro>
          <para>Is the general-purpose source register holding the second addend and the destination register for the upper 32 bits of the result, encoded in the "RdHi" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UMAAL_A1, UMAAL_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UMAAL_A1, UMAAL_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register holding the multiplier, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UMAAL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    result = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]) * <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[dHi]) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[dLo]);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[dHi] = result&lt;63:32&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[dLo] = result&lt;31:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="umlal.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UMLAL" title="UMLAL, UMLALS -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>UMLAL, UMLALS</heading>
  <desc>
    <brief>
      <para>Unsigned Multiply Accumulate Long</para>
    </brief>
    <authored>
      <para>Unsigned Multiply Accumulate Long multiplies two unsigned 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value.</para>
      <para>In A32 instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many implementations.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UMLAL/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="RdHi" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="RdLo" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UMLALS_A1" oneofinclass="2" oneof="3" label="Flag setting" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UMLALS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>UMLALS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="UMLAL_A1" oneofinclass="2" oneof="3" label="Not flag setting" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UMLAL" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>UMLAL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UMLAL/A1_A.txt" mylink="aarch32.instrs.UMLAL.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>dLo = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdLo);  dHi = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdHi);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>if dHi == dLo then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>dHi == dLo</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UMLAL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UMLAL/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="RdLo" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="RdHi" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" name="op2" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UMLAL_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UMLAL" />
        </docvars>
        <asmtemplate><text>UMLAL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UMLAL/T1_A.txt" mylink="aarch32.instrs.UMLAL.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>dLo = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdLo);  dHi = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdHi);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = FALSE;</line>
<line>if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
<line>if dHi == dLo then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>dHi == dLo</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UMLAL_A1, UMLAL_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UMLAL_A1, UMLAL_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UMLAL_A1, UMLAL_T1" symboldefcount="1">
      <symbol link="sa_rdlo">&lt;RdLo&gt;</symbol>
      <account encodedin="RdLo">
        <intro>
          <para>Is the general-purpose source register holding the lower 32 bits of the addend, and the destination register for the lower 32 bits of the result, encoded in the "RdLo" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UMLAL_A1, UMLAL_T1" symboldefcount="1">
      <symbol link="sa_rdhi">&lt;RdHi&gt;</symbol>
      <account encodedin="RdHi">
        <intro>
          <para>Is the general-purpose source register holding the upper 32 bits of the addend, and the destination register for the upper 32 bits of the result, encoded in the "RdHi" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UMLAL_A1, UMLAL_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UMLAL_A1, UMLAL_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register holding the multiplier, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UMLAL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    result = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]) * <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[dHi]:<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[dLo]);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[dHi] = result&lt;63:32&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[dLo] = result&lt;31:0&gt;;</line>
<line>    if setflags then</line>
<line>        PSTATE.N = result&lt;63&gt;;</line>
<line>        PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result&lt;63:0&gt;);</line>
<line>        // PSTATE.C, PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="umull.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UMULL" title="UMULL, UMULLS -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>UMULL, UMULLS</heading>
  <desc>
    <brief>
      <para>Unsigned Multiply Long</para>
    </brief>
    <authored>
      <para>Unsigned Multiply Long multiplies two 32-bit unsigned values to produce a 64-bit result.</para>
      <para>In A32 instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many implementations.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UMULL/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="RdHi" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="RdLo" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UMULLS_A1" oneofinclass="2" oneof="3" label="Flag setting" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UMULLS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>UMULLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose destination register for lower 32 bits of result (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose destination register for upper 32 bits of result (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="UMULL_A1" oneofinclass="2" oneof="3" label="Not flag setting" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UMULL" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>UMULL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose destination register for lower 32 bits of result (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose destination register for upper 32 bits of result (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UMULL/A1_A.txt" mylink="aarch32.instrs.UMULL.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>dLo = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdLo);  dHi = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdHi);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');</line>
<line>if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>if dHi == dLo then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>dHi == dLo</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UMULL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UMULL/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="RdLo" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="RdHi" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" name="op2" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UMULL_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UMULL" />
        </docvars>
        <asmtemplate><text>UMULL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose destination register for lower 32 bits of result (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose destination register for upper 32 bits of result (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register holding multiplicand (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register holding multiplier (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UMULL/T1_A.txt" mylink="aarch32.instrs.UMULL.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>dLo = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdLo);  dHi = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdHi);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = FALSE;</line>
<line>if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
<line>// Armv8-A removes UNPREDICTABLE for R13</line>
<line>if dHi == dLo then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>dHi == dLo</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UMULL_A1, UMULL_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UMULL_A1, UMULL_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UMULL_A1, UMULL_T1" symboldefcount="1">
      <symbol link="sa_rdlo">&lt;RdLo&gt;</symbol>
      <account encodedin="RdLo">
        <intro>
          <para>Is the general-purpose destination register for the lower 32 bits of the result, encoded in the "RdLo" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UMULL_A1, UMULL_T1" symboldefcount="1">
      <symbol link="sa_rdhi">&lt;RdHi&gt;</symbol>
      <account encodedin="RdHi">
        <intro>
          <para>Is the general-purpose destination register for the upper 32 bits of the result, encoded in the "RdHi" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UMULL_A1, UMULL_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UMULL_A1, UMULL_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register holding the multiplier, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UMULL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    result = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]) * <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[dHi] = result&lt;63:32&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[dLo] = result&lt;31:0&gt;;</line>
<line>    if setflags then</line>
<line>        PSTATE.N = result&lt;63&gt;;</line>
<line>        PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result&lt;63:0&gt;);</line>
<line>        // PSTATE.C, PSTATE.V unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="uqadd16.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UQADD16" title="UQADD16 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UQADD16" />
  </docvars>
  <heading>UQADD16</heading>
  <desc>
    <brief>
      <para>Unsigned Saturating Add 16</para>
    </brief>
    <authored>
      <para>Unsigned Saturating Add 16 performs two unsigned 16-bit integer additions, saturates the results to the 16-bit unsigned integer range 0 &lt;= x &lt;= 2<sup>16</sup> - 1, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UQADD16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UQADD16/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UQADD16_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UQADD16" />
        </docvars>
        <asmtemplate><text>UQADD16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UQADD16/A1_A.txt" mylink="aarch32.instrs.UQADD16.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UQADD16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UQADD16/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UQADD16_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UQADD16" />
        </docvars>
        <asmtemplate><text>UQADD16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UQADD16/T1_A.txt" mylink="aarch32.instrs.UQADD16.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UQADD16_A1, UQADD16_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQADD16_A1, UQADD16_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQADD16_A1, UQADD16_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQADD16_A1, UQADD16_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQADD16_A1, UQADD16_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UQADD16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    sum1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    sum2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = <a link="impl-aarch32.UnsignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) UnsignedSat(integer i, integer N)">UnsignedSat</a>(sum1, 16);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = <a link="impl-aarch32.UnsignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) UnsignedSat(integer i, integer N)">UnsignedSat</a>(sum2, 16);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="uqadd8.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UQADD8" title="UQADD8 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UQADD8" />
  </docvars>
  <heading>UQADD8</heading>
  <desc>
    <brief>
      <para>Unsigned Saturating Add 8</para>
    </brief>
    <authored>
      <para>Unsigned Saturating Add 8 performs four unsigned 8-bit integer additions, saturates the results to the 8-bit unsigned integer range 0 &lt;= x &lt;= 2<sup>8</sup> - 1, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UQADD8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UQADD8/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UQADD8_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UQADD8" />
        </docvars>
        <asmtemplate><text>UQADD8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UQADD8/A1_A.txt" mylink="aarch32.instrs.UQADD8.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UQADD8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UQADD8/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UQADD8_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UQADD8" />
        </docvars>
        <asmtemplate><text>UQADD8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UQADD8/T1_A.txt" mylink="aarch32.instrs.UQADD8.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UQADD8_A1, UQADD8_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQADD8_A1, UQADD8_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQADD8_A1, UQADD8_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQADD8_A1, UQADD8_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQADD8_A1, UQADD8_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UQADD8/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    sum1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;7:0&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;7:0&gt;);</line>
<line>    sum2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:8&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:8&gt;);</line>
<line>    sum3 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;23:16&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;23:16&gt;);</line>
<line>    sum4 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:24&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:24&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;7:0&gt;   = <a link="impl-aarch32.UnsignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) UnsignedSat(integer i, integer N)">UnsignedSat</a>(sum1, 8);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:8&gt;  = <a link="impl-aarch32.UnsignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) UnsignedSat(integer i, integer N)">UnsignedSat</a>(sum2, 8);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;23:16&gt; = <a link="impl-aarch32.UnsignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) UnsignedSat(integer i, integer N)">UnsignedSat</a>(sum3, 8);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:24&gt; = <a link="impl-aarch32.UnsignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) UnsignedSat(integer i, integer N)">UnsignedSat</a>(sum4, 8);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="uqasx.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UQASX" title="UQASX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UQASX" />
  </docvars>
  <heading>UQASX</heading>
  <desc>
    <brief>
      <para>Unsigned Saturating Add and Subtract with Exchange</para>
    </brief>
    <authored>
      <para>Unsigned Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturates the results to the 16-bit unsigned integer range 0 &lt;= x &lt;= 2<sup>16</sup> - 1, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UQASX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UQASX/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UQASX_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UQASX" />
        </docvars>
        <asmtemplate><text>UQASX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UQASX/A1_A.txt" mylink="aarch32.instrs.UQASX.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UQASX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UQASX/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UQASX_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UQASX" />
        </docvars>
        <asmtemplate><text>UQASX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UQASX/T1_A.txt" mylink="aarch32.instrs.UQASX.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UQASX_A1, UQASX_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQASX_A1, UQASX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQASX_A1, UQASX_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQASX_A1, UQASX_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQASX_A1, UQASX_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UQASX/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    diff = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    sum  = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = <a link="impl-aarch32.UnsignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) UnsignedSat(integer i, integer N)">UnsignedSat</a>(diff, 16);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = <a link="impl-aarch32.UnsignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) UnsignedSat(integer i, integer N)">UnsignedSat</a>(sum, 16);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="uqsax.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UQSAX" title="UQSAX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UQSAX" />
  </docvars>
  <heading>UQSAX</heading>
  <desc>
    <brief>
      <para>Unsigned Saturating Subtract and Add with Exchange</para>
    </brief>
    <authored>
      <para>Unsigned Saturating Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturates the results to the 16-bit unsigned integer range 0 &lt;= x &lt;= 2<sup>16</sup> - 1, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UQSAX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UQSAX/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UQSAX_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UQSAX" />
        </docvars>
        <asmtemplate><text>UQSAX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UQSAX/A1_A.txt" mylink="aarch32.instrs.UQSAX.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UQSAX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UQSAX/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UQSAX_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UQSAX" />
        </docvars>
        <asmtemplate><text>UQSAX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UQSAX/T1_A.txt" mylink="aarch32.instrs.UQSAX.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UQSAX_A1, UQSAX_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQSAX_A1, UQSAX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQSAX_A1, UQSAX_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQSAX_A1, UQSAX_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQSAX_A1, UQSAX_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UQSAX/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    sum  = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    diff = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = <a link="impl-aarch32.UnsignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) UnsignedSat(integer i, integer N)">UnsignedSat</a>(sum, 16);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = <a link="impl-aarch32.UnsignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) UnsignedSat(integer i, integer N)">UnsignedSat</a>(diff, 16);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="uqsub16.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UQSUB16" title="UQSUB16 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UQSUB16" />
  </docvars>
  <heading>UQSUB16</heading>
  <desc>
    <brief>
      <para>Unsigned Saturating Subtract 16</para>
    </brief>
    <authored>
      <para>Unsigned Saturating Subtract 16 performs two unsigned 16-bit integer subtractions, saturates the results to the 16-bit unsigned integer range 0 &lt;= x &lt;= 2<sup>16</sup> - 1, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UQSUB16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UQSUB16/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UQSUB16_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UQSUB16" />
        </docvars>
        <asmtemplate><text>UQSUB16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UQSUB16/A1_A.txt" mylink="aarch32.instrs.UQSUB16.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UQSUB16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UQSUB16/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UQSUB16_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UQSUB16" />
        </docvars>
        <asmtemplate><text>UQSUB16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UQSUB16/T1_A.txt" mylink="aarch32.instrs.UQSUB16.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UQSUB16_A1, UQSUB16_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQSUB16_A1, UQSUB16_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQSUB16_A1, UQSUB16_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQSUB16_A1, UQSUB16_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQSUB16_A1, UQSUB16_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UQSUB16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    diff1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    diff2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = <a link="impl-aarch32.UnsignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) UnsignedSat(integer i, integer N)">UnsignedSat</a>(diff1, 16);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = <a link="impl-aarch32.UnsignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) UnsignedSat(integer i, integer N)">UnsignedSat</a>(diff2, 16);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="uqsub8.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UQSUB8" title="UQSUB8 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UQSUB8" />
  </docvars>
  <heading>UQSUB8</heading>
  <desc>
    <brief>
      <para>Unsigned Saturating Subtract 8</para>
    </brief>
    <authored>
      <para>Unsigned Saturating Subtract 8 performs four unsigned 8-bit integer subtractions, saturates the results to the 8-bit unsigned integer range 0 &lt;= x &lt;= 2<sup>8</sup> - 1, and writes the results to the destination register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UQSUB8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UQSUB8/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UQSUB8_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UQSUB8" />
        </docvars>
        <asmtemplate><text>UQSUB8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UQSUB8/A1_A.txt" mylink="aarch32.instrs.UQSUB8.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UQSUB8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UQSUB8/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UQSUB8_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UQSUB8" />
        </docvars>
        <asmtemplate><text>UQSUB8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UQSUB8/T1_A.txt" mylink="aarch32.instrs.UQSUB8.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UQSUB8_A1, UQSUB8_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQSUB8_A1, UQSUB8_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQSUB8_A1, UQSUB8_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQSUB8_A1, UQSUB8_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UQSUB8_A1, UQSUB8_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UQSUB8/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    diff1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;7:0&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;7:0&gt;);</line>
<line>    diff2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:8&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:8&gt;);</line>
<line>    diff3 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;23:16&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;23:16&gt;);</line>
<line>    diff4 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:24&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:24&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;7:0&gt;   = <a link="impl-aarch32.UnsignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) UnsignedSat(integer i, integer N)">UnsignedSat</a>(diff1, 8);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:8&gt;  = <a link="impl-aarch32.UnsignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) UnsignedSat(integer i, integer N)">UnsignedSat</a>(diff2, 8);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;23:16&gt; = <a link="impl-aarch32.UnsignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) UnsignedSat(integer i, integer N)">UnsignedSat</a>(diff3, 8);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:24&gt; = <a link="impl-aarch32.UnsignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) UnsignedSat(integer i, integer N)">UnsignedSat</a>(diff4, 8);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="usad8.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="USAD8" title="USAD8 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="USAD8" />
  </docvars>
  <heading>USAD8</heading>
  <desc>
    <brief>
      <para>Unsigned Sum of Absolute Differences</para>
    </brief>
    <authored>
      <para>Unsigned Sum of Absolute Differences performs four unsigned 8-bit subtractions, and adds the absolute values of the differences together.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="USAD8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/USAD8/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="8" settings="8">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="USAD8_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="USAD8" />
        </docvars>
        <asmtemplate><text>USAD8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/USAD8/A1_A.txt" mylink="aarch32.instrs.USAD8.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="USAD8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/USAD8/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="USAD8_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="USAD8" />
        </docvars>
        <asmtemplate><text>USAD8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/USAD8/T1_A.txt" mylink="aarch32.instrs.USAD8.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="USAD8_A1, USAD8_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USAD8_A1, USAD8_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USAD8_A1, USAD8_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USAD8_A1, USAD8_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USAD8_A1, USAD8_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/USAD8/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    absdiff1 = <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;7:0&gt;)   - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;7:0&gt;));</line>
<line>    absdiff2 = <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:8&gt;)  - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:8&gt;));</line>
<line>    absdiff3 = <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;23:16&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;23:16&gt;));</line>
<line>    absdiff4 = <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:24&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:24&gt;));</line>
<line>    result = absdiff1 + absdiff2 + absdiff3 + absdiff4;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result&lt;31:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="usada8.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="USADA8" title="USADA8 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="USADA8" />
  </docvars>
  <heading>USADA8</heading>
  <desc>
    <brief>
      <para>Unsigned Sum of Absolute Differences and Accumulate</para>
    </brief>
    <authored>
      <para>Unsigned Sum of Absolute Differences and Accumulate performs four unsigned 8-bit subtractions, and adds the absolute values of the differences to a 32-bit accumulate operand.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="USADA8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/USADA8/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="8" settings="8">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="USADA8_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="USADA8" />
        </docvars>
        <asmtemplate><text>USADA8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/USADA8/A1_A.txt" mylink="aarch32.instrs.USADA8.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Ra == '1111' then SEE "USAD8";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="USADA8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/USADA8/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Ra" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="USADA8_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="USADA8" />
        </docvars>
        <asmtemplate><text>USADA8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_ra" hover="Third general-purpose source register holding addend (field &quot;Ra&quot;)">&lt;Ra&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/USADA8/T1_A.txt" mylink="aarch32.instrs.USADA8.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Ra == '1111' then SEE "USAD8";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="USADA8_A1, USADA8_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USADA8_A1, USADA8_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USADA8_A1, USADA8_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USADA8_A1, USADA8_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USADA8_A1, USADA8_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USADA8_A1, USADA8_T1" symboldefcount="1">
      <symbol link="sa_ra">&lt;Ra&gt;</symbol>
      <account encodedin="Ra">
        <intro>
          <para>Is the third general-purpose source register holding the addend, encoded in the "Ra" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/USADA8/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    absdiff1 = <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;7:0&gt;)   - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;7:0&gt;));</line>
<line>    absdiff2 = <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:8&gt;)  - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:8&gt;));</line>
<line>    absdiff3 = <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;23:16&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;23:16&gt;));</line>
<line>    absdiff4 = <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:24&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:24&gt;));</line>
<line>    result = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[a]) + absdiff1 + absdiff2 + absdiff3 + absdiff4;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result&lt;31:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="usat.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="USAT" title="USAT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="USAT" />
  </docvars>
  <heading>USAT</heading>
  <desc>
    <brief>
      <para>Unsigned Saturate</para>
    </brief>
    <authored>
      <para>Unsigned Saturate saturates an optionally-shifted signed value to a selected unsigned range.</para>
      <para>This instruction sets <xref linkend="BEIDIGBH">PSTATE</xref>.Q to 1 if the operation saturates.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="USAT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/USAT/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="sat_imm" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" name="sh" usename="1">
          <c></c>
        </box>
        <box hibit="5" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="USAT_A1_ASR" oneofinclass="2" oneof="4" label="Arithmetic shift right" bitdiffs="sh == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="USAT" />
          <docvar key="mnemonic-shift-type" value="USAT-asr" />
          <docvar key="shift-type" value="asr" />
        </docvars>
        <box hibit="6" width="1" name="sh">
          <c>1</c>
        </box>
        <asmtemplate><text>USAT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_imm" hover="Bit position for saturation [0-31] (field &quot;sat_imm&quot;)">&lt;imm&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, ASR #</text><a link="sa_amount_3" hover="Shift amount [1-32 (field &quot;imm5&quot;)">&lt;amount&gt;</a></asmtemplate>
      </encoding>
      <encoding name="USAT_A1_LSL" oneofinclass="2" oneof="4" label="Logical shift left" bitdiffs="sh == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="USAT" />
          <docvar key="mnemonic-shift-type" value="USAT-lsl" />
          <docvar key="shift-type" value="lsl" />
        </docvars>
        <box hibit="6" width="1" name="sh">
          <c>0</c>
        </box>
        <asmtemplate><text>USAT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_imm" hover="Bit position for saturation [0-31] (field &quot;sat_imm&quot;)">&lt;imm&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, LSL #</text><a link="sa_amount_2" hover="Optional shift amount [0-31], default 0 (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/USAT/A1_A.txt" mylink="aarch32.instrs.USAT.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  saturate_to = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sat_imm);</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(sh:'0', imm5);</line>
<line>if d == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="USAT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/USAT/T1_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="21" name="sh" usename="1">
          <c></c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" width="5" name="sat_imm" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="USAT_T1_ASR" oneofinclass="2" oneof="4" label="Arithmetic shift right" bitdiffs="sh == 1 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00)">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="USAT" />
          <docvar key="mnemonic-shift-type" value="USAT-asr" />
          <docvar key="shift-type" value="asr" />
        </docvars>
        <box hibit="21" width="1" name="sh">
          <c>1</c>
        </box>
        <box hibit="14" width="9" name="imm3:imm2">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
        </box>
        <asmtemplate><text>USAT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_imm" hover="Bit position for saturation [0-31] (field &quot;sat_imm&quot;)">&lt;imm&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, ASR #</text><a link="sa_amount_1" hover="Shift amount [1-31 (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a></asmtemplate>
      </encoding>
      <encoding name="USAT_T1_LSL" oneofinclass="2" oneof="4" label="Logical shift left" bitdiffs="sh == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="USAT" />
          <docvar key="mnemonic-shift-type" value="USAT-lsl" />
          <docvar key="shift-type" value="lsl" />
        </docvars>
        <box hibit="21" width="1" name="sh">
          <c>0</c>
        </box>
        <asmtemplate><text>USAT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_imm" hover="Bit position for saturation [0-31] (field &quot;sat_imm&quot;)">&lt;imm&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, LSL #</text><a link="sa_amount" hover="Optional shift amount [0-31], default 0 (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/USAT/T1_A.txt" mylink="aarch32.instrs.USAT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if sh == '1' &amp;&amp; (imm3:imm2) == '00000' then SEE "USAT16";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  saturate_to = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sat_imm);</line>
<line>(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(sh:'0', imm3:imm2);</line>
<line>if d == 15 || n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="USAT_A1_LSL, USAT_T1_LSL" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USAT_A1_LSL, USAT_T1_LSL" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USAT_A1_LSL, USAT_T1_LSL" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USAT_A1_LSL, USAT_T1_LSL" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="sat_imm">
        <intro>
          <para>Is the bit position for saturation, in the range 0 to 31, encoded in the "sat_imm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USAT_A1_LSL, USAT_T1_LSL" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USAT_A1_LSL" symboldefcount="1">
      <symbol link="sa_amount_2">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="USAT-lsl" />
          <docvar key="shift-type" value="lsl" />
        </docvars>
        <intro>
          <para>For encoding A1: is the optional shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm5" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USAT_A1_ASR" symboldefcount="2">
      <symbol link="sa_amount_3">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="USAT-asr" />
          <docvar key="shift-type" value="asr" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 32 encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USAT_T1_LSL" symboldefcount="3">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic-shift-type" value="USAT-lsl" />
          <docvar key="shift-type" value="lsl" />
        </docvars>
        <intro>
          <para>For encoding T1: is the optional shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm3:imm2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USAT_T1_ASR" symboldefcount="4">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic-shift-type" value="USAT-asr" />
          <docvar key="shift-type" value="asr" />
        </docvars>
        <intro>
          <para>For encoding T1: is the shift amount, in the range 1 to 31 encoded in the "imm3:imm2" field as &lt;amount&gt;.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/USAT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    operand = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], shift_t, shift_n, PSTATE.C);  // PSTATE.C ignored</line>
<line>    (result, sat) = <a link="impl-shared.UnsignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand), saturate_to);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(result, 32);</line>
<line>    if sat then</line>
<line>        PSTATE.Q = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="usat16.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="USAT16" title="USAT16 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="USAT16" />
  </docvars>
  <heading>USAT16</heading>
  <desc>
    <brief>
      <para>Unsigned Saturate 16</para>
    </brief>
    <authored>
      <para>Unsigned Saturate 16 saturates two signed 16-bit values to a selected unsigned range.</para>
      <para>This instruction sets <xref linkend="BEIDIGBH">PSTATE</xref>.Q to 1 if the operation saturates.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="USAT16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/USAT16/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="sat_imm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="USAT16_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="USAT16" />
        </docvars>
        <asmtemplate><text>USAT16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_imm" hover="Bit position for saturation [0-15] (field &quot;sat_imm&quot;)">&lt;imm&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/USAT16/A1_A.txt" mylink="aarch32.instrs.USAT16.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  saturate_to = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sat_imm);</line>
<line>if d == 15 || n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="USAT16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/USAT16/T1_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" width="2" name="op1&lt;2:1&gt;" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="21" name="op1&lt;0&gt;" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="3" width="4" name="sat_imm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="USAT16_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="USAT16" />
        </docvars>
        <asmtemplate><text>USAT16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_imm" hover="Bit position for saturation [0-15] (field &quot;sat_imm&quot;)">&lt;imm&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/USAT16/T1_A.txt" mylink="aarch32.instrs.USAT16.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  saturate_to = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sat_imm);</line>
<line>if d == 15 || n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="USAT16_A1, USAT16_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USAT16_A1, USAT16_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USAT16_A1, USAT16_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USAT16_A1, USAT16_T1" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="sat_imm">
        <intro>
          <para>Is the bit position for saturation, in the range 0 to 15, encoded in the "sat_imm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USAT16_A1, USAT16_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/USAT16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    (result1, sat1) = <a link="impl-shared.UnsignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;), saturate_to);</line>
<line>    (result2, sat2) = <a link="impl-shared.UnsignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;), saturate_to);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt; = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(result1, 16);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(result2, 16);</line>
<line>    if sat1 || sat2 then</line>
<line>        PSTATE.Q = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="usax.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="USAX" title="USAX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="USAX" />
  </docvars>
  <heading>USAX</heading>
  <desc>
    <brief>
      <para>Unsigned Subtract and Add with Exchange</para>
    </brief>
    <authored>
      <para>Unsigned Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, and writes the results to the destination register. It sets <xref linkend="BEIDIGBH">PSTATE</xref>.GE according to the results.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="USAX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/USAX/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="USAX_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="USAX" />
        </docvars>
        <asmtemplate><text>USAX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/USAX/A1_A.txt" mylink="aarch32.instrs.USAX.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="USAX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/USAX/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="USAX_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="USAX" />
        </docvars>
        <asmtemplate><text>USAX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/USAX/T1_A.txt" mylink="aarch32.instrs.USAX.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="USAX_A1, USAX_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USAX_A1, USAX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USAX_A1, USAX_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USAX_A1, USAX_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USAX_A1, USAX_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/USAX/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    sum  = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    diff = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = sum&lt;15:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = diff&lt;15:0&gt;;</line>
<line>    PSTATE.GE&lt;1:0&gt; = if sum  &gt;= 0x10000 then '11' else '00';</line>
<line>    PSTATE.GE&lt;3:2&gt; = if diff &gt;= 0 then '11' else '00';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="usub16.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="USUB16" title="USUB16 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="USUB16" />
  </docvars>
  <heading>USUB16</heading>
  <desc>
    <brief>
      <para>Unsigned Subtract 16</para>
    </brief>
    <authored>
      <para>Unsigned Subtract 16 performs two 16-bit unsigned integer subtractions, and writes the results to the destination register. It sets <xref linkend="BEIDIGBH">PSTATE</xref>.GE according to the results of the subtractions.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="USUB16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/USUB16/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="USUB16_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="USUB16" />
        </docvars>
        <asmtemplate><text>USUB16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/USUB16/A1_A.txt" mylink="aarch32.instrs.USUB16.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="USUB16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/USUB16/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="USUB16_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="USUB16" />
        </docvars>
        <asmtemplate><text>USUB16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/USUB16/T1_A.txt" mylink="aarch32.instrs.USUB16.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="USUB16_A1, USUB16_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USUB16_A1, USUB16_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USUB16_A1, USUB16_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USUB16_A1, USUB16_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USUB16_A1, USUB16_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/USUB16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    diff1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:0&gt;);</line>
<line>    diff2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:16&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = diff1&lt;15:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = diff2&lt;15:0&gt;;</line>
<line>    PSTATE.GE&lt;1:0&gt; = if diff1 &gt;= 0 then '11' else '00';</line>
<line>    PSTATE.GE&lt;3:2&gt; = if diff2 &gt;= 0 then '11' else '00';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="usub8.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="USUB8" title="USUB8 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="USUB8" />
  </docvars>
  <heading>USUB8</heading>
  <desc>
    <brief>
      <para>Unsigned Subtract 8</para>
    </brief>
    <authored>
      <para>Unsigned Subtract 8 performs four 8-bit unsigned integer subtractions, and writes the results to the destination register. It sets <xref linkend="BEIDIGBH">PSTATE</xref>.GE according to the results of the subtractions.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="USUB8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/USUB8/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" name="B" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="USUB8_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="USUB8" />
        </docvars>
        <asmtemplate><text>USUB8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/USUB8/A1_A.txt" mylink="aarch32.instrs.USUB8.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="USUB8" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/USUB8/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="H" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="USUB8_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="USUB8" />
        </docvars>
        <asmtemplate><text>USUB8</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/USUB8/T1_A.txt" mylink="aarch32.instrs.USUB8.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="USUB8_A1, USUB8_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USUB8_A1, USUB8_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USUB8_A1, USUB8_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USUB8_A1, USUB8_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="USUB8_A1, USUB8_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/USUB8/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    diff1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;7:0&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;7:0&gt;);</line>
<line>    diff2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:8&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;15:8&gt;);</line>
<line>    diff3 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;23:16&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;23:16&gt;);</line>
<line>    diff4 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:24&gt;) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]&lt;31:24&gt;);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;7:0&gt;   = diff1&lt;7:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:8&gt;  = diff2&lt;7:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;23:16&gt; = diff3&lt;7:0&gt;;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:24&gt; = diff4&lt;7:0&gt;;</line>
<line>    PSTATE.GE&lt;0&gt;  = if diff1 &gt;= 0 then '1' else '0';</line>
<line>    PSTATE.GE&lt;1&gt;  = if diff2 &gt;= 0 then '1' else '0';</line>
<line>    PSTATE.GE&lt;2&gt;  = if diff3 &gt;= 0 then '1' else '0';</line>
<line>    PSTATE.GE&lt;3&gt;  = if diff4 &gt;= 0 then '1' else '0';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="uxtab.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UXTAB" title="UXTAB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UXTAB" />
  </docvars>
  <heading>UXTAB</heading>
  <desc>
    <brief>
      <para>Unsigned Extend and Add Byte</para>
    </brief>
    <authored>
      <para>Unsigned Extend and Add Byte extracts an 8-bit value from a register, zero-extends it to 32 bits, adds the result to the value in another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UXTAB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UXTAB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" width="2" name="op" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UXTAB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UXTAB" />
        </docvars>
        <asmtemplate><text>UXTAB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UXTAB/A1_A.txt" mylink="aarch32.instrs.UXTAB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "UXTB";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UXTAB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UXTAB/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="op1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UXTAB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UXTAB" />
        </docvars>
        <asmtemplate><text>UXTAB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UXTAB/T1_A.txt" mylink="aarch32.instrs.UXTAB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "UXTB";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UXTAB_A1, UXTAB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTAB_A1, UXTAB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTAB_A1, UXTAB_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTAB_A1, UXTAB_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTAB_A1, UXTAB_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTAB_A1, UXTAB_T1" symboldefcount="1">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <definition encodedin="rotate">
        <intro>Is the rotate amount, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">rotate</entry>
                <entry class="symbol">&lt;amount&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">(omitted)</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">24</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UXTAB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    rotated = <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], rotation);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(rotated&lt;7:0&gt;, 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="uxtab16.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UXTAB16" title="UXTAB16 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UXTAB16" />
  </docvars>
  <heading>UXTAB16</heading>
  <desc>
    <brief>
      <para>Unsigned Extend and Add Byte 16</para>
    </brief>
    <authored>
      <para>Unsigned Extend and Add Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, adds the results to two 16-bit values from another register, and writes the final results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UXTAB16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UXTAB16/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" width="2" name="op" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UXTAB16_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UXTAB16" />
        </docvars>
        <asmtemplate><text>UXTAB16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UXTAB16/A1_A.txt" mylink="aarch32.instrs.UXTAB16.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "UXTB16";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UXTAB16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UXTAB16/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="op1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UXTAB16_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UXTAB16" />
        </docvars>
        <asmtemplate><text>UXTAB16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UXTAB16/T1_A.txt" mylink="aarch32.instrs.UXTAB16.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "UXTB16";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UXTAB16_A1, UXTAB16_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTAB16_A1, UXTAB16_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTAB16_A1, UXTAB16_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTAB16_A1, UXTAB16_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTAB16_A1, UXTAB16_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTAB16_A1, UXTAB16_T1" symboldefcount="1">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <definition encodedin="rotate">
        <intro>Is the rotate amount, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">rotate</entry>
                <entry class="symbol">&lt;amount&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">(omitted)</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">24</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UXTAB16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    rotated = <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], rotation);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt; + <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(rotated&lt;7:0&gt;, 16);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt; + <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(rotated&lt;23:16&gt;, 16);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="uxtah.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UXTAH" title="UXTAH -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UXTAH" />
  </docvars>
  <heading>UXTAH</heading>
  <desc>
    <brief>
      <para>Unsigned Extend and Add Halfword</para>
    </brief>
    <authored>
      <para>Unsigned Extend and Add Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, adds the result to a value from another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UXTAH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UXTAH/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" width="2" name="op" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UXTAH_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UXTAH" />
        </docvars>
        <asmtemplate><text>UXTAH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UXTAH/A1_A.txt" mylink="aarch32.instrs.UXTAH.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "UXTH";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UXTAH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UXTAH/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="op1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UXTAH_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UXTAH" />
        </docvars>
        <asmtemplate><text>UXTAH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UXTAH/T1_A.txt" mylink="aarch32.instrs.UXTAH.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Rn == '1111' then SEE "UXTH";</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UXTAH_A1, UXTAH_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTAH_A1, UXTAH_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTAH_A1, UXTAH_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTAH_A1, UXTAH_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTAH_A1, UXTAH_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTAH_A1, UXTAH_T1" symboldefcount="1">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <definition encodedin="rotate">
        <intro>Is the rotate amount, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">rotate</entry>
                <entry class="symbol">&lt;amount&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">(omitted)</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">24</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UXTAH/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    rotated = <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], rotation);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(rotated&lt;15:0&gt;, 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="uxtb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UXTB" title="UXTB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UXTB" />
  </docvars>
  <heading>UXTB</heading>
  <desc>
    <brief>
      <para>Unsigned Extend Byte</para>
    </brief>
    <authored>
      <para>Unsigned Extend Byte extracts an 8-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UXTB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UXTB/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" width="2" name="op" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UXTB_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UXTB" />
        </docvars>
        <asmtemplate><text>UXTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UXTB/A1_A.txt" mylink="aarch32.instrs.UXTB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UXTB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/UXTB/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="B" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="UXTB_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UXTB" />
        </docvars>
        <asmtemplate><text>UXTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UXTB/T1_A.txt" mylink="aarch32.instrs.UXTB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = 0;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UXTB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UXTB/T2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="op1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UXTB_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UXTB" />
        </docvars>
        <asmtemplate comment="&lt;Rd&gt;, &lt;Rm&gt; can be represented in T1"><text>UXTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>UXTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UXTB/T2_A.txt" mylink="aarch32.instrs.UXTB.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UXTB_A1, UXTB_T1, UXTB_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTB_A1, UXTB_T1, UXTB_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTB_A1, UXTB_T1, UXTB_T2" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTB_A1, UXTB_T1, UXTB_T2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTB_A1, UXTB_T2" symboldefcount="1">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <definition encodedin="rotate">
        <intro>Is the rotate amount, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">rotate</entry>
                <entry class="symbol">&lt;amount&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">(omitted)</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">24</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UXTB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    rotated = <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], rotation);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(rotated&lt;7:0&gt;, 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="uxtb16.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UXTB16" title="UXTB16 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UXTB16" />
  </docvars>
  <heading>UXTB16</heading>
  <desc>
    <brief>
      <para>Unsigned Extend Byte 16</para>
    </brief>
    <authored>
      <para>Unsigned Extend Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, and writes the results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UXTB16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UXTB16/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" width="2" name="op" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UXTB16_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UXTB16" />
        </docvars>
        <asmtemplate><text>UXTB16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UXTB16/A1_A.txt" mylink="aarch32.instrs.UXTB16.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UXTB16" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UXTB16/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="op1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UXTB16_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UXTB16" />
        </docvars>
        <asmtemplate><text>UXTB16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UXTB16/T1_A.txt" mylink="aarch32.instrs.UXTB16.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UXTB16_A1, UXTB16_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTB16_A1, UXTB16_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTB16_A1, UXTB16_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTB16_A1" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTB16_T1" symboldefcount="2">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTB16_A1, UXTB16_T1" symboldefcount="1">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <definition encodedin="rotate">
        <intro>Is the rotate amount, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">rotate</entry>
                <entry class="symbol">&lt;amount&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">(omitted)</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">24</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UXTB16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    rotated = <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], rotation);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;15:0&gt;  = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(rotated&lt;7:0&gt;, 16);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;31:16&gt; = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(rotated&lt;23:16&gt;, 16);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="uxth.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="UXTH" title="UXTH -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="UXTH" />
  </docvars>
  <heading>UXTH</heading>
  <desc>
    <brief>
      <para>Unsigned Extend Halfword</para>
    </brief>
    <authored>
      <para>Unsigned Extend Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="UXTH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/UXTH/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" width="2" name="op" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UXTH_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="UXTH" />
        </docvars>
        <asmtemplate><text>UXTH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UXTH/A1_A.txt" mylink="aarch32.instrs.UXTH.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UXTH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/UXTH/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="3" name="Rm" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rd" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="UXTH_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UXTH" />
        </docvars>
        <asmtemplate><text>UXTH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UXTH/T1_A.txt" mylink="aarch32.instrs.UXTH.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = 0;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="UXTH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/UXTH/T2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="op1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" width="2" name="rotate" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="UXTH_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="UXTH" />
        </docvars>
        <asmtemplate comment="&lt;Rd&gt;, &lt;Rm&gt; can be represented in T1"><text>UXTH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>UXTH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rm" hover="General-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, ROR #</text><a link="sa_amount" hover="Rotate amount (field &quot;rotate&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/UXTH/T2_A.txt" mylink="aarch32.instrs.UXTH.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  rotation = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(rotate:'000');</line>
<line>if d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="UXTH_A1, UXTH_T1, UXTH_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTH_A1, UXTH_T1, UXTH_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTH_A1, UXTH_T1, UXTH_T2" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTH_A1, UXTH_T1, UXTH_T2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="UXTH_A1, UXTH_T2" symboldefcount="1">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <definition encodedin="rotate">
        <intro>Is the rotate amount, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">rotate</entry>
                <entry class="symbol">&lt;amount&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">(omitted)</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">24</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/UXTH/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    rotated = <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], rotation);</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(rotated&lt;15:0&gt;, 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vaba.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VABA" title="VABA -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VABA" />
  </docvars>
  <heading>VABA</heading>
  <desc>
    <brief>
      <para>Vector Absolute Difference and Accumulate</para>
    </brief>
    <authored>
      <para>Vector Absolute Difference and Accumulate subtracts the elements of one vector from the corresponding elements of another vector, and accumulates the absolute values of the results into the elements of the destination vector.</para>
      <para>Operand and result elements are all integers of the same length.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VABA" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VABA/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VABA_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VABA" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VABA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VABA_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VABA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VABA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VABA/T1A1_A.txt" mylink="aarch32.instrs.VABA.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');  long_destination = FALSE;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VABA" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VABA/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VABA_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VABA" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VABA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VABA_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VABA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VABA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VABA/T1A1_A.txt" mylink="aarch32.instrs.VABA.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');  long_destination = FALSE;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VABA_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABA_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABA_A1_Q, VABA_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABA_A1_Q, VABA_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VABA_A1_Q, VABA_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABA_A1_Q, VABA_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABA_A1_Q, VABA_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABA_A1_D, VABA_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABA_A1_D, VABA_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABA_A1_D, VABA_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VABA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r],e,esize];</line>
<line>            op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m+r],e,esize];</line>
<line>            absdiff = <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(<a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op1,unsigned) - <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op2,unsigned));</line>
<line>            if long_destination then</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[d&gt;&gt;1],e,2*esize] + absdiff;</line>
<line>            else</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r],e,esize] + absdiff;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vabal.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VABAL" title="VABAL -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VABAL" />
  </docvars>
  <heading>VABAL</heading>
  <desc>
    <brief>
      <para>Vector Absolute Difference and Accumulate Long</para>
    </brief>
    <authored>
      <para>Vector Absolute Difference and Accumulate Long subtracts the elements of one vector from the corresponding elements of another vector, and accumulates the absolute values of the results into the elements of the destination vector.</para>
      <para>Operand elements are all integers of the same length, and the result elements are double the length of the operands.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VABAL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VABA/T2A2_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VABAL_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VABAL" />
        </docvars>
        <asmtemplate><text>VABAL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VABA/T2A2_A.txt" mylink="aarch32.instrs.VABA.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>unsigned = (U == '1');  long_destination = TRUE;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VABAL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VABA/T2A2_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VABAL_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VABAL" />
        </docvars>
        <asmtemplate><text>VABAL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VABA/T2A2_A.txt" mylink="aarch32.instrs.VABA.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>unsigned = (U == '1');  long_destination = TRUE;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VABAL_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABAL_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABAL_A1, VABAL_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABAL_A1, VABAL_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VABAL_A1, VABAL_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABAL_A1, VABAL_T1" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABAL_A1, VABAL_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VABA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r],e,esize];</line>
<line>            op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m+r],e,esize];</line>
<line>            absdiff = <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(<a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op1,unsigned) - <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op2,unsigned));</line>
<line>            if long_destination then</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[d&gt;&gt;1],e,2*esize] + absdiff;</line>
<line>            else</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r],e,esize] + absdiff;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vabd_f.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VABD_f" title="VABD (floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VABD" />
  </docvars>
  <heading>VABD (floating-point)</heading>
  <desc>
    <brief>
      <para>Vector Absolute Difference (floating-point)</para>
    </brief>
    <authored>
      <para>Vector Absolute Difference (floating-point) subtracts the elements of one vector from the corresponding elements of another vector, and places the absolute values of the results in the elements of the destination vector.</para>
      <para>Operand and result elements are floating-point numbers of the same size.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VABD" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VABD_f/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VABD_f_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VABD" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VABD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VABD_f_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VABD" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VABD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VABD_f/A1_A.txt" mylink="aarch32.instrs.VABD_f.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VABD" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VABD_f/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VABD_f_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VABD" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VABD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VABD_f_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VABD" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VABD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VABD_f/T1_A.txt" mylink="aarch32.instrs.VABD_f.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>sz == '1' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VABD_f_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABD_f_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABD_f_A1_Q, VABD_f_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABD_f_A1_Q, VABD_f_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VABD_f_A1_Q, VABD_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABD_f_A1_Q, VABD_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABD_f_A1_Q, VABD_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABD_f_A1_D, VABD_f_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABD_f_A1_D, VABD_f_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABD_f_A1_D, VABD_f_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VABD_f/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize];  op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize];</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPAbs.1" file="shared_pseudocode.xml" hover="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(<a link="impl-shared.FPSub.3" file="shared_pseudocode.xml" hover="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPSub</a>(op1,op2,<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>()));</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vabd_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VABD_i" title="VABD (integer) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VABD" />
  </docvars>
  <heading>VABD (integer)</heading>
  <desc>
    <brief>
      <para>Vector Absolute Difference (integer)</para>
    </brief>
    <authored>
      <para>Vector Absolute Difference (integer) subtracts the elements of one vector from the corresponding elements of another vector, and places the absolute values of the results in the elements of the destination vector.</para>
      <para>Operand and result elements are all integers of the same length.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VABD" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VABD_i/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VABD_i_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VABD" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VABD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VABD_i_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VABD" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VABD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VABD_i/T1A1_A.txt" mylink="aarch32.instrs.VABD_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');  long_destination = FALSE;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VABD" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VABD_i/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VABD_i_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VABD" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VABD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VABD_i_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VABD" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VABD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VABD_i/T1A1_A.txt" mylink="aarch32.instrs.VABD_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');  long_destination = FALSE;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VABD_i_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABD_i_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABD_i_A1_Q, VABD_i_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABD_i_A1_Q, VABD_i_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VABD_i_A1_Q, VABD_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABD_i_A1_Q, VABD_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABD_i_A1_Q, VABD_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABD_i_A1_D, VABD_i_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABD_i_A1_D, VABD_i_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABD_i_A1_D, VABD_i_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VABD_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r],e,esize];</line>
<line>            op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m+r],e,esize];</line>
<line>            absdiff = <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(<a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op1,unsigned) - <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op2,unsigned));</line>
<line>            if long_destination then</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = absdiff&lt;2*esize-1:0&gt;;</line>
<line>            else</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = absdiff&lt;esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vabdl_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VABDL_i" title="VABDL (integer) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VABDL" />
  </docvars>
  <heading>VABDL (integer)</heading>
  <desc>
    <brief>
      <para>Vector Absolute Difference Long (integer)</para>
    </brief>
    <authored>
      <para>Vector Absolute Difference Long (integer) subtracts the elements of one vector from the corresponding elements of another vector, and places the absolute values of the results in the elements of the destination vector.</para>
      <para>Operand elements are all integers of the same length, and the result elements are double the length of the operands.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VABDL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VABD_i/T2A2_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VABDL_i_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VABDL" />
        </docvars>
        <asmtemplate><text>VABDL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VABD_i/T2A2_A.txt" mylink="aarch32.instrs.VABD_i.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>unsigned = (U == '1');  long_destination = TRUE;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VABDL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VABD_i/T2A2_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VABDL_i_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VABDL" />
        </docvars>
        <asmtemplate><text>VABDL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VABD_i/T2A2_A.txt" mylink="aarch32.instrs.VABD_i.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>unsigned = (U == '1');  long_destination = TRUE;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VABDL_i_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABDL_i_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABDL_i_A1, VABDL_i_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABDL_i_A1, VABDL_i_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VABDL_i_A1, VABDL_i_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABDL_i_A1, VABDL_i_T1" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABDL_i_A1, VABDL_i_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VABD_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r],e,esize];</line>
<line>            op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m+r],e,esize];</line>
<line>            absdiff = <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(<a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op1,unsigned) - <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op2,unsigned));</line>
<line>            if long_destination then</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = absdiff&lt;2*esize-1:0&gt;;</line>
<line>            else</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = absdiff&lt;esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vabs.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VABS" title="VABS -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VABS" />
  </docvars>
  <heading>VABS</heading>
  <desc>
    <brief>
      <para>Vector Absolute</para>
    </brief>
    <authored>
      <para>Vector Absolute takes the absolute value of each element in a vector, and places the results in a second vector. The floating-point version only clears the sign bit.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check and is operating only on integer vector elements, then the following apply:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VABS" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VABS/A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="9" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VABS_A1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VABS" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VABS</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;F:size&quot;) [F16,F32,S8,S16,S32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VABS_A1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VABS" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VABS</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;F:size&quot;) [F16,F32,S8,S16,S32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VABS/A1_A.txt" mylink="aarch32.instrs.VABS.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; ((size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size == '00') then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>advsimd = TRUE;  floating_point = (F == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VABS" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VABS/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="o3" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VABS_A2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VABS" />
          <docvar key="mnemonic-fpdatasize" value="VABS-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VABS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VABS_A2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VABS" />
          <docvar key="mnemonic-fpdatasize" value="VABS-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VABS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VABS_A2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VABS" />
          <docvar key="mnemonic-fpdatasize" value="VABS-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VABS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VABS/A2_A.txt" mylink="aarch32.instrs.VABS.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>advsimd = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VABS" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VABS/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="9" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VABS_T1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VABS" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VABS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;F:size&quot;) [F16,F32,S8,S16,S32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VABS_T1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VABS" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VABS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;F:size&quot;) [F16,F32,S8,S16,S32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VABS/T1_A.txt" mylink="aarch32.instrs.VABS.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; ((size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size == '00') then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>advsimd = TRUE;  floating_point = (F == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>F == '1' &amp;&amp; size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VABS" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VABS/T2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="o3" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VABS_T2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VABS" />
          <docvar key="mnemonic-fpdatasize" value="VABS-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VABS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VABS_T2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VABS" />
          <docvar key="mnemonic-fpdatasize" value="VABS-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VABS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VABS_T2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VABS" />
          <docvar key="mnemonic-fpdatasize" value="VABS-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VABS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VABS/T2_A.txt" mylink="aarch32.instrs.VABS.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>advsimd = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VABS_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABS_A2_H, VABS_T1_Q, VABS_T2_H" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For encoding A2, T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABS_A1_Q, VABS_A2_H, VABS_T1_Q, VABS_T2_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABS_A1_Q, VABS_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="F:size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">F</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VABS_A1_Q, VABS_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABS_A1_Q, VABS_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABS_A1_D, VABS_A2_D, VABS_T1_D, VABS_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABS_A1_D, VABS_A2_D, VABS_T1_D, VABS_T2_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABS_A2_H, VABS_T2_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VABS_A2_H, VABS_T2_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VABS/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDOrVFPEnabled.2" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDOrVFPEnabled(boolean include_fpexc_check, boolean advsimd)">CheckAdvSIMDOrVFPEnabled</a>(TRUE, advsimd);</line>
<line>    if advsimd then  // Advanced SIMD instruction</line>
<line>        for r = 0 to regs-1</line>
<line>            for e = 0 to elements-1</line>
<line>                if floating_point then</line>
<line>                    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPAbs.1" file="shared_pseudocode.xml" hover="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize]);</line>
<line>                else</line>
<line>                    result = <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize]));</line>
<line>                    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result&lt;esize-1:0&gt;;</line>
<line>    else             // VFP instruction</line>
<line>        case esize of</line>
<line>            when 16 <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPAbs.1" file="shared_pseudocode.xml" hover="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;);</line>
<line>            when 32 <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPAbs.1" file="shared_pseudocode.xml" hover="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]);</line>
<line>            when 64 <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPAbs.1" file="shared_pseudocode.xml" hover="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vacge.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VACGE" title="VACGE -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VACGE" />
  </docvars>
  <heading>VACGE</heading>
  <desc>
    <brief>
      <para>Vector Absolute Compare Greater Than or Equal</para>
    </brief>
    <authored>
      <para>Vector Absolute Compare Greater Than or Equal takes the absolute value of each element in a vector, and compares it with the absolute value of the corresponding element of a second vector. If the first is greater than or equal to the second, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.</para>
      <para>The operands and result can be quadword or doubleword vectors.  They must all be the same size.</para>
      <para>The operand vector elements are floating-point numbers. The result vector elements are the same size as the operand vector elements.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="1">
    <alias_list_intro>This instruction is used by the alias </alias_list_intro>
    <aliasref aliaspageid="VACLE_VACGE" aliasfile="vacle_vacge.xml" hover="Vector Absolute Compare Less Than or Equal" punct=".">
      <text>VACLE</text>
      <aliaspref>Never</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink />
      <text> below for details of when the alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VACGE" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VACGE/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VACGE_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VACGE" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VACGE</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VACGE_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VACGE" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VACGE</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VACGE/A1_A.txt" mylink="aarch32.instrs.VACGE.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>or_equal = (op == '0');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VACGE" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VACGE/T1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VACGE_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VACGE" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VACGE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VACGE_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VACGE" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VACGE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VACGE/T1_A.txt" mylink="aarch32.instrs.VACGE.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>or_equal = (op == '0');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>sz == '1' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VACGE_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACGE_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACGE_A1_Q, VACGE_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACGE_A1_Q, VACGE_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VACGE_A1_Q, VACGE_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACGE_A1_Q, VACGE_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACGE_A1_Q, VACGE_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACGE_A1_D, VACGE_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACGE_A1_D, VACGE_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACGE_A1_D, VACGE_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VACGE/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.FPAbs.1" file="shared_pseudocode.xml" hover="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize]);  op2 = <a link="impl-shared.FPAbs.1" file="shared_pseudocode.xml" hover="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize]);</line>
<line>            boolean test_passed;</line>
<line>            if or_equal then</line>
<line>                test_passed = <a link="impl-shared.FPCompareGE.3" file="shared_pseudocode.xml" hover="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(op1, op2, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            else</line>
<line>                test_passed = <a link="impl-shared.FPCompareGT.3" file="shared_pseudocode.xml" hover="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(op1, op2, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = if test_passed then <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(esize) else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(esize);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vacgt.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VACGT" title="VACGT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VACGT" />
  </docvars>
  <heading>VACGT</heading>
  <desc>
    <brief>
      <para>Vector Absolute Compare Greater Than</para>
    </brief>
    <authored>
      <para>Vector Absolute Compare Greater Than takes the absolute value of each element in a vector, and compares it with the absolute value of the corresponding element of a second vector. If the first is greater than the second, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.</para>
      <para>The operands and result can be quadword or doubleword vectors.  They must all be the same size.</para>
      <para>The operand vector elements are floating-point numbers. The result vector elements are the same size as the operand vector elements.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="1">
    <alias_list_intro>This instruction is used by the alias </alias_list_intro>
    <aliasref aliaspageid="VACLT_VACGT" aliasfile="vaclt_vacgt.xml" hover="Vector Absolute Compare Less Than" punct=".">
      <text>VACLT</text>
      <aliaspref>Never</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink />
      <text> below for details of when the alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VACGT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VACGE/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VACGT_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VACGT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VACGT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VACGT_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VACGT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VACGT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VACGE/A1_A.txt" mylink="aarch32.instrs.VACGE.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>or_equal = (op == '0');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VACGT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VACGE/T1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VACGT_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VACGT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VACGT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VACGT_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VACGT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VACGT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VACGE/T1_A.txt" mylink="aarch32.instrs.VACGE.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>or_equal = (op == '0');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>sz == '1' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VACGT_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACGT_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACGT_A1_Q, VACGT_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACGT_A1_Q, VACGT_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VACGT_A1_Q, VACGT_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACGT_A1_Q, VACGT_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACGT_A1_Q, VACGT_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACGT_A1_D, VACGT_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACGT_A1_D, VACGT_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACGT_A1_D, VACGT_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VACGE/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.FPAbs.1" file="shared_pseudocode.xml" hover="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize]);  op2 = <a link="impl-shared.FPAbs.1" file="shared_pseudocode.xml" hover="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize]);</line>
<line>            boolean test_passed;</line>
<line>            if or_equal then</line>
<line>                test_passed = <a link="impl-shared.FPCompareGE.3" file="shared_pseudocode.xml" hover="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(op1, op2, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            else</line>
<line>                test_passed = <a link="impl-shared.FPCompareGT.3" file="shared_pseudocode.xml" hover="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(op1, op2, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = if test_passed then <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(esize) else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(esize);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vacle_vacge.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VACLE_VACGE" title="VACLE -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="VACLE" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VACGE" />
  </docvars>
  <heading>VACLE</heading>
  <desc>
    <brief>
      <para>Vector Absolute Compare Less Than or Equal</para>
    </brief>
    <authored>
      <para>Vector Absolute Compare Less Than or Equal takes the absolute value of each element in a vector, and compares it with the absolute value of the corresponding element of a second vector. If the first is less than or equal to the second, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>The description of <xref>VACGE</xref> gives the operational pseudocode for this instruction.</para>
  </operationalnotes>
  <aliasto refiform="vacge.xml" iformid="VACGE">VACGE</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VACGE" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VACLE_VACGE_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VACLE" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VACGE" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VACLE</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vacge.xml#VACGE_A1_D">VACGE</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VACLE_VACGE_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VACLE" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VACGE" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VACLE</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vacge.xml#VACGE_A1_Q">VACGE</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VACGE" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VACLE_VACGE_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VACLE" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VACGE" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VACLE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vacge.xml#VACGE_T1_D">VACGE</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VACLE_VACGE_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VACLE" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VACGE" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VACLE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vacge.xml#VACGE_T1_Q">VACGE</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VACLE_VACGE_A1_D, VACLE_VACGE_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACLE_VACGE_A1_D, VACLE_VACGE_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACLE_VACGE_A1_Q, VACLE_VACGE_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACLE_VACGE_A1_Q, VACLE_VACGE_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACLE_VACGE_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACLE_VACGE_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACLE_VACGE_A1_Q, VACLE_VACGE_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACLE_VACGE_A1_Q, VACLE_VACGE_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VACLE_VACGE_A1_Q, VACLE_VACGE_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACLE_VACGE_A1_D, VACLE_VACGE_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="vaclt_vacgt.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VACLT_VACGT" title="VACLT -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="VACLT" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VACGT" />
  </docvars>
  <heading>VACLT</heading>
  <desc>
    <brief>
      <para>Vector Absolute Compare Less Than</para>
    </brief>
    <authored>
      <para>Vector Absolute Compare Less Than takes the absolute value of each element in a vector, and compares it with the absolute value of the corresponding element of a second vector. If the first is less than the second, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>The description of <xref>VACGT</xref> gives the operational pseudocode for this instruction.</para>
  </operationalnotes>
  <aliasto refiform="vacgt.xml" iformid="VACGT">VACGT</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VACGT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VACLT_VACGT_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VACLT" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VACGT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VACLT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vacgt.xml#VACGT_A1_D">VACGT</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VACLT_VACGT_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VACLT" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VACGT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VACLT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vacgt.xml#VACGT_A1_Q">VACGT</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VACGT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VACLT_VACGT_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VACLT" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VACGT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VACLT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vacgt.xml#VACGT_T1_D">VACGT</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VACLT_VACGT_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VACLT" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VACGT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VACLT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vacgt.xml#VACGT_T1_Q">VACGT</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VACLT_VACGT_A1_D, VACLT_VACGT_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACLT_VACGT_A1_D, VACLT_VACGT_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACLT_VACGT_A1_Q, VACLT_VACGT_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACLT_VACGT_A1_Q, VACLT_VACGT_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACLT_VACGT_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACLT_VACGT_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACLT_VACGT_A1_Q, VACLT_VACGT_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACLT_VACGT_A1_Q, VACLT_VACGT_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VACLT_VACGT_A1_Q, VACLT_VACGT_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VACLT_VACGT_A1_D, VACLT_VACGT_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="vadd_f.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VADD_f" title="VADD (floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VADD" />
  </docvars>
  <heading>VADD (floating-point)</heading>
  <desc>
    <brief>
      <para>Vector Add (floating-point)</para>
    </brief>
    <authored>
      <para>Vector Add (floating-point) adds corresponding elements in two vectors, and places the results in the destination vector.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VADD" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VADD_f/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VADD_f_A1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VADD" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VADD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VADD_f_A1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VADD" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VADD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VADD_f/A1_A.txt" mylink="aarch32.instrs.VADD_f.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>advsimd = TRUE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VADD" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VADD_f/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VADD_f_A2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VADD" />
          <docvar key="mnemonic-fpdatasize" value="VADD-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><text>{</text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VADD_f_A2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VADD" />
          <docvar key="mnemonic-fpdatasize" value="VADD-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><text>{</text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VADD_f_A2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VADD" />
          <docvar key="mnemonic-fpdatasize" value="VADD-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VADD_f/A2_A.txt" mylink="aarch32.instrs.VADD_f.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>advsimd = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VADD" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VADD_f/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VADD_f_T1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VADD" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VADD_f_T1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VADD" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VADD_f/T1_A.txt" mylink="aarch32.instrs.VADD_f.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>advsimd = TRUE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>sz == '1' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VADD" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VADD_f/T2_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VADD_f_T2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VADD" />
          <docvar key="mnemonic-fpdatasize" value="VADD-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><text>{</text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VADD_f_T2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VADD" />
          <docvar key="mnemonic-fpdatasize" value="VADD-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><text>{</text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VADD_f_T2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VADD" />
          <docvar key="mnemonic-fpdatasize" value="VADD-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VADD_f/T2_A.txt" mylink="aarch32.instrs.VADD_f.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>advsimd = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VADD_f_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADD_f_A2_H, VADD_f_T1_Q, VADD_f_T2_H" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For encoding A2, T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADD_f_A1_Q, VADD_f_A2_H, VADD_f_T1_Q, VADD_f_T2_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADD_f_A1_Q, VADD_f_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VADD_f_A1_Q, VADD_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADD_f_A1_Q, VADD_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADD_f_A1_Q, VADD_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADD_f_A1_D, VADD_f_A2_D, VADD_f_T1_D, VADD_f_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADD_f_A1_D, VADD_f_A2_D, VADD_f_T1_D, VADD_f_T2_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADD_f_A1_D, VADD_f_A2_D, VADD_f_T1_D, VADD_f_T2_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADD_f_A2_H, VADD_f_T2_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADD_f_A2_H, VADD_f_T2_H" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADD_f_A2_H, VADD_f_T2_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VADD_f/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDOrVFPEnabled.2" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDOrVFPEnabled(boolean include_fpexc_check, boolean advsimd)">CheckAdvSIMDOrVFPEnabled</a>(TRUE, advsimd);</line>
<line>    if advsimd then  // Advanced SIMD instruction</line>
<line>        for r = 0 to regs-1</line>
<line>            for e = 0 to elements-1</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize], <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize],</line>
<line>                                             <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>    else             // VFP instruction</line>
<line>        case esize of</line>
<line>            when 16</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[]);</line>
<line>            when 32</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n], <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[]);</line>
<line>            when 64</line>
<line>                <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n], <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vadd_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VADD_i" title="VADD (integer) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VADD" />
  </docvars>
  <heading>VADD (integer)</heading>
  <desc>
    <brief>
      <para>Vector Add (integer)</para>
    </brief>
    <authored>
      <para>Vector Add (integer) adds corresponding elements in two vectors, and places the results in the destination vector.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VADD" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VADD_i/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VADD_i_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VADD" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VADD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;) [I8,I16,I32,I64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VADD_i_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VADD" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VADD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;) [I8,I16,I32,I64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VADD_i/T1A1_A.txt" mylink="aarch32.instrs.VADD_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VADD" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VADD_i/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VADD_i_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VADD" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;) [I8,I16,I32,I64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VADD_i_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VADD" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;) [I8,I16,I32,I64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VADD_i/T1A1_A.txt" mylink="aarch32.instrs.VADD_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VADD_i_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADD_i_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADD_i_A1_Q, VADD_i_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADD_i_A1_Q, VADD_i_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">I8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">I16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">I32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">I64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VADD_i_A1_Q, VADD_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADD_i_A1_Q, VADD_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADD_i_A1_Q, VADD_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADD_i_A1_D, VADD_i_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADD_i_A1_D, VADD_i_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADD_i_A1_D, VADD_i_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VADD_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize] + <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize];</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vaddhn.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VADDHN" title="VADDHN -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VADDHN" />
  </docvars>
  <heading>VADDHN</heading>
  <desc>
    <brief>
      <para>Vector Add and Narrow, returning High Half</para>
    </brief>
    <authored>
      <para>Vector Add and Narrow, returning High Half adds corresponding elements in two quadword vectors, and places the most significant half of each result in a doubleword vector. The results are truncated. For rounded results, see <xref linkend="A32T32-fpsimd.instructions.VRADDHN">VRADDHN</xref>.</para>
      <para>The operand elements can be 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and unsigned integers.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VADDHN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VADDHN/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VADDHN_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VADDHN" />
        </docvars>
        <asmtemplate><text>VADDHN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VADDHN/T1A1_A.txt" mylink="aarch32.instrs.VADDHN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VADDHN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VADDHN/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VADDHN_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VADDHN" />
        </docvars>
        <asmtemplate><text>VADDHN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VADDHN/T1A1_A.txt" mylink="aarch32.instrs.VADDHN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VADDHN_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADDHN_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADDHN_A1, VADDHN_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADDHN_A1, VADDHN_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">I16</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">I32</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">I64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VADDHN_A1, VADDHN_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADDHN_A1, VADDHN_T1" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADDHN_A1, VADDHN_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VADDHN/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for e = 0 to elements-1</line>
<line>        result = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[n&gt;&gt;1],e,2*esize] + <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[m&gt;&gt;1],e,2*esize];</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d],e,esize] = result&lt;2*esize-1:esize&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vaddl.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VADDL" title="VADDL -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VADDL" />
  </docvars>
  <heading>VADDL</heading>
  <desc>
    <brief>
      <para>Vector Add Long</para>
    </brief>
    <authored>
      <para>Vector Add Long adds corresponding elements in two doubleword vectors, and places the results in a quadword vector. Before adding, it sign-extends or zero-extends the elements of both operands.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VADDL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VADDL/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="8" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VADDL_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VADDL" />
        </docvars>
        <asmtemplate><text>VADDL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of second operand vector (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VADDL/T1A1_A.txt" mylink="aarch32.instrs.VADDL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vd&lt;0&gt; == '1' || (op == '1' &amp;&amp; Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;  is_vaddw = (op == '1');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VADDL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VADDL/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="8" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VADDL_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VADDL" />
        </docvars>
        <asmtemplate><text>VADDL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of second operand vector (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VADDL/T1A1_A.txt" mylink="aarch32.instrs.VADDL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vd&lt;0&gt; == '1' || (op == '1' &amp;&amp; Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;  is_vaddw = (op == '1');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VADDL_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADDL_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADDL_A1, VADDL_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADDL_A1, VADDL_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the second operand vector, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VADDL_A1, VADDL_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADDL_A1, VADDL_T1" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADDL_A1, VADDL_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VADDL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for e = 0 to elements-1</line>
<line>        integer op1;</line>
<line>        if is_vaddw then</line>
<line>            op1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[n&gt;&gt;1],e,2*esize], unsigned);</line>
<line>        else</line>
<line>            op1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n],e,esize], unsigned);</line>
<line>        result = op1 + <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m],e,esize],unsigned);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = result&lt;2*esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vaddw.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VADDW" title="VADDW -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VADDW" />
  </docvars>
  <heading>VADDW</heading>
  <desc>
    <brief>
      <para>Vector Add Wide</para>
    </brief>
    <authored>
      <para>Vector Add Wide adds corresponding elements in one quadword and one doubleword vector, and places the results in a quadword vector. Before adding, it sign-extends or zero-extends the elements of the doubleword operand.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VADDW" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VADDL/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="8" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VADDW_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VADDW" />
        </docvars>
        <asmtemplate><text>VADDW</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of second operand vector (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VADDL/T1A1_A.txt" mylink="aarch32.instrs.VADDL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vd&lt;0&gt; == '1' || (op == '1' &amp;&amp; Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;  is_vaddw = (op == '1');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VADDW" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VADDL/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="8" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VADDW_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VADDW" />
        </docvars>
        <asmtemplate><text>VADDW</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of second operand vector (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VADDL/T1A1_A.txt" mylink="aarch32.instrs.VADDL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vd&lt;0&gt; == '1' || (op == '1' &amp;&amp; Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;  is_vaddw = (op == '1');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VADDW_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADDW_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADDW_A1, VADDW_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADDW_A1, VADDW_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the second operand vector, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VADDW_A1, VADDW_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADDW_A1, VADDW_T1" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VADDW_A1, VADDW_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VADDL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for e = 0 to elements-1</line>
<line>        integer op1;</line>
<line>        if is_vaddw then</line>
<line>            op1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[n&gt;&gt;1],e,2*esize], unsigned);</line>
<line>        else</line>
<line>            op1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n],e,esize], unsigned);</line>
<line>        result = op1 + <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m],e,esize],unsigned);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = result&lt;2*esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vand_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VAND_r" title="VAND (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VAND" />
  </docvars>
  <heading>VAND (register)</heading>
  <desc>
    <brief>
      <para>Vector Bitwise AND (register)</para>
    </brief>
    <authored>
      <para>Vector Bitwise AND (register) performs a bitwise AND operation between two registers, and places the result in the destination register.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VAND" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VAND_r/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VAND_r_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VAND" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VAND</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VAND_r_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VAND" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VAND</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VAND_r/T1A1_A.txt" mylink="aarch32.instrs.VAND_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VAND" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VAND_r/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VAND_r_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VAND" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VAND</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VAND_r_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VAND" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VAND</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VAND_r/T1A1_A.txt" mylink="aarch32.instrs.VAND_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VAND_r_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VAND_r_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VAND_r_A1_Q, VAND_r_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VAND_r_A1_Q, VAND_r_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>An optional data type. It is ignored by assemblers, and does not affect the encoding.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VAND_r_A1_Q, VAND_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VAND_r_A1_Q, VAND_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VAND_r_A1_Q, VAND_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VAND_r_A1_D, VAND_r_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VAND_r_A1_D, VAND_r_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VAND_r_A1_D, VAND_r_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VAND_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r] AND <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r];</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vand_vbic_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VAND_VBIC_i" title="VAND (immediate) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="VAND" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VBIC" />
  </docvars>
  <heading>VAND (immediate)</heading>
  <desc>
    <brief>Vector Bitwise AND (immediate)</brief>
    <longer> performs a bitwise AND between a register value and an immediate value, and returns the result into the destination vector</longer>
  </desc>
  <aliasto refiform="vbic_i.xml" iformid="VBIC_i">VBIC (immediate)</aliasto>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VBIC" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="2">
          <c>0</c>
          <c>x</c>
          <c>x</c>
          <c>1</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VAND_VBIC_i_A1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VAND" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VBIC" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VAND</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vbic_i.xml#VBIC_i_A1_D">VBIC</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #~</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VAND_VBIC_i_A1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VAND" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VBIC" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VAND</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vbic_i.xml#VBIC_i_A1_Q">VBIC</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #~</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VBIC" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>x</c>
          <c>1</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VAND_VBIC_i_A2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VAND" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VBIC" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VAND</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vbic_i.xml#VBIC_i_A2_D">VBIC</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #~</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VAND_VBIC_i_A2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VAND" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VBIC" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VAND</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vbic_i.xml#VBIC_i_A2_Q">VBIC</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #~</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VBIC" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="2">
          <c>0</c>
          <c>x</c>
          <c>x</c>
          <c>1</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VAND_VBIC_i_T1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VAND" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VBIC" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VAND</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vbic_i.xml#VBIC_i_T1_D">VBIC</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #~</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VAND_VBIC_i_T1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VAND" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VBIC" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VAND</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vbic_i.xml#VBIC_i_T1_Q">VBIC</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #~</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VBIC" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>x</c>
          <c>1</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VAND_VBIC_i_T2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VAND" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VBIC" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VAND</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vbic_i.xml#VBIC_i_T2_D">VBIC</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #~</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VAND_VBIC_i_T2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VAND" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VBIC" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VAND</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vbic_i.xml#VBIC_i_T2_Q">VBIC</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #~</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VAND_VBIC_i_A1_Q, VAND_VBIC_i_A2_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For encoding A1 and A2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VAND_VBIC_i_T1_Q, VAND_VBIC_i_T2_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VAND_VBIC_i_A1_Q, VAND_VBIC_i_A2_Q, VAND_VBIC_i_T1_Q, VAND_VBIC_i_T2_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VAND_VBIC_i_A1_Q, VAND_VBIC_i_A2_Q, VAND_VBIC_i_T1_Q, VAND_VBIC_i_T2_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VAND_VBIC_i_A1_D, VAND_VBIC_i_A2_D, VAND_VBIC_i_T1_D, VAND_VBIC_i_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VAND_VBIC_i_A1_Q, VAND_VBIC_i_A2_Q, VAND_VBIC_i_T1_Q, VAND_VBIC_i_T2_Q" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is a constant of the specified type that is replicated to fill the destination register. For details of the range of constants available and the encoding of <syntax>&lt;imm&gt;</syntax>, see <xref linkend="CJAIDJDJ">Modified immediate constants in T32 and A32 Advanced SIMD instructions</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="vbic_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VBIC_i" title="VBIC (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VBIC" />
  </docvars>
  <heading>VBIC (immediate)</heading>
  <desc>
    <brief>
      <para>Vector Bitwise Bit Clear (immediate)</para>
    </brief>
    <authored>
      <para>Vector Bitwise Bit Clear (immediate) performs a bitwise AND between a register value and the complement of an immediate value, and returns the result into the destination vector.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_1r_imm">Advanced SIMD one register and modified immediate</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd1reg_imm">Advanced SIMD one register and modified immediate</xref> for the A32 instruction set.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>The I8, I64, and F32 data types are permitted as pseudo-instructions, if the immediate can be represented by this instruction, and are encoded using a permitted encoding of the I16 or I32 data type.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="1">
    <alias_list_intro>This instruction is used by the alias </alias_list_intro>
    <aliasref aliaspageid="VAND_VBIC_i" aliasfile="vand_vbic_i.xml" hover="Vector Bitwise AND (immediate)" punct=".">
      <text>VAND (immediate)</text>
      <aliaspref>Never</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink />
      <text> below for details of when the alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VBIC" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VBIC_i/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="2">
          <c>0</c>
          <c>x</c>
          <c>x</c>
          <c>1</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VBIC_i_A1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VBIC" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VBIC</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VBIC_i_A1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VBIC" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VBIC</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VBIC_i/T1A1_A.txt" mylink="aarch32.instrs.VBIC_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if cmode&lt;0&gt; == '0' || cmode&lt;3:2&gt; == '11' then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>('1', cmode, i:imm3:imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VBIC" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VBIC_i/T2A2_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>x</c>
          <c>1</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VBIC_i_A2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VBIC" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VBIC</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VBIC_i_A2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VBIC" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VBIC</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VBIC_i/T2A2_A.txt" mylink="aarch32.instrs.VBIC_i.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if cmode&lt;0&gt; == '0' || cmode&lt;3:2&gt; == '11' then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>('1', cmode, i:imm3:imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VBIC" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VBIC_i/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="2">
          <c>0</c>
          <c>x</c>
          <c>x</c>
          <c>1</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VBIC_i_T1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VBIC" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VBIC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VBIC_i_T1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VBIC" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VBIC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VBIC_i/T1A1_A.txt" mylink="aarch32.instrs.VBIC_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if cmode&lt;0&gt; == '0' || cmode&lt;3:2&gt; == '11' then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>('1', cmode, i:imm3:imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VBIC" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VBIC_i/T2A2_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>x</c>
          <c>1</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VBIC_i_T2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VBIC" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VBIC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VBIC_i_T2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VBIC" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VBIC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VBIC_i/T2A2_A.txt" mylink="aarch32.instrs.VBIC_i.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if cmode&lt;0&gt; == '0' || cmode&lt;3:2&gt; == '11' then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>('1', cmode, i:imm3:imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VBIC_i_A1_Q, VBIC_i_A2_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1 and A2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIC_i_T1_Q, VBIC_i_T2_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIC_i_A1_Q, VBIC_i_A2_Q, VBIC_i_T1_Q, VBIC_i_T2_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIC_i_A1_Q, VBIC_i_A2_Q, VBIC_i_T1_Q, VBIC_i_T2_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIC_i_A1_D, VBIC_i_A2_D, VBIC_i_T1_D, VBIC_i_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIC_i_A1_Q, VBIC_i_A2_Q, VBIC_i_T1_Q, VBIC_i_T2_Q" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is a constant of the specified type that is replicated to fill the destination register. For details of the range of constants available and the encoding of <syntax>&lt;imm&gt;</syntax>, see <xref linkend="CJAIDJDJ">Modified immediate constants in T32 and A32 Advanced SIMD instructions</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VBIC_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r] AND NOT(imm64);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vbic_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VBIC_r" title="VBIC (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VBIC" />
  </docvars>
  <heading>VBIC (register)</heading>
  <desc>
    <brief>
      <para>Vector Bitwise Bit Clear (register)</para>
    </brief>
    <authored>
      <para>Vector Bitwise Bit Clear (register) performs a bitwise AND between a register value and the complement of a register value, and places the result in the destination register.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VBIC" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VBIC_r/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VBIC_r_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VBIC" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VBIC</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VBIC_r_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VBIC" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VBIC</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VBIC_r/T1A1_A.txt" mylink="aarch32.instrs.VBIC_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VBIC" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VBIC_r/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VBIC_r_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VBIC" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VBIC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VBIC_r_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VBIC" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VBIC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VBIC_r/T1A1_A.txt" mylink="aarch32.instrs.VBIC_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VBIC_r_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIC_r_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIC_r_A1_Q, VBIC_r_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIC_r_A1_Q, VBIC_r_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>An optional data type. It is ignored by assemblers, and does not affect the encoding.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIC_r_A1_Q, VBIC_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIC_r_A1_Q, VBIC_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIC_r_A1_Q, VBIC_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIC_r_A1_D, VBIC_r_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIC_r_A1_D, VBIC_r_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIC_r_A1_D, VBIC_r_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VBIC_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r] AND NOT(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vbif.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VBIF" title="VBIF -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VBIF" />
  </docvars>
  <heading>VBIF</heading>
  <desc>
    <brief>
      <para>Vector Bitwise Insert if False</para>
    </brief>
    <authored>
      <para>Vector Bitwise Insert if False inserts each bit from the first source register into the destination register if the corresponding bit of the second source register is 0, otherwise leaves the bit in the destination register unchanged.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VBIF" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VBIF/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op" usename="1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VBIF_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VBIF" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VBIF</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VBIF_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VBIF" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VBIF</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VBIF/T1A1_A.txt" mylink="aarch32.instrs.VBIF.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if op == '00' then SEE "VEOR";</line>
<line>if op == '01' then operation = <a link="VBitOps_VBSL" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBSL</a>;</line>
<line>if op == '10' then operation = <a link="VBitOps_VBIT" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBIT</a>;</line>
<line>if op == '11' then operation = <a link="VBitOps_VBIF" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBIF</a>;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VBIF" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VBIF/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op" usename="1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VBIF_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VBIF" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VBIF</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VBIF_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VBIF" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VBIF</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VBIF/T1A1_A.txt" mylink="aarch32.instrs.VBIF.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if op == '00' then SEE "VEOR";</line>
<line>if op == '01' then operation = <a link="VBitOps_VBSL" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBSL</a>;</line>
<line>if op == '10' then operation = <a link="VBitOps_VBIT" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBIT</a>;</line>
<line>if op == '11' then operation = <a link="VBitOps_VBIF" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBIF</a>;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VBIF_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIF_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIF_A1_Q, VBIF_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIF_A1_Q, VBIF_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>An optional data type. It is ignored by assemblers, and does not affect the encoding.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIF_A1_Q, VBIF_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIF_A1_Q, VBIF_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIF_A1_Q, VBIF_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIF_A1_D, VBIF_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIF_A1_D, VBIF_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIF_A1_D, VBIF_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VBIF/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        case operation of</line>
<line>            when <a link="VBitOps_VBIF" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBIF</a>  <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = (<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r] AND <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r]) OR (<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r] AND NOT(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r]));</line>
<line>            when <a link="VBitOps_VBIT" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBIT</a>  <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = (<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r] AND <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r]) OR (<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r] AND NOT(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r]));</line>
<line>            when <a link="VBitOps_VBSL" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBSL</a>  <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = (<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r] AND <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r]) OR (<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r] AND NOT(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r]));</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vbit.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VBIT" title="VBIT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VBIT" />
  </docvars>
  <heading>VBIT</heading>
  <desc>
    <brief>
      <para>Vector Bitwise Insert if True</para>
    </brief>
    <authored>
      <para>Vector Bitwise Insert if True inserts each bit from the first source register into the destination register if the corresponding bit of the second source register is 1, otherwise leaves the bit in the destination register unchanged.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VBIT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VBIF/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VBIT_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VBIT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VBIT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VBIT_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VBIT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VBIT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VBIF/T1A1_A.txt" mylink="aarch32.instrs.VBIF.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if op == '00' then SEE "VEOR";</line>
<line>if op == '01' then operation = <a link="VBitOps_VBSL" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBSL</a>;</line>
<line>if op == '10' then operation = <a link="VBitOps_VBIT" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBIT</a>;</line>
<line>if op == '11' then operation = <a link="VBitOps_VBIF" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBIF</a>;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VBIT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VBIF/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VBIT_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VBIT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VBIT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VBIT_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VBIT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VBIT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VBIF/T1A1_A.txt" mylink="aarch32.instrs.VBIF.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if op == '00' then SEE "VEOR";</line>
<line>if op == '01' then operation = <a link="VBitOps_VBSL" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBSL</a>;</line>
<line>if op == '10' then operation = <a link="VBitOps_VBIT" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBIT</a>;</line>
<line>if op == '11' then operation = <a link="VBitOps_VBIF" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBIF</a>;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VBIT_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIT_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIT_A1_Q, VBIT_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIT_A1_Q, VBIT_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>An optional data type. It is ignored by assemblers, and does not affect the encoding.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIT_A1_Q, VBIT_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIT_A1_Q, VBIT_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIT_A1_Q, VBIT_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIT_A1_D, VBIT_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIT_A1_D, VBIT_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBIT_A1_D, VBIT_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VBIF/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        case operation of</line>
<line>            when <a link="VBitOps_VBIF" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBIF</a>  <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = (<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r] AND <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r]) OR (<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r] AND NOT(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r]));</line>
<line>            when <a link="VBitOps_VBIT" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBIT</a>  <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = (<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r] AND <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r]) OR (<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r] AND NOT(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r]));</line>
<line>            when <a link="VBitOps_VBSL" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBSL</a>  <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = (<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r] AND <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r]) OR (<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r] AND NOT(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r]));</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vbsl.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VBSL" title="VBSL -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VBSL" />
  </docvars>
  <heading>VBSL</heading>
  <desc>
    <brief>
      <para>Vector Bitwise Select</para>
    </brief>
    <authored>
      <para>Vector Bitwise Select sets each bit in the destination to the corresponding bit from the first source operand when the original destination bit was 1, otherwise from the second source operand.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VBSL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VBIF/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VBSL_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VBSL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VBSL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VBSL_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VBSL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VBSL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VBIF/T1A1_A.txt" mylink="aarch32.instrs.VBIF.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if op == '00' then SEE "VEOR";</line>
<line>if op == '01' then operation = <a link="VBitOps_VBSL" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBSL</a>;</line>
<line>if op == '10' then operation = <a link="VBitOps_VBIT" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBIT</a>;</line>
<line>if op == '11' then operation = <a link="VBitOps_VBIF" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBIF</a>;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VBSL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VBIF/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VBSL_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VBSL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VBSL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VBSL_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VBSL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VBSL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VBIF/T1A1_A.txt" mylink="aarch32.instrs.VBIF.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if op == '00' then SEE "VEOR";</line>
<line>if op == '01' then operation = <a link="VBitOps_VBSL" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBSL</a>;</line>
<line>if op == '10' then operation = <a link="VBitOps_VBIT" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBIT</a>;</line>
<line>if op == '11' then operation = <a link="VBitOps_VBIF" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBIF</a>;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VBSL_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBSL_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBSL_A1_Q, VBSL_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBSL_A1_Q, VBSL_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>An optional data type. It is ignored by assemblers, and does not affect the encoding.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBSL_A1_Q, VBSL_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBSL_A1_Q, VBSL_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBSL_A1_Q, VBSL_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBSL_A1_D, VBSL_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBSL_A1_D, VBSL_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VBSL_A1_D, VBSL_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VBIF/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        case operation of</line>
<line>            when <a link="VBitOps_VBIF" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBIF</a>  <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = (<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r] AND <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r]) OR (<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r] AND NOT(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r]));</line>
<line>            when <a link="VBitOps_VBIT" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBIT</a>  <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = (<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r] AND <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r]) OR (<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r] AND NOT(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r]));</line>
<line>            when <a link="VBitOps_VBSL" file="shared_pseudocode.xml" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBSL</a>  <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = (<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r] AND <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r]) OR (<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r] AND NOT(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r]));</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcadd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCADD" title="VCADD -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCADD" />
  </docvars>
  <heading>VCADD</heading>
  <desc>
    <brief>
      <para>Vector Complex Add</para>
    </brief>
    <authored>
      <para>Vector Complex Add.</para>
      <para>This instruction operates on complex numbers that are represented in SIMD&amp;FP registers as pairs of elements, with the more significant element holding the imaginary part of the number and the less significant element holding the real part of the number. Each element holds a floating-point value. It performs the following computation on the corresponding complex number element pairs from the two source registers:</para>
      <list type="unordered">
        <listitem><content>Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 90 or 270 degrees.</content></listitem>
        <listitem><content>The rotated complex number is added to the complex number from the first source register.</content></listitem>
      </list>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCADD" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.3" feature="FEAT_FCMA" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VCADD/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="rot" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCADD_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCADD" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCADD</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;S&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_rotate" hover="Rotation applied to elements in the second SIMD&amp;FP source register (field &quot;rot&quot;) [90,270]">&lt;rotate&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCADD_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCADD" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCADD</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;S&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_rotate" hover="Rotation applied to elements in the second SIMD&amp;FP source register (field &quot;rot&quot;) [90,270]">&lt;rotate&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCADD/A1_A.txt" mylink="aarch32.instrs.VCADD.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveFCADDExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveFCADDExt()">HaveFCADDExt</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>esize = 16 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(S);</line>
<line>if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() &amp;&amp; esize == 16 then UNDEFINED;</line>
<line>elements = 64 DIV esize;</line>
<line>regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCADD" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.3" feature="FEAT_FCMA" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VCADD/T1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="rot" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCADD_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCADD" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCADD</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;S&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_rotate" hover="Rotation applied to elements in the second SIMD&amp;FP source register (field &quot;rot&quot;) [90,270]">&lt;rotate&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCADD_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCADD" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCADD</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;S&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_rotate" hover="Rotation applied to elements in the second SIMD&amp;FP source register (field &quot;rot&quot;) [90,270]">&lt;rotate&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCADD/T1_A.txt" mylink="aarch32.instrs.VCADD.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveFCADDExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveFCADDExt()">HaveFCADDExt</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>esize = 16 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(S);</line>
<line>if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() &amp;&amp; esize == 16 then UNDEFINED;</line>
<line>elements = 64 DIV esize;</line>
<line>regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCADD_A1_D, VCADD_T1_D" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCADD_A1_D, VCADD_T1_D" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="S">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">S</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VCADD_A1_Q, VCADD_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCADD_A1_Q, VCADD_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCADD_A1_Q, VCADD_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCADD_A1_D, VCADD_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCADD_A1_D, VCADD_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCADD_A1_D, VCADD_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCADD_A1_D, VCADD_T1_D" symboldefcount="1">
      <symbol link="sa_rotate">&lt;rotate&gt;</symbol>
      <definition encodedin="rot">
        <intro>Is the rotation to be applied to elements in the second SIMD&amp;FP source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">rot</entry>
                <entry class="symbol">&lt;rotate&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">90</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">270</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCADD/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations();</line>
<line><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>for r = 0 to regs-1</line>
<line>    operand1 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r];</line>
<line>    operand2 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r];</line>
<line>    for e = 0 to (elements DIV 2)-1</line>
<line>        bits(esize) element1;</line>
<line>        bits(esize) element3;</line>
<line>        case rot of</line>
<line>            when '0'</line>
<line>                element1 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,e*2+1,esize]);</line>
<line>                element3 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,e*2,esize];</line>
<line>            when '1'</line>
<line>                element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,e*2+1,esize];</line>
<line>                element3 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,e*2,esize]);</line>
<line>        result1 = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2,esize],element1,<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>        result2 = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2+1,esize],element3,<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e*2,esize] = result1;</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e*2+1,esize] = result2;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vceq_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCEQ_i" title="VCEQ (immediate #0) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCEQ" />
  </docvars>
  <heading>VCEQ (immediate #0)</heading>
  <desc>
    <brief>
      <para>Vector Compare Equal to Zero</para>
    </brief>
    <authored>
      <para>Vector Compare Equal to Zero takes each element in a vector, and compares it with zero.  If it is equal to zero, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.</para>
      <para>The operand vector elements are the same type, and are integers or floating-point numbers. The result vector elements are fields the same size as the operand vector elements.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCEQ" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCEQ_i/A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="9" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCEQ_i_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCEQ" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCEQ</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #0</text></asmtemplate>
      </encoding>
      <encoding name="VCEQ_i_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCEQ" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCEQ</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCEQ_i/A1_A.txt" mylink="aarch32.instrs.VCEQ_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; ((size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size == '00') then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>floating_point = (F == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCEQ" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCEQ_i/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="9" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCEQ_i_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCEQ" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCEQ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #0</text></asmtemplate>
      </encoding>
      <encoding name="VCEQ_i_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCEQ" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCEQ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCEQ_i/T1_A.txt" mylink="aarch32.instrs.VCEQ_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; ((size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size == '00') then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>floating_point = (F == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>F == '1' &amp;&amp; size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCEQ_i_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCEQ_i_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCEQ_i_A1_Q, VCEQ_i_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCEQ_i_A1_Q, VCEQ_i_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="F:size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">F</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">I8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">I16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">I32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VCEQ_i_A1_Q, VCEQ_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCEQ_i_A1_Q, VCEQ_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCEQ_i_A1_D, VCEQ_i_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCEQ_i_A1_D, VCEQ_i_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCEQ_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            boolean test_passed;</line>
<line>            if floating_point then</line>
<line>                bits(esize) zero = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>('0', esize);</line>
<line>                test_passed = <a link="impl-shared.FPCompareEQ.3" file="shared_pseudocode.xml" hover="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], zero, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            else</line>
<line>                test_passed = (<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize] == <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(esize));</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = if test_passed then <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(esize) else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(esize);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vceq_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCEQ_r" title="VCEQ (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCEQ" />
  </docvars>
  <heading>VCEQ (register)</heading>
  <desc>
    <brief>
      <para>Vector Compare Equal</para>
    </brief>
    <authored>
      <para>Vector Compare Equal takes each element in a vector, and compares it with the corresponding element of a second vector. If they are equal, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.</para>
      <para>The operand vector elements are the same type, and are integers or floating-point numbers. The result vector elements are fields the same size as the operand vector elements.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCEQ" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCEQ_r/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCEQ_r_A1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCEQ" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCEQ</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCEQ_r_A1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCEQ" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCEQ</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCEQ_r/T1A1_A.txt" mylink="aarch32.instrs.VCEQ_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>int_operation = TRUE;  esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCEQ" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCEQ_r/A2_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCEQ_r_A2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCEQ" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCEQ</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCEQ_r_A2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCEQ" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCEQ</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCEQ_r/A2_A.txt" mylink="aarch32.instrs.VCEQ_r.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>int_operation = FALSE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCEQ" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCEQ_r/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCEQ_r_T1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCEQ" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCEQ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCEQ_r_T1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCEQ" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCEQ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCEQ_r/T1A1_A.txt" mylink="aarch32.instrs.VCEQ_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>int_operation = TRUE;  esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCEQ" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCEQ_r/T2_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCEQ_r_T2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCEQ" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCEQ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCEQ_r_T2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCEQ" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCEQ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCEQ_r/T2_A.txt" mylink="aarch32.instrs.VCEQ_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>int_operation = FALSE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>sz == '1' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCEQ_r_A1_Q, VCEQ_r_A2_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1 and A2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCEQ_r_T1_Q, VCEQ_r_T2_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCEQ_r_A1_Q, VCEQ_r_A2_Q, VCEQ_r_T1_Q, VCEQ_r_T2_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCEQ_r_A1_Q, VCEQ_r_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>For encoding A1 and T1: is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">I8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">I16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">I32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VCEQ_r_A2_Q, VCEQ_r_T2_Q" symboldefcount="2">
      <symbol link="sa_dt_1">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>For encoding A2 and T2: is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VCEQ_r_A1_Q, VCEQ_r_A2_Q, VCEQ_r_T1_Q, VCEQ_r_T2_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCEQ_r_A1_Q, VCEQ_r_A2_Q, VCEQ_r_T1_Q, VCEQ_r_T2_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCEQ_r_A1_Q, VCEQ_r_A2_Q, VCEQ_r_T1_Q, VCEQ_r_T2_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCEQ_r_A1_D, VCEQ_r_A2_D, VCEQ_r_T1_D, VCEQ_r_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCEQ_r_A1_D, VCEQ_r_A2_D, VCEQ_r_T1_D, VCEQ_r_T2_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCEQ_r_A1_D, VCEQ_r_A2_D, VCEQ_r_T1_D, VCEQ_r_T2_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCEQ_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize];  op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize];</line>
<line>            boolean test_passed;</line>
<line>            if int_operation then</line>
<line>                test_passed = (op1 == op2);</line>
<line>            else</line>
<line>                test_passed = <a link="impl-shared.FPCompareEQ.3" file="shared_pseudocode.xml" hover="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(op1, op2, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = if test_passed then <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(esize) else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(esize);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcge_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCGE_i" title="VCGE (immediate #0) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCGE" />
  </docvars>
  <heading>VCGE (immediate #0)</heading>
  <desc>
    <brief>
      <para>Vector Compare Greater Than or Equal to Zero</para>
    </brief>
    <authored>
      <para>Vector Compare Greater Than or Equal to Zero takes each element in a vector, and compares it with zero. If it is greater than or equal to zero, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.</para>
      <para>The operand vector elements are the same type, and are signed integers or floating-point numbers. The result vector elements are fields the same size as the operand vector elements.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check and is operating only on integer vector elements, then the following apply:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCGE" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCGE_i/A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="9" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCGE_i_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCGE" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCGE</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #0</text></asmtemplate>
      </encoding>
      <encoding name="VCGE_i_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCGE" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCGE</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCGE_i/A1_A.txt" mylink="aarch32.instrs.VCGE_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; ((size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size == '00') then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>floating_point = (F == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCGE" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCGE_i/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="9" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCGE_i_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCGE" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCGE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #0</text></asmtemplate>
      </encoding>
      <encoding name="VCGE_i_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCGE" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCGE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCGE_i/T1_A.txt" mylink="aarch32.instrs.VCGE_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; ((size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size == '00') then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>floating_point = (F == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>F == '1' &amp;&amp; size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCGE_i_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGE_i_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGE_i_A1_Q, VCGE_i_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGE_i_A1_Q, VCGE_i_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="F:size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">F</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VCGE_i_A1_Q, VCGE_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGE_i_A1_Q, VCGE_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGE_i_A1_D, VCGE_i_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGE_i_A1_D, VCGE_i_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCGE_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            boolean test_passed;</line>
<line>            if floating_point then</line>
<line>                bits(esize) zero = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>('0', esize);</line>
<line>                test_passed = <a link="impl-shared.FPCompareGE.3" file="shared_pseudocode.xml" hover="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], zero, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            else</line>
<line>                test_passed = (<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[m+r],e,esize]) &gt;= 0);</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = if test_passed then <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(esize) else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(esize);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcge_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCGE_r" title="VCGE (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCGE" />
  </docvars>
  <heading>VCGE (register)</heading>
  <desc>
    <brief>
      <para>Vector Compare Greater Than or Equal</para>
    </brief>
    <authored>
      <para>Vector Compare Greater Than or Equal takes each element in a vector, and compares it with the corresponding element of a second vector. If the first is greater than or equal to the second, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.</para>
      <para>The operand vector elements are the same type, and are signed integers, unsigned integers, or floating-point numbers. The result vector elements are fields the same size as the operand vector elements.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check and is operating only on integer vector elements, then the following apply:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="1">
    <alias_list_intro>This instruction is used by the alias </alias_list_intro>
    <aliasref aliaspageid="VCLE_VCGE_r" aliasfile="vcle_vcge_r.xml" hover="Vector Compare Less Than or Equal" punct=".">
      <text>VCLE (register)</text>
      <aliaspref>Never</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink />
      <text> below for details of when the alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCGE" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCGE_r/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCGE_r_A1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCGE" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCGE</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCGE_r_A1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCGE" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCGE</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCGE_r/T1A1_A.txt" mylink="aarch32.instrs.VCGE_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>vtype = if U == '1' then <a link="VCGEType_unsigned" file="shared_pseudocode.xml" hover="enumeration VCGEType {VCGEType_signed, VCGEType_unsigned, VCGEType_fp}">VCGEType_unsigned</a> else <a link="VCGEType_signed" file="shared_pseudocode.xml" hover="enumeration VCGEType {VCGEType_signed, VCGEType_unsigned, VCGEType_fp}">VCGEType_signed</a>;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCGE" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCGE_r/A2_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCGE_r_A2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCGE" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCGE</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCGE_r_A2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCGE" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCGE</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCGE_r/A2_A.txt" mylink="aarch32.instrs.VCGE_r.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>vtype = <a link="VCGEType_fp" file="shared_pseudocode.xml" hover="enumeration VCGEType {VCGEType_signed, VCGEType_unsigned, VCGEType_fp}">VCGEType_fp</a>;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCGE" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCGE_r/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCGE_r_T1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCGE" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCGE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCGE_r_T1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCGE" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCGE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCGE_r/T1A1_A.txt" mylink="aarch32.instrs.VCGE_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>vtype = if U == '1' then <a link="VCGEType_unsigned" file="shared_pseudocode.xml" hover="enumeration VCGEType {VCGEType_signed, VCGEType_unsigned, VCGEType_fp}">VCGEType_unsigned</a> else <a link="VCGEType_signed" file="shared_pseudocode.xml" hover="enumeration VCGEType {VCGEType_signed, VCGEType_unsigned, VCGEType_fp}">VCGEType_signed</a>;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCGE" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCGE_r/T2_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCGE_r_T2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCGE" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCGE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCGE_r_T2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCGE" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCGE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCGE_r/T2_A.txt" mylink="aarch32.instrs.VCGE_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>vtype = <a link="VCGEType_fp" file="shared_pseudocode.xml" hover="enumeration VCGEType {VCGEType_signed, VCGEType_unsigned, VCGEType_fp}">VCGEType_fp</a>;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>sz == '1' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCGE_r_A1_Q, VCGE_r_A2_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1 and A2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGE_r_T1_Q, VCGE_r_T2_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGE_r_A1_Q, VCGE_r_A2_Q, VCGE_r_T1_Q, VCGE_r_T2_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGE_r_A1_Q, VCGE_r_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>For encoding A1 and T1: is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VCGE_r_A2_Q, VCGE_r_T2_Q" symboldefcount="2">
      <symbol link="sa_dt_1">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>For encoding A2 and T2: is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VCGE_r_A1_Q, VCGE_r_A2_Q, VCGE_r_T1_Q, VCGE_r_T2_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGE_r_A1_Q, VCGE_r_A2_Q, VCGE_r_T1_Q, VCGE_r_T2_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGE_r_A1_Q, VCGE_r_A2_Q, VCGE_r_T1_Q, VCGE_r_T2_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGE_r_A1_D, VCGE_r_A2_D, VCGE_r_T1_D, VCGE_r_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGE_r_A1_D, VCGE_r_A2_D, VCGE_r_T1_D, VCGE_r_T2_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGE_r_A1_D, VCGE_r_A2_D, VCGE_r_T1_D, VCGE_r_T2_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCGE_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize];  op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize];</line>
<line>            boolean test_passed;</line>
<line>            case vtype of</line>
<line>                when <a link="VCGEType_signed" file="shared_pseudocode.xml" hover="enumeration VCGEType {VCGEType_signed, VCGEType_unsigned, VCGEType_fp}">VCGEType_signed</a>    test_passed = (<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(op1) &gt;= <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(op2));</line>
<line>                when <a link="VCGEType_unsigned" file="shared_pseudocode.xml" hover="enumeration VCGEType {VCGEType_signed, VCGEType_unsigned, VCGEType_fp}">VCGEType_unsigned</a>  test_passed = (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op1) &gt;= <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op2));</line>
<line>                when <a link="VCGEType_fp" file="shared_pseudocode.xml" hover="enumeration VCGEType {VCGEType_signed, VCGEType_unsigned, VCGEType_fp}">VCGEType_fp</a>        test_passed = <a link="impl-shared.FPCompareGE.3" file="shared_pseudocode.xml" hover="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(op1, op2, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = if test_passed then <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(esize) else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(esize);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcgt_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCGT_i" title="VCGT (immediate #0) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCGT" />
  </docvars>
  <heading>VCGT (immediate #0)</heading>
  <desc>
    <brief>
      <para>Vector Compare Greater Than Zero</para>
    </brief>
    <authored>
      <para>Vector Compare Greater Than Zero takes each element in a vector, and compares it with zero.  If it is greater than zero, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.</para>
      <para>The operand vector elements are the same type, and are signed integers or floating-point numbers. The result vector elements are fields the same size as the operand vector elements.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check and is operating only on integer vector elements, then the following apply:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCGT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCGT_i/A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="9" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCGT_i_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCGT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCGT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #0</text></asmtemplate>
      </encoding>
      <encoding name="VCGT_i_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCGT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCGT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCGT_i/A1_A.txt" mylink="aarch32.instrs.VCGT_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; ((size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size == '00') then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>floating_point = (F == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCGT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCGT_i/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="9" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCGT_i_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCGT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCGT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #0</text></asmtemplate>
      </encoding>
      <encoding name="VCGT_i_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCGT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCGT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCGT_i/T1_A.txt" mylink="aarch32.instrs.VCGT_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; ((size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size == '00') then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>floating_point = (F == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>F == '1' &amp;&amp; size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCGT_i_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGT_i_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGT_i_A1_Q, VCGT_i_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGT_i_A1_Q, VCGT_i_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="F:size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">F</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VCGT_i_A1_Q, VCGT_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGT_i_A1_Q, VCGT_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGT_i_A1_D, VCGT_i_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGT_i_A1_D, VCGT_i_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCGT_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            boolean test_passed;</line>
<line>            if floating_point then</line>
<line>                bits(esize) zero = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>('0', esize);</line>
<line>                test_passed = <a link="impl-shared.FPCompareGT.3" file="shared_pseudocode.xml" hover="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], zero, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            else</line>
<line>                test_passed = (<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize]) &gt; 0);</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = if test_passed then <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(esize) else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(esize);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcgt_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCGT_r" title="VCGT (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCGT" />
  </docvars>
  <heading>VCGT (register)</heading>
  <desc>
    <brief>
      <para>Vector Compare Greater Than</para>
    </brief>
    <authored>
      <para>Vector Compare Greater Than takes each element in a vector, and compares it with the corresponding element of a second vector. If the first is greater than the second, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.</para>
      <para>The operand vector elements are the same type, and are signed integers, unsigned integers, or floating-point numbers. The result vector elements are fields the same size as the operand vector elements.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check and is operating only on integer vector elements, then the following apply:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="1">
    <alias_list_intro>This instruction is used by the alias </alias_list_intro>
    <aliasref aliaspageid="VCLT_VCGT_r" aliasfile="vclt_vcgt_r.xml" hover="Vector Compare Less Than" punct=".">
      <text>VCLT (register)</text>
      <aliaspref>Never</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink />
      <text> below for details of when the alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCGT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCGT_r/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCGT_r_A1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCGT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCGT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCGT_r_A1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCGT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCGT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCGT_r/T1A1_A.txt" mylink="aarch32.instrs.VCGT_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>vtype = if U == '1' then <a link="VCGTtype_unsigned" file="shared_pseudocode.xml" hover="enumeration VCGTtype {VCGTtype_signed, VCGTtype_unsigned, VCGTtype_fp}">VCGTtype_unsigned</a> else <a link="VCGTtype_signed" file="shared_pseudocode.xml" hover="enumeration VCGTtype {VCGTtype_signed, VCGTtype_unsigned, VCGTtype_fp}">VCGTtype_signed</a>;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCGT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCGT_r/A2_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCGT_r_A2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCGT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCGT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCGT_r_A2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCGT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCGT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCGT_r/A2_A.txt" mylink="aarch32.instrs.VCGT_r.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>vtype = <a link="VCGTtype_fp" file="shared_pseudocode.xml" hover="enumeration VCGTtype {VCGTtype_signed, VCGTtype_unsigned, VCGTtype_fp}">VCGTtype_fp</a>;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCGT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCGT_r/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCGT_r_T1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCGT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCGT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCGT_r_T1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCGT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCGT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCGT_r/T1A1_A.txt" mylink="aarch32.instrs.VCGT_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>vtype = if U == '1' then <a link="VCGTtype_unsigned" file="shared_pseudocode.xml" hover="enumeration VCGTtype {VCGTtype_signed, VCGTtype_unsigned, VCGTtype_fp}">VCGTtype_unsigned</a> else <a link="VCGTtype_signed" file="shared_pseudocode.xml" hover="enumeration VCGTtype {VCGTtype_signed, VCGTtype_unsigned, VCGTtype_fp}">VCGTtype_signed</a>;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCGT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCGT_r/T2_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCGT_r_T2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCGT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCGT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCGT_r_T2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCGT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCGT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCGT_r/T2_A.txt" mylink="aarch32.instrs.VCGT_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>vtype = <a link="VCGTtype_fp" file="shared_pseudocode.xml" hover="enumeration VCGTtype {VCGTtype_signed, VCGTtype_unsigned, VCGTtype_fp}">VCGTtype_fp</a>;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>sz == '1' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCGT_r_A1_Q, VCGT_r_A2_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1 and A2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGT_r_T1_Q, VCGT_r_T2_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGT_r_A1_Q, VCGT_r_A2_Q, VCGT_r_T1_Q, VCGT_r_T2_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGT_r_A1_Q, VCGT_r_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>For encoding A1 and T1: is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VCGT_r_A2_Q, VCGT_r_T2_Q" symboldefcount="2">
      <symbol link="sa_dt_1">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>For encoding A2 and T2: is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VCGT_r_A1_Q, VCGT_r_A2_Q, VCGT_r_T1_Q, VCGT_r_T2_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGT_r_A1_Q, VCGT_r_A2_Q, VCGT_r_T1_Q, VCGT_r_T2_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGT_r_A1_Q, VCGT_r_A2_Q, VCGT_r_T1_Q, VCGT_r_T2_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGT_r_A1_D, VCGT_r_A2_D, VCGT_r_T1_D, VCGT_r_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGT_r_A1_D, VCGT_r_A2_D, VCGT_r_T1_D, VCGT_r_T2_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCGT_r_A1_D, VCGT_r_A2_D, VCGT_r_T1_D, VCGT_r_T2_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCGT_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize];  op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize];</line>
<line>            boolean test_passed;</line>
<line>            case vtype of</line>
<line>                when <a link="VCGTtype_signed" file="shared_pseudocode.xml" hover="enumeration VCGTtype {VCGTtype_signed, VCGTtype_unsigned, VCGTtype_fp}">VCGTtype_signed</a>    test_passed = (<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(op1) &gt; <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(op2));</line>
<line>                when <a link="VCGTtype_unsigned" file="shared_pseudocode.xml" hover="enumeration VCGTtype {VCGTtype_signed, VCGTtype_unsigned, VCGTtype_fp}">VCGTtype_unsigned</a>  test_passed = (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op1) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op2));</line>
<line>                when <a link="VCGTtype_fp" file="shared_pseudocode.xml" hover="enumeration VCGTtype {VCGTtype_signed, VCGTtype_unsigned, VCGTtype_fp}">VCGTtype_fp</a>        test_passed = <a link="impl-shared.FPCompareGT.3" file="shared_pseudocode.xml" hover="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(op1, op2, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = if test_passed then <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(esize) else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(esize);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcle_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCLE_i" title="VCLE (immediate #0) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCLE" />
  </docvars>
  <heading>VCLE (immediate #0)</heading>
  <desc>
    <brief>
      <para>Vector Compare Less Than or Equal to Zero</para>
    </brief>
    <authored>
      <para>Vector Compare Less Than or Equal to Zero takes each element in a vector, and compares it with zero. If it is less than or equal to zero, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.</para>
      <para>The operand vector elements are the same type, and are signed integers or floating-point numbers. The result vector elements are fields the same size as the operand vector elements.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check and is operating only on integer vector elements, then the following apply:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCLE" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCLE_i/A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="9" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCLE_i_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCLE" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCLE</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #0</text></asmtemplate>
      </encoding>
      <encoding name="VCLE_i_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCLE" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCLE</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCLE_i/A1_A.txt" mylink="aarch32.instrs.VCLE_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; ((size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size == '00') then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>floating_point = (F == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCLE" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCLE_i/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="9" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCLE_i_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCLE" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCLE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #0</text></asmtemplate>
      </encoding>
      <encoding name="VCLE_i_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCLE" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCLE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCLE_i/T1_A.txt" mylink="aarch32.instrs.VCLE_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; ((size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size == '00') then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>floating_point = (F == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>F == '1' &amp;&amp; size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCLE_i_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLE_i_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLE_i_A1_Q, VCLE_i_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLE_i_A1_Q, VCLE_i_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="F:size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">F</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VCLE_i_A1_Q, VCLE_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLE_i_A1_Q, VCLE_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLE_i_A1_D, VCLE_i_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLE_i_A1_D, VCLE_i_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCLE_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            boolean test_passed;</line>
<line>            if floating_point then</line>
<line>                bits(esize) zero = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>('0', esize);</line>
<line>                test_passed = <a link="impl-shared.FPCompareGE.3" file="shared_pseudocode.xml" hover="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            else</line>
<line>                test_passed = (<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[m+r],e,esize]) &lt;= 0);</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = if test_passed then <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(esize) else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(esize);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcle_vcge_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCLE_VCGE_r" title="VCLE (register) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="VCLE" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCGE" />
  </docvars>
  <heading>VCLE (register)</heading>
  <desc>
    <brief>
      <para>Vector Compare Less Than or Equal</para>
    </brief>
    <authored>
      <para>Vector Compare Less Than or Equal takes each element in a vector, and compares it with the corresponding element of a second vector. If the first is less than or equal to the second, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>The description of <xref>VCGE_r</xref> gives the operational pseudocode for this instruction.</para>
  </operationalnotes>
  <aliasto refiform="vcge_r.xml" iformid="VCGE_r">VCGE (register)</aliasto>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCGE" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCLE_VCGE_r_A1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VCLE" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCGE" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCLE</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vcge_r.xml#VCGE_r_A1_D">VCGE</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VCLE_VCGE_r_A1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VCLE" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCGE" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCLE</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vcge_r.xml#VCGE_r_A1_Q">VCGE</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCGE" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCLE_VCGE_r_A2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VCLE" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCGE" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCLE</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vcge_r.xml#VCGE_r_A2_D">VCGE</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VCLE_VCGE_r_A2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VCLE" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCGE" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCLE</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vcge_r.xml#VCGE_r_A2_Q">VCGE</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCGE" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCLE_VCGE_r_T1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VCLE" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCGE" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCLE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vcge_r.xml#VCGE_r_T1_D">VCGE</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VCLE_VCGE_r_T1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VCLE" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCGE" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCLE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vcge_r.xml#VCGE_r_T1_Q">VCGE</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCGE" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCLE_VCGE_r_T2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VCLE" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCGE" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCLE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vcge_r.xml#VCGE_r_T2_D">VCGE</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VCLE_VCGE_r_T2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VCLE" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCGE" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCLE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vcge_r.xml#VCGE_r_T2_Q">VCGE</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCLE_VCGE_r_A1_D, VCLE_VCGE_r_A2_D, VCLE_VCGE_r_T1_D, VCLE_VCGE_r_T2_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLE_VCGE_r_A1_D, VCLE_VCGE_r_A2_D, VCLE_VCGE_r_T1_D, VCLE_VCGE_r_T2_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLE_VCGE_r_A1_Q, VCLE_VCGE_r_A2_Q, VCLE_VCGE_r_T1_Q, VCLE_VCGE_r_T2_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLE_VCGE_r_A1_Q, VCLE_VCGE_r_A2_Q, VCLE_VCGE_r_T1_Q, VCLE_VCGE_r_T2_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLE_VCGE_r_A1_Q, VCLE_VCGE_r_A2_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For encoding A1 and A2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLE_VCGE_r_T1_Q, VCLE_VCGE_r_T2_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLE_VCGE_r_A1_Q, VCLE_VCGE_r_A2_Q, VCLE_VCGE_r_T1_Q, VCLE_VCGE_r_T2_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLE_VCGE_r_A1_Q, VCLE_VCGE_r_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>For encoding A1 and T1: is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VCLE_VCGE_r_A2_Q, VCLE_VCGE_r_T2_Q" symboldefcount="2">
      <symbol link="sa_dt_1">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>For encoding A2 and T2: is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VCLE_VCGE_r_A1_Q, VCLE_VCGE_r_A2_Q, VCLE_VCGE_r_T1_Q, VCLE_VCGE_r_T2_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLE_VCGE_r_A1_D, VCLE_VCGE_r_A2_D, VCLE_VCGE_r_T1_D, VCLE_VCGE_r_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="vcls.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCLS" title="VCLS -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCLS" />
  </docvars>
  <heading>VCLS</heading>
  <desc>
    <brief>
      <para>Vector Count Leading Sign Bits</para>
    </brief>
    <authored>
      <para>Vector Count Leading Sign Bits counts the number of consecutive bits following the topmost bit, that are the same as the topmost bit, in each element in a vector, and places the results in a second vector. The count does not include the topmost bit itself.</para>
      <para>The operand vector elements can be any one of 8-bit, 16-bit, or 32-bit signed integers.</para>
      <para>The result vector elements are the same data type as the operand vector elements.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCLS" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCLS/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCLS_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCLS" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCLS</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCLS_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCLS" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCLS</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCLS/T1A1_A.txt" mylink="aarch32.instrs.VCLS.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCLS" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCLS/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCLS_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCLS" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCLS_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCLS" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCLS/T1A1_A.txt" mylink="aarch32.instrs.VCLS.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCLS_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLS_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLS_A1_Q, VCLS_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLS_A1_Q, VCLS_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VCLS_A1_Q, VCLS_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLS_A1_Q, VCLS_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLS_A1_D, VCLS_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLS_A1_D, VCLS_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCLS/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.CountLeadingSignBits.1" file="shared_pseudocode.xml" hover="function: integer CountLeadingSignBits(bits(N) x)">CountLeadingSignBits</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize])&lt;esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vclt_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCLT_i" title="VCLT (immediate #0) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCLT" />
  </docvars>
  <heading>VCLT (immediate #0)</heading>
  <desc>
    <brief>
      <para>Vector Compare Less Than Zero</para>
    </brief>
    <authored>
      <para>Vector Compare Less Than Zero takes each element in a vector, and compares it with zero.  If it is less than zero, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.</para>
      <para>The operand vector elements are the same type, and are signed integers or floating-point numbers. The result vector elements are fields the same size as the operand vector elements.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check and is operating only on integer vector elements, then the following apply:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCLT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCLT_i/A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="9" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCLT_i_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCLT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCLT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #0</text></asmtemplate>
      </encoding>
      <encoding name="VCLT_i_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCLT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCLT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCLT_i/A1_A.txt" mylink="aarch32.instrs.VCLT_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; ((size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size == '00') then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>floating_point = (F == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCLT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCLT_i/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="9" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCLT_i_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCLT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCLT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #0</text></asmtemplate>
      </encoding>
      <encoding name="VCLT_i_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCLT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCLT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCLT_i/T1_A.txt" mylink="aarch32.instrs.VCLT_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; ((size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size == '00') then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>floating_point = (F == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>F == '1' &amp;&amp; size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCLT_i_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLT_i_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLT_i_A1_Q, VCLT_i_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLT_i_A1_Q, VCLT_i_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="F:size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">F</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VCLT_i_A1_Q, VCLT_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLT_i_A1_Q, VCLT_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLT_i_A1_D, VCLT_i_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLT_i_A1_D, VCLT_i_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCLT_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            boolean test_passed;</line>
<line>            if floating_point then</line>
<line>                bits(esize) zero = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>('0', esize);</line>
<line>                test_passed = <a link="impl-shared.FPCompareGT.3" file="shared_pseudocode.xml" hover="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            else</line>
<line>                test_passed = (<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize]) &lt; 0);</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = if test_passed then <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(esize) else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(esize);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vclt_vcgt_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCLT_VCGT_r" title="VCLT (register) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="VCLT" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCGT" />
  </docvars>
  <heading>VCLT (register)</heading>
  <desc>
    <brief>
      <para>Vector Compare Less Than</para>
    </brief>
    <authored>
      <para>Vector Compare Less Than takes each element in a vector, and compares it with the corresponding element of a second vector. If the first is less than the second, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>The description of <xref>VCGT_r</xref> gives the operational pseudocode for this instruction.</para>
  </operationalnotes>
  <aliasto refiform="vcgt_r.xml" iformid="VCGT_r">VCGT (register)</aliasto>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCGT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCLT_VCGT_r_A1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VCLT" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCGT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCLT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vcgt_r.xml#VCGT_r_A1_D">VCGT</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VCLT_VCGT_r_A1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VCLT" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCGT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCLT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vcgt_r.xml#VCGT_r_A1_Q">VCGT</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCGT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCLT_VCGT_r_A2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VCLT" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCGT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCLT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vcgt_r.xml#VCGT_r_A2_D">VCGT</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VCLT_VCGT_r_A2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VCLT" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCGT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCLT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vcgt_r.xml#VCGT_r_A2_Q">VCGT</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCGT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCLT_VCGT_r_T1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VCLT" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCGT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCLT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vcgt_r.xml#VCGT_r_T1_D">VCGT</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VCLT_VCGT_r_T1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VCLT" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCGT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCLT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vcgt_r.xml#VCGT_r_T1_Q">VCGT</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCGT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCLT_VCGT_r_T2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VCLT" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCGT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCLT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vcgt_r.xml#VCGT_r_T2_D">VCGT</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VCLT_VCGT_r_T2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VCLT" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCGT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCLT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vcgt_r.xml#VCGT_r_T2_Q">VCGT</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCLT_VCGT_r_A1_D, VCLT_VCGT_r_A2_D, VCLT_VCGT_r_T1_D, VCLT_VCGT_r_T2_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLT_VCGT_r_A1_D, VCLT_VCGT_r_A2_D, VCLT_VCGT_r_T1_D, VCLT_VCGT_r_T2_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLT_VCGT_r_A1_Q, VCLT_VCGT_r_A2_Q, VCLT_VCGT_r_T1_Q, VCLT_VCGT_r_T2_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLT_VCGT_r_A1_Q, VCLT_VCGT_r_A2_Q, VCLT_VCGT_r_T1_Q, VCLT_VCGT_r_T2_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLT_VCGT_r_A1_Q, VCLT_VCGT_r_A2_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For encoding A1 and A2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLT_VCGT_r_T1_Q, VCLT_VCGT_r_T2_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLT_VCGT_r_A1_Q, VCLT_VCGT_r_A2_Q, VCLT_VCGT_r_T1_Q, VCLT_VCGT_r_T2_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLT_VCGT_r_A1_Q, VCLT_VCGT_r_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>For encoding A1 and T1: is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VCLT_VCGT_r_A2_Q, VCLT_VCGT_r_T2_Q" symboldefcount="2">
      <symbol link="sa_dt_1">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>For encoding A2 and T2: is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VCLT_VCGT_r_A1_Q, VCLT_VCGT_r_A2_Q, VCLT_VCGT_r_T1_Q, VCLT_VCGT_r_T2_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLT_VCGT_r_A1_D, VCLT_VCGT_r_A2_D, VCLT_VCGT_r_T1_D, VCLT_VCGT_r_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="vclz.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCLZ" title="VCLZ -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCLZ" />
  </docvars>
  <heading>VCLZ</heading>
  <desc>
    <brief>
      <para>Vector Count Leading Zeros</para>
    </brief>
    <authored>
      <para>Vector Count Leading Zeros counts the number of consecutive zeros, starting from the most significant bit, in each element in a vector, and places the results in a second vector.</para>
      <para>The operand vector elements can be any one of 8-bit, 16-bit, or 32-bit integers. There is no distinction between signed and unsigned integers.</para>
      <para>The result vector elements are the same data type as the operand vector elements.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCLZ" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCLZ/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCLZ_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCLZ" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCLZ</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCLZ_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCLZ" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCLZ</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCLZ/T1A1_A.txt" mylink="aarch32.instrs.VCLZ.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCLZ" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCLZ/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCLZ_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCLZ" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCLZ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCLZ_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCLZ" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCLZ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCLZ/T1A1_A.txt" mylink="aarch32.instrs.VCLZ.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCLZ_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLZ_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLZ_A1_Q, VCLZ_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLZ_A1_Q, VCLZ_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">I8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">I16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">I32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VCLZ_A1_Q, VCLZ_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLZ_A1_Q, VCLZ_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLZ_A1_D, VCLZ_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCLZ_A1_D, VCLZ_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCLZ/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.CountLeadingZeroBits.1" file="shared_pseudocode.xml" hover="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize])&lt;esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcmla.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCMLA" title="VCMLA -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCMLA" />
  </docvars>
  <heading>VCMLA</heading>
  <desc>
    <brief>
      <para>Vector Complex Multiply Accumulate</para>
    </brief>
    <authored>
      <para>Vector Complex Multiply Accumulate.</para>
      <para>This instruction operates on complex numbers that are represented in SIMD&amp;FP registers as pairs of elements, with the more significant element holding the imaginary part of the number and the less significant element holding the real part of the number. Each element holds a floating-point value. It performs the following computation on the corresponding complex number element pairs from the two source registers and the destination register:</para>
      <list type="unordered">
        <listitem><content>Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees.</content></listitem>
        <listitem><content>The two elements of the transformed complex number are multiplied by:<list type="unordered"><listitem><content>The real element of the complex number from the first source register, if the transformation was a rotation by 0 or 180 degrees.</content></listitem><listitem><content>The imaginary element of the complex number from the first source register, if the transformation was a rotation by 90 or 270 degrees.</content></listitem></list></content></listitem>
        <listitem><content>The complex number resulting from that multiplication is added to the complex number from the destination register.</content></listitem>
      </list>
      <para>The multiplication and addition operations are performed as a fused multiply-add, without any intermediate rounding.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCMLA" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.3" feature="FEAT_FCMA" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VCMLA/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="rot" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCMLA_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCMLA" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;S&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_rotate" hover="Rotation applied to elements in the second SIMD&amp;FP source register (field &quot;rot&quot;) [0,90,180,270]">&lt;rotate&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCMLA_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCMLA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;S&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_rotate" hover="Rotation applied to elements in the second SIMD&amp;FP source register (field &quot;rot&quot;) [0,90,180,270]">&lt;rotate&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCMLA/A1_A.txt" mylink="aarch32.instrs.VCMLA.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveFCADDExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveFCADDExt()">HaveFCADDExt</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>esize = 16 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(S);</line>
<line>if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() &amp;&amp; esize == 16 then UNDEFINED;</line>
<line>elements = 64 DIV esize;</line>
<line>regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCMLA" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.3" feature="FEAT_FCMA" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VCMLA/T1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="rot" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCMLA_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCMLA" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;S&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_rotate" hover="Rotation applied to elements in the second SIMD&amp;FP source register (field &quot;rot&quot;) [0,90,180,270]">&lt;rotate&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCMLA_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCMLA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;S&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_rotate" hover="Rotation applied to elements in the second SIMD&amp;FP source register (field &quot;rot&quot;) [0,90,180,270]">&lt;rotate&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCMLA/T1_A.txt" mylink="aarch32.instrs.VCMLA.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveFCADDExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveFCADDExt()">HaveFCADDExt</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>esize = 16 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(S);</line>
<line>if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() &amp;&amp; esize == 16 then UNDEFINED;</line>
<line>elements = 64 DIV esize;</line>
<line>regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCMLA_A1_D, VCMLA_T1_D" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMLA_A1_D, VCMLA_T1_D" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="S">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">S</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VCMLA_A1_Q, VCMLA_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMLA_A1_Q, VCMLA_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMLA_A1_Q, VCMLA_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMLA_A1_D, VCMLA_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMLA_A1_D, VCMLA_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMLA_A1_D, VCMLA_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMLA_A1_D, VCMLA_T1_D" symboldefcount="1">
      <symbol link="sa_rotate">&lt;rotate&gt;</symbol>
      <definition encodedin="rot">
        <intro>Is the rotation to be applied to elements in the second SIMD&amp;FP source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">rot</entry>
                <entry class="symbol">&lt;rotate&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">0</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">90</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">180</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">270</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCMLA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations();</line>
<line><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>for r = 0 to regs-1</line>
<line>    operand1 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r];</line>
<line>    operand2 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r];</line>
<line>    operand3 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r];</line>
<line>    for e = 0 to (elements DIV 2)-1</line>
<line>        bits(esize) element1;</line>
<line>        bits(esize) element2;</line>
<line>        bits(esize) element3;</line>
<line>        bits(esize) element4;</line>
<line>        case rot of</line>
<line>            when '00'</line>
<line>                element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,e*2,esize];</line>
<line>                element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2,esize];</line>
<line>                element3 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,e*2+1,esize];</line>
<line>                element4 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2,esize];</line>
<line>            when '01'</line>
<line>                element1 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,e*2+1,esize]);</line>
<line>                element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2+1,esize];</line>
<line>                element3 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,e*2,esize];</line>
<line>                element4 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2+1,esize];</line>
<line>            when '10'</line>
<line>                element1 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,e*2,esize]);</line>
<line>                element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2,esize];</line>
<line>                element3 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,e*2+1,esize]);</line>
<line>                element4 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2,esize];</line>
<line>            when '11'</line>
<line>                element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,e*2+1,esize];</line>
<line>                element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2+1,esize];</line>
<line>                element3 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,e*2,esize]);</line>
<line>                element4 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2+1,esize];</line>
<line>        result1 = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3,e*2,esize],element2,element1, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>        result2 = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3,e*2+1,esize],element4,element3, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e*2,esize] = result1;</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e*2+1,esize] = result2;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcmla_s.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCMLA_s" title="VCMLA (by element) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCMLA" />
  </docvars>
  <heading>VCMLA (by element)</heading>
  <desc>
    <brief>
      <para>Vector Complex Multiply Accumulate (by element)</para>
    </brief>
    <authored>
      <para>Vector Complex Multiply Accumulate (by element).</para>
      <para>This instruction operates on complex numbers that are represented in SIMD&amp;FP registers as pairs of elements, with the more significant element holding the imaginary part of the number and the less significant element holding the real part of the number. Each element holds a floating-point value. It performs the following computation on complex numbers from the first source register and the destination register with the specified complex number from the second source register:</para>
      <list type="unordered">
        <listitem><content>Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees.</content></listitem>
        <listitem><content>The two elements of the transformed complex number are multiplied by:<list type="unordered"><listitem><content>The real element of the complex number from the first source register, if the transformation was a rotation by 0 or 180 degrees.</content></listitem><listitem><content>The imaginary element of the complex number from the first source register, if the transformation was a rotation by 90 or 270 degrees.</content></listitem></list></content></listitem>
        <listitem><content>The complex number resulting from that multiplication is added to the complex number from the destination register.</content></listitem>
      </list>
      <para>The multiplication and addition operations are performed as a fused multiply-add, without any intermediate rounding.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCMLA" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.3" feature="FEAT_FCMA" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VCMLA_idx/A1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="rot" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCMLA_s_A1_DH" oneofinclass="4" oneof="8" label="64-bit SIMD vector of half-precision floating-point" bitdiffs="S == 0 &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCMLA" />
          <docvar key="mnemonic-fpdatasize" value="VCMLA-halfprec" />
          <docvar key="simd-fp-type" value="double-halfprec" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="23" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>], #</text><a link="sa_rotate" hover="Rotation applied to elements in the second SIMD&amp;FP source register (field &quot;rot&quot;) [0,90,180,270]">&lt;rotate&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCMLA_s_A1_DS" oneofinclass="4" oneof="8" label="64-bit SIMD vector of single-precision floating-point" bitdiffs="S == 1 &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCMLA" />
          <docvar key="mnemonic-fpdatasize" value="VCMLA-singleprec" />
          <docvar key="simd-fp-type" value="double-singleprec" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="23" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_1" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>[0], #</text><a link="sa_rotate" hover="Rotation applied to elements in the second SIMD&amp;FP source register (field &quot;rot&quot;) [0,90,180,270]">&lt;rotate&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCMLA_s_A1_QH" oneofinclass="4" oneof="8" label="128-bit SIMD vector of half-precision floating-point" bitdiffs="S == 0 &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCMLA" />
          <docvar key="mnemonic-fpdatasize" value="VCMLA-halfprec" />
          <docvar key="simd-fp-type" value="quad-halfprec" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="23" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>], #</text><a link="sa_rotate" hover="Rotation applied to elements in the second SIMD&amp;FP source register (field &quot;rot&quot;) [0,90,180,270]">&lt;rotate&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCMLA_s_A1_QS" oneofinclass="4" oneof="8" label="128-bit SIMD vector of single-precision floating-point" bitdiffs="S == 1 &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCMLA" />
          <docvar key="mnemonic-fpdatasize" value="VCMLA-singleprec" />
          <docvar key="simd-fp-type" value="quad-singleprec" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="23" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm_1" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>[0], #</text><a link="sa_rotate" hover="Rotation applied to elements in the second SIMD&amp;FP source register (field &quot;rot&quot;) [0,90,180,270]">&lt;rotate&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCMLA_idx/A1_A.txt" mylink="aarch32.instrs.VCMLA_idx.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveFCADDExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveFCADDExt()">HaveFCADDExt</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>m = if S=='1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);</line>
<line>esize = 16 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(S);</line>
<line>if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() &amp;&amp; esize == 16 then UNDEFINED;</line>
<line>elements = 64 DIV esize;</line>
<line>regs = if Q == '0' then 1 else 2;</line>
<line>index = if S=='1' then 0 else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCMLA" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.3" feature="FEAT_FCMA" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VCMLA_idx/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="rot" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCMLA_s_T1_DH" oneofinclass="4" oneof="8" label="64-bit SIMD vector of half-precision floating-point" bitdiffs="S == 0 &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCMLA" />
          <docvar key="mnemonic-fpdatasize" value="VCMLA-halfprec" />
          <docvar key="simd-fp-type" value="double-halfprec" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="23" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>], #</text><a link="sa_rotate" hover="Rotation applied to elements in the second SIMD&amp;FP source register (field &quot;rot&quot;) [0,90,180,270]">&lt;rotate&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCMLA_s_T1_DS" oneofinclass="4" oneof="8" label="64-bit SIMD vector of single-precision floating-point" bitdiffs="S == 1 &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCMLA" />
          <docvar key="mnemonic-fpdatasize" value="VCMLA-singleprec" />
          <docvar key="simd-fp-type" value="double-singleprec" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="23" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_1" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>[0], #</text><a link="sa_rotate" hover="Rotation applied to elements in the second SIMD&amp;FP source register (field &quot;rot&quot;) [0,90,180,270]">&lt;rotate&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCMLA_s_T1_QH" oneofinclass="4" oneof="8" label="128-bit SIMD vector of half-precision floating-point" bitdiffs="S == 0 &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCMLA" />
          <docvar key="mnemonic-fpdatasize" value="VCMLA-halfprec" />
          <docvar key="simd-fp-type" value="quad-halfprec" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="23" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>], #</text><a link="sa_rotate" hover="Rotation applied to elements in the second SIMD&amp;FP source register (field &quot;rot&quot;) [0,90,180,270]">&lt;rotate&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCMLA_s_T1_QS" oneofinclass="4" oneof="8" label="128-bit SIMD vector of single-precision floating-point" bitdiffs="S == 1 &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCMLA" />
          <docvar key="mnemonic-fpdatasize" value="VCMLA-singleprec" />
          <docvar key="simd-fp-type" value="quad-singleprec" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="23" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm_1" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>[0], #</text><a link="sa_rotate" hover="Rotation applied to elements in the second SIMD&amp;FP source register (field &quot;rot&quot;) [0,90,180,270]">&lt;rotate&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCMLA_idx/T1_A.txt" mylink="aarch32.instrs.VCMLA_idx.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveFCADDExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveFCADDExt()">HaveFCADDExt</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>m = if S=='1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);</line>
<line>esize = 16 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(S);</line>
<line>if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() &amp;&amp; esize == 16 then UNDEFINED;</line>
<line>elements = 64 DIV esize;</line>
<line>regs = if Q == '0' then 1 else 2;</line>
<line>index = if S=='1' then 0 else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCMLA_s_A1_DH, VCMLA_s_T1_DH" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMLA_s_A1_QH, VCMLA_s_T1_QH" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMLA_s_A1_QH, VCMLA_s_T1_QH" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMLA_s_A1_DH, VCMLA_s_T1_DH" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMLA_s_A1_DH, VCMLA_s_T1_DH" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMLA_s_A1_DH, VCMLA_s_A1_QH, VCMLA_s_T1_DH, VCMLA_s_T1_QH" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="Vm">
        <docvars>
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="mnemonic-fpdatasize" value="VCMLA-halfprec" />
        </docvars>
        <intro>
          <para>For the half-precision scalar variant: is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMLA_s_A1_DS, VCMLA_s_A1_QS, VCMLA_s_T1_DS, VCMLA_s_T1_QS" symboldefcount="2">
      <symbol link="sa_dm_1">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <docvars>
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="mnemonic-fpdatasize" value="VCMLA-singleprec" />
        </docvars>
        <intro>
          <para>For the single-precision scalar variant: is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMLA_s_A1_DH, VCMLA_s_T1_DH" symboldefcount="1">
      <symbol link="sa_index">&lt;index&gt;</symbol>
      <account encodedin="M">
        <intro>
          <para>Is the element index in the range 0 to 1, encoded in the "M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMLA_s_A1_DH, VCMLA_s_T1_DH" symboldefcount="1">
      <symbol link="sa_rotate">&lt;rotate&gt;</symbol>
      <definition encodedin="rot">
        <intro>Is the rotation to be applied to elements in the second SIMD&amp;FP source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">rot</entry>
                <entry class="symbol">&lt;rotate&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">0</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">90</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">180</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">270</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCMLA_idx/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations();</line>
<line><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>for r = 0 to regs-1</line>
<line>    operand1 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r];</line>
<line>    operand2 = <a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m];</line>
<line>    operand3 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r];</line>
<line>    for e = 0 to (elements DIV 2)-1</line>
<line>        bits(esize) element1;</line>
<line>        bits(esize) element2;</line>
<line>        bits(esize) element3;</line>
<line>        bits(esize) element4;</line>
<line>        case rot of</line>
<line>            when '00'</line>
<line>                element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,index*2,esize];</line>
<line>                element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2,esize];</line>
<line>                element3 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,index*2+1,esize];</line>
<line>                element4 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2,esize];</line>
<line>            when '01'</line>
<line>                element1 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,index*2+1,esize]);</line>
<line>                element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2+1,esize];</line>
<line>                element3 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,index*2,esize];</line>
<line>                element4 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2+1,esize];</line>
<line>            when '10'</line>
<line>                element1 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,index*2,esize]);</line>
<line>                element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2,esize];</line>
<line>                element3 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,index*2+1,esize]);</line>
<line>                element4 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2,esize];</line>
<line>            when '11'</line>
<line>                element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,index*2+1,esize];</line>
<line>                element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2+1,esize];</line>
<line>                element3 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,index*2,esize]);</line>
<line>                element4 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2+1,esize];</line>
<line>        result1 = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3,e*2,esize],element2,element1, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>        result2 = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3,e*2+1,esize],element4,element3,<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e*2,esize] = result1;</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e*2+1,esize] = result2;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcmp.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCMP" title="VCMP -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCMP" />
  </docvars>
  <heading>VCMP</heading>
  <desc>
    <brief>
      <para>Vector Compare</para>
    </brief>
    <authored>
      <para>Vector Compare compares two floating-point registers, or one floating-point register and zero. It writes the result to the <xref linkend="AArch32.fpscr">FPSCR</xref> flags. These are normally transferred to the <xref linkend="BEIDIGBH">PSTATE</xref>.{N, Z, C, V} Condition flags by a subsequent <instruction>VMRS</instruction> instruction.</para>
      <para>This instruction raises an Invalid Operation floating-point exception if either or both of the operands is a signaling NaN.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>The IEEE 754 standard specifies that the result of a comparison is precisely one of &lt;, ==, &gt; or unordered.  If either or both of the operands is a NaN, they are unordered, and all three of (Operand1 &lt; Operand2), (Operand1 == Operand2) and (Operand1 &gt; Operand2) are false. An unordered comparison sets the <xref linkend="AArch32.fpscr">FPSCR</xref> condition flags to N=0, Z=0, C=1, and V=1.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCMP" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCMP/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="E" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCMP_A1_H" oneofinclass="3" oneof="12" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCMP" />
          <docvar key="mnemonic-fpdatasize" value="VCMP-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCMP_A1_S" oneofinclass="3" oneof="12" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCMP" />
          <docvar key="mnemonic-fpdatasize" value="VCMP-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCMP_A1_D" oneofinclass="3" oneof="12" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCMP" />
          <docvar key="mnemonic-fpdatasize" value="VCMP-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCMP/A1_A.txt" mylink="aarch32.instrs.VCMP.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>quiet_nan_exc = (E == '1');  with_zero = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCMP" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCMP/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="E" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="VCMP_A2_H" oneofinclass="3" oneof="12" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCMP" />
          <docvar key="mnemonic-fpdatasize" value="VCMP-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, #0.0</text></asmtemplate>
      </encoding>
      <encoding name="VCMP_A2_S" oneofinclass="3" oneof="12" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCMP" />
          <docvar key="mnemonic-fpdatasize" value="VCMP-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, #0.0</text></asmtemplate>
      </encoding>
      <encoding name="VCMP_A2_D" oneofinclass="3" oneof="12" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCMP" />
          <docvar key="mnemonic-fpdatasize" value="VCMP-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #0.0</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCMP/A2_A.txt" mylink="aarch32.instrs.VCMP.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>quiet_nan_exc = (E == '1');  with_zero = TRUE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCMP" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCMP/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="E" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCMP_T1_H" oneofinclass="3" oneof="12" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCMP" />
          <docvar key="mnemonic-fpdatasize" value="VCMP-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCMP_T1_S" oneofinclass="3" oneof="12" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCMP" />
          <docvar key="mnemonic-fpdatasize" value="VCMP-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCMP_T1_D" oneofinclass="3" oneof="12" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCMP" />
          <docvar key="mnemonic-fpdatasize" value="VCMP-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCMP/T1_A.txt" mylink="aarch32.instrs.VCMP.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>quiet_nan_exc = (E == '1');  with_zero = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCMP" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCMP/T2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="E" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="VCMP_T2_H" oneofinclass="3" oneof="12" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCMP" />
          <docvar key="mnemonic-fpdatasize" value="VCMP-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, #0.0</text></asmtemplate>
      </encoding>
      <encoding name="VCMP_T2_S" oneofinclass="3" oneof="12" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCMP" />
          <docvar key="mnemonic-fpdatasize" value="VCMP-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, #0.0</text></asmtemplate>
      </encoding>
      <encoding name="VCMP_T2_D" oneofinclass="3" oneof="12" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCMP" />
          <docvar key="mnemonic-fpdatasize" value="VCMP-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCMP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #0.0</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCMP/T2_A.txt" mylink="aarch32.instrs.VCMP.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>quiet_nan_exc = (E == '1');  with_zero = TRUE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCMP_A1_H, VCMP_A2_H, VCMP_T1_H, VCMP_T2_H" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMP_A1_H, VCMP_A2_H, VCMP_T1_H, VCMP_T2_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMP_A1_H, VCMP_A2_H, VCMP_T1_H, VCMP_T2_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMP_A1_H, VCMP_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMP_A1_D, VCMP_A2_D, VCMP_T1_D, VCMP_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMP_A1_D, VCMP_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCMP/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    bits(4) nzcv;</line>
<line>    case esize of</line>
<line>        when 16</line>
<line>            bits(16) op16 = if with_zero then <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>('0', 16) else <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;;</line>
<line>            nzcv = <a link="impl-shared.FPCompare.4" file="shared_pseudocode.xml" hover="function: bits(4) FPCompare(bits(N) op1, bits(N) op2, boolean signal_nans, FPCRType fpcr)">FPCompare</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]&lt;15:0&gt;, op16, quiet_nan_exc, FPSCR[]);</line>
<line>        when 32</line>
<line>            bits(32) op32 = if with_zero then <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>('0', 32) else <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m];</line>
<line>            nzcv = <a link="impl-shared.FPCompare.4" file="shared_pseudocode.xml" hover="function: bits(4) FPCompare(bits(N) op1, bits(N) op2, boolean signal_nans, FPCRType fpcr)">FPCompare</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d], op32, quiet_nan_exc, FPSCR[]);</line>
<line>        when 64</line>
<line>            bits(64) op64 = if with_zero then <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>('0', 64) else <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m];</line>
<line>            nzcv = <a link="impl-shared.FPCompare.4" file="shared_pseudocode.xml" hover="function: bits(4) FPCompare(bits(N) op1, bits(N) op2, boolean signal_nans, FPCRType fpcr)">FPCompare</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d], op64, quiet_nan_exc, FPSCR[]);</line>
<line></line>
<line>    FPSCR&lt;31:28&gt; = nzcv; // FPSCR.&lt;N,Z,C,V&gt; set to nzcv</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcmpe.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCMPE" title="VCMPE -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCMPE" />
  </docvars>
  <heading>VCMPE</heading>
  <desc>
    <brief>
      <para>Vector Compare, raising Invalid Operation on NaN</para>
    </brief>
    <authored>
      <para>Vector Compare, raising Invalid Operation on NaN compares two floating-point registers, or one floating-point register and zero. It writes the result to the <xref linkend="AArch32.fpscr">FPSCR</xref> flags. These are normally transferred to the <xref linkend="BEIDIGBH">PSTATE</xref>.{N, Z, C, V} Condition flags by a subsequent <instruction>VMRS</instruction> instruction.</para>
      <para>This instruction raises an Invalid Operation floating-point exception if either or both of the operands is any type of NaN.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>The IEEE 754 standard specifies that the result of a comparison is precisely one of &lt;, ==, &gt; or unordered.  If either or both of the operands is a NaN, they are unordered, and all three of (Operand1 &lt; Operand2), (Operand1 == Operand2) and (Operand1 &gt; Operand2) are false. An unordered comparison sets the <xref linkend="AArch32.fpscr">FPSCR</xref> condition flags to N=0, Z=0, C=1, and V=1.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCMPE" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCMP/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="E" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCMPE_A1_H" oneofinclass="3" oneof="12" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCMPE" />
          <docvar key="mnemonic-fpdatasize" value="VCMPE-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCMPE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCMPE_A1_S" oneofinclass="3" oneof="12" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCMPE" />
          <docvar key="mnemonic-fpdatasize" value="VCMPE-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCMPE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCMPE_A1_D" oneofinclass="3" oneof="12" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCMPE" />
          <docvar key="mnemonic-fpdatasize" value="VCMPE-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCMPE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCMP/A1_A.txt" mylink="aarch32.instrs.VCMP.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>quiet_nan_exc = (E == '1');  with_zero = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCMPE" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCMP/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="E" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="VCMPE_A2_H" oneofinclass="3" oneof="12" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCMPE" />
          <docvar key="mnemonic-fpdatasize" value="VCMPE-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCMPE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, #0.0</text></asmtemplate>
      </encoding>
      <encoding name="VCMPE_A2_S" oneofinclass="3" oneof="12" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCMPE" />
          <docvar key="mnemonic-fpdatasize" value="VCMPE-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCMPE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, #0.0</text></asmtemplate>
      </encoding>
      <encoding name="VCMPE_A2_D" oneofinclass="3" oneof="12" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCMPE" />
          <docvar key="mnemonic-fpdatasize" value="VCMPE-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCMPE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #0.0</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCMP/A2_A.txt" mylink="aarch32.instrs.VCMP.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>quiet_nan_exc = (E == '1');  with_zero = TRUE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCMPE" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCMP/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="E" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCMPE_T1_H" oneofinclass="3" oneof="12" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCMPE" />
          <docvar key="mnemonic-fpdatasize" value="VCMPE-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCMPE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCMPE_T1_S" oneofinclass="3" oneof="12" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCMPE" />
          <docvar key="mnemonic-fpdatasize" value="VCMPE-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCMPE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCMPE_T1_D" oneofinclass="3" oneof="12" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCMPE" />
          <docvar key="mnemonic-fpdatasize" value="VCMPE-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCMPE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCMP/T1_A.txt" mylink="aarch32.instrs.VCMP.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>quiet_nan_exc = (E == '1');  with_zero = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCMPE" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCMP/T2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="E" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="VCMPE_T2_H" oneofinclass="3" oneof="12" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCMPE" />
          <docvar key="mnemonic-fpdatasize" value="VCMPE-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCMPE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, #0.0</text></asmtemplate>
      </encoding>
      <encoding name="VCMPE_T2_S" oneofinclass="3" oneof="12" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCMPE" />
          <docvar key="mnemonic-fpdatasize" value="VCMPE-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCMPE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, #0.0</text></asmtemplate>
      </encoding>
      <encoding name="VCMPE_T2_D" oneofinclass="3" oneof="12" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCMPE" />
          <docvar key="mnemonic-fpdatasize" value="VCMPE-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCMPE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #0.0</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCMP/T2_A.txt" mylink="aarch32.instrs.VCMP.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>quiet_nan_exc = (E == '1');  with_zero = TRUE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCMPE_A1_H, VCMPE_A2_H, VCMPE_T1_H, VCMPE_T2_H" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMPE_A1_H, VCMPE_A2_H, VCMPE_T1_H, VCMPE_T2_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMPE_A1_H, VCMPE_A2_H, VCMPE_T1_H, VCMPE_T2_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMPE_A1_H, VCMPE_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMPE_A1_D, VCMPE_A2_D, VCMPE_T1_D, VCMPE_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMPE_A1_D, VCMPE_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCMP/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    bits(4) nzcv;</line>
<line>    case esize of</line>
<line>        when 16</line>
<line>            bits(16) op16 = if with_zero then <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>('0', 16) else <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;;</line>
<line>            nzcv = <a link="impl-shared.FPCompare.4" file="shared_pseudocode.xml" hover="function: bits(4) FPCompare(bits(N) op1, bits(N) op2, boolean signal_nans, FPCRType fpcr)">FPCompare</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]&lt;15:0&gt;, op16, quiet_nan_exc, FPSCR[]);</line>
<line>        when 32</line>
<line>            bits(32) op32 = if with_zero then <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>('0', 32) else <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m];</line>
<line>            nzcv = <a link="impl-shared.FPCompare.4" file="shared_pseudocode.xml" hover="function: bits(4) FPCompare(bits(N) op1, bits(N) op2, boolean signal_nans, FPCRType fpcr)">FPCompare</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d], op32, quiet_nan_exc, FPSCR[]);</line>
<line>        when 64</line>
<line>            bits(64) op64 = if with_zero then <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>('0', 64) else <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m];</line>
<line>            nzcv = <a link="impl-shared.FPCompare.4" file="shared_pseudocode.xml" hover="function: bits(4) FPCompare(bits(N) op1, bits(N) op2, boolean signal_nans, FPCRType fpcr)">FPCompare</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d], op64, quiet_nan_exc, FPSCR[]);</line>
<line></line>
<line>    FPSCR&lt;31:28&gt; = nzcv; // FPSCR.&lt;N,Z,C,V&gt; set to nzcv</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcnt.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCNT" title="VCNT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCNT" />
  </docvars>
  <heading>VCNT</heading>
  <desc>
    <brief>
      <para>Vector Count Set Bits</para>
    </brief>
    <authored>
      <para>Vector Count Set Bits counts the number of bits that are one in each element in a vector, and places the results in a second vector.</para>
      <para>The operand vector elements must be 8-bit fields.</para>
      <para>The result vector elements are 8-bit integers.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCNT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCNT/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCNT_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCNT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate comment="Encoded as Q = 0"><text>VCNT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.8 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCNT_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCNT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate comment="Encoded as Q = 1"><text>VCNT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.8 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCNT/T1A1_A.txt" mylink="aarch32.instrs.VCNT.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size != '00' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>esize = 8;  elements = 8;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCNT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCNT/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCNT_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCNT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate comment="Encoded as Q = 0"><text>VCNT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.8 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCNT_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCNT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate comment="Encoded as Q = 1"><text>VCNT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.8 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCNT/T1A1_A.txt" mylink="aarch32.instrs.VCNT.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size != '00' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>esize = 8;  elements = 8;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCNT_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCNT_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCNT_A1_Q, VCNT_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCNT_A1_Q, VCNT_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCNT_A1_Q, VCNT_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCNT_A1_D, VCNT_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCNT_A1_D, VCNT_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCNT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize])&lt;esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcvt_bfs.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCVT_bfs" title="VCVT (from single-precision to BFloat16, Advanced SIMD) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCVT" />
  </docvars>
  <heading>VCVT (from single-precision to BFloat16, Advanced SIMD)</heading>
  <desc>
    <brief>
      <para>Vector Convert from single-precision to BFloat16</para>
    </brief>
    <authored>
      <para>Vector Convert from single-precision to BFloat16 converts each 32-bit element in a vector from single-precision floating-point to BFloat16 format, and writes the result into a second vector. The result vector elements are half the width of the source vector elements.</para>
      <para>Unlike the BFloat16 multiplication instructions, this instruction uses the Round to Nearest rounding mode, and can generate a floating-point exception that causes cumulative exception bits in the <xref linkend="AArch32.fpscr">FPSCR</xref> to be set.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCVT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VCVT/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVT_bfs_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
        </docvars>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16.F32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVT/T1A1_A.txt" mylink="aarch32.instrs.VCVT.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;</line>
<line>if Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCVT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VCVT/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVT_bfs_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
        </docvars>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16.F32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVT/T1A1_A.txt" mylink="aarch32.instrs.VCVT.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;</line>
<line>if Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVT_bfs_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_bfs_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_bfs_A1, VCVT_bfs_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_bfs_A1, VCVT_bfs_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_bfs_A1, VCVT_bfs_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCVT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>bits(128) operand;</line>
<line>bits(64) result;</line>
<line></line>
<line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>    operand = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1];</line>
<line>    for e = 0 to 3</line>
<line>        bits(32) op = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 32];</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 16] = <a link="impl-shared.FPConvertBF.2" file="shared_pseudocode.xml" hover="function: bits(16) FPConvertBF(bits(32) op, FPCRType fpcr)">FPConvertBF</a>(op, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcvt_ds.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCVT_ds" title="VCVT (between double-precision and single-precision) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCVT" />
  </docvars>
  <heading>VCVT (between double-precision and single-precision)</heading>
  <desc>
    <brief>
      <para>Convert between double-precision and single-precision</para>
    </brief>
    <authored>
      <para>Convert between double-precision and single-precision does one of the following:</para>
      <list type="unordered">
        <listitem><content>Converts the value in a double-precision register to single-precision and writes the result to a single-precision register.</content></listitem>
        <listitem><content>Converts the value in a single-precision register to double-precision and writes the result to a double-precision register.</content></listitem>
      </list>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCVT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCVT_ds/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="1">
          <c>1</c>
          <c>x</c>
        </box>
        <box hibit="7" name="o3" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVT_ds_A1" oneofinclass="2" oneof="4" label="Single-precision to double-precision" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="convert-type" value="single-to-double" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
        </docvars>
        <box hibit="9" width="" name="size">
          <c></c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64.F32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_sd_A1" oneofinclass="2" oneof="4" label="Double-precision to single-precision" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="convert-type" value="double-to-single" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
        </docvars>
        <box hibit="9" width="" name="size">
          <c></c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVT_ds/T1A1_A.txt" mylink="aarch32.instrs.VCVT_ds.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>double_to_single = (size == '11');</line>
<line>d = if double_to_single then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>m = if double_to_single then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCVT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCVT_ds/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="1">
          <c>1</c>
          <c>x</c>
        </box>
        <box hibit="7" name="o3" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVT_ds_T1" oneofinclass="2" oneof="4" label="Single-precision to double-precision" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="convert-type" value="single-to-double" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
        </docvars>
        <box hibit="9" width="" name="size">
          <c></c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64.F32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_sd_T1" oneofinclass="2" oneof="4" label="Double-precision to single-precision" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="convert-type" value="double-to-single" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
        </docvars>
        <box hibit="9" width="" name="size">
          <c></c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVT_ds/T1A1_A.txt" mylink="aarch32.instrs.VCVT_ds.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>double_to_single = (size == '11');</line>
<line>d = if double_to_single then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>m = if double_to_single then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVT_ds_A1, VCVT_ds_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_ds_A1, VCVT_ds_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_sd_A1, VCVT_sd_T1" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_sd_A1, VCVT_sd_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_ds_A1, VCVT_ds_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_ds_A1, VCVT_ds_T1" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCVT_ds/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    if double_to_single then</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPConvert.3" file="shared_pseudocode.xml" hover="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, integer M)">FPConvert</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[], 32);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPConvert.3" file="shared_pseudocode.xml" hover="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, integer M)">FPConvert</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[], 64);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcvt_hs.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCVT_hs" title="VCVT (between half-precision and single-precision, Advanced SIMD) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCVT" />
  </docvars>
  <heading>VCVT (between half-precision and single-precision, Advanced SIMD)</heading>
  <desc>
    <brief>
      <para>Vector Convert between half-precision and single-precision</para>
    </brief>
    <authored>
      <para>Vector Convert between half-precision and single-precision converts each element in a vector from single-precision to half-precision floating-point, or from half-precision to single-precision, and places the results in a second vector.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCVT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCVT_hs/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVT_sh_A1" oneofinclass="2" oneof="4" label="Half-precision to single-precision" bitdiffs="op == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="convert-type" value="half-to-single" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
        </docvars>
        <box hibit="8" width="1" name="op">
          <c>1</c>
        </box>
        <asmtemplate comment="Encoded as op = 1"><text>VCVT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32.F16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_hs_A1" oneofinclass="2" oneof="4" label="Single-precision to half-precision" bitdiffs="op == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="convert-type" value="single-to-half" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
        </docvars>
        <box hibit="8" width="1" name="op">
          <c>0</c>
        </box>
        <asmtemplate comment="Encoded as op = 0"><text>VCVT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16.F32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVT_hs/T1A1_A.txt" mylink="aarch32.instrs.VCVT_hs.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size != '01' then UNDEFINED;</line>
<line>half_to_single = (op == '1');</line>
<line>if half_to_single &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>if !half_to_single &amp;&amp; Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>esize = 16;  elements = 4;</line>
<line>m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCVT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCVT_hs/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVT_sh_T1" oneofinclass="2" oneof="4" label="Half-precision to single-precision" bitdiffs="op == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="convert-type" value="half-to-single" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
        </docvars>
        <box hibit="8" width="1" name="op">
          <c>1</c>
        </box>
        <asmtemplate comment="Encoded as op = 1"><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32.F16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_hs_T1" oneofinclass="2" oneof="4" label="Single-precision to half-precision" bitdiffs="op == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="convert-type" value="single-to-half" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
        </docvars>
        <box hibit="8" width="1" name="op">
          <c>0</c>
        </box>
        <asmtemplate comment="Encoded as op = 0"><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16.F32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVT_hs/T1A1_A.txt" mylink="aarch32.instrs.VCVT_hs.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size != '01' then UNDEFINED;</line>
<line>half_to_single = (op == '1');</line>
<line>if half_to_single &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>if !half_to_single &amp;&amp; Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>esize = 16;  elements = 4;</line>
<line>m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVT_hs_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_hs_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_hs_A1, VCVT_hs_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_sh_A1, VCVT_sh_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_sh_A1, VCVT_sh_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_hs_A1, VCVT_hs_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_hs_A1, VCVT_hs_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCVT_hs/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for e = 0 to elements-1</line>
<line>        if half_to_single then</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,32] = <a link="impl-shared.FPConvert.3" file="shared_pseudocode.xml" hover="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, integer M)">FPConvert</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m],e,16], <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>(), 32);</line>
<line>        else</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d],e,16] = <a link="impl-shared.FPConvert.3" file="shared_pseudocode.xml" hover="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, integer M)">FPConvert</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[m&gt;&gt;1],e,32], <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>(), 16);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcvt_is.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCVT_is" title="VCVT (between floating-point and integer, Advanced SIMD) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCVT" />
  </docvars>
  <heading>VCVT (between floating-point and integer, Advanced SIMD)</heading>
  <desc>
    <brief>
      <para>Vector Convert between floating-point and integer</para>
    </brief>
    <authored>
      <para>Vector Convert between floating-point and integer converts each element in a vector from floating-point to integer, or from integer to floating-point, and places the results in a second vector.</para>
      <para>The vector elements are the same type, and are floating-point numbers or integers. Signed and unsigned integers are distinct.</para>
      <para>The floating-point to integer operation uses the Round towards Zero rounding mode. The integer to floating-point operation uses the Round to Nearest rounding mode.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCVT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCVT_is/A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" width="2" name="op" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVT_is_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt1" hover="Data type for elements of destination vector (field &quot;size:op&quot;)">&lt;dt1&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;size:op&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_is_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt1" hover="Data type for elements of destination vector (field &quot;size:op&quot;)">&lt;dt1&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;size:op&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVT_is/A1_A.txt" mylink="aarch32.instrs.VCVT_is.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size IN {'00', '11'} then UNDEFINED;</line>
<line>to_integer = (op&lt;1&gt; == '1');  unsigned = (op&lt;0&gt; == '1');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCVT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCVT_is/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" width="2" name="op" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVT_is_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt1" hover="Data type for elements of destination vector (field &quot;size:op&quot;)">&lt;dt1&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;size:op&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_is_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt1" hover="Data type for elements of destination vector (field &quot;size:op&quot;)">&lt;dt1&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;size:op&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVT_is/T1_A.txt" mylink="aarch32.instrs.VCVT_is.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size IN {'00', '11'} then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>to_integer = (op&lt;1&gt; == '1');  unsigned = (op&lt;0&gt; == '1');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVT_is_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_is_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_is_A1_Q, VCVT_is_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_is_A1_Q, VCVT_is_T1_Q" symboldefcount="1">
      <symbol link="sa_dt1">&lt;dt1&gt;</symbol>
      <definition encodedin="size:op">
        <intro>Is the data type for the elements of the destination vector, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="bitfield">op</entry>
                <entry class="symbol">&lt;dt1&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="bitfield">0x</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="bitfield">0x</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VCVT_is_A1_Q, VCVT_is_T1_Q" symboldefcount="1">
      <symbol link="sa_dt2">&lt;dt2&gt;</symbol>
      <definition encodedin="size:op">
        <intro>Is the data type for the elements of the source vector, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="bitfield">op</entry>
                <entry class="symbol">&lt;dt2&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="bitfield">1x</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U32</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="bitfield">1x</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VCVT_is_A1_Q, VCVT_is_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_is_A1_Q, VCVT_is_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_is_A1_D, VCVT_is_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_is_A1_D, VCVT_is_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCVT_is/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    bits(esize) result;</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize];</line>
<line>            if to_integer then</line>
<line>                result = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(op1, 0, unsigned, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>(),</line>
<line>                                   <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>, esize);</line>
<line>            else</line>
<line>                result = <a link="impl-shared.FixedToFP.6" file="shared_pseudocode.xml" hover="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer N)">FixedToFP</a>(op1, 0, unsigned, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>(),</line>
<line>                                   <a link="FPRounding_TIEEVEN" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEEVEN</a>, esize);</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcvt_iv.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCVT_iv" title="VCVT (floating-point to integer, floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCVT" />
  </docvars>
  <heading>VCVT (floating-point to integer, floating-point)</heading>
  <desc>
    <brief>
      <para>Convert floating-point to integer with Round towards Zero</para>
    </brief>
    <authored>
      <para>Convert floating-point to integer with Round towards Zero converts a value in a register from floating-point to a 32-bit integer, using the Round towards Zero rounding mode, and places the result in a second register.</para>
      <para><xref linkend="A32T32-fpsimd.instructions.VCVT_xv">VCVT (between floating-point and fixed-point, floating-point)</xref> describes conversions between floating-point and 16-bit integers.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.fpdp">Floating-point data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.fpdp">Floating-point data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="6" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCVT" />
      </docvars>
      <iclassintro count="6"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCVT_iv/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="18" width="3" name="opc2" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
          <c>x</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVT_uiv_A1_H" oneofinclass="6" oneof="12" label="Half-precision scalar" bitdiffs="opc2 == 100 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U32.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_siv_A1_H" oneofinclass="6" oneof="12" label="Half-precision scalar" bitdiffs="opc2 == 101 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S32.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_uiv_A1_S" oneofinclass="6" oneof="12" label="Single-precision scalar" bitdiffs="opc2 == 100 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-singleprec" />
        </docvars>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U32.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_siv_A1_S" oneofinclass="6" oneof="12" label="Single-precision scalar" bitdiffs="opc2 == 101 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-singleprec" />
        </docvars>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S32.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_uiv_A1_D" oneofinclass="6" oneof="12" label="Double-precision scalar" bitdiffs="opc2 == 100 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-doubleprec" />
        </docvars>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U32.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_siv_A1_D" oneofinclass="6" oneof="12" label="Double-precision scalar" bitdiffs="opc2 == 101 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-doubleprec" />
        </docvars>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S32.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVT_iv/A1_A.txt" mylink="aarch32.instrs.VCVT_iv.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if opc2 != '000' &amp;&amp; !(opc2 IN {'10x'}) then SEE "Related encodings";</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>integer d;</line>
<line>integer esize;</line>
<line>integer m;</line>
<line>boolean unsigned;</line>
<line><a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding;</line>
<line>to_integer = (opc2&lt;2&gt; == '1');</line>
<line>if to_integer then</line>
<line>    unsigned = (opc2&lt;0&gt; == '0');</line>
<line>    rounding = if op == '1' then <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a> else <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPSCR[]);</line>
<line>    d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    case size of</line>
<line>        when '01' esize = 16; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>        when '10' esize = 32; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>        when '11' esize = 64; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>else</line>
<line>    unsigned = (op == '0');</line>
<line>    rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPSCR[]);</line>
<line>    m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    case size of</line>
<line>        when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>        when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>        when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="6" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCVT" />
      </docvars>
      <iclassintro count="6"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCVT_iv/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="18" width="3" name="opc2" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
          <c>x</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVT_uiv_T1_H" oneofinclass="6" oneof="12" label="Half-precision scalar" bitdiffs="opc2 == 100 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U32.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_siv_T1_H" oneofinclass="6" oneof="12" label="Half-precision scalar" bitdiffs="opc2 == 101 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S32.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_uiv_T1_S" oneofinclass="6" oneof="12" label="Single-precision scalar" bitdiffs="opc2 == 100 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-singleprec" />
        </docvars>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U32.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_siv_T1_S" oneofinclass="6" oneof="12" label="Single-precision scalar" bitdiffs="opc2 == 101 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-singleprec" />
        </docvars>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S32.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_uiv_T1_D" oneofinclass="6" oneof="12" label="Double-precision scalar" bitdiffs="opc2 == 100 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-doubleprec" />
        </docvars>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U32.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_siv_T1_D" oneofinclass="6" oneof="12" label="Double-precision scalar" bitdiffs="opc2 == 101 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-doubleprec" />
        </docvars>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S32.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVT_iv/T1_A.txt" mylink="aarch32.instrs.VCVT_iv.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if opc2 != '000' &amp;&amp; !(opc2 IN {'10x'}) then SEE "Related encodings";</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>integer esize;</line>
<line>integer m;</line>
<line>integer d;</line>
<line>boolean unsigned;</line>
<line><a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding;</line>
<line>to_integer = (opc2&lt;2&gt; == '1');</line>
<line>if to_integer then</line>
<line>    unsigned = (opc2&lt;0&gt; == '0');</line>
<line>    rounding = if op == '1' then <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a> else <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPSCR[]);</line>
<line>    d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    case size of</line>
<line>        when '01' esize = 16; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>        when '10' esize = 32; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>        when '11' esize = 64; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>else</line>
<line>    unsigned = (op == '0');</line>
<line>    rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPSCR[]);</line>
<line>    m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    case size of</line>
<line>        when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>        when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>        when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVT_uiv_A1_H, VCVT_uiv_T1_H" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_uiv_A1_H, VCVT_uiv_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_uiv_A1_H, VCVT_uiv_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_uiv_A1_H, VCVT_uiv_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_uiv_A1_D, VCVT_uiv_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCVT_iv/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    if to_integer then</line>
<line>        case esize of</line>
<line>            when 16</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, 0, unsigned, FPSCR[], rounding, 32);</line>
<line>            when 32</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], 0, unsigned, FPSCR[], rounding, 32);</line>
<line>            when 64</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], 0, unsigned, FPSCR[], rounding, 32);</line>
<line>    else</line>
<line>        case esize of</line>
<line>            when 16</line>
<line>                bits(16) fp16 = <a link="impl-shared.FixedToFP.6" file="shared_pseudocode.xml" hover="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer N)">FixedToFP</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], 0, unsigned, FPSCR[], rounding, 16);</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16):fp16;</line>
<line>            when 32</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FixedToFP.6" file="shared_pseudocode.xml" hover="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer N)">FixedToFP</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], 0, unsigned, FPSCR[], rounding, 32);</line>
<line>            when 64</line>
<line>                <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FixedToFP.6" file="shared_pseudocode.xml" hover="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer N)">FixedToFP</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], 0, unsigned, FPSCR[], rounding, 64);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcvt_vi.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCVT_vi" title="VCVT (integer to floating-point, floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCVT" />
  </docvars>
  <heading>VCVT (integer to floating-point, floating-point)</heading>
  <desc>
    <brief>
      <para>Convert integer to floating-point</para>
    </brief>
    <authored>
      <para>Convert integer to floating-point converts a 32-bit integer to floating-point using the rounding mode specified by the <xref linkend="AArch32.fpscr">FPSCR</xref>, and places the result in a second register.</para>
      <para><xref linkend="A32T32-fpsimd.instructions.VCVT_xv">VCVT (between floating-point and fixed-point, floating-point)</xref> describes conversions between floating-point and 16-bit integers.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.fpdp">Floating-point data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.fpdp">Floating-point data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCVT" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCVT_iv/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="18" width="3" name="opc2" usename="1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVT_vi_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16.</text><a link="sa_dt" hover="Data type for operand (field &quot;op&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_vi_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32.</text><a link="sa_dt" hover="Data type for operand (field &quot;op&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_vi_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64.</text><a link="sa_dt" hover="Data type for operand (field &quot;op&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVT_iv/A1_A.txt" mylink="aarch32.instrs.VCVT_iv.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if opc2 != '000' &amp;&amp; !(opc2 IN {'10x'}) then SEE "Related encodings";</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>integer d;</line>
<line>integer esize;</line>
<line>integer m;</line>
<line>boolean unsigned;</line>
<line><a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding;</line>
<line>to_integer = (opc2&lt;2&gt; == '1');</line>
<line>if to_integer then</line>
<line>    unsigned = (opc2&lt;0&gt; == '0');</line>
<line>    rounding = if op == '1' then <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a> else <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPSCR[]);</line>
<line>    d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    case size of</line>
<line>        when '01' esize = 16; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>        when '10' esize = 32; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>        when '11' esize = 64; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>else</line>
<line>    unsigned = (op == '0');</line>
<line>    rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPSCR[]);</line>
<line>    m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    case size of</line>
<line>        when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>        when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>        when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCVT" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCVT_iv/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="18" width="3" name="opc2" usename="1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVT_vi_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16.</text><a link="sa_dt" hover="Data type for operand (field &quot;op&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_vi_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32.</text><a link="sa_dt" hover="Data type for operand (field &quot;op&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_vi_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64.</text><a link="sa_dt" hover="Data type for operand (field &quot;op&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVT_iv/T1_A.txt" mylink="aarch32.instrs.VCVT_iv.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if opc2 != '000' &amp;&amp; !(opc2 IN {'10x'}) then SEE "Related encodings";</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>integer esize;</line>
<line>integer m;</line>
<line>integer d;</line>
<line>boolean unsigned;</line>
<line><a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding;</line>
<line>to_integer = (opc2&lt;2&gt; == '1');</line>
<line>if to_integer then</line>
<line>    unsigned = (opc2&lt;0&gt; == '0');</line>
<line>    rounding = if op == '1' then <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a> else <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPSCR[]);</line>
<line>    d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    case size of</line>
<line>        when '01' esize = 16; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>        when '10' esize = 32; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>        when '11' esize = 64; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>else</line>
<line>    unsigned = (op == '0');</line>
<line>    rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPSCR[]);</line>
<line>    m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    case size of</line>
<line>        when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>        when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>        when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVT_vi_A1_H, VCVT_vi_T1_H" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_vi_A1_H, VCVT_vi_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_vi_A1_H, VCVT_vi_T1_H" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="op">
        <intro>Is the data type for the operand, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">op</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">U32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">S32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VCVT_vi_A1_H, VCVT_vi_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_vi_A1_D, VCVT_vi_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_vi_A1_H, VCVT_vi_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCVT_iv/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    if to_integer then</line>
<line>        case esize of</line>
<line>            when 16</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, 0, unsigned, FPSCR[], rounding, 32);</line>
<line>            when 32</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], 0, unsigned, FPSCR[], rounding, 32);</line>
<line>            when 64</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], 0, unsigned, FPSCR[], rounding, 32);</line>
<line>    else</line>
<line>        case esize of</line>
<line>            when 16</line>
<line>                bits(16) fp16 = <a link="impl-shared.FixedToFP.6" file="shared_pseudocode.xml" hover="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer N)">FixedToFP</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], 0, unsigned, FPSCR[], rounding, 16);</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16):fp16;</line>
<line>            when 32</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FixedToFP.6" file="shared_pseudocode.xml" hover="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer N)">FixedToFP</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], 0, unsigned, FPSCR[], rounding, 32);</line>
<line>            when 64</line>
<line>                <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FixedToFP.6" file="shared_pseudocode.xml" hover="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer N)">FixedToFP</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], 0, unsigned, FPSCR[], rounding, 64);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcvt_xs.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCVT_xs" title="VCVT (between floating-point and fixed-point, Advanced SIMD) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCVT" />
  </docvars>
  <heading>VCVT (between floating-point and fixed-point, Advanced SIMD)</heading>
  <desc>
    <brief>
      <para>Vector Convert between floating-point and fixed-point</para>
    </brief>
    <authored>
      <para>Vector Convert between floating-point and fixed-point converts each element in a vector from floating-point to fixed-point, or from fixed-point to floating-point, and places the results in a second vector.</para>
      <para>The vector elements are the same type, and are floating-point numbers or integers. Signed and unsigned integers are distinct.</para>
      <para>The floating-point to fixed-point operation uses the Round towards Zero rounding mode. The fixed-point to floating-point operation uses the Round to Nearest rounding mode.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_1r_imm">Advanced SIMD one register and modified immediate</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd1reg_imm">Advanced SIMD one register and modified immediate</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCVT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCVT_xs/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="op" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVT_xs_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="imm6 != 000xxx &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="21" width="6" name="imm6">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt1" hover="Data type for elements of destination vector (field &quot;op:U&quot;)">&lt;dt1&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;op:U&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_fbits" hover="The number of fraction bits in the fixed point number [1-32 for 32-bit elements]">&lt;fbits&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_xs_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="imm6 != 000xxx &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="21" width="6" name="imm6">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt1" hover="Data type for elements of destination vector (field &quot;op:U&quot;)">&lt;dt1&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;op:U&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_fbits" hover="The number of fraction bits in the fixed point number [1-32 for 32-bit elements]">&lt;fbits&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVT_xs/A1_A.txt" mylink="aarch32.instrs.VCVT_xs.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if imm6 IN {'000xxx'} then SEE "Related encodings";</line>
<line>if op&lt;1&gt; == '0' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if op&lt;1&gt; == '0' &amp;&amp; imm6 IN {'10xxxx'} then UNDEFINED;</line>
<line>if imm6 IN {'0xxxxx'} then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>to_fixed = (op&lt;0&gt; == '1');  frac_bits = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>unsigned = (U == '1');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case op&lt;1&gt; of</line>
<line>    when '0' esize = 16; elements = 4;</line>
<line>    when '1' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCVT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCVT_xs/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="op" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVT_xs_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="imm6 != 000xxx &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="21" width="6" name="imm6">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt1" hover="Data type for elements of destination vector (field &quot;op:U&quot;)">&lt;dt1&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;op:U&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_fbits" hover="The number of fraction bits in the fixed point number [1-32 for 32-bit elements]">&lt;fbits&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_xs_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="imm6 != 000xxx &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="21" width="6" name="imm6">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt1" hover="Data type for elements of destination vector (field &quot;op:U&quot;)">&lt;dt1&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;op:U&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_fbits" hover="The number of fraction bits in the fixed point number [1-32 for 32-bit elements]">&lt;fbits&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVT_xs/T1_A.txt" mylink="aarch32.instrs.VCVT_xs.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if imm6 IN {'000xxx'} then SEE "Related encodings";</line>
<line>if op&lt;1&gt; == '0' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if op&lt;1&gt; == '0' &amp;&amp; imm6 IN {'10xxxx'} then UNDEFINED;</line>
<line>if imm6 IN {'0xxxxx'} then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>to_fixed = (op&lt;0&gt; == '1');  frac_bits = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>unsigned = (U == '1');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case op&lt;1&gt; of</line>
<line>    when '0' esize = 16; elements = 4;</line>
<line>    when '1' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVT_xs_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_xs_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_xs_A1_Q, VCVT_xs_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_xs_A1_Q, VCVT_xs_T1_Q" symboldefcount="1">
      <symbol link="sa_dt1">&lt;dt1&gt;</symbol>
      <definition encodedin="op:U">
        <intro>Is the data type for the elements of the destination vector, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">op</entry>
                <entry class="bitfield">U</entry>
                <entry class="symbol">&lt;dt1&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="bitfield">x</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="bitfield">x</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VCVT_xs_A1_Q, VCVT_xs_T1_Q" symboldefcount="1">
      <symbol link="sa_dt2">&lt;dt2&gt;</symbol>
      <definition encodedin="op:U">
        <intro>Is the data type for the elements of the source vector, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">op</entry>
                <entry class="bitfield">U</entry>
                <entry class="symbol">&lt;dt2&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="bitfield">x</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">U32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="bitfield">x</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VCVT_xs_A1_Q, VCVT_xs_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_xs_A1_Q, VCVT_xs_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_xs_A1_D, VCVT_xs_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_xs_A1_D, VCVT_xs_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_xs_A1_Q, VCVT_xs_T1_Q" symboldefcount="1">
      <symbol link="sa_fbits">&lt;fbits&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The number of fraction bits in the fixed point number, in the range 1 to 32 for 32-bit elements, or in the range 1 to 16 for 16-bit elements:</para>
          <list type="unordered">
            <listitem><content>(64 - <syntax>&lt;fbits&gt;</syntax>) is encoded in imm6.</content></listitem>
          </list>
          <para>An assembler can permit an <syntax>&lt;fbits&gt;</syntax> value of 0. This is encoded as floating-point to integer or integer to floating-point instruction, see <xref linkend="A32T32-fpsimd.instructions.VCVT_is">VCVT (between floating-point and integer, Advanced SIMD)</xref>.</para>
        </intro>
      </account>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCVT_xs/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    bits(esize) result;</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize];</line>
<line>            if to_fixed then</line>
<line>                result = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(op1, frac_bits, unsigned, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>(),</line>
<line>                                   <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>, esize);</line>
<line>            else</line>
<line>                result = <a link="impl-shared.FixedToFP.6" file="shared_pseudocode.xml" hover="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer N)">FixedToFP</a>(op1, frac_bits, unsigned, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>(),</line>
<line>                                   <a link="FPRounding_TIEEVEN" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEEVEN</a>, esize);</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcvt_xv.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCVT_xv" title="VCVT (between floating-point and fixed-point, floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCVT" />
  </docvars>
  <heading>VCVT (between floating-point and fixed-point, floating-point)</heading>
  <desc>
    <brief>
      <para>Convert between floating-point and fixed-point</para>
    </brief>
    <authored>
      <para>Convert between floating-point and fixed-point converts a value in a register from floating-point to fixed-point, or from fixed-point to floating-point. Software can specify the fixed-point value as either signed or unsigned.</para>
      <para>The fixed-point value can be 16-bit or 32-bit. Conversions from fixed-point values take their operand from the low-order bits of the source register and ignore any remaining bits. Signed conversions to fixed-point values sign-extend the result value to the destination register width. Unsigned conversions to fixed-point values zero-extend the result value to the destination register width.</para>
      <para>The floating-point to fixed-point operation uses the Round towards Zero rounding mode. The fixed-point to floating-point operation uses the Round to Nearest rounding mode.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGDIADD">VCVT (between floating-point and fixed-point)</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="6" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCVT" />
      </docvars>
      <iclassintro count="6"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCVT_xv/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="18" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="17" settings="1">
          <c>1</c>
        </box>
        <box hibit="16" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="sf" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="sx" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVT_toxv_A1_H" oneofinclass="6" oneof="12" label="Half-precision scalar" bitdiffs="op == 0 &amp;&amp; sf == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="18" width="1" name="op">
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="sf">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16.</text><a link="sa_dt" hover="Data type for fixed-point number (field &quot;U:sx&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_sdm" hover="32-bit SIMD&amp;FP destination and source register (field &quot;Vd:D&quot;)">&lt;Sdm&gt;</a><text>, </text><a link="sa_sdm" hover="32-bit SIMD&amp;FP destination and source register (field &quot;Vd:D&quot;)">&lt;Sdm&gt;</a><text>, #</text><a link="sa_fbits" hover="The number of fraction bits in the fixed-point number:&#10;* If {syntax{&lt;dt&gt;}} is {value{S16}} or {value{U16}}">&lt;fbits&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_xv_A1_H" oneofinclass="6" oneof="12" label="Half-precision scalar" bitdiffs="op == 1 &amp;&amp; sf == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="18" width="1" name="op">
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="sf">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for fixed-point number (field &quot;U:sx&quot;)">&lt;dt&gt;</a><text>.F16 </text><a link="sa_sdm" hover="32-bit SIMD&amp;FP destination and source register (field &quot;Vd:D&quot;)">&lt;Sdm&gt;</a><text>, </text><a link="sa_sdm" hover="32-bit SIMD&amp;FP destination and source register (field &quot;Vd:D&quot;)">&lt;Sdm&gt;</a><text>, #</text><a link="sa_fbits" hover="The number of fraction bits in the fixed-point number:&#10;* If {syntax{&lt;dt&gt;}} is {value{S16}} or {value{U16}}">&lt;fbits&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_toxv_A1_S" oneofinclass="6" oneof="12" label="Single-precision scalar" bitdiffs="op == 0 &amp;&amp; sf == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-singleprec" />
        </docvars>
        <box hibit="18" width="1" name="op">
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="sf">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32.</text><a link="sa_dt" hover="Data type for fixed-point number (field &quot;U:sx&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_sdm" hover="32-bit SIMD&amp;FP destination and source register (field &quot;Vd:D&quot;)">&lt;Sdm&gt;</a><text>, </text><a link="sa_sdm" hover="32-bit SIMD&amp;FP destination and source register (field &quot;Vd:D&quot;)">&lt;Sdm&gt;</a><text>, #</text><a link="sa_fbits" hover="The number of fraction bits in the fixed-point number:&#10;* If {syntax{&lt;dt&gt;}} is {value{S16}} or {value{U16}}">&lt;fbits&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_xv_A1_S" oneofinclass="6" oneof="12" label="Single-precision scalar" bitdiffs="op == 1 &amp;&amp; sf == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-singleprec" />
        </docvars>
        <box hibit="18" width="1" name="op">
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="sf">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for fixed-point number (field &quot;U:sx&quot;)">&lt;dt&gt;</a><text>.F32 </text><a link="sa_sdm" hover="32-bit SIMD&amp;FP destination and source register (field &quot;Vd:D&quot;)">&lt;Sdm&gt;</a><text>, </text><a link="sa_sdm" hover="32-bit SIMD&amp;FP destination and source register (field &quot;Vd:D&quot;)">&lt;Sdm&gt;</a><text>, #</text><a link="sa_fbits" hover="The number of fraction bits in the fixed-point number:&#10;* If {syntax{&lt;dt&gt;}} is {value{S16}} or {value{U16}}">&lt;fbits&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_toxv_A1_D" oneofinclass="6" oneof="12" label="Double-precision scalar" bitdiffs="op == 0 &amp;&amp; sf == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-doubleprec" />
        </docvars>
        <box hibit="18" width="1" name="op">
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="sf">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64.</text><a link="sa_dt" hover="Data type for fixed-point number (field &quot;U:sx&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_ddm" hover="64-bit SIMD&amp;FP destination and source register (field &quot;D:Vd&quot;)">&lt;Ddm&gt;</a><text>, </text><a link="sa_ddm" hover="64-bit SIMD&amp;FP destination and source register (field &quot;D:Vd&quot;)">&lt;Ddm&gt;</a><text>, #</text><a link="sa_fbits" hover="The number of fraction bits in the fixed-point number:&#10;* If {syntax{&lt;dt&gt;}} is {value{S16}} or {value{U16}}">&lt;fbits&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_xv_A1_D" oneofinclass="6" oneof="12" label="Double-precision scalar" bitdiffs="op == 1 &amp;&amp; sf == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-doubleprec" />
        </docvars>
        <box hibit="18" width="1" name="op">
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="sf">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for fixed-point number (field &quot;U:sx&quot;)">&lt;dt&gt;</a><text>.F64 </text><a link="sa_ddm" hover="64-bit SIMD&amp;FP destination and source register (field &quot;D:Vd&quot;)">&lt;Ddm&gt;</a><text>, </text><a link="sa_ddm" hover="64-bit SIMD&amp;FP destination and source register (field &quot;D:Vd&quot;)">&lt;Ddm&gt;</a><text>, #</text><a link="sa_fbits" hover="The number of fraction bits in the fixed-point number:&#10;* If {syntax{&lt;dt&gt;}} is {value{S16}} or {value{U16}}">&lt;fbits&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVT_xv/A1_A.txt" mylink="aarch32.instrs.VCVT_xv.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if sf == '00' || (sf == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if sf == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>to_fixed = (op == '1');  unsigned = (U == '1');</line>
<line>size = if sx == '0' then 16 else 32;</line>
<line>frac_bits = size - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm4:i);</line>
<line>integer fp_size;</line>
<line>integer d;</line>
<line>case sf of</line>
<line>    when '01' fp_size = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '10' fp_size = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '11' fp_size = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line></line>
<line>if frac_bits &lt; 0 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>frac_bits &lt; 0</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="6" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCVT" />
      </docvars>
      <iclassintro count="6"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCVT_xv/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="18" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="17" settings="1">
          <c>1</c>
        </box>
        <box hibit="16" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="sf" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="sx" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVT_toxv_T1_H" oneofinclass="6" oneof="12" label="Half-precision scalar" bitdiffs="op == 0 &amp;&amp; sf == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="18" width="1" name="op">
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="sf">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16.</text><a link="sa_dt" hover="Data type for fixed-point number (field &quot;U:sx&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_sdm" hover="32-bit SIMD&amp;FP destination and source register (field &quot;Vd:D&quot;)">&lt;Sdm&gt;</a><text>, </text><a link="sa_sdm" hover="32-bit SIMD&amp;FP destination and source register (field &quot;Vd:D&quot;)">&lt;Sdm&gt;</a><text>, #</text><a link="sa_fbits" hover="The number of fraction bits in the fixed-point number:&#10;* If {syntax{&lt;dt&gt;}} is {value{S16}} or {value{U16}}">&lt;fbits&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_xv_T1_H" oneofinclass="6" oneof="12" label="Half-precision scalar" bitdiffs="op == 1 &amp;&amp; sf == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="18" width="1" name="op">
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="sf">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for fixed-point number (field &quot;U:sx&quot;)">&lt;dt&gt;</a><text>.F16 </text><a link="sa_sdm" hover="32-bit SIMD&amp;FP destination and source register (field &quot;Vd:D&quot;)">&lt;Sdm&gt;</a><text>, </text><a link="sa_sdm" hover="32-bit SIMD&amp;FP destination and source register (field &quot;Vd:D&quot;)">&lt;Sdm&gt;</a><text>, #</text><a link="sa_fbits" hover="The number of fraction bits in the fixed-point number:&#10;* If {syntax{&lt;dt&gt;}} is {value{S16}} or {value{U16}}">&lt;fbits&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_toxv_T1_S" oneofinclass="6" oneof="12" label="Single-precision scalar" bitdiffs="op == 0 &amp;&amp; sf == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-singleprec" />
        </docvars>
        <box hibit="18" width="1" name="op">
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="sf">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32.</text><a link="sa_dt" hover="Data type for fixed-point number (field &quot;U:sx&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_sdm" hover="32-bit SIMD&amp;FP destination and source register (field &quot;Vd:D&quot;)">&lt;Sdm&gt;</a><text>, </text><a link="sa_sdm" hover="32-bit SIMD&amp;FP destination and source register (field &quot;Vd:D&quot;)">&lt;Sdm&gt;</a><text>, #</text><a link="sa_fbits" hover="The number of fraction bits in the fixed-point number:&#10;* If {syntax{&lt;dt&gt;}} is {value{S16}} or {value{U16}}">&lt;fbits&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_xv_T1_S" oneofinclass="6" oneof="12" label="Single-precision scalar" bitdiffs="op == 1 &amp;&amp; sf == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-singleprec" />
        </docvars>
        <box hibit="18" width="1" name="op">
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="sf">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for fixed-point number (field &quot;U:sx&quot;)">&lt;dt&gt;</a><text>.F32 </text><a link="sa_sdm" hover="32-bit SIMD&amp;FP destination and source register (field &quot;Vd:D&quot;)">&lt;Sdm&gt;</a><text>, </text><a link="sa_sdm" hover="32-bit SIMD&amp;FP destination and source register (field &quot;Vd:D&quot;)">&lt;Sdm&gt;</a><text>, #</text><a link="sa_fbits" hover="The number of fraction bits in the fixed-point number:&#10;* If {syntax{&lt;dt&gt;}} is {value{S16}} or {value{U16}}">&lt;fbits&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_toxv_T1_D" oneofinclass="6" oneof="12" label="Double-precision scalar" bitdiffs="op == 0 &amp;&amp; sf == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-doubleprec" />
        </docvars>
        <box hibit="18" width="1" name="op">
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="sf">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64.</text><a link="sa_dt" hover="Data type for fixed-point number (field &quot;U:sx&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_ddm" hover="64-bit SIMD&amp;FP destination and source register (field &quot;D:Vd&quot;)">&lt;Ddm&gt;</a><text>, </text><a link="sa_ddm" hover="64-bit SIMD&amp;FP destination and source register (field &quot;D:Vd&quot;)">&lt;Ddm&gt;</a><text>, #</text><a link="sa_fbits" hover="The number of fraction bits in the fixed-point number:&#10;* If {syntax{&lt;dt&gt;}} is {value{S16}} or {value{U16}}">&lt;fbits&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVT_xv_T1_D" oneofinclass="6" oneof="12" label="Double-precision scalar" bitdiffs="op == 1 &amp;&amp; sf == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVT" />
          <docvar key="mnemonic-fpdatasize" value="VCVT-doubleprec" />
        </docvars>
        <box hibit="18" width="1" name="op">
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="sf">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for fixed-point number (field &quot;U:sx&quot;)">&lt;dt&gt;</a><text>.F64 </text><a link="sa_ddm" hover="64-bit SIMD&amp;FP destination and source register (field &quot;D:Vd&quot;)">&lt;Ddm&gt;</a><text>, </text><a link="sa_ddm" hover="64-bit SIMD&amp;FP destination and source register (field &quot;D:Vd&quot;)">&lt;Ddm&gt;</a><text>, #</text><a link="sa_fbits" hover="The number of fraction bits in the fixed-point number:&#10;* If {syntax{&lt;dt&gt;}} is {value{S16}} or {value{U16}}">&lt;fbits&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVT_xv/T1_A.txt" mylink="aarch32.instrs.VCVT_xv.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if sf == '00' || (sf == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if sf == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>to_fixed = (op == '1');  unsigned = (U == '1');</line>
<line>size = if sx == '0' then 16 else 32;</line>
<line>frac_bits = size - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm4:i);</line>
<line>integer fp_size;</line>
<line>integer d;</line>
<line>case sf of</line>
<line>    when '01' fp_size = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '10' fp_size = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '11' fp_size = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line></line>
<line>if frac_bits &lt; 0 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>frac_bits &lt; 0</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVT_toxv_A1_H, VCVT_toxv_T1_H" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_toxv_A1_H, VCVT_toxv_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_toxv_A1_H, VCVT_toxv_T1_H" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:sx">
        <intro>Is the data type for the fixed-point number, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">sx</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VCVT_toxv_A1_H, VCVT_toxv_T1_H" symboldefcount="1">
      <symbol link="sa_sdm">&lt;Sdm&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination and source register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_toxv_A1_D, VCVT_toxv_T1_D" symboldefcount="1">
      <symbol link="sa_ddm">&lt;Ddm&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination and source register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVT_toxv_A1_H, VCVT_toxv_T1_H" symboldefcount="1">
      <symbol link="sa_fbits">&lt;fbits&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The number of fraction bits in the fixed-point number:</para>
          <list type="unordered">
            <listitem><content>If <syntax>&lt;dt&gt;</syntax> is <value>S16</value> or <value>U16</value>, <syntax>&lt;fbits&gt;</syntax> must be in the range 0-16. (16 - <syntax>&lt;fbits&gt;</syntax>) is encoded in <field>[imm4, i]</field></content></listitem>
            <listitem><content>If <syntax>&lt;dt&gt;</syntax> is <value>S32</value> or <value>U32</value>, <syntax>&lt;fbits&gt;</syntax> must be in the range 1-32. (32 - <syntax>&lt;fbits&gt;</syntax>) is encoded in <field>[imm4, i]</field>.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCVT_xv/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    if to_fixed then</line>
<line>        bits(size) result;</line>
<line>        case fp_size of</line>
<line>            when 16</line>
<line>                result = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]&lt;15:0&gt;, frac_bits, unsigned, FPSCR[],</line>
<line>                                   <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>, size);</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Extend.3" file="shared_pseudocode.xml" hover="function: bits(N) Extend(bits(M) x, integer N, boolean unsigned)">Extend</a>(result, 32, unsigned);</line>
<line>            when 32</line>
<line>                result = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d], frac_bits, unsigned, FPSCR[], <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>, size);</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Extend.3" file="shared_pseudocode.xml" hover="function: bits(N) Extend(bits(M) x, integer N, boolean unsigned)">Extend</a>(result, 32, unsigned);</line>
<line>            when 64</line>
<line>                result = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d], frac_bits, unsigned, FPSCR[], <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>, size);</line>
<line>                <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.Extend.3" file="shared_pseudocode.xml" hover="function: bits(N) Extend(bits(M) x, integer N, boolean unsigned)">Extend</a>(result, 64, unsigned);</line>
<line>    else</line>
<line>        case fp_size of</line>
<line>            when 16</line>
<line>                bits(16) fp16 = <a link="impl-shared.FixedToFP.6" file="shared_pseudocode.xml" hover="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer N)">FixedToFP</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]&lt;size-1:0&gt;, frac_bits, unsigned, FPSCR[],</line>
<line>                                          <a link="FPRounding_TIEEVEN" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEEVEN</a>, 16);</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16):fp16;</line>
<line>            when 32</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FixedToFP.6" file="shared_pseudocode.xml" hover="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer N)">FixedToFP</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]&lt;size-1:0&gt;, frac_bits, unsigned, FPSCR[],</line>
<line>                                 <a link="FPRounding_TIEEVEN" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEEVEN</a>, 32);</line>
<line>            when 64</line>
<line>                <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FixedToFP.6" file="shared_pseudocode.xml" hover="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer N)">FixedToFP</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d]&lt;size-1:0&gt;, frac_bits, unsigned, FPSCR[],</line>
<line>                                 <a link="FPRounding_TIEEVEN" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEEVEN</a>, 64);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcvta_asimd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCVTA_asimd" title="VCVTA (Advanced SIMD) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCVTA" />
  </docvars>
  <heading>VCVTA (Advanced SIMD)</heading>
  <desc>
    <brief>
      <para>Vector Convert floating-point to integer with Round to Nearest with Ties to Away</para>
    </brief>
    <authored>
      <para>Vector Convert floating-point to integer with Round to Nearest with Ties to Away converts each element in a vector from floating-point to integer using the Round to Nearest with Ties to Away rounding mode, and places the results in a second vector.</para>
      <para>The operand vector elements are floating-point numbers.</para>
      <para>The result vector elements are integers, and the same size as the operand vector elements. Signed and unsigned integers are distinct.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCVTA" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCVTA_asimd/A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="OP" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="RM" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTA_asimd_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTA" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op:size&quot;)">&lt;dt&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;size&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTA_asimd_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op:size&quot;)">&lt;dt&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;size&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTA_asimd/A1_A.txt" mylink="aarch32.instrs.VCVTA_asimd.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size IN {'00', '11'} then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  unsigned = (op == '1');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCVTA" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCVTA_asimd/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="RM" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTA_asimd_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTA" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op:size&quot;)">&lt;dt&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;size&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTA_asimd_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op:size&quot;)">&lt;dt&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;size&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTA_asimd/T1_A.txt" mylink="aarch32.instrs.VCVTA_asimd.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size IN {'00', '11'} then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  unsigned = (op == '1');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVTA_asimd_A1_Q, VCVTA_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTA_asimd_A1_Q, VCVTA_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="op:size">
        <intro>Is the data type for the elements of the destination, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">op</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VCVTA_asimd_A1_Q, VCVTA_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_dt2">&lt;dt2&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the source vector, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt2&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VCVTA_asimd_A1_Q, VCVTA_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTA_asimd_A1_Q, VCVTA_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTA_asimd_A1_D, VCVTA_asimd_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTA_asimd_A1_D, VCVTA_asimd_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCVTA_asimd/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations(); <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>bits(esize) result;</line>
<line>for r = 0 to regs-1</line>
<line>    for e = 0 to elements-1</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], 0, unsigned,</line>
<line>                                         <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>(), rounding, esize);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcvta_vfp.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCVTA_vfp" title="VCVTA (floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCVTA" />
  </docvars>
  <heading>VCVTA (floating-point)</heading>
  <desc>
    <brief>
      <para>Convert floating-point to integer with Round to Nearest with Ties to Away</para>
    </brief>
    <authored>
      <para>Convert floating-point to integer with Round to Nearest with Ties to Away converts a value in a register from floating-point to a 32-bit integer using the Round to Nearest with Ties to Away rounding mode, and places the result in a second register.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCVTA" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCVTA_vfp/A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="18" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="17" width="2" name="RM" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTA_vfp_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTA" />
          <docvar key="mnemonic-fpdatasize" value="VCVTA-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTA_vfp_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTA" />
          <docvar key="mnemonic-fpdatasize" value="VCVTA-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTA_vfp_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTA" />
          <docvar key="mnemonic-fpdatasize" value="VCVTA-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTA_vfp/A1_A.txt" mylink="aarch32.instrs.VCVTA_vfp.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  unsigned = (op == '0');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>integer esize;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCVTA" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCVTA_vfp/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="18" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="17" width="2" name="RM" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTA_vfp_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTA" />
          <docvar key="mnemonic-fpdatasize" value="VCVTA-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTA_vfp_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTA" />
          <docvar key="mnemonic-fpdatasize" value="VCVTA-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTA_vfp_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTA" />
          <docvar key="mnemonic-fpdatasize" value="VCVTA-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTA_vfp/T1_A.txt" mylink="aarch32.instrs.VCVTA_vfp.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  unsigned = (op == '0');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>integer esize;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVTA_vfp_A1_H, VCVTA_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTA_vfp_A1_H, VCVTA_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="op">
        <intro>Is the data type for the elements of the destination, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">op</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">U32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">S32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VCVTA_vfp_A1_H, VCVTA_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTA_vfp_A1_H, VCVTA_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTA_vfp_A1_D, VCVTA_vfp_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCVTA_vfp/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations(); <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>case esize of</line>
<line>    when 16</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, 0, unsigned, FPSCR[], rounding, 32);</line>
<line>    when 32</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], 0, unsigned, FPSCR[], rounding, 32);</line>
<line>    when 64</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], 0, unsigned, FPSCR[], rounding, 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcvtb.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCVTB" title="VCVTB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCVTB" />
  </docvars>
  <heading>VCVTB</heading>
  <desc>
    <brief>
      <para>Convert to or from a half-precision value in the bottom half of a single-precision register</para>
    </brief>
    <authored>
      <para>Convert to or from a half-precision value in the bottom half of a single-precision register does one of the following:</para>
      <list type="unordered">
        <listitem><content>Converts the half-precision value in the bottom half of a single-precision register to single-precision and writes the result to a single-precision register.</content></listitem>
        <listitem><content>Converts the half-precision value in the bottom half of a single-precision register to double-precision and writes the result to a double-precision register.</content></listitem>
        <listitem><content>Converts the single-precision value in a single-precision register to half-precision and writes the result into the bottom half of a single-precision register, preserving the other half of the destination register.</content></listitem>
        <listitem><content>Converts the double-precision value in a double-precision register to half-precision and writes the result into the bottom half of a single-precision register, preserving the other half of the destination register.</content></listitem>
      </list>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCVTB" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCVTB/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="16" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="7" name="T" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTB_A1_SH" oneofinclass="4" oneof="8" label="Half-precision to single-precision" bitdiffs="op == 0 &amp;&amp; sz == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="convert-type" value="half-to-single" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTB" />
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTB_A1_DH" oneofinclass="4" oneof="8" label="Half-precision to double-precision" bitdiffs="op == 0 &amp;&amp; sz == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="convert-type" value="half-to-double" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTB" />
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64.F16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTB_A1_HS" oneofinclass="4" oneof="8" label="Single-precision to half-precision" bitdiffs="op == 1 &amp;&amp; sz == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="convert-type" value="single-to-half" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTB" />
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTB_A1_HD" oneofinclass="4" oneof="8" label="Double-precision to half-precision" bitdiffs="op == 1 &amp;&amp; sz == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="convert-type" value="double-to-half" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTB" />
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTB/T1A1_A.txt" mylink="aarch32.instrs.VCVTB.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>uses_double = (sz == '1'); convert_from_half = (op == '0');</line>
<line>lowbit = (if T == '1' then 16 else 0);</line>
<line>integer d;</line>
<line>integer m;</line>
<line>if uses_double then</line>
<line>    if convert_from_half then</line>
<line>        d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    else</line>
<line>        d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>else</line>
<line>    d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCVTB" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCVTB/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="16" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="7" name="T" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTB_T1_SH" oneofinclass="4" oneof="8" label="Half-precision to single-precision" bitdiffs="op == 0 &amp;&amp; sz == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="convert-type" value="half-to-single" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTB" />
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTB_T1_DH" oneofinclass="4" oneof="8" label="Half-precision to double-precision" bitdiffs="op == 0 &amp;&amp; sz == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="convert-type" value="half-to-double" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTB" />
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64.F16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTB_T1_HS" oneofinclass="4" oneof="8" label="Single-precision to half-precision" bitdiffs="op == 1 &amp;&amp; sz == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="convert-type" value="single-to-half" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTB" />
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTB_T1_HD" oneofinclass="4" oneof="8" label="Double-precision to half-precision" bitdiffs="op == 1 &amp;&amp; sz == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="convert-type" value="double-to-half" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTB" />
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTB/T1A1_A.txt" mylink="aarch32.instrs.VCVTB.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>uses_double = (sz == '1'); convert_from_half = (op == '0');</line>
<line>lowbit = (if T == '1' then 16 else 0);</line>
<line>integer d;</line>
<line>integer m;</line>
<line>if uses_double then</line>
<line>    if convert_from_half then</line>
<line>        d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    else</line>
<line>        d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>else</line>
<line>    d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVTB_A1_SH, VCVTB_T1_SH" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTB_A1_SH, VCVTB_T1_SH" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTB_A1_SH, VCVTB_T1_SH" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTB_A1_HD, VCVTB_T1_HD" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTB_A1_DH, VCVTB_T1_DH" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTB_A1_SH, VCVTB_T1_SH" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCVTB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations(); <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    bits(16) hp;</line>
<line>    if convert_from_half then</line>
<line>        hp = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;lowbit+15:lowbit&gt;;</line>
<line>        if uses_double then</line>
<line>            <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPConvert.3" file="shared_pseudocode.xml" hover="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, integer M)">FPConvert</a>(hp, FPSCR[], 64);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPConvert.3" file="shared_pseudocode.xml" hover="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, integer M)">FPConvert</a>(hp, FPSCR[], 32);</line>
<line>    else</line>
<line>        if uses_double then</line>
<line>            hp = <a link="impl-shared.FPConvert.3" file="shared_pseudocode.xml" hover="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, integer M)">FPConvert</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[], 16);</line>
<line>        else</line>
<line>            hp = <a link="impl-shared.FPConvert.3" file="shared_pseudocode.xml" hover="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, integer M)">FPConvert</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[], 16);</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d]&lt;lowbit+15:lowbit&gt; = hp;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcvtb_bfs.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCVTB_bfs" title="VCVTB (BFloat16) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCVTB" />
  </docvars>
  <heading>VCVTB (BFloat16)</heading>
  <desc>
    <brief>
      <para>Converts from a single-precision value to a BFloat16 value in the bottom half of a single-precision register</para>
    </brief>
    <authored>
      <para>Converts the single-precision value in a single-precision register to BFloat16 format and writes the result into the bottom half of a single precision register, preserving the top 16 bits of the destination register.</para>
      <para>Unlike the BFloat16 multiplication instructions, this instruction honors all the control bits in the <xref linkend="AArch32.fpscr">FPSCR</xref> that apply to single-precision arithmetic, including the rounding mode. This instruction can generate a floating-point exception which causes a cumulative exception bit in the <xref linkend="AArch32.fpscr">FPSCR</xref> to be set, or a synchronous exception to be taken, depending on the enable bits in the <xref linkend="AArch32.fpscr">FPSCR</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCVTB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VCVTB_bf16/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="o3" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTB_A1_bfs" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTB" />
        </docvars>
        <asmtemplate><text>VCVTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTB_bf16/T1A1_A.txt" mylink="aarch32.instrs.VCVTB_bf16.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCVTB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VCVTB_bf16/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="o3" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTB_T1_bfs" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTB" />
        </docvars>
        <asmtemplate><text>VCVTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTB_bf16/T1A1_A.txt" mylink="aarch32.instrs.VCVTB_bf16.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVTB_A1_bfs, VCVTB_T1_bfs" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTB_A1_bfs, VCVTB_T1_bfs" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTB_A1_bfs, VCVTB_T1_bfs" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTB_A1_bfs, VCVTB_T1_bfs" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCVTB_bf16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line></line>
<line>    <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d]&lt;15:0&gt; = <a link="impl-shared.FPConvertBF.2" file="shared_pseudocode.xml" hover="function: bits(16) FPConvertBF(bits(32) op, FPCRType fpcr)">FPConvertBF</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcvtm_asimd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCVTM_asimd" title="VCVTM (Advanced SIMD) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCVTM" />
  </docvars>
  <heading>VCVTM (Advanced SIMD)</heading>
  <desc>
    <brief>
      <para>Vector Convert floating-point to integer with Round towards -Infinity</para>
    </brief>
    <authored>
      <para>Vector Convert floating-point to integer with Round towards -Infinity converts each element in a vector from floating-point to integer using the Round towards -Infinity rounding mode, and places the results in a second vector.</para>
      <para>The operand vector elements are floating-point numbers.</para>
      <para>The result vector elements are integers, and the same size as the operand vector elements. Signed and unsigned integers are distinct.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCVTM" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCVTA_asimd/A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="OP" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="RM" usename="1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTM_asimd_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTM" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op:size&quot;)">&lt;dt&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;size&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTM_asimd_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTM" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op:size&quot;)">&lt;dt&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;size&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTA_asimd/A1_A.txt" mylink="aarch32.instrs.VCVTA_asimd.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size IN {'00', '11'} then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  unsigned = (op == '1');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCVTM" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCVTA_asimd/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="RM" usename="1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTM_asimd_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTM" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op:size&quot;)">&lt;dt&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;size&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTM_asimd_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTM" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op:size&quot;)">&lt;dt&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;size&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTA_asimd/T1_A.txt" mylink="aarch32.instrs.VCVTA_asimd.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size IN {'00', '11'} then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  unsigned = (op == '1');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVTM_asimd_A1_Q, VCVTM_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTM_asimd_A1_Q, VCVTM_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="op:size">
        <intro>Is the data type for the elements of the destination, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">op</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VCVTM_asimd_A1_Q, VCVTM_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_dt2">&lt;dt2&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the source vector, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt2&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VCVTM_asimd_A1_Q, VCVTM_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTM_asimd_A1_Q, VCVTM_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTM_asimd_A1_D, VCVTM_asimd_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTM_asimd_A1_D, VCVTM_asimd_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCVTA_asimd/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations(); <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>bits(esize) result;</line>
<line>for r = 0 to regs-1</line>
<line>    for e = 0 to elements-1</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], 0, unsigned,</line>
<line>                                         <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>(), rounding, esize);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcvtm_vfp.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCVTM_vfp" title="VCVTM (floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCVTM" />
  </docvars>
  <heading>VCVTM (floating-point)</heading>
  <desc>
    <brief>
      <para>Convert floating-point to integer with Round towards -Infinity</para>
    </brief>
    <authored>
      <para>Convert floating-point to integer with Round towards -Infinity converts a value in a register from floating-point to a 32-bit integer using the Round towards -Infinity rounding mode, and places the result in a second register.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCVTM" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCVTA_vfp/A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="18" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="17" width="2" name="RM" usename="1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTM_vfp_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTM" />
          <docvar key="mnemonic-fpdatasize" value="VCVTM-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTM_vfp_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTM" />
          <docvar key="mnemonic-fpdatasize" value="VCVTM-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTM_vfp_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTM" />
          <docvar key="mnemonic-fpdatasize" value="VCVTM-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTA_vfp/A1_A.txt" mylink="aarch32.instrs.VCVTA_vfp.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  unsigned = (op == '0');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>integer esize;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCVTM" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCVTA_vfp/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="18" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="17" width="2" name="RM" usename="1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTM_vfp_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTM" />
          <docvar key="mnemonic-fpdatasize" value="VCVTM-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTM_vfp_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTM" />
          <docvar key="mnemonic-fpdatasize" value="VCVTM-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTM_vfp_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTM" />
          <docvar key="mnemonic-fpdatasize" value="VCVTM-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTA_vfp/T1_A.txt" mylink="aarch32.instrs.VCVTA_vfp.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  unsigned = (op == '0');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>integer esize;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVTM_vfp_A1_H, VCVTM_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTM_vfp_A1_H, VCVTM_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="op">
        <intro>Is the data type for the elements of the destination, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">op</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">U32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">S32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VCVTM_vfp_A1_H, VCVTM_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTM_vfp_A1_H, VCVTM_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTM_vfp_A1_D, VCVTM_vfp_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCVTA_vfp/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations(); <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>case esize of</line>
<line>    when 16</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, 0, unsigned, FPSCR[], rounding, 32);</line>
<line>    when 32</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], 0, unsigned, FPSCR[], rounding, 32);</line>
<line>    when 64</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], 0, unsigned, FPSCR[], rounding, 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcvtn_asimd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCVTN_asimd" title="VCVTN (Advanced SIMD) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCVTN" />
  </docvars>
  <heading>VCVTN (Advanced SIMD)</heading>
  <desc>
    <brief>
      <para>Vector Convert floating-point to integer with Round to Nearest</para>
    </brief>
    <authored>
      <para>Vector Convert floating-point to integer with Round to Nearest converts each element in a vector from floating-point to integer using the Round to Nearest rounding mode, and places the results in a second vector.</para>
      <para>The operand vector elements are floating-point numbers.</para>
      <para>The result vector elements are integers, and the same size as the operand vector elements. Signed and unsigned integers are distinct.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCVTN" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCVTA_asimd/A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="OP" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="RM" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTN_asimd_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTN</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op:size&quot;)">&lt;dt&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;size&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTN_asimd_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTN" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTN</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op:size&quot;)">&lt;dt&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;size&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTA_asimd/A1_A.txt" mylink="aarch32.instrs.VCVTA_asimd.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size IN {'00', '11'} then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  unsigned = (op == '1');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCVTN" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCVTA_asimd/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="RM" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTN_asimd_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTN</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op:size&quot;)">&lt;dt&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;size&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTN_asimd_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTN" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTN</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op:size&quot;)">&lt;dt&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;size&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTA_asimd/T1_A.txt" mylink="aarch32.instrs.VCVTA_asimd.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size IN {'00', '11'} then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  unsigned = (op == '1');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVTN_asimd_A1_Q, VCVTN_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTN_asimd_A1_Q, VCVTN_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="op:size">
        <intro>Is the data type for the elements of the destination, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">op</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VCVTN_asimd_A1_Q, VCVTN_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_dt2">&lt;dt2&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the source vector, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt2&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VCVTN_asimd_A1_Q, VCVTN_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTN_asimd_A1_Q, VCVTN_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTN_asimd_A1_D, VCVTN_asimd_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTN_asimd_A1_D, VCVTN_asimd_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCVTA_asimd/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations(); <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>bits(esize) result;</line>
<line>for r = 0 to regs-1</line>
<line>    for e = 0 to elements-1</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], 0, unsigned,</line>
<line>                                         <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>(), rounding, esize);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcvtn_vfp.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCVTN_vfp" title="VCVTN (floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCVTN" />
  </docvars>
  <heading>VCVTN (floating-point)</heading>
  <desc>
    <brief>
      <para>Convert floating-point to integer with Round to Nearest</para>
    </brief>
    <authored>
      <para>Convert floating-point to integer with Round to Nearest converts a value in a register from floating-point to a 32-bit integer using the Round to Nearest rounding mode, and places the result in a second register.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCVTN" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCVTA_vfp/A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="18" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="17" width="2" name="RM" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTN_vfp_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTN" />
          <docvar key="mnemonic-fpdatasize" value="VCVTN-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTN</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTN_vfp_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTN" />
          <docvar key="mnemonic-fpdatasize" value="VCVTN-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTN</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTN_vfp_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTN" />
          <docvar key="mnemonic-fpdatasize" value="VCVTN-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTN</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTA_vfp/A1_A.txt" mylink="aarch32.instrs.VCVTA_vfp.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  unsigned = (op == '0');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>integer esize;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCVTN" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCVTA_vfp/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="18" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="17" width="2" name="RM" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTN_vfp_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTN" />
          <docvar key="mnemonic-fpdatasize" value="VCVTN-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTN</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTN_vfp_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTN" />
          <docvar key="mnemonic-fpdatasize" value="VCVTN-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTN</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTN_vfp_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTN" />
          <docvar key="mnemonic-fpdatasize" value="VCVTN-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTN</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTA_vfp/T1_A.txt" mylink="aarch32.instrs.VCVTA_vfp.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  unsigned = (op == '0');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>integer esize;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVTN_vfp_A1_H, VCVTN_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTN_vfp_A1_H, VCVTN_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="op">
        <intro>Is the data type for the elements of the destination, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">op</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">U32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">S32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VCVTN_vfp_A1_H, VCVTN_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTN_vfp_A1_H, VCVTN_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTN_vfp_A1_D, VCVTN_vfp_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCVTA_vfp/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations(); <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>case esize of</line>
<line>    when 16</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, 0, unsigned, FPSCR[], rounding, 32);</line>
<line>    when 32</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], 0, unsigned, FPSCR[], rounding, 32);</line>
<line>    when 64</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], 0, unsigned, FPSCR[], rounding, 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcvtp_asimd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCVTP_asimd" title="VCVTP (Advanced SIMD) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCVTP" />
  </docvars>
  <heading>VCVTP (Advanced SIMD)</heading>
  <desc>
    <brief>
      <para>Vector Convert floating-point to integer with Round towards +Infinity</para>
    </brief>
    <authored>
      <para>Vector Convert floating-point to integer with Round towards +Infinity converts each element in a vector from floating-point to integer using the Round towards +Infinity rounding mode, and places the results in a second vector.</para>
      <para>The operand vector elements are floating-point numbers.</para>
      <para>The result vector elements are integers, and the same size as the operand vector elements. Signed and unsigned integers are distinct.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCVTP" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCVTA_asimd/A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="OP" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="RM" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTP_asimd_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTP" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTP</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op:size&quot;)">&lt;dt&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;size&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTP_asimd_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTP" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTP</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op:size&quot;)">&lt;dt&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;size&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTA_asimd/A1_A.txt" mylink="aarch32.instrs.VCVTA_asimd.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size IN {'00', '11'} then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  unsigned = (op == '1');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCVTP" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCVTA_asimd/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="RM" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTP_asimd_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTP" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTP</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op:size&quot;)">&lt;dt&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;size&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTP_asimd_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTP" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTP</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op:size&quot;)">&lt;dt&gt;</a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field &quot;size&quot;)">&lt;dt2&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTA_asimd/T1_A.txt" mylink="aarch32.instrs.VCVTA_asimd.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size IN {'00', '11'} then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  unsigned = (op == '1');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVTP_asimd_A1_Q, VCVTP_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTP_asimd_A1_Q, VCVTP_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="op:size">
        <intro>Is the data type for the elements of the destination, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">op</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VCVTP_asimd_A1_Q, VCVTP_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_dt2">&lt;dt2&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the source vector, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt2&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VCVTP_asimd_A1_Q, VCVTP_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTP_asimd_A1_Q, VCVTP_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTP_asimd_A1_D, VCVTP_asimd_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTP_asimd_A1_D, VCVTP_asimd_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCVTA_asimd/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations(); <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>bits(esize) result;</line>
<line>for r = 0 to regs-1</line>
<line>    for e = 0 to elements-1</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], 0, unsigned,</line>
<line>                                         <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>(), rounding, esize);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcvtp_vfp.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCVTP_vfp" title="VCVTP (floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCVTP" />
  </docvars>
  <heading>VCVTP (floating-point)</heading>
  <desc>
    <brief>
      <para>Convert floating-point to integer with Round towards +Infinity</para>
    </brief>
    <authored>
      <para>Convert floating-point to integer with Round towards +Infinity converts a value in a register from floating-point to a 32-bit integer using the Round towards +Infinity rounding mode, and places the result in a second register.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCVTP" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCVTA_vfp/A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="18" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="17" width="2" name="RM" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTP_vfp_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTP" />
          <docvar key="mnemonic-fpdatasize" value="VCVTP-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTP</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTP_vfp_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTP" />
          <docvar key="mnemonic-fpdatasize" value="VCVTP-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTP</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTP_vfp_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTP" />
          <docvar key="mnemonic-fpdatasize" value="VCVTP-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTP</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTA_vfp/A1_A.txt" mylink="aarch32.instrs.VCVTA_vfp.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  unsigned = (op == '0');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>integer esize;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCVTP" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCVTA_vfp/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="18" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="17" width="2" name="RM" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTP_vfp_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTP" />
          <docvar key="mnemonic-fpdatasize" value="VCVTP-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTP</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTP_vfp_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTP" />
          <docvar key="mnemonic-fpdatasize" value="VCVTP-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTP</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTP_vfp_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTP" />
          <docvar key="mnemonic-fpdatasize" value="VCVTP-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTP</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of destination (field &quot;op&quot;)">&lt;dt&gt;</a><text>.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTA_vfp/T1_A.txt" mylink="aarch32.instrs.VCVTA_vfp.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  unsigned = (op == '0');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>integer esize;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVTP_vfp_A1_H, VCVTP_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTP_vfp_A1_H, VCVTP_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="op">
        <intro>Is the data type for the elements of the destination, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">op</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">U32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">S32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VCVTP_vfp_A1_H, VCVTP_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTP_vfp_A1_H, VCVTP_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTP_vfp_A1_D, VCVTP_vfp_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCVTA_vfp/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations(); <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>case esize of</line>
<line>    when 16</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, 0, unsigned, FPSCR[], rounding, 32);</line>
<line>    when 32</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], 0, unsigned, FPSCR[], rounding, 32);</line>
<line>    when 64</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], 0, unsigned, FPSCR[], rounding, 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcvtr_iv.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCVTR_iv" title="VCVTR -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCVTR" />
  </docvars>
  <heading>VCVTR</heading>
  <desc>
    <brief>
      <para>Convert floating-point to integer</para>
    </brief>
    <authored>
      <para>Convert floating-point to integer converts a value in a register from floating-point to a 32-bit integer, using the rounding mode specified by the <xref linkend="AArch32.fpscr">FPSCR</xref> and places the result in a second register.</para>
      <para><xref linkend="A32T32-fpsimd.instructions.VCVT_xv">VCVT (between floating-point and fixed-point, floating-point)</xref> describes conversions between floating-point and 16-bit integers.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.fpdp">Floating-point data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.fpdp">Floating-point data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="6" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCVTR" />
      </docvars>
      <iclassintro count="6"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCVT_iv/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="18" width="3" name="opc2" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
          <c>x</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTR_uiv_A1_H" oneofinclass="6" oneof="12" label="Half-precision scalar" bitdiffs="opc2 == 100 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTR" />
          <docvar key="mnemonic-fpdatasize" value="VCVTR-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U32.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTR_siv_A1_H" oneofinclass="6" oneof="12" label="Half-precision scalar" bitdiffs="opc2 == 101 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTR" />
          <docvar key="mnemonic-fpdatasize" value="VCVTR-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S32.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTR_uiv_A1_S" oneofinclass="6" oneof="12" label="Single-precision scalar" bitdiffs="opc2 == 100 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTR" />
          <docvar key="mnemonic-fpdatasize" value="VCVTR-singleprec" />
        </docvars>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U32.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTR_siv_A1_S" oneofinclass="6" oneof="12" label="Single-precision scalar" bitdiffs="opc2 == 101 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTR" />
          <docvar key="mnemonic-fpdatasize" value="VCVTR-singleprec" />
        </docvars>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S32.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTR_uiv_A1_D" oneofinclass="6" oneof="12" label="Double-precision scalar" bitdiffs="opc2 == 100 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTR" />
          <docvar key="mnemonic-fpdatasize" value="VCVTR-doubleprec" />
        </docvars>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U32.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTR_siv_A1_D" oneofinclass="6" oneof="12" label="Double-precision scalar" bitdiffs="opc2 == 101 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTR" />
          <docvar key="mnemonic-fpdatasize" value="VCVTR-doubleprec" />
        </docvars>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S32.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVT_iv/A1_A.txt" mylink="aarch32.instrs.VCVT_iv.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if opc2 != '000' &amp;&amp; !(opc2 IN {'10x'}) then SEE "Related encodings";</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>integer d;</line>
<line>integer esize;</line>
<line>integer m;</line>
<line>boolean unsigned;</line>
<line><a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding;</line>
<line>to_integer = (opc2&lt;2&gt; == '1');</line>
<line>if to_integer then</line>
<line>    unsigned = (opc2&lt;0&gt; == '0');</line>
<line>    rounding = if op == '1' then <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a> else <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPSCR[]);</line>
<line>    d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    case size of</line>
<line>        when '01' esize = 16; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>        when '10' esize = 32; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>        when '11' esize = 64; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>else</line>
<line>    unsigned = (op == '0');</line>
<line>    rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPSCR[]);</line>
<line>    m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    case size of</line>
<line>        when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>        when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>        when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="6" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCVTR" />
      </docvars>
      <iclassintro count="6"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCVT_iv/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="18" width="3" name="opc2" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
          <c>x</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTR_uiv_T1_H" oneofinclass="6" oneof="12" label="Half-precision scalar" bitdiffs="opc2 == 100 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTR" />
          <docvar key="mnemonic-fpdatasize" value="VCVTR-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U32.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTR_siv_T1_H" oneofinclass="6" oneof="12" label="Half-precision scalar" bitdiffs="opc2 == 101 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTR" />
          <docvar key="mnemonic-fpdatasize" value="VCVTR-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S32.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTR_uiv_T1_S" oneofinclass="6" oneof="12" label="Single-precision scalar" bitdiffs="opc2 == 100 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTR" />
          <docvar key="mnemonic-fpdatasize" value="VCVTR-singleprec" />
        </docvars>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U32.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTR_siv_T1_S" oneofinclass="6" oneof="12" label="Single-precision scalar" bitdiffs="opc2 == 101 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTR" />
          <docvar key="mnemonic-fpdatasize" value="VCVTR-singleprec" />
        </docvars>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S32.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTR_uiv_T1_D" oneofinclass="6" oneof="12" label="Double-precision scalar" bitdiffs="opc2 == 100 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTR" />
          <docvar key="mnemonic-fpdatasize" value="VCVTR-doubleprec" />
        </docvars>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U32.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTR_siv_T1_D" oneofinclass="6" oneof="12" label="Double-precision scalar" bitdiffs="opc2 == 101 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTR" />
          <docvar key="mnemonic-fpdatasize" value="VCVTR-doubleprec" />
        </docvars>
        <box hibit="18" width="" name="opc2">
          <c></c>
          <c></c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S32.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVT_iv/T1_A.txt" mylink="aarch32.instrs.VCVT_iv.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if opc2 != '000' &amp;&amp; !(opc2 IN {'10x'}) then SEE "Related encodings";</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>integer esize;</line>
<line>integer m;</line>
<line>integer d;</line>
<line>boolean unsigned;</line>
<line><a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding;</line>
<line>to_integer = (opc2&lt;2&gt; == '1');</line>
<line>if to_integer then</line>
<line>    unsigned = (opc2&lt;0&gt; == '0');</line>
<line>    rounding = if op == '1' then <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a> else <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPSCR[]);</line>
<line>    d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    case size of</line>
<line>        when '01' esize = 16; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>        when '10' esize = 32; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>        when '11' esize = 64; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>else</line>
<line>    unsigned = (op == '0');</line>
<line>    rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPSCR[]);</line>
<line>    m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    case size of</line>
<line>        when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>        when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>        when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVTR_uiv_A1_H, VCVTR_uiv_T1_H" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTR_uiv_A1_H, VCVTR_uiv_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTR_uiv_A1_H, VCVTR_uiv_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTR_uiv_A1_H, VCVTR_uiv_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTR_uiv_A1_D, VCVTR_uiv_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCVT_iv/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    if to_integer then</line>
<line>        case esize of</line>
<line>            when 16</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, 0, unsigned, FPSCR[], rounding, 32);</line>
<line>            when 32</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], 0, unsigned, FPSCR[], rounding, 32);</line>
<line>            when 64</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], 0, unsigned, FPSCR[], rounding, 32);</line>
<line>    else</line>
<line>        case esize of</line>
<line>            when 16</line>
<line>                bits(16) fp16 = <a link="impl-shared.FixedToFP.6" file="shared_pseudocode.xml" hover="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer N)">FixedToFP</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], 0, unsigned, FPSCR[], rounding, 16);</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16):fp16;</line>
<line>            when 32</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FixedToFP.6" file="shared_pseudocode.xml" hover="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer N)">FixedToFP</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], 0, unsigned, FPSCR[], rounding, 32);</line>
<line>            when 64</line>
<line>                <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FixedToFP.6" file="shared_pseudocode.xml" hover="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer N)">FixedToFP</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], 0, unsigned, FPSCR[], rounding, 64);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcvtt.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCVTT" title="VCVTT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCVTT" />
  </docvars>
  <heading>VCVTT</heading>
  <desc>
    <brief>
      <para>Convert to or from a half-precision value in the top half of a single-precision register</para>
    </brief>
    <authored>
      <para>Convert to or from a half-precision value in the top half of a single-precision register does one of the following:</para>
      <list type="unordered">
        <listitem><content>Converts the half-precision value in the top half of a single-precision register to single-precision and writes the result to a single-precision register.</content></listitem>
        <listitem><content>Converts the half-precision value in the top half of a single-precision register to double-precision and writes the result to a double-precision register.</content></listitem>
        <listitem><content>Converts the single-precision value in a single-precision register to half-precision and writes the result into the top half of a single-precision register, preserving the other half of the destination register.</content></listitem>
        <listitem><content>Converts the double-precision value in a double-precision register to half-precision and writes the result into the top half of a single-precision register, preserving the other half of the destination register.</content></listitem>
      </list>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCVTT" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VCVTB/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="16" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="7" name="T" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTT_A1_SH" oneofinclass="4" oneof="8" label="Half-precision to single-precision" bitdiffs="op == 0 &amp;&amp; sz == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="convert-type" value="half-to-single" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTT" />
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTT_A1_DH" oneofinclass="4" oneof="8" label="Half-precision to double-precision" bitdiffs="op == 0 &amp;&amp; sz == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="convert-type" value="half-to-double" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTT" />
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64.F16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTT_A1_HS" oneofinclass="4" oneof="8" label="Single-precision to half-precision" bitdiffs="op == 1 &amp;&amp; sz == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="convert-type" value="single-to-half" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTT" />
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTT_A1_HD" oneofinclass="4" oneof="8" label="Double-precision to half-precision" bitdiffs="op == 1 &amp;&amp; sz == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="convert-type" value="double-to-half" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTT" />
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTB/T1A1_A.txt" mylink="aarch32.instrs.VCVTB.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>uses_double = (sz == '1'); convert_from_half = (op == '0');</line>
<line>lowbit = (if T == '1' then 16 else 0);</line>
<line>integer d;</line>
<line>integer m;</line>
<line>if uses_double then</line>
<line>    if convert_from_half then</line>
<line>        d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    else</line>
<line>        d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>else</line>
<line>    d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCVTT" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VCVTB/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="16" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="7" name="T" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTT_T1_SH" oneofinclass="4" oneof="8" label="Half-precision to single-precision" bitdiffs="op == 0 &amp;&amp; sz == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="convert-type" value="half-to-single" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTT" />
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTT_T1_DH" oneofinclass="4" oneof="8" label="Half-precision to double-precision" bitdiffs="op == 0 &amp;&amp; sz == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="convert-type" value="half-to-double" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTT" />
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64.F16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTT_T1_HS" oneofinclass="4" oneof="8" label="Single-precision to half-precision" bitdiffs="op == 1 &amp;&amp; sz == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="convert-type" value="single-to-half" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTT" />
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>0</c>
        </box>
        <asmtemplate><text>VCVTT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCVTT_T1_HD" oneofinclass="4" oneof="8" label="Double-precision to half-precision" bitdiffs="op == 1 &amp;&amp; sz == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="convert-type" value="double-to-half" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTT" />
        </docvars>
        <box hibit="16" width="1" name="op">
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="sz">
          <c>1</c>
        </box>
        <asmtemplate><text>VCVTT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTB/T1A1_A.txt" mylink="aarch32.instrs.VCVTB.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>uses_double = (sz == '1'); convert_from_half = (op == '0');</line>
<line>lowbit = (if T == '1' then 16 else 0);</line>
<line>integer d;</line>
<line>integer m;</line>
<line>if uses_double then</line>
<line>    if convert_from_half then</line>
<line>        d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    else</line>
<line>        d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>else</line>
<line>    d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVTT_A1_SH, VCVTT_T1_SH" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTT_A1_SH, VCVTT_T1_SH" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTT_A1_SH, VCVTT_T1_SH" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTT_A1_HD, VCVTT_T1_HD" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTT_A1_DH, VCVTT_T1_DH" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTT_A1_SH, VCVTT_T1_SH" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCVTB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations(); <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    bits(16) hp;</line>
<line>    if convert_from_half then</line>
<line>        hp = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;lowbit+15:lowbit&gt;;</line>
<line>        if uses_double then</line>
<line>            <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPConvert.3" file="shared_pseudocode.xml" hover="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, integer M)">FPConvert</a>(hp, FPSCR[], 64);</line>
<line>        else</line>
<line>            <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPConvert.3" file="shared_pseudocode.xml" hover="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, integer M)">FPConvert</a>(hp, FPSCR[], 32);</line>
<line>    else</line>
<line>        if uses_double then</line>
<line>            hp = <a link="impl-shared.FPConvert.3" file="shared_pseudocode.xml" hover="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, integer M)">FPConvert</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[], 16);</line>
<line>        else</line>
<line>            hp = <a link="impl-shared.FPConvert.3" file="shared_pseudocode.xml" hover="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, integer M)">FPConvert</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[], 16);</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d]&lt;lowbit+15:lowbit&gt; = hp;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vcvtt_bfs.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCVTT_bfs" title="VCVTT (BFloat16) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCVTT" />
  </docvars>
  <heading>VCVTT (BFloat16)</heading>
  <desc>
    <brief>
      <para>Converts from a single-precision value to a BFloat16 value in the top half of a single-precision register.</para>
    </brief>
    <authored>
      <para>Converts the single-precision value in a single-precision register to BFloat16 format and writes the result in the top half of a single-precision register, preserving the bottom 16 bits of the register.</para>
      <para>Unlike the BFloat16 multiplication instructions, this instruction honors all the control bits in the <xref linkend="AArch32.fpscr">FPSCR</xref> that apply to single-precision arithmetic, including the rounding mode. This instruction can generate a floating-point exception which causes a cumulative exception bit in the <xref linkend="AArch32.fpscr">FPSCR</xref> to be set, or a synchronous exception to be taken, depending on the enable bits in the <xref linkend="AArch32.fpscr">FPSCR</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCVTT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VCVTT/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="o3" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTT_A1_bfs" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTT" />
        </docvars>
        <asmtemplate><text>VCVTT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTT/T1A1_A.txt" mylink="aarch32.instrs.VCVTT.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCVTT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VCVTT/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="o3" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTT_T1_bfs" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTT" />
        </docvars>
        <asmtemplate><text>VCVTT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTT/T1A1_A.txt" mylink="aarch32.instrs.VCVTT.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVTT_A1_bfs, VCVTT_T1_bfs" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTT_A1_bfs, VCVTT_T1_bfs" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTT_A1_bfs, VCVTT_T1_bfs" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTT_A1_bfs, VCVTT_T1_bfs" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCVTT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line></line>
<line>    <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d]&lt;31:16&gt; = <a link="impl-shared.FPConvertBF.2" file="shared_pseudocode.xml" hover="function: bits(16) FPConvertBF(bits(32) op, FPCRType fpcr)">FPConvertBF</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vdiv.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VDIV" title="VDIV -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VDIV" />
  </docvars>
  <heading>VDIV</heading>
  <desc>
    <brief>
      <para>Divide</para>
    </brief>
    <authored>
      <para>Divide divides one floating-point value by another floating-point value and writes the result to a third floating-point register.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VDIV" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VDIV/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VDIV_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VDIV" />
          <docvar key="mnemonic-fpdatasize" value="VDIV-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VDIV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><text>{</text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VDIV_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VDIV" />
          <docvar key="mnemonic-fpdatasize" value="VDIV-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VDIV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><text>{</text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VDIV_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VDIV" />
          <docvar key="mnemonic-fpdatasize" value="VDIV-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VDIV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VDIV/A1_A.txt" mylink="aarch32.instrs.VDIV.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VDIV" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VDIV/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VDIV_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VDIV" />
          <docvar key="mnemonic-fpdatasize" value="VDIV-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VDIV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><text>{</text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VDIV_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VDIV" />
          <docvar key="mnemonic-fpdatasize" value="VDIV-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VDIV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><text>{</text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VDIV_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VDIV" />
          <docvar key="mnemonic-fpdatasize" value="VDIV-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VDIV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VDIV/T1_A.txt" mylink="aarch32.instrs.VDIV.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VDIV_A1_H, VDIV_T1_H" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDIV_A1_H, VDIV_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDIV_A1_H, VDIV_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDIV_A1_H, VDIV_T1_H" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDIV_A1_H, VDIV_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDIV_A1_D, VDIV_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDIV_A1_D, VDIV_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDIV_A1_D, VDIV_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VDIV/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    case esize of</line>
<line>        when 16</line>
<line>            <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPDiv.3" file="shared_pseudocode.xml" hover="function: bits(N) FPDiv(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPDiv</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[]);</line>
<line>        when 32</line>
<line>            <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPDiv.3" file="shared_pseudocode.xml" hover="function: bits(N) FPDiv(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPDiv</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n], <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[]);</line>
<line>        when 64</line>
<line>            <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPDiv.3" file="shared_pseudocode.xml" hover="function: bits(N) FPDiv(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPDiv</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n], <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vdot.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VDOT" title="VDOT (vector) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VDOT" />
  </docvars>
  <heading>VDOT (vector)</heading>
  <desc>
    <brief>
      <para>BFloat16 floating-point (BF16) dot product (vector)</para>
    </brief>
    <authored>
      <para>BFloat16 floating-point (BF16) dot product (vector). This instruction delimits the source vectors into pairs of 16-bit BF16 elements. Within each pair, the elements in the first source vector are multiplied by the corresponding elements in the second source vector. The resulting single-precision products are then summed and added destructively to the single-precision element in the destination vector which aligns with the pair of BF16 values in the first source vector. The instruction does not update the <xref linkend="AArch32.fpscr">FPSCR</xref> exception status.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VDOT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VDOT_bf16/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="op1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VDOT_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VDOT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VDOT_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VDOT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VDOT_bf16/A1_A.txt" mylink="aarch32.instrs.VDOT_bf16.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>integer regs = if Q == '1' then 2 else 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VDOT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VDOT_bf16/T1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="op1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VDOT_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VDOT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VDOT_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VDOT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VDOT_bf16/T1_A.txt" mylink="aarch32.instrs.VDOT_bf16.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>integer regs = if Q == '1' then 2 else 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VDOT_A1_D, VDOT_T1_D" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDOT_A1_Q, VDOT_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDOT_A1_Q, VDOT_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDOT_A1_Q, VDOT_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDOT_A1_D, VDOT_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDOT_A1_D, VDOT_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDOT_A1_D, VDOT_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VDOT_bf16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>bits(64) operand1;</line>
<line>bits(64) operand2;</line>
<line>bits(64) result;</line>
<line></line>
<line><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>for r = 0 to regs-1</line>
<line>    operand1 = <a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r];</line>
<line>    operand2 = <a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m+r];</line>
<line>    result = <a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r];</line>
<line>    for e = 0 to 1</line>
<line>        bits(16) elt1_a = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * e + 0, 16];</line>
<line>        bits(16) elt1_b = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * e + 1, 16];</line>
<line>        bits(16) elt2_a = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * e + 0, 16];</line>
<line>        bits(16) elt2_b = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * e + 1, 16];</line>
<line>        bits(32) sum = <a link="impl-shared.FPAdd_BF16.2" file="shared_pseudocode.xml" hover="function: bits(32) FPAdd_BF16(bits(32) op1, bits(32) op2)">FPAdd_BF16</a>(<a link="impl-shared.BFMulH.2" file="shared_pseudocode.xml" hover="function: bits(32) BFMulH(bits(16) op1, bits(16) op2)">BFMulH</a>(elt1_a, elt2_a), <a link="impl-shared.BFMulH.2" file="shared_pseudocode.xml" hover="function: bits(32) BFMulH(bits(16) op1, bits(16) op2)">BFMulH</a>(elt1_b, elt2_b));</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = <a link="impl-shared.FPAdd_BF16.2" file="shared_pseudocode.xml" hover="function: bits(32) FPAdd_BF16(bits(32) op1, bits(32) op2)">FPAdd_BF16</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 32], sum);</line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vdot_s.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VDOT_s" title="VDOT (by element) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VDOT" />
  </docvars>
  <heading>VDOT (by element)</heading>
  <desc>
    <brief>
      <para>BFloat16 floating-point indexed dot product (vector, by element)</para>
    </brief>
    <authored>
      <para>BFloat16 floating-point indexed dot product (vector, by element). This instruction delimits the source vectors into pairs of 16-bit BF16 elements. Each pair of elements in the first source vector is multiplied by the indexed pair of elements in the second source vector. The resulting single-precision products are then summed and added destructively to the single-precision element in the destination vector which aligns with the pair of BFloat16 values in the first source vector. The instruction does not update the <xref linkend="AArch32.fpscr">FPSCR</xref> exception status.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VDOT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VDOT_bf16_i/A1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="op1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VDOT_s_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VDOT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VDOT_s_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VDOT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VDOT_bf16_i/A1_A.txt" mylink="aarch32.instrs.VDOT_bf16_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);</line>
<line>integer i = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
<line>integer regs = if Q == '1' then 2 else 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VDOT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VDOT_bf16_i/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="op1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VDOT_s_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VDOT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VDOT_s_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VDOT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VDOT_bf16_i/T1_A.txt" mylink="aarch32.instrs.VDOT_bf16_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);</line>
<line>integer i = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
<line>integer regs = if Q == '1' then 2 else 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VDOT_s_A1_D, VDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDOT_s_A1_Q, VDOT_s_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDOT_s_A1_Q, VDOT_s_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDOT_s_A1_D, VDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDOT_s_A1_D, VDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDOT_s_A1_D, VDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDOT_s_A1_D, VDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_index">&lt;index&gt;</symbol>
      <account encodedin="M">
        <intro>
          <para>Is the element index in the range 0 to 1, encoded in the "M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VDOT_bf16_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>bits(64) operand1;</line>
<line>bits(64) operand2;</line>
<line>bits(64) result;</line>
<line></line>
<line><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>operand2 = <a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m];</line>
<line>for r = 0 to regs-1</line>
<line>    operand1 = <a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r];</line>
<line>    result = <a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r];</line>
<line>    for e = 0 to 1</line>
<line>        bits(16) elt1_a = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * e + 0, 16];</line>
<line>        bits(16) elt1_b = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * e + 1, 16];</line>
<line>        bits(16) elt2_a = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * i + 0, 16];</line>
<line>        bits(16) elt2_b = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * i + 1, 16];</line>
<line>        bits(32) sum = <a link="impl-shared.FPAdd_BF16.2" file="shared_pseudocode.xml" hover="function: bits(32) FPAdd_BF16(bits(32) op1, bits(32) op2)">FPAdd_BF16</a>(<a link="impl-shared.BFMulH.2" file="shared_pseudocode.xml" hover="function: bits(32) BFMulH(bits(16) op1, bits(16) op2)">BFMulH</a>(elt1_a, elt2_a), <a link="impl-shared.BFMulH.2" file="shared_pseudocode.xml" hover="function: bits(32) BFMulH(bits(16) op1, bits(16) op2)">BFMulH</a>(elt1_b, elt2_b));</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = <a link="impl-shared.FPAdd_BF16.2" file="shared_pseudocode.xml" hover="function: bits(32) FPAdd_BF16(bits(32) op1, bits(32) op2)">FPAdd_BF16</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 32], sum);</line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vdup_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VDUP_r" title="VDUP (general-purpose register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VDUP" />
  </docvars>
  <heading>VDUP (general-purpose register)</heading>
  <desc>
    <brief>
      <para>Duplicate general-purpose register to vector</para>
    </brief>
    <authored>
      <para>Duplicate general-purpose register to vector duplicates an element from a general-purpose register into every element of the destination vector.</para>
      <para>The destination vector elements can be 8-bit, 16-bit, or 32-bit fields. The source element is the least significant 8, 16, or 32 bits of the general-purpose register. There is no distinction between data types.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VDUP" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VDUP_r/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="B" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="E" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="VDUP_r_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VDUP" />
        </docvars>
        <asmtemplate comment="Encoded as Q = 1"><text>VDUP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="The data size for elements of destination vector">&lt;size&gt;</a><text> </text><a link="sa_qd" hover="The destination vector for a quadword operation">&lt;Qd&gt;</a><text>, </text><a link="sa_rt" hover="The Arm source register">&lt;Rt&gt;</a></asmtemplate>
        <asmtemplate comment="Encoded as Q = 0"><text>VDUP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="The data size for elements of destination vector">&lt;size&gt;</a><text> </text><a link="sa_dd" hover="The destination vector for a doubleword operation">&lt;Dd&gt;</a><text>, </text><a link="sa_rt" hover="The Arm source register">&lt;Rt&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VDUP_r/T1A1_A.txt" mylink="aarch32.instrs.VDUP_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  regs = if Q == '0' then 1 else 2;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case B:E of</line>
<line>    when '00'  esize = 32;  elements = 2;</line>
<line>    when '01'  esize = 16;  elements = 4;</line>
<line>    when '10'  esize = 8;   elements = 8;</line>
<line>    when '11'  UNDEFINED;</line>
<line>if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VDUP" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VDUP_r/T1A1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="B" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="E" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="VDUP_r_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VDUP" />
        </docvars>
        <asmtemplate comment="Encoded as Q = 1"><text>VDUP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="The data size for elements of destination vector">&lt;size&gt;</a><text> </text><a link="sa_qd" hover="The destination vector for a quadword operation">&lt;Qd&gt;</a><text>, </text><a link="sa_rt" hover="The Arm source register">&lt;Rt&gt;</a></asmtemplate>
        <asmtemplate comment="Encoded as Q = 0"><text>VDUP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="The data size for elements of destination vector">&lt;size&gt;</a><text> </text><a link="sa_dd" hover="The destination vector for a doubleword operation">&lt;Dd&gt;</a><text>, </text><a link="sa_rt" hover="The Arm source register">&lt;Rt&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VDUP_r/T1A1_A.txt" mylink="aarch32.instrs.VDUP_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  regs = if Q == '0' then 1 else 2;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case B:E of</line>
<line>    when '00'  esize = 32;  elements = 2;</line>
<line>    when '01'  esize = 16;  elements = 4;</line>
<line>    when '10'  esize = 8;   elements = 8;</line>
<line>    when '11'  UNDEFINED;</line>
<line>if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VDUP_r_A1, VDUP_r_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. Arm strongly recommends that any <instruction>VDUP</instruction> instruction is unconditional, see <xref linkend="BABGABFG">Conditional execution</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDUP_r_A1, VDUP_r_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDUP_r_A1, VDUP_r_T1" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The data size for the elements of the destination vector. It must be one of:</para>
          <list type="param">
            <listitem>
              <param>8</param><content>Encoded as [b, e] = <binarynumber>0b10</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>16</param><content>Encoded as [b, e] = <binarynumber>0b01</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>32</param><content>Encoded as [b, e] = <binarynumber>0b00</binarynumber>.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDUP_r_A1, VDUP_r_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The destination vector for a quadword operation.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDUP_r_A1, VDUP_r_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The destination vector for a doubleword operation.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDUP_r_A1, VDUP_r_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The Arm source register.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VDUP_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    scalar = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]&lt;esize-1:0&gt;;</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = scalar;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vdup_s.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VDUP_s" title="VDUP (scalar) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VDUP" />
  </docvars>
  <heading>VDUP (scalar)</heading>
  <desc>
    <brief>
      <para>Duplicate vector element to vector</para>
    </brief>
    <authored>
      <para>Duplicate vector element to vector duplicates a single element of a vector into every element of the destination vector.</para>
      <para>The scalar, and the destination vector elements, can be any one of 8-bit, 16-bit, or 32-bit fields. There is no distinction between data types.</para>
      <para>For more information about scalars see <xref linkend="Cjaibjhd">Advanced SIMD scalars</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VDUP" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VDUP_s/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="3" name="opc" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VDUP_s_A1_D" oneofinclass="2" oneof="4" label="" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VDUP" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VDUP</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="The data size">&lt;size&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm_x" hover="The scalar">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VDUP_s_A1_Q" oneofinclass="2" oneof="4" label="" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VDUP" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VDUP</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="The data size">&lt;size&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dm_x" hover="The scalar">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VDUP_s/T1A1_A.txt" mylink="aarch32.instrs.VDUP_s.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if imm4 IN {'x000'} then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer index;</line>
<line>case imm4 of</line>
<line>    when 'xxx1'  esize = 8;  elements = 8;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm4&lt;3:1&gt;);</line>
<line>    when 'xx10'  esize = 16;  elements = 4;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm4&lt;3:2&gt;);</line>
<line>    when 'x100'  esize = 32;  elements = 2;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm4&lt;3&gt;);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VDUP" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VDUP_s/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="3" name="opc" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VDUP_s_T1_D" oneofinclass="2" oneof="4" label="" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VDUP" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VDUP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="The data size">&lt;size&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm_x" hover="The scalar">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VDUP_s_T1_Q" oneofinclass="2" oneof="4" label="" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VDUP" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VDUP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="The data size">&lt;size&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dm_x" hover="The scalar">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VDUP_s/T1A1_A.txt" mylink="aarch32.instrs.VDUP_s.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if imm4 IN {'x000'} then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer index;</line>
<line>case imm4 of</line>
<line>    when 'xxx1'  esize = 8;  elements = 8;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm4&lt;3:1&gt;);</line>
<line>    when 'xx10'  esize = 16;  elements = 4;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm4&lt;3:2&gt;);</line>
<line>    when 'x100'  esize = 32;  elements = 2;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm4&lt;3&gt;);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VDUP_s_A1_D" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDUP_s_T1_D" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDUP_s_A1_D, VDUP_s_T1_D" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDUP_s_A1_D, VDUP_s_T1_D" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The data size. It must be one of:</para>
          <list type="param">
            <listitem>
              <param>8</param><content>Encoded as imm4&lt;0&gt; = '1'. imm4&lt;3:1&gt; encodes the index<syntax>[x]</syntax> of the scalar.</content>
            </listitem>
            <listitem>
              <param>16</param><content>Encoded as imm4&lt;1:0&gt; = '10'. imm4&lt;3:2&gt; encodes the index <syntax>[x]</syntax> of the scalar.</content>
            </listitem>
            <listitem>
              <param>32</param><content>Encoded as imm4&lt;2:0&gt; = '100'. imm4&lt;3&gt; encodes the index <syntax>[x]</syntax> of the scalar.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDUP_s_A1_Q, VDUP_s_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDUP_s_A1_D, VDUP_s_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VDUP_s_A1_D, VDUP_s_T1_D" symboldefcount="1">
      <symbol link="sa_dm_x">&lt;Dm[x]&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The scalar. For details of how <syntax>[x]</syntax> is encoded, see the description of <syntax>&lt;size&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VDUP_s/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    scalar = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m],index,esize];</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = scalar;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="veor.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VEOR" title="VEOR -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VEOR" />
  </docvars>
  <heading>VEOR</heading>
  <desc>
    <brief>
      <para>Vector Bitwise Exclusive-OR</para>
    </brief>
    <authored>
      <para>Vector Bitwise Exclusive-OR performs a bitwise exclusive-OR operation between two registers, and places the result in the destination register. The operand and result registers can be quadword or doubleword. They must all be the same size.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VEOR" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VEOR/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VEOR_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VEOR" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VEOR</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VEOR_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VEOR" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VEOR</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VEOR/T1A1_A.txt" mylink="aarch32.instrs.VEOR.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VEOR" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VEOR/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VEOR_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VEOR" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VEOR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VEOR_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VEOR" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VEOR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VEOR/T1A1_A.txt" mylink="aarch32.instrs.VEOR.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VEOR_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEOR_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEOR_A1_Q, VEOR_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEOR_A1_Q, VEOR_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>An optional data type. It is ignored by assemblers, and does not affect the encoding.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEOR_A1_Q, VEOR_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEOR_A1_Q, VEOR_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEOR_A1_Q, VEOR_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEOR_A1_D, VEOR_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEOR_A1_D, VEOR_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEOR_A1_D, VEOR_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VEOR/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r] EOR <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r];</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vext.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VEXT" title="VEXT (byte elements) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VEXT" />
  </docvars>
  <heading>VEXT (byte elements)</heading>
  <desc>
    <brief>
      <para>Vector Extract</para>
    </brief>
    <authored>
      <para>Vector Extract extracts elements from the bottom end of the second operand vector and the top end of the first, concatenates them and places the result in the destination vector.</para>
      <para>The elements of the vectors are treated as being 8-bit fields. There is no distinction between data types.</para>
      <para><image file="vext_doubleword_operation_for_imm_3.svg" label="VEXT doubleword operation for imm = 3"></image></para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="1">
    <alias_list_intro>This instruction is used by the alias </alias_list_intro>
    <aliasref aliaspageid="VEXT_VEXT" aliasfile="vext_vext.xml" hover="Vector Extract" punct=".">
      <text>VEXT (multibyte elements)</text>
      <aliaspref>Never</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink />
      <text> below for details of when the alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VEXT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VEXT/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VEXT_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VEXT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VEXT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.8 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm_1" hover="Location of extracted result in the concatenation of the operands (field &quot;imm4&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VEXT_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VEXT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VEXT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.8 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Location of extracted result in the concatenation of the operands (field &quot;imm4&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VEXT/T1A1_A.txt" mylink="aarch32.instrs.VEXT.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if Q == '0' &amp;&amp; imm4&lt;3&gt; == '1' then UNDEFINED;</line>
<line>quadword_operation = (Q == '1');  position = 8 * <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VEXT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VEXT/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VEXT_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VEXT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VEXT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.8 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm_1" hover="Location of extracted result in the concatenation of the operands (field &quot;imm4&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VEXT_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VEXT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VEXT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.8 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Location of extracted result in the concatenation of the operands (field &quot;imm4&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VEXT/T1A1_A.txt" mylink="aarch32.instrs.VEXT.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if Q == '0' &amp;&amp; imm4&lt;3&gt; == '1' then UNDEFINED;</line>
<line>quadword_operation = (Q == '1');  position = 8 * <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VEXT_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEXT_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEXT_A1_Q, VEXT_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEXT_A1_Q, VEXT_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEXT_A1_Q, VEXT_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEXT_A1_Q, VEXT_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEXT_A1_D, VEXT_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEXT_A1_D, VEXT_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEXT_A1_D, VEXT_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEXT_A1_D, VEXT_T1_D" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm4">
        <docvars>
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <intro>
          <para>For the 64-bit SIMD vector variant: is the location of the extracted result in the concatenation of the operands, as a number of bytes from the least significant end, in the range 0 to 7, encoded in the "imm4" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEXT_A1_Q, VEXT_T1_Q" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm4">
        <docvars>
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <intro>
          <para>For the 128-bit SIMD vector variant: is the location of the extracted result in the concatenation of the operands, as a number of bytes from the least significant end, in the range 0 to 15, encoded in the "imm4" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VEXT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    if quadword_operation then</line>
<line>        <a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = (<a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1]:<a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[n&gt;&gt;1])&lt;position+127:position&gt;;</line>
<line>    else</line>
<line>        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = (<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m]:<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n])&lt;position+63:position&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vext_vext.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VEXT_VEXT" title="VEXT (multibyte elements) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="VEXT" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VEXT" />
  </docvars>
  <heading>VEXT (multibyte elements)</heading>
  <desc>
    <brief>Vector Extract</brief>
    <longer> extracts elements from the bottom end of the second operand vector and the top end of the first, concatenates them and places the result in the destination vector</longer>
  </desc>
  <aliasto refiform="vext.xml" iformid="VEXT">VEXT (byte elements)</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VEXT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VEXT_VEXT_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VEXT" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VEXT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VEXT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size_1" hover="Size of operation, and can be one of 16 or 32">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm_3" hover="Location of extracted result in the concatenation of the operands">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vext.xml#VEXT_A1_D">VEXT</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.8 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a>&lt;imm*(size/8)&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VEXT_VEXT_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VEXT" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VEXT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VEXT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Size of operation, and can be one of 16, 32 or 64">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm_2" hover="Location of extracted result in the concatenation of the operands">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vext.xml#VEXT_A1_Q">VEXT</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.8 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a>&lt;imm*(size/8)&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VEXT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VEXT_VEXT_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VEXT" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VEXT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VEXT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size_1" hover="Size of operation, and can be one of 16 or 32">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm_3" hover="Location of extracted result in the concatenation of the operands">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vext.xml#VEXT_T1_D">VEXT</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.8 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a>&lt;imm*(size/8)&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VEXT_VEXT_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VEXT" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VEXT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VEXT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Size of operation, and can be one of 16, 32 or 64">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm_2" hover="Location of extracted result in the concatenation of the operands">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vext.xml#VEXT_T1_Q">VEXT</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.8 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a>&lt;imm*(size/8)&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VEXT_VEXT_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEXT_VEXT_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEXT_VEXT_A1_Q, VEXT_VEXT_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEXT_VEXT_A1_D, VEXT_VEXT_T1_D" symboldefcount="1">
      <symbol link="sa_size_1">&lt;size&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <intro>
          <para>For the 64-bit SIMD vector variant: is the size of the operation, and can be one of 16 or 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEXT_VEXT_A1_Q, VEXT_VEXT_T1_Q" symboldefcount="2">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <intro>
          <para>For the 128-bit SIMD vector variant: is the size of the operation, and can be one of 16, 32 or 64.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEXT_VEXT_A1_Q, VEXT_VEXT_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEXT_VEXT_A1_Q, VEXT_VEXT_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEXT_VEXT_A1_Q, VEXT_VEXT_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEXT_VEXT_A1_D, VEXT_VEXT_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEXT_VEXT_A1_D, VEXT_VEXT_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEXT_VEXT_A1_D, VEXT_VEXT_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEXT_VEXT_A1_D, VEXT_VEXT_T1_D" symboldefcount="1">
      <symbol link="sa_imm_3">&lt;imm&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <intro>
          <para>For the 64-bit SIMD vector variant: is the location of the extracted result in the concatenation of the operands, as a number of bytes from the least significant end, in the range 0 to (128/<syntax>&lt;size&gt;</syntax>)-1.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VEXT_VEXT_A1_Q, VEXT_VEXT_T1_Q" symboldefcount="2">
      <symbol link="sa_imm_2">&lt;imm&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <intro>
          <para>For the 128-bit SIMD vector variant: is the location of the extracted result in the concatenation of the operands, as a number of bytes from the least significant end, in the range 0 to (64/<syntax>&lt;size&gt;</syntax>)-1.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="vfma.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VFMA" title="VFMA -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VFMA" />
  </docvars>
  <heading>VFMA</heading>
  <desc>
    <brief>
      <para>Vector Fused Multiply Accumulate</para>
    </brief>
    <authored>
      <para>Vector Fused Multiply Accumulate multiplies corresponding elements of two vectors, and accumulates the results into the elements of the destination vector. The instruction does not round the result of the multiply before the accumulation.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VFMA" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VFMA/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMA_A1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMA" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VFMA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFMA_A1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VFMA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMA/A1_A.txt" mylink="aarch32.instrs.VFMA.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>advsimd = TRUE; op1_neg = (op == '1');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VFMA" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VFMA/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMA_A2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMA" />
          <docvar key="mnemonic-fpdatasize" value="VFMA-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VFMA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFMA_A2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMA" />
          <docvar key="mnemonic-fpdatasize" value="VFMA-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VFMA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFMA_A2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMA" />
          <docvar key="mnemonic-fpdatasize" value="VFMA-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VFMA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMA/A2_A.txt" mylink="aarch32.instrs.VFMA.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>advsimd = FALSE; op1_neg = (op == '1');</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VFMA" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VFMA/T1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMA_T1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMA" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VFMA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFMA_T1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VFMA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMA/T1_A.txt" mylink="aarch32.instrs.VFMA.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>advsimd = TRUE; op1_neg = (op == '1');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>sz == '1' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VFMA" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VFMA/T2_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMA_T2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMA" />
          <docvar key="mnemonic-fpdatasize" value="VFMA-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VFMA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFMA_T2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMA" />
          <docvar key="mnemonic-fpdatasize" value="VFMA-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VFMA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFMA_T2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMA" />
          <docvar key="mnemonic-fpdatasize" value="VFMA-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VFMA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMA/T2_A.txt" mylink="aarch32.instrs.VFMA.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>advsimd = FALSE; op1_neg = (op == '1');</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VFMA_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_A2_H, VFMA_T1_Q, VFMA_T2_H" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For encoding A2, T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_A1_Q, VFMA_A2_H, VFMA_T1_Q, VFMA_T2_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_A1_Q, VFMA_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VFMA_A1_Q, VFMA_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_A1_Q, VFMA_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_A1_Q, VFMA_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_A1_D, VFMA_A2_D, VFMA_T1_D, VFMA_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_A1_D, VFMA_A2_D, VFMA_T1_D, VFMA_T2_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_A1_D, VFMA_A2_D, VFMA_T1_D, VFMA_T2_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_A2_H, VFMA_T2_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_A2_H, VFMA_T2_H" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_A2_H, VFMA_T2_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VFMA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDOrVFPEnabled.2" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDOrVFPEnabled(boolean include_fpexc_check, boolean advsimd)">CheckAdvSIMDOrVFPEnabled</a>(TRUE, advsimd);</line>
<line>    if advsimd then // Advanced SIMD instruction</line>
<line>        for r = 0 to regs-1</line>
<line>            for e = 0 to elements-1</line>
<line>                bits(esize) op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize];</line>
<line>                if op1_neg then op1 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(op1);</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r],e,esize],</line>
<line>                                       op1, <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line></line>
<line>    else // VFP instruction</line>
<line>        case esize of</line>
<line>            when 16</line>
<line>                op16 = if op1_neg then <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;) else <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;;</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]&lt;15:0&gt;, op16, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[]);</line>
<line>            when 32</line>
<line>                op32 = if op1_neg then <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]) else <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n];</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d], op32, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[]);</line>
<line>            when 64</line>
<line>                op64 = if op1_neg then <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n]) else <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n];</line>
<line>                <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d], op64, <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vfma_bf.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VFMA_bf" title="VFMAB, VFMAT (BFloat16, vector) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VFMA" />
    <docvar key="simdvectorsize" value="quad" />
  </docvars>
  <heading>VFMAB, VFMAT (BFloat16, vector)</heading>
  <desc>
    <brief>
      <para>BFloat16 floating-point widening multiply-add long (vector)</para>
    </brief>
    <authored>
      <para>The Bfloat16 floating-point widening multiply-add long instruction widens the even-numbered (bottom) or odd-numbered (top) 16-bit elements in the first and second source vectors from Bfloat16 to single-precision format. The instruction then multiplies and adds these values to the overlapping single-precision elements of the destination vector.</para>
      <para>Unlike other BFloat16 multiplication instructions, this performs a fused multiply-add, without intermediate rounding that uses the Round to Nearest rounding mode and can generate a floating-point exception that causes cumulative exception bits in the <xref linkend="AArch32.fpscr">FPSCR</xref> to be set.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VFMA" />
        <docvar key="simdvectorsize" value="quad" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VFMA_bf/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="op1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMA_bf_A1_Q" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <asmtemplate><text>VFMA</text><a link="sa_bt" hover="Bottom or top element specifier (field &quot;Q&quot;)">&lt;bt&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMA_bf/A1_A.txt" mylink="aarch32.instrs.VFMA_bf.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>integer elements = 128 DIV 32;</line>
<line>integer sel = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Q);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VFMA" />
        <docvar key="simdvectorsize" value="quad" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VFMA_bf/T1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="op1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMA_bf_T1_Q" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <asmtemplate><text>VFMA</text><a link="sa_bt" hover="Bottom or top element specifier (field &quot;Q&quot;)">&lt;bt&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMA_bf/T1_A.txt" mylink="aarch32.instrs.VFMA_bf.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>integer elements = 128 DIV 32;</line>
<line>integer sel = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Q);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VFMA_bf_A1_Q, VFMA_bf_T1_Q" symboldefcount="1">
      <symbol link="sa_bt">&lt;bt&gt;</symbol>
      <definition encodedin="Q">
        <intro>Is the bottom or top element specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">Q</entry>
                <entry class="symbol">&lt;bt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">B</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">T</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VFMA_bf_A1_Q, VFMA_bf_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_bf_A1_Q, VFMA_bf_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_bf_A1_Q, VFMA_bf_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_bf_A1_Q, VFMA_bf_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VFMA_bf/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>bits(128) operand1 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[n&gt;&gt;1];</line>
<line>bits(128) operand2 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1];</line>
<line>bits(128) operand3 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[d&gt;&gt;1];</line>
<line>bits(128) result;</line>
<line></line>
<line>for e = 0 to elements-1</line>
<line>    bits(32) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * e + sel, 16] : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>    bits(32) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * e + sel, 16] : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>    bits(32) addend = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 32];</line>
<line>    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(addend, element1, element2,</line>
<line>                                   <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line></line>
<line><a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vfma_bfs.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VFMA_bfs" title="VFMAB, VFMAT (BFloat16, by scalar) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VFMA" />
    <docvar key="simdvectorsize" value="quad" />
  </docvars>
  <heading>VFMAB, VFMAT (BFloat16, by scalar)</heading>
  <desc>
    <brief>
      <para>BFloat16 floating-point widening multiply-add long (by scalar)</para>
    </brief>
    <authored>
      <para>The BFloat16 floating-point widening multiply-add long instruction widens the even-numbered (bottom) or odd-numbered (top) 16-bit elements in the first source vector, and an indexed element in the second source vector from Bfloat16 to single-precision format. The instruction then multiplies and adds these values to the overlapping single-precision elements of the destination vector.</para>
      <para>Unlike other BFloat16 multiplication instructions, this performs a fused multiply-add, without intermediate rounding that uses the Round to Nearest rounding mode and can generate a floating-point exception that causes cumulative exception bits in the <xref linkend="AArch32.fpscr">FPSCR</xref> to be set.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VFMA" />
        <docvar key="simdvectorsize" value="quad" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VFMA_bfs/A1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="op1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMA_bfs_A1_Q" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <asmtemplate><text>VFMA</text><a link="sa_bt" hover="Bottom or top element specifier (field &quot;Q&quot;)">&lt;bt&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-3] (field &quot;M:Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMA_bfs/A1_A.txt" mylink="aarch32.instrs.VFMA_bfs.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);</line>
<line>integer i = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>integer elements = 128 DIV 32;</line>
<line>integer sel = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Q);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VFMA" />
        <docvar key="simdvectorsize" value="quad" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VFMA_bfs/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="op1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMA_bfs_T1_Q" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <asmtemplate><text>VFMA</text><a link="sa_bt" hover="Bottom or top element specifier (field &quot;Q&quot;)">&lt;bt&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-3] (field &quot;M:Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMA_bfs/T1_A.txt" mylink="aarch32.instrs.VFMA_bfs.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);</line>
<line>integer i = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>integer elements = 128 DIV 32;</line>
<line>integer sel = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Q);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VFMA_bfs_A1_Q, VFMA_bfs_T1_Q" symboldefcount="1">
      <symbol link="sa_bt">&lt;bt&gt;</symbol>
      <definition encodedin="Q">
        <intro>Is the bottom or top element specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">Q</entry>
                <entry class="symbol">&lt;bt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">B</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">T</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VFMA_bfs_A1_Q, VFMA_bfs_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_bfs_A1_Q, VFMA_bfs_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_bfs_A1_Q, VFMA_bfs_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_bfs_A1_Q, VFMA_bfs_T1_Q" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="Vm&lt;2:0&gt;">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "Vm&lt;2:0&gt;" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_bfs_A1_Q, VFMA_bfs_T1_Q" symboldefcount="1">
      <symbol link="sa_index">&lt;index&gt;</symbol>
      <account encodedin="M:Vm&lt;3&gt;">
        <intro>
          <para>Is the element index in the range 0 to 3, encoded in the "M:Vm&lt;3&gt;" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VFMA_bfs/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>bits(128) operand1 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[n&gt;&gt;1];</line>
<line>bits(64) operand2 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m];</line>
<line>bits(128) operand3 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[d&gt;&gt;1];</line>
<line>bits(128) result;</line>
<line></line>
<line>bits(32) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, i, 16] : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line></line>
<line>for e = 0 to elements-1</line>
<line>    bits(32) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * e + sel, 16] : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>    bits(32) addend = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 32];</line>
<line>    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(addend, element1, element2,</line>
<line>                                   <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line></line>
<line><a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vfmal.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VFMAL" title="VFMAL (vector) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VFMAL" />
  </docvars>
  <heading>VFMAL (vector)</heading>
  <desc>
    <brief>
      <para>Vector Floating-point Multiply-Add Long to accumulator (vector)</para>
    </brief>
    <authored>
      <para>Vector Floating-point Multiply-Add Long to accumulator (vector). This instruction multiplies corresponding values in the vectors in the two source SIMD&amp;FP registers, and accumulates the product to the corresponding vector element of the destination SIMD&amp;FP register. The instruction does not round the result of the multiply before the accumulation.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
      <para>In Armv8.2 and Armv8.3, this is an <arm-defined-word>optional</arm-defined-word> instruction. From Armv8.4 it is mandatory for all implementations to support it.</para>
      <note>
        <para><xref linkend="AArch32.id_isar6">ID_ISAR6</xref>.FHM indicates whether this instruction is supported.</para>
      </note>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VFMAL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_FHM" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VFMAL/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMAL_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMAL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VFMAL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFMAL_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMAL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VFMAL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMAL/A1_A.txt" mylink="aarch32.instrs.VFMAL.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveFP16MulNoRoundingToFP32Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16MulNoRoundingToFP32Ext()">HaveFP16MulNoRoundingToFP32Ext</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line></line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N);</line>
<line>integer m = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>integer esize = 32;</line>
<line>integer regs = if Q=='1' then 2 else 1;</line>
<line>integer datasize = if Q=='1' then 64 else 32;</line>
<line>boolean sub_op = S=='1';</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VFMAL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_FHM" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VFMAL/T1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMAL_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMAL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VFMAL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFMAL_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMAL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VFMAL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMAL/T1_A.txt" mylink="aarch32.instrs.VFMAL.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveFP16MulNoRoundingToFP32Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16MulNoRoundingToFP32Ext()">HaveFP16MulNoRoundingToFP32Ext</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line></line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N);</line>
<line>integer m = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>integer esize = 32;</line>
<line>integer regs = if Q=='1' then 2 else 1;</line>
<line>integer datasize = if Q=='1' then 64 else 32;</line>
<line>boolean sub_op = S=='1';</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VFMAL_A1_Q, VFMAL_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMAL_A1_Q, VFMAL_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMAL_A1_Q, VFMAL_T1_Q" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMAL_A1_Q, VFMAL_T1_Q" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMAL_A1_D, VFMAL_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMAL_A1_D, VFMAL_T1_D" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMAL_A1_D, VFMAL_T1_D" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VFMAL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>bits(datasize) operand1 ;</line>
<line>bits(datasize) operand2 ;</line>
<line>bits(64) operand3;</line>
<line>bits(64) result;</line>
<line>bits(esize DIV 2) element1;</line>
<line>bits(esize DIV 2) element2;</line>
<line></line>
<line>if Q=='0' then</line>
<line>    operand1 = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;datasize-1:0&gt;;</line>
<line>    operand2 = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;datasize-1:0&gt;;</line>
<line>else</line>
<line>    operand1 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n]&lt;datasize-1:0&gt;;</line>
<line>    operand2 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m]&lt;datasize-1:0&gt;;</line>
<line>for r = 0 to regs-1</line>
<line>    operand3 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r];</line>
<line>    for e = 0 to 1</line>
<line>        element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*r+e, esize DIV 2];</line>
<line>        element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*r+e, esize DIV 2];</line>
<line>        if sub_op then element1 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.FPMulAddH.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAddH(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, FPCRType fpcr)">FPMulAddH</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2,</line>
<line>                                           <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vfmal_s.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VFMAL_s" title="VFMAL (by scalar) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VFMAL" />
  </docvars>
  <heading>VFMAL (by scalar)</heading>
  <desc>
    <brief>
      <para>Vector Floating-point Multiply-Add Long to accumulator (by scalar)</para>
    </brief>
    <authored>
      <para>Vector Floating-point Multiply-Add Long to accumulator (by scalar). This instruction multiplies the vector elements in the first source SIMD&amp;FP register by the specified value in the second source SIMD&amp;FP register, and accumulates the product to the corresponding vector element of the destination SIMD&amp;FP register. The instruction does not round the result of the multiply before the accumulation.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
      <para>In Armv8.2 and Armv8.3, this is an <arm-defined-word>optional</arm-defined-word> instruction. From Armv8.4 it is mandatory for all implementations to support it.</para>
      <note>
        <para><xref linkend="AArch32.id_isar6">ID_ISAR6</xref>.FHM indicates whether this instruction is supported.</para>
      </note>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VFMAL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_FHM" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VFMAL_i/A1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="op1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMAL_s_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMAL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VFMAL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;:M&quot;)">&lt;Sm&gt;</a><text>[</text><a link="sa_index_1" hover="Element index [0-1] (field &quot;Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VFMAL_s_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMAL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VFMAL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-3] (field &quot;M:Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMAL_i/A1_A.txt" mylink="aarch32.instrs.VFMAL_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveFP16MulNoRoundingToFP32Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16MulNoRoundingToFP32Ext()">HaveFP16MulNoRoundingToFP32Ext</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line></line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N);</line>
<line>integer m = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;:M);</line>
<line></line>
<line>integer index = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;3&gt;);</line>
<line>integer esize = 32;</line>
<line>integer regs = if Q=='1' then 2 else 1;</line>
<line>integer datasize = if Q=='1' then 64 else 32;</line>
<line>boolean sub_op = S=='1';</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VFMAL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_FHM" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VFMAL_i/T1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="op1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMAL_s_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMAL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VFMAL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;:M&quot;)">&lt;Sm&gt;</a><text>[</text><a link="sa_index_1" hover="Element index [0-1] (field &quot;Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VFMAL_s_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMAL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VFMAL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-3] (field &quot;M:Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMAL_i/T1_A.txt" mylink="aarch32.instrs.VFMAL_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveFP16MulNoRoundingToFP32Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16MulNoRoundingToFP32Ext()">HaveFP16MulNoRoundingToFP32Ext</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line></line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N);</line>
<line>integer m = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;:M);</line>
<line></line>
<line>integer index = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;3&gt;);</line>
<line>integer esize = 32;</line>
<line>integer regs = if Q=='1' then 2 else 1;</line>
<line>integer datasize = if Q=='1' then 64 else 32;</line>
<line>boolean sub_op = S=='1';</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VFMAL_s_A1_Q, VFMAL_s_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMAL_s_A1_Q, VFMAL_s_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMAL_s_A1_Q, VFMAL_s_T1_Q" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMAL_s_A1_Q, VFMAL_s_T1_Q" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="Vm&lt;2:0&gt;">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "Vm&lt;2:0&gt;" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMAL_s_A1_D, VFMAL_s_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMAL_s_A1_D, VFMAL_s_T1_D" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMAL_s_A1_D, VFMAL_s_T1_D" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm&lt;2:0&gt;:M">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Vm&lt;2:0&gt;:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMAL_s_A1_D, VFMAL_s_T1_D" symboldefcount="1">
      <symbol link="sa_index_1">&lt;index&gt;</symbol>
      <account encodedin="Vm&lt;3&gt;">
        <docvars>
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <intro>
          <para>For the 64-bit SIMD vector variant: is the element index in the range 0 to 1, encoded in the "Vm&lt;3&gt;" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMAL_s_A1_Q, VFMAL_s_T1_Q" symboldefcount="2">
      <symbol link="sa_index">&lt;index&gt;</symbol>
      <account encodedin="M:Vm&lt;3&gt;">
        <docvars>
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <intro>
          <para>For the 128-bit SIMD vector variant: is the element index in the range 0 to 3, encoded in the "M:Vm&lt;3&gt;" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VFMAL_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>bits(datasize) operand1 ;</line>
<line>bits(datasize) operand2 ;</line>
<line>bits(64) operand3;</line>
<line>bits(64) result;</line>
<line>bits(esize DIV 2) element1;</line>
<line>bits(esize DIV 2) element2;</line>
<line></line>
<line>if Q=='0' then</line>
<line>    operand1 = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;datasize-1:0&gt;;</line>
<line>    operand2 = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;datasize-1:0&gt;;</line>
<line>else</line>
<line>    operand1 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n]&lt;datasize-1:0&gt;;</line>
<line>    operand2 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m]&lt;datasize-1:0&gt;;</line>
<line>element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize DIV 2];</line>
<line>for r = 0 to regs-1</line>
<line>    operand3 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r];</line>
<line>    for e = 0 to 1</line>
<line>        element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*r+e, esize DIV 2];</line>
<line>        if sub_op then element1 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.FPMulAddH.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAddH(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, FPCRType fpcr)">FPMulAddH</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2,</line>
<line>                                           <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vfms.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VFMS" title="VFMS -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VFMS" />
  </docvars>
  <heading>VFMS</heading>
  <desc>
    <brief>
      <para>Vector Fused Multiply Subtract</para>
    </brief>
    <authored>
      <para>Vector Fused Multiply Subtract negates the elements of one vector and multiplies them with the corresponding elements of another vector, adds the products to the corresponding elements of the destination vector, and places the results in the destination vector. The instruction does not round the result of the multiply before the addition.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VFMS" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VFMA/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMS_A1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMS" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VFMS</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFMS_A1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMS" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VFMS</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMA/A1_A.txt" mylink="aarch32.instrs.VFMA.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>advsimd = TRUE; op1_neg = (op == '1');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VFMS" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VFMA/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMS_A2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMS" />
          <docvar key="mnemonic-fpdatasize" value="VFMS-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VFMS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFMS_A2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMS" />
          <docvar key="mnemonic-fpdatasize" value="VFMS-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VFMS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFMS_A2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMS" />
          <docvar key="mnemonic-fpdatasize" value="VFMS-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VFMS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMA/A2_A.txt" mylink="aarch32.instrs.VFMA.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>advsimd = FALSE; op1_neg = (op == '1');</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VFMS" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VFMA/T1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMS_T1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMS" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VFMS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFMS_T1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMS" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VFMS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMA/T1_A.txt" mylink="aarch32.instrs.VFMA.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>advsimd = TRUE; op1_neg = (op == '1');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>sz == '1' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VFMS" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VFMA/T2_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMS_T2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMS" />
          <docvar key="mnemonic-fpdatasize" value="VFMS-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VFMS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFMS_T2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMS" />
          <docvar key="mnemonic-fpdatasize" value="VFMS-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VFMS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFMS_T2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMS" />
          <docvar key="mnemonic-fpdatasize" value="VFMS-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VFMS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMA/T2_A.txt" mylink="aarch32.instrs.VFMA.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>advsimd = FALSE; op1_neg = (op == '1');</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VFMS_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMS_A2_H, VFMS_T1_Q, VFMS_T2_H" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For encoding A2, T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMS_A1_Q, VFMS_A2_H, VFMS_T1_Q, VFMS_T2_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMS_A1_Q, VFMS_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VFMS_A1_Q, VFMS_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMS_A1_Q, VFMS_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMS_A1_Q, VFMS_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMS_A1_D, VFMS_A2_D, VFMS_T1_D, VFMS_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMS_A1_D, VFMS_A2_D, VFMS_T1_D, VFMS_T2_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMS_A1_D, VFMS_A2_D, VFMS_T1_D, VFMS_T2_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMS_A2_H, VFMS_T2_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMS_A2_H, VFMS_T2_H" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMS_A2_H, VFMS_T2_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VFMA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDOrVFPEnabled.2" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDOrVFPEnabled(boolean include_fpexc_check, boolean advsimd)">CheckAdvSIMDOrVFPEnabled</a>(TRUE, advsimd);</line>
<line>    if advsimd then // Advanced SIMD instruction</line>
<line>        for r = 0 to regs-1</line>
<line>            for e = 0 to elements-1</line>
<line>                bits(esize) op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize];</line>
<line>                if op1_neg then op1 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(op1);</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r],e,esize],</line>
<line>                                       op1, <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line></line>
<line>    else // VFP instruction</line>
<line>        case esize of</line>
<line>            when 16</line>
<line>                op16 = if op1_neg then <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;) else <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;;</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]&lt;15:0&gt;, op16, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[]);</line>
<line>            when 32</line>
<line>                op32 = if op1_neg then <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]) else <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n];</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d], op32, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[]);</line>
<line>            when 64</line>
<line>                op64 = if op1_neg then <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n]) else <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n];</line>
<line>                <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d], op64, <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vfmsl.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VFMSL" title="VFMSL (vector) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VFMSL" />
  </docvars>
  <heading>VFMSL (vector)</heading>
  <desc>
    <brief>
      <para>Vector Floating-point Multiply-Subtract Long from accumulator (vector)</para>
    </brief>
    <authored>
      <para>Vector Floating-point Multiply-Subtract Long from accumulator (vector). This instruction negates the values in the vector of one SIMD&amp;FP register, multiplies these with the corresponding values in another vector, and accumulates the product to the corresponding vector element of the destination SIMD&amp;FP register. The instruction does not round the result of the multiply before the accumulation.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
      <para>In Armv8.2 and Armv8.3, this is an <arm-defined-word>optional</arm-defined-word> instruction. From Armv8.4 it is mandatory for all implementations to support it.</para>
      <note>
        <para><xref linkend="AArch32.id_isar6">ID_ISAR6</xref>.FHM indicates whether this instruction is supported.</para>
      </note>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VFMSL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_FHM" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VFMAL/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMSL_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMSL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VFMSL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFMSL_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMSL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VFMSL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMAL/A1_A.txt" mylink="aarch32.instrs.VFMAL.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveFP16MulNoRoundingToFP32Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16MulNoRoundingToFP32Ext()">HaveFP16MulNoRoundingToFP32Ext</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line></line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N);</line>
<line>integer m = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>integer esize = 32;</line>
<line>integer regs = if Q=='1' then 2 else 1;</line>
<line>integer datasize = if Q=='1' then 64 else 32;</line>
<line>boolean sub_op = S=='1';</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VFMSL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_FHM" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VFMAL/T1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMSL_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMSL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VFMSL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFMSL_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMSL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VFMSL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMAL/T1_A.txt" mylink="aarch32.instrs.VFMAL.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveFP16MulNoRoundingToFP32Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16MulNoRoundingToFP32Ext()">HaveFP16MulNoRoundingToFP32Ext</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line></line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N);</line>
<line>integer m = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>integer esize = 32;</line>
<line>integer regs = if Q=='1' then 2 else 1;</line>
<line>integer datasize = if Q=='1' then 64 else 32;</line>
<line>boolean sub_op = S=='1';</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VFMSL_A1_Q, VFMSL_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMSL_A1_Q, VFMSL_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMSL_A1_Q, VFMSL_T1_Q" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMSL_A1_Q, VFMSL_T1_Q" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMSL_A1_D, VFMSL_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMSL_A1_D, VFMSL_T1_D" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMSL_A1_D, VFMSL_T1_D" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VFMAL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>bits(datasize) operand1 ;</line>
<line>bits(datasize) operand2 ;</line>
<line>bits(64) operand3;</line>
<line>bits(64) result;</line>
<line>bits(esize DIV 2) element1;</line>
<line>bits(esize DIV 2) element2;</line>
<line></line>
<line>if Q=='0' then</line>
<line>    operand1 = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;datasize-1:0&gt;;</line>
<line>    operand2 = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;datasize-1:0&gt;;</line>
<line>else</line>
<line>    operand1 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n]&lt;datasize-1:0&gt;;</line>
<line>    operand2 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m]&lt;datasize-1:0&gt;;</line>
<line>for r = 0 to regs-1</line>
<line>    operand3 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r];</line>
<line>    for e = 0 to 1</line>
<line>        element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*r+e, esize DIV 2];</line>
<line>        element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*r+e, esize DIV 2];</line>
<line>        if sub_op then element1 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.FPMulAddH.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAddH(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, FPCRType fpcr)">FPMulAddH</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2,</line>
<line>                                           <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vfmsl_s.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VFMSL_s" title="VFMSL (by scalar) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VFMSL" />
  </docvars>
  <heading>VFMSL (by scalar)</heading>
  <desc>
    <brief>
      <para>Vector Floating-point Multiply-Subtract Long from accumulator (by scalar)</para>
    </brief>
    <authored>
      <para>Vector Floating-point Multiply-Subtract Long from accumulator (by scalar). This instruction multiplies the negated vector elements in the first source SIMD&amp;FP register by the specified value in the second source SIMD&amp;FP register, and accumulates the product to the corresponding vector element of the destination SIMD&amp;FP register. The instruction does not round the result of the multiply before the accumulation.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
      <para>In Armv8.2 and Armv8.3, this is an <arm-defined-word>optional</arm-defined-word> instruction. From Armv8.4 it is mandatory for all implementations to support it.</para>
      <note>
        <para><xref linkend="AArch32.id_isar6">ID_ISAR6</xref>.FHM indicates whether this instruction is supported.</para>
      </note>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VFMSL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_FHM" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VFMAL_i/A1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="op1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMSL_s_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMSL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VFMSL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;:M&quot;)">&lt;Sm&gt;</a><text>[</text><a link="sa_index_1" hover="Element index [0-1] (field &quot;Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VFMSL_s_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMSL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VFMSL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-3] (field &quot;M:Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMAL_i/A1_A.txt" mylink="aarch32.instrs.VFMAL_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveFP16MulNoRoundingToFP32Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16MulNoRoundingToFP32Ext()">HaveFP16MulNoRoundingToFP32Ext</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line></line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N);</line>
<line>integer m = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;:M);</line>
<line></line>
<line>integer index = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;3&gt;);</line>
<line>integer esize = 32;</line>
<line>integer regs = if Q=='1' then 2 else 1;</line>
<line>integer datasize = if Q=='1' then 64 else 32;</line>
<line>boolean sub_op = S=='1';</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VFMSL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_FHM" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VFMAL_i/T1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="op1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMSL_s_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMSL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VFMSL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;:M&quot;)">&lt;Sm&gt;</a><text>[</text><a link="sa_index_1" hover="Element index [0-1] (field &quot;Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VFMSL_s_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMSL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VFMSL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-3] (field &quot;M:Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMAL_i/T1_A.txt" mylink="aarch32.instrs.VFMAL_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveFP16MulNoRoundingToFP32Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16MulNoRoundingToFP32Ext()">HaveFP16MulNoRoundingToFP32Ext</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line></line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N);</line>
<line>integer m = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;:M);</line>
<line></line>
<line>integer index = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;3&gt;);</line>
<line>integer esize = 32;</line>
<line>integer regs = if Q=='1' then 2 else 1;</line>
<line>integer datasize = if Q=='1' then 64 else 32;</line>
<line>boolean sub_op = S=='1';</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VFMSL_s_A1_Q, VFMSL_s_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMSL_s_A1_Q, VFMSL_s_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMSL_s_A1_Q, VFMSL_s_T1_Q" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMSL_s_A1_Q, VFMSL_s_T1_Q" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="Vm&lt;2:0&gt;">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "Vm&lt;2:0&gt;" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMSL_s_A1_D, VFMSL_s_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMSL_s_A1_D, VFMSL_s_T1_D" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMSL_s_A1_D, VFMSL_s_T1_D" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm&lt;2:0&gt;:M">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Vm&lt;2:0&gt;:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMSL_s_A1_D, VFMSL_s_T1_D" symboldefcount="1">
      <symbol link="sa_index_1">&lt;index&gt;</symbol>
      <account encodedin="Vm&lt;3&gt;">
        <docvars>
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <intro>
          <para>For the 64-bit SIMD vector variant: is the element index in the range 0 to 1, encoded in the "Vm&lt;3&gt;" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMSL_s_A1_Q, VFMSL_s_T1_Q" symboldefcount="2">
      <symbol link="sa_index">&lt;index&gt;</symbol>
      <account encodedin="M:Vm&lt;3&gt;">
        <docvars>
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <intro>
          <para>For the 128-bit SIMD vector variant: is the element index in the range 0 to 3, encoded in the "M:Vm&lt;3&gt;" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VFMAL_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>bits(datasize) operand1 ;</line>
<line>bits(datasize) operand2 ;</line>
<line>bits(64) operand3;</line>
<line>bits(64) result;</line>
<line>bits(esize DIV 2) element1;</line>
<line>bits(esize DIV 2) element2;</line>
<line></line>
<line>if Q=='0' then</line>
<line>    operand1 = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;datasize-1:0&gt;;</line>
<line>    operand2 = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;datasize-1:0&gt;;</line>
<line>else</line>
<line>    operand1 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n]&lt;datasize-1:0&gt;;</line>
<line>    operand2 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m]&lt;datasize-1:0&gt;;</line>
<line>element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize DIV 2];</line>
<line>for r = 0 to regs-1</line>
<line>    operand3 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r];</line>
<line>    for e = 0 to 1</line>
<line>        element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*r+e, esize DIV 2];</line>
<line>        if sub_op then element1 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.FPMulAddH.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAddH(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, FPCRType fpcr)">FPMulAddH</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2,</line>
<line>                                           <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vfnma.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VFNMA" title="VFNMA -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VFNMA" />
  </docvars>
  <heading>VFNMA</heading>
  <desc>
    <brief>
      <para>Vector Fused Negate Multiply Accumulate</para>
    </brief>
    <authored>
      <para>Vector Fused Negate Multiply Accumulate negates one floating-point register value and multiplies it by another floating-point register value, adds the negation of the floating-point value in the destination register to the product, and writes the result back to the destination register. The instruction does not round the result of the multiply before the addition.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VFNMA" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VFNMA/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFNMA_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFNMA" />
          <docvar key="mnemonic-fpdatasize" value="VFNMA-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VFNMA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFNMA_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFNMA" />
          <docvar key="mnemonic-fpdatasize" value="VFNMA-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VFNMA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFNMA_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFNMA" />
          <docvar key="mnemonic-fpdatasize" value="VFNMA-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VFNMA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFNMA/A1_A.txt" mylink="aarch32.instrs.VFNMA.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>op1_neg = (op == '1');</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VFNMA" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VFNMA/T1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFNMA_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFNMA" />
          <docvar key="mnemonic-fpdatasize" value="VFNMA-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VFNMA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFNMA_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFNMA" />
          <docvar key="mnemonic-fpdatasize" value="VFNMA-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VFNMA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFNMA_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFNMA" />
          <docvar key="mnemonic-fpdatasize" value="VFNMA-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VFNMA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFNMA/T1_A.txt" mylink="aarch32.instrs.VFNMA.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>op1_neg = (op == '1');</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VFNMA_A1_H, VFNMA_T1_H" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFNMA_A1_H, VFNMA_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFNMA_A1_H, VFNMA_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFNMA_A1_H, VFNMA_T1_H" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFNMA_A1_H, VFNMA_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFNMA_A1_D, VFNMA_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFNMA_A1_D, VFNMA_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFNMA_A1_D, VFNMA_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VFNMA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations(); <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    case esize of</line>
<line>        when 16</line>
<line>            op16 = if op1_neg then <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;) else <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;;</line>
<line>            <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]&lt;15:0&gt;), op16, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[]);</line>
<line>        when 32</line>
<line>            op32 = if op1_neg then <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]) else <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n];</line>
<line>            <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]), op32, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[]);</line>
<line>        when 64</line>
<line>            op64 = if op1_neg then <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n]) else <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n];</line>
<line>            <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d]), op64, <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vfnms.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VFNMS" title="VFNMS -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VFNMS" />
  </docvars>
  <heading>VFNMS</heading>
  <desc>
    <brief>
      <para>Vector Fused Negate Multiply Subtract</para>
    </brief>
    <authored>
      <para>Vector Fused Negate Multiply Subtract multiplies together two floating-point register values, adds the negation of the floating-point value in the destination register to the product, and writes the result back to the destination register. The instruction does not round the result of the multiply before the addition.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VFNMS" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VFNMA/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFNMS_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFNMS" />
          <docvar key="mnemonic-fpdatasize" value="VFNMS-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VFNMS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFNMS_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFNMS" />
          <docvar key="mnemonic-fpdatasize" value="VFNMS-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VFNMS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFNMS_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFNMS" />
          <docvar key="mnemonic-fpdatasize" value="VFNMS-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VFNMS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFNMA/A1_A.txt" mylink="aarch32.instrs.VFNMA.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>op1_neg = (op == '1');</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VFNMS" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VFNMA/T1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFNMS_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFNMS" />
          <docvar key="mnemonic-fpdatasize" value="VFNMS-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VFNMS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFNMS_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFNMS" />
          <docvar key="mnemonic-fpdatasize" value="VFNMS-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VFNMS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VFNMS_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFNMS" />
          <docvar key="mnemonic-fpdatasize" value="VFNMS-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VFNMS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFNMA/T1_A.txt" mylink="aarch32.instrs.VFNMA.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>op1_neg = (op == '1');</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VFNMS_A1_H, VFNMS_T1_H" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFNMS_A1_H, VFNMS_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFNMS_A1_H, VFNMS_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFNMS_A1_H, VFNMS_T1_H" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFNMS_A1_H, VFNMS_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFNMS_A1_D, VFNMS_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFNMS_A1_D, VFNMS_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFNMS_A1_D, VFNMS_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VFNMA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations(); <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    case esize of</line>
<line>        when 16</line>
<line>            op16 = if op1_neg then <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;) else <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;;</line>
<line>            <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]&lt;15:0&gt;), op16, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[]);</line>
<line>        when 32</line>
<line>            op32 = if op1_neg then <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]) else <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n];</line>
<line>            <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]), op32, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[]);</line>
<line>        when 64</line>
<line>            op64 = if op1_neg then <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n]) else <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n];</line>
<line>            <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d]), op64, <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vhadd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VHADD" title="VHADD -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VHADD" />
  </docvars>
  <heading>VHADD</heading>
  <desc>
    <brief>
      <para>Vector Halving Add</para>
    </brief>
    <authored>
      <para>Vector Halving Add adds corresponding elements in two vectors of integers, shifts each result right one bit, and places the final results in the destination vector. The results of the halving operations are truncated. For rounded results, see <xref linkend="A32T32-fpsimd.instructions.VRHADD">VRHADD</xref>).</para>
      <para>The operand and result elements are all the same type, and can be any one of:</para>
      <list type="unordered">
        <listitem><content>8-bit, 16-bit, or 32-bit signed integers.</content></listitem>
        <listitem><content>8-bit, 16-bit, or 32-bit unsigned integers.</content></listitem>
      </list>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VHADD" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VHADD/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VHADD_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VHADD" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VHADD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VHADD_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VHADD" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VHADD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VHADD/T1A1_A.txt" mylink="aarch32.instrs.VHADD.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>add = (op == '0');  unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VHADD" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VHADD/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VHADD_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VHADD" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VHADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VHADD_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VHADD" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VHADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VHADD/T1A1_A.txt" mylink="aarch32.instrs.VHADD.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>add = (op == '0');  unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VHADD_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VHADD_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VHADD_A1_Q, VHADD_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VHADD_A1_Q, VHADD_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VHADD_A1_Q, VHADD_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VHADD_A1_Q, VHADD_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VHADD_A1_Q, VHADD_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VHADD_A1_D, VHADD_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VHADD_A1_D, VHADD_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VHADD_A1_D, VHADD_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VHADD/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize], unsigned);</line>
<line>            op2 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], unsigned);</line>
<line>            result = (if add then op1+op2 else op1-op2) &gt;&gt; 1;</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result&lt;esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vhsub.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VHSUB" title="VHSUB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VHSUB" />
  </docvars>
  <heading>VHSUB</heading>
  <desc>
    <brief>
      <para>Vector Halving Subtract</para>
    </brief>
    <authored>
      <para>Vector Halving Subtract subtracts the elements of the second operand from the corresponding elements of the first operand, shifts each result right one bit, and places the final results in the destination vector. The results of the halving operations are truncated. There is no rounding version.</para>
      <para>The operand and result elements are all the same type, and can be any one of:</para>
      <list type="unordered">
        <listitem><content>8-bit, 16-bit, or 32-bit signed integers.</content></listitem>
        <listitem><content>8-bit, 16-bit, or 32-bit unsigned integers.</content></listitem>
      </list>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VHSUB" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VHADD/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VHSUB_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VHSUB" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VHSUB</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VHSUB_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VHSUB" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VHSUB</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VHADD/T1A1_A.txt" mylink="aarch32.instrs.VHADD.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>add = (op == '0');  unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VHSUB" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VHADD/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VHSUB_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VHSUB" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VHSUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VHSUB_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VHSUB" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VHSUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VHADD/T1A1_A.txt" mylink="aarch32.instrs.VHADD.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>add = (op == '0');  unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VHSUB_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VHSUB_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VHSUB_A1_Q, VHSUB_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VHSUB_A1_Q, VHSUB_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VHSUB_A1_Q, VHSUB_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VHSUB_A1_Q, VHSUB_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VHSUB_A1_Q, VHSUB_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VHSUB_A1_D, VHSUB_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VHSUB_A1_D, VHSUB_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VHSUB_A1_D, VHSUB_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VHADD/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize], unsigned);</line>
<line>            op2 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], unsigned);</line>
<line>            result = (if add then op1+op2 else op1-op2) &gt;&gt; 1;</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result&lt;esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vins.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VINS" title="VINS -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VINS" />
  </docvars>
  <heading>VINS</heading>
  <desc>
    <brief>
      <para>Vector move Insertion</para>
    </brief>
    <authored>
      <para>Vector move Insertion. This instruction copies the lower 16 bits of the 32-bit source SIMD&amp;FP register into the upper 16 bits of the 32-bit destination SIMD&amp;FP register, while preserving the values in the remaining bits.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VINS" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VINS/A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" settings="6">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VINS_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VINS" />
        </docvars>
        <asmtemplate><text>VINS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VINS/A1_A.txt" mylink="aarch32.instrs.VINS.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VINS" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VINS/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" settings="6">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VINS_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VINS" />
        </docvars>
        <asmtemplate><text>VINS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VINS/T1_A.txt" mylink="aarch32.instrs.VINS.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VINS_A1, VINS_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VINS_A1, VINS_T1" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VINS_A1, VINS_T1" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VINS/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt; : <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]&lt;15:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vjcvt.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VJCVT" title="VJCVT -- AArch32" type="instruction">
  <docvars>
    <docvar key="convert-type" value="double-to-single" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VJCVT" />
  </docvars>
  <heading>VJCVT</heading>
  <desc>
    <brief>
      <para>Javascript Convert to signed fixed-point, rounding toward Zero</para>
    </brief>
    <authored>
      <para>Javascript Convert to signed fixed-point, rounding toward Zero. This instruction converts the double-precision floating-point value in the SIMD&amp;FP source register to a 32-bit signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&amp;FP destination register. If the result is too large to be accommodated as a signed 32-bit integer, then the result is the integer modulo 2<sup>32</sup>, as held in a 32-bit signed integer.</para>
      <para>This instruction can generate a floating-point exception. Depending on the settings in <xref linkend="AArch32.fpscr">FPSCR</xref>, the exception results in either a flag being set or a synchronous exception being generated. For more information, see <xref linkend="CFIHBHHD">Floating-point exceptions and exception traps</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="convert-type" value="double-to-single" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VJCVT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.3" feature="FEAT_JSCVT" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VJCVT/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="o3" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VJCVT_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="convert-type" value="double-to-single" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VJCVT" />
        </docvars>
        <asmtemplate><text>VJCVT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S32.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VJCVT/A1_A.txt" mylink="aarch32.instrs.VJCVT.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveFJCVTZSExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveFJCVTZSExt()">HaveFJCVTZSExt</a>() then UNDEFINED;</line>
<line>if cond != '1110' then UNPREDICTABLE;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="convert-type" value="double-to-single" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VJCVT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.3" feature="FEAT_JSCVT" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VJCVT/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="o3" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VJCVT_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="convert-type" value="double-to-single" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VJCVT" />
        </docvars>
        <asmtemplate><text>VJCVT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S32.F64 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VJCVT/T1_A.txt" mylink="aarch32.instrs.VJCVT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveFJCVTZSExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveFJCVTZSExt()">HaveFJCVTZSExt</a>() then UNDEFINED;</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VJCVT_A1, VJCVT_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VJCVT_A1, VJCVT_T1" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VJCVT_A1, VJCVT_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VJCVT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations();</line>
<line><a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>bits(64) fltval = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m];</line>
<line>bits(32) intval;</line>
<line>bit      Z;</line>
<line>(intval, Z) = <a link="impl-shared.FPToFixedJS.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) FPToFixedJS(bits(M) op, FPCRType fpcr, boolean Is64, integer N)">FPToFixedJS</a>(fltval, FPSCR[], FALSE, 32);</line>
<line>FPSCR&lt;31:28&gt; = '0':Z:'00';</line>
<line><a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = intval;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vld1_1.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VLD1_1" title="VLD1 (single element to one lane) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VLD1" />
  </docvars>
  <heading>VLD1 (single element to one lane)</heading>
  <desc>
    <brief>
      <para>Load single 1-element structure to one lane of one register</para>
    </brief>
    <authored>
      <para>Load single 1-element structure to one lane of one register loads one element from memory into one element of a register. Elements of the register that are not loaded are unchanged. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For more information about the variants of this instruction, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="6">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>, </txt>
      <a href="#iclass_a2">A2</a>
      <txt> and </txt>
      <a href="#iclass_a3">A3</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="6" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD1_1/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_1_A1_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_1_A1_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_1_A1_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_1/T1A1_A.txt" mylink="aarch32.instrs.VLD1_1.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD1 (single element to all lanes)";</line>
<line>if index_align&lt;0&gt; != '0' then UNDEFINED;</line>
<line>ebytes = 1;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:1&gt;);  alignment = 1;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="6" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD1_1/T2A2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_1_A2_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_1_A2_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_1_A2_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_1/T2A2_A.txt" mylink="aarch32.instrs.VLD1_1.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD1 (single element to all lanes)";</line>
<line>if index_align&lt;1&gt; != '0' then UNDEFINED;</line>
<line>ebytes = 2;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:2&gt;);</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A3" oneof="6" id="iclass_a3" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD1_1/T3A3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_1_A3_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_1_A3_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_1_A3_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_1/T3A3_A.txt" mylink="aarch32.instrs.VLD1_1.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD1 (single element to all lanes)";</line>
<line>if index_align&lt;2&gt; != '0' then UNDEFINED;</line>
<line>if index_align&lt;1:0&gt; != '00' &amp;&amp; index_align&lt;1:0&gt; != '11' then UNDEFINED;</line>
<line>ebytes = 4;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3&gt;);</line>
<line>alignment = if index_align&lt;1:0&gt; == '00' then 1 else 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="6" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD1_1/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_1_T1_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_1_T1_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_1_T1_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_1/T1A1_A.txt" mylink="aarch32.instrs.VLD1_1.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD1 (single element to all lanes)";</line>
<line>if index_align&lt;0&gt; != '0' then UNDEFINED;</line>
<line>ebytes = 1;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:1&gt;);  alignment = 1;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="6" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD1_1/T2A2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_1_T2_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_1_T2_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_1_T2_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_1/T2A2_A.txt" mylink="aarch32.instrs.VLD1_1.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD1 (single element to all lanes)";</line>
<line>if index_align&lt;1&gt; != '0' then UNDEFINED;</line>
<line>ebytes = 2;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:2&gt;);</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T3" oneof="6" id="iclass_t3" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD1_1/T3A3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_1_T3_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_1_T3_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_1_T3_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_1/T3A3_A.txt" mylink="aarch32.instrs.VLD1_1.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD1 (single element to all lanes)";</line>
<line>if index_align&lt;2&gt; != '0' then UNDEFINED;</line>
<line>if index_align&lt;1:0&gt; != '00' &amp;&amp; index_align&lt;1:0&gt; != '11' then UNDEFINED;</line>
<line>ebytes = 4;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3&gt;);</line>
<line>alignment = if index_align&lt;1:0&gt; == '00' then 1 else 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VLD1_1_A1_nowb, VLD1_1_A2_nowb, VLD1_1_A3_nowb" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1, A2 and A3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_1_T1_nowb, VLD1_1_T2_nowb, VLD1_1_T3_nowb" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1, T2 and T3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_1_A1_nowb, VLD1_1_A2_nowb, VLD1_1_A3_nowb, VLD1_1_T1_nowb, VLD1_1_T2_nowb, VLD1_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_1_A1_nowb, VLD1_1_A2_nowb, VLD1_1_A3_nowb, VLD1_1_T1_nowb, VLD1_1_T2_nowb, VLD1_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data size, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VLD1_1_A1_nowb, VLD1_1_A2_nowb, VLD1_1_A3_nowb, VLD1_1_T1_nowb, VLD1_1_T2_nowb, VLD1_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is a list containing the single 64-bit name of the SIMD&amp;FP register holding the element.</para>
          <para>The list must be <syntax>{ &lt;Dd&gt;[&lt;index&gt;] }</syntax>.</para>
          <para>The register <syntax>&lt;Dd&gt;</syntax> is encoded in the "D:Vd" field.</para>
          <para>The permitted values and encoding of <syntax>&lt;index&gt;</syntax> depend on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 8</param><content><syntax>&lt;index&gt;</syntax> is in the range 0 to 7, encoded in the "index_align&lt;3:1&gt;" field.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content><syntax>&lt;index&gt;</syntax> is in the range 0 to 3, encoded in the "index_align&lt;3:2&gt;" field.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content><syntax>&lt;index&gt;</syntax> is 0 or 1, encoded in the "index_align&lt;3&gt;" field.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_1_A1_nowb, VLD1_1_A2_nowb, VLD1_1_A3_nowb, VLD1_1_T1_nowb, VLD1_1_T2_nowb, VLD1_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_1_A1_nowb, VLD1_1_A2_nowb, VLD1_1_A3_nowb, VLD1_1_T1_nowb, VLD1_1_T2_nowb, VLD1_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_align">&lt;align&gt;</symbol>
      <account encodedin="index_align&lt;0&gt;">
        <intro>
          <para>When <syntax>&lt;size&gt;</syntax> == 8, <syntax>&lt;align&gt;</syntax> must be omitted, otherwise it is the optional alignment.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is omitted, the standard alignment is used, see <xref linkend="Chdijihg">Unaligned data access</xref>, and the encoding depends on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 8</param><content>Encoded in the "index_align&lt;0&gt;" field as <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content>Encoded in the "index_align&lt;1:0&gt;" field as <binarynumber>0b00</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content>Encoded in the "index_align&lt;2:0&gt;" field as <binarynumber>0b000</binarynumber>.</content>
            </listitem>
          </list>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is present, the permitted values and encoding depend on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content><syntax>&lt;align&gt;</syntax> is 16, meaning 16-bit alignment, encoded in the "index_align&lt;1:0&gt;" field as <binarynumber>0b01</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content><syntax>&lt;align&gt;</syntax> is 32, meaning 32-bit alignment, encoded in the "index_align&lt;2:0&gt;" field as <binarynumber>0b011</binarynumber>.</content>
            </listitem>
          </list>
          <para><value>:</value> is the preferred separator before the <syntax>&lt;align&gt;</syntax> value, but the alignment can be specified as <value>@&lt;align&gt;</value>, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_1_A1_postr, VLD1_1_A2_postr, VLD1_1_A3_postr, VLD1_1_T1_postr, VLD1_1_T2_postr, VLD1_1_T3_postr" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VLD1_1/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line></line>
<line>    boolean nontemporal = FALSE;</line>
<line>    boolean tagchecked  = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, nontemporal, tagchecked);</line>
<line>    if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment) then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d],index,8*ebytes] = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,ebytes];</line>
<line>    if wback then</line>
<line>        if register_index then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + ebytes;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vld1_a.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VLD1_a" title="VLD1 (single element to all lanes) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VLD1" />
  </docvars>
  <heading>VLD1 (single element to all lanes)</heading>
  <desc>
    <brief>
      <para>Load single 1-element structure and replicate to all lanes of one register</para>
    </brief>
    <authored>
      <para>Load single 1-element structure and replicate to all lanes of one register loads one element from memory into every element of one or two vectors. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGGFBBG">VLD1 (single element to all lanes)</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For more information about the variants of this instruction, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD1_a/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" name="T" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="a" usename="1">
          <c></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_a_A1_nowb" oneofinclass="3" oneof="6" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;a&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_a_A1_posti" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;a&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_a_A1_postr" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;a&quot;)">&lt;align&gt;</a><text>}</text><text>],</text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_a/T1A1_A.txt" mylink="aarch32.instrs.VLD1_a.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' || (size == '00' &amp;&amp; a == '1') then UNDEFINED;</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  regs = if T == '0' then 1 else 2;</line>
<line>alignment = if a == '0' then 1 else ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d+regs &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d+regs &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD1_a/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" name="T" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="a" usename="1">
          <c></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_a_T1_nowb" oneofinclass="3" oneof="6" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;a&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_a_T1_posti" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;a&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_a_T1_postr" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;a&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_a/T1A1_A.txt" mylink="aarch32.instrs.VLD1_a.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' || (size == '00' &amp;&amp; a == '1') then UNDEFINED;</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  regs = if T == '0' then 1 else 2;</line>
<line>alignment = if a == '0' then 1 else ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d+regs &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d+regs &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VLD1_a_A1_nowb" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_a_T1_nowb" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_a_A1_nowb, VLD1_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_a_A1_nowb, VLD1_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data size, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VLD1_a_A1_nowb, VLD1_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="T">
        <intro>
          <para>Is a list containing the 64-bit names of the SIMD&amp;FP registers.</para>
          <para>The list must be one of:</para>
          <list type="param">
            <listitem>
              <param><syntax>{ &lt;Dd&gt;[] }</syntax></param><content>Encoded in the "T" field as <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;[], &lt;Dd+1&gt;[] }</syntax></param><content>Encoded in the "T" field as <binarynumber>1</binarynumber>.</content>
            </listitem>
          </list>
          <para>The register <syntax>&lt;Dd&gt;</syntax> is encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_a_A1_nowb, VLD1_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_a_A1_nowb, VLD1_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_align">&lt;align&gt;</symbol>
      <account encodedin="a">
        <intro>
          <para>When <syntax>&lt;size&gt;</syntax> == 8, <syntax>&lt;align&gt;</syntax> must be omitted, otherwise it is the optional alignment.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is omitted, the standard alignment is used, see <xref linkend="Chdijihg">Unaligned data access</xref>, and is encoded in the "a" field as <binarynumber>0</binarynumber>.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is present, the permitted values and encoding depend on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content><syntax>&lt;align&gt;</syntax> is 16, meaning 16-bit alignment, encoded in the "a" field as <binarynumber>1</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content><syntax>&lt;align&gt;</syntax> is 32, meaning 32-bit alignment, encoded in the "a" field as <binarynumber>1</binarynumber>.</content>
            </listitem>
          </list>
          <para><value>:</value> is the preferred separator before the <syntax>&lt;align&gt;</syntax> value, but the alignment can be specified as <value>@&lt;align&gt;</value>, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_a_A1_postr, VLD1_a_T1_postr" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VLD1_a/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line></line>
<line>    boolean nontemporal = FALSE;</line>
<line>    boolean tagchecked  = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, nontemporal, tagchecked);</line>
<line>    if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment) then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    constant integer esize = 8 * ebytes;</line>
<line>    bits(esize) element = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,ebytes];</line>
<line>    bits(64) replicated_element = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, 64 DIV esize);</line>
<line>    for r = 0 to regs-1</line>
<line>        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = replicated_element;</line>
<line>    if wback then</line>
<line>        if register_index then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + ebytes;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vld1_m.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VLD1_m" title="VLD1 (multiple single elements) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VLD1" />
  </docvars>
  <heading>VLD1 (multiple single elements)</heading>
  <desc>
    <brief>
      <para>Load multiple single 1-element structures to one, two, three, or four registers</para>
    </brief>
    <authored>
      <para>Load multiple single 1-element structures to one, two, three, or four registers loads elements from memory into one, two, three, or four registers, without de-interleaving. Every element of each register is loaded. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGBIHAI">VLD1 (multiple single elements)</xref>.</para>
      <para>Related encodings: See <xref linkend="T32.encoding_index.vldst">Advanced SIMD element or structure load/store</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimdls">Advanced SIMD element or structure load/store</xref> for the A32 instruction set.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For more information about the variants of this instruction, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="8">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>, </txt>
      <a href="#iclass_a2">A2</a>
      <txt>, </txt>
      <a href="#iclass_a3">A3</a>
      <txt> and </txt>
      <a href="#iclass_a4">A4</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt>, </txt>
      <a href="#iclass_t3">T3</a>
      <txt> and </txt>
      <a href="#iclass_t4">T4</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="8" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD1_m/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_m_A1_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_A1_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_A1_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_m/T1A1_A.txt" mylink="aarch32.instrs.VLD1_m.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>regs = 1;  if align&lt;1&gt; == '1' then UNDEFINED;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="8" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD1_m/T2A2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_m_A2_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_A2_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_A2_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_m/T2A2_A.txt" mylink="aarch32.instrs.VLD1_m.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>regs = 2;  if align == '11' then UNDEFINED;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d+regs &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d+regs &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A3" oneof="8" id="iclass_a3" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD1_m/T3A3_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_m_A3_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_A3_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_A3_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_m/T3A3_A.txt" mylink="aarch32.instrs.VLD1_m.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>regs = 3;  if align&lt;1&gt; == '1' then UNDEFINED;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d+regs &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d+regs &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A4" oneof="8" id="iclass_a4" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A4" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD1_m/T4A4_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_m_A4_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A4" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_A4_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A4" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_A4_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A4" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_m/T4A4_A.txt" mylink="aarch32.instrs.VLD1_m.T4A4_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>regs = 4;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d+regs &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A4" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d+regs &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="8" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD1_m/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_m_T1_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_T1_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_T1_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_m/T1A1_A.txt" mylink="aarch32.instrs.VLD1_m.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>regs = 1;  if align&lt;1&gt; == '1' then UNDEFINED;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="8" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD1_m/T2A2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_m_T2_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_T2_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_T2_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_m/T2A2_A.txt" mylink="aarch32.instrs.VLD1_m.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>regs = 2;  if align == '11' then UNDEFINED;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d+regs &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d+regs &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T3" oneof="8" id="iclass_t3" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD1_m/T3A3_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_m_T3_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_T3_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_T3_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_m/T3A3_A.txt" mylink="aarch32.instrs.VLD1_m.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>regs = 3;  if align&lt;1&gt; == '1' then UNDEFINED;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d+regs &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d+regs &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T4" oneof="8" id="iclass_t4" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T4" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD1_m/T4A4_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_m_T4_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_T4_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_T4_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_m/T4A4_A.txt" mylink="aarch32.instrs.VLD1_m.T4A4_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>regs = 4;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d+regs &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T4" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d+regs &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VLD1_m_A1_nowb, VLD1_m_A2_nowb, VLD1_m_A3_nowb, VLD1_m_A4_nowb" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1, A2, A3 and A4: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_m_T1_nowb, VLD1_m_T2_nowb, VLD1_m_T3_nowb, VLD1_m_T4_nowb" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1, T2, T3 and T4: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_m_A1_nowb, VLD1_m_A2_nowb, VLD1_m_A3_nowb, VLD1_m_A4_nowb, VLD1_m_T1_nowb, VLD1_m_T2_nowb, VLD1_m_T3_nowb, VLD1_m_T4_nowb" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_m_A1_nowb, VLD1_m_A2_nowb, VLD1_m_A3_nowb, VLD1_m_A4_nowb, VLD1_m_T1_nowb, VLD1_m_T2_nowb, VLD1_m_T3_nowb, VLD1_m_T4_nowb" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data size, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VLD1_m_A1_nowb, VLD1_m_A2_nowb, VLD1_m_A3_nowb, VLD1_m_A4_nowb, VLD1_m_T1_nowb, VLD1_m_T2_nowb, VLD1_m_T3_nowb, VLD1_m_T4_nowb" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is a list containing the 64-bit names of the SIMD&amp;FP registers.</para>
          <para>The list must be one of:</para>
          <list type="param">
            <listitem>
              <param><syntax>{ &lt;Dd&gt; }</syntax></param><content>Single register. Selects the A1 and T1 encodings of the instruction.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+1&gt; }</syntax></param><content>Two single-spaced registers. Selects the A2 and T2 encodings of the instruction.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+1&gt;, &lt;Dd+2&gt; }</syntax></param><content>Three single-spaced registers. Selects the A3 and T3 encodings of the instruction.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+1&gt;, &lt;Dd+2&gt;, &lt;Dd+3&gt; }</syntax></param><content>Four single-spaced registers. Selects the A4 and T4 encodings of the instruction.</content>
            </listitem>
          </list>
          <para>The register <syntax>&lt;Dd&gt;</syntax> is encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_m_A1_nowb, VLD1_m_A2_nowb, VLD1_m_A3_nowb, VLD1_m_A4_nowb, VLD1_m_T1_nowb, VLD1_m_T2_nowb, VLD1_m_T3_nowb, VLD1_m_T4_nowb" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_m_A1_nowb, VLD1_m_A2_nowb, VLD1_m_A3_nowb, VLD1_m_A4_nowb, VLD1_m_T1_nowb, VLD1_m_T2_nowb, VLD1_m_T3_nowb, VLD1_m_T4_nowb" symboldefcount="1">
      <symbol link="sa_align">&lt;align&gt;</symbol>
      <account encodedin="align">
        <intro>
          <para>Is the optional alignment.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is omitted, the standard alignment is used, see <xref linkend="Chdijihg">Unaligned data access</xref>, and is encoded in the "align" field as <binarynumber>0b00</binarynumber>.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is present, the permitted values are:</para>
          <list type="param">
            <listitem>
              <param>64</param><content>64-bit alignment, encoded in the "align" field as <binarynumber>0b01</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>128</param><content>128-bit alignment, encoded in the "align" field as <binarynumber>0b10</binarynumber>. Available only if <syntax>&lt;list&gt;</syntax> contains two or four registers.</content>
            </listitem>
            <listitem>
              <param>256</param><content>256-bit alignment, encoded in the "align" field as <binarynumber>0b11</binarynumber>. Available only if <syntax>&lt;list&gt;</syntax> contains four registers.</content>
            </listitem>
          </list>
          <para><value>:</value> is the preferred separator before the <syntax>&lt;align&gt;</syntax> value, but the alignment can be specified as <value>@&lt;align&gt;</value>, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_m_A1_postr, VLD1_m_A2_postr, VLD1_m_A3_postr, VLD1_m_A4_postr, VLD1_m_T1_postr, VLD1_m_T2_postr, VLD1_m_T3_postr, VLD1_m_T4_postr" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VLD1_m/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line></line>
<line>    boolean nontemporal = FALSE;</line>
<line>    boolean tagchecked  = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, nontemporal, tagchecked);</line>
<line>    if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment) then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            bits(ebytes*8) data;</line>
<line>            if ebytes != 8 then</line>
<line>                data = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,ebytes];</line>
<line>            else</line>
<line>                if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, ebytes) &amp;&amp; <a link="impl-shared.AlignmentEnforced.0" file="shared_pseudocode.xml" hover="function: boolean AlignmentEnforced()">AlignmentEnforced</a>() then</line>
<line>                    <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>                if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_ASIMD" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_ASIMD</a>) then</line>
<line>                    data&lt;31:0&gt; = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+4,4];</line>
<line>                    data&lt;63:32&gt; = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,4];</line>
<line>                else</line>
<line>                    data&lt;31:0&gt; = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,4];</line>
<line>                    data&lt;63:32&gt; = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+4,4];</line>
<line></line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,8*ebytes] = data;</line>
<line>            address = address + ebytes;</line>
<line>    if wback then</line>
<line>        if register_index then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 8*regs;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vld2_1.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VLD2_1" title="VLD2 (single 2-element structure to one lane) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VLD2" />
  </docvars>
  <heading>VLD2 (single 2-element structure to one lane)</heading>
  <desc>
    <brief>
      <para>Load single 2-element structure to one lane of two registers</para>
    </brief>
    <authored>
      <para>Load single 2-element structure to one lane of two registers loads one 2-element structure from memory into corresponding elements of two registers. Elements of the registers that are not loaded are unchanged. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGEDHDB">VLD2 (single 2-element structure to one lane)</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For more information about the variants of this instruction, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="6">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>, </txt>
      <a href="#iclass_a2">A2</a>
      <txt> and </txt>
      <a href="#iclass_a3">A3</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="6" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD2" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD2_1/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD2_1_A1_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_1_A1_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_1_A1_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD2_1/T1A1_A.txt" mylink="aarch32.instrs.VLD2_1.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD2 (single 2-element structure to all lanes)";</line>
<line>ebytes = 1;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:1&gt;);  inc = 1;</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d2 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d2 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A2" oneof="6" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD2" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD2_1/T2A2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD2_1_A2_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_1_A2_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_1_A2_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD2_1/T2A2_A.txt" mylink="aarch32.instrs.VLD2_1.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD2 (single 2-element structure to all lanes)";</line>
<line>ebytes = 2;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:2&gt;);</line>
<line>inc = if index_align&lt;1&gt; == '0' then 1 else 2;</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d2 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d2 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A3" oneof="6" id="iclass_a3" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD2" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD2_1/T3A3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD2_1_A3_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_1_A3_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_1_A3_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD2_1/T3A3_A.txt" mylink="aarch32.instrs.VLD2_1.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD2 (single 2-element structure to all lanes)";</line>
<line>if index_align&lt;1&gt; != '0' then UNDEFINED;</line>
<line>ebytes = 4;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3&gt;);</line>
<line>inc = if index_align&lt;2&gt; == '0' then 1 else 2;</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 8;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d2 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d2 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="6" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD2" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD2_1/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD2_1_T1_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_1_T1_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_1_T1_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD2_1/T1A1_A.txt" mylink="aarch32.instrs.VLD2_1.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD2 (single 2-element structure to all lanes)";</line>
<line>ebytes = 1;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:1&gt;);  inc = 1;</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d2 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d2 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="6" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD2" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD2_1/T2A2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD2_1_T2_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_1_T2_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_1_T2_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD2_1/T2A2_A.txt" mylink="aarch32.instrs.VLD2_1.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD2 (single 2-element structure to all lanes)";</line>
<line>ebytes = 2;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:2&gt;);</line>
<line>inc = if index_align&lt;1&gt; == '0' then 1 else 2;</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d2 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d2 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T3" oneof="6" id="iclass_t3" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD2" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD2_1/T3A3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD2_1_T3_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_1_T3_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_1_T3_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD2_1/T3A3_A.txt" mylink="aarch32.instrs.VLD2_1.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD2 (single 2-element structure to all lanes)";</line>
<line>if index_align&lt;1&gt; != '0' then UNDEFINED;</line>
<line>ebytes = 4;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3&gt;);</line>
<line>inc = if index_align&lt;2&gt; == '0' then 1 else 2;</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 8;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d2 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d2 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VLD2_1_A1_nowb, VLD2_1_A2_nowb, VLD2_1_A3_nowb" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1, A2 and A3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD2_1_T1_nowb, VLD2_1_T2_nowb, VLD2_1_T3_nowb" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1, T2 and T3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD2_1_A1_nowb, VLD2_1_A2_nowb, VLD2_1_A3_nowb, VLD2_1_T1_nowb, VLD2_1_T2_nowb, VLD2_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD2_1_A1_nowb, VLD2_1_A2_nowb, VLD2_1_A3_nowb, VLD2_1_T1_nowb, VLD2_1_T2_nowb, VLD2_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data size, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VLD2_1_A1_nowb, VLD2_1_A2_nowb, VLD2_1_A3_nowb, VLD2_1_T1_nowb, VLD2_1_T2_nowb, VLD2_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="index_align&lt;1&gt;">
        <intro>
          <para>Is a list containing the 64-bit names of the two SIMD&amp;FP registers holding the element.</para>
          <para>The list must be one of:</para>
          <list type="param">
            <listitem>
              <param><syntax>{ &lt;Dd&gt;[&lt;index&gt;], &lt;Dd+1&gt;[&lt;index&gt;] }</syntax></param><content>Single-spaced registers, encoded as "spacing" = <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;[&lt;index&gt;], &lt;Dd+2&gt;[&lt;index&gt;] }</syntax></param><content>Double-spaced registers, encoded as "spacing" = <binarynumber>1</binarynumber>. Not permitted when <syntax>&lt;size&gt;</syntax> == 8.</content>
            </listitem>
          </list>
          <para>The encoding of "spacing" depends on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content>"spacing" is encoded in the "index_align&lt;1&gt;" field.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content>"spacing" is encoded in the "index_align&lt;2&gt;" field.</content>
            </listitem>
          </list>
          <para>The register <syntax>&lt;Dd&gt;</syntax> is encoded in the "D:Vd" field.</para>
          <para>The permitted values and encoding of <syntax>&lt;index&gt;</syntax> depend on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 8</param><content><syntax>&lt;index&gt;</syntax> is in the range 0 to 7, encoded in the "index_align&lt;3:1&gt;" field.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content><syntax>&lt;index&gt;</syntax> is in the range 0 to 3, encoded in the "index_align&lt;3:2&gt;" field.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content><syntax>&lt;index&gt;</syntax> is 0 or 1, encoded in the "index_align&lt;3&gt;" field.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD2_1_A1_nowb, VLD2_1_A2_nowb, VLD2_1_A3_nowb, VLD2_1_T1_nowb, VLD2_1_T2_nowb, VLD2_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD2_1_A1_nowb, VLD2_1_A2_nowb, VLD2_1_A3_nowb, VLD2_1_T1_nowb, VLD2_1_T2_nowb, VLD2_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_align">&lt;align&gt;</symbol>
      <account encodedin="index_align&lt;0&gt;">
        <intro>
          <para>Is the optional alignment.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is omitted, the standard alignment is used, see <xref linkend="Chdijihg">Unaligned data access</xref>, and the encoding depends on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 8</param><content>Encoded in the "index_align&lt;0&gt;" field as <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content>Encoded in the "index_align&lt;0&gt;" field as <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content>Encoded in the "index_align&lt;1:0&gt;" field as <binarynumber>0b00</binarynumber>.</content>
            </listitem>
          </list>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is present, the permitted values and encoding depend on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 8</param><content><syntax>&lt;align&gt;</syntax> is 16, meaning 16-bit alignment, encoded in the "index_align&lt;0&gt;" field as <binarynumber>1</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content><syntax>&lt;align&gt;</syntax> is 32, meaning 32-bit alignment, encoded in the "index_align&lt;0&gt;" field as <binarynumber>1</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content><syntax>&lt;align&gt;</syntax> is 64, meaning 64-bit alignment, encoded in the "index_align&lt;1:0&gt;" field as <binarynumber>0b01</binarynumber>.</content>
            </listitem>
          </list>
          <para><value>:</value> is the preferred separator before the <syntax>&lt;align&gt;</syntax> value, but the alignment can be specified as <value>@&lt;align&gt;</value>, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD2_1_A1_postr, VLD2_1_A2_postr, VLD2_1_A3_postr, VLD2_1_T1_postr, VLD2_1_T2_postr, VLD2_1_T3_postr" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VLD2_1/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line></line>
<line>    boolean nontemporal = FALSE;</line>
<line>    boolean tagchecked  = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, nontemporal, tagchecked);</line>
<line>    if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment) then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d], index,8*ebytes] = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,ebytes];</line>
<line>    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d2],index,8*ebytes] = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+ebytes,ebytes];</line>
<line>    if wback then</line>
<line>        if register_index then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 2*ebytes;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vld2_a.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VLD2_a" title="VLD2 (single 2-element structure to all lanes) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VLD2" />
  </docvars>
  <heading>VLD2 (single 2-element structure to all lanes)</heading>
  <desc>
    <brief>
      <para>Load single 2-element structure and replicate to all lanes of two registers</para>
    </brief>
    <authored>
      <para>Load single 2-element structure and replicate to all lanes of two registers loads one 2-element structure from memory into all lanes of two registers. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGEGFCF">VLD2 (single 2-element structure to all lanes)</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For more information about the variants of this instruction, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD2" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD2_a/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" name="T" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="a" usename="1">
          <c></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD2_a_A1_nowb" oneofinclass="3" oneof="6" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;a&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_a_A1_posti" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;a&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_a_A1_postr" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;a&quot;)">&lt;align&gt;</a><text>}</text><text>],</text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD2_a/T1A1_A.txt" mylink="aarch32.instrs.VLD2_a.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);</line>
<line>alignment = if a == '0' then 1 else 2*ebytes;</line>
<line>inc = if T == '0' then 1 else 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d2 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d2 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD2" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD2_a/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" name="T" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="a" usename="1">
          <c></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD2_a_T1_nowb" oneofinclass="3" oneof="6" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;a&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_a_T1_posti" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;a&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_a_T1_postr" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;a&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD2_a/T1A1_A.txt" mylink="aarch32.instrs.VLD2_a.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);</line>
<line>alignment = if a == '0' then 1 else 2*ebytes;</line>
<line>inc = if T == '0' then 1 else 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d2 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d2 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VLD2_a_A1_nowb" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD2_a_T1_nowb" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD2_a_A1_nowb, VLD2_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD2_a_A1_nowb, VLD2_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data size, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VLD2_a_A1_nowb, VLD2_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="T">
        <intro>
          <para>Is a list containing the 64-bit names of two SIMD&amp;FP registers.</para>
          <para>The list must be one of:</para>
          <list type="param">
            <listitem>
              <param><syntax>{ &lt;Dd&gt;[], &lt;Dd+1&gt;[] }</syntax></param><content>Single-spaced registers, encoded in the "T" field as <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;[], &lt;Dd+2&gt;[] }</syntax></param><content>Double-spaced registers, encoded in the "T" field as <binarynumber>1</binarynumber>.</content>
            </listitem>
          </list>
          <para>The register <syntax>&lt;Dd&gt;</syntax> is encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD2_a_A1_nowb, VLD2_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD2_a_A1_nowb, VLD2_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_align">&lt;align&gt;</symbol>
      <account encodedin="a">
        <intro>
          <para>Is the optional alignment.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is omitted, the standard alignment is used, see <xref linkend="Chdijihg">Unaligned data access</xref>, and is encoded in the "a" field as <binarynumber>0</binarynumber>.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is present, the permitted values and encoding depend on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 8</param><content><syntax>&lt;align&gt;</syntax> is 16, meaning 16-bit alignment, encoded in the "a" field as <binarynumber>1</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content><syntax>&lt;align&gt;</syntax> is 32, meaning 32-bit alignment, encoded in the "a" field as <binarynumber>1</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content><syntax>&lt;align&gt;</syntax> is 64, meaning 64-bit alignment, encoded in the "a" field as <binarynumber>1</binarynumber>.</content>
            </listitem>
          </list>
          <para><value>:</value> is the preferred separator before the <syntax>&lt;align&gt;</syntax> value, but the alignment can be specified as <value>@&lt;align&gt;</value>, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD2_a_A1_postr, VLD2_a_T1_postr" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VLD2_a/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line></line>
<line>    boolean nontemporal = FALSE;</line>
<line>    boolean tagchecked  = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, nontemporal, tagchecked);</line>
<line>    if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment) then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    constant integer esize = 8 * ebytes;</line>
<line>    bits(esize) element1 = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address, ebytes];</line>
<line>    bits(esize) element2 = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+ebytes, ebytes];</line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element1, 64 DIV esize);</line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d2] = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element2, 64 DIV esize);</line>
<line></line>
<line>    if wback then</line>
<line>        if register_index then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 2*ebytes;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vld2_m.xml">
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<instructionsection id="VLD2_m" title="VLD2 (multiple 2-element structures) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VLD2" />
  </docvars>
  <heading>VLD2 (multiple 2-element structures)</heading>
  <desc>
    <brief>
      <para>Load multiple 2-element structures to two or four registers</para>
    </brief>
    <authored>
      <para>Load multiple 2-element structures to two or four registers loads multiple 2-element structures from memory into two or four registers, with de-interleaving. For more information, see <xref linkend="BABHJAGF">Element and structure load/store instructions</xref>. Every element of each register is loaded. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGIJCEE">VLD2 (multiple 2-element structures)</xref>.</para>
      <para>Related encodings: See <xref linkend="T32.encoding_index.vldst">Advanced SIMD element or structure load/store</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimdls">Advanced SIMD element or structure load/store</xref> for the A32 instruction set.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For more information about the variants of this instruction, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD2" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD2_m/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" usename="1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>x</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD2_m_A1_nowb" oneofinclass="3" oneof="12" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_m_A1_posti" oneofinclass="3" oneof="12" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_m_A1_postr" oneofinclass="3" oneof="12" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD2_m/T1A1_A.txt" mylink="aarch32.instrs.VLD2_m.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>pairs = 1;  if align == '11' then UNDEFINED;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>inc = if itype == '1001' then 2 else 1;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d2+pairs &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d2+pairs &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD2" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD2_m/T2A2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD2_m_A2_nowb" oneofinclass="3" oneof="12" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_m_A2_posti" oneofinclass="3" oneof="12" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_m_A2_postr" oneofinclass="3" oneof="12" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD2_m/T2A2_A.txt" mylink="aarch32.instrs.VLD2_m.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>pairs = 2;  inc = 2;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d2+pairs &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d2+pairs &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD2" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD2_m/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" usename="1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>x</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD2_m_T1_nowb" oneofinclass="3" oneof="12" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_m_T1_posti" oneofinclass="3" oneof="12" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_m_T1_postr" oneofinclass="3" oneof="12" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD2_m/T1A1_A.txt" mylink="aarch32.instrs.VLD2_m.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>pairs = 1;  if align == '11' then UNDEFINED;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>inc = if itype == '1001' then 2 else 1;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d2+pairs &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d2+pairs &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD2" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD2_m/T2A2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD2_m_T2_nowb" oneofinclass="3" oneof="12" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_m_T2_posti" oneofinclass="3" oneof="12" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD2_m_T2_postr" oneofinclass="3" oneof="12" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD2_m/T2A2_A.txt" mylink="aarch32.instrs.VLD2_m.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>pairs = 2;  inc = 2;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d2+pairs &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d2+pairs &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VLD2_m_A1_nowb, VLD2_m_A2_nowb" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1 and A2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD2_m_T1_nowb, VLD2_m_T2_nowb" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD2_m_A1_nowb, VLD2_m_A2_nowb, VLD2_m_T1_nowb, VLD2_m_T2_nowb" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD2_m_A1_nowb, VLD2_m_A2_nowb, VLD2_m_T1_nowb, VLD2_m_T2_nowb" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data size, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VLD2_m_A1_nowb, VLD2_m_A2_nowb, VLD2_m_T1_nowb, VLD2_m_T2_nowb" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="itype">
        <intro>
          <para>Is a list containing the 64-bit names of the SIMD&amp;FP registers.</para>
          <para>The list must be one of:</para>
          <list type="param">
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+1&gt; }</syntax></param><content>Two single-spaced registers. Selects the A1 and T1 encodings of the instruction, and encoded in the "itype" field as <binarynumber>0b1000</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+2&gt; }</syntax></param><content>Two double-spaced registers. Selects the A1 and T1 encodings of the instruction, and encoded in the "itype" field as <binarynumber>0b1001</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+1&gt;, &lt;Dd+2&gt;, &lt;Dd+3&gt; }</syntax></param><content>Three single-spaced registers. Selects the A2 and T2 encodings of the instruction.</content>
            </listitem>
          </list>
          <para>The register <syntax>&lt;Dd&gt;</syntax> is encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD2_m_A1_nowb, VLD2_m_A2_nowb, VLD2_m_T1_nowb, VLD2_m_T2_nowb" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD2_m_A1_nowb, VLD2_m_A2_nowb, VLD2_m_T1_nowb, VLD2_m_T2_nowb" symboldefcount="1">
      <symbol link="sa_align">&lt;align&gt;</symbol>
      <account encodedin="align">
        <intro>
          <para>Is the optional alignment.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is omitted, the standard alignment is used, see <xref linkend="Chdijihg">Unaligned data access</xref>, and is encoded in the "align" field as <binarynumber>0b00</binarynumber>.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is present, the permitted values are:</para>
          <list type="param">
            <listitem>
              <param>64</param><content>64-bit alignment, encoded in the "align" field as <binarynumber>0b01</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>128</param><content>128-bit alignment, encoded in the "align" field as <binarynumber>0b10</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>256</param><content>256-bit alignment, encoded in the "align" field as <binarynumber>0b11</binarynumber>. Available only if <syntax>&lt;list&gt;</syntax> contains four registers.</content>
            </listitem>
          </list>
          <para><value>:</value> is the preferred separator before the <syntax>&lt;align&gt;</syntax> value, but the alignment can be specified as <value>@&lt;align&gt;</value>, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD2_m_A1_postr, VLD2_m_A2_postr, VLD2_m_T1_postr, VLD2_m_T2_postr" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VLD2_m/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line></line>
<line>    boolean nontemporal = FALSE;</line>
<line>    boolean tagchecked  = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, nontemporal, tagchecked);</line>
<line>    if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment) then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    for r = 0 to pairs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r], e,8*ebytes] = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,ebytes];</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d2+r],e,8*ebytes] = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+ebytes,ebytes];</line>
<line>            address = address + 2*ebytes;</line>
<line>    if wback then</line>
<line>        if register_index then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 16*pairs;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vld3_1.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VLD3_1" title="VLD3 (single 3-element structure to one lane) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VLD3" />
  </docvars>
  <heading>VLD3 (single 3-element structure to one lane)</heading>
  <desc>
    <brief>
      <para>Load single 3-element structure to one lane of three registers</para>
    </brief>
    <authored>
      <para>Load single 3-element structure to one lane of three registers loads one 3-element structure from memory into corresponding elements of three registers. Elements of the registers that are not loaded are unchanged. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGBCJIB">VLD3 (single 3-element structure to one lane)</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For more information about the variants of this instruction, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Alignment</para>
      <para>Standard alignment rules apply, see <xref linkend="CHDIDCCI">Alignment support</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="6">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>, </txt>
      <a href="#iclass_a2">A2</a>
      <txt> and </txt>
      <a href="#iclass_a3">A3</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="6" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD3" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD3_1/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD3_1_A1_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_1_A1_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_1_A1_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD3_1/T1A1_A.txt" mylink="aarch32.instrs.VLD3_1.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD3 (single 3-element structure to all lanes)";</line>
<line>if index_align&lt;0&gt; != '0' then UNDEFINED;</line>
<line>ebytes = 1;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:1&gt;);  inc = 1;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d3 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d3 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A2" oneof="6" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD3" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD3_1/T2A2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD3_1_A2_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_1_A2_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_1_A2_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD3_1/T2A2_A.txt" mylink="aarch32.instrs.VLD3_1.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD3 (single 3-element structure to all lanes)";</line>
<line>if index_align&lt;0&gt; != '0' then UNDEFINED;</line>
<line>ebytes = 2;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:2&gt;);</line>
<line>inc = if index_align&lt;1&gt; == '0' then 1 else 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d3 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d3 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A3" oneof="6" id="iclass_a3" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD3" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD3_1/T3A3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD3_1_A3_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_1_A3_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_1_A3_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD3_1/T3A3_A.txt" mylink="aarch32.instrs.VLD3_1.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD3 (single 3-element structure to all lanes)";</line>
<line>if index_align&lt;1:0&gt; != '00' then UNDEFINED;</line>
<line>ebytes = 4;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3&gt;);</line>
<line>inc = if index_align&lt;2&gt; == '0' then 1 else 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d3 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d3 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="6" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD3" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD3_1/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD3_1_T1_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_1_T1_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_1_T1_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD3_1/T1A1_A.txt" mylink="aarch32.instrs.VLD3_1.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD3 (single 3-element structure to all lanes)";</line>
<line>if index_align&lt;0&gt; != '0' then UNDEFINED;</line>
<line>ebytes = 1;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:1&gt;);  inc = 1;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d3 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d3 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="6" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD3" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD3_1/T2A2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD3_1_T2_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_1_T2_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_1_T2_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD3_1/T2A2_A.txt" mylink="aarch32.instrs.VLD3_1.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD3 (single 3-element structure to all lanes)";</line>
<line>if index_align&lt;0&gt; != '0' then UNDEFINED;</line>
<line>ebytes = 2;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:2&gt;);</line>
<line>inc = if index_align&lt;1&gt; == '0' then 1 else 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d3 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d3 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T3" oneof="6" id="iclass_t3" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD3" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD3_1/T3A3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD3_1_T3_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_1_T3_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_1_T3_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD3_1/T3A3_A.txt" mylink="aarch32.instrs.VLD3_1.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD3 (single 3-element structure to all lanes)";</line>
<line>if index_align&lt;1:0&gt; != '00' then UNDEFINED;</line>
<line>ebytes = 4;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3&gt;);</line>
<line>inc = if index_align&lt;2&gt; == '0' then 1 else 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d3 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d3 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VLD3_1_A1_nowb, VLD3_1_A2_nowb, VLD3_1_A3_nowb" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1, A2 and A3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD3_1_T1_nowb, VLD3_1_T2_nowb, VLD3_1_T3_nowb" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1, T2 and T3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD3_1_A1_nowb, VLD3_1_A2_nowb, VLD3_1_A3_nowb, VLD3_1_T1_nowb, VLD3_1_T2_nowb, VLD3_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD3_1_A1_nowb, VLD3_1_A2_nowb, VLD3_1_A3_nowb, VLD3_1_T1_nowb, VLD3_1_T2_nowb, VLD3_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data size, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VLD3_1_A1_nowb, VLD3_1_A2_nowb, VLD3_1_A3_nowb, VLD3_1_T1_nowb, VLD3_1_T2_nowb, VLD3_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="index_align&lt;0&gt;">
        <intro>
          <para>Is a list containing the 64-bit names of the three SIMD&amp;FP registers holding the element.</para>
          <para>The list must be one of:</para>
          <list type="param">
            <listitem>
              <param><syntax>{ &lt;Dd&gt;[&lt;index&gt;], &lt;Dd+1&gt;[&lt;index&gt;], &lt;Dd+2&gt;[&lt;index&gt;] }</syntax></param><content>Single-spaced registers, encoded as "spacing" = <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;[&lt;index&gt;], &lt;Dd+2&gt;[&lt;index&gt;], &lt;Dd+4&gt;[&lt;index&gt;] }</syntax></param><content>Double-spaced registers, encoded as "spacing" = <binarynumber>1</binarynumber>. Not permitted when <syntax>&lt;size&gt;</syntax> == 8.</content>
            </listitem>
          </list>
          <para>The encoding of "spacing" depends on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 8</param><content>"spacing" is encoded in the "index_align&lt;0&gt;" field.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content>"spacing" is encoded in the "index_align&lt;1&gt;" field, and "index_align&lt;0&gt;" is set to <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content>"spacing" is encoded in the "index_align&lt;2&gt;" field, and "index_align&lt;1:0&gt;" is set to <binarynumber>0b00</binarynumber>.</content>
            </listitem>
          </list>
          <para>The register <syntax>&lt;Dd&gt;</syntax> is encoded in the "D:Vd" field.</para>
          <para>The permitted values and encoding of <syntax>&lt;index&gt;</syntax> depend on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 8</param><content><syntax>&lt;index&gt;</syntax> is in the range 0 to 7, encoded in the "index_align&lt;3:1&gt;" field.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content><syntax>&lt;index&gt;</syntax> is in the range 0 to 3, encoded in the "index_align&lt;3:2&gt;" field.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content><syntax>&lt;index&gt;</syntax> is 0 or 1, encoded in the "index_align&lt;3&gt;" field.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD3_1_A1_nowb, VLD3_1_A2_nowb, VLD3_1_A3_nowb, VLD3_1_T1_nowb, VLD3_1_T2_nowb, VLD3_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD3_1_A1_postr, VLD3_1_A2_postr, VLD3_1_A3_postr, VLD3_1_T1_postr, VLD3_1_T2_postr, VLD3_1_T3_postr" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VLD3_1/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d], index,8*ebytes] = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,ebytes];</line>
<line>    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d2],index,8*ebytes] = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+ebytes,ebytes];</line>
<line>    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d3],index,8*ebytes] = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+2*ebytes,ebytes];</line>
<line>    if wback then</line>
<line>        if register_index then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 3*ebytes;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vld3_a.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VLD3_a" title="VLD3 (single 3-element structure to all lanes) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VLD3" />
  </docvars>
  <heading>VLD3 (single 3-element structure to all lanes)</heading>
  <desc>
    <brief>
      <para>Load single 3-element structure and replicate to all lanes of three registers</para>
    </brief>
    <authored>
      <para>Load single 3-element structure and replicate to all lanes of three registers loads one 3-element structure from memory into all lanes of three registers. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGHGDDF">VLD3 (single 3-element structure to all lanes)</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For more information about the variants of this instruction, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Alignment</para>
      <para>Standard alignment rules apply, see <xref linkend="CHDIDCCI">Alignment support</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD3" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD3_a/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" name="T" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="a" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD3_a_A1_nowb" oneofinclass="3" oneof="6" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_a_A1_posti" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_a_A1_postr" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD3_a/T1A1_A.txt" mylink="aarch32.instrs.VLD3_a.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' || a == '1' then UNDEFINED;</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);</line>
<line>inc = if T == '0' then 1 else 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d3 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d3 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD3" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD3_a/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" name="T" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="a" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD3_a_T1_nowb" oneofinclass="3" oneof="6" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_a_T1_posti" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_a_T1_postr" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD3_a/T1A1_A.txt" mylink="aarch32.instrs.VLD3_a.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' || a == '1' then UNDEFINED;</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);</line>
<line>inc = if T == '0' then 1 else 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d3 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d3 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VLD3_a_A1_nowb" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD3_a_T1_nowb" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD3_a_A1_nowb, VLD3_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD3_a_A1_nowb, VLD3_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data size, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VLD3_a_A1_nowb, VLD3_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="T">
        <intro>
          <para>Is a list containing the 64-bit names of three SIMD&amp;FP registers.</para>
          <para>The list must be one of:</para>
          <list type="param">
            <listitem>
              <param><syntax>{ &lt;Dd&gt;[], &lt;Dd+1&gt;[], &lt;Dd+2&gt;[] }</syntax></param><content>Single-spaced registers, encoded in the "T" field as <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;[], &lt;Dd+2&gt;[], &lt;Dd+4&gt;[] }</syntax></param><content>Double-spaced registers, encoded in the "T" field as <binarynumber>1</binarynumber>.</content>
            </listitem>
          </list>
          <para>The register <syntax>&lt;Dd&gt;</syntax> is encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD3_a_A1_nowb, VLD3_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD3_a_A1_postr, VLD3_a_T1_postr" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VLD3_a/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    constant integer esize = ebytes * 8;</line>
<line>    bits(esize) element1 = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address, ebytes];</line>
<line>    bits(esize) element2 = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+ebytes,ebytes];</line>
<line>    bits(esize) element3 = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+2*ebytes,ebytes];</line>
<line></line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element1, 64 DIV esize);</line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d2] = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element2, 64 DIV esize);</line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d3] = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element3, 64 DIV esize);</line>
<line>    if wback then</line>
<line>        if register_index then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 3*ebytes;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vld3_m.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<instructionsection id="VLD3_m" title="VLD3 (multiple 3-element structures) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VLD3" />
  </docvars>
  <heading>VLD3 (multiple 3-element structures)</heading>
  <desc>
    <brief>
      <para>Load multiple 3-element structures to three registers</para>
    </brief>
    <authored>
      <para>Load multiple 3-element structures to three registers loads multiple 3-element structures from memory into three registers, with de-interleaving. For more information, see <xref linkend="BABHJAGF">Element and structure load/store instructions</xref>. Every element of each register is loaded. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGFGBAH">VLD3 (multiple 3-element structures)</xref>.</para>
      <para>Related encodings: See <xref linkend="T32.encoding_index.vldst">Advanced SIMD element or structure load/store</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimdls">Advanced SIMD element or structure load/store</xref> for the A32 instruction set.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For more information about <syntax>&lt;Rn&gt;</syntax>, <syntax>!</syntax>, and <syntax>&lt;Rm&gt;</syntax>, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD3" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD3_m/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" usename="1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>x</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD3_m_A1_nowb" oneofinclass="3" oneof="6" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_m_A1_posti" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_m_A1_postr" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD3_m/T1A1_A.txt" mylink="aarch32.instrs.VLD3_m.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>integer inc;</line>
<line>case itype of</line>
<line>    when '0100'</line>
<line>        inc = 1;</line>
<line>    when '0101'</line>
<line>        inc = 2;</line>
<line>    otherwise</line>
<line>        SEE "Related encodings";</line>
<line>if size == '11' || align&lt;1&gt; == '1' then UNDEFINED;</line>
<line>alignment = if align&lt;0&gt; == '0' then 1 else 8;</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d3 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d3 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD3" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD3_m/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" usename="1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>x</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD3_m_T1_nowb" oneofinclass="3" oneof="6" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_m_T1_posti" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_m_T1_postr" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD3_m/T1A1_A.txt" mylink="aarch32.instrs.VLD3_m.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>integer inc;</line>
<line>case itype of</line>
<line>    when '0100'</line>
<line>        inc = 1;</line>
<line>    when '0101'</line>
<line>        inc = 2;</line>
<line>    otherwise</line>
<line>        SEE "Related encodings";</line>
<line>if size == '11' || align&lt;1&gt; == '1' then UNDEFINED;</line>
<line>alignment = if align&lt;0&gt; == '0' then 1 else 8;</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d3 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d3 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VLD3_m_A1_nowb" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD3_m_T1_nowb" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD3_m_A1_nowb, VLD3_m_T1_nowb" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD3_m_A1_nowb, VLD3_m_T1_nowb" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data size, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VLD3_m_A1_nowb, VLD3_m_T1_nowb" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="itype">
        <intro>
          <para>Is a list containing the 64-bit names of the SIMD&amp;FP registers.</para>
          <para>The list must be one of:</para>
          <list type="param">
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+1&gt;, &lt;Dd+2&gt; }</syntax></param><content>Single-spaced registers, encoded in the "itype" field as <binarynumber>0b0100</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+2&gt;, &lt;Dd+4&gt; }</syntax></param><content>Double-spaced registers, encoded in the "itype" field as <binarynumber>0b0101</binarynumber>.</content>
            </listitem>
          </list>
          <para>The register <syntax>&lt;Dd&gt;</syntax> is encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD3_m_A1_nowb, VLD3_m_T1_nowb" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD3_m_A1_nowb, VLD3_m_T1_nowb" symboldefcount="1">
      <symbol link="sa_align">&lt;align&gt;</symbol>
      <account encodedin="align">
        <intro>
          <para>Is the optional alignment.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is omitted, the standard alignment is used, see <xref linkend="Chdijihg">Unaligned data access</xref>, and is encoded in the "align" field as <binarynumber>0b00</binarynumber>.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is present, the only permitted values is 64, meaning 64-bit alignment, encoded in the "align" field as <binarynumber>0b01</binarynumber>.</para>
          <para><value>:</value> is the preferred separator before the <syntax>&lt;align&gt;</syntax> value, but the alignment can be specified as <value>@&lt;align&gt;</value>, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD3_m_A1_postr, VLD3_m_T1_postr" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VLD3_m/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line></line>
<line>    boolean nontemporal = FALSE;</line>
<line>    boolean tagchecked  = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, nontemporal, tagchecked);</line>
<line>    if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment) then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    for e = 0 to elements-1</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d], e,8*ebytes] = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,ebytes];</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d2],e,8*ebytes] = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+ebytes,ebytes];</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d3],e,8*ebytes] = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+2*ebytes,ebytes];</line>
<line>        address = address + 3*ebytes;</line>
<line>    if wback then</line>
<line>        if register_index then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 24;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vld4_1.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VLD4_1" title="VLD4 (single 4-element structure to one lane) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VLD4" />
  </docvars>
  <heading>VLD4 (single 4-element structure to one lane)</heading>
  <desc>
    <brief>
      <para>Load single 4-element structure to one lane of four registers</para>
    </brief>
    <authored>
      <para>Load single 4-element structure to one lane of four registers loads one 4-element structure from memory into corresponding elements of four registers. Elements of the registers that are not loaded are unchanged. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGJAEJA">VLD4 (single 4-element structure to one lane)</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For more information about the variants of this instruction, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="6">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>, </txt>
      <a href="#iclass_a2">A2</a>
      <txt> and </txt>
      <a href="#iclass_a3">A3</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="6" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD4" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD4_1/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD4_1_A1_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD4_1_A1_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD4_1_A1_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD4_1/T1A1_A.txt" mylink="aarch32.instrs.VLD4_1.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD4 (single 4-element structure to all lanes)";</line>
<line>ebytes = 1;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:1&gt;);  inc = 1;</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  d4 = d3 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d4 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d4 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A2" oneof="6" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD4" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD4_1/T2A2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD4_1_A2_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD4_1_A2_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD4_1_A2_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD4_1/T2A2_A.txt" mylink="aarch32.instrs.VLD4_1.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD4 (single 4-element structure to all lanes)";</line>
<line>ebytes = 2;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:2&gt;);</line>
<line>inc = if index_align&lt;1&gt; == '0' then 1 else 2;</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 8;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  d4 = d3 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d4 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d4 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A3" oneof="6" id="iclass_a3" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD4" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD4_1/T3A3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD4_1_A3_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD4_1_A3_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD4_1_A3_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD4_1/T3A3_A.txt" mylink="aarch32.instrs.VLD4_1.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD4 (single 4-element structure to all lanes)";</line>
<line>if index_align&lt;1:0&gt; == '11' then UNDEFINED;</line>
<line>ebytes = 4;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3&gt;);</line>
<line>inc = if index_align&lt;2&gt; == '0' then 1 else 2;</line>
<line>alignment = if index_align&lt;1:0&gt; == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;1:0&gt;);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  d4 = d3 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d4 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d4 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="6" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD4" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD4_1/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD4_1_T1_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD4_1_T1_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD4_1_T1_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD4_1/T1A1_A.txt" mylink="aarch32.instrs.VLD4_1.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD4 (single 4-element structure to all lanes)";</line>
<line>ebytes = 1;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:1&gt;);  inc = 1;</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  d4 = d3 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d4 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d4 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="6" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD4" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD4_1/T2A2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD4_1_T2_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD4_1_T2_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD4_1_T2_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD4_1/T2A2_A.txt" mylink="aarch32.instrs.VLD4_1.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD4 (single 4-element structure to all lanes)";</line>
<line>ebytes = 2;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:2&gt;);</line>
<line>inc = if index_align&lt;1&gt; == '0' then 1 else 2;</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 8;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  d4 = d3 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d4 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d4 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T3" oneof="6" id="iclass_t3" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD4" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD4_1/T3A3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD4_1_T3_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD4_1_T3_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD4_1_T3_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD4_1/T3A3_A.txt" mylink="aarch32.instrs.VLD4_1.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "VLD4 (single 4-element structure to all lanes)";</line>
<line>if index_align&lt;1:0&gt; == '11' then UNDEFINED;</line>
<line>ebytes = 4;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3&gt;);</line>
<line>inc = if index_align&lt;2&gt; == '0' then 1 else 2;</line>
<line>alignment = if index_align&lt;1:0&gt; == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;1:0&gt;);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  d4 = d3 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d4 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d4 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VLD4_1_A1_nowb, VLD4_1_A2_nowb, VLD4_1_A3_nowb" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1, A2 and A3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD4_1_T1_nowb, VLD4_1_T2_nowb, VLD4_1_T3_nowb" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1, T2 and T3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD4_1_A1_nowb, VLD4_1_A2_nowb, VLD4_1_A3_nowb, VLD4_1_T1_nowb, VLD4_1_T2_nowb, VLD4_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD4_1_A1_nowb, VLD4_1_A2_nowb, VLD4_1_A3_nowb, VLD4_1_T1_nowb, VLD4_1_T2_nowb, VLD4_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data size, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VLD4_1_A1_nowb, VLD4_1_A2_nowb, VLD4_1_A3_nowb, VLD4_1_T1_nowb, VLD4_1_T2_nowb, VLD4_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="index_align&lt;1&gt;">
        <intro>
          <para>Is a list containing the 64-bit names of the four SIMD&amp;FP registers holding the element.</para>
          <para>The list must be one of:</para>
          <list type="param">
            <listitem>
              <param><syntax>{ &lt;Dd&gt;[&lt;index&gt;], &lt;Dd+1&gt;[&lt;index&gt;], &lt;Dd+2&gt;[&lt;index&gt;], &lt;Dd+3&gt;[&lt;index&gt;] }</syntax></param><content>Single-spaced registers, encoded as "spacing" = <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;[&lt;index&gt;], &lt;Dd+2&gt;[&lt;index&gt;], &lt;Dd+4&gt;[&lt;index&gt;], &lt;Dd+6&gt;[&lt;index&gt;] }</syntax></param><content>Double-spaced registers, encoded as "spacing" = <binarynumber>1</binarynumber>. Not permitted when <syntax>&lt;size&gt;</syntax> == 8.</content>
            </listitem>
          </list>
          <para>The encoding of "spacing" depends on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content>"spacing" is encoded in the "index_align&lt;1&gt;" field.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content>"spacing" is encoded in the "index_align&lt;2&gt;" field.</content>
            </listitem>
          </list>
          <para>The register <syntax>&lt;Dd&gt;</syntax> is encoded in the "D:Vd" field.</para>
          <para>The permitted values and encoding of <syntax>&lt;index&gt;</syntax> depend on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 8</param><content><syntax>&lt;index&gt;</syntax> is in the range 0 to 7, encoded in the "index_align&lt;3:1&gt;" field.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content><syntax>&lt;index&gt;</syntax> is in the range 0 to 3, encoded in the "index_align&lt;3:2&gt;" field.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content><syntax>&lt;index&gt;</syntax> is 0 or 1, encoded in the "index_align&lt;3&gt;" field.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD4_1_A1_nowb, VLD4_1_A2_nowb, VLD4_1_A3_nowb, VLD4_1_T1_nowb, VLD4_1_T2_nowb, VLD4_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD4_1_A1_nowb, VLD4_1_A2_nowb, VLD4_1_A3_nowb, VLD4_1_T1_nowb, VLD4_1_T2_nowb, VLD4_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_align">&lt;align&gt;</symbol>
      <account encodedin="index_align&lt;0&gt;">
        <intro>
          <para>Is the optional alignment.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is omitted, the standard alignment is used, see <xref linkend="Chdijihg">Unaligned data access</xref>, and the encoding depends on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 8</param><content>Encoded in the "index_align&lt;0&gt;" field as <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content>Encoded in the "index_align&lt;0&gt;" field as <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content>Encoded in the "index_align&lt;1:0&gt;" field as <binarynumber>0b00</binarynumber>.</content>
            </listitem>
          </list>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is present, the permitted values and encoding depend on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 8</param><content><syntax>&lt;align&gt;</syntax> is 32, meaning 32-bit alignment, encoded in the "index_align&lt;0&gt;" field as <binarynumber>1</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content><syntax>&lt;align&gt;</syntax> is 64, meaning 64-bit alignment, encoded in the "index_align&lt;0&gt;" field as <binarynumber>1</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content><syntax>&lt;align&gt;</syntax> can be 64 or 128. 64-bit alignment is encoded in the "index_align&lt;1:0&gt;" field as <binarynumber>0b01</binarynumber>, and 128-bit alignment is encoded in the "index_align&lt;1:0&gt;" field as <binarynumber>0b10</binarynumber>.</content>
            </listitem>
          </list>
          <para><value>:</value> is the preferred separator before the <syntax>&lt;align&gt;</syntax> value, but the alignment can be specified as <value>@&lt;align&gt;</value>, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD4_1_A1_postr, VLD4_1_A2_postr, VLD4_1_A3_postr, VLD4_1_T1_postr, VLD4_1_T2_postr, VLD4_1_T3_postr" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VLD4_1/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line></line>
<line>    boolean nontemporal = FALSE;</line>
<line>    boolean tagchecked  = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, nontemporal, tagchecked);</line>
<line>    if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment) then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d], index,8*ebytes] = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,ebytes];</line>
<line>    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d2],index,8*ebytes] = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+ebytes,ebytes];</line>
<line>    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d3],index,8*ebytes] = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+2*ebytes,ebytes];</line>
<line>    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d4],index,8*ebytes] = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+3*ebytes,ebytes];</line>
<line>    if wback then</line>
<line>        if register_index then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 4*ebytes;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vld4_a.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VLD4_a" title="VLD4 (single 4-element structure to all lanes) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VLD4" />
  </docvars>
  <heading>VLD4 (single 4-element structure to all lanes)</heading>
  <desc>
    <brief>
      <para>Load single 4-element structure and replicate to all lanes of four registers</para>
    </brief>
    <authored>
      <para>Load single 4-element structure and replicate to all lanes of four registers loads one 4-element structure from memory into all lanes of four registers. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGGCHBB">VLD4 (single 4-element structure to all lanes)</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For more information about the variants of this instruction, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD4" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD4_a/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" name="T" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="a" usename="1">
          <c></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD4_a_A1_nowb" oneofinclass="3" oneof="6" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;a&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD4_a_A1_posti" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;a&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD4_a_A1_postr" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;a&quot;)">&lt;align&gt;</a><text>}</text><text>],</text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD4_a/T1A1_A.txt" mylink="aarch32.instrs.VLD4_a.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' &amp;&amp; a == '0' then UNDEFINED;</line>
<line>integer ebytes;</line>
<line>integer alignment;</line>
<line>if size == '11' then</line>
<line>    ebytes = 4;  alignment = 16;</line>
<line>else</line>
<line>    ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);</line>
<line>    if size == '10' then</line>
<line>        alignment = if a == '0' then 1 else 8;</line>
<line>    else</line>
<line>        alignment = if a == '0' then 1 else 4*ebytes;</line>
<line>inc = if T == '0' then 1 else 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  d4 = d3 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d4 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d4 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD4" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD4_a/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" name="T" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="a" usename="1">
          <c></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD4_a_T1_nowb" oneofinclass="3" oneof="6" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;a&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD4_a_T1_posti" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;a&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD4_a_T1_postr" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;a&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD4_a/T1A1_A.txt" mylink="aarch32.instrs.VLD4_a.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' &amp;&amp; a == '0' then UNDEFINED;</line>
<line>integer ebytes;</line>
<line>integer alignment;</line>
<line>if size == '11' then</line>
<line>    ebytes = 4;  alignment = 16;</line>
<line>else</line>
<line>    ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);</line>
<line>    if size == '10' then</line>
<line>        alignment = if a == '0' then 1 else 8;</line>
<line>    else</line>
<line>        alignment = if a == '0' then 1 else 4*ebytes;</line>
<line>inc = if T == '0' then 1 else 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  d4 = d3 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d4 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d4 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VLD4_a_A1_nowb" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD4_a_T1_nowb" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD4_a_A1_nowb, VLD4_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD4_a_A1_nowb, VLD4_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data size, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">1x</entry>
                <entry class="symbol">32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VLD4_a_A1_nowb, VLD4_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="T">
        <intro>
          <para>Is a list containing the 64-bit names of four SIMD&amp;FP registers.</para>
          <para>The list must be one of:</para>
          <list type="param">
            <listitem>
              <param><syntax>{ &lt;Dd&gt;[], &lt;Dd+1&gt;[], &lt;Dd+2&gt;[], &lt;Dd+3&gt;[] }</syntax></param><content>Single-spaced registers, encoded in the "T" field as <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;[], &lt;Dd+2&gt;[], &lt;Dd+4&gt;[], &lt;Dd+6&gt;[] }</syntax></param><content>Double-spaced registers, encoded in the "T" field as <binarynumber>1</binarynumber>.</content>
            </listitem>
          </list>
          <para>The register <syntax>&lt;Dd&gt;</syntax> is encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD4_a_A1_nowb, VLD4_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD4_a_A1_nowb, VLD4_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_align">&lt;align&gt;</symbol>
      <account encodedin="a">
        <intro>
          <para>Is the optional alignment.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is omitted, the standard alignment is used, see <xref linkend="Chdijihg">Unaligned data access</xref>, and is encoded in the "a" field as <binarynumber>0</binarynumber>.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is present, the permitted values and encoding depend on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 8</param><content><syntax>&lt;align&gt;</syntax> is 32, meaning 32-bit alignment, encoded in the "a" field as <binarynumber>1</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content><syntax>&lt;align&gt;</syntax> is 64, meaning 64-bit alignment, encoded in the "a" field as <binarynumber>1</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content><syntax>&lt;align&gt;</syntax> can be 64 or 128. 64-bit alignment is encoded in the "a:size&lt;0&gt;" field as <binarynumber>0b10</binarynumber>, and 128-bit alignment is encoded in the "a:size&lt;0&gt;" field as <binarynumber>0b11</binarynumber>.</content>
            </listitem>
          </list>
          <para><value>:</value> is the preferred separator before the <syntax>&lt;align&gt;</syntax> value, but the alignment can be specified as <value>@&lt;align&gt;</value>, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD4_a_A1_postr, VLD4_a_T1_postr" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VLD4_a/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line></line>
<line>    boolean nontemporal = FALSE;</line>
<line>    boolean tagchecked  = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, nontemporal, tagchecked);</line>
<line>    if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment) then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    constant integer esize = ebytes * 8;</line>
<line>    bits(esize) element1 = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address, ebytes];</line>
<line>    bits(esize) element2 = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+ebytes,ebytes];</line>
<line>    bits(esize) element3 = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+2*ebytes,ebytes];</line>
<line>    bits(esize) element4 = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+3*ebytes,ebytes];</line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element1, 64 DIV esize);</line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d2] = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element2, 64 DIV esize);</line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d3] = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element3, 64 DIV esize);</line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d4] = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element4, 64 DIV esize);</line>
<line>    if wback then</line>
<line>        if register_index then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 4*ebytes;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vld4_m.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VLD4_m" title="VLD4 (multiple 4-element structures) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VLD4" />
  </docvars>
  <heading>VLD4 (multiple 4-element structures)</heading>
  <desc>
    <brief>
      <para>Load multiple 4-element structures to four registers</para>
    </brief>
    <authored>
      <para>Load multiple 4-element structures to four registers loads multiple 4-element structures from memory into four registers, with de-interleaving. For more information, see <xref linkend="BABHJAGF">Element and structure load/store instructions</xref>. Every element of each register is loaded. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGECHGI">VLD4 (multiple 4-element structures)</xref>.</para>
      <para>Related encodings: See <xref linkend="T32.encoding_index.vldst">Advanced SIMD element or structure load/store</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimdls">Advanced SIMD element or structure load/store</xref> for the A32 instruction set.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For more information about the variants of this instruction, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD4" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD4_m/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" usename="1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>x</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD4_m_A1_nowb" oneofinclass="3" oneof="6" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD4_m_A1_posti" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD4_m_A1_postr" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD4_m/T1A1_A.txt" mylink="aarch32.instrs.VLD4_m.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>integer inc;</line>
<line>case itype of</line>
<line>    when '0000'</line>
<line>        inc = 1;</line>
<line>    when '0001'</line>
<line>        inc = 2;</line>
<line>    otherwise</line>
<line>        SEE "Related encodings";</line>
<line>if size == '11' then UNDEFINED;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  d4 = d3 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d4 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d4 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD4" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD4_m/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" usename="1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>x</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD4_m_T1_nowb" oneofinclass="3" oneof="6" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD4_m_T1_posti" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD4_m_T1_postr" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD4_m/T1A1_A.txt" mylink="aarch32.instrs.VLD4_m.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>integer inc;</line>
<line>case itype of</line>
<line>    when '0000'</line>
<line>        inc = 1;</line>
<line>    when '0001'</line>
<line>        inc = 2;</line>
<line>    otherwise</line>
<line>        SEE "Related encodings";</line>
<line>if size == '11' then UNDEFINED;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  d4 = d3 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d4 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d4 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VLD4_m_A1_nowb" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD4_m_T1_nowb" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD4_m_A1_nowb, VLD4_m_T1_nowb" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD4_m_A1_nowb, VLD4_m_T1_nowb" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data size, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VLD4_m_A1_nowb, VLD4_m_T1_nowb" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="itype">
        <intro>
          <para>Is a list containing the 64-bit names of the SIMD&amp;FP registers.</para>
          <para>The list must be one of:</para>
          <list type="param">
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+1&gt;, &lt;Dd+2&gt;, &lt;Dd+3&gt; }</syntax></param><content>Single-spaced registers, encoded in the "itype" field as <binarynumber>0b0000</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+2&gt;, &lt;Dd+4&gt;, &lt;Dd+6&gt; }</syntax></param><content>Double-spaced registers, encoded in the "itype" field as <binarynumber>0b0001</binarynumber>.</content>
            </listitem>
          </list>
          <para>The register <syntax>&lt;Dd&gt;</syntax> is encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD4_m_A1_nowb, VLD4_m_T1_nowb" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD4_m_A1_nowb, VLD4_m_T1_nowb" symboldefcount="1">
      <symbol link="sa_align">&lt;align&gt;</symbol>
      <account encodedin="align">
        <intro>
          <para>Is the optional alignment.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is omitted, the standard alignment is used, see <xref linkend="Chdijihg">Unaligned data access</xref>, and is encoded in the "align" field as <binarynumber>0b00</binarynumber>.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is present, the permitted values are:</para>
          <list type="param">
            <listitem>
              <param>64</param><content>64-bit alignment, encoded in the "align" field as <binarynumber>0b01</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>128</param><content>128-bit alignment, encoded in the "align" field as <binarynumber>0b10</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>256</param><content>256-bit alignment, encoded in the "align" field as <binarynumber>0b11</binarynumber>.</content>
            </listitem>
          </list>
          <para><value>:</value> is the preferred separator before the <syntax>&lt;align&gt;</syntax> value, but the alignment can be specified as <value>@&lt;align&gt;</value>, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD4_m_A1_postr, VLD4_m_T1_postr" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VLD4_m/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line></line>
<line>    boolean nontemporal = FALSE;</line>
<line>    boolean tagchecked  = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, nontemporal, tagchecked);</line>
<line>    if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment) then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    for e = 0 to elements-1</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d], e,8*ebytes] = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,ebytes];</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d2],e,8*ebytes] = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+ebytes,ebytes];</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d3],e,8*ebytes] = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+2*ebytes,ebytes];</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d4],e,8*ebytes] = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+3*ebytes,ebytes];</line>
<line>        address = address + 4*ebytes;</line>
<line>    if wback then</line>
<line>        if register_index then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 32;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vldm.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VLDM" title="VLDM, VLDMDB, VLDMIA -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
  </docvars>
  <heading>VLDM, VLDMDB, VLDMIA</heading>
  <desc>
    <brief>
      <para>Load Multiple SIMD&amp;FP registers</para>
    </brief>
    <authored>
      <para>Load Multiple SIMD&amp;FP registers loads multiple registers from consecutive locations in the Advanced SIMD and floating-point register file using an address from a general-purpose register.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGFAHHG">VLDM</xref>.</para>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simdfp_mov64">Advanced SIMD and floating-point 64-bit move</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.movsimdfpgp64">Advanced SIMD and floating-point 64-bit move</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="1">
    <alias_list_intro>This instruction is used by the alias </alias_list_intro>
    <aliasref aliaspageid="VPOP_VLDM" aliasfile="vpop_vldm.xml" hover="Pop SIMD&amp;FP registers from Stack" punct=".">
      <text>VPOP</text>
      <aliaspref>P == '0' &amp;&amp; U == '1' &amp;&amp; W == '1' &amp;&amp; Rn == '1101'</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink />
      <text> below for details of when the alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="fpdatasize" value="doubleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLDM/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="7" name="imm8&lt;7:1&gt;" usename="1">
          <c colspan="7"></c>
        </box>
        <box hibit="0" name="imm8&lt;0&gt;" usename="1" settings="1">
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="VLDMDB_A1" oneofinclass="2" oneof="8" label="Decrement Before" bitdiffs="P == 1 &amp;&amp; U == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="VLDMDB" />
          <docvar key="mnemonic-fpdatasize" value="VLDMDB-doubleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>VLDMDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>!, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VLDM_A1" oneofinclass="2" oneof="8" label="Increment After" bitdiffs="P == 0 &amp;&amp; U == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="inc-after" />
          <docvar key="mnemonic" value="VLDM" />
          <docvar key="mnemonic-fpdatasize" value="VLDM-doubleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>1</c>
        </box>
        <asmtemplate><text>VLDM</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="Specifies base register writeback (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
        <asmtemplate><text>VLDMIA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="Specifies base register writeback (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLDM/T1A1_A.txt" mylink="aarch32.instrs.VLDM.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; U == '0' &amp;&amp; W == '0' then SEE "Related encodings";</line>
<line>if P == '1' &amp;&amp; W == '0' then SEE "VLDR";</line>
<line>if P == U &amp;&amp; W == '1' then UNDEFINED;</line>
<line>// Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)</line>
<line>single_regs = FALSE;  add = (U == '1');  wback = (W == '1');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
<line>regs = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm8) DIV 2;  // If UInt(imm8) is odd, see "FLDM*X".</line>
<line>if n == 15 &amp;&amp; (wback || <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>) then UNPREDICTABLE;</line>
<line>if regs == 0 || regs &gt; 16 || (d+regs) &gt; 32 then UNPREDICTABLE;</line>
<line>if imm8&lt;0&gt; == '1' &amp;&amp; (d+regs) &gt; 16 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>regs == 0</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction operates as a <instruction>VLDM</instruction> with the same addressing mode but loads no registers.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>regs &gt; 16 || (d+regs) &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="fpdatasize" value="singleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLDM/T2A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="VLDMDB_A2" oneofinclass="2" oneof="8" label="Decrement Before" bitdiffs="P == 1 &amp;&amp; U == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="VLDMDB" />
          <docvar key="mnemonic-fpdatasize" value="VLDMDB-singleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>VLDMDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>!, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VLDM_A2" oneofinclass="2" oneof="8" label="Increment After" bitdiffs="P == 0 &amp;&amp; U == 1">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="inc-after" />
          <docvar key="mnemonic" value="VLDM" />
          <docvar key="mnemonic-fpdatasize" value="VLDM-singleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>1</c>
        </box>
        <asmtemplate><text>VLDM</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="Specifies base register writeback (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
        <asmtemplate><text>VLDMIA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="Specifies base register writeback (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLDM/T2A2_A.txt" mylink="aarch32.instrs.VLDM.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; U == '0' &amp;&amp; W == '0' then SEE "Related encodings";</line>
<line>if P == '1' &amp;&amp; W == '0' then SEE "VLDR";</line>
<line>if P == U &amp;&amp; W == '1' then UNDEFINED;</line>
<line>// Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)</line>
<line>single_regs = TRUE;  add = (U == '1');  wback = (W == '1');  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);  regs = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm8);</line>
<line>if n == 15 &amp;&amp; (wback || <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>) then UNPREDICTABLE;</line>
<line>if regs == 0 || (d+regs) &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>regs == 0</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction operates as a <instruction>VLDM</instruction> with the same addressing mode but loads no registers.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>(d+regs) &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="fpdatasize" value="doubleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLDM/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="7" name="imm8&lt;7:1&gt;" usename="1">
          <c colspan="7"></c>
        </box>
        <box hibit="0" name="imm8&lt;0&gt;" usename="1" settings="1">
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="VLDMDB_T1" oneofinclass="2" oneof="8" label="Decrement Before" bitdiffs="P == 1 &amp;&amp; U == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="VLDMDB" />
          <docvar key="mnemonic-fpdatasize" value="VLDMDB-doubleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>VLDMDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>!, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VLDM_T1" oneofinclass="2" oneof="8" label="Increment After" bitdiffs="P == 0 &amp;&amp; U == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="ldmstm-mode" value="inc-after" />
          <docvar key="mnemonic" value="VLDM" />
          <docvar key="mnemonic-fpdatasize" value="VLDM-doubleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>1</c>
        </box>
        <asmtemplate><text>VLDM</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="Specifies base register writeback (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
        <asmtemplate><text>VLDMIA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="Specifies base register writeback (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLDM/T1A1_A.txt" mylink="aarch32.instrs.VLDM.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; U == '0' &amp;&amp; W == '0' then SEE "Related encodings";</line>
<line>if P == '1' &amp;&amp; W == '0' then SEE "VLDR";</line>
<line>if P == U &amp;&amp; W == '1' then UNDEFINED;</line>
<line>// Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)</line>
<line>single_regs = FALSE;  add = (U == '1');  wback = (W == '1');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
<line>regs = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm8) DIV 2;  // If UInt(imm8) is odd, see "FLDM*X".</line>
<line>if n == 15 &amp;&amp; (wback || <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>) then UNPREDICTABLE;</line>
<line>if regs == 0 || regs &gt; 16 || (d+regs) &gt; 32 then UNPREDICTABLE;</line>
<line>if imm8&lt;0&gt; == '1' &amp;&amp; (d+regs) &gt; 16 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>regs == 0</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction operates as a <instruction>VLDM</instruction> with the same addressing mode but loads no registers.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>regs &gt; 16 || (d+regs) &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="fpdatasize" value="singleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLDM/T2A2_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="VLDMDB_T2" oneofinclass="2" oneof="8" label="Decrement Before" bitdiffs="P == 1 &amp;&amp; U == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="VLDMDB" />
          <docvar key="mnemonic-fpdatasize" value="VLDMDB-singleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>VLDMDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>!, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VLDM_T2" oneofinclass="2" oneof="8" label="Increment After" bitdiffs="P == 0 &amp;&amp; U == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="ldmstm-mode" value="inc-after" />
          <docvar key="mnemonic" value="VLDM" />
          <docvar key="mnemonic-fpdatasize" value="VLDM-singleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>1</c>
        </box>
        <asmtemplate><text>VLDM</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="Specifies base register writeback (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
        <asmtemplate><text>VLDMIA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="Specifies base register writeback (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLDM/T2A2_A.txt" mylink="aarch32.instrs.VLDM.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; U == '0' &amp;&amp; W == '0' then SEE "Related encodings";</line>
<line>if P == '1' &amp;&amp; W == '0' then SEE "VLDR";</line>
<line>if P == U &amp;&amp; W == '1' then UNDEFINED;</line>
<line>// Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)</line>
<line>single_regs = TRUE;  add = (U == '1');  wback = (W == '1');  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);  regs = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm8);</line>
<line>if n == 15 &amp;&amp; (wback || <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>) then UNPREDICTABLE;</line>
<line>if regs == 0 || (d+regs) &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>regs == 0</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction operates as a <instruction>VLDM</instruction> with the same addressing mode but loads no registers.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>(d+regs) &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VLDM_A1, VLDM_A2, VLDM_T1, VLDM_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLDM_A1, VLDM_A2, VLDM_T1, VLDM_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLDM_A1, VLDM_A2, VLDM_T1, VLDM_T2" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>An optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers being transferred.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLDM_A1, VLDM_A2, VLDM_T1, VLDM_T2" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field. If writeback is not specified, the PC can be used.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLDM_A1, VLDM_A2, VLDM_T1, VLDM_T2" symboldefcount="1">
      <symbol link="sa_0d33">!</symbol>
      <account encodedin="W">
        <intro>
          <para>Specifies base register writeback. Encoded in the "W" field as 1 if present, otherwise 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLDM_A2, VLDM_T2" symboldefcount="1">
      <symbol link="sa_sreglist">&lt;sreglist&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the list of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred. The first register in the list is encoded in "Vd:D", and "imm8" is set to the number of registers in the list. The list must contain at least one register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLDM_A1, VLDM_T1" symboldefcount="1">
      <symbol link="sa_dreglist">&lt;dreglist&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the list of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred. The first register in the list is encoded in "D:Vd", and "imm8" is set to twice the number of registers in the list. The list must contain at least one register, and must not contain more than 16 registers.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VLDM/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    address = if add then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]-imm32;</line>
<line></line>
<line>    for r = 0 to regs-1</line>
<line>        if single_regs then</line>
<line>            <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d+r] = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,4];</line>
<line>            address = address+4;</line>
<line>        else</line>
<line>            word1 = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,4];</line>
<line>            word2 = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address+4,4];</line>
<line>            address = address+8;</line>
<line></line>
<line>            // Combine the word-aligned words in the correct order for current endianness.</line>
<line>            <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_ASIMD" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_ASIMD</a>) then word1:word2 else word2:word1;</line>
<line></line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = if add then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]+imm32 else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]-imm32;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vldr_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VLDR_i" title="VLDR (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="address-form" value="base-plus-offset" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VLDR" />
  </docvars>
  <heading>VLDR (immediate)</heading>
  <desc>
    <brief>
      <para>Load SIMD&amp;FP register (immediate)</para>
    </brief>
    <authored>
      <para>Load SIMD&amp;FP register (immediate) loads a single register from the Advanced SIMD and floating-point register file, using an address from a general-purpose register, with an optional offset.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLDR" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLDR/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="VLDR_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLDR" />
          <docvar key="mnemonic-fpdatasize" value="VLDR-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLDR_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLDR" />
          <docvar key="mnemonic-fpdatasize" value="VLDR-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><a link="sa_32" hover="Optional data size specifier for 32-bit memory accesses that can be used in the assembler source code">{.32}</a><text> </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLDR_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLDR" />
          <docvar key="mnemonic-fpdatasize" value="VLDR-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><a link="sa_64" hover="Optional data size specifier for 64-bit memory accesses that can be used in the assembler source code">{.64}</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLDR/A1_A.txt" mylink="aarch32.instrs.VLDR.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  add = (U == '1');</line>
<line>imm32 = if esize == 16 then <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'0', 32) else <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
<line>integer d;</line>
<line>case size of</line>
<line>    when '01' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '10' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '11' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLDR" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLDR/T1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="VLDR_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLDR" />
          <docvar key="mnemonic-fpdatasize" value="VLDR-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLDR_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLDR" />
          <docvar key="mnemonic-fpdatasize" value="VLDR-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><a link="sa_32" hover="Optional data size specifier for 32-bit memory accesses that can be used in the assembler source code">{.32}</a><text> </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLDR_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLDR" />
          <docvar key="mnemonic-fpdatasize" value="VLDR-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><a link="sa_64" hover="Optional data size specifier for 64-bit memory accesses that can be used in the assembler source code">{.64}</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLDR/T1_A.txt" mylink="aarch32.instrs.VLDR.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  add = (U == '1');</line>
<line>imm32 = if esize == 16 then <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'0', 32) else <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
<line>integer d;</line>
<line>case size of</line>
<line>    when '01' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '10' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '11' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VLDR_A1_H, VLDR_T1_H" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLDR_A1_H, VLDR_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLDR_A1_D, VLDR_T1_D" symboldefcount="1">
      <symbol link="sa_64">.64</symbol>
      <account encodedin="">
        <intro>
          <para>Is an optional data size specifier for 64-bit memory accesses that can be used in the assembler source code, but is otherwise ignored.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLDR_A1_D, VLDR_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLDR_A1_S, VLDR_T1_S" symboldefcount="1">
      <symbol link="sa_32">.32</symbol>
      <account encodedin="">
        <intro>
          <para>Is an optional data size specifier for 32-bit memory accesses that can be used in the assembler source code, but is otherwise ignored.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLDR_A1_H, VLDR_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLDR_A1_H, VLDR_T1_H" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLDR_A1_H, VLDR_T1_H" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VLDR_A1_H, VLDR_T1_H" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <intro>
          <para>For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset, a multiple of 4, in the range 0 to 1020, defaulting to 0, and encoded in the "imm8" field as &lt;imm&gt;/4.</para>
          <para>For the half-precision scalar variant: is the optional unsigned immediate byte offset, a multiple of 2, in the range 0 to 510, defaulting to 0, and encoded in the "imm8" field as &lt;imm&gt;/2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VLDR/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    base = if n == 15 then <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4) else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    address = if add then (base + imm32) else (base - imm32);</line>
<line>    case esize of</line>
<line>        when 16</line>
<line>            <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,2];</line>
<line>        when 32</line>
<line>            <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,4];</line>
<line>        when 64</line>
<line>            word1 = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,4];</line>
<line>            word2 = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address+4,4];</line>
<line>            // Combine the word-aligned words in the correct order for current endianness.</line>
<line>            <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_ASIMD" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_ASIMD</a>) then word1:word2 else word2:word1;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vldr_l.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VLDR_l" title="VLDR (literal) -- AArch32" type="instruction">
  <docvars>
    <docvar key="address-form" value="literal" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VLDR" />
  </docvars>
  <heading>VLDR (literal)</heading>
  <desc>
    <brief>
      <para>Load SIMD&amp;FP register (literal)</para>
    </brief>
    <authored>
      <para>Load SIMD&amp;FP register (literal) loads a single register from the Advanced SIMD and floating-point register file, using an address from the PC value and an immediate offset.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <syntaxnotes>
      <para>The alternative syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see <xref linkend="BABGCIBA">Use of labels in UAL instruction syntax</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="address-form" value="literal" />
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLDR" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLDR/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="VLDR_l_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLDR" />
          <docvar key="mnemonic-fpdatasize" value="VLDR-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_label" hover="The label of literal data item to be loaded">&lt;label&gt;</a></asmtemplate>
        <asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLDR_l_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLDR" />
          <docvar key="mnemonic-fpdatasize" value="VLDR-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><a link="sa_32" hover="Optional data size specifier for 32-bit memory accesses that can be used in the assembler source code">{.32}</a><text> </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_label" hover="The label of literal data item to be loaded">&lt;label&gt;</a></asmtemplate>
        <asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><a link="sa_32" hover="Optional data size specifier for 32-bit memory accesses that can be used in the assembler source code">{.32}</a><text> </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLDR_l_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLDR" />
          <docvar key="mnemonic-fpdatasize" value="VLDR-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><a link="sa_64" hover="Optional data size specifier for 64-bit memory accesses that can be used in the assembler source code">{.64}</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_label" hover="The label of literal data item to be loaded">&lt;label&gt;</a></asmtemplate>
        <asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><a link="sa_64" hover="Optional data size specifier for 64-bit memory accesses that can be used in the assembler source code">{.64}</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLDR/A1_A.txt" mylink="aarch32.instrs.VLDR.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  add = (U == '1');</line>
<line>imm32 = if esize == 16 then <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'0', 32) else <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
<line>integer d;</line>
<line>case size of</line>
<line>    when '01' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '10' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '11' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="address-form" value="literal" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLDR" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLDR/T1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="VLDR_l_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLDR" />
          <docvar key="mnemonic-fpdatasize" value="VLDR-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_label" hover="The label of literal data item to be loaded">&lt;label&gt;</a></asmtemplate>
        <asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLDR_l_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLDR" />
          <docvar key="mnemonic-fpdatasize" value="VLDR-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><a link="sa_32" hover="Optional data size specifier for 32-bit memory accesses that can be used in the assembler source code">{.32}</a><text> </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_label" hover="The label of literal data item to be loaded">&lt;label&gt;</a></asmtemplate>
        <asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><a link="sa_32" hover="Optional data size specifier for 32-bit memory accesses that can be used in the assembler source code">{.32}</a><text> </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLDR_l_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="address-form" value="literal" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLDR" />
          <docvar key="mnemonic-fpdatasize" value="VLDR-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><a link="sa_64" hover="Optional data size specifier for 64-bit memory accesses that can be used in the assembler source code">{.64}</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_label" hover="The label of literal data item to be loaded">&lt;label&gt;</a></asmtemplate>
        <asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><a link="sa_64" hover="Optional data size specifier for 64-bit memory accesses that can be used in the assembler source code">{.64}</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLDR/T1_A.txt" mylink="aarch32.instrs.VLDR.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  add = (U == '1');</line>
<line>imm32 = if esize == 16 then <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'0', 32) else <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
<line>integer d;</line>
<line>case size of</line>
<line>    when '01' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '10' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '11' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VLDR_l_A1_H, VLDR_l_T1_H" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLDR_l_A1_H, VLDR_l_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLDR_l_A1_D, VLDR_l_T1_D" symboldefcount="1">
      <symbol link="sa_64">.64</symbol>
      <account encodedin="">
        <intro>
          <para>Is an optional data size specifier for 64-bit memory accesses that can be used in the assembler source code, but is otherwise ignored.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLDR_l_A1_D, VLDR_l_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLDR_l_A1_S, VLDR_l_T1_S" symboldefcount="1">
      <symbol link="sa_32">.32</symbol>
      <account encodedin="">
        <intro>
          <para>Is an optional data size specifier for 32-bit memory accesses that can be used in the assembler source code, but is otherwise ignored.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLDR_l_A1_H, VLDR_l_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLDR_l_A1_H, VLDR_l_T1_H" symboldefcount="1">
      <symbol link="sa_label">&lt;label&gt;</symbol>
      <account encodedin="imm8">
        <intro>
          <para>The label of the literal data item to be loaded.</para>
          <para>For the single-precision scalar or double-precision scalar variants: the assembler calculates the required value of the offset from the Align(PC, 4) value of the instruction to this label. Permitted values are multiples of 4 in the range -1020 to 1020.</para>
          <para>For the half-precision scalar variant: the assembler calculates the required value of the offset from the Align(PC, 4) value of the instruction to this label. Permitted values are multiples of 2 in the range -510 to 510.</para>
          <para>If the offset is zero or positive, <field>imm32</field> is equal to the offset and <field>add</field> == <enumvalue>TRUE</enumvalue>.</para>
          <para>If the offset is negative, <field>imm32</field> is equal to minus the offset and <field>add</field> == <enumvalue>FALSE</enumvalue>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLDR_l_A1_H, VLDR_l_T1_H" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VLDR_l_A1_H, VLDR_l_T1_H" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <intro>
          <para>For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset, a multiple of 4, in the range 0 to 1020, defaulting to 0, and encoded in the "imm8" field as &lt;imm&gt;/4.</para>
          <para>For the half-precision scalar variant: is the optional unsigned immediate byte offset, a multiple of 2, in the range 0 to 510, defaulting to 0, and encoded in the "imm8" field as &lt;imm&gt;/2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VLDR/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    base = if n == 15 then <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4) else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    address = if add then (base + imm32) else (base - imm32);</line>
<line>    case esize of</line>
<line>        when 16</line>
<line>            <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,2];</line>
<line>        when 32</line>
<line>            <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,4];</line>
<line>        when 64</line>
<line>            word1 = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,4];</line>
<line>            word2 = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address+4,4];</line>
<line>            // Combine the word-aligned words in the correct order for current endianness.</line>
<line>            <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_ASIMD" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_ASIMD</a>) then word1:word2 else word2:word1;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmax_f.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMAX_f" title="VMAX (floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMAX" />
  </docvars>
  <heading>VMAX (floating-point)</heading>
  <desc>
    <brief>
      <para>Vector Maximum (floating-point)</para>
    </brief>
    <authored>
      <para>Vector Maximum compares corresponding elements in two vectors, and copies the larger of each pair into the corresponding element in the destination vector.</para>
      <para>The operand vector elements are floating-point numbers.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <syntaxnotes>
      <para>Floating-point maximum and minimum</para>
      <list type="unordered">
        <listitem><content>max(+0.0, -0.0) = +0.0</content></listitem>
        <listitem><content>If any input is a NaN, the corresponding result element is the default NaN.</content></listitem>
      </list>
    </syntaxnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMAX" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMAX_f/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMAX_f_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMAX" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMAX</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMAX_f_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMAX" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMAX</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMAX_f/A1_A.txt" mylink="aarch32.instrs.VMAX_f.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>maximum = (op == '0');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMAX" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMAX_f/T1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMAX_f_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMAX" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMAX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMAX_f_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMAX" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMAX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMAX_f/T1_A.txt" mylink="aarch32.instrs.VMAX_f.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>maximum = (op == '0');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>sz == '1' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMAX_f_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAX_f_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAX_f_A1_Q, VMAX_f_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAX_f_A1_Q, VMAX_f_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VMAX_f_A1_Q, VMAX_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAX_f_A1_Q, VMAX_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAX_f_A1_Q, VMAX_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAX_f_A1_D, VMAX_f_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAX_f_A1_D, VMAX_f_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAX_f_A1_D, VMAX_f_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMAX_f/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize];  op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize];</line>
<line>            if maximum then</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPMax.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(op1, op2, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            else</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPMin.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(op1, op2, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmax_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMAX_i" title="VMAX (integer) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMAX" />
  </docvars>
  <heading>VMAX (integer)</heading>
  <desc>
    <brief>
      <para>Vector Maximum (integer)</para>
    </brief>
    <authored>
      <para>Vector Maximum compares corresponding elements in two vectors, and copies the larger of each pair into the corresponding element in the destination vector.</para>
      <para>The operand vector elements can be any one of:</para>
      <list type="unordered">
        <listitem><content>8-bit, 16-bit, or 32-bit signed integers.</content></listitem>
        <listitem><content>8-bit, 16-bit, or 32-bit unsigned integers.</content></listitem>
      </list>
      <para>The result vector elements are the same size as the operand vector elements.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMAX" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMAX_i/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMAX_i_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMAX" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMAX</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMAX_i_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMAX" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMAX</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMAX_i/T1A1_A.txt" mylink="aarch32.instrs.VMAX_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>maximum = (op == '0');  unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMAX" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMAX_i/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMAX_i_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMAX" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMAX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMAX_i_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMAX" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMAX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMAX_i/T1A1_A.txt" mylink="aarch32.instrs.VMAX_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>maximum = (op == '0');  unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMAX_i_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAX_i_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAX_i_A1_Q, VMAX_i_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAX_i_A1_Q, VMAX_i_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VMAX_i_A1_Q, VMAX_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAX_i_A1_Q, VMAX_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAX_i_A1_Q, VMAX_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAX_i_A1_D, VMAX_i_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAX_i_A1_D, VMAX_i_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAX_i_A1_D, VMAX_i_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMAX_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize], unsigned);</line>
<line>            op2 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], unsigned);</line>
<line>            result = if maximum then <a link="impl-shared.Max.2" file="shared_pseudocode.xml" hover="function: integer Max(integer a, integer b)">Max</a>(op1,op2) else <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(op1,op2);</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result&lt;esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmaxnm.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMAXNM" title="VMAXNM -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMAXNM" />
  </docvars>
  <heading>VMAXNM</heading>
  <desc>
    <brief>
      <para>Floating-point Maximum Number</para>
    </brief>
    <authored>
      <para>This instruction determines the floating-point maximum number.</para>
      <para>It handles NaNs in consistence with the IEEE754-2008 specification. It returns the numerical operand when one operand is numerical and the other is a quiet NaN, but otherwise the result is identical to floating-point <instruction>VMAX</instruction>.</para>
      <para>This instruction is not conditional.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMAXNM" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMAXNM/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMAXNM_A1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMAXNM" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMAXNM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMAXNM_A1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMAXNM" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMAXNM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMAXNM/A1_A.txt" mylink="aarch32.instrs.VMAXNM.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>maximum = (op == '0');</line>
<line>advsimd = TRUE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm); regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMAXNM" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMAXNM/A2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMAXNM_A2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMAXNM" />
          <docvar key="mnemonic-fpdatasize" value="VMAXNM-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VMAXNM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMAXNM_A2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMAXNM" />
          <docvar key="mnemonic-fpdatasize" value="VMAXNM-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VMAXNM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMAXNM_A2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMAXNM" />
          <docvar key="mnemonic-fpdatasize" value="VMAXNM-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VMAXNM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMAXNM/A2_A.txt" mylink="aarch32.instrs.VMAXNM.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>advsimd = FALSE;</line>
<line>maximum = (op == '0');</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMAXNM" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMAXNM/T1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMAXNM_T1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMAXNM" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMAXNM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMAXNM_T1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMAXNM" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMAXNM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMAXNM/T1_A.txt" mylink="aarch32.instrs.VMAXNM.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>maximum = (op == '0');</line>
<line>advsimd = TRUE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm); regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMAXNM" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMAXNM/T2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMAXNM_T2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMAXNM" />
          <docvar key="mnemonic-fpdatasize" value="VMAXNM-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VMAXNM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMAXNM_T2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMAXNM" />
          <docvar key="mnemonic-fpdatasize" value="VMAXNM-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VMAXNM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMAXNM_T2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMAXNM" />
          <docvar key="mnemonic-fpdatasize" value="VMAXNM-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VMAXNM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMAXNM/T2_A.txt" mylink="aarch32.instrs.VMAXNM.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>advsimd = FALSE;</line>
<line>maximum = (op == '0');</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMAXNM_A1_Q, VMAXNM_A2_H, VMAXNM_T1_Q, VMAXNM_T2_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAXNM_A1_Q, VMAXNM_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VMAXNM_A1_Q, VMAXNM_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAXNM_A1_Q, VMAXNM_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAXNM_A1_Q, VMAXNM_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAXNM_A1_D, VMAXNM_A2_D, VMAXNM_T1_D, VMAXNM_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAXNM_A1_D, VMAXNM_A2_D, VMAXNM_T1_D, VMAXNM_T2_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAXNM_A1_D, VMAXNM_A2_D, VMAXNM_T1_D, VMAXNM_T2_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAXNM_A2_H, VMAXNM_T2_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAXNM_A2_H, VMAXNM_T2_H" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMAXNM_A2_H, VMAXNM_T2_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMAXNM/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDOrVFPEnabled.2" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDOrVFPEnabled(boolean include_fpexc_check, boolean advsimd)">CheckAdvSIMDOrVFPEnabled</a>(TRUE, advsimd);</line>
<line>if advsimd then             // Advanced SIMD instruction</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r], e, esize]; op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r], e, esize];</line>
<line>            if maximum then</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r], e, esize] = <a link="impl-shared.FPMaxNum.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMaxNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)">FPMaxNum</a>(op1, op2, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            else</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r], e, esize] = <a link="impl-shared.FPMinNum.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMinNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)">FPMinNum</a>(op1, op2, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>else                        // VFP instruction</line>
<line>    case esize of</line>
<line>        when 16</line>
<line>            if maximum then</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPMaxNum.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMaxNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)">FPMaxNum</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[]);</line>
<line>            else</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPMinNum.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMinNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)">FPMinNum</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[]);</line>
<line>        when 32</line>
<line>            if maximum then</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPMaxNum.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMaxNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)">FPMaxNum</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n], <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[]);</line>
<line>            else</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPMinNum.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMinNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)">FPMinNum</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n], <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[]);</line>
<line>        when 64</line>
<line>            if maximum then</line>
<line>                <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPMaxNum.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMaxNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)">FPMaxNum</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n], <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[]);</line>
<line>            else</line>
<line>                <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPMinNum.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMinNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)">FPMinNum</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n], <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmin_f.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMIN_f" title="VMIN (floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMIN" />
  </docvars>
  <heading>VMIN (floating-point)</heading>
  <desc>
    <brief>
      <para>Vector Minimum (floating-point)</para>
    </brief>
    <authored>
      <para>Vector Minimum compares corresponding elements in two vectors, and copies the smaller of each pair into the corresponding element in the destination vector.</para>
      <para>The operand vector elements are floating-point numbers.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <syntaxnotes>
      <para>Floating-point minimum</para>
      <list type="unordered">
        <listitem><content>min(+0.0, -0.0) = -0.0</content></listitem>
        <listitem><content>If any input is a NaN, the corresponding result element is the default NaN.</content></listitem>
      </list>
    </syntaxnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMIN" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMAX_f/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMIN_f_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMIN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMIN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMIN_f_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMIN" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMIN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMAX_f/A1_A.txt" mylink="aarch32.instrs.VMAX_f.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>maximum = (op == '0');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMIN" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMAX_f/T1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMIN_f_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMIN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMIN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMIN_f_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMIN" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMIN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMAX_f/T1_A.txt" mylink="aarch32.instrs.VMAX_f.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>maximum = (op == '0');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>sz == '1' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMIN_f_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMIN_f_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMIN_f_A1_Q, VMIN_f_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMIN_f_A1_Q, VMIN_f_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VMIN_f_A1_Q, VMIN_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMIN_f_A1_Q, VMIN_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMIN_f_A1_Q, VMIN_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMIN_f_A1_D, VMIN_f_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMIN_f_A1_D, VMIN_f_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMIN_f_A1_D, VMIN_f_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMAX_f/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize];  op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize];</line>
<line>            if maximum then</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPMax.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(op1, op2, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            else</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPMin.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(op1, op2, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmin_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMIN_i" title="VMIN (integer) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMIN" />
  </docvars>
  <heading>VMIN (integer)</heading>
  <desc>
    <brief>
      <para>Vector Minimum (integer)</para>
    </brief>
    <authored>
      <para>Vector Minimum compares corresponding elements in two vectors, and copies the smaller of each pair into the corresponding element in the destination vector.</para>
      <para>The operand vector elements can be any one of:</para>
      <list type="unordered">
        <listitem><content>8-bit, 16-bit, or 32-bit signed integers.</content></listitem>
        <listitem><content>8-bit, 16-bit, or 32-bit unsigned integers.</content></listitem>
      </list>
      <para>The result vector elements are the same size as the operand vector elements.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMIN" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMAX_i/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMIN_i_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMIN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMIN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMIN_i_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMIN" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMIN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMAX_i/T1A1_A.txt" mylink="aarch32.instrs.VMAX_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>maximum = (op == '0');  unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMIN" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMAX_i/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMIN_i_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMIN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMIN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMIN_i_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMIN" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMIN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMAX_i/T1A1_A.txt" mylink="aarch32.instrs.VMAX_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>maximum = (op == '0');  unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMIN_i_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMIN_i_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMIN_i_A1_Q, VMIN_i_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMIN_i_A1_Q, VMIN_i_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VMIN_i_A1_Q, VMIN_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMIN_i_A1_Q, VMIN_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMIN_i_A1_Q, VMIN_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMIN_i_A1_D, VMIN_i_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMIN_i_A1_D, VMIN_i_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMIN_i_A1_D, VMIN_i_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMAX_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize], unsigned);</line>
<line>            op2 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], unsigned);</line>
<line>            result = if maximum then <a link="impl-shared.Max.2" file="shared_pseudocode.xml" hover="function: integer Max(integer a, integer b)">Max</a>(op1,op2) else <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(op1,op2);</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result&lt;esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vminnm.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMINNM" title="VMINNM -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMINNM" />
  </docvars>
  <heading>VMINNM</heading>
  <desc>
    <brief>
      <para>Floating-point Minimum Number</para>
    </brief>
    <authored>
      <para>This instruction determines the floating point minimum number.</para>
      <para>It handles NaNs in consistence with the IEEE754-2008 specification. It returns the numerical operand when one operand is numerical and the other is a quiet NaN, but otherwise the result is identical to floating-point <instruction>VMIN</instruction>.</para>
      <para>This instruction is not conditional.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMINNM" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMAXNM/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMINNM_A1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMINNM" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMINNM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMINNM_A1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMINNM" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMINNM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMAXNM/A1_A.txt" mylink="aarch32.instrs.VMAXNM.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>maximum = (op == '0');</line>
<line>advsimd = TRUE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm); regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMINNM" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMAXNM/A2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMINNM_A2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMINNM" />
          <docvar key="mnemonic-fpdatasize" value="VMINNM-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VMINNM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMINNM_A2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMINNM" />
          <docvar key="mnemonic-fpdatasize" value="VMINNM-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VMINNM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMINNM_A2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMINNM" />
          <docvar key="mnemonic-fpdatasize" value="VMINNM-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VMINNM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMAXNM/A2_A.txt" mylink="aarch32.instrs.VMAXNM.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>advsimd = FALSE;</line>
<line>maximum = (op == '0');</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMINNM" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMAXNM/T1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMINNM_T1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMINNM" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMINNM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMINNM_T1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMINNM" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMINNM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMAXNM/T1_A.txt" mylink="aarch32.instrs.VMAXNM.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>maximum = (op == '0');</line>
<line>advsimd = TRUE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm); regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMINNM" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMAXNM/T2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMINNM_T2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMINNM" />
          <docvar key="mnemonic-fpdatasize" value="VMINNM-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VMINNM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMINNM_T2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMINNM" />
          <docvar key="mnemonic-fpdatasize" value="VMINNM-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VMINNM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMINNM_T2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMINNM" />
          <docvar key="mnemonic-fpdatasize" value="VMINNM-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VMINNM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMAXNM/T2_A.txt" mylink="aarch32.instrs.VMAXNM.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>advsimd = FALSE;</line>
<line>maximum = (op == '0');</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMINNM_A1_Q, VMINNM_A2_H, VMINNM_T1_Q, VMINNM_T2_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMINNM_A1_Q, VMINNM_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VMINNM_A1_Q, VMINNM_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMINNM_A1_Q, VMINNM_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMINNM_A1_Q, VMINNM_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMINNM_A1_D, VMINNM_A2_D, VMINNM_T1_D, VMINNM_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMINNM_A1_D, VMINNM_A2_D, VMINNM_T1_D, VMINNM_T2_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMINNM_A1_D, VMINNM_A2_D, VMINNM_T1_D, VMINNM_T2_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMINNM_A2_H, VMINNM_T2_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMINNM_A2_H, VMINNM_T2_H" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMINNM_A2_H, VMINNM_T2_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMAXNM/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDOrVFPEnabled.2" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDOrVFPEnabled(boolean include_fpexc_check, boolean advsimd)">CheckAdvSIMDOrVFPEnabled</a>(TRUE, advsimd);</line>
<line>if advsimd then             // Advanced SIMD instruction</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r], e, esize]; op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r], e, esize];</line>
<line>            if maximum then</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r], e, esize] = <a link="impl-shared.FPMaxNum.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMaxNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)">FPMaxNum</a>(op1, op2, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            else</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r], e, esize] = <a link="impl-shared.FPMinNum.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMinNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)">FPMinNum</a>(op1, op2, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>else                        // VFP instruction</line>
<line>    case esize of</line>
<line>        when 16</line>
<line>            if maximum then</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPMaxNum.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMaxNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)">FPMaxNum</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[]);</line>
<line>            else</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPMinNum.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMinNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)">FPMinNum</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[]);</line>
<line>        when 32</line>
<line>            if maximum then</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPMaxNum.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMaxNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)">FPMaxNum</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n], <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[]);</line>
<line>            else</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPMinNum.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMinNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)">FPMinNum</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n], <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[]);</line>
<line>        when 64</line>
<line>            if maximum then</line>
<line>                <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPMaxNum.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMaxNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)">FPMaxNum</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n], <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[]);</line>
<line>            else</line>
<line>                <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPMinNum.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMinNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)">FPMinNum</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n], <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmla_f.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMLA_f" title="VMLA (floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMLA" />
  </docvars>
  <heading>VMLA (floating-point)</heading>
  <desc>
    <brief>
      <para>Vector Multiply Accumulate (floating-point)</para>
    </brief>
    <authored>
      <para>Vector Multiply Accumulate multiplies corresponding elements in two vectors, and accumulates the results into the elements of the destination vector.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMLA" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMLA_f/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLA_f_A1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMLA" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMLA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMLA_f_A1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMLA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMLA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_f/A1_A.txt" mylink="aarch32.instrs.VMLA_f.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>advsimd = TRUE;  add = (op == '0');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMLA" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMLA_f/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLA_f_A2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMLA" />
          <docvar key="mnemonic-fpdatasize" value="VMLA-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VMLA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMLA_f_A2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMLA" />
          <docvar key="mnemonic-fpdatasize" value="VMLA-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VMLA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMLA_f_A2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMLA" />
          <docvar key="mnemonic-fpdatasize" value="VMLA-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VMLA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_f/A2_A.txt" mylink="aarch32.instrs.VMLA_f.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>advsimd = FALSE; add = (op == '0');</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMLA" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMLA_f/T1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLA_f_T1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMLA" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMLA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMLA_f_T1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMLA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMLA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_f/T1_A.txt" mylink="aarch32.instrs.VMLA_f.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>advsimd = TRUE;  add = (op == '0');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>sz == '1' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMLA" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMLA_f/T2_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLA_f_T2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMLA" />
          <docvar key="mnemonic-fpdatasize" value="VMLA-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VMLA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMLA_f_T2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMLA" />
          <docvar key="mnemonic-fpdatasize" value="VMLA-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VMLA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMLA_f_T2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMLA" />
          <docvar key="mnemonic-fpdatasize" value="VMLA-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VMLA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_f/T2_A.txt" mylink="aarch32.instrs.VMLA_f.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>advsimd = FALSE; add = (op == '0');</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMLA_f_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_f_A2_H, VMLA_f_T1_Q, VMLA_f_T2_H" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For encoding A2, T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_f_A1_Q, VMLA_f_A2_H, VMLA_f_T1_Q, VMLA_f_T2_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_f_A1_Q, VMLA_f_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VMLA_f_A1_Q, VMLA_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_f_A1_Q, VMLA_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_f_A1_Q, VMLA_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_f_A1_D, VMLA_f_A2_D, VMLA_f_T1_D, VMLA_f_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_f_A1_D, VMLA_f_A2_D, VMLA_f_T1_D, VMLA_f_T2_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_f_A1_D, VMLA_f_A2_D, VMLA_f_T1_D, VMLA_f_T2_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_f_A2_H, VMLA_f_T2_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_f_A2_H, VMLA_f_T2_H" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_f_A2_H, VMLA_f_T2_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMLA_f/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDOrVFPEnabled.2" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDOrVFPEnabled(boolean include_fpexc_check, boolean advsimd)">CheckAdvSIMDOrVFPEnabled</a>(TRUE, advsimd);</line>
<line>    if advsimd then  // Advanced SIMD instruction</line>
<line>        for r = 0 to regs-1</line>
<line>            for e = 0 to elements-1</line>
<line>                product = <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize], <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>                addend = if add then product else <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(product);</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r],e,esize], addend, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>    else             // VFP instruction</line>
<line>        case esize of</line>
<line>            when 16</line>
<line>                addend16 = (if add then <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[])</line>
<line>                            else <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[])));</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]&lt;15:0&gt;, addend16, FPSCR[]);</line>
<line>            when 32</line>
<line>                addend32 = (if add then <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n], <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[])</line>
<line>                            else <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n], <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[])));</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d], addend32, FPSCR[]);</line>
<line>            when 64</line>
<line>                addend64 = (if add then <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n], <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[])</line>
<line>                            else <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n], <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[])));</line>
<line>                <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d], addend64, FPSCR[]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmla_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMLA_i" title="VMLA (integer) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMLA" />
  </docvars>
  <heading>VMLA (integer)</heading>
  <desc>
    <brief>
      <para>Vector Multiply Accumulate (integer)</para>
    </brief>
    <authored>
      <para>Vector Multiply Accumulate multiplies corresponding elements in two vectors, and adds the products to the corresponding elements of the destination vector.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMLA" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMLA_i/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLA_i_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMLA" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMLA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMLA_i_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMLA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMLA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_i/T1A1_A.txt" mylink="aarch32.instrs.VMLA_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>add = (op == '0');  long_destination = FALSE;</line>
<line>unsigned = FALSE;  // "Don't care" value: TRUE produces same functionality</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMLA" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMLA_i/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLA_i_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMLA" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMLA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMLA_i_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMLA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMLA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_i/T1A1_A.txt" mylink="aarch32.instrs.VMLA_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>add = (op == '0');  long_destination = FALSE;</line>
<line>unsigned = FALSE;  // "Don't care" value: TRUE produces same functionality</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMLA_i_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_i_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_i_A1_Q, VMLA_i_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_i_A1_Q, VMLA_i_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">I8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">I16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">I32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VMLA_i_A1_Q, VMLA_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_i_A1_Q, VMLA_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_i_A1_Q, VMLA_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_i_A1_D, VMLA_i_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_i_A1_D, VMLA_i_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_i_A1_D, VMLA_i_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMLA_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            product = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r],e,esize],unsigned) * <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m+r],e,esize],unsigned);</line>
<line>            addend = if add then product else -product;</line>
<line>            if long_destination then</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[d&gt;&gt;1],e,2*esize] + addend;</line>
<line>            else</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r],e,esize] + addend;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmla_s.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMLA_s" title="VMLA (by scalar) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMLA" />
  </docvars>
  <heading>VMLA (by scalar)</heading>
  <desc>
    <brief>
      <para>Vector Multiply Accumulate (by scalar)</para>
    </brief>
    <authored>
      <para>Vector Multiply Accumulate multiplies elements of a vector by a scalar, and adds the products to corresponding elements of the destination vector.</para>
      <para>For more information about scalars see <xref linkend="Cjaibjhd">Advanced SIMD scalars</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check and is operating only on integer vector elements, then the following apply:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMLA" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMLA_s/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLA_s_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMLA" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="24" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMLA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for scalar and the elements of operand vector (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMLA_s_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMLA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="24" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMLA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for scalar and the elements of operand vector (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_s/A1_A.txt" mylink="aarch32.instrs.VMLA_s.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || (F == '1' &amp;&amp; size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = FALSE;  // "Don't care" value: TRUE produces same functionality</line>
<line>add = (op == '0');  floating_point = (F == '1');  long_destination = FALSE;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = if Q == '0' then 1 else 2;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMLA" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMLA_s/T1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLA_s_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMLA" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="28" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMLA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for scalar and the elements of operand vector (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMLA_s_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMLA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="28" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMLA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for scalar and the elements of operand vector (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_s/T1_A.txt" mylink="aarch32.instrs.VMLA_s.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || (F == '1' &amp;&amp; size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = FALSE;  // "Don't care" value: TRUE produces same functionality</line>
<line>add = (op == '0');  floating_point = (F == '1');  long_destination = FALSE;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = if Q == '0' then 1 else 2;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>F == '1' &amp;&amp; size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMLA_s_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_s_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_s_A1_Q, VMLA_s_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_s_A1_Q, VMLA_s_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="F:size">
        <intro>Is the data type for the scalar and the elements of the operand vector, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">F</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">I16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">I32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VMLA_s_A1_Q, VMLA_s_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP register holding the accumulate vector, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_s_A1_Q, VMLA_s_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_s_A1_D, VMLA_s_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP register holding the accumulate vector, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_s_A1_D, VMLA_s_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLA_s_A1_Q, VMLA_s_T1_Q" symboldefcount="1">
      <symbol link="sa_dm_x">&lt;Dm[x]&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register holding the scalar. If <syntax>&lt;dt&gt;</syntax> is <value>I16</value> or <value>F16</value>, <syntax>Dm</syntax> is restricted to D0-D7. <syntax>Dm</syntax> is encoded in "Vm&lt;2:0&gt;", and <syntax>x</syntax> is encoded in "M:Vm&lt;3&gt;". If <syntax>&lt;dt&gt;</syntax> is <value>I32</value> or <value>F32</value>, <syntax>Dm</syntax> is restricted to D0-D15. <syntax>Dm</syntax> is encoded in "Vm", and <syntax>x</syntax> is encoded in "M".</para>
        </intro>
      </account>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMLA_s/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m],index,esize];  op2val = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op2, unsigned);</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r],e,esize];  op1val = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op1, unsigned);</line>
<line>            if floating_point then</line>
<line>                fp_addend = (if add then <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(op1,op2,<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>())</line>
<line>                             else <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(op1,op2,<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>())));</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r],e,esize], fp_addend,</line>
<line>                                             <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            else</line>
<line>                addend = if add then op1val*op2val else -op1val*op2val;</line>
<line>                if long_destination then</line>
<line>                    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[d&gt;&gt;1],e,2*esize] + addend;</line>
<line>                else</line>
<line>                    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r],e,esize] + addend;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmlal_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMLAL_i" title="VMLAL (integer) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMLAL" />
  </docvars>
  <heading>VMLAL (integer)</heading>
  <desc>
    <brief>
      <para>Vector Multiply Accumulate Long (integer)</para>
    </brief>
    <authored>
      <para>Vector Multiply Accumulate Long multiplies corresponding elements in two vectors, and add the products to the corresponding element of the destination vector. The destination vector element is twice as long as the elements that are multiplied.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMLAL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMLA_i/T2A2_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLAL_i_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMLAL" />
        </docvars>
        <asmtemplate><text>VMLAL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_i/T2A2_A.txt" mylink="aarch32.instrs.VMLA_i.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>add = (op == '0');  long_destination = TRUE;  unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMLAL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMLA_i/T2A2_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLAL_i_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMLAL" />
        </docvars>
        <asmtemplate><text>VMLAL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_i/T2A2_A.txt" mylink="aarch32.instrs.VMLA_i.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>add = (op == '0');  long_destination = TRUE;  unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMLAL_i_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLAL_i_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLAL_i_A1, VMLAL_i_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLAL_i_A1, VMLAL_i_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VMLAL_i_A1, VMLAL_i_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLAL_i_A1, VMLAL_i_T1" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLAL_i_A1, VMLAL_i_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMLA_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            product = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r],e,esize],unsigned) * <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m+r],e,esize],unsigned);</line>
<line>            addend = if add then product else -product;</line>
<line>            if long_destination then</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[d&gt;&gt;1],e,2*esize] + addend;</line>
<line>            else</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r],e,esize] + addend;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmlal_s.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMLAL_s" title="VMLAL (by scalar) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMLAL" />
  </docvars>
  <heading>VMLAL (by scalar)</heading>
  <desc>
    <brief>
      <para>Vector Multiply Accumulate Long (by scalar)</para>
    </brief>
    <authored>
      <para>Vector Multiply Accumulate Long multiplies elements of a vector by a scalar, and adds the products to corresponding elements of the destination vector. The destination vector elements are twice as long as the elements that are multiplied.</para>
      <para>For more information about scalars see <xref linkend="Cjaibjhd">Advanced SIMD scalars</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMLAL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMLA_s/T2A2_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLAL_s_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMLAL" />
        </docvars>
        <asmtemplate><text>VMLAL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for scalar and the elements of operand vector (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_s/T2A2_A.txt" mylink="aarch32.instrs.VMLA_s.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>unsigned = (U == '1');  add = (op == '0');  floating_point = FALSE;  long_destination = TRUE;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = 1;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMLAL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMLA_s/T2A2_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLAL_s_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMLAL" />
        </docvars>
        <asmtemplate><text>VMLAL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for scalar and the elements of operand vector (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_s/T2A2_A.txt" mylink="aarch32.instrs.VMLA_s.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>unsigned = (U == '1');  add = (op == '0');  floating_point = FALSE;  long_destination = TRUE;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = 1;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMLAL_s_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLAL_s_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLAL_s_A1, VMLAL_s_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLAL_s_A1, VMLAL_s_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the scalar and the elements of the operand vector, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VMLAL_s_A1, VMLAL_s_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP register holding the accumulate vector, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLAL_s_A1, VMLAL_s_T1" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLAL_s_A1, VMLAL_s_T1" symboldefcount="1">
      <symbol link="sa_dm_x">&lt;Dm[x]&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register holding the scalar. If <syntax>&lt;dt&gt;</syntax> is <value>S16</value> or <value>U16</value>, <syntax>Dm</syntax> is restricted to D0-D7. <syntax>Dm</syntax> is encoded in "Vm&lt;2:0&gt;", and <syntax>x</syntax> is encoded in "M:Vm&lt;3&gt;". If <syntax>&lt;dt&gt;</syntax> is <value>S32</value> or <value>U32</value>, <syntax>Dm</syntax> is restricted to D0-D15. <syntax>Dm</syntax> is encoded in "Vm", and <syntax>x</syntax> is encoded in "M".</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMLA_s/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m],index,esize];  op2val = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op2, unsigned);</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r],e,esize];  op1val = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op1, unsigned);</line>
<line>            if floating_point then</line>
<line>                fp_addend = (if add then <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(op1,op2,<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>())</line>
<line>                             else <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(op1,op2,<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>())));</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r],e,esize], fp_addend,</line>
<line>                                             <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            else</line>
<line>                addend = if add then op1val*op2val else -op1val*op2val;</line>
<line>                if long_destination then</line>
<line>                    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[d&gt;&gt;1],e,2*esize] + addend;</line>
<line>                else</line>
<line>                    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r],e,esize] + addend;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmls_f.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMLS_f" title="VMLS (floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMLS" />
  </docvars>
  <heading>VMLS (floating-point)</heading>
  <desc>
    <brief>
      <para>Vector Multiply Subtract (floating-point)</para>
    </brief>
    <authored>
      <para>Vector Multiply Subtract multiplies corresponding elements in two vectors, subtracts the products from corresponding elements of the destination vector, and places the results in the destination vector.</para>
      <note>
        <para>Arm recommends that software does not use the <instruction>VMLS</instruction> instruction in the Round towards Plus Infinity and Round towards Minus Infinity rounding modes, because the rounding of the product and of the sum can change the result of the instruction in opposite directions, defeating the purpose of these rounding modes.</para>
      </note>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMLS" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMLA_f/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLS_f_A1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMLS" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMLS</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMLS_f_A1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMLS" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMLS</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_f/A1_A.txt" mylink="aarch32.instrs.VMLA_f.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>advsimd = TRUE;  add = (op == '0');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMLS" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMLA_f/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLS_f_A2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMLS" />
          <docvar key="mnemonic-fpdatasize" value="VMLS-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VMLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMLS_f_A2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMLS" />
          <docvar key="mnemonic-fpdatasize" value="VMLS-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VMLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMLS_f_A2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMLS" />
          <docvar key="mnemonic-fpdatasize" value="VMLS-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VMLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_f/A2_A.txt" mylink="aarch32.instrs.VMLA_f.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>advsimd = FALSE; add = (op == '0');</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMLS" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMLA_f/T1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLS_f_T1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMLS" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMLS_f_T1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMLS" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_f/T1_A.txt" mylink="aarch32.instrs.VMLA_f.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>advsimd = TRUE;  add = (op == '0');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>sz == '1' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMLS" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMLA_f/T2_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLS_f_T2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMLS" />
          <docvar key="mnemonic-fpdatasize" value="VMLS-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VMLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMLS_f_T2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMLS" />
          <docvar key="mnemonic-fpdatasize" value="VMLS-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VMLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMLS_f_T2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMLS" />
          <docvar key="mnemonic-fpdatasize" value="VMLS-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VMLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_f/T2_A.txt" mylink="aarch32.instrs.VMLA_f.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>advsimd = FALSE; add = (op == '0');</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMLS_f_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_f_A2_H, VMLS_f_T1_Q, VMLS_f_T2_H" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For encoding A2, T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_f_A1_Q, VMLS_f_A2_H, VMLS_f_T1_Q, VMLS_f_T2_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_f_A1_Q, VMLS_f_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VMLS_f_A1_Q, VMLS_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_f_A1_Q, VMLS_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_f_A1_Q, VMLS_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_f_A1_D, VMLS_f_A2_D, VMLS_f_T1_D, VMLS_f_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_f_A1_D, VMLS_f_A2_D, VMLS_f_T1_D, VMLS_f_T2_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_f_A1_D, VMLS_f_A2_D, VMLS_f_T1_D, VMLS_f_T2_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_f_A2_H, VMLS_f_T2_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_f_A2_H, VMLS_f_T2_H" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_f_A2_H, VMLS_f_T2_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMLA_f/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDOrVFPEnabled.2" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDOrVFPEnabled(boolean include_fpexc_check, boolean advsimd)">CheckAdvSIMDOrVFPEnabled</a>(TRUE, advsimd);</line>
<line>    if advsimd then  // Advanced SIMD instruction</line>
<line>        for r = 0 to regs-1</line>
<line>            for e = 0 to elements-1</line>
<line>                product = <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize], <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>                addend = if add then product else <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(product);</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r],e,esize], addend, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>    else             // VFP instruction</line>
<line>        case esize of</line>
<line>            when 16</line>
<line>                addend16 = (if add then <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[])</line>
<line>                            else <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[])));</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]&lt;15:0&gt;, addend16, FPSCR[]);</line>
<line>            when 32</line>
<line>                addend32 = (if add then <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n], <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[])</line>
<line>                            else <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n], <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[])));</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d], addend32, FPSCR[]);</line>
<line>            when 64</line>
<line>                addend64 = (if add then <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n], <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[])</line>
<line>                            else <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n], <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[])));</line>
<line>                <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d], addend64, FPSCR[]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmls_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMLS_i" title="VMLS (integer) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMLS" />
  </docvars>
  <heading>VMLS (integer)</heading>
  <desc>
    <brief>
      <para>Vector Multiply Subtract (integer)</para>
    </brief>
    <authored>
      <para>Vector Multiply Subtract multiplies corresponding elements in two vectors, and subtracts the products from the corresponding elements of the destination vector.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMLS" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMLA_i/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLS_i_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMLS" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMLS</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMLS_i_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMLS" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMLS</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_i/T1A1_A.txt" mylink="aarch32.instrs.VMLA_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>add = (op == '0');  long_destination = FALSE;</line>
<line>unsigned = FALSE;  // "Don't care" value: TRUE produces same functionality</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMLS" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMLA_i/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLS_i_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMLS" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMLS_i_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMLS" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_i/T1A1_A.txt" mylink="aarch32.instrs.VMLA_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>add = (op == '0');  long_destination = FALSE;</line>
<line>unsigned = FALSE;  // "Don't care" value: TRUE produces same functionality</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMLS_i_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_i_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_i_A1_Q, VMLS_i_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_i_A1_Q, VMLS_i_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">I8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">I16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">I32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VMLS_i_A1_Q, VMLS_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_i_A1_Q, VMLS_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_i_A1_Q, VMLS_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_i_A1_D, VMLS_i_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_i_A1_D, VMLS_i_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_i_A1_D, VMLS_i_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMLA_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            product = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r],e,esize],unsigned) * <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m+r],e,esize],unsigned);</line>
<line>            addend = if add then product else -product;</line>
<line>            if long_destination then</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[d&gt;&gt;1],e,2*esize] + addend;</line>
<line>            else</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r],e,esize] + addend;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmls_s.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMLS_s" title="VMLS (by scalar) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMLS" />
  </docvars>
  <heading>VMLS (by scalar)</heading>
  <desc>
    <brief>
      <para>Vector Multiply Subtract (by scalar)</para>
    </brief>
    <authored>
      <para>Vector Multiply Subtract multiplies elements of a vector by a scalar, and either subtracts the products from corresponding elements of the destination vector.</para>
      <para>For more information about scalars see <xref linkend="Cjaibjhd">Advanced SIMD scalars</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check and is operating only on integer vector elements, then the following apply:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMLS" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMLA_s/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLS_s_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMLS" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="24" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMLS</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for scalar and the elements of operand vector (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMLS_s_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMLS" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="24" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMLS</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for scalar and the elements of operand vector (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_s/A1_A.txt" mylink="aarch32.instrs.VMLA_s.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || (F == '1' &amp;&amp; size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = FALSE;  // "Don't care" value: TRUE produces same functionality</line>
<line>add = (op == '0');  floating_point = (F == '1');  long_destination = FALSE;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = if Q == '0' then 1 else 2;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMLS" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMLA_s/T1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLS_s_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMLS" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="28" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for scalar and the elements of operand vector (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMLS_s_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMLS" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="28" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for scalar and the elements of operand vector (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_s/T1_A.txt" mylink="aarch32.instrs.VMLA_s.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || (F == '1' &amp;&amp; size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = FALSE;  // "Don't care" value: TRUE produces same functionality</line>
<line>add = (op == '0');  floating_point = (F == '1');  long_destination = FALSE;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = if Q == '0' then 1 else 2;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>F == '1' &amp;&amp; size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMLS_s_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_s_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_s_A1_Q, VMLS_s_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_s_A1_Q, VMLS_s_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="F:size">
        <intro>Is the data type for the scalar and the elements of the operand vector, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">F</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">I16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">I32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VMLS_s_A1_Q, VMLS_s_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP register holding the accumulate vector, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_s_A1_Q, VMLS_s_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_s_A1_D, VMLS_s_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP register holding the accumulate vector, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_s_A1_D, VMLS_s_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLS_s_A1_Q, VMLS_s_T1_Q" symboldefcount="1">
      <symbol link="sa_dm_x">&lt;Dm[x]&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register holding the scalar. If <syntax>&lt;dt&gt;</syntax> is <value>I16</value> or <value>F16</value>, <syntax>Dm</syntax> is restricted to D0-D7. <syntax>Dm</syntax> is encoded in "Vm&lt;2:0&gt;", and <syntax>x</syntax> is encoded in "M:Vm&lt;3&gt;". If <syntax>&lt;dt&gt;</syntax> is <value>I32</value> or <value>F32</value>, <syntax>Dm</syntax> is restricted to D0-D15. <syntax>Dm</syntax> is encoded in "Vm", and <syntax>x</syntax> is encoded in "M".</para>
        </intro>
      </account>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMLA_s/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m],index,esize];  op2val = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op2, unsigned);</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r],e,esize];  op1val = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op1, unsigned);</line>
<line>            if floating_point then</line>
<line>                fp_addend = (if add then <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(op1,op2,<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>())</line>
<line>                             else <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(op1,op2,<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>())));</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r],e,esize], fp_addend,</line>
<line>                                             <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            else</line>
<line>                addend = if add then op1val*op2val else -op1val*op2val;</line>
<line>                if long_destination then</line>
<line>                    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[d&gt;&gt;1],e,2*esize] + addend;</line>
<line>                else</line>
<line>                    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r],e,esize] + addend;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmlsl_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMLSL_i" title="VMLSL (integer) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMLSL" />
  </docvars>
  <heading>VMLSL (integer)</heading>
  <desc>
    <brief>
      <para>Vector Multiply Subtract Long (integer)</para>
    </brief>
    <authored>
      <para>Vector Multiply Subtract Long multiplies corresponding elements in two vectors, and subtract the products from the corresponding elements of the destination vector. The destination vector element is twice as long as the elements that are multiplied.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMLSL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMLA_i/T2A2_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLSL_i_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMLSL" />
        </docvars>
        <asmtemplate><text>VMLSL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_i/T2A2_A.txt" mylink="aarch32.instrs.VMLA_i.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>add = (op == '0');  long_destination = TRUE;  unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMLSL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMLA_i/T2A2_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLSL_i_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMLSL" />
        </docvars>
        <asmtemplate><text>VMLSL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_i/T2A2_A.txt" mylink="aarch32.instrs.VMLA_i.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>add = (op == '0');  long_destination = TRUE;  unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMLSL_i_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLSL_i_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLSL_i_A1, VMLSL_i_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLSL_i_A1, VMLSL_i_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VMLSL_i_A1, VMLSL_i_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLSL_i_A1, VMLSL_i_T1" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLSL_i_A1, VMLSL_i_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMLA_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            product = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r],e,esize],unsigned) * <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m+r],e,esize],unsigned);</line>
<line>            addend = if add then product else -product;</line>
<line>            if long_destination then</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[d&gt;&gt;1],e,2*esize] + addend;</line>
<line>            else</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r],e,esize] + addend;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmlsl_s.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMLSL_s" title="VMLSL (by scalar) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMLSL" />
  </docvars>
  <heading>VMLSL (by scalar)</heading>
  <desc>
    <brief>
      <para>Vector Multiply Subtract Long (by scalar)</para>
    </brief>
    <authored>
      <para>Vector Multiply Subtract Long multiplies elements of a vector by a scalar, and subtracts the products from corresponding elements of the destination vector. The destination vector elements are twice as long as the elements that are multiplied.</para>
      <para>For more information about scalars see <xref linkend="Cjaibjhd">Advanced SIMD scalars</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMLSL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMLA_s/T2A2_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLSL_s_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMLSL" />
        </docvars>
        <asmtemplate><text>VMLSL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for scalar and the elements of operand vector (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_s/T2A2_A.txt" mylink="aarch32.instrs.VMLA_s.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>unsigned = (U == '1');  add = (op == '0');  floating_point = FALSE;  long_destination = TRUE;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = 1;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMLSL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMLA_s/T2A2_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMLSL_s_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMLSL" />
        </docvars>
        <asmtemplate><text>VMLSL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for scalar and the elements of operand vector (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMLA_s/T2A2_A.txt" mylink="aarch32.instrs.VMLA_s.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>unsigned = (U == '1');  add = (op == '0');  floating_point = FALSE;  long_destination = TRUE;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = 1;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMLSL_s_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLSL_s_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLSL_s_A1, VMLSL_s_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLSL_s_A1, VMLSL_s_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the scalar and the elements of the operand vector, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VMLSL_s_A1, VMLSL_s_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP register holding the accumulate vector, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLSL_s_A1, VMLSL_s_T1" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMLSL_s_A1, VMLSL_s_T1" symboldefcount="1">
      <symbol link="sa_dm_x">&lt;Dm[x]&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register holding the scalar. If <syntax>&lt;dt&gt;</syntax> is <value>S16</value> or <value>U16</value>, <syntax>Dm</syntax> is restricted to D0-D7. <syntax>Dm</syntax> is encoded in "Vm&lt;2:0&gt;", and <syntax>x</syntax> is encoded in "M:Vm&lt;3&gt;". If <syntax>&lt;dt&gt;</syntax> is <value>S32</value> or <value>U32</value>, <syntax>Dm</syntax> is restricted to D0-D15. <syntax>Dm</syntax> is encoded in "Vm", and <syntax>x</syntax> is encoded in "M".</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMLA_s/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m],index,esize];  op2val = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op2, unsigned);</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r],e,esize];  op1val = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op1, unsigned);</line>
<line>            if floating_point then</line>
<line>                fp_addend = (if add then <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(op1,op2,<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>())</line>
<line>                             else <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(op1,op2,<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>())));</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r],e,esize], fp_addend,</line>
<line>                                             <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            else</line>
<line>                addend = if add then op1val*op2val else -op1val*op2val;</line>
<line>                if long_destination then</line>
<line>                    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[d&gt;&gt;1],e,2*esize] + addend;</line>
<line>                else</line>
<line>                    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r],e,esize] + addend;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmmla.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMMLA" title="VMMLA -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMMLA" />
    <docvar key="simdvectorsize" value="quad" />
  </docvars>
  <heading>VMMLA</heading>
  <desc>
    <brief>
      <para>BFloat16 floating-point matrix multiply-accumulate</para>
    </brief>
    <authored>
      <para>BFloat16 floating-point matrix multiply-accumulate. This instruction multiplies the 2x4 matrix of BF16 values in the first 128-bit source vector by the 4x2 BF16 matrix in the second 128-bit source vector. The resulting 2x2 single-precision matrix product is then added destructively to the 2x2 single-precision matrix in the 128-bit destination vector. This is equivalent to performing a 4-way dot product per destination element. The instruction does not update the <xref linkend="AArch32.fpscr">FPSCR</xref> exception status.</para>
      <note>
        <para>Arm expects that the VMMLA instruction will deliver a peak BF16 multiply throughput that is at least as high as can be achieved using two VDOT instructions, with a goal that it should have significantly higher throughput.</para>
      </note>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMMLA" />
        <docvar key="simdvectorsize" value="quad" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VMMLA/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="op1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMMLA_A1_Q" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMMLA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <asmtemplate><text>VMMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMMLA/A1_A.txt" mylink="aarch32.instrs.VMMLA.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>integer regs = 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMMLA" />
        <docvar key="simdvectorsize" value="quad" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VMMLA/T1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="op1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMMLA_T1_Q" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMMLA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <asmtemplate><text>VMMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMMLA/T1_A.txt" mylink="aarch32.instrs.VMMLA.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>integer regs = 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMMLA_A1_Q, VMMLA_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMMLA_A1_Q, VMMLA_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMMLA_A1_Q, VMMLA_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMMLA_A1_Q, VMMLA_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMMLA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>bits(128) op1 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[n&gt;&gt;1];</line>
<line>bits(128) op2 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1];</line>
<line>bits(128) acc = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[d&gt;&gt;1];</line>
<line></line>
<line><a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = <a link="impl-shared.BFMatMulAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) BFMatMulAdd(bits(N) addend, bits(N) op1, bits(N) op2)">BFMatMulAdd</a>(acc, op1, op2);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmov_d.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMOV_d" title="VMOV (between two general-purpose registers and a doubleword floating-point register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMOV" />
  </docvars>
  <heading>VMOV (between two general-purpose registers and a doubleword floating-point register)</heading>
  <desc>
    <brief>
      <para>Copy two general-purpose registers to or from a SIMD&amp;FP register</para>
    </brief>
    <authored>
      <para>Copy two general-purpose registers to or from a SIMD&amp;FP register copies two words from two general-purpose registers into a doubleword register in the Advanced SIMD and floating-point register file, or from a doubleword register in the Advanced SIMD and floating-point register file to two general-purpose registers.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGGHFHD">VMOV (between two general-purpose registers and a doubleword floating-point register)</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMOV_d/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rt2" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="2" name="opc2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o3" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOV_tod_A1" oneofinclass="2" oneof="4" label="From general-purpose registers" bitdiffs="op == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="to-or-from-gp" value="from-gps" />
        </docvars>
        <box hibit="20" width="1" name="op">
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP register to be transferred (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_rt" hover="First general-purpose register that {syntax{&lt;Dm&gt;}}[31:0] will be transferred to or from (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register that {syntax{&lt;Dm&gt;}}[63:32] will be transferred to or from (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_d_A1" oneofinclass="2" oneof="4" label="To general-purpose registers" bitdiffs="op == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="to-or-from-gp" value="to-gps" />
        </docvars>
        <box hibit="20" width="1" name="op">
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register that {syntax{&lt;Dm&gt;}}[31:0] will be transferred to or from (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register that {syntax{&lt;Dm&gt;}}[63:32] will be transferred to or from (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP register to be transferred (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_d/T1A1_A.txt" mylink="aarch32.instrs.VMOV_d.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>to_arm_registers = (op == '1');  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>if t == 15 || t2 == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
<line>if to_arm_registers &amp;&amp; t == t2 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>to_arm_registers &amp;&amp; t == t2</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMOV_d/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rt2" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="2" name="opc2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o3" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOV_tod_T1" oneofinclass="2" oneof="4" label="From general-purpose registers" bitdiffs="op == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="to-or-from-gp" value="from-gps" />
        </docvars>
        <box hibit="20" width="1" name="op">
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP register to be transferred (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_rt" hover="First general-purpose register that {syntax{&lt;Dm&gt;}}[31:0] will be transferred to or from (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register that {syntax{&lt;Dm&gt;}}[63:32] will be transferred to or from (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_d_T1" oneofinclass="2" oneof="4" label="To general-purpose registers" bitdiffs="op == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="to-or-from-gp" value="to-gps" />
        </docvars>
        <box hibit="20" width="1" name="op">
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register that {syntax{&lt;Dm&gt;}}[31:0] will be transferred to or from (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register that {syntax{&lt;Dm&gt;}}[63:32] will be transferred to or from (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP register to be transferred (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_d/T1A1_A.txt" mylink="aarch32.instrs.VMOV_d.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>to_arm_registers = (op == '1');  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>if t == 15 || t2 == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
<line>if to_arm_registers &amp;&amp; t == t2 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>to_arm_registers &amp;&amp; t == t2</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMOV_d_A1, VMOV_d_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP register to be transferred, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_d_A1, VMOV_d_T1" symboldefcount="1">
      <symbol link="sa_rt2">&lt;Rt2&gt;</symbol>
      <account encodedin="Rt2">
        <intro>
          <para>Is the second general-purpose register that <syntax>&lt;Dm&gt;</syntax>[63:32] will be transferred to or from, encoded in the "Rt2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_d_A1, VMOV_d_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the first general-purpose register that <syntax>&lt;Dm&gt;</syntax>[31:0] will be transferred to or from, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_d_A1, VMOV_d_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_d_A1, VMOV_d_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMOV_d/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    if to_arm_registers then</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m]&lt;31:0&gt;;</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t2] = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m]&lt;63:32&gt;;</line>
<line>    else</line>
<line>        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[m]&lt;31:0&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];</line>
<line>        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[m]&lt;63:32&gt; = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t2];</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmov_h.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMOV_h" title="VMOV (between general-purpose register and half-precision) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMOV" />
  </docvars>
  <heading>VMOV (between general-purpose register and half-precision)</heading>
  <desc>
    <brief>
      <para>Copy 16 bits of a general-purpose register to or from a 32-bit SIMD&amp;FP register</para>
    </brief>
    <authored>
      <para>Copy 16 bits of a general-purpose register to or from a 32-bit SIMD&amp;FP register.  This instruction transfers the value held in the bottom 16 bits of a 32-bit SIMD&amp;FP register to the bottom 16 bits of a general-purpose register, or the value held in the bottom 16 bits of a general-purpose register to the bottom 16 bits of a 32-bit SIMD&amp;FP register.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VMOV_h/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="VMOV_toh_A1" oneofinclass="2" oneof="4" label="From general-purpose register" bitdiffs="op == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="to-or-from-gp" value="from-gp" />
        </docvars>
        <box hibit="20" width="1" name="op">
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sn" hover="32-bit SIMD&amp;FP register to be transferred (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register that {syntax{&lt;Sn&gt;}} will be transferred to or from (field &quot;Rt&quot;)">&lt;Rt&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_h_A1" oneofinclass="2" oneof="4" label="To general-purpose register" bitdiffs="op == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="to-or-from-gp" value="to-gp" />
        </docvars>
        <box hibit="20" width="1" name="op">
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_rt" hover="General-purpose register that {syntax{&lt;Sn&gt;}} will be transferred to or from (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_sn" hover="32-bit SIMD&amp;FP register to be transferred (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_h/A1_A.txt" mylink="aarch32.instrs.VMOV_h.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if cond != '1110' then UNPREDICTABLE;</line>
<line>to_arm_register = (op == '1');  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N);</line>
<line>if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VMOV_h/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="VMOV_toh_T1" oneofinclass="2" oneof="4" label="From general-purpose register" bitdiffs="op == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="to-or-from-gp" value="from-gp" />
        </docvars>
        <box hibit="20" width="1" name="op">
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sn" hover="32-bit SIMD&amp;FP register to be transferred (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register that {syntax{&lt;Sn&gt;}} will be transferred to or from (field &quot;Rt&quot;)">&lt;Rt&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_h_T1" oneofinclass="2" oneof="4" label="To general-purpose register" bitdiffs="op == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="to-or-from-gp" value="to-gp" />
        </docvars>
        <box hibit="20" width="1" name="op">
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_rt" hover="General-purpose register that {syntax{&lt;Sn&gt;}} will be transferred to or from (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_sn" hover="32-bit SIMD&amp;FP register to be transferred (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_h/T1_A.txt" mylink="aarch32.instrs.VMOV_h.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>to_arm_register = (op == '1');  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N);</line>
<line>if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMOV_h_A1, VMOV_toh_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register that <syntax>&lt;Sn&gt;</syntax> will be transferred to or from, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_h_A1, VMOV_toh_T1" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP register to be transferred, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_h_A1, VMOV_toh_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_h_A1, VMOV_toh_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMOV_h/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    if to_arm_register then</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;;</line>
<line>    else</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[n] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]&lt;15:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmov_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMOV_i" title="VMOV (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMOV" />
  </docvars>
  <heading>VMOV (immediate)</heading>
  <desc>
    <brief>
      <para>Copy immediate value to a SIMD&amp;FP register</para>
    </brief>
    <authored>
      <para>Copy immediate value to a SIMD&amp;FP register places an immediate constant into every element of the destination register.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode.  For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_1r_imm">Advanced SIMD one register and modified immediate</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd1reg_imm">Advanced SIMD one register and modified immediate</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="10">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>, </txt>
      <a href="#iclass_a2">A2</a>
      <txt>, </txt>
      <a href="#iclass_a3">A3</a>
      <txt>, </txt>
      <a href="#iclass_a4">A4</a>
      <txt> and </txt>
      <a href="#iclass_a5">A5</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt>, </txt>
      <a href="#iclass_t3">T3</a>
      <txt>, </txt>
      <a href="#iclass_t4">T4</a>
      <txt> and </txt>
      <a href="#iclass_t5">T5</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="10" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMOV_i/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="2">
          <c>0</c>
          <c>x</c>
          <c>x</c>
          <c>0</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOV_i_A1_D" oneofinclass="2" oneof="22" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_i_A1_Q" oneofinclass="2" oneof="22" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_i/T1A1_A.txt" mylink="aarch32.instrs.VMOV_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if op == '0' &amp;&amp; cmode&lt;0&gt; == '1' &amp;&amp; cmode&lt;3:2&gt; != '11' then SEE "VORR (immediate)";</line>
<line>if op == '1' &amp;&amp; cmode != '1110' then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>single_register = FALSE;  advsimd = TRUE;  imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>(op, cmode, i:imm3:imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="10" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMOV_i/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="imm4H" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="imm4L" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOV_i_A2_H" oneofinclass="3" oneof="22" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="mnemonic-fpdatasize" value="VMOV-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, #</text><a link="sa_imm_1" hover="Signed floating-point constant with 3-bit exponent and normalized 4 bits of precision (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_i_A2_S" oneofinclass="3" oneof="22" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="mnemonic-fpdatasize" value="VMOV-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, #</text><a link="sa_imm_1" hover="Signed floating-point constant with 3-bit exponent and normalized 4 bits of precision (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_i_A2_D" oneofinclass="3" oneof="22" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="mnemonic-fpdatasize" value="VMOV-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm_1" hover="Signed floating-point constant with 3-bit exponent and normalized 4 bits of precision (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_i/A2_A.txt" mylink="aarch32.instrs.VMOV_i.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>single_register = (size != '11'); advsimd = FALSE;</line>
<line>bits(16) imm16;</line>
<line>bits(32) imm32;</line>
<line>bits(64) imm64;</line>
<line>integer d;</line>
<line>integer regs;</line>
<line>case size of</line>
<line>    when '01' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);  imm16 = <a link="impl-shared.VFPExpandImm.2" file="shared_pseudocode.xml" hover="function: bits(N) VFPExpandImm(bits(8) imm8, integer N)">VFPExpandImm</a>(imm4H:imm4L, 16); imm32 = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : imm16;</line>
<line>    when '10' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);  imm32 = <a link="impl-shared.VFPExpandImm.2" file="shared_pseudocode.xml" hover="function: bits(N) VFPExpandImm(bits(8) imm8, integer N)">VFPExpandImm</a>(imm4H:imm4L, 32);</line>
<line>    when '11' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  imm64 = <a link="impl-shared.VFPExpandImm.2" file="shared_pseudocode.xml" hover="function: bits(N) VFPExpandImm(bits(8) imm8, integer N)">VFPExpandImm</a>(imm4H:imm4L, 64);  regs = 1;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A3" oneof="10" id="iclass_a3" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMOV_i/T3A3_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>x</c>
          <c>0</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOV_i_A3_D" oneofinclass="2" oneof="22" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_i_A3_Q" oneofinclass="2" oneof="22" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_i/T3A3_A.txt" mylink="aarch32.instrs.VMOV_i.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if op == '0' &amp;&amp; cmode&lt;0&gt; == '1' &amp;&amp; cmode&lt;3:2&gt; != '11' then SEE "VORR (immediate)";</line>
<line>if op == '1' &amp;&amp; cmode != '1110' then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>single_register = FALSE;  advsimd = TRUE;  imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>(op, cmode, i:imm3:imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A4" oneof="10" id="iclass_a4" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A4" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMOV_i/T4A4_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="2">
          <c>1</c>
          <c>1</c>
          <c>x</c>
          <c>x</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOV_i_A4_D" oneofinclass="2" oneof="22" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A4" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="The data type (field &quot;cmode&quot;) [F32,I8,I32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_i_A4_Q" oneofinclass="2" oneof="22" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A4" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="The data type (field &quot;cmode&quot;) [F32,I8,I32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_i/T4A4_A.txt" mylink="aarch32.instrs.VMOV_i.T4A4_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if op == '0' &amp;&amp; cmode&lt;0&gt; == '1' &amp;&amp; cmode&lt;3:2&gt; != '11' then SEE "VORR (immediate)";</line>
<line>if op == '1' &amp;&amp; cmode != '1110' then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>single_register = FALSE;  advsimd = TRUE;  imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>(op, cmode, i:imm3:imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A5" oneof="10" id="iclass_a5" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A5" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMOV_i/T5A5_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOV_i_A5_D" oneofinclass="2" oneof="22" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A5" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_i_A5_Q" oneofinclass="2" oneof="22" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A5" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I64 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_i/T5A5_A.txt" mylink="aarch32.instrs.VMOV_i.T5A5_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if op == '0' &amp;&amp; cmode&lt;0&gt; == '1' &amp;&amp; cmode&lt;3:2&gt; != '11' then SEE "VORR (immediate)";</line>
<line>if op == '1' &amp;&amp; cmode != '1110' then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>single_register = FALSE;  advsimd = TRUE;  imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>(op, cmode, i:imm3:imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="10" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMOV_i/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="2">
          <c>0</c>
          <c>x</c>
          <c>x</c>
          <c>0</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOV_i_T1_D" oneofinclass="2" oneof="22" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_i_T1_Q" oneofinclass="2" oneof="22" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_i/T1A1_A.txt" mylink="aarch32.instrs.VMOV_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if op == '0' &amp;&amp; cmode&lt;0&gt; == '1' &amp;&amp; cmode&lt;3:2&gt; != '11' then SEE "VORR (immediate)";</line>
<line>if op == '1' &amp;&amp; cmode != '1110' then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>single_register = FALSE;  advsimd = TRUE;  imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>(op, cmode, i:imm3:imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="10" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMOV_i/T2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="imm4H" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="imm4L" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOV_i_T2_H" oneofinclass="3" oneof="22" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="mnemonic-fpdatasize" value="VMOV-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, #</text><a link="sa_imm_1" hover="Signed floating-point constant with 3-bit exponent and normalized 4 bits of precision (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_i_T2_S" oneofinclass="3" oneof="22" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="mnemonic-fpdatasize" value="VMOV-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, #</text><a link="sa_imm_1" hover="Signed floating-point constant with 3-bit exponent and normalized 4 bits of precision (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_i_T2_D" oneofinclass="3" oneof="22" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="mnemonic-fpdatasize" value="VMOV-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm_1" hover="Signed floating-point constant with 3-bit exponent and normalized 4 bits of precision (field &quot;imm4H:imm4L&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_i/T2_A.txt" mylink="aarch32.instrs.VMOV_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>single_register = (size != '11'); advsimd = FALSE;</line>
<line>bits(16) imm16;</line>
<line>bits(32) imm32;</line>
<line>bits(64) imm64;</line>
<line>integer d;</line>
<line>integer regs;</line>
<line>case size of</line>
<line>    when '01' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);  imm16 = <a link="impl-shared.VFPExpandImm.2" file="shared_pseudocode.xml" hover="function: bits(N) VFPExpandImm(bits(8) imm8, integer N)">VFPExpandImm</a>(imm4H:imm4L, 16); imm32 = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : imm16;</line>
<line>    when '10' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);  imm32 = <a link="impl-shared.VFPExpandImm.2" file="shared_pseudocode.xml" hover="function: bits(N) VFPExpandImm(bits(8) imm8, integer N)">VFPExpandImm</a>(imm4H:imm4L, 32);</line>
<line>    when '11' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  imm64 = <a link="impl-shared.VFPExpandImm.2" file="shared_pseudocode.xml" hover="function: bits(N) VFPExpandImm(bits(8) imm8, integer N)">VFPExpandImm</a>(imm4H:imm4L, 64);  regs = 1;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T3" oneof="10" id="iclass_t3" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMOV_i/T3A3_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>x</c>
          <c>0</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOV_i_T3_D" oneofinclass="2" oneof="22" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_i_T3_Q" oneofinclass="2" oneof="22" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_i/T3A3_A.txt" mylink="aarch32.instrs.VMOV_i.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if op == '0' &amp;&amp; cmode&lt;0&gt; == '1' &amp;&amp; cmode&lt;3:2&gt; != '11' then SEE "VORR (immediate)";</line>
<line>if op == '1' &amp;&amp; cmode != '1110' then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>single_register = FALSE;  advsimd = TRUE;  imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>(op, cmode, i:imm3:imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T4" oneof="10" id="iclass_t4" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T4" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMOV_i/T4A4_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="2">
          <c>1</c>
          <c>1</c>
          <c>x</c>
          <c>x</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOV_i_T4_D" oneofinclass="2" oneof="22" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="The data type (field &quot;cmode&quot;) [F32,I8,I32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_i_T4_Q" oneofinclass="2" oneof="22" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="The data type (field &quot;cmode&quot;) [F32,I8,I32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_i/T4A4_A.txt" mylink="aarch32.instrs.VMOV_i.T4A4_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if op == '0' &amp;&amp; cmode&lt;0&gt; == '1' &amp;&amp; cmode&lt;3:2&gt; != '11' then SEE "VORR (immediate)";</line>
<line>if op == '1' &amp;&amp; cmode != '1110' then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>single_register = FALSE;  advsimd = TRUE;  imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>(op, cmode, i:imm3:imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T5" oneof="10" id="iclass_t5" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T5" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMOV_i/T5A5_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOV_i_T5_D" oneofinclass="2" oneof="22" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T5" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_i_T5_Q" oneofinclass="2" oneof="22" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T5" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I64 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_i/T5A5_A.txt" mylink="aarch32.instrs.VMOV_i.T5A5_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if op == '0' &amp;&amp; cmode&lt;0&gt; == '1' &amp;&amp; cmode&lt;3:2&gt; != '11' then SEE "VORR (immediate)";</line>
<line>if op == '1' &amp;&amp; cmode != '1110' then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>single_register = FALSE;  advsimd = TRUE;  imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>(op, cmode, i:imm3:imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMOV_i_A1_Q, VMOV_i_A3_Q, VMOV_i_A4_Q, VMOV_i_A5_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <intro>
          <para>For encoding A1, A3, A4 and A5: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_i_A2_H, VMOV_i_T1_Q, VMOV_i_T2_H, VMOV_i_T3_Q, VMOV_i_T4_Q, VMOV_i_T5_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For encoding A2, T1, T2, T3, T4 and T5: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_i_A1_Q, VMOV_i_A2_H, VMOV_i_A3_Q, VMOV_i_A4_Q, VMOV_i_A5_Q, VMOV_i_T1_Q, VMOV_i_T2_H, VMOV_i_T3_Q, VMOV_i_T4_Q, VMOV_i_T5_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_i_A4_Q, VMOV_i_T4_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="cmode">
        <intro>The data type, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">cmode</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">110x</entry>
                <entry class="symbol">I32</entry>
              </row>
              <row>
                <entry class="bitfield">1110</entry>
                <entry class="symbol">I8</entry>
              </row>
              <row>
                <entry class="bitfield">1111</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VMOV_i_A1_Q, VMOV_i_A3_Q, VMOV_i_A4_Q, VMOV_i_A5_Q, VMOV_i_T1_Q, VMOV_i_T3_Q, VMOV_i_T4_Q, VMOV_i_T5_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_i_A1_D, VMOV_i_A2_D, VMOV_i_A3_D, VMOV_i_A4_D, VMOV_i_A5_D, VMOV_i_T1_D, VMOV_i_T2_D, VMOV_i_T3_D, VMOV_i_T4_D, VMOV_i_T5_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_i_A2_H, VMOV_i_T2_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_i_A1_Q, VMOV_i_A3_Q, VMOV_i_A4_Q, VMOV_i_A5_Q, VMOV_i_T1_Q, VMOV_i_T3_Q, VMOV_i_T4_Q, VMOV_i_T5_Q" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <intro>
          <para>For encoding A1, A3, A4, A5, T1, T3, T4 and T5: is a constant of the specified type that is replicated to fill the destination register. For details of the range of constants available and the encoding of <syntax>&lt;imm&gt;</syntax>, see <xref linkend="CJAIDJDJ">Modified immediate constants in T32 and A32 Advanced SIMD instructions</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_i_A2_H, VMOV_i_T2_H" symboldefcount="2">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="mnemonic-fpdatasize" value="VMOV-halfprec" />
        </docvars>
        <intro>
          <para>For encoding A2 and T2: is a signed floating-point constant with 3-bit exponent and normalized 4 bits of precision, encoded in "imm4H:imm4L". For details of the range of constants available and the encoding of <syntax>&lt;imm&gt;</syntax>, see <xref linkend="CJAJBHCG">Modified immediate constants in T32 and A32 floating-point instructions</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMOV_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDOrVFPEnabled.2" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDOrVFPEnabled(boolean include_fpexc_check, boolean advsimd)">CheckAdvSIMDOrVFPEnabled</a>(TRUE, advsimd);</line>
<line>    if single_register then</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = imm32;</line>
<line>    else</line>
<line>        for r = 0 to regs-1</line>
<line>            <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = imm64;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmov_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMOV_r" title="VMOV (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMOV" />
  </docvars>
  <heading>VMOV (register)</heading>
  <desc>
    <brief>
      <para>Copy between FP registers</para>
    </brief>
    <authored>
      <para>Copy between FP registers copies the contents of one FP register to another.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A2" oneof="2" id="iclass_a2" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMOV_r/T2A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="1">
          <c>1</c>
          <c>x</c>
        </box>
        <box hibit="7" name="o3" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOV_r_A2_S" oneofinclass="2" oneof="4" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="mnemonic-fpdatasize" value="VMOV-singleprec" />
        </docvars>
        <box hibit="9" width="" name="size">
          <c></c>
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_r_A2_D" oneofinclass="2" oneof="4" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="mnemonic-fpdatasize" value="VMOV-doubleprec" />
        </docvars>
        <box hibit="9" width="" name="size">
          <c></c>
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_r/T2A2_A.txt" mylink="aarch32.instrs.VMOV_r.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>single_register = (size == '10');  advsimd = FALSE;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>integer regs;</line>
<line>if single_register then</line>
<line>    d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>else</line>
<line>    d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="2" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMOV_r/T2A2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="1">
          <c>1</c>
          <c>x</c>
        </box>
        <box hibit="7" name="o3" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOV_r_T2_S" oneofinclass="2" oneof="4" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="mnemonic-fpdatasize" value="VMOV-singleprec" />
        </docvars>
        <box hibit="9" width="" name="size">
          <c></c>
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_r_T2_D" oneofinclass="2" oneof="4" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="mnemonic-fpdatasize" value="VMOV-doubleprec" />
        </docvars>
        <box hibit="9" width="" name="size">
          <c></c>
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_r/T2A2_A.txt" mylink="aarch32.instrs.VMOV_r.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>single_register = (size == '10');  advsimd = FALSE;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>integer regs;</line>
<line>if single_register then</line>
<line>    d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>else</line>
<line>    d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMOV_r_A2_S, VMOV_r_T2_S" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_r_A2_S, VMOV_r_T2_S" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_r_A2_S, VMOV_r_T2_S" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_r_A2_S, VMOV_r_T2_S" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_r_A2_D, VMOV_r_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_r_A2_D, VMOV_r_T2_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMOV_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDOrVFPEnabled.2" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDOrVFPEnabled(boolean include_fpexc_check, boolean advsimd)">CheckAdvSIMDOrVFPEnabled</a>(TRUE, advsimd);</line>
<line>    if single_register then</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m];</line>
<line>    else</line>
<line>        for r = 0 to regs-1</line>
<line>            <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r];</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmov_rs.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMOV_rs" title="VMOV (general-purpose register to scalar) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMOV" />
  </docvars>
  <heading>VMOV (general-purpose register to scalar)</heading>
  <desc>
    <brief>
      <para>Copy a general-purpose register to a vector element</para>
    </brief>
    <authored>
      <para>Copy a general-purpose register to a vector element copies a byte, halfword, or word from a general-purpose register into an Advanced SIMD scalar.</para>
      <para>On a Floating-point-only system, this instruction transfers one word to the upper or lower half of a double-precision floating-point register from a general-purpose register. This is an identical operation to the Advanced SIMD single word transfer.</para>
      <para>For more information about scalars see <xref linkend="Cjaibjhd">Advanced SIMD scalars</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMOV_rs/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc1" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="6" width="2" name="opc2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="VMOV_rs_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
        </docvars>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="The data size">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_dd_x" hover="The scalar">&lt;Dd[x]&gt;</a><text>, </text><a link="sa_rt" hover="The source general-purpose register">&lt;Rt&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_rs/T1A1_A.txt" mylink="aarch32.instrs.VMOV_rs.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>boolean advsimd;</line>
<line>integer esize;</line>
<line>integer index;</line>
<line>case opc1:opc2 of</line>
<line>    when '1xxx'  advsimd = TRUE;  esize = 8;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc1&lt;0&gt;:opc2);</line>
<line>    when '0xx1'  advsimd = TRUE;  esize = 16;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc1&lt;0&gt;:opc2&lt;1&gt;);</line>
<line>    when '0x00'  advsimd = FALSE;  esize = 32;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc1&lt;0&gt;);</line>
<line>    when '0x10'  UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);</line>
<line>if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMOV_rs/T1A1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="opc1" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="6" width="2" name="opc2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="VMOV_rs_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
        </docvars>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="The data size">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_dd_x" hover="The scalar">&lt;Dd[x]&gt;</a><text>, </text><a link="sa_rt" hover="The source general-purpose register">&lt;Rt&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_rs/T1A1_A.txt" mylink="aarch32.instrs.VMOV_rs.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>boolean advsimd;</line>
<line>integer esize;</line>
<line>integer index;</line>
<line>case opc1:opc2 of</line>
<line>    when '1xxx'  advsimd = TRUE;  esize = 8;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc1&lt;0&gt;:opc2);</line>
<line>    when '0xx1'  advsimd = TRUE;  esize = 16;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc1&lt;0&gt;:opc2&lt;1&gt;);</line>
<line>    when '0x00'  advsimd = FALSE;  esize = 32;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc1&lt;0&gt;);</line>
<line>    when '0x10'  UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);</line>
<line>if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMOV_rs_A1, VMOV_rs_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_rs_A1, VMOV_rs_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_rs_A1, VMOV_rs_T1" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The data size. It must be one of:</para>
          <list type="param">
            <listitem>
              <param>8</param><content>Encoded as <field>opc1&lt;1&gt;</field> = 1. <syntax>[x]</syntax> is encoded in <field>opc1&lt;0&gt;</field>, <field>opc2</field>.</content>
            </listitem>
            <listitem>
              <param>16</param><content>Encoded as <field>opc1&lt;1&gt;</field> = 0, <field>opc2&lt;0&gt;</field> = 1. <syntax>[x]</syntax> is encoded in <field>opc1&lt;0&gt;</field>, <field>opc2&lt;1&gt;</field>.</content>
            </listitem>
            <listitem>
              <param>32</param><content>Encoded as <field>opc1&lt;1&gt;</field> = 0, <field>opc2</field> = <binarynumber>0b00</binarynumber>. <syntax>[x]</syntax> is encoded in <field>opc1&lt;0&gt;</field>.</content>
            </listitem>
            <listitem>
              <param>omitted</param><content>Equivalent to <value>32</value>.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_rs_A1, VMOV_rs_T1" symboldefcount="1">
      <symbol link="sa_dd_x">&lt;Dd[x]&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The scalar. The register <syntax>&lt;Dd&gt;</syntax> is encoded in D:Vd. For details of how <syntax>[x]</syntax> is encoded, see the description of <syntax>&lt;size&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_rs_A1, VMOV_rs_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The source general-purpose register.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMOV_rs/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDOrVFPEnabled.2" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDOrVFPEnabled(boolean include_fpexc_check, boolean advsimd)">CheckAdvSIMDOrVFPEnabled</a>(TRUE, advsimd);</line>
<line>    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d],index,esize] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]&lt;esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmov_s.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMOV_s" title="VMOV (between general-purpose register and single-precision) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMOV" />
  </docvars>
  <heading>VMOV (between general-purpose register and single-precision)</heading>
  <desc>
    <brief>
      <para>Copy a general-purpose register to or from a 32-bit SIMD&amp;FP register</para>
    </brief>
    <authored>
      <para>Copy a general-purpose register to or from a 32-bit SIMD&amp;FP register. This instruction transfers the value held in a 32-bit SIMD&amp;FP register to a general-purpose register, or the value held in a general-purpose register to a 32-bit SIMD&amp;FP register.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMOV_s/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="VMOV_tos_A1" oneofinclass="2" oneof="4" label="From general-purpose register" bitdiffs="op == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="to-or-from-gp" value="from-gp" />
        </docvars>
        <box hibit="20" width="1" name="op">
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_sn" hover="32-bit SIMD&amp;FP register to be transferred (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register that {syntax{&lt;Sn&gt;}} will be transferred to or from (field &quot;Rt&quot;)">&lt;Rt&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_s_A1" oneofinclass="2" oneof="4" label="To general-purpose register" bitdiffs="op == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="to-or-from-gp" value="to-gp" />
        </docvars>
        <box hibit="20" width="1" name="op">
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register that {syntax{&lt;Sn&gt;}} will be transferred to or from (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_sn" hover="32-bit SIMD&amp;FP register to be transferred (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_s/A1_A.txt" mylink="aarch32.instrs.VMOV_s.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>to_arm_register = (op == '1');  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N);</line>
<line>if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMOV_s/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="VMOV_tos_T1" oneofinclass="2" oneof="4" label="From general-purpose register" bitdiffs="op == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="to-or-from-gp" value="from-gp" />
        </docvars>
        <box hibit="20" width="1" name="op">
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_sn" hover="32-bit SIMD&amp;FP register to be transferred (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register that {syntax{&lt;Sn&gt;}} will be transferred to or from (field &quot;Rt&quot;)">&lt;Rt&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_s_T1" oneofinclass="2" oneof="4" label="To general-purpose register" bitdiffs="op == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="to-or-from-gp" value="to-gp" />
        </docvars>
        <box hibit="20" width="1" name="op">
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register that {syntax{&lt;Sn&gt;}} will be transferred to or from (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_sn" hover="32-bit SIMD&amp;FP register to be transferred (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_s/T1_A.txt" mylink="aarch32.instrs.VMOV_s.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>to_arm_register = (op == '1');  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N);</line>
<line>if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMOV_s_A1, VMOV_tos_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register that <syntax>&lt;Sn&gt;</syntax> will be transferred to or from, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_s_A1, VMOV_tos_T1" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP register to be transferred, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_s_A1, VMOV_tos_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_s_A1, VMOV_tos_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMOV_s/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    if to_arm_register then</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n];</line>
<line>    else</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmov_sr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMOV_sr" title="VMOV (scalar to general-purpose register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMOV" />
  </docvars>
  <heading>VMOV (scalar to general-purpose register)</heading>
  <desc>
    <brief>
      <para>Copy a vector element to a general-purpose register with sign or zero extension</para>
    </brief>
    <authored>
      <para>Copy a vector element to a general-purpose register with sign or zero extension copies a byte, halfword, or word from an Advanced SIMD scalar to a general-purpose register. Bytes and halfwords can be either zero-extended or sign-extended.</para>
      <para>On a Floating-point-only system, this instruction transfers one word from the upper or lower half of a double-precision floating-point register to a general-purpose register. This is an identical operation to the Advanced SIMD single word transfer.</para>
      <para>For more information about scalars see <xref linkend="Cjaibjhd">Advanced SIMD scalars</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMOV_sr/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" width="2" name="opc1" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" width="2" name="opc2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="VMOV_sr_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
        </docvars>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="The data type">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="The destination general-purpose register">&lt;Rt&gt;</a><text>, </text><a link="sa_dn_x" hover="The scalar">&lt;Dn[x]&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_sr/T1A1_A.txt" mylink="aarch32.instrs.VMOV_sr.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>boolean advsimd;</line>
<line>integer esize;</line>
<line>integer index;</line>
<line>case U:opc1:opc2 of</line>
<line>    when 'x1xxx'  advsimd = TRUE;  esize = 8;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc1&lt;0&gt;:opc2);</line>
<line>    when 'x0xx1'  advsimd = TRUE;  esize = 16;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc1&lt;0&gt;:opc2&lt;1&gt;);</line>
<line>    when '00x00'  advsimd = FALSE;  esize = 32;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc1&lt;0&gt;);</line>
<line>    when '10x00'  UNDEFINED;</line>
<line>    when 'x0x10'  UNDEFINED;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  unsigned = (U == '1');</line>
<line>if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMOV_sr/T1A1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" width="2" name="opc1" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" width="2" name="opc2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="VMOV_sr_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
        </docvars>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="The data type">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="The destination general-purpose register">&lt;Rt&gt;</a><text>, </text><a link="sa_dn_x" hover="The scalar">&lt;Dn[x]&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_sr/T1A1_A.txt" mylink="aarch32.instrs.VMOV_sr.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>boolean advsimd;</line>
<line>integer esize;</line>
<line>integer index;</line>
<line>case U:opc1:opc2 of</line>
<line>    when 'x1xxx'  advsimd = TRUE;  esize = 8;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc1&lt;0&gt;:opc2);</line>
<line>    when 'x0xx1'  advsimd = TRUE;  esize = 16;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc1&lt;0&gt;:opc2&lt;1&gt;);</line>
<line>    when '00x00'  advsimd = FALSE;  esize = 32;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc1&lt;0&gt;);</line>
<line>    when '10x00'  UNDEFINED;</line>
<line>    when 'x0x10'  UNDEFINED;</line>
<line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  unsigned = (U == '1');</line>
<line>if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMOV_sr_A1, VMOV_sr_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_sr_A1, VMOV_sr_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_sr_A1, VMOV_sr_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The data type. It must be one of:</para>
          <list type="param">
            <listitem>
              <param>S8</param><content>Encoded as U = 0, <field>opc1&lt;1&gt;</field> = 1. <syntax>[x]</syntax> is encoded in <field>opc1&lt;0&gt;</field>, <field>opc2</field>.</content>
            </listitem>
            <listitem>
              <param>S16</param><content>Encoded as U = 0, <field>opc1&lt;1&gt;</field> = 0, <field>opc2&lt;0&gt;</field> = 1. <syntax>[x]</syntax> is encoded in <field>opc1&lt;0&gt;</field>, <field>opc2&lt;1&gt;</field>.</content>
            </listitem>
            <listitem>
              <param>U8</param><content>Encoded as U = 1, <field>opc1&lt;1&gt;</field> = 1. <syntax>[x]</syntax> is encoded in <field>opc1&lt;0&gt;</field>, <field>opc2</field>.</content>
            </listitem>
            <listitem>
              <param>U16</param><content>Encoded as U = 1, <field>opc1&lt;1&gt;</field> = 0, <field>opc2&lt;0&gt;</field> = 1. <syntax>[x]</syntax> is encoded in <field>opc1&lt;0&gt;</field>, <field>opc2&lt;1&gt;</field>.</content>
            </listitem>
            <listitem>
              <param>32</param><content>Encoded as U = 0, <field>opc1&lt;1&gt;</field> = 0, <field>opc2</field> = <binarynumber>0b00</binarynumber>. <syntax>[x]</syntax> is encoded in <field>opc1&lt;0&gt;</field>.</content>
            </listitem>
            <listitem>
              <param>omitted</param><content>Equivalent to <value>32</value>.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_sr_A1, VMOV_sr_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The destination general-purpose register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_sr_A1, VMOV_sr_T1" symboldefcount="1">
      <symbol link="sa_dn_x">&lt;Dn[x]&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The scalar. For details of how <syntax>[x]</syntax> is encoded see the description of <syntax>&lt;dt&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMOV_sr/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDOrVFPEnabled.2" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDOrVFPEnabled(boolean include_fpexc_check, boolean advsimd)">CheckAdvSIMDOrVFPEnabled</a>(TRUE, advsimd);</line>
<line>    if unsigned then</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n],index,esize], 32);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n],index,esize], 32);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmov_ss.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMOV_ss" title="VMOV (between two general-purpose registers and two single-precision registers) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMOV" />
  </docvars>
  <heading>VMOV (between two general-purpose registers and two single-precision registers)</heading>
  <desc>
    <brief>
      <para>Copy two general-purpose registers to a pair of 32-bit SIMD&amp;FP registers</para>
    </brief>
    <authored>
      <para>Copy two general-purpose registers to a pair of 32-bit SIMD&amp;FP registers transfers the contents of two consecutively numbered single-precision Floating-point registers to two general-purpose registers, or the contents of two general-purpose registers to a pair of single-precision Floating-point registers. The general-purpose registers do not have to be contiguous.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGFBGAI">VMOV (between two general-purpose registers and two single-precision registers)</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMOV_ss/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rt2" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="opc2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o3" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOV_toss_A1" oneofinclass="2" oneof="4" label="From general-purpose registers" bitdiffs="op == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="to-or-from-gp" value="from-gps" />
        </docvars>
        <box hibit="20" width="1" name="op">
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_sm" hover="First 32-bit SIMD&amp;FP register to be transferred (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a><text>, </text><a link="sa_sm1" hover="Second 32-bit SIMD&amp;FP register to be transferred">&lt;Sm1&gt;</a><text>, </text><a link="sa_rt" hover="First general-purpose register that {syntax{&lt;Sm&gt;}} will be transferred to or from (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register that {syntax{&lt;Sm1&gt;}} will be transferred to or from (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_ss_A1" oneofinclass="2" oneof="4" label="To general-purpose registers" bitdiffs="op == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="to-or-from-gp" value="to-gps" />
        </docvars>
        <box hibit="20" width="1" name="op">
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register that {syntax{&lt;Sm&gt;}} will be transferred to or from (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register that {syntax{&lt;Sm1&gt;}} will be transferred to or from (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a><text>, </text><a link="sa_sm" hover="First 32-bit SIMD&amp;FP register to be transferred (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a><text>, </text><a link="sa_sm1" hover="Second 32-bit SIMD&amp;FP register to be transferred">&lt;Sm1&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_ss/T1A1_A.txt" mylink="aarch32.instrs.VMOV_ss.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>to_arm_registers = (op == '1');  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>if t == 15 || t2 == 15 || m == 31 then UNPREDICTABLE;</line>
<line>if to_arm_registers &amp;&amp; t == t2 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>to_arm_registers &amp;&amp; t == t2</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>m == 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the single-precision registers become <arm-defined-word>unknown</arm-defined-word> for a move to the single-precision register. The general-purpose registers listed in the instruction become <arm-defined-word>unknown</arm-defined-word> for a move from the single-precision registers. This behavior does not affect any other general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMOV_ss/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rt2" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="opc2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o3" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOV_toss_T1" oneofinclass="2" oneof="4" label="From general-purpose registers" bitdiffs="op == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="to-or-from-gp" value="from-gps" />
        </docvars>
        <box hibit="20" width="1" name="op">
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_sm" hover="First 32-bit SIMD&amp;FP register to be transferred (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a><text>, </text><a link="sa_sm1" hover="Second 32-bit SIMD&amp;FP register to be transferred">&lt;Sm1&gt;</a><text>, </text><a link="sa_rt" hover="First general-purpose register that {syntax{&lt;Sm&gt;}} will be transferred to or from (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register that {syntax{&lt;Sm1&gt;}} will be transferred to or from (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_ss_T1" oneofinclass="2" oneof="4" label="To general-purpose registers" bitdiffs="op == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="to-or-from-gp" value="to-gps" />
        </docvars>
        <box hibit="20" width="1" name="op">
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register that {syntax{&lt;Sm&gt;}} will be transferred to or from (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register that {syntax{&lt;Sm1&gt;}} will be transferred to or from (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a><text>, </text><a link="sa_sm" hover="First 32-bit SIMD&amp;FP register to be transferred (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a><text>, </text><a link="sa_sm1" hover="Second 32-bit SIMD&amp;FP register to be transferred">&lt;Sm1&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_ss/T1A1_A.txt" mylink="aarch32.instrs.VMOV_ss.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>to_arm_registers = (op == '1');  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>if t == 15 || t2 == 15 || m == 31 then UNPREDICTABLE;</line>
<line>if to_arm_registers &amp;&amp; t == t2 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>to_arm_registers &amp;&amp; t == t2</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>m == 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the single-precision registers become <arm-defined-word>unknown</arm-defined-word> for a move to the single-precision register. The general-purpose registers listed in the instruction become <arm-defined-word>unknown</arm-defined-word> for a move from the single-precision registers. This behavior does not affect any other general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMOV_ss_A1, VMOV_ss_T1" symboldefcount="1">
      <symbol link="sa_rt2">&lt;Rt2&gt;</symbol>
      <account encodedin="Rt2">
        <intro>
          <para>Is the second general-purpose register that <syntax>&lt;Sm1&gt;</syntax> will be transferred to or from, encoded in the "Rt2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_ss_A1, VMOV_ss_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the first general-purpose register that <syntax>&lt;Sm&gt;</syntax> will be transferred to or from, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_ss_A1, VMOV_ss_T1" symboldefcount="1">
      <symbol link="sa_sm1">&lt;Sm1&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP register to be transferred. This is the next SIMD&amp;FP register after <syntax>&lt;Sm&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_ss_A1, VMOV_ss_T1" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP register to be transferred, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_ss_A1, VMOV_ss_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_ss_A1, VMOV_ss_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMOV_ss/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    if to_arm_registers then</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m];</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t2] = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m+1];</line>
<line>    else</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[m] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[m+1] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t2];</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmov_vorr_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMOV_VORR_r" title="VMOV (register, SIMD) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="VMOV" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VORR" />
  </docvars>
  <heading>VMOV (register, SIMD)</heading>
  <desc>
    <brief>Copy between SIMD registers</brief>
    <longer> copies the contents of one SIMD register to another</longer>
  </desc>
  <aliasto refiform="vorr_r.xml" iformid="VORR_r">VORR (register)</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VORR" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOV_VORR_r_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VMOV" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt_1" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vorr_r.xml#VORR_r_A1_D">VORR</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt_1" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dm&gt;</a></asmtemplate>
          <aliascond>N:Vn == M:Vm</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VMOV_VORR_r_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VMOV" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt_1" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vorr_r.xml#VORR_r_A1_Q">VORR</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt_1" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qm&gt;</a></asmtemplate>
          <aliascond>N:Vn == M:Vm</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VORR" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOV_VORR_r_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VMOV" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt_1" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vorr_r.xml#VORR_r_T1_D">VORR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt_1" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dm&gt;</a></asmtemplate>
          <aliascond>N:Vn == M:Vm</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VMOV_VORR_r_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VMOV" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt_1" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vorr_r.xml#VORR_r_T1_Q">VORR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt_1" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qm&gt;</a></asmtemplate>
          <aliascond>N:Vn == M:Vm</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMOV_VORR_r_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_VORR_r_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_VORR_r_A1_Q, VMOV_VORR_r_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_VORR_r_A1_Q, VMOV_VORR_r_T1_Q" symboldefcount="1">
      <symbol link="sa_dt_1">&lt;dt&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>An optional data type. <syntax>&lt;dt&gt;</syntax> must not be <value>F64</value>, but it is otherwise ignored.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_VORR_r_A1_Q, VMOV_VORR_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_VORR_r_A1_Q, VMOV_VORR_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qm_1">&lt;Qm&gt;</symbol>
      <account encodedin="N:Vn&quot; and &quot;M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "N:Vn" and "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_VORR_r_A1_D, VMOV_VORR_r_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_VORR_r_A1_D, VMOV_VORR_r_T1_D" symboldefcount="1">
      <symbol link="sa_dm_1">&lt;Dm&gt;</symbol>
      <account encodedin="N:Vn&quot; and &quot;M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "N:Vn" and "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="vmovl.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMOVL" title="VMOVL -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMOVL" />
  </docvars>
  <heading>VMOVL</heading>
  <desc>
    <brief>
      <para>Vector Move Long</para>
    </brief>
    <authored>
      <para>Vector Move Long takes each element in a doubleword vector, sign or zero-extends them to twice their original length, and places the results in a quadword vector.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_1r_imm">Advanced SIMD one register and modified immediate</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd1reg_imm">Advanced SIMD one register and modified immediate</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMOVL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMOVL/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" name="imm3H" usename="1" settings="3" constraint="!= 000">
          <c colspan="3">!= 000</c>
        </box>
        <box hibit="18" width="3" name="imm3L" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOVL_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOVL" />
        </docvars>
        <asmtemplate><text>VMOVL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;U:imm3H&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOVL/T1A1_A.txt" mylink="aarch32.instrs.VMOVL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if imm3H == '000' then SEE "Related encodings";</line>
<line>if imm3H != '001' &amp;&amp; imm3H != '010' &amp;&amp; imm3H != '100' then SEE "VSHLL";</line>
<line>if Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>esize = 8 * <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm3H);</line>
<line>unsigned = (U == '1');  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMOVL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMOVL/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" name="imm3H" usename="1" settings="3" constraint="!= 000">
          <c colspan="3">!= 000</c>
        </box>
        <box hibit="18" width="3" name="imm3L" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOVL_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOVL" />
        </docvars>
        <asmtemplate><text>VMOVL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;U:imm3H&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOVL/T1A1_A.txt" mylink="aarch32.instrs.VMOVL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if imm3H == '000' then SEE "Related encodings";</line>
<line>if imm3H != '001' &amp;&amp; imm3H != '010' &amp;&amp; imm3H != '100' then SEE "VSHLL";</line>
<line>if Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>esize = 8 * <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm3H);</line>
<line>unsigned = (U == '1');  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMOVL_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOVL_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOVL_A1, VMOVL_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOVL_A1, VMOVL_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:imm3H">
        <intro>Is the data type for the elements of the operand, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">imm3H</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">001</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">010</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">100</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">001</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">010</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">100</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VMOVL_A1, VMOVL_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOVL_A1, VMOVL_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMOVL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for e = 0 to elements-1</line>
<line>        result = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m],e,esize], unsigned);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = result&lt;2*esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmovn.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMOVN" title="VMOVN -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMOVN" />
  </docvars>
  <heading>VMOVN</heading>
  <desc>
    <brief>
      <para>Vector Move and Narrow</para>
    </brief>
    <authored>
      <para>Vector Move and Narrow copies the least significant half of each element of a quadword vector into the corresponding elements of a doubleword vector.</para>
      <para>The operand vector elements can be any one of 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and unsigned integers.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="2">
    <alias_list_intro>This instruction is used by the aliases </alias_list_intro>
    <aliasref aliaspageid="VRSHRN_VMOVN" aliasfile="vrshrn_vmovn.xml" hover="Vector Rounding Shift Right and Narrow" punct=" and ">
      <text>VRSHRN (zero)</text>
      <aliaspref>Never</aliaspref>
    </aliasref>
    <aliasref aliaspageid="VSHRN_VMOVN" aliasfile="vshrn_vmovn.xml" hover="Vector Shift Right Narrow" punct=".">
      <text>VSHRN (zero)</text>
      <aliaspref>Never</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink />
      <text> below for details of when each alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMOVN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMOVN/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOVN_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOVN" />
        </docvars>
        <asmtemplate><text>VMOVN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOVN/T1A1_A.txt" mylink="aarch32.instrs.VMOVN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMOVN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMOVN/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOVN_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOVN" />
        </docvars>
        <asmtemplate><text>VMOVN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOVN/T1A1_A.txt" mylink="aarch32.instrs.VMOVN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMOVN_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOVN_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOVN_A1, VMOVN_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOVN_A1, VMOVN_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operand, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">I16</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">I32</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">I64</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VMOVN_A1, VMOVN_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOVN_A1, VMOVN_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMOVN/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for e = 0 to elements-1</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d],e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[m&gt;&gt;1],e,2*esize]&lt;esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmovx.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMOVX" title="VMOVX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMOVX" />
  </docvars>
  <heading>VMOVX</heading>
  <desc>
    <brief>
      <para>Vector Move extraction</para>
    </brief>
    <authored>
      <para>Vector Move extraction. This instruction copies the upper 16 bits of the 32-bit source SIMD&amp;FP register into the lower 16 bits of the 32-bit destination SIMD&amp;FP register, while clearing the remaining bits to zero.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMOVX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VMOVX/A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" settings="6">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOVX_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOVX" />
        </docvars>
        <asmtemplate><text>VMOVX</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOVX/A1_A.txt" mylink="aarch32.instrs.VMOVX.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMOVX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VMOVX/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" settings="6">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMOVX_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOVX" />
        </docvars>
        <asmtemplate><text>VMOVX</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOVX/T1_A.txt" mylink="aarch32.instrs.VMOVX.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMOVX_A1, VMOVX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOVX_A1, VMOVX_T1" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOVX_A1, VMOVX_T1" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMOVX/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;31:16&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmrs.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMRS" title="VMRS -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMRS" />
  </docvars>
  <heading>VMRS</heading>
  <desc>
    <brief>
      <para>Move SIMD&amp;FP Special register to general-purpose register</para>
    </brief>
    <authored>
      <para>Move SIMD&amp;FP Special register to general-purpose register moves the value of an Advanced SIMD and floating-point System register to a general-purpose register. When the specified System register is the <xref linkend="AArch32.fpscr">FPSCR</xref>, a form of the instruction transfers the <xref linkend="AArch32.fpscr">FPSCR</xref>.{N, Z, C, V} condition flags to the <xref linkend="AArch32.apsr">APSR</xref>.{N, Z, C, V} condition flags.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
      <para>When these settings permit the execution of Advanced SIMD and floating-point instructions, if the specified floating-point System register is not the <xref linkend="AArch32.fpscr">FPSCR</xref>, the instruction is <arm-defined-word>undefined</arm-defined-word> if executed in User mode.</para>
      <para>In an implementation that includes EL2, when <xref linkend="AArch32.hcr">HCR</xref>.TID0 is set to 1, any <instruction>VMRS</instruction> access to <xref linkend="AArch32.fpsid">FPSID</xref> from a Non-secure EL1 mode that would be permitted if <xref linkend="AArch32.hcr">HCR</xref>.TID0 was set to 0 generates a Hyp Trap exception. For more information, see <xref linkend="CHDFGEDI">ID group 0, Primary device identification registers</xref>.</para>
      <para>For simplicity, the <instruction>VMRS</instruction> pseudocode does not show the possible trap to Hyp mode.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMRS" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMRS/T1A1_AS.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="reg" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="VMRS_A1_AS" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMRS" />
        </docvars>
        <asmtemplate><text>VMRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose destination register (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_spec_reg" hover="Source Advanced SIMD and floating-point System register (field &quot;reg&quot;)">&lt;spec_reg&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMRS/T1A1_AS.txt" mylink="aarch32.instrs.VMRS.T1A1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);</line>
<line>if !(reg IN {'000x', '0101', '011x', '1000'}) then UNPREDICTABLE;</line>
<line>if t == 15 &amp;&amp; reg != '0001' then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>!(reg IN {'000x', '0101', '011x', '1000'})</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction transfers an <arm-defined-word>unknown</arm-defined-word> value to the specified target register. When the Rt field holds the value <value>0b1111</value>, the specified target register is the <xref linkend="AArch32.apsr">APSR</xref>.{N, Z, C, V} bits, and these bits become <arm-defined-word>unknown</arm-defined-word>. Otherwise, the specified target register is the register specified by the <syntax>Rt</syntax> field, R0 - R14.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMRS" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMRS/T1A1_AS.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="reg" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="VMRS_T1_AS" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMRS" />
        </docvars>
        <asmtemplate><text>VMRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose destination register (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_spec_reg" hover="Source Advanced SIMD and floating-point System register (field &quot;reg&quot;)">&lt;spec_reg&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMRS/T1A1_AS.txt" mylink="aarch32.instrs.VMRS.T1A1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);</line>
<line>if !(reg IN {'000x', '0101', '011x', '1000'}) then UNPREDICTABLE;</line>
<line>if t == 15 &amp;&amp; reg != '0001' then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>!(reg IN {'000x', '0101', '011x', '1000'})</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction transfers an <arm-defined-word>unknown</arm-defined-word> value to the specified target register. When the Rt field holds the value <value>0b1111</value>, the specified target register is the <xref linkend="AArch32.apsr">APSR</xref>.{N, Z, C, V} bits, and these bits become <arm-defined-word>unknown</arm-defined-word>. Otherwise, the specified target register is the register specified by the <syntax>Rt</syntax> field, R0 - R14.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMRS_A1_AS, VMRS_T1_AS" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMRS_A1_AS, VMRS_T1_AS" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMRS_A1_AS, VMRS_T1_AS" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rt" field. Is one of:</para>
          <list type="param">
            <listitem>
              <param>R0-R14</param><content>General-purpose register.</content>
            </listitem>
            <listitem>
              <param>APSR_nzcv</param><content>Permitted only when <syntax>&lt;spec_reg&gt;</syntax> is <value>FPSCR</value>. Encoded as <binarynumber>0b1111</binarynumber>. The instruction transfers the <xref linkend="AArch32.fpscr">FPSCR</xref>.{N, Z, C, V} condition flags to the <xref linkend="AArch32.apsr">APSR</xref>.{N, Z, C, V} condition flags.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMRS_A1_AS, VMRS_T1_AS" symboldefcount="1">
      <symbol link="sa_spec_reg">&lt;spec_reg&gt;</symbol>
      <definition encodedin="reg">
        <intro>Is the source Advanced SIMD and floating-point System register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">reg</entry>
                <entry class="symbol">&lt;spec_reg&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0000</entry>
                <entry class="symbol">FPSID</entry>
              </row>
              <row>
                <entry class="bitfield">0001</entry>
                <entry class="symbol">FPSCR</entry>
              </row>
              <row>
                <entry class="bitfield">001x</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">0100</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">0101</entry>
                <entry class="symbol">MVFR2</entry>
              </row>
              <row>
                <entry class="bitfield">0110</entry>
                <entry class="symbol">MVFR1</entry>
              </row>
              <row>
                <entry class="bitfield">0111</entry>
                <entry class="symbol">MVFR0</entry>
              </row>
              <row>
                <entry class="bitfield">1000</entry>
                <entry class="symbol">FPEXC</entry>
              </row>
              <row>
                <entry class="bitfield">1001</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">101x</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">11xx</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMRS/Op_AS.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if reg == '0001' then                 // FPSCR</line>
<line>        <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>        if t == 15 then</line>
<line>            PSTATE.&lt;N,Z,C,V&gt; = FPSR.&lt;N,Z,C,V&gt;;</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = FPSCR;</line>
<line>    elsif PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        UNDEFINED;                        // Non-FPSCR registers accessible only at PL1 or above</line>
<line>    else</line>
<line>        <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(FALSE);           // Non-FPSCR registers are not affected by FPEXC.EN</line>
<line>        <a link="AArch32.CheckAdvSIMDOrFPRegisterTraps.1" file="shared_pseudocode.xml" hover="function: AArch32.CheckAdvSIMDOrFPRegisterTraps(bits(4) reg)">AArch32.CheckAdvSIMDOrFPRegisterTraps</a>(reg);</line>
<line>        case reg of</line>
<line>            when '0000'  <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = FPSID;</line>
<line>            when '0101'  <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = MVFR2;</line>
<line>            when '0110'  <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = MVFR1;</line>
<line>            when '0111'  <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = MVFR0;</line>
<line>            when '1000'  <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = FPEXC;</line>
<line>            otherwise    <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();   // Dealt with above or in encoding-specific pseudocode</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmsr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMSR" title="VMSR -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMSR" />
  </docvars>
  <heading>VMSR</heading>
  <desc>
    <brief>
      <para>Move general-purpose register to SIMD&amp;FP Special register</para>
    </brief>
    <authored>
      <para>Move general-purpose register to SIMD&amp;FP Special register moves the value of a general-purpose register to a floating-point System register.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
      <para>When these settings permit the execution of Advanced SIMD and floating-point instructions:</para>
      <list type="unordered">
        <listitem><content>If the specified floating-point System register is <xref linkend="AArch32.fpsid">FPSID</xref> or <xref linkend="AArch32.fpexc">FPEXC</xref>, the instruction is <arm-defined-word>undefined</arm-defined-word> if executed in User mode.</content></listitem>
        <listitem><content>If the specified floating-point System register is the <xref linkend="AArch32.fpsid">FPSID</xref> and the instruction is executed in a mode other than User mode, the instruction is ignored.</content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMSR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMSR/T1A1_AS.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="reg" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="VMSR_A1_AS" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMSR" />
        </docvars>
        <asmtemplate><text>VMSR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_spec_reg" hover="Destination Advanced SIMD and floating-point System register (field &quot;reg&quot;)">&lt;spec_reg&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose source register (field &quot;Rt&quot;)">&lt;Rt&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMSR/T1A1_AS.txt" mylink="aarch32.instrs.VMSR.T1A1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);</line>
<line>if !(reg IN {'000x'}) &amp;&amp; reg != '1000' then</line>
<line>    <a link="Constraint" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint</a> c = <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_VMSR" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_VMSR</a>);</line>
<line>    assert c IN {<a link="Constraint_UNDEF" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNDEF</a>, <a link="Constraint_NOP" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NOP</a>};</line>
<line>    case c of</line>
<line>        when <a link="Constraint_UNDEF" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNDEF</a></line>
<line>            UNDEFINED;</line>
<line>        when <a link="Constraint_NOP" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NOP</a></line>
<line>            <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
<line>if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>reg != '000x' &amp;&amp; reg != '1000'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction transfers the value in the general-purpose register to one of the allocated registers accessible using <instruction>VMSR</instruction> at the same Exception level.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMSR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMSR/T1A1_AS.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="reg" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="VMSR_T1_AS" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMSR" />
        </docvars>
        <asmtemplate><text>VMSR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_spec_reg" hover="Destination Advanced SIMD and floating-point System register (field &quot;reg&quot;)">&lt;spec_reg&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose source register (field &quot;Rt&quot;)">&lt;Rt&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMSR/T1A1_AS.txt" mylink="aarch32.instrs.VMSR.T1A1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);</line>
<line>if !(reg IN {'000x'}) &amp;&amp; reg != '1000' then</line>
<line>    <a link="Constraint" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint</a> c = <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_VMSR" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_VMSR</a>);</line>
<line>    assert c IN {<a link="Constraint_UNDEF" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNDEF</a>, <a link="Constraint_NOP" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NOP</a>};</line>
<line>    case c of</line>
<line>        when <a link="Constraint_UNDEF" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNDEF</a></line>
<line>            UNDEFINED;</line>
<line>        when <a link="Constraint_NOP" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NOP</a></line>
<line>            <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
<line>if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>reg != '000x' &amp;&amp; reg != '1000'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction transfers the value in the general-purpose register to one of the allocated registers accessible using <instruction>VMSR</instruction> at the same Exception level.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMSR_A1_AS, VMSR_T1_AS" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMSR_A1_AS, VMSR_T1_AS" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMSR_A1_AS, VMSR_T1_AS" symboldefcount="1">
      <symbol link="sa_spec_reg">&lt;spec_reg&gt;</symbol>
      <definition encodedin="reg">
        <intro>Is the destination Advanced SIMD and floating-point System register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">reg</entry>
                <entry class="symbol">&lt;spec_reg&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0000</entry>
                <entry class="symbol">FPSID</entry>
              </row>
              <row>
                <entry class="bitfield">0001</entry>
                <entry class="symbol">FPSCR</entry>
              </row>
              <row>
                <entry class="bitfield">001x</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">01xx</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">1000</entry>
                <entry class="symbol">FPEXC</entry>
              </row>
              <row>
                <entry class="bitfield">1001</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">101x</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
              <row>
                <entry class="bitfield">11xx</entry>
                <entry class="symbol">UNPREDICTABLE</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VMSR_A1_AS, VMSR_T1_AS" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose source register, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMSR/Op_AS.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if reg == '0001' then                 // FPSCR</line>
<line>        <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>        FPSCR = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];</line>
<line>    elsif PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        UNDEFINED;                        // Non-FPSCR registers accessible only at PL1 or above</line>
<line>    else</line>
<line>        <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(FALSE);           // Non-FPSCR registers are not affected by FPEXC.EN</line>
<line>        case reg of</line>
<line>            when '0000'                   // VMSR access to FPSID is ignored</line>
<line>            when '1000'</line>
<line>                FPEXC = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];</line>
<line>            otherwise</line>
<line>                <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();   // Dealt with above or in encoding-specific pseudocode</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmul_f.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMUL_f" title="VMUL (floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMUL" />
  </docvars>
  <heading>VMUL (floating-point)</heading>
  <desc>
    <brief>
      <para>Vector Multiply (floating-point)</para>
    </brief>
    <authored>
      <para>Vector Multiply multiplies corresponding elements in two vectors, and places the results in the destination vector.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMUL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMUL_f/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMUL_f_A1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMUL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMUL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMUL_f_A1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMUL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMUL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMUL_f/A1_A.txt" mylink="aarch32.instrs.VMUL_f.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>advsimd = TRUE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMUL" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMUL_f/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMUL_f_A2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMUL" />
          <docvar key="mnemonic-fpdatasize" value="VMUL-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VMUL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><text>{</text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMUL_f_A2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMUL" />
          <docvar key="mnemonic-fpdatasize" value="VMUL-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VMUL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><text>{</text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMUL_f_A2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMUL" />
          <docvar key="mnemonic-fpdatasize" value="VMUL-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VMUL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMUL_f/A2_A.txt" mylink="aarch32.instrs.VMUL_f.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>advsimd = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMUL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMUL_f/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMUL_f_T1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMUL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMUL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMUL_f_T1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMUL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMUL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMUL_f/T1_A.txt" mylink="aarch32.instrs.VMUL_f.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if sz == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>advsimd = TRUE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>sz == '1' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMUL" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMUL_f/T2_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMUL_f_T2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMUL" />
          <docvar key="mnemonic-fpdatasize" value="VMUL-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VMUL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><text>{</text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMUL_f_T2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMUL" />
          <docvar key="mnemonic-fpdatasize" value="VMUL-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VMUL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><text>{</text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMUL_f_T2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMUL" />
          <docvar key="mnemonic-fpdatasize" value="VMUL-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VMUL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMUL_f/T2_A.txt" mylink="aarch32.instrs.VMUL_f.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>advsimd = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMUL_f_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_f_A2_H, VMUL_f_T1_Q, VMUL_f_T2_H" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For encoding A2, T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_f_A1_Q, VMUL_f_A2_H, VMUL_f_T1_Q, VMUL_f_T2_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_f_A1_Q, VMUL_f_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VMUL_f_A1_Q, VMUL_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_f_A1_Q, VMUL_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_f_A1_Q, VMUL_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_f_A1_D, VMUL_f_A2_D, VMUL_f_T1_D, VMUL_f_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_f_A1_D, VMUL_f_A2_D, VMUL_f_T1_D, VMUL_f_T2_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_f_A1_D, VMUL_f_A2_D, VMUL_f_T1_D, VMUL_f_T2_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_f_A2_H, VMUL_f_T2_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_f_A2_H, VMUL_f_T2_H" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_f_A2_H, VMUL_f_T2_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMUL_f/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDOrVFPEnabled.2" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDOrVFPEnabled(boolean include_fpexc_check, boolean advsimd)">CheckAdvSIMDOrVFPEnabled</a>(TRUE, advsimd);</line>
<line>    if advsimd then  // Advanced SIMD instruction</line>
<line>        for r = 0 to regs-1</line>
<line>            for e = 0 to elements-1</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize], <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize],</line>
<line>                                             <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>    else             // VFP instruction</line>
<line>        case esize of</line>
<line>            when 16</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[]);</line>
<line>            when 32</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n], <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[]);</line>
<line>            when 64</line>
<line>                <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n], <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmul_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMUL_i" title="VMUL (integer and polynomial) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMUL" />
  </docvars>
  <heading>VMUL (integer and polynomial)</heading>
  <desc>
    <brief>
      <para>Vector Multiply (integer and polynomial)</para>
    </brief>
    <authored>
      <para>Vector Multiply multiplies corresponding elements in two vectors.</para>
      <para>For information about multiplying polynomials, see <xref linkend="BABDGBIC">Polynomial arithmetic over {0, 1}</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMUL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMUL_i/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMUL_i_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMUL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMUL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;op:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMUL_i_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMUL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMUL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;op:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMUL_i/T1A1_A.txt" mylink="aarch32.instrs.VMUL_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' || (op == '1' &amp;&amp; size != '00') then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = FALSE;  // "Don't care" value: TRUE produces same functionality</line>
<line>polynomial = (op == '1');  long_destination = FALSE;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMUL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMUL_i/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMUL_i_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMUL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMUL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;op:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMUL_i_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMUL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMUL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;op:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMUL_i/T1A1_A.txt" mylink="aarch32.instrs.VMUL_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' || (op == '1' &amp;&amp; size != '00') then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = FALSE;  // "Don't care" value: TRUE produces same functionality</line>
<line>polynomial = (op == '1');  long_destination = FALSE;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMUL_i_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_i_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_i_A1_Q, VMUL_i_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_i_A1_Q, VMUL_i_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="op:size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">op</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">I8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">I16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">I32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">P8</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VMUL_i_A1_Q, VMUL_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_i_A1_Q, VMUL_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_i_A1_Q, VMUL_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_i_A1_D, VMUL_i_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_i_A1_D, VMUL_i_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_i_A1_D, VMUL_i_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMUL_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r],e,esize];  op1val = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op1, unsigned);</line>
<line>            op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m+r],e,esize];  op2val = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op2, unsigned);</line>
<line>            bits(2 * esize) product;</line>
<line>            if polynomial then</line>
<line>                product = <a link="impl-shared.PolynomialMult.2" file="shared_pseudocode.xml" hover="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(op1,op2);</line>
<line>            else</line>
<line>                product = (op1val*op2val)&lt;2*esize-1:0&gt;;</line>
<line>            if long_destination then</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = product;</line>
<line>            else</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = product&lt;esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmul_s.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMUL_s" title="VMUL (by scalar) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMUL" />
  </docvars>
  <heading>VMUL (by scalar)</heading>
  <desc>
    <brief>
      <para>Vector Multiply (by scalar)</para>
    </brief>
    <authored>
      <para>Vector Multiply multiplies each element in a vector by a scalar, and places the results in a second vector.</para>
      <para>For more information about scalars see <xref linkend="Cjaibjhd">Advanced SIMD scalars</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMUL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMUL_s/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="8" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMUL_s_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMUL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="24" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMUL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for scalar and the elements of operand vector (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index (field &quot;M:Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VMUL_s_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMUL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="24" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMUL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for scalar and the elements of operand vector (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index (field &quot;M:Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMUL_s/A1_A.txt" mylink="aarch32.instrs.VMUL_s.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || (F == '1' &amp;&amp; size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = FALSE;  // "Don't care" value: TRUE produces same functionality</line>
<line>floating_point = (F == '1');  long_destination = FALSE;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = if Q == '0' then 1 else 2;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMUL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMUL_s/T1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="8" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMUL_s_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMUL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="28" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMUL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for scalar and the elements of operand vector (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index (field &quot;M:Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VMUL_s_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMUL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="28" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMUL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for scalar and the elements of operand vector (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index (field &quot;M:Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMUL_s/T1_A.txt" mylink="aarch32.instrs.VMUL_s.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if F == '1' &amp;&amp; size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if size == '00' || (F == '1' &amp;&amp; size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = FALSE;  // "Don't care" value: TRUE produces same functionality</line>
<line>floating_point = (F == '1');  long_destination = FALSE;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = if Q == '0' then 1 else 2;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>F == '1' &amp;&amp; size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMUL_s_A1_D" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_s_T1_D" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_s_A1_D, VMUL_s_T1_D" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_s_A1_D, VMUL_s_T1_D" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="F:size">
        <intro>Is the data type for the scalar and the elements of the operand vector, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">F</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">I16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">I32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VMUL_s_A1_Q, VMUL_s_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_s_A1_Q, VMUL_s_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_s_A1_D, VMUL_s_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_s_A1_D, VMUL_s_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_s_A1_D, VMUL_s_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="Vm&lt;2:0&gt;">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register. When <syntax>&lt;dt&gt;</syntax> is I16 or F16, this is encoded in the "Vm&lt;2:0&gt;" field. Otherwise it is encoded in the "Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMUL_s_A1_D, VMUL_s_T1_D" symboldefcount="1">
      <symbol link="sa_index">&lt;index&gt;</symbol>
      <account encodedin="M:Vm&lt;3&gt;">
        <intro>
          <para>Is the element index. When <syntax>&lt;dt&gt;</syntax> is I16 or F16, this is in the range 0 to 3 and is encoded in the "M:Vm&lt;3&gt;" field. Otherwise it is in the range 0 to 1 and is encoded in the "M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMUL_s/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m],index,esize];  op2val = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op2, unsigned);</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r],e,esize];  op1val = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op1, unsigned);</line>
<line>            if floating_point then</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(op1, op2, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            else</line>
<line>                if long_destination then</line>
<line>                    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = (op1val*op2val)&lt;2*esize-1:0&gt;;</line>
<line>                else</line>
<line>                    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = (op1val*op2val)&lt;esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmull_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMULL_i" title="VMULL (integer and polynomial) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMULL" />
  </docvars>
  <heading>VMULL (integer and polynomial)</heading>
  <desc>
    <brief>
      <para>Vector Multiply Long (integer and polynomial)</para>
    </brief>
    <authored>
      <para>Vector Multiply Long multiplies corresponding elements in two vectors. The destination vector elements are twice as long as the elements that are multiplied.</para>
      <para>For information about multiplying polynomials see <xref linkend="BABDGBIC">Polynomial arithmetic over {0, 1}</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMULL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMUL_i/A2_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="8" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMULL_i_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMULL" />
        </docvars>
        <asmtemplate><text>VMULL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;op:U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMUL_i/A2_A.txt" mylink="aarch32.instrs.VMUL_i.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>unsigned = (U == '1'); polynomial = (op == '1'); long_destination = TRUE;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size); elements = 64 DIV esize;</line>
<line>if polynomial then</line>
<line>    if U == '1' || size == '01' then UNDEFINED;</line>
<line>    if size == '10' then    // .p64</line>
<line>        if !<a link="impl-shared.HaveBit128PMULLExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveBit128PMULLExt()">HaveBit128PMULLExt</a>() then UNDEFINED;</line>
<line>        esize = 64; elements = 1;</line>
<line>if Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm); regs = 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMULL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMUL_i/T2_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="8" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMULL_i_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMULL" />
        </docvars>
        <asmtemplate><text>VMULL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;op:U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMUL_i/T2_A.txt" mylink="aarch32.instrs.VMUL_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>unsigned = (U == '1'); polynomial = (op == '1'); long_destination = TRUE;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size); elements = 64 DIV esize;</line>
<line>if polynomial then</line>
<line>    if U == '1' || size == '01' then UNDEFINED;</line>
<line>    if size == '10' then    // .p64</line>
<line>        if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>        if !<a link="impl-shared.HaveBit128PMULLExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveBit128PMULLExt()">HaveBit128PMULLExt</a>() then UNDEFINED;</line>
<line>        esize = 64; elements = 1;</line>
<line>if Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm); regs = 1;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>op == '1' &amp;&amp; size == '10' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMULL_i_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMULL_i_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMULL_i_A1, VMULL_i_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMULL_i_A1, VMULL_i_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="op:U:size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="4">
            <thead>
              <row>
                <entry class="bitfield">op</entry>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">P8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">P64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VMULL_i_A1, VMULL_i_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMULL_i_A1, VMULL_i_T1" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMULL_i_A1, VMULL_i_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMUL_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r],e,esize];  op1val = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op1, unsigned);</line>
<line>            op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m+r],e,esize];  op2val = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op2, unsigned);</line>
<line>            bits(2 * esize) product;</line>
<line>            if polynomial then</line>
<line>                product = <a link="impl-shared.PolynomialMult.2" file="shared_pseudocode.xml" hover="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</a>(op1,op2);</line>
<line>            else</line>
<line>                product = (op1val*op2val)&lt;2*esize-1:0&gt;;</line>
<line>            if long_destination then</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = product;</line>
<line>            else</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = product&lt;esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmull_s.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMULL_s" title="VMULL (by scalar) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMULL" />
  </docvars>
  <heading>VMULL (by scalar)</heading>
  <desc>
    <brief>
      <para>Vector Multiply Long (by scalar)</para>
    </brief>
    <authored>
      <para>Vector Multiply Long multiplies each element in a vector by a scalar, and places the results in a second vector. The destination vector elements are twice as long as the elements that are multiplied.</para>
      <para>For more information about scalars see <xref linkend="Cjaibjhd">Advanced SIMD scalars</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMULL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMUL_s/T2A2_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMULL_s_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMULL" />
        </docvars>
        <asmtemplate><text>VMULL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for scalar and the elements of operand vector (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-3] (field &quot;M:Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMUL_s/T2A2_A.txt" mylink="aarch32.instrs.VMUL_s.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>unsigned = (U == '1');  long_destination = TRUE;  floating_point = FALSE;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = 1;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer index;</line>
<line>integer m;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMULL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMUL_s/T2A2_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMULL_s_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMULL" />
        </docvars>
        <asmtemplate><text>VMULL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for scalar and the elements of operand vector (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-3] (field &quot;M:Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMUL_s/T2A2_A.txt" mylink="aarch32.instrs.VMUL_s.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>unsigned = (U == '1');  long_destination = TRUE;  floating_point = FALSE;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = 1;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer index;</line>
<line>integer m;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMULL_s_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMULL_s_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMULL_s_A1, VMULL_s_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMULL_s_A1, VMULL_s_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the scalar and the elements of the operand vector, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VMULL_s_A1, VMULL_s_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMULL_s_A1, VMULL_s_T1" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMULL_s_A1, VMULL_s_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="Vm&lt;2:0&gt;">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "Vm&lt;2:0&gt;" field when <syntax>&lt;dt&gt;</syntax> is S16 or U16, otherwise the "Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMULL_s_A1, VMULL_s_T1" symboldefcount="1">
      <symbol link="sa_index">&lt;index&gt;</symbol>
      <account encodedin="M:Vm&lt;3&gt;">
        <intro>
          <para>Is the element index in the range 0 to 3, encoded in the "M:Vm&lt;3&gt;" field when <syntax>&lt;dt&gt;</syntax> is S16 or U16, otherwise in range 0 to 1, encoded in the "M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMUL_s/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m],index,esize];  op2val = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op2, unsigned);</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r],e,esize];  op1val = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op1, unsigned);</line>
<line>            if floating_point then</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(op1, op2, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            else</line>
<line>                if long_destination then</line>
<line>                    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = (op1val*op2val)&lt;2*esize-1:0&gt;;</line>
<line>                else</line>
<line>                    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = (op1val*op2val)&lt;esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmvn_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMVN_i" title="VMVN (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMVN" />
  </docvars>
  <heading>VMVN (immediate)</heading>
  <desc>
    <brief>
      <para>Vector Bitwise NOT (immediate)</para>
    </brief>
    <authored>
      <para>Vector Bitwise NOT (immediate) places the bitwise inverse of an immediate integer constant into every element of the destination register.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_1r_imm">Advanced SIMD one register and modified immediate</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd1reg_imm">Advanced SIMD one register and modified immediate</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="6">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>, </txt>
      <a href="#iclass_a2">A2</a>
      <txt> and </txt>
      <a href="#iclass_a3">A3</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="6" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMVN" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMVN_i/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="2">
          <c>0</c>
          <c>x</c>
          <c>x</c>
          <c>0</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMVN_i_A1_D" oneofinclass="2" oneof="12" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMVN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMVN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMVN_i_A1_Q" oneofinclass="2" oneof="12" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMVN" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMVN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMVN_i/T1A1_A.txt" mylink="aarch32.instrs.VMVN_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (cmode&lt;0&gt; == '1' &amp;&amp; cmode&lt;3:2&gt; != '11') || cmode&lt;3:1&gt; == '111' then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>('1', cmode, i:imm3:imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="6" id="iclass_a2" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMVN" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMVN_i/T2A2_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>x</c>
          <c>0</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMVN_i_A2_D" oneofinclass="2" oneof="12" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMVN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMVN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMVN_i_A2_Q" oneofinclass="2" oneof="12" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMVN" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMVN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMVN_i/T2A2_A.txt" mylink="aarch32.instrs.VMVN_i.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (cmode&lt;0&gt; == '1' &amp;&amp; cmode&lt;3:2&gt; != '11') || cmode&lt;3:1&gt; == '111' then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>('1', cmode, i:imm3:imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A3" oneof="6" id="iclass_a3" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMVN" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMVN_i/T3A3_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>x</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMVN_i_A3_D" oneofinclass="2" oneof="12" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMVN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMVN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMVN_i_A3_Q" oneofinclass="2" oneof="12" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMVN" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMVN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMVN_i/T3A3_A.txt" mylink="aarch32.instrs.VMVN_i.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (cmode&lt;0&gt; == '1' &amp;&amp; cmode&lt;3:2&gt; != '11') || cmode&lt;3:1&gt; == '111' then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>('1', cmode, i:imm3:imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="6" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMVN" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMVN_i/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="2">
          <c>0</c>
          <c>x</c>
          <c>x</c>
          <c>0</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMVN_i_T1_D" oneofinclass="2" oneof="12" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMVN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMVN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMVN_i_T1_Q" oneofinclass="2" oneof="12" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMVN" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMVN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMVN_i/T1A1_A.txt" mylink="aarch32.instrs.VMVN_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (cmode&lt;0&gt; == '1' &amp;&amp; cmode&lt;3:2&gt; != '11') || cmode&lt;3:1&gt; == '111' then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>('1', cmode, i:imm3:imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="6" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMVN" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMVN_i/T2A2_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>x</c>
          <c>0</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMVN_i_T2_D" oneofinclass="2" oneof="12" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMVN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMVN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMVN_i_T2_Q" oneofinclass="2" oneof="12" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMVN" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMVN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMVN_i/T2A2_A.txt" mylink="aarch32.instrs.VMVN_i.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (cmode&lt;0&gt; == '1' &amp;&amp; cmode&lt;3:2&gt; != '11') || cmode&lt;3:1&gt; == '111' then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>('1', cmode, i:imm3:imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T3" oneof="6" id="iclass_t3" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMVN" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMVN_i/T3A3_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>x</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMVN_i_T3_D" oneofinclass="2" oneof="12" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMVN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMVN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMVN_i_T3_Q" oneofinclass="2" oneof="12" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMVN" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMVN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMVN_i/T3A3_A.txt" mylink="aarch32.instrs.VMVN_i.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (cmode&lt;0&gt; == '1' &amp;&amp; cmode&lt;3:2&gt; != '11') || cmode&lt;3:1&gt; == '111' then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>('1', cmode, i:imm3:imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMVN_i_A1_Q, VMVN_i_A2_Q, VMVN_i_A3_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1, A2 and A3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMVN_i_T1_Q, VMVN_i_T2_Q, VMVN_i_T3_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1, T2 and T3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMVN_i_A1_Q, VMVN_i_A2_Q, VMVN_i_A3_Q, VMVN_i_T1_Q, VMVN_i_T2_Q, VMVN_i_T3_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMVN_i_A1_Q, VMVN_i_A2_Q, VMVN_i_A3_Q, VMVN_i_T1_Q, VMVN_i_T2_Q, VMVN_i_T3_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMVN_i_A1_D, VMVN_i_A2_D, VMVN_i_A3_D, VMVN_i_T1_D, VMVN_i_T2_D, VMVN_i_T3_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMVN_i_A1_Q, VMVN_i_A2_Q, VMVN_i_A3_Q, VMVN_i_T1_Q, VMVN_i_T2_Q, VMVN_i_T3_Q" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is a constant of the specified type that is replicated to fill the destination register. For details of the range of constants available and the encoding of <syntax>&lt;imm&gt;</syntax>, see <xref linkend="CJAIDJDJ">Modified immediate constants in T32 and A32 Advanced SIMD instructions</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMVN_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = NOT(imm64);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vmvn_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VMVN_r" title="VMVN (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMVN" />
  </docvars>
  <heading>VMVN (register)</heading>
  <desc>
    <brief>
      <para>Vector Bitwise NOT (register)</para>
    </brief>
    <authored>
      <para>Vector Bitwise NOT (register) takes a value from a register, inverts the value of each bit, and places the result in the destination register. The registers can be either doubleword or quadword.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMVN" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VMVN_r/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMVN_r_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMVN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMVN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMVN_r_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMVN" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMVN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMVN_r/T1A1_A.txt" mylink="aarch32.instrs.VMVN_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size != '00' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMVN" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VMVN_r/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VMVN_r_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMVN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VMVN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMVN_r_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMVN" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VMVN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMVN_r/T1A1_A.txt" mylink="aarch32.instrs.VMVN_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size != '00' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMVN_r_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMVN_r_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMVN_r_A1_Q, VMVN_r_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMVN_r_A1_Q, VMVN_r_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>An optional data type. It is ignored by assemblers, and does not affect the encoding.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMVN_r_A1_Q, VMVN_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMVN_r_A1_Q, VMVN_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMVN_r_A1_D, VMVN_r_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMVN_r_A1_D, VMVN_r_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMVN_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = NOT(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vneg.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VNEG" title="VNEG -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VNEG" />
  </docvars>
  <heading>VNEG</heading>
  <desc>
    <brief>
      <para>Vector Negate</para>
    </brief>
    <authored>
      <para>Vector Negate negates each element in a vector, and places the results in a second vector. The floating-point version only inverts the sign bit.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check and is operating only on integer vector elements, then the following apply:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VNEG" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VNEG/A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="9" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VNEG_A1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VNEG" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VNEG</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;F:size&quot;) [F16,F32,S8,S16,S32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VNEG_A1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VNEG" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VNEG</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;F:size&quot;) [F16,F32,S8,S16,S32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VNEG/A1_A.txt" mylink="aarch32.instrs.VNEG.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; ((size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size == '00') then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>advsimd = TRUE;  floating_point = (F == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VNEG" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VNEG/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="o3" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VNEG_A2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VNEG" />
          <docvar key="mnemonic-fpdatasize" value="VNEG-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VNEG</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VNEG_A2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VNEG" />
          <docvar key="mnemonic-fpdatasize" value="VNEG-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VNEG</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VNEG_A2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VNEG" />
          <docvar key="mnemonic-fpdatasize" value="VNEG-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VNEG</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VNEG/A2_A.txt" mylink="aarch32.instrs.VNEG.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>advsimd = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VNEG" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VNEG/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="9" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VNEG_T1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VNEG" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VNEG</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;F:size&quot;) [F16,F32,S8,S16,S32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VNEG_T1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VNEG" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VNEG</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;F:size&quot;) [F16,F32,S8,S16,S32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VNEG/T1_A.txt" mylink="aarch32.instrs.VNEG.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; ((size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size == '00') then UNDEFINED;</line>
<line>if F == '1' &amp;&amp; size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>advsimd = TRUE;  floating_point = (F == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>F == '1' &amp;&amp; size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VNEG" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VNEG/T2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="o3" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VNEG_T2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VNEG" />
          <docvar key="mnemonic-fpdatasize" value="VNEG-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VNEG</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VNEG_T2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VNEG" />
          <docvar key="mnemonic-fpdatasize" value="VNEG-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VNEG</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VNEG_T2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VNEG" />
          <docvar key="mnemonic-fpdatasize" value="VNEG-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VNEG</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VNEG/T2_A.txt" mylink="aarch32.instrs.VNEG.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>advsimd = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VNEG_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNEG_A2_H, VNEG_T1_Q, VNEG_T2_H" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For encoding A2, T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNEG_A1_Q, VNEG_A2_H, VNEG_T1_Q, VNEG_T2_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNEG_A1_Q, VNEG_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="F:size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">F</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VNEG_A1_Q, VNEG_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNEG_A1_Q, VNEG_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNEG_A1_D, VNEG_A2_D, VNEG_T1_D, VNEG_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNEG_A1_D, VNEG_A2_D, VNEG_T1_D, VNEG_T2_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNEG_A2_H, VNEG_T2_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNEG_A2_H, VNEG_T2_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VNEG/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDOrVFPEnabled.2" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDOrVFPEnabled(boolean include_fpexc_check, boolean advsimd)">CheckAdvSIMDOrVFPEnabled</a>(TRUE, advsimd);</line>
<line>    if advsimd then  // Advanced SIMD instruction</line>
<line>        for r = 0 to regs-1</line>
<line>            for e = 0 to elements-1</line>
<line>                if floating_point then</line>
<line>                    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize]);</line>
<line>                else</line>
<line>                    result = -<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize]);</line>
<line>                    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result&lt;esize-1:0&gt;;</line>
<line>    else             // VFP instruction</line>
<line>        case esize of</line>
<line>            when 16 <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;);</line>
<line>            when 32 <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]);</line>
<line>            when 64 <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vnmla.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VNMLA" title="VNMLA -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VNMLA" />
  </docvars>
  <heading>VNMLA</heading>
  <desc>
    <brief>
      <para>Vector Negate Multiply Accumulate</para>
    </brief>
    <authored>
      <para>Vector Negate Multiply Accumulate multiplies together two floating-point register values, adds the negation of the floating-point value in the destination register to the negation of the product, and writes the result back to the destination register.</para>
      <note>
        <para>Arm recommends that software does not use the <instruction>VNMLA</instruction> instruction in the Round towards Plus Infinity and Round towards Minus Infinity rounding modes, because the rounding of the product and of the sum can change the result of the instruction in opposite directions, defeating the purpose of these rounding modes.</para>
      </note>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VNMLA" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VNMLA/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VNMLA_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VNMLA" />
          <docvar key="mnemonic-fpdatasize" value="VNMLA-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VNMLA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VNMLA_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VNMLA" />
          <docvar key="mnemonic-fpdatasize" value="VNMLA-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VNMLA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VNMLA_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VNMLA" />
          <docvar key="mnemonic-fpdatasize" value="VNMLA-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VNMLA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VNMLA/A1_A.txt" mylink="aarch32.instrs.VNMLA.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>vtype = if op == '1' then <a link="VFPNegMul_VNMLA" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLA</a> else <a link="VFPNegMul_VNMLS" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLS</a>;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VNMLA" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VNMLA/T1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VNMLA_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VNMLA" />
          <docvar key="mnemonic-fpdatasize" value="VNMLA-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VNMLA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VNMLA_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VNMLA" />
          <docvar key="mnemonic-fpdatasize" value="VNMLA-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VNMLA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VNMLA_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VNMLA" />
          <docvar key="mnemonic-fpdatasize" value="VNMLA-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VNMLA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VNMLA/T1_A.txt" mylink="aarch32.instrs.VNMLA.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>vtype = if op == '1' then <a link="VFPNegMul_VNMLA" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLA</a> else <a link="VFPNegMul_VNMLS" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLS</a>;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VNMLA_A1_H, VNMLA_T1_H" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNMLA_A1_H, VNMLA_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNMLA_A1_H, VNMLA_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNMLA_A1_H, VNMLA_T1_H" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNMLA_A1_H, VNMLA_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNMLA_A1_D, VNMLA_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNMLA_A1_D, VNMLA_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNMLA_A1_D, VNMLA_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VNMLA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    case esize of</line>
<line>        when 16</line>
<line>            product16 = <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[]);</line>
<line>            case vtype of</line>
<line>                when <a link="VFPNegMul_VNMLA" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLA</a>  <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = (<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]&lt;15:0&gt;),</line>
<line>                                                                <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(product16), FPSCR[]));</line>
<line>                when <a link="VFPNegMul_VNMLS" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLS</a>  <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = (<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]&lt;15:0&gt;),</line>
<line>                                                                product16, FPSCR[]));</line>
<line>                when <a link="VFPNegMul_VNMUL" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMUL</a>  <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] =  <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(product16);</line>
<line>        when 32</line>
<line>            product32 = <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n], <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[]);</line>
<line>            case vtype of</line>
<line>                when <a link="VFPNegMul_VNMLA" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLA</a>  <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]), <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(product32), FPSCR[]);</line>
<line>                when <a link="VFPNegMul_VNMLS" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLS</a>  <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]), product32, FPSCR[]);</line>
<line>                when <a link="VFPNegMul_VNMUL" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMUL</a>  <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(product32);</line>
<line>        when 64</line>
<line>            product64 = <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n], <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[]);</line>
<line>            case vtype of</line>
<line>                when <a link="VFPNegMul_VNMLA" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLA</a>  <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d]), <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(product64), FPSCR[]);</line>
<line>                when <a link="VFPNegMul_VNMLS" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLS</a>  <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d]), product64, FPSCR[]);</line>
<line>                when <a link="VFPNegMul_VNMUL" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMUL</a>  <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(product64);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vnmls.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VNMLS" title="VNMLS -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VNMLS" />
  </docvars>
  <heading>VNMLS</heading>
  <desc>
    <brief>
      <para>Vector Negate Multiply Subtract</para>
    </brief>
    <authored>
      <para>Vector Negate Multiply Subtract multiplies together two floating-point register values, adds the negation of the floating-point value in the destination register to the product, and writes the result back to the destination register.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VNMLS" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VNMLA/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VNMLS_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VNMLS" />
          <docvar key="mnemonic-fpdatasize" value="VNMLS-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VNMLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VNMLS_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VNMLS" />
          <docvar key="mnemonic-fpdatasize" value="VNMLS-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VNMLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VNMLS_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VNMLS" />
          <docvar key="mnemonic-fpdatasize" value="VNMLS-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VNMLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VNMLA/A1_A.txt" mylink="aarch32.instrs.VNMLA.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>vtype = if op == '1' then <a link="VFPNegMul_VNMLA" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLA</a> else <a link="VFPNegMul_VNMLS" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLS</a>;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VNMLS" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VNMLA/T1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VNMLS_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VNMLS" />
          <docvar key="mnemonic-fpdatasize" value="VNMLS-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VNMLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VNMLS_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VNMLS" />
          <docvar key="mnemonic-fpdatasize" value="VNMLS-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VNMLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VNMLS_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VNMLS" />
          <docvar key="mnemonic-fpdatasize" value="VNMLS-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VNMLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VNMLA/T1_A.txt" mylink="aarch32.instrs.VNMLA.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>vtype = if op == '1' then <a link="VFPNegMul_VNMLA" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLA</a> else <a link="VFPNegMul_VNMLS" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLS</a>;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VNMLS_A1_H, VNMLS_T1_H" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNMLS_A1_H, VNMLS_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNMLS_A1_H, VNMLS_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNMLS_A1_H, VNMLS_T1_H" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNMLS_A1_H, VNMLS_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNMLS_A1_D, VNMLS_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNMLS_A1_D, VNMLS_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNMLS_A1_D, VNMLS_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VNMLA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    case esize of</line>
<line>        when 16</line>
<line>            product16 = <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[]);</line>
<line>            case vtype of</line>
<line>                when <a link="VFPNegMul_VNMLA" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLA</a>  <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = (<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]&lt;15:0&gt;),</line>
<line>                                                                <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(product16), FPSCR[]));</line>
<line>                when <a link="VFPNegMul_VNMLS" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLS</a>  <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = (<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]&lt;15:0&gt;),</line>
<line>                                                                product16, FPSCR[]));</line>
<line>                when <a link="VFPNegMul_VNMUL" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMUL</a>  <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] =  <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(product16);</line>
<line>        when 32</line>
<line>            product32 = <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n], <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[]);</line>
<line>            case vtype of</line>
<line>                when <a link="VFPNegMul_VNMLA" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLA</a>  <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]), <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(product32), FPSCR[]);</line>
<line>                when <a link="VFPNegMul_VNMLS" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLS</a>  <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]), product32, FPSCR[]);</line>
<line>                when <a link="VFPNegMul_VNMUL" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMUL</a>  <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(product32);</line>
<line>        when 64</line>
<line>            product64 = <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n], <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[]);</line>
<line>            case vtype of</line>
<line>                when <a link="VFPNegMul_VNMLA" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLA</a>  <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d]), <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(product64), FPSCR[]);</line>
<line>                when <a link="VFPNegMul_VNMLS" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLS</a>  <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d]), product64, FPSCR[]);</line>
<line>                when <a link="VFPNegMul_VNMUL" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMUL</a>  <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(product64);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vnmul.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VNMUL" title="VNMUL -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VNMUL" />
  </docvars>
  <heading>VNMUL</heading>
  <desc>
    <brief>
      <para>Vector Negate Multiply</para>
    </brief>
    <authored>
      <para>Vector Negate Multiply multiplies together two floating-point register values, and writes the negation of the result to the destination register.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VNMUL" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VNMLA/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VNMUL_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VNMUL" />
          <docvar key="mnemonic-fpdatasize" value="VNMUL-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VNMUL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><text>{</text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VNMUL_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VNMUL" />
          <docvar key="mnemonic-fpdatasize" value="VNMUL-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VNMUL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><text>{</text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VNMUL_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VNMUL" />
          <docvar key="mnemonic-fpdatasize" value="VNMUL-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VNMUL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VNMLA/A2_A.txt" mylink="aarch32.instrs.VNMLA.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>vtype = <a link="VFPNegMul_VNMUL" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMUL</a>;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VNMUL" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VNMLA/T2_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VNMUL_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VNMUL" />
          <docvar key="mnemonic-fpdatasize" value="VNMUL-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VNMUL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><text>{</text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VNMUL_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VNMUL" />
          <docvar key="mnemonic-fpdatasize" value="VNMUL-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VNMUL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><text>{</text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VNMUL_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VNMUL" />
          <docvar key="mnemonic-fpdatasize" value="VNMUL-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VNMUL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VNMLA/T2_A.txt" mylink="aarch32.instrs.VNMLA.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>vtype = <a link="VFPNegMul_VNMUL" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMUL</a>;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VNMUL_A1_H, VNMUL_T1_H" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNMUL_A1_H, VNMUL_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNMUL_A1_H, VNMUL_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNMUL_A1_H, VNMUL_T1_H" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNMUL_A1_H, VNMUL_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNMUL_A1_D, VNMUL_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNMUL_A1_D, VNMUL_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VNMUL_A1_D, VNMUL_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VNMLA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    case esize of</line>
<line>        when 16</line>
<line>            product16 = <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[]);</line>
<line>            case vtype of</line>
<line>                when <a link="VFPNegMul_VNMLA" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLA</a>  <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = (<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]&lt;15:0&gt;),</line>
<line>                                                                <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(product16), FPSCR[]));</line>
<line>                when <a link="VFPNegMul_VNMLS" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLS</a>  <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = (<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]&lt;15:0&gt;),</line>
<line>                                                                product16, FPSCR[]));</line>
<line>                when <a link="VFPNegMul_VNMUL" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMUL</a>  <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] =  <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(product16);</line>
<line>        when 32</line>
<line>            product32 = <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n], <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[]);</line>
<line>            case vtype of</line>
<line>                when <a link="VFPNegMul_VNMLA" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLA</a>  <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]), <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(product32), FPSCR[]);</line>
<line>                when <a link="VFPNegMul_VNMLS" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLS</a>  <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]), product32, FPSCR[]);</line>
<line>                when <a link="VFPNegMul_VNMUL" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMUL</a>  <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(product32);</line>
<line>        when 64</line>
<line>            product64 = <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n], <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[]);</line>
<line>            case vtype of</line>
<line>                when <a link="VFPNegMul_VNMLA" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLA</a>  <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d]), <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(product64), FPSCR[]);</line>
<line>                when <a link="VFPNegMul_VNMLS" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLS</a>  <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d]), product64, FPSCR[]);</line>
<line>                when <a link="VFPNegMul_VNMUL" file="shared_pseudocode.xml" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMUL</a>  <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(product64);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vorn_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VORN_r" title="VORN (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VORN" />
  </docvars>
  <heading>VORN (register)</heading>
  <desc>
    <brief>
      <para>Vector bitwise OR NOT (register)</para>
    </brief>
    <authored>
      <para>Vector bitwise OR NOT (register) performs a bitwise OR NOT operation between two registers, and places the result in the destination register.  The operand and result registers can be quadword or doubleword.  They must all be the same size.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VORN" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VORN_r/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VORN_r_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VORN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VORN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VORN_r_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VORN" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VORN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VORN_r/T1A1_A.txt" mylink="aarch32.instrs.VORN_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VORN" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VORN_r/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VORN_r_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VORN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VORN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VORN_r_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VORN" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VORN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VORN_r/T1A1_A.txt" mylink="aarch32.instrs.VORN_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VORN_r_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORN_r_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORN_r_A1_Q, VORN_r_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORN_r_A1_Q, VORN_r_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>An optional data type. It is ignored by assemblers, and does not affect the encoding.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORN_r_A1_Q, VORN_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORN_r_A1_Q, VORN_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORN_r_A1_Q, VORN_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORN_r_A1_D, VORN_r_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORN_r_A1_D, VORN_r_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORN_r_A1_D, VORN_r_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VORN_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r] OR NOT(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vorn_vorr_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VORN_VORR_i" title="VORN (immediate) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="VORN" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VORR" />
  </docvars>
  <heading>VORN (immediate)</heading>
  <desc>
    <brief>Vector Bitwise OR NOT (immediate)</brief>
    <longer> performs a bitwise OR between a register value and the complement of an immediate value, and returns the result into the destination vector</longer>
  </desc>
  <aliasto refiform="vorr_i.xml" iformid="VORR_i">VORR (immediate)</aliasto>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VORR" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="2">
          <c>0</c>
          <c>x</c>
          <c>x</c>
          <c>1</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VORN_VORR_i_A1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VORN" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VORN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vorr_i.xml#VORR_i_A1_D">VORR</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #~</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VORN_VORR_i_A1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VORN" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VORN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vorr_i.xml#VORR_i_A1_Q">VORR</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #~</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VORR" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>x</c>
          <c>1</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VORN_VORR_i_A2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VORN" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VORN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vorr_i.xml#VORR_i_A2_D">VORR</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #~</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VORN_VORR_i_A2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VORN" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VORN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vorr_i.xml#VORR_i_A2_Q">VORR</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #~</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VORR" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="2">
          <c>0</c>
          <c>x</c>
          <c>x</c>
          <c>1</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VORN_VORR_i_T1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VORN" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VORN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vorr_i.xml#VORR_i_T1_D">VORR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #~</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VORN_VORR_i_T1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VORN" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VORN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vorr_i.xml#VORR_i_T1_Q">VORR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #~</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VORR" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>x</c>
          <c>1</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VORN_VORR_i_T2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VORN" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VORN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vorr_i.xml#VORR_i_T2_D">VORR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #~</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VORN_VORR_i_T2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VORN" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VORN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vorr_i.xml#VORR_i_T2_Q">VORR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #~</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VORN_VORR_i_A1_Q, VORN_VORR_i_A2_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For encoding A1 and A2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORN_VORR_i_T1_Q, VORN_VORR_i_T2_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORN_VORR_i_A1_Q, VORN_VORR_i_A2_Q, VORN_VORR_i_T1_Q, VORN_VORR_i_T2_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORN_VORR_i_A1_Q, VORN_VORR_i_A2_Q, VORN_VORR_i_T1_Q, VORN_VORR_i_T2_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORN_VORR_i_A1_D, VORN_VORR_i_A2_D, VORN_VORR_i_T1_D, VORN_VORR_i_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORN_VORR_i_A1_Q, VORN_VORR_i_A2_Q, VORN_VORR_i_T1_Q, VORN_VORR_i_T2_Q" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is a constant of the specified type that is replicated to fill the destination register. For details of the range of constants available and the encoding of <syntax>&lt;imm&gt;</syntax>, see <xref linkend="CJAIDJDJ">Modified immediate constants in T32 and A32 Advanced SIMD instructions</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="vorr_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VORR_i" title="VORR (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VORR" />
  </docvars>
  <heading>VORR (immediate)</heading>
  <desc>
    <brief>
      <para>Vector Bitwise OR (immediate)</para>
    </brief>
    <authored>
      <para>Vector Bitwise OR (immediate) performs a bitwise OR between a register value and an immediate value, and returns the result into the destination vector.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <syntaxnotes>
      <para>The I8, I64, and F32 data types are permitted as pseudo-instructions, if the immediate can be represented by this instruction, and are encoded using a permitted encoding of the I16 or I32 data type.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="1">
    <alias_list_intro>This instruction is used by the alias </alias_list_intro>
    <aliasref aliaspageid="VORN_VORR_i" aliasfile="vorn_vorr_i.xml" hover="Vector Bitwise OR NOT (immediate)" punct=".">
      <text>VORN (immediate)</text>
      <aliaspref>Never</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink />
      <text> below for details of when the alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VORR" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VORR_i/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="2">
          <c>0</c>
          <c>x</c>
          <c>x</c>
          <c>1</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VORR_i_A1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VORR</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VORR_i_A1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VORR</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VORR_i/T1A1_A.txt" mylink="aarch32.instrs.VORR_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if cmode&lt;0&gt; == '0' || cmode&lt;3:2&gt; == '11' then SEE "VMOV (immediate)";</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>('0', cmode, i:imm3:imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VORR" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VORR_i/T2A2_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>x</c>
          <c>1</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VORR_i_A2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VORR</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VORR_i_A2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VORR</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VORR_i/T2A2_A.txt" mylink="aarch32.instrs.VORR_i.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if cmode&lt;0&gt; == '0' || cmode&lt;3:2&gt; == '11' then SEE "VMOV (immediate)";</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>('0', cmode, i:imm3:imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VORR" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VORR_i/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="2">
          <c>0</c>
          <c>x</c>
          <c>x</c>
          <c>1</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VORR_i_T1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VORR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VORR_i_T1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VORR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I32 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VORR_i/T1A1_A.txt" mylink="aarch32.instrs.VORR_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if cmode&lt;0&gt; == '0' || cmode&lt;3:2&gt; == '11' then SEE "VMOV (immediate)";</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>('0', cmode, i:imm3:imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VORR" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VORR_i/T2A2_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="cmode" usename="1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>x</c>
          <c>1</c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="imm4" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VORR_i_T2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VORR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VORR_i_T2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VORR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I16 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VORR_i/T2A2_A.txt" mylink="aarch32.instrs.VORR_i.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if cmode&lt;0&gt; == '0' || cmode&lt;3:2&gt; == '11' then SEE "VMOV (immediate)";</line>
<line>if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>('0', cmode, i:imm3:imm4);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VORR_i_A1_Q, VORR_i_A2_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1 and A2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORR_i_T1_Q, VORR_i_T2_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORR_i_A1_Q, VORR_i_A2_Q, VORR_i_T1_Q, VORR_i_T2_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORR_i_A1_Q, VORR_i_A2_Q, VORR_i_T1_Q, VORR_i_T2_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORR_i_A1_D, VORR_i_A2_D, VORR_i_T1_D, VORR_i_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORR_i_A1_Q, VORR_i_A2_Q, VORR_i_T1_Q, VORR_i_T2_Q" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is a constant of the specified type that is replicated to fill the destination register. For details of the range of constants available and the encoding of <syntax>&lt;imm&gt;</syntax>, see <xref linkend="CJAIDJDJ">Modified immediate constants in T32 and A32 Advanced SIMD instructions</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VORR_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r] OR imm64;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vorr_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VORR_r" title="VORR (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VORR" />
  </docvars>
  <heading>VORR (register)</heading>
  <desc>
    <brief>
      <para>Vector bitwise OR (register)</para>
    </brief>
    <authored>
      <para>Vector bitwise OR (register) performs a bitwise OR operation between two registers, and places the result in the destination register. The operand and result registers can be quadword or doubleword. They must all be the same size.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="3">
    <alias_list_intro>This instruction is used by the aliases </alias_list_intro>
    <aliasref aliaspageid="VMOV_VORR_r" aliasfile="vmov_vorr_r.xml" hover="Copy between SIMD registers" punct=", ">
      <text>VMOV (register, SIMD)</text>
      <aliaspref>N:Vn == M:Vm</aliaspref>
    </aliasref>
    <aliasref aliaspageid="VRSHR_VORR_r" aliasfile="vrshr_vorr_r.xml" hover="Vector Rounding Shift Right" punct=" and ">
      <text>VRSHR (zero)</text>
      <aliaspref>Never</aliaspref>
    </aliasref>
    <aliasref aliaspageid="VSHR_VORR_r" aliasfile="vshr_vorr_r.xml" hover="Vector Shift Right" punct=".">
      <text>VSHR (zero)</text>
      <aliaspref>Never</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink />
      <text> below for details of when each alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VORR" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VORR_r/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VORR_r_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VORR</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VORR_r_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VORR</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VORR_r/T1A1_A.txt" mylink="aarch32.instrs.VORR_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VORR" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VORR_r/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VORR_r_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VORR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VORR_r_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VORR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VORR_r/T1A1_A.txt" mylink="aarch32.instrs.VORR_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VORR_r_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORR_r_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORR_r_A1_Q, VORR_r_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORR_r_A1_Q, VORR_r_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>An optional data type. It is ignored by assemblers, and does not affect the encoding.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORR_r_A1_Q, VORR_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORR_r_A1_Q, VORR_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORR_r_A1_Q, VORR_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORR_r_A1_D, VORR_r_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORR_r_A1_D, VORR_r_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VORR_r_A1_D, VORR_r_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VORR_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r] OR <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r];</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vpadal.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VPADAL" title="VPADAL -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VPADAL" />
  </docvars>
  <heading>VPADAL</heading>
  <desc>
    <brief>
      <para>Vector Pairwise Add and Accumulate Long</para>
    </brief>
    <authored>
      <para>Vector Pairwise Add and Accumulate Long adds adjacent pairs of elements of a vector, and accumulates the results into the elements of the destination vector.</para>
      <para>The vectors can be doubleword or quadword. The operand elements can be 8-bit, 16-bit, or 32-bit integers. The result elements are twice the length of the operand elements.</para>
      <para><image file="vpadal_doubleword_operation_for_data_type_s16.svg" label="VPADAL doubleword operation for data type S16"></image></para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VPADAL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VPADAL/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VPADAL_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VPADAL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VPADAL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;op:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VPADAL_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VPADAL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VPADAL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;op:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VPADAL/T1A1_A.txt" mylink="aarch32.instrs.VPADAL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (op == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VPADAL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VPADAL/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VPADAL_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VPADAL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VPADAL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;op:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VPADAL_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VPADAL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VPADAL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;op:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VPADAL/T1A1_A.txt" mylink="aarch32.instrs.VPADAL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (op == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VPADAL_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPADAL_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPADAL_A1_Q, VPADAL_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPADAL_A1_Q, VPADAL_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="op:size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">op</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VPADAL_A1_Q, VPADAL_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPADAL_A1_Q, VPADAL_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPADAL_A1_D, VPADAL_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPADAL_A1_D, VPADAL_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VPADAL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    h = elements DIV 2;</line>
<line></line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to h-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],2*e,esize];  op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],2*e+1,esize];</line>
<line>            result = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op1, unsigned) + <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op2, unsigned);</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,2*esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r],e,2*esize] + result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vpadd_f.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VPADD_f" title="VPADD (floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VPADD" />
  </docvars>
  <heading>VPADD (floating-point)</heading>
  <desc>
    <brief>
      <para>Vector Pairwise Add (floating-point)</para>
    </brief>
    <authored>
      <para>Vector Pairwise Add (floating-point) adds adjacent pairs of elements of two vectors, and places the results in the destination vector.</para>
      <para>The operands and result are doubleword vectors.</para>
      <para>The operand and result elements are floating-point numbers.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VPADD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VPADD_f/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VPADD_f_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VPADD" />
        </docvars>
        <asmtemplate><text>VPADD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VPADD_f/A1_A.txt" mylink="aarch32.instrs.VPADD_f.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VPADD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VPADD_f/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VPADD_f_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VPADD" />
        </docvars>
        <asmtemplate><text>VPADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VPADD_f/T1_A.txt" mylink="aarch32.instrs.VPADD_f.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>sz == '1' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VPADD_f_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPADD_f_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPADD_f_A1, VPADD_f_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPADD_f_A1, VPADD_f_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VPADD_f_A1, VPADD_f_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPADD_f_A1, VPADD_f_T1" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPADD_f_A1, VPADD_f_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VPADD_f/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    bits(64) dest;</line>
<line>    h = elements DIV 2;</line>
<line></line>
<line>    for e = 0 to h-1</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[dest,e,esize]   = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n],2*e,esize], <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n],2*e+1,esize],</line>
<line>                                     <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[dest,e+h,esize] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m],2*e,esize], <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m],2*e+1,esize],</line>
<line>                                     <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line></line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = dest;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vpadd_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VPADD_i" title="VPADD (integer) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VPADD" />
    <docvar key="simdvectorsize" value="double" />
  </docvars>
  <heading>VPADD (integer)</heading>
  <desc>
    <brief>
      <para>Vector Pairwise Add (integer)</para>
    </brief>
    <authored>
      <para>Vector Pairwise Add (integer) adds adjacent pairs of elements of two vectors, and places the results in the destination vector.</para>
      <para>The operands and result are doubleword vectors.</para>
      <para>The operand and result elements must all be the same type, and can be 8-bit, 16-bit, or 32-bit integers. There is no distinction between signed and unsigned integers.</para>
      <para><image file="vpadd_operation_for_data_type_i16.svg" label="VPADD doubleword operation for data type I16"></image></para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VPADD" />
        <docvar key="simdvectorsize" value="double" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VPADD_i/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VPADD_i_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VPADD" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <asmtemplate><text>VPADD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VPADD_i/T1A1_A.txt" mylink="aarch32.instrs.VPADD_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' || Q == '1' then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VPADD" />
        <docvar key="simdvectorsize" value="double" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VPADD_i/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VPADD_i_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VPADD" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <asmtemplate><text>VPADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VPADD_i/T1A1_A.txt" mylink="aarch32.instrs.VPADD_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' || Q == '1' then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VPADD_i_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPADD_i_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPADD_i_A1, VPADD_i_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPADD_i_A1, VPADD_i_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">I8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">I16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">I32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VPADD_i_A1, VPADD_i_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPADD_i_A1, VPADD_i_T1" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPADD_i_A1, VPADD_i_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VPADD_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    bits(64) dest;</line>
<line>    h = elements DIV 2;</line>
<line></line>
<line>    for e = 0 to h-1</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[dest,e,esize]   = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n],2*e,esize] + <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n],2*e+1,esize];</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[dest,e+h,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m],2*e,esize] + <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m],2*e+1,esize];</line>
<line></line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = dest;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vpaddl.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VPADDL" title="VPADDL -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VPADDL" />
  </docvars>
  <heading>VPADDL</heading>
  <desc>
    <brief>
      <para>Vector Pairwise Add Long</para>
    </brief>
    <authored>
      <para>Vector Pairwise Add Long adds adjacent pairs of elements of two vectors, and places the results in the destination vector.</para>
      <para>The vectors can be doubleword or quadword. The operand elements can be 8-bit, 16-bit, or 32-bit integers. The result elements are twice the length of the operand elements.</para>
      <para><image file="vpaddl_doubleword_operation_for_data_type_s16.svg" label="VPADDL doubleword operation for data type S16"></image></para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VPADDL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VPADDL/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VPADDL_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VPADDL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VPADDL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;op:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VPADDL_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VPADDL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VPADDL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;op:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VPADDL/T1A1_A.txt" mylink="aarch32.instrs.VPADDL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (op == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VPADDL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VPADDL/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VPADDL_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VPADDL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VPADDL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;op:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VPADDL_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VPADDL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VPADDL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;op:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VPADDL/T1A1_A.txt" mylink="aarch32.instrs.VPADDL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (op == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VPADDL_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPADDL_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPADDL_A1_Q, VPADDL_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPADDL_A1_Q, VPADDL_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="op:size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">op</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VPADDL_A1_Q, VPADDL_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPADDL_A1_Q, VPADDL_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPADDL_A1_D, VPADDL_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPADDL_A1_D, VPADDL_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VPADDL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    h = elements DIV 2;</line>
<line></line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to h-1</line>
<line>            op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],2*e,esize];  op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],2*e+1,esize];</line>
<line>            result = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op1, unsigned) + <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op2, unsigned);</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,2*esize] = result&lt;2*esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vpmax_f.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VPMAX_f" title="VPMAX (floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VPMAX" />
  </docvars>
  <heading>VPMAX (floating-point)</heading>
  <desc>
    <brief>
      <para>Vector Pairwise Maximum (floating-point)</para>
    </brief>
    <authored>
      <para>Vector Pairwise Maximum compares adjacent pairs of elements in two doubleword vectors, and copies the larger of each pair into the corresponding element in the destination doubleword vector.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VPMAX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VPMAX_f/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VPMAX_f_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VPMAX" />
        </docvars>
        <asmtemplate><text>VPMAX</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VPMAX_f/A1_A.txt" mylink="aarch32.instrs.VPMAX_f.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>maximum = (op == '0');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VPMAX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VPMAX_f/T1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VPMAX_f_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VPMAX" />
        </docvars>
        <asmtemplate><text>VPMAX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VPMAX_f/T1_A.txt" mylink="aarch32.instrs.VPMAX_f.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>maximum = (op == '0');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>sz == '1' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VPMAX_f_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPMAX_f_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPMAX_f_A1, VPMAX_f_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPMAX_f_A1, VPMAX_f_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VPMAX_f_A1, VPMAX_f_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPMAX_f_A1, VPMAX_f_T1" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPMAX_f_A1, VPMAX_f_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VPMAX_f/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    bits(64) dest;</line>
<line>    h = elements DIV 2;</line>
<line></line>
<line>    for e = 0 to h-1</line>
<line>        op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n],2*e,esize];  op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n],2*e+1,esize];</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[dest,e,esize] = (if maximum then <a link="impl-shared.FPMax.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(op1,op2,<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>())</line>
<line>                              else <a link="impl-shared.FPMin.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(op1,op2,<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>()));</line>
<line>        op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m],2*e,esize];  op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m],2*e+1,esize];</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[dest,e+h,esize] = (if maximum then <a link="impl-shared.FPMax.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(op1,op2,<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>())</line>
<line>                                else <a link="impl-shared.FPMin.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(op1,op2,<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>()));</line>
<line></line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = dest;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vpmax_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VPMAX_i" title="VPMAX (integer) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VPMAX" />
  </docvars>
  <heading>VPMAX (integer)</heading>
  <desc>
    <brief>
      <para>Vector Pairwise Maximum (integer)</para>
    </brief>
    <authored>
      <para>Vector Pairwise Maximum compares adjacent pairs of elements in two doubleword vectors, and copies the larger of each pair into the corresponding element in the destination doubleword vector.</para>
      <para><image file="vpmax_operation_for_data_type_s16_or_u16.svg" label="VPMAX doubleword operation for data type S16 or U16"></image></para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VPMAX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VPMAX_i/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VPMAX_i_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VPMAX" />
        </docvars>
        <asmtemplate><text>VPMAX</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VPMAX_i/T1A1_A.txt" mylink="aarch32.instrs.VPMAX_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>maximum = (op == '0');  unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VPMAX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VPMAX_i/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VPMAX_i_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VPMAX" />
        </docvars>
        <asmtemplate><text>VPMAX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VPMAX_i/T1A1_A.txt" mylink="aarch32.instrs.VPMAX_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>maximum = (op == '0');  unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VPMAX_i_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPMAX_i_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPMAX_i_A1, VPMAX_i_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPMAX_i_A1, VPMAX_i_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VPMAX_i_A1, VPMAX_i_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPMAX_i_A1, VPMAX_i_T1" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPMAX_i_A1, VPMAX_i_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VPMAX_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    bits(64) dest;</line>
<line>    h = elements DIV 2;</line>
<line></line>
<line>    for e = 0 to h-1</line>
<line>        op1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n],2*e,esize], unsigned);</line>
<line>        op2 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n],2*e+1,esize], unsigned);</line>
<line>        result = if maximum then <a link="impl-shared.Max.2" file="shared_pseudocode.xml" hover="function: integer Max(integer a, integer b)">Max</a>(op1,op2) else <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(op1,op2);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[dest,e,esize] = result&lt;esize-1:0&gt;;</line>
<line>        op1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m],2*e,esize], unsigned);</line>
<line>        op2 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m],2*e+1,esize], unsigned);</line>
<line>        result = if maximum then <a link="impl-shared.Max.2" file="shared_pseudocode.xml" hover="function: integer Max(integer a, integer b)">Max</a>(op1,op2) else <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(op1,op2);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[dest,e+h,esize] = result&lt;esize-1:0&gt;;</line>
<line></line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = dest;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vpmin_f.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VPMIN_f" title="VPMIN (floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VPMIN" />
  </docvars>
  <heading>VPMIN (floating-point)</heading>
  <desc>
    <brief>
      <para>Vector Pairwise Minimum (floating-point)</para>
    </brief>
    <authored>
      <para>Vector Pairwise Minimum compares adjacent pairs of elements in two doubleword vectors, and copies the smaller of each pair into the corresponding element in the destination doubleword vector.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VPMIN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VPMAX_f/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VPMIN_f_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VPMIN" />
        </docvars>
        <asmtemplate><text>VPMIN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VPMAX_f/A1_A.txt" mylink="aarch32.instrs.VPMAX_f.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>maximum = (op == '0');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VPMIN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VPMAX_f/T1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VPMIN_f_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VPMIN" />
        </docvars>
        <asmtemplate><text>VPMIN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VPMAX_f/T1_A.txt" mylink="aarch32.instrs.VPMAX_f.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>maximum = (op == '0');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>sz == '1' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VPMIN_f_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPMIN_f_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPMIN_f_A1, VPMIN_f_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPMIN_f_A1, VPMIN_f_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VPMIN_f_A1, VPMIN_f_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPMIN_f_A1, VPMIN_f_T1" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPMIN_f_A1, VPMIN_f_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VPMAX_f/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    bits(64) dest;</line>
<line>    h = elements DIV 2;</line>
<line></line>
<line>    for e = 0 to h-1</line>
<line>        op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n],2*e,esize];  op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n],2*e+1,esize];</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[dest,e,esize] = (if maximum then <a link="impl-shared.FPMax.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(op1,op2,<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>())</line>
<line>                              else <a link="impl-shared.FPMin.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(op1,op2,<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>()));</line>
<line>        op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m],2*e,esize];  op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m],2*e+1,esize];</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[dest,e+h,esize] = (if maximum then <a link="impl-shared.FPMax.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(op1,op2,<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>())</line>
<line>                                else <a link="impl-shared.FPMin.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</a>(op1,op2,<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>()));</line>
<line></line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = dest;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vpmin_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VPMIN_i" title="VPMIN (integer) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VPMIN" />
  </docvars>
  <heading>VPMIN (integer)</heading>
  <desc>
    <brief>
      <para>Vector Pairwise Minimum (integer)</para>
    </brief>
    <authored>
      <para>Vector Pairwise Minimum compares adjacent pairs of elements in two doubleword vectors, and copies the smaller of each pair into the corresponding element in the destination doubleword vector.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VPMIN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VPMAX_i/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VPMIN_i_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VPMIN" />
        </docvars>
        <asmtemplate><text>VPMIN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VPMAX_i/T1A1_A.txt" mylink="aarch32.instrs.VPMAX_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>maximum = (op == '0');  unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VPMIN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VPMAX_i/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VPMIN_i_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VPMIN" />
        </docvars>
        <asmtemplate><text>VPMIN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VPMAX_i/T1A1_A.txt" mylink="aarch32.instrs.VPMAX_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>maximum = (op == '0');  unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VPMIN_i_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPMIN_i_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPMIN_i_A1, VPMIN_i_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPMIN_i_A1, VPMIN_i_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VPMIN_i_A1, VPMIN_i_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPMIN_i_A1, VPMIN_i_T1" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPMIN_i_A1, VPMIN_i_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VPMAX_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    bits(64) dest;</line>
<line>    h = elements DIV 2;</line>
<line></line>
<line>    for e = 0 to h-1</line>
<line>        op1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n],2*e,esize], unsigned);</line>
<line>        op2 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n],2*e+1,esize], unsigned);</line>
<line>        result = if maximum then <a link="impl-shared.Max.2" file="shared_pseudocode.xml" hover="function: integer Max(integer a, integer b)">Max</a>(op1,op2) else <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(op1,op2);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[dest,e,esize] = result&lt;esize-1:0&gt;;</line>
<line>        op1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m],2*e,esize], unsigned);</line>
<line>        op2 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m],2*e+1,esize], unsigned);</line>
<line>        result = if maximum then <a link="impl-shared.Max.2" file="shared_pseudocode.xml" hover="function: integer Max(integer a, integer b)">Max</a>(op1,op2) else <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(op1,op2);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[dest,e+h,esize] = result&lt;esize-1:0&gt;;</line>
<line></line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = dest;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vpop_vldm.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VPOP_VLDM" title="VPOP -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="VPOP" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="ldmstm-mode" value="inc-after" />
    <docvar key="mnemonic" value="VLDM" />
  </docvars>
  <heading>VPOP</heading>
  <desc>
    <brief>
      <para>Pop SIMD&amp;FP registers from stack</para>
    </brief>
    <authored>
      <para>Pop SIMD&amp;FP registers from stack loads multiple consecutive Advanced SIMD and floating-point register file registers from the stack.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <aliasto refiform="vldm.xml" iformid="VLDM">VLDM, VLDMDB, VLDMIA</aliasto>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="fpdatasize" value="doubleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1" settings="1" psbits="1">
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="7" name="imm8&lt;7:1&gt;" usename="1">
          <c colspan="7"></c>
        </box>
        <box hibit="0" name="imm8&lt;0&gt;" usename="1" settings="1">
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="VPOP_VLDM_A1" oneofinclass="1" oneof="4" label="Increment After">
        <docvars>
          <docvar key="alias_mnemonic" value="VPOP" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="inc-after" />
          <docvar key="mnemonic" value="VLDM" />
          <docvar key="mnemonic-fpdatasize" value="VLDM-doubleprec" />
        </docvars>
        <asmtemplate><text>VPOP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vldm.xml#VLDM_A1">VLDM</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> SP!, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="fpdatasize" value="singleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1" settings="1" psbits="1">
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="VPOP_VLDM_A2" oneofinclass="1" oneof="4" label="Increment After">
        <docvars>
          <docvar key="alias_mnemonic" value="VPOP" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="inc-after" />
          <docvar key="mnemonic" value="VLDM" />
          <docvar key="mnemonic-fpdatasize" value="VLDM-singleprec" />
        </docvars>
        <asmtemplate><text>VPOP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vldm.xml#VLDM_A2">VLDM</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> SP!, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="fpdatasize" value="doubleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1" settings="1" psbits="1">
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="7" name="imm8&lt;7:1&gt;" usename="1">
          <c colspan="7"></c>
        </box>
        <box hibit="0" name="imm8&lt;0&gt;" usename="1" settings="1">
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="VPOP_VLDM_T1" oneofinclass="1" oneof="4" label="Increment After">
        <docvars>
          <docvar key="alias_mnemonic" value="VPOP" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="ldmstm-mode" value="inc-after" />
          <docvar key="mnemonic" value="VLDM" />
          <docvar key="mnemonic-fpdatasize" value="VLDM-doubleprec" />
        </docvars>
        <asmtemplate><text>VPOP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vldm.xml#VLDM_T1">VLDM</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> SP!, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="fpdatasize" value="singleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1" settings="1" psbits="1">
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="VPOP_VLDM_T2" oneofinclass="1" oneof="4" label="Increment After">
        <docvars>
          <docvar key="alias_mnemonic" value="VPOP" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="ldmstm-mode" value="inc-after" />
          <docvar key="mnemonic" value="VLDM" />
          <docvar key="mnemonic-fpdatasize" value="VLDM-singleprec" />
        </docvars>
        <asmtemplate><text>VPOP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vldm.xml#VLDM_T2">VLDM</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> SP!, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VPOP_VLDM_A1, VPOP_VLDM_A2, VPOP_VLDM_T1, VPOP_VLDM_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPOP_VLDM_A1, VPOP_VLDM_A2, VPOP_VLDM_T1, VPOP_VLDM_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPOP_VLDM_A1, VPOP_VLDM_A2, VPOP_VLDM_T1, VPOP_VLDM_T2" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>An optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers being transferred.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPOP_VLDM_A2, VPOP_VLDM_T2" symboldefcount="1">
      <symbol link="sa_sreglist">&lt;sreglist&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the list of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred. The first register in the list is encoded in "Vd:D", and "imm8" is set to the number of registers in the list. The list must contain at least one register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPOP_VLDM_A1, VPOP_VLDM_T1" symboldefcount="1">
      <symbol link="sa_dreglist">&lt;dreglist&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the list of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred. The first register in the list is encoded in "D:Vd", and "imm8" is set to twice the number of registers in the list. The list must contain at least one register, and must not contain more than 16 registers.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="vpush_vstm.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VPUSH_VSTM" title="VPUSH -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="VPUSH" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="ldmstm-mode" value="dec-before" />
    <docvar key="mnemonic" value="VSTMDB" />
  </docvars>
  <heading>VPUSH</heading>
  <desc>
    <brief>
      <para>Push SIMD&amp;FP registers to stack</para>
    </brief>
    <authored>
      <para>Push SIMD&amp;FP registers to stack stores multiple consecutive registers from the Advanced SIMD and floating-point register file to the stack.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <aliasto refiform="vstm.xml" iformid="VSTM">VSTM, VSTMDB, VSTMIA</aliasto>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="fpdatasize" value="doubleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="7" name="imm8&lt;7:1&gt;" usename="1">
          <c colspan="7"></c>
        </box>
        <box hibit="0" name="imm8&lt;0&gt;" usename="1" settings="1">
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="VPUSH_VSTMDB_A1" oneofinclass="1" oneof="4" label="Decrement Before">
        <docvars>
          <docvar key="alias_mnemonic" value="VPUSH" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="VSTMDB" />
          <docvar key="mnemonic-fpdatasize" value="VSTMDB-doubleprec" />
        </docvars>
        <asmtemplate><text>VPUSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vstm.xml#VSTMDB_A1">VSTMDB</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> SP!, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="fpdatasize" value="singleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="VPUSH_VSTMDB_A2" oneofinclass="1" oneof="4" label="Decrement Before">
        <docvars>
          <docvar key="alias_mnemonic" value="VPUSH" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="VSTMDB" />
          <docvar key="mnemonic-fpdatasize" value="VSTMDB-singleprec" />
        </docvars>
        <asmtemplate><text>VPUSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vstm.xml#VSTMDB_A2">VSTMDB</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> SP!, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="fpdatasize" value="doubleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="7" name="imm8&lt;7:1&gt;" usename="1">
          <c colspan="7"></c>
        </box>
        <box hibit="0" name="imm8&lt;0&gt;" usename="1" settings="1">
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="VPUSH_VSTMDB_T1" oneofinclass="1" oneof="4" label="Decrement Before">
        <docvars>
          <docvar key="alias_mnemonic" value="VPUSH" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="VSTMDB" />
          <docvar key="mnemonic-fpdatasize" value="VSTMDB-doubleprec" />
        </docvars>
        <asmtemplate><text>VPUSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vstm.xml#VSTMDB_T1">VSTMDB</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> SP!, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="fpdatasize" value="singleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="VPUSH_VSTMDB_T2" oneofinclass="1" oneof="4" label="Decrement Before">
        <docvars>
          <docvar key="alias_mnemonic" value="VPUSH" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="VSTMDB" />
          <docvar key="mnemonic-fpdatasize" value="VSTMDB-singleprec" />
        </docvars>
        <asmtemplate><text>VPUSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vstm.xml#VSTMDB_T2">VSTMDB</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> SP!, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VPUSH_VSTMDB_A1, VPUSH_VSTMDB_A2, VPUSH_VSTMDB_T1, VPUSH_VSTMDB_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPUSH_VSTMDB_A1, VPUSH_VSTMDB_A2, VPUSH_VSTMDB_T1, VPUSH_VSTMDB_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPUSH_VSTMDB_A1, VPUSH_VSTMDB_A2, VPUSH_VSTMDB_T1, VPUSH_VSTMDB_T2" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>An optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers being transferred.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPUSH_VSTMDB_A2, VPUSH_VSTMDB_T2" symboldefcount="1">
      <symbol link="sa_sreglist">&lt;sreglist&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the list of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred. The first register in the list is encoded in "Vd:D", and "imm8" is set to the number of registers in the list. The list must contain at least one register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPUSH_VSTMDB_A1, VPUSH_VSTMDB_T1" symboldefcount="1">
      <symbol link="sa_dreglist">&lt;dreglist&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the list of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred. The first register in the list is encoded in "D:Vd", and "imm8" is set to twice the number of registers in the list. The list must contain at least one register, and must not contain more than 16 registers.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="vqabs.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VQABS" title="VQABS -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VQABS" />
  </docvars>
  <heading>VQABS</heading>
  <desc>
    <brief>
      <para>Vector Saturating Absolute</para>
    </brief>
    <authored>
      <para>Vector Saturating Absolute takes the absolute value of each element in a vector, and places the results in the destination vector.</para>
      <para>If any of the results overflow, they are saturated. The cumulative saturation bit, <xref linkend="AArch32.fpscr">FPSCR</xref>.QC, is set if saturation occurs. For details see <xref linkend="BEIHABGJ">Pseudocode details of saturation</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VQABS" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VQABS/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQABS_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQABS" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQABS</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQABS_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQABS" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQABS</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQABS/T1A1_A.txt" mylink="aarch32.instrs.VQABS.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VQABS" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VQABS/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQABS_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQABS" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQABS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQABS_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQABS" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQABS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQABS/T1A1_A.txt" mylink="aarch32.instrs.VQABS.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VQABS_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQABS_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQABS_A1_Q, VQABS_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQABS_A1_Q, VQABS_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQABS_A1_Q, VQABS_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQABS_A1_Q, VQABS_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQABS_A1_D, VQABS_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQABS_A1_D, VQABS_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VQABS/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            result = <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize]));</line>
<line>            boolean sat;</line>
<line>            (<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize], sat) = <a link="impl-shared.SignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(result, esize);</line>
<line>            if sat then FPSCR.QC = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vqadd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VQADD" title="VQADD -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VQADD" />
  </docvars>
  <heading>VQADD</heading>
  <desc>
    <brief>
      <para>Vector Saturating Add</para>
    </brief>
    <authored>
      <para>Vector Saturating Add adds the values of corresponding elements of two vectors, and places the results in the destination vector.</para>
      <para>If any of the results overflow, they are saturated. The cumulative saturation bit, <xref linkend="AArch32.fpscr">FPSCR</xref>.QC, is set if saturation occurs. For details see <xref linkend="BEIHABGJ">Pseudocode details of saturation</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VQADD" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VQADD/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQADD_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQADD" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQADD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQADD_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQADD" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQADD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQADD/T1A1_A.txt" mylink="aarch32.instrs.VQADD.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VQADD" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VQADD/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQADD_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQADD" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQADD_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQADD" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQADD/T1A1_A.txt" mylink="aarch32.instrs.VQADD.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VQADD_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQADD_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQADD_A1_Q, VQADD_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQADD_A1_Q, VQADD_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">S64</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">U64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQADD_A1_Q, VQADD_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQADD_A1_Q, VQADD_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQADD_A1_Q, VQADD_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQADD_A1_D, VQADD_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQADD_A1_D, VQADD_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQADD_A1_D, VQADD_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VQADD/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            sum = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize], unsigned) + <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], unsigned);</line>
<line>            boolean sat;</line>
<line>            (<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize], sat) = <a link="impl-shared.SatQ.3" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(sum, esize, unsigned);</line>
<line>            if sat then FPSCR.QC = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vqdmlal.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VQDMLAL" title="VQDMLAL -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VQDMLAL" />
  </docvars>
  <heading>VQDMLAL</heading>
  <desc>
    <brief>
      <para>Vector Saturating Doubling Multiply Accumulate Long</para>
    </brief>
    <authored>
      <para>Vector Saturating Doubling Multiply Accumulate Long multiplies corresponding elements in two doubleword vectors, doubles the products, and accumulates the results into the elements of a quadword vector.</para>
      <para>The second operand can be a scalar instead of a vector. For more information about scalars see <xref linkend="Cjaibjhd">Advanced SIMD scalars</xref>.</para>
      <para>If any of the results overflow, they are saturated. The cumulative saturation bit, <xref linkend="AArch32.fpscr">FPSCR</xref>.QC, is set if saturation occurs. For details see <xref linkend="BEIHABGJ">Pseudocode details of saturation</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VQDMLAL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VQDMLAL/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQDMLAL_A1" oneofinclass="1" oneof="4" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQDMLAL" />
        </docvars>
        <asmtemplate><text>VQDMLAL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQDMLAL/T1A1_A.txt" mylink="aarch32.instrs.VQDMLAL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>add = (op == '0');</line>
<line>scalar_form = FALSE;  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VQDMLAL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VQDMLAL/T2A2_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQDMLAL_A2" oneofinclass="1" oneof="4" label="A2">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQDMLAL" />
        </docvars>
        <asmtemplate><text>VQDMLAL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_1" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-3] (field &quot;M:Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQDMLAL/T2A2_A.txt" mylink="aarch32.instrs.VQDMLAL.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>add = (op == '0');</line>
<line>scalar_form = TRUE;  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VQDMLAL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VQDMLAL/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQDMLAL_T1" oneofinclass="1" oneof="4" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQDMLAL" />
        </docvars>
        <asmtemplate><text>VQDMLAL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQDMLAL/T1A1_A.txt" mylink="aarch32.instrs.VQDMLAL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>add = (op == '0');</line>
<line>scalar_form = FALSE;  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VQDMLAL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VQDMLAL/T2A2_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQDMLAL_T2" oneofinclass="1" oneof="4" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQDMLAL" />
        </docvars>
        <asmtemplate><text>VQDMLAL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_1" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-3] (field &quot;M:Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQDMLAL/T2A2_A.txt" mylink="aarch32.instrs.VQDMLAL.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>add = (op == '0');</line>
<line>scalar_form = TRUE;  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VQDMLAL_A1, VQDMLAL_A2" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1 and A2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMLAL_T1, VQDMLAL_T2" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMLAL_A1, VQDMLAL_A2, VQDMLAL_T1, VQDMLAL_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMLAL_A1, VQDMLAL_A2, VQDMLAL_T1, VQDMLAL_T2" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQDMLAL_A1, VQDMLAL_A2, VQDMLAL_T1, VQDMLAL_T2" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMLAL_A1, VQDMLAL_A2, VQDMLAL_T1, VQDMLAL_T2" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMLAL_A1, VQDMLAL_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>For encoding A1 and T1: is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMLAL_A2, VQDMLAL_T2" symboldefcount="2">
      <symbol link="sa_dm_1">&lt;Dm&gt;</symbol>
      <account encodedin="Vm&lt;2:0&gt;">
        <intro>
          <para>For encoding A2 and T2: is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "Vm&lt;2:0&gt;" field when <syntax>&lt;dt&gt;</syntax> is S16, otherwise the "Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMLAL_A2, VQDMLAL_T2" symboldefcount="1">
      <symbol link="sa_index">&lt;index&gt;</symbol>
      <account encodedin="M:Vm&lt;3&gt;">
        <intro>
          <para>Is the element index in the range 0 to 3, encoded in the "M:Vm&lt;3&gt;" field when <syntax>&lt;dt&gt;</syntax> is S16, otherwise in range 0 to 1, encoded in the "M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VQDMLAL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    integer op2;</line>
<line>    if scalar_form then op2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m],index,esize]);</line>
<line>    for e = 0 to elements-1</line>
<line>        if !scalar_form then op2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m],e,esize]);</line>
<line>        op1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n],e,esize]);</line>
<line>        // The following only saturates if both op1 and op2 equal -(2^(esize-1))</line>
<line>        (product, sat1) = <a link="impl-shared.SignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2*op1*op2, 2*esize);</line>
<line>        integer result;</line>
<line>        if add then</line>
<line>            result = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[d&gt;&gt;1],e,2*esize]) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(product);</line>
<line>        else</line>
<line>            result = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[d&gt;&gt;1],e,2*esize]) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(product);</line>
<line>        boolean sat2;</line>
<line>        (<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize], sat2) = <a link="impl-shared.SignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(result, 2*esize);</line>
<line>        if sat1 || sat2 then FPSCR.QC = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vqdmlsl.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VQDMLSL" title="VQDMLSL -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VQDMLSL" />
  </docvars>
  <heading>VQDMLSL</heading>
  <desc>
    <brief>
      <para>Vector Saturating Doubling Multiply Subtract Long</para>
    </brief>
    <authored>
      <para>Vector Saturating Doubling Multiply Subtract Long multiplies corresponding elements in two doubleword vectors, subtracts double the products from corresponding elements of a quadword vector, and places the results in the same quadword vector.</para>
      <para>The second operand can be a scalar instead of a vector. For more information about scalars see <xref linkend="Cjaibjhd">Advanced SIMD scalars</xref>.</para>
      <para>If any of the results overflow, they are saturated. The cumulative saturation bit, <xref linkend="AArch32.fpscr">FPSCR</xref>.QC, is set if saturation occurs. For details see <xref linkend="BEIHABGJ">Pseudocode details of saturation</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VQDMLSL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VQDMLSL/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQDMLSL_A1" oneofinclass="1" oneof="4" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQDMLSL" />
        </docvars>
        <asmtemplate><text>VQDMLSL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQDMLSL/T1A1_A.txt" mylink="aarch32.instrs.VQDMLSL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>add = (op == '0');</line>
<line>scalar_form = FALSE;  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VQDMLSL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VQDMLSL/T2A2_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQDMLSL_A2" oneofinclass="1" oneof="4" label="A2">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQDMLSL" />
        </docvars>
        <asmtemplate><text>VQDMLSL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_1" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-3] (field &quot;M:Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQDMLSL/T2A2_A.txt" mylink="aarch32.instrs.VQDMLSL.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>add = (op == '0');</line>
<line>scalar_form = TRUE;  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VQDMLSL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VQDMLSL/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQDMLSL_T1" oneofinclass="1" oneof="4" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQDMLSL" />
        </docvars>
        <asmtemplate><text>VQDMLSL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQDMLSL/T1A1_A.txt" mylink="aarch32.instrs.VQDMLSL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>add = (op == '0');</line>
<line>scalar_form = FALSE;  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VQDMLSL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VQDMLSL/T2A2_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQDMLSL_T2" oneofinclass="1" oneof="4" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQDMLSL" />
        </docvars>
        <asmtemplate><text>VQDMLSL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_1" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-3] (field &quot;M:Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQDMLSL/T2A2_A.txt" mylink="aarch32.instrs.VQDMLSL.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>add = (op == '0');</line>
<line>scalar_form = TRUE;  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VQDMLSL_A1, VQDMLSL_A2" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1 and A2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMLSL_T1, VQDMLSL_T2" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMLSL_A1, VQDMLSL_A2, VQDMLSL_T1, VQDMLSL_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMLSL_A1, VQDMLSL_A2, VQDMLSL_T1, VQDMLSL_T2" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQDMLSL_A1, VQDMLSL_A2, VQDMLSL_T1, VQDMLSL_T2" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMLSL_A1, VQDMLSL_A2, VQDMLSL_T1, VQDMLSL_T2" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMLSL_A1, VQDMLSL_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>For encoding A1 and T1: is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMLSL_A2, VQDMLSL_T2" symboldefcount="2">
      <symbol link="sa_dm_1">&lt;Dm&gt;</symbol>
      <account encodedin="Vm&lt;2:0&gt;">
        <intro>
          <para>For encoding A2 and T2: is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "Vm&lt;2:0&gt;" field when <syntax>&lt;dt&gt;</syntax> is S16, otherwise the "Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMLSL_A2, VQDMLSL_T2" symboldefcount="1">
      <symbol link="sa_index">&lt;index&gt;</symbol>
      <account encodedin="M:Vm&lt;3&gt;">
        <intro>
          <para>Is the element index in the range 0 to 3, encoded in the "M:Vm&lt;3&gt;" field when <syntax>&lt;dt&gt;</syntax> is S16, otherwise in range 0 to 1, encoded in the "M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VQDMLSL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    integer op2;</line>
<line>    if scalar_form then op2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m],index,esize]);</line>
<line>    for e = 0 to elements-1</line>
<line>        if !scalar_form then op2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m],e,esize]);</line>
<line>        op1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n],e,esize]);</line>
<line>        // The following only saturates if both op1 and op2 equal -(2^(esize-1))</line>
<line>        (product, sat1) = <a link="impl-shared.SignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2*op1*op2, 2*esize);</line>
<line>        integer result;</line>
<line>        if add then</line>
<line>            result = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[d&gt;&gt;1],e,2*esize]) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(product);</line>
<line>        else</line>
<line>            result = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[d&gt;&gt;1],e,2*esize]) - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(product);</line>
<line>        boolean sat2;</line>
<line>        (<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize], sat2) = <a link="impl-shared.SignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(result, 2*esize);</line>
<line>        if sat1 || sat2 then FPSCR.QC = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vqdmulh.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VQDMULH" title="VQDMULH -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VQDMULH" />
  </docvars>
  <heading>VQDMULH</heading>
  <desc>
    <brief>
      <para>Vector Saturating Doubling Multiply Returning High Half</para>
    </brief>
    <authored>
      <para>Vector Saturating Doubling Multiply Returning High Half multiplies corresponding elements in two vectors, doubles the results, and places the most significant half of the final results in the destination vector. The results are truncated, for rounded results see <xref linkend="A32T32-fpsimd.instructions.VQRDMULH">VQRDMULH</xref>.</para>
      <para>The second operand can be a scalar instead of a vector. For more information about scalars see <xref linkend="Cjaibjhd">Advanced SIMD scalars</xref>.</para>
      <para>If any of the results overflow, they are saturated. The cumulative saturation bit, <xref linkend="AArch32.fpscr">FPSCR</xref>.QC, is set if saturation occurs. For details see <xref linkend="BEIHABGJ">Pseudocode details of saturation</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VQDMULH" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VQDMULH/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQDMULH_A1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQDMULH" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQDMULH</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQDMULH_A1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQDMULH" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQDMULH</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQDMULH/T1A1_A.txt" mylink="aarch32.instrs.VQDMULH.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '00' || size == '11' then UNDEFINED;</line>
<line>scalar_form = FALSE;  esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VQDMULH" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VQDMULH/T2A2_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQDMULH_A2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQDMULH" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="24" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQDMULH</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQDMULH_A2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQDMULH" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="24" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQDMULH</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQDMULH/T2A2_A.txt" mylink="aarch32.instrs.VQDMULH.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>scalar_form = TRUE;  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = if Q == '0' then 1 else 2;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VQDMULH" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VQDMULH/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQDMULH_T1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQDMULH" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQDMULH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQDMULH_T1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQDMULH" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQDMULH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQDMULH/T1A1_A.txt" mylink="aarch32.instrs.VQDMULH.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '00' || size == '11' then UNDEFINED;</line>
<line>scalar_form = FALSE;  esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VQDMULH" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VQDMULH/T2A2_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQDMULH_T2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQDMULH" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="28" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQDMULH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQDMULH_T2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQDMULH" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="28" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQDMULH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQDMULH/T2A2_A.txt" mylink="aarch32.instrs.VQDMULH.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>scalar_form = TRUE;  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = if Q == '0' then 1 else 2;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VQDMULH_A1_Q, VQDMULH_A2_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1 and A2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMULH_T1_Q, VQDMULH_T2_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMULH_A1_Q, VQDMULH_A2_Q, VQDMULH_T1_Q, VQDMULH_T2_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMULH_A1_Q, VQDMULH_A2_Q, VQDMULH_T1_Q, VQDMULH_T2_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQDMULH_A1_Q, VQDMULH_A2_Q, VQDMULH_T1_Q, VQDMULH_T2_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMULH_A1_Q, VQDMULH_A2_Q, VQDMULH_T1_Q, VQDMULH_T2_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMULH_A1_Q, VQDMULH_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMULH_A1_D, VQDMULH_A2_D, VQDMULH_T1_D, VQDMULH_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMULH_A1_D, VQDMULH_A2_D, VQDMULH_T1_D, VQDMULH_T2_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMULH_A2_Q, VQDMULH_T2_Q" symboldefcount="1">
      <symbol link="sa_dm_x">&lt;Dm[x]&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register holding the scalar. If <syntax>&lt;dt&gt;</syntax> is <value>S16</value>, <syntax>Dm</syntax> is restricted to D0-D7. <syntax>Dm</syntax> is encoded in "Vm&lt;2:0&gt;", and <syntax>x</syntax> is encoded in "M:Vm&lt;3&gt;". If <syntax>&lt;dt&gt;</syntax> is <value>S32</value>, <syntax>Dm</syntax> is restricted to D0-D15. <syntax>Dm</syntax> is encoded in "Vm", and <syntax>x</syntax> is encoded in "M".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMULH_A1_D, VQDMULH_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VQDMULH/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    integer op2;</line>
<line>    if scalar_form then op2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m],index,esize]);</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            if !scalar_form then op2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize]);</line>
<line>            op1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize]);</line>
<line>            // The following only saturates if both op1 and op2 equal -(2^(esize-1))</line>
<line>            (result, sat) = <a link="impl-shared.SignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>((2*op1*op2) &gt;&gt; esize, esize);</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result;</line>
<line>            if sat then FPSCR.QC = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vqdmull.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VQDMULL" title="VQDMULL -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VQDMULL" />
  </docvars>
  <heading>VQDMULL</heading>
  <desc>
    <brief>
      <para>Vector Saturating Doubling Multiply Long</para>
    </brief>
    <authored>
      <para>Vector Saturating Doubling Multiply Long multiplies corresponding elements in two doubleword vectors, doubles the products, and places the results in a quadword vector.</para>
      <para>The second operand can be a scalar instead of a vector. For more information about scalars see <xref linkend="Cjaibjhd">Advanced SIMD scalars</xref>.</para>
      <para>If any of the results overflow, they are saturated. The cumulative saturation bit, <xref linkend="AArch32.fpscr">FPSCR</xref>.QC, is set if saturation occurs. For details see <xref linkend="BEIHABGJ">Pseudocode details of saturation</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VQDMULL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VQDMULL/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQDMULL_A1" oneofinclass="1" oneof="4" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQDMULL" />
        </docvars>
        <asmtemplate><text>VQDMULL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQDMULL/T1A1_A.txt" mylink="aarch32.instrs.VQDMULL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>scalar_form = FALSE;  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VQDMULL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VQDMULL/T2A2_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQDMULL_A2" oneofinclass="1" oneof="4" label="A2">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQDMULL" />
        </docvars>
        <asmtemplate><text>VQDMULL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQDMULL/T2A2_A.txt" mylink="aarch32.instrs.VQDMULL.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>scalar_form = TRUE;  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VQDMULL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VQDMULL/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQDMULL_T1" oneofinclass="1" oneof="4" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQDMULL" />
        </docvars>
        <asmtemplate><text>VQDMULL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQDMULL/T1A1_A.txt" mylink="aarch32.instrs.VQDMULL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>scalar_form = FALSE;  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VQDMULL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VQDMULL/T2A2_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQDMULL_T2" oneofinclass="1" oneof="4" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQDMULL" />
        </docvars>
        <asmtemplate><text>VQDMULL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQDMULL/T2A2_A.txt" mylink="aarch32.instrs.VQDMULL.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' || Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>scalar_form = TRUE;  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VQDMULL_A1, VQDMULL_A2" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1 and A2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMULL_T1, VQDMULL_T2" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMULL_A1, VQDMULL_A2, VQDMULL_T1, VQDMULL_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMULL_A1, VQDMULL_A2, VQDMULL_T1, VQDMULL_T2" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQDMULL_A1, VQDMULL_A2, VQDMULL_T1, VQDMULL_T2" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMULL_A1, VQDMULL_A2, VQDMULL_T1, VQDMULL_T2" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMULL_A2, VQDMULL_T2" symboldefcount="1">
      <symbol link="sa_dm_x">&lt;Dm[x]&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register holding the scalar. If <syntax>&lt;dt&gt;</syntax> is <value>S16</value>, <syntax>Dm</syntax> is restricted to D0-D7. <syntax>Dm</syntax> is encoded in "Vm&lt;2:0&gt;", and <syntax>x</syntax> is encoded in "M:Vm&lt;3&gt;". If <syntax>&lt;dt&gt;</syntax> is <value>S32</value>, <syntax>Dm</syntax> is restricted to D0-D15. <syntax>Dm</syntax> is encoded in "Vm", and <syntax>x</syntax> is encoded in "M".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQDMULL_A1, VQDMULL_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VQDMULL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    integer op2;</line>
<line>    if scalar_form then op2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m],index,esize]);</line>
<line>    for e = 0 to elements-1</line>
<line>        if !scalar_form then op2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m],e,esize]);</line>
<line>        op1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n],e,esize]);</line>
<line>        // The following only saturates if both op1 and op2 equal -(2^(esize-1))</line>
<line>        (product, sat) = <a link="impl-shared.SignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(2*op1*op2, 2*esize);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = product;</line>
<line>        if sat then FPSCR.QC = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vqmovn.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VQMOVN" title="VQMOVN, VQMOVUN -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
  </docvars>
  <heading>VQMOVN, VQMOVUN</heading>
  <desc>
    <brief>
      <para>Vector Saturating Move and Narrow</para>
    </brief>
    <authored>
      <para>Vector Saturating Move and Narrow copies each element of the operand vector to the corresponding element of the destination vector.</para>
      <para>The operand is a quadword vector. The elements can be any one of:</para>
      <list type="unordered">
        <listitem><content>16-bit, 32-bit, or 64-bit signed integers.</content></listitem>
        <listitem><content>16-bit, 32-bit, or 64-bit unsigned integers.</content></listitem>
      </list>
      <para>The result is a doubleword vector. The elements are half the length of the operand vector elements. If the operand is unsigned, the results are unsigned. If the operand is signed, the results can be signed or unsigned.</para>
      <para>If any of the results overflow, they are saturated. The cumulative saturation bit, <xref linkend="AArch32.fpscr">FPSCR</xref>.QC, is set if saturation occurs. For details see <xref linkend="BEIHABGJ">Pseudocode details of saturation</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="4">
    <alias_list_intro>This instruction is used by the aliases </alias_list_intro>
    <aliasref aliaspageid="VQRSHRN_VQMOVN" aliasfile="vqrshrn_vqmovn.xml" hover="Vector Saturating Rounding Shift Right" punct=", ">
      <text>VQRSHRN (zero)</text>
      <aliaspref>Never</aliaspref>
    </aliasref>
    <aliasref aliaspageid="VQRSHRUN_VQMOVN" aliasfile="vqrshrun_vqmovn.xml" hover="Vector Saturating Rounding Shift Right" punct=", ">
      <text>VQRSHRUN (zero)</text>
      <aliaspref>Never</aliaspref>
    </aliasref>
    <aliasref aliaspageid="VQSHRN_VQMOVN" aliasfile="vqshrn_vqmovn.xml" hover="Vector Saturating Shift Right" punct=" and ">
      <text>VQSHRN (zero)</text>
      <aliaspref>Never</aliaspref>
    </aliasref>
    <aliasref aliaspageid="VQSHRUN_VQMOVN" aliasfile="vqshrun_vqmovn.xml" hover="Vector Saturating Shift Right" punct=".">
      <text>VQSHRUN (zero)</text>
      <aliaspref>Never</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink />
      <text> below for details of when each alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VQMOVN/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="op" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQMOVN_A1" oneofinclass="2" oneof="4" label="Signed result" bitdiffs="op == 1x">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQMOVN" />
          <docvar key="result-type" value="signed-result" />
        </docvars>
        <box hibit="7" width="2" name="op">
          <c>1</c>
          <c></c>
        </box>
        <asmtemplate><text>VQMOVN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;op&lt;0&gt;:size&quot;) [S16,S32,S64,U16,U32,U64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQMOVUN_A1" oneofinclass="2" oneof="4" label="Unsigned result" bitdiffs="op == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQMOVUN" />
          <docvar key="result-type" value="unsigned-result" />
        </docvars>
        <box hibit="7" width="2" name="op">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VQMOVUN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of operand (field &quot;size&quot;) [S16,S32,S64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQMOVN/T1A1_A.txt" mylink="aarch32.instrs.VQMOVN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if op == '00' then SEE "VMOVN";</line>
<line>if size == '11' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>src_unsigned = (op == '11');  dest_unsigned = (op&lt;0&gt; == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VQMOVN/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="op" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQMOVN_T1" oneofinclass="2" oneof="4" label="Signed result" bitdiffs="op == 1x">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQMOVN" />
          <docvar key="result-type" value="signed-result" />
        </docvars>
        <box hibit="7" width="2" name="op">
          <c>1</c>
          <c></c>
        </box>
        <asmtemplate><text>VQMOVN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;op&lt;0&gt;:size&quot;) [S16,S32,S64,U16,U32,U64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQMOVUN_T1" oneofinclass="2" oneof="4" label="Unsigned result" bitdiffs="op == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQMOVUN" />
          <docvar key="result-type" value="unsigned-result" />
        </docvars>
        <box hibit="7" width="2" name="op">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VQMOVUN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of operand (field &quot;size&quot;) [S16,S32,S64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQMOVN/T1A1_A.txt" mylink="aarch32.instrs.VQMOVN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if op == '00' then SEE "VMOVN";</line>
<line>if size == '11' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>src_unsigned = (op == '11');  dest_unsigned = (op&lt;0&gt; == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VQMOVN_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQMOVN_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQMOVN_A1, VQMOVN_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQMOVN_A1, VQMOVN_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="op&lt;0&gt;:size">
        <intro>For the signed result variant: is the data type for the elements of the operand, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">op&lt;0&gt;</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S64</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U64</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQMOVUN_A1, VQMOVUN_T1" symboldefcount="2">
      <symbol link="sa_dt_1">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>For the unsigned result variant: is the data type for the elements of the operand, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S64</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQMOVN_A1, VQMOVN_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQMOVN_A1, VQMOVN_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VQMOVN/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for e = 0 to elements-1</line>
<line>        operand = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[m&gt;&gt;1],e,2*esize], src_unsigned);</line>
<line>        boolean sat;</line>
<line>        (<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d],e,esize], sat) = <a link="impl-shared.SatQ.3" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(operand, esize, dest_unsigned);</line>
<line>        if sat then FPSCR.QC = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vqneg.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VQNEG" title="VQNEG -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VQNEG" />
  </docvars>
  <heading>VQNEG</heading>
  <desc>
    <brief>
      <para>Vector Saturating Negate</para>
    </brief>
    <authored>
      <para>Vector Saturating Negate negates each element in a vector, and places the results in the destination vector.</para>
      <para>If any of the results overflow, they are saturated. The cumulative saturation bit, <xref linkend="AArch32.fpscr">FPSCR</xref>.QC, is set if saturation occurs. For details see <xref linkend="BEIHABGJ">Pseudocode details of saturation</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VQNEG" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VQNEG/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQNEG_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQNEG" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQNEG</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQNEG_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQNEG" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQNEG</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQNEG/T1A1_A.txt" mylink="aarch32.instrs.VQNEG.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VQNEG" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VQNEG/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQNEG_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQNEG" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQNEG</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQNEG_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQNEG" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQNEG</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQNEG/T1A1_A.txt" mylink="aarch32.instrs.VQNEG.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VQNEG_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQNEG_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQNEG_A1_Q, VQNEG_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQNEG_A1_Q, VQNEG_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQNEG_A1_Q, VQNEG_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQNEG_A1_Q, VQNEG_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQNEG_A1_D, VQNEG_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQNEG_A1_D, VQNEG_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VQNEG/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            result = -<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize]);</line>
<line>            boolean sat;</line>
<line>            (<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize], sat) = <a link="impl-shared.SignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(result, esize);</line>
<line>            if sat then FPSCR.QC = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vqrdmlah.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VQRDMLAH" title="VQRDMLAH -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VQRDMLAH" />
  </docvars>
  <heading>VQRDMLAH</heading>
  <desc>
    <brief>
      <para>Vector Saturating Rounding Doubling Multiply Accumulate Returning High Half</para>
    </brief>
    <authored>
      <para>Vector Saturating Rounding Doubling Multiply Accumulate Returning High Half. This instruction multiplies the vector elements of the first source SIMD&amp;FP register with either the corresponding vector elements of the second source SIMD&amp;FP register or the value of a vector element of the second source SIMD&amp;FP register, without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&amp;FP register. The results are rounded.</para>
      <para>If any of the results overflow, they are saturated. The cumulative saturation bit, <xref linkend="AArch32.fpscr">FPSCR</xref>.QC, is set if saturation occurs. For details see <xref linkend="BEIHABGJ">Pseudocode details of saturation</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VQRDMLAH" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.1" feature="FEAT_RDM" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VQRDMLAH/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQRDMLAH_A1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQRDMLAH" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQRDMLAH</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQRDMLAH_A1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQRDMLAH" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQRDMLAH</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQRDMLAH/A1_A.txt" mylink="aarch32.instrs.VQRDMLAH.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveQRDMLAHExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveQRDMLAHExt()">HaveQRDMLAHExt</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '00' || size == '11' then UNDEFINED;</line>
<line>add = TRUE;  scalar_form = FALSE;  esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VQRDMLAH" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.1" feature="FEAT_RDM" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VQRDMLAH/A2_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQRDMLAH_A2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQRDMLAH" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="24" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQRDMLAH</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQRDMLAH_A2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQRDMLAH" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="24" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQRDMLAH</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQRDMLAH/A2_A.txt" mylink="aarch32.instrs.VQRDMLAH.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveQRDMLAHExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveQRDMLAHExt()">HaveQRDMLAHExt</a>() then UNDEFINED;</line>
<line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>add = TRUE;  scalar_form = TRUE;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>regs = if Q == '0' then 1 else 2;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VQRDMLAH" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.1" feature="FEAT_RDM" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VQRDMLAH/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQRDMLAH_T1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQRDMLAH" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQRDMLAH</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQRDMLAH_T1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQRDMLAH" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQRDMLAH</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQRDMLAH/T1_A.txt" mylink="aarch32.instrs.VQRDMLAH.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveQRDMLAHExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveQRDMLAHExt()">HaveQRDMLAHExt</a>() then UNDEFINED;</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '00' || size == '11' then UNDEFINED;</line>
<line>add = TRUE;  scalar_form = FALSE;  esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VQRDMLAH" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.1" feature="FEAT_RDM" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VQRDMLAH/T2_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQRDMLAH_T2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQRDMLAH" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="28" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQRDMLAH</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQRDMLAH_T2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQRDMLAH" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="28" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQRDMLAH</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQRDMLAH/T2_A.txt" mylink="aarch32.instrs.VQRDMLAH.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveQRDMLAHExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveQRDMLAHExt()">HaveQRDMLAHExt</a>() then UNDEFINED;</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>add = TRUE;  scalar_form = TRUE;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>regs = if Q == '0' then 1 else 2;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VQRDMLAH_A1_Q, VQRDMLAH_A2_Q, VQRDMLAH_T1_Q, VQRDMLAH_T2_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMLAH_A1_Q, VQRDMLAH_A2_Q, VQRDMLAH_T1_Q, VQRDMLAH_T2_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQRDMLAH_A1_Q, VQRDMLAH_A2_Q, VQRDMLAH_T1_Q, VQRDMLAH_T2_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP register holding the accumulate vector, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMLAH_A1_Q, VQRDMLAH_A2_Q, VQRDMLAH_T1_Q, VQRDMLAH_T2_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMLAH_A1_Q, VQRDMLAH_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMLAH_A1_D, VQRDMLAH_A2_D, VQRDMLAH_T1_D, VQRDMLAH_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP register holding the accumulate vector, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMLAH_A1_D, VQRDMLAH_A2_D, VQRDMLAH_T1_D, VQRDMLAH_T2_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMLAH_A2_Q, VQRDMLAH_T2_Q" symboldefcount="1">
      <symbol link="sa_dm_x">&lt;Dm[x]&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register holding the scalar. If <syntax>&lt;dt&gt;</syntax> is <value>S16</value>, <syntax>Dm</syntax> is restricted to D0-D7. <syntax>Dm</syntax> is encoded in "Vm&lt;2:0&gt;", and <syntax>x</syntax> is encoded in "M:Vm&lt;3&gt;". If <syntax>&lt;dt&gt;</syntax> is <value>S32</value>, <syntax>Dm</syntax> is restricted to D0-D15. <syntax>Dm</syntax> is encoded in "Vm", and <syntax>x</syntax> is encoded in "M".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMLAH_A1_D, VQRDMLAH_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VQRDMLAH/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>round_const = 1 &lt;&lt; (esize-1);</line>
<line>integer op2;</line>
<line>if scalar_form then op2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m],index,esize]);</line>
<line>for r = 0 to regs-1</line>
<line>    for e = 0 to elements-1</line>
<line>        op1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize]);</line>
<line>        op3 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r],e,esize]) &lt;&lt; esize;</line>
<line>        if !scalar_form then op2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize]);</line>
<line>        (result, sat) = <a link="impl-shared.SignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>((op3 + 2*(op1*op2) + round_const) &gt;&gt; esize, esize);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result;</line>
<line>        if sat then FPSCR.QC = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vqrdmlsh.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VQRDMLSH" title="VQRDMLSH -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VQRDMLSH" />
  </docvars>
  <heading>VQRDMLSH</heading>
  <desc>
    <brief>
      <para>Vector Saturating Rounding Doubling Multiply Subtract Returning High Half</para>
    </brief>
    <authored>
      <para>Vector Saturating Rounding Doubling Multiply Subtract Returning High Half. This instruction multiplies the vector elements of the first source SIMD&amp;FP register with either the corresponding vector elements of the second source SIMD&amp;FP register or the value of a vector element of the second source SIMD&amp;FP register, without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&amp;FP register. The results are rounded.</para>
      <para>If any of the results overflow, they are saturated. The cumulative saturation bit, <xref linkend="AArch32.fpscr">FPSCR</xref>.QC, is set if saturation occurs. For details see <xref linkend="BEIHABGJ">Pseudocode details of saturation</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VQRDMLSH" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.1" feature="FEAT_RDM" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VQRDMLSH/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQRDMLSH_A1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQRDMLSH" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQRDMLSH</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQRDMLSH_A1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQRDMLSH" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQRDMLSH</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQRDMLSH/A1_A.txt" mylink="aarch32.instrs.VQRDMLSH.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveQRDMLAHExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveQRDMLAHExt()">HaveQRDMLAHExt</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '00' || size == '11' then UNDEFINED;</line>
<line>add = FALSE;  scalar_form = FALSE;  esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VQRDMLSH" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.1" feature="FEAT_RDM" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VQRDMLSH/A2_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQRDMLSH_A2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQRDMLSH" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="24" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQRDMLSH</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQRDMLSH_A2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQRDMLSH" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="24" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQRDMLSH</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQRDMLSH/A2_A.txt" mylink="aarch32.instrs.VQRDMLSH.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveQRDMLAHExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveQRDMLAHExt()">HaveQRDMLAHExt</a>() then UNDEFINED;</line>
<line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>add = FALSE;  scalar_form = TRUE;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>regs = if Q == '0' then 1 else 2;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VQRDMLSH" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.1" feature="FEAT_RDM" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VQRDMLSH/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQRDMLSH_T1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQRDMLSH" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQRDMLSH</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQRDMLSH_T1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQRDMLSH" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQRDMLSH</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQRDMLSH/T1_A.txt" mylink="aarch32.instrs.VQRDMLSH.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveQRDMLAHExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveQRDMLAHExt()">HaveQRDMLAHExt</a>() then UNDEFINED;</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '00' || size == '11' then UNDEFINED;</line>
<line>add = FALSE;  scalar_form = FALSE;  esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VQRDMLSH" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.1" feature="FEAT_RDM" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VQRDMLSH/T2_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQRDMLSH_T2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQRDMLSH" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="28" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQRDMLSH</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQRDMLSH_T2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQRDMLSH" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="28" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQRDMLSH</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP register holding accumulate vector (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQRDMLSH/T2_A.txt" mylink="aarch32.instrs.VQRDMLSH.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveQRDMLAHExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveQRDMLAHExt()">HaveQRDMLAHExt</a>() then UNDEFINED;</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>add = FALSE;  scalar_form = TRUE;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>regs = if Q == '0' then 1 else 2;</line>
<line>integer esize;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>integer elements;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VQRDMLSH_A1_Q, VQRDMLSH_A2_Q, VQRDMLSH_T1_Q, VQRDMLSH_T2_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMLSH_A1_Q, VQRDMLSH_A2_Q, VQRDMLSH_T1_Q, VQRDMLSH_T2_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQRDMLSH_A1_Q, VQRDMLSH_A2_Q, VQRDMLSH_T1_Q, VQRDMLSH_T2_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP register holding the accumulate vector, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMLSH_A1_Q, VQRDMLSH_A2_Q, VQRDMLSH_T1_Q, VQRDMLSH_T2_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMLSH_A1_Q, VQRDMLSH_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMLSH_A1_D, VQRDMLSH_A2_D, VQRDMLSH_T1_D, VQRDMLSH_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP register holding the accumulate vector, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMLSH_A1_D, VQRDMLSH_A2_D, VQRDMLSH_T1_D, VQRDMLSH_T2_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMLSH_A2_Q, VQRDMLSH_T2_Q" symboldefcount="1">
      <symbol link="sa_dm_x">&lt;Dm[x]&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register holding the scalar. If <syntax>&lt;dt&gt;</syntax> is <value>S16</value>, <syntax>Dm</syntax> is restricted to D0-D7. <syntax>Dm</syntax> is encoded in "Vm&lt;2:0&gt;", and <syntax>x</syntax> is encoded in "M:Vm&lt;3&gt;". If <syntax>&lt;dt&gt;</syntax> is <value>S32</value>, <syntax>Dm</syntax> is restricted to D0-D15. <syntax>Dm</syntax> is encoded in "Vm", and <syntax>x</syntax> is encoded in "M".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMLSH_A1_D, VQRDMLSH_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VQRDMLSH/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>round_const = 1 &lt;&lt; (esize-1);</line>
<line>integer op2;</line>
<line>if scalar_form then op2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m],index,esize]);</line>
<line>for r = 0 to regs-1</line>
<line>    for e = 0 to elements-1</line>
<line>        op1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize]);</line>
<line>        op3 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r],e,esize]) &lt;&lt; esize;</line>
<line>        if !scalar_form then op2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize]);</line>
<line>        (result, sat) = <a link="impl-shared.SignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>((op3 - 2*(op1*op2) + round_const) &gt;&gt; esize, esize);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result;</line>
<line>        if sat then FPSCR.QC = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vqrdmulh.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VQRDMULH" title="VQRDMULH -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VQRDMULH" />
  </docvars>
  <heading>VQRDMULH</heading>
  <desc>
    <brief>
      <para>Vector Saturating Rounding Doubling Multiply Returning High Half</para>
    </brief>
    <authored>
      <para>Vector Saturating Rounding Doubling Multiply Returning High Half multiplies corresponding elements in two vectors, doubles the results, and places the most significant half of the final results in the destination vector. The results are rounded. For truncated results see <xref linkend="A32T32-fpsimd.instructions.VQDMULH">VQDMULH</xref>.</para>
      <para>The second operand can be a scalar instead of a vector. For more information about scalars see <xref linkend="Cjaibjhd">Advanced SIMD scalars</xref>.</para>
      <para>If any of the results overflow, they are saturated. The cumulative saturation bit, <xref linkend="AArch32.fpscr">FPSCR</xref>.QC, is set if saturation occurs. For details see <xref linkend="BEIHABGJ">Pseudocode details of saturation</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VQRDMULH" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VQRDMULH/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQRDMULH_A1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQRDMULH" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQRDMULH</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQRDMULH_A1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQRDMULH" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQRDMULH</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQRDMULH/T1A1_A.txt" mylink="aarch32.instrs.VQRDMULH.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '00' || size == '11' then UNDEFINED;</line>
<line>scalar_form = FALSE;  esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VQRDMULH" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VQRDMULH/T2A2_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQRDMULH_A2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQRDMULH" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="24" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQRDMULH</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQRDMULH_A2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQRDMULH" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="24" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQRDMULH</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQRDMULH/T2A2_A.txt" mylink="aarch32.instrs.VQRDMULH.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>scalar_form = TRUE;  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = if Q == '0' then 1 else 2;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VQRDMULH" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VQRDMULH/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQRDMULH_T1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQRDMULH" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQRDMULH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQRDMULH_T1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQRDMULH" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQRDMULH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQRDMULH/T1A1_A.txt" mylink="aarch32.instrs.VQRDMULH.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '00' || size == '11' then UNDEFINED;</line>
<line>scalar_form = FALSE;  esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VQRDMULH" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VQRDMULH/T2A2_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQRDMULH_T2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQRDMULH" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="28" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQRDMULH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQRDMULH_T2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQRDMULH" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="28" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQRDMULH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&amp;FP source register holding scalar (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm[x]&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQRDMULH/T2A2_A.txt" mylink="aarch32.instrs.VQRDMULH.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if size == '00' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>scalar_form = TRUE;  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = if Q == '0' then 1 else 2;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer m;</line>
<line>integer index;</line>
<line>if size == '01' then esize = 16;  elements = 4;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;);</line>
<line>if size == '10' then esize = 32;  elements = 2;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VQRDMULH_A1_Q, VQRDMULH_A2_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1 and A2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMULH_T1_Q, VQRDMULH_T2_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMULH_A1_Q, VQRDMULH_A2_Q, VQRDMULH_T1_Q, VQRDMULH_T2_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMULH_A1_Q, VQRDMULH_A2_Q, VQRDMULH_T1_Q, VQRDMULH_T2_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQRDMULH_A1_Q, VQRDMULH_A2_Q, VQRDMULH_T1_Q, VQRDMULH_T2_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMULH_A1_Q, VQRDMULH_A2_Q, VQRDMULH_T1_Q, VQRDMULH_T2_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMULH_A1_Q, VQRDMULH_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMULH_A1_D, VQRDMULH_A2_D, VQRDMULH_T1_D, VQRDMULH_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMULH_A1_D, VQRDMULH_A2_D, VQRDMULH_T1_D, VQRDMULH_T2_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMULH_A2_Q, VQRDMULH_T2_Q" symboldefcount="1">
      <symbol link="sa_dm_x">&lt;Dm[x]&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register holding the scalar. If <syntax>&lt;dt&gt;</syntax> is <value>S16</value>, <syntax>Dm</syntax> is restricted to D0-D7. <syntax>Dm</syntax> is encoded in "Vm&lt;2:0&gt;", and <syntax>x</syntax> is encoded in "M:Vm&lt;3&gt;". If <syntax>&lt;dt&gt;</syntax> is <value>S32</value>, <syntax>Dm</syntax> is restricted to D0-D15. <syntax>Dm</syntax> is encoded in "Vm", and <syntax>x</syntax> is encoded in "M".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRDMULH_A1_D, VQRDMULH_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VQRDMULH/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    round_const = 1 &lt;&lt; (esize-1);</line>
<line>    integer op2;</line>
<line>    if scalar_form then op2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m],index,esize]);</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize]);</line>
<line>            if !scalar_form then op2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize]);</line>
<line>            (result, sat) = <a link="impl-shared.SignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>((2*op1*op2 + round_const) &gt;&gt; esize, esize);</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result;</line>
<line>            if sat then FPSCR.QC = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vqrshl.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VQRSHL" title="VQRSHL -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VQRSHL" />
  </docvars>
  <heading>VQRSHL</heading>
  <desc>
    <brief>
      <para>Vector Saturating Rounding Shift Left</para>
    </brief>
    <authored>
      <para>Vector Saturating Rounding Shift Left takes each element in a vector, shifts them by a value from the least significant byte of the corresponding element of a second vector, and places the results in the destination vector. If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift.</para>
      <para>For truncated results see <xref linkend="A32T32-fpsimd.instructions.VQSHL_r">VQSHL (register)</xref>.</para>
      <para>The first operand and result elements are the same data type, and can be any one of:</para>
      <list type="unordered">
        <listitem><content>8-bit, 16-bit, 32-bit, or 64-bit signed integers.</content></listitem>
        <listitem><content>8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.</content></listitem>
      </list>
      <para>The second operand is a signed integer of the same size.</para>
      <para>If any of the results overflow, they are saturated. The cumulative saturation bit, <xref linkend="AArch32.fpscr">FPSCR</xref>.QC, is set if saturation occurs. For details see <xref linkend="BEIHABGJ">Pseudocode details of saturation</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VQRSHL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VQRSHL/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQRSHL_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQRSHL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQRSHL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQRSHL_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQRSHL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQRSHL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQRSHL/T1A1_A.txt" mylink="aarch32.instrs.VQRSHL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VQRSHL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VQRSHL/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQRSHL_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQRSHL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQRSHL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQRSHL_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQRSHL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQRSHL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQRSHL/T1A1_A.txt" mylink="aarch32.instrs.VQRSHL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VQRSHL_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRSHL_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRSHL_A1_Q, VQRSHL_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRSHL_A1_Q, VQRSHL_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">S64</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">U64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQRSHL_A1_Q, VQRSHL_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRSHL_A1_Q, VQRSHL_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRSHL_A1_Q, VQRSHL_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRSHL_A1_D, VQRSHL_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRSHL_A1_D, VQRSHL_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRSHL_A1_D, VQRSHL_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VQRSHL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    bits(esize) result;</line>
<line>    boolean sat;</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            integer element = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r], e, esize], unsigned);</line>
<line>            integer shift = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r], e, esize]&lt;7:0&gt;);</line>
<line>            if shift &gt;= 0 then // left shift</line>
<line>                element = element &lt;&lt; shift;</line>
<line>            else               // rounding right shift</line>
<line>                shift = -shift;</line>
<line>                element = (element + (1 &lt;&lt; (shift - 1))) &gt;&gt; shift;</line>
<line>            (result, sat) = <a link="impl-shared.SatQ.3" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r], e, esize] = result;</line>
<line>            if sat then FPSCR.QC = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vqrshrn.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VQRSHRN" title="VQRSHRN, VQRSHRUN -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
  </docvars>
  <heading>VQRSHRN, VQRSHRUN</heading>
  <desc>
    <brief>
      <para>Vector Saturating Rounding Shift Right, Narrow</para>
    </brief>
    <authored>
      <para>Vector Saturating Rounding Shift Right, Narrow takes each element in a quadword vector of integers, right shifts them by an immediate value, and places the rounded results in a doubleword vector.</para>
      <para>For truncated results, see <xref linkend="A32T32-fpsimd.instructions.VQSHL_r">VQSHRN and VQSHRUN</xref>.</para>
      <para>The operand elements must all be the same size, and can be any one of:</para>
      <list type="unordered">
        <listitem><content>16-bit, 32-bit, or 64-bit signed integers.</content></listitem>
        <listitem><content>16-bit, 32-bit, or 64-bit unsigned integers.</content></listitem>
      </list>
      <para>The result elements are half the width of the operand elements. If the operand elements are signed, the results can be either signed or unsigned. If the operand elements are unsigned, the result elements must also be unsigned.</para>
      <para>If any of the results overflow, they are saturated. The cumulative saturation bit, <xref linkend="AArch32.fpscr">FPSCR</xref>.QC, is set if saturation occurs. For details see <xref linkend="BEIHABGJ">Pseudocode details of saturation</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_1r_imm">Advanced SIMD one register and modified immediate</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd1reg_imm">Advanced SIMD one register and modified immediate</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VQRSHRN/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="8" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="7" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQRSHRN_A1" oneofinclass="2" oneof="4" label="Signed result" bitdiffs="!(imm6 == 000xxx) &amp;&amp; op == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQRSHRN" />
          <docvar key="result-type" value="signed-result" />
        </docvars>
        <box hibit="21" width="15" name="imm6">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
        </box>
        <box hibit="8" width="1" name="op">
          <c>1</c>
        </box>
        <asmtemplate><text>VQRSHRN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;imm6&lt;5:3&gt;&quot;) [16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}/2] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQRSHRUN_A1" oneofinclass="2" oneof="4" label="Unsigned result" bitdiffs="U == 1 &amp;&amp; !(imm6 == 000xxx) &amp;&amp; op == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQRSHRUN" />
          <docvar key="result-type" value="unsigned-result" />
        </docvars>
        <box hibit="24" width="1" name="U">
          <c>1</c>
        </box>
        <box hibit="21" width="15" name="imm6">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
        </box>
        <box hibit="8" width="1" name="op">
          <c>0</c>
        </box>
        <asmtemplate><text>VQRSHRUN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type_1" hover="Data type for elements of vectors (field &quot;U&quot;) [S]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;imm6&lt;5:3&gt;&quot;) [16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}/2] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQRSHRN/T1A1_A.txt" mylink="aarch32.instrs.VQRSHRN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if imm6 IN {'000xxx'} then SEE "Related encodings";</line>
<line>if U == '0' &amp;&amp; op == '0' then SEE "VRSHRN";</line>
<line>if Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case imm6 of</line>
<line>    when '001xxx'  esize = 8;  elements = 8;  shift_amount = 16 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '01xxxx'  esize = 16;  elements = 4;  shift_amount = 32 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '1xxxxx'  esize = 32;  elements = 2;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>src_unsigned = (U == '1' &amp;&amp; op == '1');  dest_unsigned = (U == '1');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VQRSHRN/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="8" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="7" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQRSHRN_T1" oneofinclass="2" oneof="4" label="Signed result" bitdiffs="!(imm6 == 000xxx) &amp;&amp; op == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQRSHRN" />
          <docvar key="result-type" value="signed-result" />
        </docvars>
        <box hibit="21" width="15" name="imm6">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
        </box>
        <box hibit="8" width="1" name="op">
          <c>1</c>
        </box>
        <asmtemplate><text>VQRSHRN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;imm6&lt;5:3&gt;&quot;) [16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}/2] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQRSHRUN_T1" oneofinclass="2" oneof="4" label="Unsigned result" bitdiffs="U == 1 &amp;&amp; !(imm6 == 000xxx) &amp;&amp; op == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQRSHRUN" />
          <docvar key="result-type" value="unsigned-result" />
        </docvars>
        <box hibit="28" width="1" name="U">
          <c>1</c>
        </box>
        <box hibit="21" width="15" name="imm6">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
        </box>
        <box hibit="8" width="1" name="op">
          <c>0</c>
        </box>
        <asmtemplate><text>VQRSHRUN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type_1" hover="Data type for elements of vectors (field &quot;U&quot;) [S]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;imm6&lt;5:3&gt;&quot;) [16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}/2] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQRSHRN/T1A1_A.txt" mylink="aarch32.instrs.VQRSHRN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if imm6 IN {'000xxx'} then SEE "Related encodings";</line>
<line>if U == '0' &amp;&amp; op == '0' then SEE "VRSHRN";</line>
<line>if Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case imm6 of</line>
<line>    when '001xxx'  esize = 8;  elements = 8;  shift_amount = 16 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '01xxxx'  esize = 16;  elements = 4;  shift_amount = 32 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '1xxxxx'  esize = 32;  elements = 2;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>src_unsigned = (U == '1' &amp;&amp; op == '1');  dest_unsigned = (U == '1');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VQRSHRN_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRSHRN_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRSHRN_A1, VQRSHRN_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRSHRN_A1, VQRSHRN_T1" symboldefcount="1">
      <symbol link="sa_type">&lt;type&gt;</symbol>
      <definition encodedin="U">
        <intro>For the signed result variant: is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">&lt;type&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">S</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">U</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQRSHRUN_A1, VQRSHRUN_T1" symboldefcount="2">
      <symbol link="sa_type_1">&lt;type&gt;</symbol>
      <definition encodedin="U">
        <intro>For the unsigned result variant: is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">&lt;type&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">S</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQRSHRN_A1, VQRSHRN_T1" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="imm6&lt;5:3&gt;">
        <intro>Is the data size for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">imm6&lt;5:3&gt;</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">001</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">01x</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">1xx</entry>
                <entry class="symbol">64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQRSHRN_A1, VQRSHRN_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRSHRN_A1, VQRSHRN_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRSHRN_A1, VQRSHRN_T1" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm6">
        <intro>
          <para>Is an immediate value, in the range 1 to <syntax>&lt;size&gt;</syntax>/2, encoded in the "imm6" field as <syntax>&lt;size&gt;</syntax>/2 - <syntax>&lt;imm&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VQRSHRN/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    round_const = 1 &lt;&lt; (shift_amount - 1);</line>
<line>    for e = 0 to elements-1</line>
<line>        operand = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[m&gt;&gt;1],e,2*esize], src_unsigned);</line>
<line>        (result, sat) = <a link="impl-shared.SatQ.3" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>((operand + round_const) &gt;&gt; shift_amount, esize, dest_unsigned);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d],e,esize] = result;</line>
<line>        if sat then FPSCR.QC = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vqrshrn_vqmovn.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VQRSHRN_VQMOVN" title="VQRSHRN (zero) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="VQRSHRN" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VQMOVN" />
    <docvar key="result-type" value="signed-result" />
  </docvars>
  <heading>VQRSHRN (zero)</heading>
  <desc>
    <brief>Vector Saturating Rounding Shift Right, Narrow</brief>
    <longer> takes each element in a quadword vector of integers, right shifts them by an immediate value, and places the signed rounded results in a doubleword vector</longer>
  </desc>
  <aliasto refiform="vqmovn.xml" iformid="VQMOVN">VQMOVN, VQMOVUN</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="op" usename="1" settings="1">
          <c>1</c>
          <c>x</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQRSHRN_VQMOVN_A1" oneofinclass="1" oneof="2" label="Signed result">
        <docvars>
          <docvar key="alias_mnemonic" value="VQRSHRN" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQMOVN" />
          <docvar key="result-type" value="signed-result" />
        </docvars>
        <asmtemplate><text>VQRSHRN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;op&lt;0&gt;:size&quot;) [S16,S32,S64,U16,U32,U64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vqmovn.xml#VQMOVN_A1">VQMOVN</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;op&lt;0&gt;:size&quot;) [S16,S32,S64,U16,U32,U64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="op" usename="1" settings="1">
          <c>1</c>
          <c>x</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQRSHRN_VQMOVN_T1" oneofinclass="1" oneof="2" label="Signed result">
        <docvars>
          <docvar key="alias_mnemonic" value="VQRSHRN" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQMOVN" />
          <docvar key="result-type" value="signed-result" />
        </docvars>
        <asmtemplate><text>VQRSHRN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;op&lt;0&gt;:size&quot;) [S16,S32,S64,U16,U32,U64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vqmovn.xml#VQMOVN_T1">VQMOVN</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;op&lt;0&gt;:size&quot;) [S16,S32,S64,U16,U32,U64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VQRSHRN_VQMOVN_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRSHRN_VQMOVN_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRSHRN_VQMOVN_A1, VQRSHRN_VQMOVN_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRSHRN_VQMOVN_A1, VQRSHRN_VQMOVN_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="op&lt;0&gt;:size">
        <intro>Is the data type for the elements of the operand, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">op&lt;0&gt;</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S64</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U64</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQRSHRN_VQMOVN_A1, VQRSHRN_VQMOVN_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRSHRN_VQMOVN_A1, VQRSHRN_VQMOVN_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="vqrshrun_vqmovn.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VQRSHRUN_VQMOVN" title="VQRSHRUN (zero) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="VQRSHRUN" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VQMOVUN" />
    <docvar key="result-type" value="unsigned-result" />
  </docvars>
  <heading>VQRSHRUN (zero)</heading>
  <desc>
    <brief>Vector Saturating Rounding Shift Right, Narrow</brief>
    <longer> takes each element in a quadword vector of integers, right shifts them by an immediate value, and places the unsigned rounded results in a doubleword vector</longer>
  </desc>
  <aliasto refiform="vqmovn.xml" iformid="VQMOVN">VQMOVN, VQMOVUN</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="op" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQRSHRUN_VQMOVUN_A1" oneofinclass="1" oneof="2" label="Unsigned result">
        <docvars>
          <docvar key="alias_mnemonic" value="VQRSHRUN" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQMOVUN" />
          <docvar key="result-type" value="unsigned-result" />
        </docvars>
        <asmtemplate><text>VQRSHRUN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of operand (field &quot;size&quot;) [S16,S32,S64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vqmovn.xml#VQMOVUN_A1">VQMOVUN</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of operand (field &quot;size&quot;) [S16,S32,S64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="op" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQRSHRUN_VQMOVUN_T1" oneofinclass="1" oneof="2" label="Unsigned result">
        <docvars>
          <docvar key="alias_mnemonic" value="VQRSHRUN" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQMOVUN" />
          <docvar key="result-type" value="unsigned-result" />
        </docvars>
        <asmtemplate><text>VQRSHRUN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of operand (field &quot;size&quot;) [S16,S32,S64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vqmovn.xml#VQMOVUN_T1">VQMOVUN</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of operand (field &quot;size&quot;) [S16,S32,S64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VQRSHRUN_VQMOVUN_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRSHRUN_VQMOVUN_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRSHRUN_VQMOVUN_A1, VQRSHRUN_VQMOVUN_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRSHRUN_VQMOVUN_A1, VQRSHRUN_VQMOVUN_T1" symboldefcount="1">
      <symbol link="sa_dt_1">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operand, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S64</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQRSHRUN_VQMOVUN_A1, VQRSHRUN_VQMOVUN_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQRSHRUN_VQMOVUN_A1, VQRSHRUN_VQMOVUN_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="vqshl_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VQSHL_i" title="VQSHL, VQSHLU (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
  </docvars>
  <heading>VQSHL, VQSHLU (immediate)</heading>
  <desc>
    <brief>
      <para>Vector Saturating Shift Left (immediate)</para>
    </brief>
    <authored>
      <para>Vector Saturating Shift Left (immediate) takes each element in a vector of integers, left shifts them by an immediate value, and places the results in a second vector.</para>
      <para>The operand elements must all be the same size, and can be any one of:</para>
      <list type="unordered">
        <listitem><content>8-bit, 16-bit, 32-bit, or 64-bit signed integers.</content></listitem>
        <listitem><content>8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.</content></listitem>
      </list>
      <para>The result elements are the same size as the operand elements. If the operand elements are signed, the results can be either signed or unsigned. If the operand elements are unsigned, the result elements must also be unsigned.</para>
      <para>If any of the results overflow, they are saturated. The cumulative saturation bit, <xref linkend="AArch32.fpscr">FPSCR</xref>.QC, is set if saturation occurs. For details see <xref linkend="BEIHABGJ">Pseudocode details of saturation</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_1r_imm">Advanced SIMD one register and modified immediate</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd1reg_imm">Advanced SIMD one register and modified immediate</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VQSHL_i/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="7" name="L" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQSHL_i_A1_D" oneofinclass="4" oneof="8" label="64-bit SIMD vector, signed result" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; op == 1 &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQSHL" />
          <docvar key="result-type" value="signed-result" />
          <docvar key="result-type-simd-vector" value="signed-result-double" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="8" width="1" name="op">
          <c>1</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQSHL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [0-{syntax{&lt;size&gt;}}-1] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQSHLU_i_A1_D" oneofinclass="4" oneof="8" label="64-bit SIMD vector, unsigned result" bitdiffs="U == 1 &amp;&amp; !(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; op == 0 &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQSHLU" />
          <docvar key="result-type" value="unsigned-result" />
          <docvar key="result-type-simd-vector" value="unsigned-result-double" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="24" width="1" name="U">
          <c>1</c>
        </box>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="8" width="1" name="op">
          <c>0</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQSHLU</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [0-{syntax{&lt;size&gt;}}-1] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQSHL_i_A1_Q" oneofinclass="4" oneof="8" label="128-bit SIMD vector, signed result" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; op == 1 &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQSHL" />
          <docvar key="result-type" value="signed-result" />
          <docvar key="result-type-simd-vector" value="signed-result-quad" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="8" width="1" name="op">
          <c>1</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQSHL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [0-{syntax{&lt;size&gt;}}-1] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQSHLU_i_A1_Q" oneofinclass="4" oneof="8" label="128-bit SIMD vector, unsigned result" bitdiffs="U == 1 &amp;&amp; !(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; op == 0 &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQSHLU" />
          <docvar key="result-type" value="unsigned-result" />
          <docvar key="result-type-simd-vector" value="unsigned-result-quad" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="24" width="1" name="U">
          <c>1</c>
        </box>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="8" width="1" name="op">
          <c>0</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQSHLU</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [0-{syntax{&lt;size&gt;}}-1] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQSHL_i/T1A1_A.txt" mylink="aarch32.instrs.VQSHL_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (L:imm6) IN {'0000xxx'} then SEE "Related encodings";</line>
<line>if U == '0' &amp;&amp; op == '0' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case L:imm6 of</line>
<line>    when '0001xxx'  esize = 8;  elements = 8;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 8;</line>
<line>    when '001xxxx'  esize = 16;  elements = 4;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 16;</line>
<line>    when '01xxxxx'  esize = 32;  elements = 2;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 32;</line>
<line>    when '1xxxxxx'  esize = 64;  elements = 1;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>src_unsigned = (U == '1' &amp;&amp; op == '1');  dest_unsigned = (U == '1');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VQSHL_i/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="7" name="L" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQSHL_i_T1_D" oneofinclass="4" oneof="8" label="64-bit SIMD vector, signed result" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; op == 1 &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQSHL" />
          <docvar key="result-type" value="signed-result" />
          <docvar key="result-type-simd-vector" value="signed-result-double" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="8" width="1" name="op">
          <c>1</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQSHL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [0-{syntax{&lt;size&gt;}}-1] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQSHLU_i_T1_D" oneofinclass="4" oneof="8" label="64-bit SIMD vector, unsigned result" bitdiffs="U == 1 &amp;&amp; !(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; op == 0 &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQSHLU" />
          <docvar key="result-type" value="unsigned-result" />
          <docvar key="result-type-simd-vector" value="unsigned-result-double" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="28" width="1" name="U">
          <c>1</c>
        </box>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="8" width="1" name="op">
          <c>0</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQSHLU</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [0-{syntax{&lt;size&gt;}}-1] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQSHL_i_T1_Q" oneofinclass="4" oneof="8" label="128-bit SIMD vector, signed result" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; op == 1 &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQSHL" />
          <docvar key="result-type" value="signed-result" />
          <docvar key="result-type-simd-vector" value="signed-result-quad" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="8" width="1" name="op">
          <c>1</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQSHL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [0-{syntax{&lt;size&gt;}}-1] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQSHLU_i_T1_Q" oneofinclass="4" oneof="8" label="128-bit SIMD vector, unsigned result" bitdiffs="U == 1 &amp;&amp; !(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; op == 0 &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQSHLU" />
          <docvar key="result-type" value="unsigned-result" />
          <docvar key="result-type-simd-vector" value="unsigned-result-quad" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="28" width="1" name="U">
          <c>1</c>
        </box>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="8" width="1" name="op">
          <c>0</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQSHLU</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [0-{syntax{&lt;size&gt;}}-1] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQSHL_i/T1A1_A.txt" mylink="aarch32.instrs.VQSHL_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (L:imm6) IN {'0000xxx'} then SEE "Related encodings";</line>
<line>if U == '0' &amp;&amp; op == '0' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case L:imm6 of</line>
<line>    when '0001xxx'  esize = 8;  elements = 8;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 8;</line>
<line>    when '001xxxx'  esize = 16;  elements = 4;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 16;</line>
<line>    when '01xxxxx'  esize = 32;  elements = 2;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 32;</line>
<line>    when '1xxxxxx'  esize = 64;  elements = 1;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>src_unsigned = (U == '1' &amp;&amp; op == '1');  dest_unsigned = (U == '1');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VQSHL_i_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHL_i_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHL_i_A1_Q, VQSHL_i_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHL_i_A1_Q, VQSHL_i_T1_Q" symboldefcount="1">
      <symbol link="sa_type">&lt;type&gt;</symbol>
      <definition encodedin="U">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">&lt;type&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">S</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">U</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQSHL_i_A1_Q, VQSHL_i_T1_Q" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="L:imm6&lt;5:3&gt;">
        <intro>Is the data size for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">L</entry>
                <entry class="bitfield">imm6&lt;5:3&gt;</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">001</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01x</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1xx</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">xxx</entry>
                <entry class="symbol">64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQSHL_i_A1_Q, VQSHL_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHL_i_A1_Q, VQSHL_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHL_i_A1_D, VQSHL_i_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHL_i_A1_D, VQSHL_i_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHL_i_A1_Q, VQSHL_i_T1_Q" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm6">
        <intro>
          <para>Is an immediate value, in the range 0 to <syntax>&lt;size&gt;</syntax>-1, encoded in the "imm6" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VQSHL_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            operand = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], src_unsigned);</line>
<line>            (result, sat) = <a link="impl-shared.SatQ.3" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(operand &lt;&lt; shift_amount, esize, dest_unsigned);</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result;</line>
<line>            if sat then FPSCR.QC = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vqshl_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VQSHL_r" title="VQSHL (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VQSHL" />
  </docvars>
  <heading>VQSHL (register)</heading>
  <desc>
    <brief>
      <para>Vector Saturating Shift Left (register)</para>
    </brief>
    <authored>
      <para>Vector Saturating Shift Left (register) takes each element in a vector, shifts them by a value from the least significant byte of the corresponding element of a second vector, and places the results in the destination vector. If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift.</para>
      <para>The results are truncated. For rounded results, see <xref linkend="A32T32-fpsimd.instructions.VQRSHL">VQRSHL</xref>.</para>
      <para>The first operand and result elements are the same data type, and can be any one of:</para>
      <list type="unordered">
        <listitem><content>8-bit, 16-bit, 32-bit, or 64-bit signed integers.</content></listitem>
        <listitem><content>8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.</content></listitem>
      </list>
      <para>The second operand is a signed integer of the same size.</para>
      <para>If any of the results overflow, they are saturated. The cumulative saturation bit, <xref linkend="AArch32.fpscr">FPSCR</xref>.QC, is set if saturation occurs. For details see <xref linkend="BEIHABGJ">Pseudocode details of saturation</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VQSHL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VQSHL_r/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQSHL_r_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQSHL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQSHL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQSHL_r_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQSHL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQSHL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQSHL_r/T1A1_A.txt" mylink="aarch32.instrs.VQSHL_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VQSHL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VQSHL_r/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQSHL_r_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQSHL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQSHL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQSHL_r_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQSHL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQSHL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQSHL_r/T1A1_A.txt" mylink="aarch32.instrs.VQSHL_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VQSHL_r_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHL_r_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHL_r_A1_Q, VQSHL_r_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHL_r_A1_Q, VQSHL_r_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">S64</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">U64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQSHL_r_A1_Q, VQSHL_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHL_r_A1_Q, VQSHL_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHL_r_A1_Q, VQSHL_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHL_r_A1_D, VQSHL_r_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHL_r_A1_D, VQSHL_r_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHL_r_A1_D, VQSHL_r_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VQSHL_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            shift = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize]&lt;7:0&gt;);</line>
<line>            operand = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], unsigned);</line>
<line>            boolean sat;</line>
<line>            bits(esize) result;</line>
<line>            if shift &gt;= 0 then</line>
<line>                (result,sat) = <a link="impl-shared.SatQ.3" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(operand &lt;&lt; shift, esize, unsigned);</line>
<line>            else</line>
<line>                (result,sat) = <a link="impl-shared.SatQ.3" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(operand &gt;&gt; -shift, esize, unsigned);</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result;</line>
<line>            if sat then FPSCR.QC = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vqshrn.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VQSHRN" title="VQSHRN, VQSHRUN -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
  </docvars>
  <heading>VQSHRN, VQSHRUN</heading>
  <desc>
    <brief>
      <para>Vector Saturating Shift Right, Narrow</para>
    </brief>
    <authored>
      <para>Vector Saturating Shift Right, Narrow takes each element in a quadword vector of integers, right shifts them by an immediate value, and places the truncated results in a doubleword vector.</para>
      <para>For rounded results, see <xref linkend="A32T32-fpsimd.instructions.VQRSHRN">VQRSHRN and VQRSHRUN</xref>.</para>
      <para>The operand elements must all be the same size, and can be any one of:</para>
      <list type="unordered">
        <listitem><content>16-bit, 32-bit, or 64-bit signed integers.</content></listitem>
        <listitem><content>16-bit, 32-bit, or 64-bit unsigned integers.</content></listitem>
      </list>
      <para>The result elements are half the width of the operand elements. If the operand elements are signed, the results can be either signed or unsigned. If the operand elements are unsigned, the result elements must also be unsigned.</para>
      <para>If any of the results overflow, they are saturated. The cumulative saturation bit, <xref linkend="AArch32.fpscr">FPSCR</xref>.QC, is set if saturation occurs. For details see <xref linkend="BEIHABGJ">Pseudocode details of saturation</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_1r_imm">Advanced SIMD one register and modified immediate</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd1reg_imm">Advanced SIMD one register and modified immediate</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VQSHRN/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="8" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="7" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQSHRN_A1" oneofinclass="2" oneof="4" label="Signed result" bitdiffs="!(imm6 == 000xxx) &amp;&amp; op == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQSHRN" />
          <docvar key="result-type" value="signed-result" />
        </docvars>
        <box hibit="21" width="15" name="imm6">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
        </box>
        <box hibit="8" width="1" name="op">
          <c>1</c>
        </box>
        <asmtemplate><text>VQSHRN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;imm6&lt;5:3&gt;&quot;) [16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}/2] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQSHRUN_A1" oneofinclass="2" oneof="4" label="Unsigned result" bitdiffs="U == 1 &amp;&amp; !(imm6 == 000xxx) &amp;&amp; op == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQSHRUN" />
          <docvar key="result-type" value="unsigned-result" />
        </docvars>
        <box hibit="24" width="1" name="U">
          <c>1</c>
        </box>
        <box hibit="21" width="15" name="imm6">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
        </box>
        <box hibit="8" width="1" name="op">
          <c>0</c>
        </box>
        <asmtemplate><text>VQSHRUN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type_1" hover="Data type for elements of vectors (field &quot;U&quot;) [S]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;imm6&lt;5:3&gt;&quot;) [16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}/2] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQSHRN/T1A1_A.txt" mylink="aarch32.instrs.VQSHRN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if imm6 IN {'000xxx'} then SEE "Related encodings";</line>
<line>if U == '0' &amp;&amp; op == '0' then SEE "VSHRN";</line>
<line>if Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case imm6 of</line>
<line>    when '001xxx'  esize = 8;  elements = 8;  shift_amount = 16 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '01xxxx'  esize = 16;  elements = 4;  shift_amount = 32 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '1xxxxx'  esize = 32;  elements = 2;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>src_unsigned = (U == '1' &amp;&amp; op == '1');  dest_unsigned = (U == '1');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VQSHRN/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="8" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="7" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQSHRN_T1" oneofinclass="2" oneof="4" label="Signed result" bitdiffs="!(imm6 == 000xxx) &amp;&amp; op == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQSHRN" />
          <docvar key="result-type" value="signed-result" />
        </docvars>
        <box hibit="21" width="15" name="imm6">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
        </box>
        <box hibit="8" width="1" name="op">
          <c>1</c>
        </box>
        <asmtemplate><text>VQSHRN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;imm6&lt;5:3&gt;&quot;) [16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}/2] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQSHRUN_T1" oneofinclass="2" oneof="4" label="Unsigned result" bitdiffs="U == 1 &amp;&amp; !(imm6 == 000xxx) &amp;&amp; op == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQSHRUN" />
          <docvar key="result-type" value="unsigned-result" />
        </docvars>
        <box hibit="28" width="1" name="U">
          <c>1</c>
        </box>
        <box hibit="21" width="15" name="imm6">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
        </box>
        <box hibit="8" width="1" name="op">
          <c>0</c>
        </box>
        <asmtemplate><text>VQSHRUN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type_1" hover="Data type for elements of vectors (field &quot;U&quot;) [S]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;imm6&lt;5:3&gt;&quot;) [16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}/2] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQSHRN/T1A1_A.txt" mylink="aarch32.instrs.VQSHRN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if imm6 IN {'000xxx'} then SEE "Related encodings";</line>
<line>if U == '0' &amp;&amp; op == '0' then SEE "VSHRN";</line>
<line>if Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case imm6 of</line>
<line>    when '001xxx'  esize = 8;  elements = 8;  shift_amount = 16 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '01xxxx'  esize = 16;  elements = 4;  shift_amount = 32 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '1xxxxx'  esize = 32;  elements = 2;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>src_unsigned = (U == '1' &amp;&amp; op == '1');  dest_unsigned = (U == '1');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VQSHRN_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHRN_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHRN_A1, VQSHRN_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHRN_A1, VQSHRN_T1" symboldefcount="1">
      <symbol link="sa_type">&lt;type&gt;</symbol>
      <definition encodedin="U">
        <intro>For the signed result variant: is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">&lt;type&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">S</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">U</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQSHRUN_A1, VQSHRUN_T1" symboldefcount="2">
      <symbol link="sa_type_1">&lt;type&gt;</symbol>
      <definition encodedin="U">
        <intro>For the unsigned result variant: is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">&lt;type&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">S</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQSHRN_A1, VQSHRN_T1" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="imm6&lt;5:3&gt;">
        <intro>Is the data size for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">imm6&lt;5:3&gt;</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">001</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">01x</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">1xx</entry>
                <entry class="symbol">64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQSHRN_A1, VQSHRN_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHRN_A1, VQSHRN_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHRN_A1, VQSHRN_T1" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm6">
        <intro>
          <para>Is an immediate value, in the range 1 to <syntax>&lt;size&gt;</syntax>/2, encoded in the "imm6" field as <syntax>&lt;size&gt;</syntax>/2 - <syntax>&lt;imm&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VQSHRN/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for e = 0 to elements-1</line>
<line>        operand = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[m&gt;&gt;1],e,2*esize], src_unsigned);</line>
<line>        (result, sat) = <a link="impl-shared.SatQ.3" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(operand &gt;&gt; shift_amount, esize, dest_unsigned);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d],e,esize] = result;</line>
<line>        if sat then FPSCR.QC = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vqshrn_vqmovn.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VQSHRN_VQMOVN" title="VQSHRN (zero) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="VQSHRN" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VQMOVN" />
    <docvar key="result-type" value="signed-result" />
  </docvars>
  <heading>VQSHRN (zero)</heading>
  <desc>
    <brief>Vector Saturating Shift Right, Narrow</brief>
    <longer> takes each element in a quadword vector of integers, right shifts them by an immediate value, and places the signed truncated results in a doubleword vector</longer>
  </desc>
  <aliasto refiform="vqmovn.xml" iformid="VQMOVN">VQMOVN, VQMOVUN</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="op" usename="1" settings="1">
          <c>1</c>
          <c>x</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQSHRN_VQMOVN_A1" oneofinclass="1" oneof="2" label="Signed result">
        <docvars>
          <docvar key="alias_mnemonic" value="VQSHRN" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQMOVN" />
          <docvar key="result-type" value="signed-result" />
        </docvars>
        <asmtemplate><text>VQSHRN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;op&lt;0&gt;:size&quot;) [S16,S32,S64,U16,U32,U64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vqmovn.xml#VQMOVN_A1">VQMOVN</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;op&lt;0&gt;:size&quot;) [S16,S32,S64,U16,U32,U64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="op" usename="1" settings="1">
          <c>1</c>
          <c>x</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQSHRN_VQMOVN_T1" oneofinclass="1" oneof="2" label="Signed result">
        <docvars>
          <docvar key="alias_mnemonic" value="VQSHRN" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQMOVN" />
          <docvar key="result-type" value="signed-result" />
        </docvars>
        <asmtemplate><text>VQSHRN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;op&lt;0&gt;:size&quot;) [S16,S32,S64,U16,U32,U64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vqmovn.xml#VQMOVN_T1">VQMOVN</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;op&lt;0&gt;:size&quot;) [S16,S32,S64,U16,U32,U64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VQSHRN_VQMOVN_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHRN_VQMOVN_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHRN_VQMOVN_A1, VQSHRN_VQMOVN_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHRN_VQMOVN_A1, VQSHRN_VQMOVN_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="op&lt;0&gt;:size">
        <intro>Is the data type for the elements of the operand, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">op&lt;0&gt;</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S64</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U64</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQSHRN_VQMOVN_A1, VQSHRN_VQMOVN_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHRN_VQMOVN_A1, VQSHRN_VQMOVN_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="vqshrun_vqmovn.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VQSHRUN_VQMOVN" title="VQSHRUN (zero) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="VQSHRUN" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VQMOVUN" />
    <docvar key="result-type" value="unsigned-result" />
  </docvars>
  <heading>VQSHRUN (zero)</heading>
  <desc>
    <brief>Vector Saturating Shift Right, Narrow</brief>
    <longer> takes each element in a quadword vector of integers, right shifts them by an immediate value, and places the unsigned truncated results in a doubleword vector</longer>
  </desc>
  <aliasto refiform="vqmovn.xml" iformid="VQMOVN">VQMOVN, VQMOVUN</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="op" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQSHRUN_VQMOVUN_A1" oneofinclass="1" oneof="2" label="Unsigned result">
        <docvars>
          <docvar key="alias_mnemonic" value="VQSHRUN" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQMOVUN" />
          <docvar key="result-type" value="unsigned-result" />
        </docvars>
        <asmtemplate><text>VQSHRUN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of operand (field &quot;size&quot;) [S16,S32,S64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vqmovn.xml#VQMOVUN_A1">VQMOVUN</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of operand (field &quot;size&quot;) [S16,S32,S64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="op" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQSHRUN_VQMOVUN_T1" oneofinclass="1" oneof="2" label="Unsigned result">
        <docvars>
          <docvar key="alias_mnemonic" value="VQSHRUN" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQMOVUN" />
          <docvar key="result-type" value="unsigned-result" />
        </docvars>
        <asmtemplate><text>VQSHRUN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of operand (field &quot;size&quot;) [S16,S32,S64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vqmovn.xml#VQMOVUN_T1">VQMOVUN</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of operand (field &quot;size&quot;) [S16,S32,S64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VQSHRUN_VQMOVUN_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHRUN_VQMOVUN_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHRUN_VQMOVUN_A1, VQSHRUN_VQMOVUN_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHRUN_VQMOVUN_A1, VQSHRUN_VQMOVUN_T1" symboldefcount="1">
      <symbol link="sa_dt_1">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operand, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S64</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQSHRUN_VQMOVUN_A1, VQSHRUN_VQMOVUN_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHRUN_VQMOVUN_A1, VQSHRUN_VQMOVUN_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="vqsub.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VQSUB" title="VQSUB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VQSUB" />
  </docvars>
  <heading>VQSUB</heading>
  <desc>
    <brief>
      <para>Vector Saturating Subtract</para>
    </brief>
    <authored>
      <para>Vector Saturating Subtract subtracts the elements of the second operand vector from the corresponding elements of the first operand vector, and places the results in the destination vector. Signed and unsigned operations are distinct.</para>
      <para>The operand and result elements must all be the same type, and can be any one of:</para>
      <list type="unordered">
        <listitem><content>8-bit, 16-bit, 32-bit, or 64-bit signed integers.</content></listitem>
        <listitem><content>8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.</content></listitem>
      </list>
      <para>If any of the results overflow, they are saturated. The cumulative saturation bit, <xref linkend="AArch32.fpscr">FPSCR</xref>.QC, is set if saturation occurs. For details see <xref linkend="BEIHABGJ">Pseudocode details of saturation</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VQSUB" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VQSUB/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQSUB_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQSUB" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQSUB</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQSUB_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQSUB" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQSUB</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQSUB/T1A1_A.txt" mylink="aarch32.instrs.VQSUB.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VQSUB" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VQSUB/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQSUB_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQSUB" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VQSUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQSUB_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQSUB" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VQSUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQSUB/T1A1_A.txt" mylink="aarch32.instrs.VQSUB.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VQSUB_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSUB_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSUB_A1_Q, VQSUB_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSUB_A1_Q, VQSUB_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">S64</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">U64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQSUB_A1_Q, VQSUB_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSUB_A1_Q, VQSUB_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSUB_A1_Q, VQSUB_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSUB_A1_D, VQSUB_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSUB_A1_D, VQSUB_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSUB_A1_D, VQSUB_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VQSUB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            diff = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize], unsigned) - <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], unsigned);</line>
<line>            boolean sat;</line>
<line>            (<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize], sat) = <a link="impl-shared.SatQ.3" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);</line>
<line>            if sat then FPSCR.QC = '1';</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vraddhn.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRADDHN" title="VRADDHN -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRADDHN" />
  </docvars>
  <heading>VRADDHN</heading>
  <desc>
    <brief>
      <para>Vector Rounding Add and Narrow, returning High Half</para>
    </brief>
    <authored>
      <para>Vector Rounding Add and Narrow, returning High Half adds corresponding elements in two quadword vectors, and places the most significant half of each result in a doubleword vector. The results are rounded.  For truncated results, see <xref linkend="A32T32-fpsimd.instructions.VADDHN">VADDHN</xref>.</para>
      <para>The operand elements can be 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and unsigned integers.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRADDHN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRADDHN/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRADDHN_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRADDHN" />
        </docvars>
        <asmtemplate><text>VRADDHN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRADDHN/T1A1_A.txt" mylink="aarch32.instrs.VRADDHN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRADDHN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRADDHN/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRADDHN_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRADDHN" />
        </docvars>
        <asmtemplate><text>VRADDHN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRADDHN/T1A1_A.txt" mylink="aarch32.instrs.VRADDHN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRADDHN_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRADDHN_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRADDHN_A1, VRADDHN_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRADDHN_A1, VRADDHN_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">I16</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">I32</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">I64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VRADDHN_A1, VRADDHN_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRADDHN_A1, VRADDHN_T1" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRADDHN_A1, VRADDHN_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRADDHN/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    round_const = 1 &lt;&lt; (esize-1);</line>
<line>    for e = 0 to elements-1</line>
<line>        result = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[n&gt;&gt;1],e,2*esize] + <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[m&gt;&gt;1],e,2*esize] + round_const;</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d],e,esize] = result&lt;2*esize-1:esize&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrecpe.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRECPE" title="VRECPE -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRECPE" />
  </docvars>
  <heading>VRECPE</heading>
  <desc>
    <brief>
      <para>Vector Reciprocal Estimate</para>
    </brief>
    <authored>
      <para>Vector Reciprocal Estimate finds an approximate reciprocal of each element in the operand vector, and places the results in the destination vector.</para>
      <para>The operand and result elements are the same type, and can be floating-point numbers or unsigned integers.</para>
      <para>For details of the operation performed by this instruction see <xref linkend="CFIGIFDB">Floating-point reciprocal square root estimate and step</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <syntaxnotes>
      <para>Newton-Raphson iteration</para>
      <para>For details of the operation performed and how it can be used in a Newton-Raphson iteration to calculate the reciprocal of a number, see <xref linkend="CFIJFDFG">Floating-point reciprocal estimate and step</xref>.</para>
    </syntaxnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRECPE" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRECPE/A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="8" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRECPE_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRECPE" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRECPE</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRECPE_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRECPE" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRECPE</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRECPE/A1_A.txt" mylink="aarch32.instrs.VRECPE.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; (!<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() || F == '0')) || size IN {'00', '11'} then UNDEFINED;</line>
<line>floating_point = (F == '1');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRECPE" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRECPE/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="8" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRECPE_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRECPE" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRECPE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRECPE_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRECPE" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRECPE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRECPE/T1_A.txt" mylink="aarch32.instrs.VRECPE.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; (!<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() || F == '0')) || size IN {'00', '11'} then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>floating_point = (F == '1');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRECPE_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRECPE_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRECPE_A1_Q, VRECPE_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRECPE_A1_Q, VRECPE_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="F:size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">F</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VRECPE_A1_Q, VRECPE_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRECPE_A1_Q, VRECPE_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRECPE_A1_D, VRECPE_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRECPE_A1_D, VRECPE_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRECPE/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            if floating_point then</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPRecipEstimate.2" file="shared_pseudocode.xml" hover="function: bits(N) FPRecipEstimate(bits(N) operand, FPCRType fpcr_in)">FPRecipEstimate</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            else</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.UnsignedRecipEstimate.1" file="shared_pseudocode.xml" hover="function: bits(N) UnsignedRecipEstimate(bits(N) operand)">UnsignedRecipEstimate</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrecps.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRECPS" title="VRECPS -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRECPS" />
  </docvars>
  <heading>VRECPS</heading>
  <desc>
    <brief>
      <para>Vector Reciprocal Step</para>
    </brief>
    <authored>
      <para>Vector Reciprocal Step multiplies the elements of one vector by the corresponding elements of another vector, subtracts each of the products from 2.0, and places the results into the elements of the destination vector.</para>
      <para>The operand and result elements are floating-point numbers.</para>
      <para>For details of the operation performed by this instruction see <xref linkend="CFIJFDFG">Floating-point reciprocal estimate and step</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <syntaxnotes>
      <para>Newton-Raphson iteration</para>
      <para>For details of the operation performed and how it can be used in a Newton-Raphson iteration to calculate the reciprocal of a number, see <xref linkend="CFIJFDFG">Floating-point reciprocal estimate and step</xref>.</para>
    </syntaxnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRECPS" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRECPS/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRECPS_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRECPS" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRECPS</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRECPS_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRECPS" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRECPS</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRECPS/A1_A.txt" mylink="aarch32.instrs.VRECPS.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRECPS" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRECPS/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRECPS_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRECPS" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRECPS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRECPS_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRECPS" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRECPS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRECPS/T1_A.txt" mylink="aarch32.instrs.VRECPS.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRECPS_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRECPS_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRECPS_A1_Q, VRECPS_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRECPS_A1_Q, VRECPS_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VRECPS_A1_Q, VRECPS_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRECPS_A1_Q, VRECPS_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRECPS_A1_Q, VRECPS_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRECPS_A1_D, VRECPS_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRECPS_A1_D, VRECPS_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRECPS_A1_D, VRECPS_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRECPS/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-aarch32.FPRecipStep.2" file="shared_pseudocode.xml" hover="function: bits(N) FPRecipStep(bits(N) op1, bits(N) op2)">FPRecipStep</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize], <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrev16.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VREV16" title="VREV16 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VREV16" />
  </docvars>
  <heading>VREV16</heading>
  <desc>
    <brief>
      <para>Vector Reverse in halfwords</para>
    </brief>
    <authored>
      <para>Vector Reverse in halfwords reverses the order of 8-bit elements in each halfword of the vector, and places the result in the corresponding destination vector.</para>
      <para>There is no distinction between data types, other than size.</para>
      <para><image file="vrev16_operation_examples.svg" label="VREV16 doubleword operation"></image></para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VREV16" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VREV16/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="8" width="2" name="op" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VREV16_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VREV16" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VREV16</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VREV16_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VREV16" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VREV16</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VREV16/T1A1_A.txt" mylink="aarch32.instrs.VREV16.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op)+<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size) &gt;= 3 then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line></line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);</line>
<line>integer container_size;</line>
<line>case op of</line>
<line>    when '10' container_size = 16;</line>
<line>    when '01' container_size = 32;</line>
<line>    when '00' container_size = 64;</line>
<line>integer containers = 64 DIV container_size;</line>
<line>integer elements_per_container = container_size DIV esize;</line>
<line></line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm); regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VREV16" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VREV16/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="8" width="2" name="op" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VREV16_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VREV16" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VREV16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VREV16_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VREV16" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VREV16</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VREV16/T1A1_A.txt" mylink="aarch32.instrs.VREV16.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op)+<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size) &gt;= 3 then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line></line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);</line>
<line>integer container_size;</line>
<line>case op of</line>
<line>    when '10' container_size = 16;</line>
<line>    when '01' container_size = 32;</line>
<line>    when '00' container_size = 64;</line>
<line>integer containers = 64 DIV container_size;</line>
<line>integer elements_per_container = container_size DIV esize;</line>
<line></line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm); regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VREV16_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VREV16_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VREV16_A1_Q, VREV16_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VREV16_A1_Q, VREV16_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operand, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">1x</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VREV16_A1_Q, VREV16_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VREV16_A1_Q, VREV16_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VREV16_A1_D, VREV16_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VREV16_A1_D, VREV16_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VREV16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>    bits(64) result;</line>
<line>    integer element;</line>
<line>    integer rev_element;</line>
<line>    for r = 0 to regs-1</line>
<line>        element = 0;</line>
<line>        for c = 0 to containers-1</line>
<line>            rev_element = (element + elements_per_container) - 1;</line>
<line>            for e = 0 to elements_per_container-1</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r], element, esize];</line>
<line>                element = element + 1;</line>
<line>                rev_element = rev_element - 1;</line>
<line>        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrev32.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VREV32" title="VREV32 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VREV32" />
  </docvars>
  <heading>VREV32</heading>
  <desc>
    <brief>
      <para>Vector Reverse in words</para>
    </brief>
    <authored>
      <para>Vector Reverse in words reverses the order of 8-bit or 16-bit elements in each word of the vector, and places the result in the corresponding destination vector.</para>
      <para>There is no distinction between data types, other than size.</para>
      <para><image file="vrev32_operation_examples.svg" label="VREV32 doubleword operations"></image></para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VREV32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VREV16/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="8" width="2" name="op" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VREV32_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VREV32" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VREV32</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VREV32_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VREV32" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VREV32</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VREV16/T1A1_A.txt" mylink="aarch32.instrs.VREV16.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op)+<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size) &gt;= 3 then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line></line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);</line>
<line>integer container_size;</line>
<line>case op of</line>
<line>    when '10' container_size = 16;</line>
<line>    when '01' container_size = 32;</line>
<line>    when '00' container_size = 64;</line>
<line>integer containers = 64 DIV container_size;</line>
<line>integer elements_per_container = container_size DIV esize;</line>
<line></line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm); regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VREV32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VREV16/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="8" width="2" name="op" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VREV32_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VREV32" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VREV32</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VREV32_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VREV32" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VREV32</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VREV16/T1A1_A.txt" mylink="aarch32.instrs.VREV16.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op)+<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size) &gt;= 3 then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line></line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);</line>
<line>integer container_size;</line>
<line>case op of</line>
<line>    when '10' container_size = 16;</line>
<line>    when '01' container_size = 32;</line>
<line>    when '00' container_size = 64;</line>
<line>integer containers = 64 DIV container_size;</line>
<line>integer elements_per_container = container_size DIV esize;</line>
<line></line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm); regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VREV32_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VREV32_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VREV32_A1_Q, VREV32_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VREV32_A1_Q, VREV32_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operand, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">1x</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VREV32_A1_Q, VREV32_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VREV32_A1_Q, VREV32_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VREV32_A1_D, VREV32_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VREV32_A1_D, VREV32_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VREV16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>    bits(64) result;</line>
<line>    integer element;</line>
<line>    integer rev_element;</line>
<line>    for r = 0 to regs-1</line>
<line>        element = 0;</line>
<line>        for c = 0 to containers-1</line>
<line>            rev_element = (element + elements_per_container) - 1;</line>
<line>            for e = 0 to elements_per_container-1</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r], element, esize];</line>
<line>                element = element + 1;</line>
<line>                rev_element = rev_element - 1;</line>
<line>        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrev64.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VREV64" title="VREV64 -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VREV64" />
  </docvars>
  <heading>VREV64</heading>
  <desc>
    <brief>
      <para>Vector Reverse in doublewords</para>
    </brief>
    <authored>
      <para>Vector Reverse in doublewords reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector, and places the result in the corresponding destination vector.</para>
      <para>There is no distinction between data types, other than size.</para>
      <para><image file="vrev64_operation_examples.svg" label="VREV64 doubleword operations"></image></para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VREV64" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VREV16/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="8" width="2" name="op" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VREV64_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VREV64" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VREV64</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VREV64_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VREV64" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VREV64</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VREV16/T1A1_A.txt" mylink="aarch32.instrs.VREV16.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op)+<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size) &gt;= 3 then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line></line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);</line>
<line>integer container_size;</line>
<line>case op of</line>
<line>    when '10' container_size = 16;</line>
<line>    when '01' container_size = 32;</line>
<line>    when '00' container_size = 64;</line>
<line>integer containers = 64 DIV container_size;</line>
<line>integer elements_per_container = container_size DIV esize;</line>
<line></line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm); regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VREV64" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VREV16/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="8" width="2" name="op" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VREV64_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VREV64" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VREV64</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VREV64_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VREV64" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VREV64</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VREV16/T1A1_A.txt" mylink="aarch32.instrs.VREV16.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op)+<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size) &gt;= 3 then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line></line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);</line>
<line>integer container_size;</line>
<line>case op of</line>
<line>    when '10' container_size = 16;</line>
<line>    when '01' container_size = 32;</line>
<line>    when '00' container_size = 64;</line>
<line>integer containers = 64 DIV container_size;</line>
<line>integer elements_per_container = container_size DIV esize;</line>
<line></line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm); regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VREV64_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VREV64_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VREV64_A1_Q, VREV64_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VREV64_A1_Q, VREV64_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operand, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VREV64_A1_Q, VREV64_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VREV64_A1_Q, VREV64_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VREV64_A1_D, VREV64_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VREV64_A1_D, VREV64_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VREV16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>    bits(64) result;</line>
<line>    integer element;</line>
<line>    integer rev_element;</line>
<line>    for r = 0 to regs-1</line>
<line>        element = 0;</line>
<line>        for c = 0 to containers-1</line>
<line>            rev_element = (element + elements_per_container) - 1;</line>
<line>            for e = 0 to elements_per_container-1</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r], element, esize];</line>
<line>                element = element + 1;</line>
<line>                rev_element = rev_element - 1;</line>
<line>        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrhadd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRHADD" title="VRHADD -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRHADD" />
  </docvars>
  <heading>VRHADD</heading>
  <desc>
    <brief>
      <para>Vector Rounding Halving Add</para>
    </brief>
    <authored>
      <para>Vector Rounding Halving Add adds corresponding elements in two vectors of integers, shifts each result right one bit, and places the final results in the destination vector.</para>
      <para>The operand and result elements are all the same type, and can be any one of:</para>
      <list type="unordered">
        <listitem><content>8-bit, 16-bit, or 32-bit signed integers.</content></listitem>
        <listitem><content>8-bit, 16-bit, or 32-bit unsigned integers.</content></listitem>
      </list>
      <para>The results of the halving operations are rounded. For truncated results, see <xref linkend="A32T32-fpsimd.instructions.VHADD">VHADD</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRHADD" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRHADD/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRHADD_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRHADD" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRHADD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRHADD_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRHADD" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRHADD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRHADD/T1A1_A.txt" mylink="aarch32.instrs.VRHADD.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRHADD" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRHADD/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRHADD_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRHADD" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRHADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRHADD_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRHADD" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRHADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;U:size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRHADD/T1A1_A.txt" mylink="aarch32.instrs.VRHADD.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRHADD_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRHADD_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRHADD_A1_Q, VRHADD_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRHADD_A1_Q, VRHADD_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VRHADD_A1_Q, VRHADD_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRHADD_A1_Q, VRHADD_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRHADD_A1_Q, VRHADD_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRHADD_A1_D, VRHADD_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRHADD_A1_D, VRHADD_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRHADD_A1_D, VRHADD_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRHADD/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            op1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize], unsigned);</line>
<line>            op2 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], unsigned);</line>
<line>            result = (op1 + op2 + 1) &gt;&gt; 1;</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result&lt;esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrinta_asimd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRINTA_asimd" title="VRINTA (Advanced SIMD) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRINTA" />
  </docvars>
  <heading>VRINTA (Advanced SIMD)</heading>
  <desc>
    <brief>
      <para>Vector Round floating-point to integer towards Nearest with Ties to Away</para>
    </brief>
    <authored>
      <para>Vector Round floating-point to integer towards Nearest with Ties to Away rounds a vector of floating-point values to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_2r_misc">Advanced SIMD two registers misc</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd2reg_misc">Advanced SIMD two registers misc</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRINTA" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRINTA_asimd/A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="3" name="op" usename="1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTA_asimd_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTA" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTA_asimd_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTA_asimd/A1_A.txt" mylink="aarch32.instrs.VRINTA_asimd.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if op&lt;2&gt; != op&lt;0&gt; then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size IN {'00', '11'} then UNDEFINED;</line>
<line>// Rounding encoded differently from other VCVT and VRINT instructions</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(op&lt;2&gt;:NOT(op&lt;1&gt;));  exact = FALSE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRINTA" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRINTA_asimd/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="3" name="op" usename="1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTA_asimd_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTA" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTA_asimd_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTA_asimd/T1_A.txt" mylink="aarch32.instrs.VRINTA_asimd.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if op&lt;2&gt; != op&lt;0&gt; then SEE "Related encodings";</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size IN {'00', '11'} then UNDEFINED;</line>
<line>// Rounding encoded differently from other VCVT and VRINT instructions</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(op&lt;2&gt;:NOT(op&lt;1&gt;));  exact = FALSE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRINTA_asimd_A1_Q, VRINTA_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTA_asimd_A1_Q, VRINTA_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VRINTA_asimd_A1_Q, VRINTA_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTA_asimd_A1_Q, VRINTA_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTA_asimd_A1_D, VRINTA_asimd_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTA_asimd_A1_D, VRINTA_asimd_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRINTA_asimd/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations(); <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>for r = 0 to regs-1</line>
<line>    for e = 0 to elements-1</line>
<line>        op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize];</line>
<line>        result = <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(op1, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>(), rounding, exact);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrinta_vfp.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRINTA_vfp" title="VRINTA (floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRINTA" />
  </docvars>
  <heading>VRINTA (floating-point)</heading>
  <desc>
    <brief>
      <para>Round floating-point to integer to Nearest with Ties to Away</para>
    </brief>
    <authored>
      <para>Round floating-point to integer to Nearest with Ties to Away rounds a floating-point value to an integral floating-point value of the same size using the Round to Nearest with Ties to Away rounding mode. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRINTA" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRINTA_vfp/A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="18" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="17" width="2" name="RM" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTA_vfp_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTA" />
          <docvar key="mnemonic-fpdatasize" value="VRINTA-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTA_vfp_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTA" />
          <docvar key="mnemonic-fpdatasize" value="VRINTA-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTA_vfp_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTA" />
          <docvar key="mnemonic-fpdatasize" value="VRINTA-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTA_vfp/A1_A.txt" mylink="aarch32.instrs.VRINTA_vfp.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  exact = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRINTA" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRINTA_vfp/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="18" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="17" width="2" name="RM" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTA_vfp_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTA" />
          <docvar key="mnemonic-fpdatasize" value="VRINTA-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTA_vfp_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTA" />
          <docvar key="mnemonic-fpdatasize" value="VRINTA-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTA_vfp_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTA" />
          <docvar key="mnemonic-fpdatasize" value="VRINTA-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTA_vfp/T1_A.txt" mylink="aarch32.instrs.VRINTA_vfp.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  exact = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRINTA_vfp_A1_H, VRINTA_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTA_vfp_A1_H, VRINTA_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTA_vfp_A1_H, VRINTA_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTA_vfp_A1_D, VRINTA_vfp_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTA_vfp_A1_D, VRINTA_vfp_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRINTA_vfp/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations(); <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>case esize of</line>
<line>    when 16</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[], rounding, exact);</line>
<line>    when 32</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[], rounding, exact);</line>
<line>    when 64</line>
<line>        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[], rounding, exact);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrintm_asimd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRINTM_asimd" title="VRINTM (Advanced SIMD) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRINTM" />
  </docvars>
  <heading>VRINTM (Advanced SIMD)</heading>
  <desc>
    <brief>
      <para>Vector Round floating-point to integer towards -Infinity</para>
    </brief>
    <authored>
      <para>Vector Round floating-point to integer towards -Infinity rounds a vector of floating-point values to integral floating-point values of the same size, using the Round towards -Infinity rounding mode. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_2r_misc">Advanced SIMD two registers misc</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd2reg_misc">Advanced SIMD two registers misc</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRINTM" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRINTA_asimd/A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="3" name="op" usename="1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTM_asimd_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTM" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTM_asimd_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTM" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTA_asimd/A1_A.txt" mylink="aarch32.instrs.VRINTA_asimd.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if op&lt;2&gt; != op&lt;0&gt; then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size IN {'00', '11'} then UNDEFINED;</line>
<line>// Rounding encoded differently from other VCVT and VRINT instructions</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(op&lt;2&gt;:NOT(op&lt;1&gt;));  exact = FALSE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRINTM" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRINTA_asimd/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="3" name="op" usename="1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTM_asimd_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTM" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTM_asimd_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTM" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTA_asimd/T1_A.txt" mylink="aarch32.instrs.VRINTA_asimd.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if op&lt;2&gt; != op&lt;0&gt; then SEE "Related encodings";</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size IN {'00', '11'} then UNDEFINED;</line>
<line>// Rounding encoded differently from other VCVT and VRINT instructions</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(op&lt;2&gt;:NOT(op&lt;1&gt;));  exact = FALSE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRINTM_asimd_A1_Q, VRINTM_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTM_asimd_A1_Q, VRINTM_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VRINTM_asimd_A1_Q, VRINTM_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTM_asimd_A1_Q, VRINTM_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTM_asimd_A1_D, VRINTM_asimd_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTM_asimd_A1_D, VRINTM_asimd_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRINTA_asimd/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations(); <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>for r = 0 to regs-1</line>
<line>    for e = 0 to elements-1</line>
<line>        op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize];</line>
<line>        result = <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(op1, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>(), rounding, exact);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrintm_vfp.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRINTM_vfp" title="VRINTM (floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRINTM" />
  </docvars>
  <heading>VRINTM (floating-point)</heading>
  <desc>
    <brief>
      <para>Round floating-point to integer towards -Infinity</para>
    </brief>
    <authored>
      <para>Round floating-point to integer towards -Infinity rounds a floating-point value to an integral floating-point value of the same size using the Round towards -Infinity rounding mode. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRINTM" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRINTA_vfp/A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="18" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="17" width="2" name="RM" usename="1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTM_vfp_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTM" />
          <docvar key="mnemonic-fpdatasize" value="VRINTM-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTM_vfp_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTM" />
          <docvar key="mnemonic-fpdatasize" value="VRINTM-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTM_vfp_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTM" />
          <docvar key="mnemonic-fpdatasize" value="VRINTM-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTA_vfp/A1_A.txt" mylink="aarch32.instrs.VRINTA_vfp.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  exact = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRINTM" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRINTA_vfp/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="18" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="17" width="2" name="RM" usename="1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTM_vfp_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTM" />
          <docvar key="mnemonic-fpdatasize" value="VRINTM-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTM_vfp_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTM" />
          <docvar key="mnemonic-fpdatasize" value="VRINTM-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTM_vfp_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTM" />
          <docvar key="mnemonic-fpdatasize" value="VRINTM-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTM</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTA_vfp/T1_A.txt" mylink="aarch32.instrs.VRINTA_vfp.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  exact = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRINTM_vfp_A1_H, VRINTM_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTM_vfp_A1_H, VRINTM_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTM_vfp_A1_H, VRINTM_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTM_vfp_A1_D, VRINTM_vfp_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTM_vfp_A1_D, VRINTM_vfp_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRINTA_vfp/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations(); <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>case esize of</line>
<line>    when 16</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[], rounding, exact);</line>
<line>    when 32</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[], rounding, exact);</line>
<line>    when 64</line>
<line>        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[], rounding, exact);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrintn_asimd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRINTN_asimd" title="VRINTN (Advanced SIMD) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRINTN" />
  </docvars>
  <heading>VRINTN (Advanced SIMD)</heading>
  <desc>
    <brief>
      <para>Vector Round floating-point to integer to Nearest</para>
    </brief>
    <authored>
      <para>Vector Round floating-point to integer to Nearest rounds a vector of floating-point values to integral floating-point values of the same size using the Round to Nearest rounding mode. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_2r_misc">Advanced SIMD two registers misc</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd2reg_misc">Advanced SIMD two registers misc</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRINTN" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRINTA_asimd/A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="3" name="op" usename="1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTN_asimd_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTN</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTN_asimd_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTN" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTN</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTA_asimd/A1_A.txt" mylink="aarch32.instrs.VRINTA_asimd.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if op&lt;2&gt; != op&lt;0&gt; then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size IN {'00', '11'} then UNDEFINED;</line>
<line>// Rounding encoded differently from other VCVT and VRINT instructions</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(op&lt;2&gt;:NOT(op&lt;1&gt;));  exact = FALSE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRINTN" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRINTA_asimd/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="3" name="op" usename="1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTN_asimd_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTN</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTN_asimd_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTN" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTN</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTA_asimd/T1_A.txt" mylink="aarch32.instrs.VRINTA_asimd.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if op&lt;2&gt; != op&lt;0&gt; then SEE "Related encodings";</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size IN {'00', '11'} then UNDEFINED;</line>
<line>// Rounding encoded differently from other VCVT and VRINT instructions</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(op&lt;2&gt;:NOT(op&lt;1&gt;));  exact = FALSE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRINTN_asimd_A1_Q, VRINTN_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTN_asimd_A1_Q, VRINTN_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VRINTN_asimd_A1_Q, VRINTN_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTN_asimd_A1_Q, VRINTN_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTN_asimd_A1_D, VRINTN_asimd_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTN_asimd_A1_D, VRINTN_asimd_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRINTA_asimd/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations(); <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>for r = 0 to regs-1</line>
<line>    for e = 0 to elements-1</line>
<line>        op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize];</line>
<line>        result = <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(op1, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>(), rounding, exact);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrintn_vfp.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRINTN_vfp" title="VRINTN (floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRINTN" />
  </docvars>
  <heading>VRINTN (floating-point)</heading>
  <desc>
    <brief>
      <para>Round floating-point to integer to Nearest</para>
    </brief>
    <authored>
      <para>Round floating-point to integer to Nearest rounds a floating-point value to an integral floating-point value of the same size using the Round to Nearest rounding mode. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRINTN" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRINTA_vfp/A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="18" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="17" width="2" name="RM" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTN_vfp_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTN" />
          <docvar key="mnemonic-fpdatasize" value="VRINTN-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTN</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTN_vfp_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTN" />
          <docvar key="mnemonic-fpdatasize" value="VRINTN-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTN</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTN_vfp_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTN" />
          <docvar key="mnemonic-fpdatasize" value="VRINTN-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTN</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTA_vfp/A1_A.txt" mylink="aarch32.instrs.VRINTA_vfp.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  exact = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRINTN" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRINTA_vfp/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="18" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="17" width="2" name="RM" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTN_vfp_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTN" />
          <docvar key="mnemonic-fpdatasize" value="VRINTN-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTN</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTN_vfp_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTN" />
          <docvar key="mnemonic-fpdatasize" value="VRINTN-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTN</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTN_vfp_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTN" />
          <docvar key="mnemonic-fpdatasize" value="VRINTN-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTN</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTA_vfp/T1_A.txt" mylink="aarch32.instrs.VRINTA_vfp.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  exact = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRINTN_vfp_A1_H, VRINTN_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTN_vfp_A1_H, VRINTN_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTN_vfp_A1_H, VRINTN_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTN_vfp_A1_D, VRINTN_vfp_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTN_vfp_A1_D, VRINTN_vfp_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRINTA_vfp/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations(); <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>case esize of</line>
<line>    when 16</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[], rounding, exact);</line>
<line>    when 32</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[], rounding, exact);</line>
<line>    when 64</line>
<line>        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[], rounding, exact);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrintp_asimd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRINTP_asimd" title="VRINTP (Advanced SIMD) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRINTP" />
  </docvars>
  <heading>VRINTP (Advanced SIMD)</heading>
  <desc>
    <brief>
      <para>Vector Round floating-point to integer towards +Infinity</para>
    </brief>
    <authored>
      <para>Vector Round floating-point to integer towards +Infinity rounds a vector of floating-point values to integral floating-point values of the same size using the Round towards +Infinity rounding mode. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_2r_misc">Advanced SIMD two registers misc</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd2reg_misc">Advanced SIMD two registers misc</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRINTP" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRINTA_asimd/A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="3" name="op" usename="1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTP_asimd_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTP" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTP</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTP_asimd_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTP" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTP</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTA_asimd/A1_A.txt" mylink="aarch32.instrs.VRINTA_asimd.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if op&lt;2&gt; != op&lt;0&gt; then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size IN {'00', '11'} then UNDEFINED;</line>
<line>// Rounding encoded differently from other VCVT and VRINT instructions</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(op&lt;2&gt;:NOT(op&lt;1&gt;));  exact = FALSE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRINTP" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRINTA_asimd/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="3" name="op" usename="1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTP_asimd_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTP" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTP</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTP_asimd_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTP" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTP</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTA_asimd/T1_A.txt" mylink="aarch32.instrs.VRINTA_asimd.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if op&lt;2&gt; != op&lt;0&gt; then SEE "Related encodings";</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size IN {'00', '11'} then UNDEFINED;</line>
<line>// Rounding encoded differently from other VCVT and VRINT instructions</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(op&lt;2&gt;:NOT(op&lt;1&gt;));  exact = FALSE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRINTP_asimd_A1_Q, VRINTP_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTP_asimd_A1_Q, VRINTP_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VRINTP_asimd_A1_Q, VRINTP_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTP_asimd_A1_Q, VRINTP_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTP_asimd_A1_D, VRINTP_asimd_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTP_asimd_A1_D, VRINTP_asimd_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRINTA_asimd/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations(); <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>for r = 0 to regs-1</line>
<line>    for e = 0 to elements-1</line>
<line>        op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize];</line>
<line>        result = <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(op1, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>(), rounding, exact);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrintp_vfp.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRINTP_vfp" title="VRINTP (floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRINTP" />
  </docvars>
  <heading>VRINTP (floating-point)</heading>
  <desc>
    <brief>
      <para>Round floating-point to integer towards +Infinity</para>
    </brief>
    <authored>
      <para>Round floating-point to integer towards +Infinity rounds a floating-point value to an integral floating-point value of the same size using the Round towards +Infinity rounding mode. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRINTP" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRINTA_vfp/A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="18" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="17" width="2" name="RM" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTP_vfp_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTP" />
          <docvar key="mnemonic-fpdatasize" value="VRINTP-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTP</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTP_vfp_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTP" />
          <docvar key="mnemonic-fpdatasize" value="VRINTP-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTP</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTP_vfp_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTP" />
          <docvar key="mnemonic-fpdatasize" value="VRINTP-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTP</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTA_vfp/A1_A.txt" mylink="aarch32.instrs.VRINTA_vfp.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  exact = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRINTP" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRINTA_vfp/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="18" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="17" width="2" name="RM" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTP_vfp_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTP" />
          <docvar key="mnemonic-fpdatasize" value="VRINTP-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTP</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTP_vfp_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTP" />
          <docvar key="mnemonic-fpdatasize" value="VRINTP-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTP</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTP_vfp_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTP" />
          <docvar key="mnemonic-fpdatasize" value="VRINTP-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTP</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTA_vfp/T1_A.txt" mylink="aarch32.instrs.VRINTA_vfp.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>rounding = <a link="impl-shared.FPDecodeRM.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</a>(RM);  exact = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRINTP_vfp_A1_H, VRINTP_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTP_vfp_A1_H, VRINTP_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTP_vfp_A1_H, VRINTP_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTP_vfp_A1_D, VRINTP_vfp_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTP_vfp_A1_D, VRINTP_vfp_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRINTA_vfp/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations(); <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>case esize of</line>
<line>    when 16</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[], rounding, exact);</line>
<line>    when 32</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[], rounding, exact);</line>
<line>    when 64</line>
<line>        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[], rounding, exact);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrintr_vfp.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRINTR_vfp" title="VRINTR -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRINTR" />
  </docvars>
  <heading>VRINTR</heading>
  <desc>
    <brief>
      <para>Round floating-point to integer</para>
    </brief>
    <authored>
      <para>Round floating-point to integer rounds a floating-point value to an integral floating-point value of the same size using the rounding mode specified in the FPSCR. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRINTR" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRINTZ_vfp/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTR_vfp_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTR" />
          <docvar key="mnemonic-fpdatasize" value="VRINTR-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTR_vfp_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTR" />
          <docvar key="mnemonic-fpdatasize" value="VRINTR-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTR_vfp_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTR" />
          <docvar key="mnemonic-fpdatasize" value="VRINTR-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTZ_vfp/A1_A.txt" mylink="aarch32.instrs.VRINTZ_vfp.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>rounding = if op == '1' then <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a> else <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPSCR[]);</line>
<line>exact = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRINTR" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRINTZ_vfp/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTR_vfp_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTR" />
          <docvar key="mnemonic-fpdatasize" value="VRINTR-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTR_vfp_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTR" />
          <docvar key="mnemonic-fpdatasize" value="VRINTR-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTR_vfp_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTR" />
          <docvar key="mnemonic-fpdatasize" value="VRINTR-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTZ_vfp/T1_A.txt" mylink="aarch32.instrs.VRINTZ_vfp.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>rounding = if op == '1' then <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a> else <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPSCR[]);</line>
<line>exact = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRINTR_vfp_A1_H, VRINTR_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTR_vfp_A1_H, VRINTR_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTR_vfp_A1_H, VRINTR_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTR_vfp_A1_H, VRINTR_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTR_vfp_A1_D, VRINTR_vfp_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTR_vfp_A1_D, VRINTR_vfp_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRINTZ_vfp/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations(); <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    case esize of</line>
<line>        when 16</line>
<line>            <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[], rounding, exact);</line>
<line>        when 32</line>
<line>            <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[], rounding, exact);</line>
<line>        when 64</line>
<line>            <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[], rounding, exact);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrintx_asimd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRINTX_asimd" title="VRINTX (Advanced SIMD) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRINTX" />
  </docvars>
  <heading>VRINTX (Advanced SIMD)</heading>
  <desc>
    <brief>
      <para>Vector round floating-point to integer inexact</para>
    </brief>
    <authored>
      <para>Vector round floating-point to integer inexact rounds a vector of floating-point values to integral floating-point values of the same size, using the Round to Nearest rounding mode, and raises the Inexact exception when the result value is not numerically equal to the input value. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRINTX" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRINTX_asimd/A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTX_asimd_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTX" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTX</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTX_asimd_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTX" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTX</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTX_asimd/A1_A.txt" mylink="aarch32.instrs.VRINTX_asimd.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size IN {'00', '11'} then UNDEFINED;</line>
<line>rounding = <a link="FPRounding_TIEEVEN" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEEVEN</a>;  exact = TRUE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRINTX" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRINTX_asimd/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTX_asimd_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTX" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTX</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTX_asimd_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTX" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTX</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTX_asimd/T1_A.txt" mylink="aarch32.instrs.VRINTX_asimd.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size IN {'00', '11'} then UNDEFINED;</line>
<line>rounding = <a link="FPRounding_TIEEVEN" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEEVEN</a>;  exact = TRUE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRINTX_asimd_A1_Q, VRINTX_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTX_asimd_A1_Q, VRINTX_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VRINTX_asimd_A1_Q, VRINTX_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTX_asimd_A1_Q, VRINTX_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTX_asimd_A1_D, VRINTX_asimd_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTX_asimd_A1_D, VRINTX_asimd_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRINTX_asimd/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations(); <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>for r = 0 to regs-1</line>
<line>    for e = 0 to elements-1</line>
<line>        op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize];</line>
<line>        result = <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(op1, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>(), rounding, exact);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrintx_vfp.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRINTX_vfp" title="VRINTX (floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRINTX" />
  </docvars>
  <heading>VRINTX (floating-point)</heading>
  <desc>
    <brief>
      <para>Round floating-point to integer inexact</para>
    </brief>
    <authored>
      <para>Round floating-point to integer inexact rounds a floating-point value to an integral floating-point value of the same size, using the rounding mode specified in the FPSCR, and raises an Inexact exception when the result value is not numerically equal to the input value. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRINTX" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRINTX_vfp/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="o3" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTX_vfp_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTX" />
          <docvar key="mnemonic-fpdatasize" value="VRINTX-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTX_vfp_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTX" />
          <docvar key="mnemonic-fpdatasize" value="VRINTX-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTX_vfp_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTX" />
          <docvar key="mnemonic-fpdatasize" value="VRINTX-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTX_vfp/A1_A.txt" mylink="aarch32.instrs.VRINTX_vfp.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>exact = TRUE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRINTX" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRINTX_vfp/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="o3" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTX_vfp_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTX" />
          <docvar key="mnemonic-fpdatasize" value="VRINTX-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTX_vfp_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTX" />
          <docvar key="mnemonic-fpdatasize" value="VRINTX-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTX_vfp_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTX" />
          <docvar key="mnemonic-fpdatasize" value="VRINTX-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTX_vfp/T1_A.txt" mylink="aarch32.instrs.VRINTX_vfp.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>exact = TRUE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRINTX_vfp_A1_H, VRINTX_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTX_vfp_A1_H, VRINTX_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTX_vfp_A1_H, VRINTX_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTX_vfp_A1_H, VRINTX_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTX_vfp_A1_D, VRINTX_vfp_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTX_vfp_A1_D, VRINTX_vfp_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRINTX_vfp/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations(); <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPSCR[]);</line>
<line>    case esize of</line>
<line>        when 16</line>
<line>            <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[], rounding, exact);</line>
<line>        when 32</line>
<line>            <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[], rounding, exact);</line>
<line>        when 64</line>
<line>            <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[], rounding, exact);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrintz_asimd.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRINTZ_asimd" title="VRINTZ (Advanced SIMD) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRINTZ" />
  </docvars>
  <heading>VRINTZ (Advanced SIMD)</heading>
  <desc>
    <brief>
      <para>Vector round floating-point to integer towards Zero</para>
    </brief>
    <authored>
      <para>Vector round floating-point to integer towards Zero rounds a vector of floating-point values to integral floating-point values of the same size, using the Round towards Zero rounding mode. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRINTZ" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRINTZ_asimd/A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTZ_asimd_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTZ" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTZ</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTZ_asimd_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTZ" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTZ</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTZ_asimd/A1_A.txt" mylink="aarch32.instrs.VRINTZ_asimd.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size IN {'00', '11'} then UNDEFINED;</line>
<line>rounding = <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>;  exact = FALSE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRINTZ" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRINTZ_asimd/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTZ_asimd_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTZ" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTZ</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTZ_asimd_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTZ" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTZ</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTZ_asimd/T1_A.txt" mylink="aarch32.instrs.VRINTZ_asimd.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) || size IN {'00', '11'} then UNDEFINED;</line>
<line>rounding = <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>;  exact = FALSE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
<line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRINTZ_asimd_A1_Q, VRINTZ_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTZ_asimd_A1_Q, VRINTZ_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VRINTZ_asimd_A1_Q, VRINTZ_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTZ_asimd_A1_Q, VRINTZ_asimd_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTZ_asimd_A1_D, VRINTZ_asimd_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTZ_asimd_A1_D, VRINTZ_asimd_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRINTZ_asimd/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations(); <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>for r = 0 to regs-1</line>
<line>    for e = 0 to elements-1</line>
<line>        op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize];</line>
<line>        result = <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(op1, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>(), rounding, exact);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrintz_vfp.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRINTZ_vfp" title="VRINTZ (floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRINTZ" />
  </docvars>
  <heading>VRINTZ (floating-point)</heading>
  <desc>
    <brief>
      <para>Round floating-point to integer towards Zero</para>
    </brief>
    <authored>
      <para>Round floating-point to integer towards Zero rounds a floating-point value to an integral floating-point value of the same size, using the Round towards Zero rounding mode. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRINTZ" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRINTZ_vfp/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTZ_vfp_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTZ" />
          <docvar key="mnemonic-fpdatasize" value="VRINTZ-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTZ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTZ_vfp_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTZ" />
          <docvar key="mnemonic-fpdatasize" value="VRINTZ-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTZ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTZ_vfp_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRINTZ" />
          <docvar key="mnemonic-fpdatasize" value="VRINTZ-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTZ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTZ_vfp/A1_A.txt" mylink="aarch32.instrs.VRINTZ_vfp.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>rounding = if op == '1' then <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a> else <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPSCR[]);</line>
<line>exact = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRINTZ" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRINTZ_vfp/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRINTZ_vfp_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTZ" />
          <docvar key="mnemonic-fpdatasize" value="VRINTZ-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTZ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTZ_vfp_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTZ" />
          <docvar key="mnemonic-fpdatasize" value="VRINTZ-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VRINTZ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRINTZ_vfp_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRINTZ" />
          <docvar key="mnemonic-fpdatasize" value="VRINTZ-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VRINTZ</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRINTZ_vfp/T1_A.txt" mylink="aarch32.instrs.VRINTZ_vfp.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>rounding = if op == '1' then <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a> else <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPSCR[]);</line>
<line>exact = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRINTZ_vfp_A1_H, VRINTZ_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTZ_vfp_A1_H, VRINTZ_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTZ_vfp_A1_H, VRINTZ_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTZ_vfp_A1_H, VRINTZ_vfp_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTZ_vfp_A1_D, VRINTZ_vfp_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRINTZ_vfp_A1_D, VRINTZ_vfp_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRINTZ_vfp/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations(); <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    case esize of</line>
<line>        when 16</line>
<line>            <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[], rounding, exact);</line>
<line>        when 32</line>
<line>            <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[], rounding, exact);</line>
<line>        when 64</line>
<line>            <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[], rounding, exact);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrshl.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRSHL" title="VRSHL -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRSHL" />
  </docvars>
  <heading>VRSHL</heading>
  <desc>
    <brief>
      <para>Vector Rounding Shift Left</para>
    </brief>
    <authored>
      <para>Vector Rounding Shift Left takes each element in a vector, shifts them by a value from the least significant byte of the corresponding element of a second vector, and places the results in the destination vector. If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see <instruction>VSHL</instruction>.</para>
      <para>The first operand and result elements are the same data type, and can be any one of:</para>
      <list type="unordered">
        <listitem><content>8-bit, 16-bit, 32-bit, or 64-bit signed integers.</content></listitem>
        <listitem><content>8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.</content></listitem>
      </list>
      <para>The second operand is always a signed integer of the same size.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRSHL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRSHL/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRSHL_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRSHL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRSHL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRSHL_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRSHL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRSHL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRSHL/T1A1_A.txt" mylink="aarch32.instrs.VRSHL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRSHL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRSHL/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRSHL_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRSHL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRSHL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRSHL_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRSHL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRSHL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRSHL/T1A1_A.txt" mylink="aarch32.instrs.VRSHL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRSHL_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHL_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHL_A1_Q, VRSHL_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHL_A1_Q, VRSHL_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">S64</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">U64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VRSHL_A1_Q, VRSHL_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHL_A1_Q, VRSHL_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHL_A1_Q, VRSHL_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHL_A1_D, VRSHL_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHL_A1_D, VRSHL_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHL_A1_D, VRSHL_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRSHL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    integer result;</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            integer element = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r], e, esize], unsigned);</line>
<line>            integer shift = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r], e, esize]&lt;7:0&gt;);</line>
<line>            if shift &gt;= 0 then  // left shift</line>
<line>                result = element &lt;&lt; shift;</line>
<line>            else                // rounding right shift</line>
<line>                shift = -shift;</line>
<line>                result = (element + (1 &lt;&lt; (shift - 1))) &gt;&gt; shift;</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r], e, esize] = result&lt;esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrshr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRSHR" title="VRSHR -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRSHR" />
  </docvars>
  <heading>VRSHR</heading>
  <desc>
    <brief>
      <para>Vector Rounding Shift Right</para>
    </brief>
    <authored>
      <para>Vector Rounding Shift Right takes each element in a vector, right shifts them by an immediate value, and places the rounded results in the destination vector. For truncated results, see <xref linkend="A32T32-fpsimd.instructions.VSHR">VSHR</xref>.</para>
      <para>The operand and result elements must be the same size, and can be any one of:</para>
      <list type="unordered">
        <listitem><content>8-bit, 16-bit, 32-bit, or 64-bit signed integers.</content></listitem>
        <listitem><content>8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.</content></listitem>
      </list>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_1r_imm">Advanced SIMD one register and modified immediate</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd1reg_imm">Advanced SIMD one register and modified immediate</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRSHR" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRSHR/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="L" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRSHR_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRSHR" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRSHR</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRSHR_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRSHR" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRSHR</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRSHR/T1A1_A.txt" mylink="aarch32.instrs.VRSHR.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (L:imm6) IN {'0000xxx'} then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case L:imm6 of</line>
<line>    when '0001xxx'  esize = 8;  elements = 8;  shift_amount = 16 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '001xxxx'  esize = 16;  elements = 4;  shift_amount = 32 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '01xxxxx'  esize = 32;  elements = 2;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '1xxxxxx'  esize = 64;  elements = 1;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>unsigned = (U == '1');  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRSHR" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRSHR/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="L" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRSHR_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRSHR" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRSHR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRSHR_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRSHR" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRSHR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRSHR/T1A1_A.txt" mylink="aarch32.instrs.VRSHR.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (L:imm6) IN {'0000xxx'} then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case L:imm6 of</line>
<line>    when '0001xxx'  esize = 8;  elements = 8;  shift_amount = 16 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '001xxxx'  esize = 16;  elements = 4;  shift_amount = 32 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '01xxxxx'  esize = 32;  elements = 2;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '1xxxxxx'  esize = 64;  elements = 1;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>unsigned = (U == '1');  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRSHR_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHR_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHR_A1_Q, VRSHR_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHR_A1_Q, VRSHR_T1_Q" symboldefcount="1">
      <symbol link="sa_type">&lt;type&gt;</symbol>
      <definition encodedin="U">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">&lt;type&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">S</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">U</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VRSHR_A1_Q, VRSHR_T1_Q" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="L:imm6&lt;5:3&gt;">
        <intro>Is the data size for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">L</entry>
                <entry class="bitfield">imm6&lt;5:3&gt;</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">001</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01x</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1xx</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">xxx</entry>
                <entry class="symbol">64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VRSHR_A1_Q, VRSHR_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHR_A1_Q, VRSHR_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHR_A1_D, VRSHR_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHR_A1_D, VRSHR_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHR_A1_Q, VRSHR_T1_Q" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm6">
        <intro>
          <para>Is an immediate value, in the range 1 to <syntax>&lt;size&gt;</syntax>, encoded in the "imm6" field as <syntax>&lt;size&gt;</syntax> - <syntax>&lt;imm&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRSHR/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    round_const = 1 &lt;&lt; (shift_amount - 1);</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            result = (<a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], unsigned) + round_const) &gt;&gt; shift_amount;</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result&lt;esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrshr_vorr_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRSHR_VORR_r" title="VRSHR (zero) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="VRSHR" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VORR" />
  </docvars>
  <heading>VRSHR (zero)</heading>
  <desc>
    <brief>Vector Rounding Shift Right</brief>
    <longer> copies the contents of one SIMD register to another</longer>
  </desc>
  <aliasto refiform="vorr_r.xml" iformid="VORR_r">VORR (register)</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VORR" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRSHR_VORR_r_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VRSHR" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRSHR</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dm&gt;</a><text>, #0</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vorr_r.xml#VORR_r_A1_D">VORR</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VRSHR_VORR_r_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VRSHR" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRSHR</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vorr_r.xml#VORR_r_A1_Q">VORR</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VORR" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRSHR_VORR_r_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VRSHR" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRSHR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dm&gt;</a><text>, #0</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vorr_r.xml#VORR_r_T1_D">VORR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VRSHR_VORR_r_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VRSHR" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRSHR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vorr_r.xml#VORR_r_T1_Q">VORR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRSHR_VORR_r_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHR_VORR_r_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHR_VORR_r_A1_Q, VRSHR_VORR_r_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHR_VORR_r_A1_Q, VRSHR_VORR_r_T1_Q" symboldefcount="1">
      <symbol link="sa_dt_2">&lt;dt&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the data type for the elements of the vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHR_VORR_r_A1_Q, VRSHR_VORR_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHR_VORR_r_A1_Q, VRSHR_VORR_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qm_1">&lt;Qm&gt;</symbol>
      <account encodedin="N:Vn&quot; and &quot;M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "N:Vn" and "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHR_VORR_r_A1_D, VRSHR_VORR_r_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHR_VORR_r_A1_D, VRSHR_VORR_r_T1_D" symboldefcount="1">
      <symbol link="sa_dm_1">&lt;Dm&gt;</symbol>
      <account encodedin="N:Vn&quot; and &quot;M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "N:Vn" and "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="vrshrn.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRSHRN" title="VRSHRN -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRSHRN" />
  </docvars>
  <heading>VRSHRN</heading>
  <desc>
    <brief>
      <para>Vector Rounding Shift Right and Narrow</para>
    </brief>
    <authored>
      <para>Vector Rounding Shift Right and Narrow takes each element in a vector, right shifts them by an immediate value, and places the rounded results in the destination vector. For truncated results, see <xref linkend="A32T32-fpsimd.instructions.VSHRN">VSHRN</xref>.</para>
      <para>The operand elements can be 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and unsigned integers. The destination elements are half the size of the source elements.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_1r_imm">Advanced SIMD one register and modified immediate</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd1reg_imm">Advanced SIMD one register and modified immediate</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRSHRN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRSHRN/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRSHRN_A1" oneofinclass="1" oneof="2" label="A1" bitdiffs="imm6 != 000xxx">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRSHRN" />
        </docvars>
        <box hibit="21" width="6" name="imm6">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
        </box>
        <asmtemplate><text>VRSHRN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I</text><a link="sa_size" hover="Data size for elements of vectors (field &quot;imm6&lt;5:3&gt;&quot;) [16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}/2] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRSHRN/T1A1_A.txt" mylink="aarch32.instrs.VRSHRN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if imm6 IN {'000xxx'} then SEE "Related encodings";</line>
<line>if Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case imm6 of</line>
<line>    when '001xxx'  esize = 8;  elements = 8;  shift_amount = 16 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '01xxxx'  esize = 16;  elements = 4;  shift_amount = 32 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '1xxxxx'  esize = 32;  elements = 2;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRSHRN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRSHRN/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRSHRN_T1" oneofinclass="1" oneof="2" label="T1" bitdiffs="imm6 != 000xxx">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRSHRN" />
        </docvars>
        <box hibit="21" width="6" name="imm6">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
        </box>
        <asmtemplate><text>VRSHRN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I</text><a link="sa_size" hover="Data size for elements of vectors (field &quot;imm6&lt;5:3&gt;&quot;) [16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}/2] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRSHRN/T1A1_A.txt" mylink="aarch32.instrs.VRSHRN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if imm6 IN {'000xxx'} then SEE "Related encodings";</line>
<line>if Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case imm6 of</line>
<line>    when '001xxx'  esize = 8;  elements = 8;  shift_amount = 16 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '01xxxx'  esize = 16;  elements = 4;  shift_amount = 32 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '1xxxxx'  esize = 32;  elements = 2;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRSHRN_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHRN_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHRN_A1, VRSHRN_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHRN_A1, VRSHRN_T1" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="imm6&lt;5:3&gt;">
        <intro>Is the data size for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">imm6&lt;5:3&gt;</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">001</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">01x</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">1xx</entry>
                <entry class="symbol">64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VRSHRN_A1, VRSHRN_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHRN_A1, VRSHRN_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHRN_A1, VRSHRN_T1" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm6">
        <intro>
          <para>Is an immediate value, in the range 1 to <syntax>&lt;size&gt;</syntax>/2, encoded in the "imm6" field as <syntax>&lt;size&gt;</syntax>/2 - <syntax>&lt;imm&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRSHRN/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    round_const = 1 &lt;&lt; (shift_amount-1);</line>
<line>    for e = 0 to elements-1</line>
<line>        result = <a link="impl-shared.LSR.2" file="shared_pseudocode.xml" hover="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[m&gt;&gt;1],e,2*esize] + round_const, shift_amount);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d],e,esize] = result&lt;esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrshrn_vmovn.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRSHRN_VMOVN" title="VRSHRN (zero) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="VRSHRN" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMOVN" />
  </docvars>
  <heading>VRSHRN (zero)</heading>
  <desc>
    <brief>Vector Rounding Shift Right and Narrow</brief>
    <longer> takes each element in a vector, right shifts them by an immediate value, and places the rounded results in the destination vector</longer>
  </desc>
  <aliasto refiform="vmovn.xml" iformid="VMOVN">VMOVN</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMOVN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRSHRN_VMOVN_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="alias_mnemonic" value="VRSHRN" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOVN" />
        </docvars>
        <asmtemplate><text>VRSHRN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vmovn.xml#VMOVN_A1">VMOVN</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMOVN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRSHRN_VMOVN_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="alias_mnemonic" value="VRSHRN" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOVN" />
        </docvars>
        <asmtemplate><text>VRSHRN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vmovn.xml#VMOVN_T1">VMOVN</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRSHRN_VMOVN_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHRN_VMOVN_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHRN_VMOVN_A1, VRSHRN_VMOVN_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHRN_VMOVN_A1, VRSHRN_VMOVN_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operand, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">I16</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">I32</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">I64</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VRSHRN_VMOVN_A1, VRSHRN_VMOVN_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSHRN_VMOVN_A1, VRSHRN_VMOVN_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="vrsqrte.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRSQRTE" title="VRSQRTE -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRSQRTE" />
  </docvars>
  <heading>VRSQRTE</heading>
  <desc>
    <brief>
      <para>Vector Reciprocal Square Root Estimate</para>
    </brief>
    <authored>
      <para>Vector Reciprocal Square Root Estimate finds an approximate reciprocal square root of each element in a vector, and places the results in a second vector.</para>
      <para>The operand and result elements are the same type, and can be floating-point numbers or unsigned integers.</para>
      <para>For details of the operation performed by this instruction see <xref linkend="CFIJFDFG">Floating-point reciprocal estimate and step</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <syntaxnotes>
      <para>Newton-Raphson iteration</para>
      <para>For details of the operation performed and how it can be used in a Newton-Raphson iteration to calculate the reciprocal of the square root of a number, see <xref linkend="CFIJFDFG">Floating-point reciprocal estimate and step</xref>.</para>
    </syntaxnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRSQRTE" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRSQRTE/A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="8" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRSQRTE_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRSQRTE" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRSQRTE</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRSQRTE_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRSQRTE" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRSQRTE</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRSQRTE/A1_A.txt" mylink="aarch32.instrs.VRSQRTE.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; (!<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() || F == '0')) || size IN {'00', '11'} then UNDEFINED;</line>
<line>floating_point = (F == '1');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRSQRTE" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRSQRTE/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="8" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRSQRTE_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRSQRTE" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRSQRTE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRSQRTE_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRSQRTE" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRSQRTE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;F:size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRSQRTE/T1_A.txt" mylink="aarch32.instrs.VRSQRTE.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if (size == '01' &amp;&amp; (!<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() || F == '0')) || size IN {'00', '11'} then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>floating_point = (F == '1');</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case size of</line>
<line>    when '01' esize = 16; elements = 4;</line>
<line>    when '10' esize = 32; elements = 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRSQRTE_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSQRTE_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSQRTE_A1_Q, VRSQRTE_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSQRTE_A1_Q, VRSQRTE_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="F:size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">F</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VRSQRTE_A1_Q, VRSQRTE_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSQRTE_A1_Q, VRSQRTE_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSQRTE_A1_D, VRSQRTE_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSQRTE_A1_D, VRSQRTE_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRSQRTE/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            if floating_point then</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPRSqrtEstimate.2" file="shared_pseudocode.xml" hover="function: bits(N) FPRSqrtEstimate(bits(N) operand, FPCRType fpcr_in)">FPRSqrtEstimate</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>            else</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.UnsignedRSqrtEstimate.1" file="shared_pseudocode.xml" hover="function: bits(N) UnsignedRSqrtEstimate(bits(N) operand)">UnsignedRSqrtEstimate</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrsqrts.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRSQRTS" title="VRSQRTS -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRSQRTS" />
  </docvars>
  <heading>VRSQRTS</heading>
  <desc>
    <brief>
      <para>Vector Reciprocal Square Root Step</para>
    </brief>
    <authored>
      <para>Vector Reciprocal Square Root Step multiplies the elements of one vector by the corresponding elements of another vector, subtracts each of the products from 3.0, divides these results by 2.0, and places the results into the elements of the destination vector.</para>
      <para>The operand and result elements are floating-point numbers.</para>
      <para>For details of the operation performed by this instruction see <xref linkend="CFIJFDFG">Floating-point reciprocal estimate and step</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <syntaxnotes>
      <para>Newton-Raphson iteration</para>
      <para>For details of the operation performed and how it can be used in a Newton-Raphson iteration to calculate the reciprocal of the square root of a number, see <xref linkend="CFIJFDFG">Floating-point reciprocal estimate and step</xref>.</para>
    </syntaxnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRSQRTS" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRSQRTS/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRSQRTS_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRSQRTS" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRSQRTS</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRSQRTS_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRSQRTS" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRSQRTS</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRSQRTS/A1_A.txt" mylink="aarch32.instrs.VRSQRTS.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRSQRTS" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRSQRTS/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRSQRTS_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRSQRTS" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRSQRTS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRSQRTS_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRSQRTS" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRSQRTS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRSQRTS/T1_A.txt" mylink="aarch32.instrs.VRSQRTS.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRSQRTS_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSQRTS_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSQRTS_A1_Q, VRSQRTS_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSQRTS_A1_Q, VRSQRTS_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VRSQRTS_A1_Q, VRSQRTS_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSQRTS_A1_Q, VRSQRTS_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSQRTS_A1_Q, VRSQRTS_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSQRTS_A1_D, VRSQRTS_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSQRTS_A1_D, VRSQRTS_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSQRTS_A1_D, VRSQRTS_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRSQRTS/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-aarch32.FPRSqrtStep.2" file="shared_pseudocode.xml" hover="function: bits(N) FPRSqrtStep(bits(N) op1, bits(N) op2)">FPRSqrtStep</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize], <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrsra.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRSRA" title="VRSRA -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRSRA" />
  </docvars>
  <heading>VRSRA</heading>
  <desc>
    <brief>
      <para>Vector Rounding Shift Right and Accumulate</para>
    </brief>
    <authored>
      <para>Vector Rounding Shift Right and Accumulate takes each element in a vector, right shifts them by an immediate value, and accumulates the rounded results into the destination vector. For truncated results, see <xref linkend="A32T32-fpsimd.instructions.VSRA">VSRA</xref>.</para>
      <para>The operand and result elements must all be the same type, and can be any one of:</para>
      <list type="unordered">
        <listitem><content>8-bit, 16-bit, 32-bit, or 64-bit signed integers.</content></listitem>
        <listitem><content>8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.</content></listitem>
      </list>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_1r_imm">Advanced SIMD one register and modified immediate</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd1reg_imm">Advanced SIMD one register and modified immediate</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRSRA" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRSRA/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="L" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRSRA_A1_Q" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRSRA" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRSRA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRSRA_A1_D" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRSRA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRSRA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRSRA/T1A1_A.txt" mylink="aarch32.instrs.VRSRA.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (L:imm6) IN {'0000xxx'} then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case L:imm6 of</line>
<line>    when '0001xxx'  esize = 8;  elements = 8;  shift_amount = 16 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '001xxxx'  esize = 16;  elements = 4;  shift_amount = 32 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '01xxxxx'  esize = 32;  elements = 2;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '1xxxxxx'  esize = 64;  elements = 1;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>unsigned = (U == '1');  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRSRA" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRSRA/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" name="L" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRSRA_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRSRA" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VRSRA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VRSRA_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRSRA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VRSRA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRSRA/T1A1_A.txt" mylink="aarch32.instrs.VRSRA.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (L:imm6) IN {'0000xxx'} then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case L:imm6 of</line>
<line>    when '0001xxx'  esize = 8;  elements = 8;  shift_amount = 16 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '001xxxx'  esize = 16;  elements = 4;  shift_amount = 32 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '01xxxxx'  esize = 32;  elements = 2;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '1xxxxxx'  esize = 64;  elements = 1;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>unsigned = (U == '1');  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRSRA_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSRA_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSRA_A1_Q, VRSRA_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSRA_A1_Q, VRSRA_T1_Q" symboldefcount="1">
      <symbol link="sa_type">&lt;type&gt;</symbol>
      <definition encodedin="U">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">&lt;type&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">S</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">U</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VRSRA_A1_Q, VRSRA_T1_Q" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="L:imm6&lt;5:3&gt;">
        <intro>Is the data size for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">L</entry>
                <entry class="bitfield">imm6&lt;5:3&gt;</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">001</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01x</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1xx</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">xxx</entry>
                <entry class="symbol">64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VRSRA_A1_D, VRSRA_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSRA_A1_D, VRSRA_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSRA_A1_Q, VRSRA_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSRA_A1_Q, VRSRA_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSRA_A1_Q, VRSRA_T1_Q" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm6">
        <intro>
          <para>Is an immediate value, in the range 1 to <syntax>&lt;size&gt;</syntax>, encoded in the "imm6" field as <syntax>&lt;size&gt;</syntax> - <syntax>&lt;imm&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRSRA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    round_const = 1 &lt;&lt; (shift_amount - 1);</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            result = (<a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], unsigned) + round_const) &gt;&gt; shift_amount;</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r],e,esize] + result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vrsubhn.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VRSUBHN" title="VRSUBHN -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VRSUBHN" />
  </docvars>
  <heading>VRSUBHN</heading>
  <desc>
    <brief>
      <para>Vector Rounding Subtract and Narrow, returning High Half</para>
    </brief>
    <authored>
      <para>Vector Rounding Subtract and Narrow, returning High Half subtracts the elements of one quadword vector from the corresponding elements of another quadword vector, takes the most significant half of each result, and places the final results in a doubleword vector. The results are rounded. For truncated results, see <xref linkend="A32T32-fpsimd.instructions.VSUBHN">VSUBHN</xref>.</para>
      <para>The operand elements can be 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and unsigned integers.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VRSUBHN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VRSUBHN/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRSUBHN_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VRSUBHN" />
        </docvars>
        <asmtemplate><text>VRSUBHN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRSUBHN/T1A1_A.txt" mylink="aarch32.instrs.VRSUBHN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VRSUBHN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VRSUBHN/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VRSUBHN_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VRSUBHN" />
        </docvars>
        <asmtemplate><text>VRSUBHN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VRSUBHN/T1A1_A.txt" mylink="aarch32.instrs.VRSUBHN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VRSUBHN_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSUBHN_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSUBHN_A1, VRSUBHN_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSUBHN_A1, VRSUBHN_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">I16</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">I32</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">I64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VRSUBHN_A1, VRSUBHN_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSUBHN_A1, VRSUBHN_T1" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VRSUBHN_A1, VRSUBHN_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VRSUBHN/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    round_const = 1 &lt;&lt; (esize-1);</line>
<line>    for e = 0 to elements-1</line>
<line>        result = (<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[n&gt;&gt;1],e,2*esize] - <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[m&gt;&gt;1],e,2*esize]) + round_const;</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d],e,esize] = result&lt;2*esize-1:esize&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vsdot.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSDOT" title="VSDOT (vector) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VSDOT" />
  </docvars>
  <heading>VSDOT (vector)</heading>
  <desc>
    <brief>
      <para>Dot Product vector form with signed integers.</para>
    </brief>
    <authored>
      <para>Dot Product vector form with signed integers. This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of the corresponding 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.</para>
      <para>In Armv8.2 and Armv8.3, this is an <arm-defined-word>optional</arm-defined-word> instruction. From Armv8.4 it is mandatory for all implementations to support it.</para>
      <note>
        <para><xref linkend="AArch32.id_isar6">ID_ISAR6</xref>.DP indicates whether this instruction is supported.</para>
      </note>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VSDOT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_DotProd" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VDOT/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="op1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSDOT_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSDOT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S8 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSDOT_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSDOT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S8 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VDOT/A1_A.txt" mylink="aarch32.instrs.VDOT.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveDOTPExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDOTPExt()">HaveDOTPExt</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>boolean signed = U=='0';</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>integer esize = 32;</line>
<line>integer regs = if Q == '1' then 2 else 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VSDOT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_DotProd" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VDOT/T1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="op1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSDOT_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSDOT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S8 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSDOT_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSDOT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S8 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VDOT/T1_A.txt" mylink="aarch32.instrs.VDOT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveDOTPExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDOTPExt()">HaveDOTPExt</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>boolean signed = U=='0';</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>integer esize = 32;</line>
<line>integer regs = if Q == '1' then 2 else 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSDOT_A1_D, VSDOT_T1_D" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSDOT_A1_Q, VSDOT_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSDOT_A1_Q, VSDOT_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSDOT_A1_Q, VSDOT_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSDOT_A1_D, VSDOT_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSDOT_A1_D, VSDOT_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSDOT_A1_D, VSDOT_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VDOT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>bits(64) operand1;</line>
<line>bits(64) operand2;</line>
<line>bits(64) result;</line>
<line><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>for r = 0 to regs-1</line>
<line>    operand1 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r];</line>
<line>    operand2 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r];</line>
<line>    result = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r];</line>
<line>    integer element1, element2;</line>
<line>    for e = 0 to 1</line>
<line>        integer res = 0;</line>
<line>        for i = 0 to 3</line>
<line>            if signed then</line>
<line>                element1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 4 * e + i, esize DIV 4]);</line>
<line>                element2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 4 * e + i, esize DIV 4]);</line>
<line>            else</line>
<line>                element1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 4 * e + i, esize DIV 4]);</line>
<line>                element2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 4 * e + i, esize DIV 4]);</line>
<line>            res = res + element1 * element2;</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + res;</line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vsdot_s.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSDOT_s" title="VSDOT (by element) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VSDOT" />
  </docvars>
  <heading>VSDOT (by element)</heading>
  <desc>
    <brief>
      <para>Dot Product index form with signed integers.</para>
    </brief>
    <authored>
      <para>Dot Product index form with signed integers. This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.</para>
      <para>In Armv8.2 and Armv8.3, this is an <arm-defined-word>optional</arm-defined-word> instruction. From Armv8.4 it is mandatory for all implementations to support it.</para>
      <note>
        <para><xref linkend="AArch32.id_isar6">ID_ISAR6</xref>.DP indicates whether this instruction is supported.</para>
      </note>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VSDOT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_DotProd" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VDOT_s/A1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="op1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSDOT_s_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSDOT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S8 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VSDOT_s_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSDOT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S8 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VDOT_s/A1_A.txt" mylink="aarch32.instrs.VDOT_s.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveDOTPExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDOTPExt()">HaveDOTPExt</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>boolean signed = (U=='0');</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;3:0&gt;);</line>
<line>integer index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
<line>integer esize = 32;</line>
<line>integer regs = if Q == '1' then 2 else 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VSDOT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_DotProd" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VDOT_s/T1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="op1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSDOT_s_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSDOT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S8 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VSDOT_s_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSDOT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S8 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VDOT_s/T1_A.txt" mylink="aarch32.instrs.VDOT_s.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveDOTPExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDOTPExt()">HaveDOTPExt</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>boolean signed = (U=='0');</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;3:0&gt;);</line>
<line>integer index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
<line>integer esize = 32;</line>
<line>integer regs = if Q == '1' then 2 else 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSDOT_s_A1_D, VSDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSDOT_s_A1_Q, VSDOT_s_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSDOT_s_A1_Q, VSDOT_s_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSDOT_s_A1_D, VSDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSDOT_s_A1_D, VSDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSDOT_s_A1_D, VSDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSDOT_s_A1_D, VSDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_index">&lt;index&gt;</symbol>
      <account encodedin="M">
        <intro>
          <para>Is the element index in the range 0 to 1, encoded in the "M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VDOT_s/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>bits(64) operand1;</line>
<line>bits(64) operand2 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m];</line>
<line>bits(64) result;</line>
<line><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>for r = 0 to regs-1</line>
<line>    operand1 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r];</line>
<line>    result = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r];</line>
<line>    integer element1, element2;</line>
<line>    for e = 0 to 1</line>
<line>        integer res = 0;</line>
<line>        for i = 0 to 3</line>
<line>            if signed then</line>
<line>                element1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 4 * e + i, esize DIV 4]);</line>
<line>                element2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 4 * index + i, esize DIV 4]);</line>
<line>            else</line>
<line>                element1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 4 * e + i, esize DIV 4]);</line>
<line>                element2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 4 * index + i, esize DIV 4]);</line>
<line>            res = res + element1 * element2;</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + res;</line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vsel.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSEL" title="VSELEQ, VSELGE, VSELGT, VSELVS -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
  </docvars>
  <heading>VSELEQ, VSELGE, VSELGT, VSELVS</heading>
  <desc>
    <brief>
      <para>Floating-point conditional select</para>
    </brief>
    <authored>
      <para>Floating-point conditional select allows the destination register to take the value in either one or the other source register according to the condition codes in the <xref linkend="CJAGBHBH">APSR</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="12" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="12"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSEL/A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="cc" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSELEQ_A1_H" oneofinclass="12" oneof="24" label="Equal, half-precision scalar" bitdiffs="cc == 00 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELEQ" />
          <docvar key="mnemonic-fpdatasize" value="VSELEQ-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELEQ.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELEQ_A1_S" oneofinclass="12" oneof="24" label="Equal, single-precision scalar" bitdiffs="cc == 00 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELEQ" />
          <docvar key="mnemonic-fpdatasize" value="VSELEQ-singleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELEQ.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELEQ_A1_D" oneofinclass="12" oneof="24" label="Equal, double-precision scalar" bitdiffs="cc == 00 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELEQ" />
          <docvar key="mnemonic-fpdatasize" value="VSELEQ-doubleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELEQ.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGE_A1_H" oneofinclass="12" oneof="24" label="Greater than or Equal, half-precision scalar" bitdiffs="cc == 10 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELGE" />
          <docvar key="mnemonic-fpdatasize" value="VSELGE-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELGE.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGE_A1_S" oneofinclass="12" oneof="24" label="Greater than or Equal, single-precision scalar" bitdiffs="cc == 10 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELGE" />
          <docvar key="mnemonic-fpdatasize" value="VSELGE-singleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELGE.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGE_A1_D" oneofinclass="12" oneof="24" label="Greater than or Equal, double-precision scalar" bitdiffs="cc == 10 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELGE" />
          <docvar key="mnemonic-fpdatasize" value="VSELGE-doubleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELGE.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGT_A1_H" oneofinclass="12" oneof="24" label="Greater than, half-precision scalar" bitdiffs="cc == 11 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELGT" />
          <docvar key="mnemonic-fpdatasize" value="VSELGT-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELGT.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGT_A1_S" oneofinclass="12" oneof="24" label="Greater than, single-precision scalar" bitdiffs="cc == 11 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELGT" />
          <docvar key="mnemonic-fpdatasize" value="VSELGT-singleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELGT.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGT_A1_D" oneofinclass="12" oneof="24" label="Greater than, double-precision scalar" bitdiffs="cc == 11 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELGT" />
          <docvar key="mnemonic-fpdatasize" value="VSELGT-doubleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELGT.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELVS_A1_H" oneofinclass="12" oneof="24" label="Unordered, half-precision scalar" bitdiffs="cc == 01 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELVS" />
          <docvar key="mnemonic-fpdatasize" value="VSELVS-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELVS.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELVS_A1_S" oneofinclass="12" oneof="24" label="Unordered, single-precision scalar" bitdiffs="cc == 01 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELVS" />
          <docvar key="mnemonic-fpdatasize" value="VSELVS-singleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELVS.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELVS_A1_D" oneofinclass="12" oneof="24" label="Unordered, double-precision scalar" bitdiffs="cc == 01 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELVS" />
          <docvar key="mnemonic-fpdatasize" value="VSELVS-doubleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELVS.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSEL/A1_A.txt" mylink="aarch32.instrs.VSEL.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>cond = cc:(cc&lt;1&gt; EOR cc&lt;0&gt;):'0';</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="12" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="12"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSEL/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="cc" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSELEQ_T1_H" oneofinclass="12" oneof="24" label="Equal, half-precision scalar" bitdiffs="cc == 00 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELEQ" />
          <docvar key="mnemonic-fpdatasize" value="VSELEQ-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELEQ.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELEQ_T1_S" oneofinclass="12" oneof="24" label="Equal, single-precision scalar" bitdiffs="cc == 00 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELEQ" />
          <docvar key="mnemonic-fpdatasize" value="VSELEQ-singleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELEQ.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELEQ_T1_D" oneofinclass="12" oneof="24" label="Equal, double-precision scalar" bitdiffs="cc == 00 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELEQ" />
          <docvar key="mnemonic-fpdatasize" value="VSELEQ-doubleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELEQ.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGE_T1_H" oneofinclass="12" oneof="24" label="Greater than or Equal, half-precision scalar" bitdiffs="cc == 10 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELGE" />
          <docvar key="mnemonic-fpdatasize" value="VSELGE-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELGE.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGE_T1_S" oneofinclass="12" oneof="24" label="Greater than or Equal, single-precision scalar" bitdiffs="cc == 10 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELGE" />
          <docvar key="mnemonic-fpdatasize" value="VSELGE-singleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELGE.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGE_T1_D" oneofinclass="12" oneof="24" label="Greater than or Equal, double-precision scalar" bitdiffs="cc == 10 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELGE" />
          <docvar key="mnemonic-fpdatasize" value="VSELGE-doubleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELGE.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGT_T1_H" oneofinclass="12" oneof="24" label="Greater than, half-precision scalar" bitdiffs="cc == 11 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELGT" />
          <docvar key="mnemonic-fpdatasize" value="VSELGT-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELGT.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGT_T1_S" oneofinclass="12" oneof="24" label="Greater than, single-precision scalar" bitdiffs="cc == 11 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELGT" />
          <docvar key="mnemonic-fpdatasize" value="VSELGT-singleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELGT.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGT_T1_D" oneofinclass="12" oneof="24" label="Greater than, double-precision scalar" bitdiffs="cc == 11 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELGT" />
          <docvar key="mnemonic-fpdatasize" value="VSELGT-doubleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELGT.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELVS_T1_H" oneofinclass="12" oneof="24" label="Unordered, half-precision scalar" bitdiffs="cc == 01 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELVS" />
          <docvar key="mnemonic-fpdatasize" value="VSELVS-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELVS.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELVS_T1_S" oneofinclass="12" oneof="24" label="Unordered, single-precision scalar" bitdiffs="cc == 01 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELVS" />
          <docvar key="mnemonic-fpdatasize" value="VSELVS-singleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELVS.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELVS_T1_D" oneofinclass="12" oneof="24" label="Unordered, double-precision scalar" bitdiffs="cc == 01 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELVS" />
          <docvar key="mnemonic-fpdatasize" value="VSELVS-doubleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELVS.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSEL/T1_A.txt" mylink="aarch32.instrs.VSEL.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>cond = cc:(cc&lt;1&gt; EOR cc&lt;0&gt;):'0';</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSELEQ_A1_D, VSELEQ_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSELEQ_A1_D, VSELEQ_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSELEQ_A1_D, VSELEQ_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSELEQ_A1_H, VSELEQ_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSELEQ_A1_H, VSELEQ_T1_H" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSELEQ_A1_H, VSELEQ_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VSEL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>EncodingSpecificOperations(); <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>case esize of</line>
<line>    when 16</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : (if <a link="impl-shared.ConditionHolds.1" file="shared_pseudocode.xml" hover="function: boolean ConditionHolds(bits(4) cond)">ConditionHolds</a>(cond) then <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n] else <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m])&lt;15:0&gt;;</line>
<line>    when 32</line>
<line>        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = if <a link="impl-shared.ConditionHolds.1" file="shared_pseudocode.xml" hover="function: boolean ConditionHolds(bits(4) cond)">ConditionHolds</a>(cond) then <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n] else <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m];</line>
<line>    when 64</line>
<line>        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = if <a link="impl-shared.ConditionHolds.1" file="shared_pseudocode.xml" hover="function: boolean ConditionHolds(bits(4) cond)">ConditionHolds</a>(cond) then <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n] else <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m];</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vshl_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSHL_i" title="VSHL (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VSHL" />
  </docvars>
  <heading>VSHL (immediate)</heading>
  <desc>
    <brief>
      <para>Vector Shift Left (immediate)</para>
    </brief>
    <authored>
      <para>Vector Shift Left (immediate) takes each element in a vector of integers, left shifts them by an immediate value, and places the results in the destination vector.</para>
      <para>Bits shifted out of the left of each element are lost.</para>
      <para>The elements must all be the same size, and can be 8-bit, 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and unsigned integers.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_1r_imm">Advanced SIMD one register and modified immediate</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd1reg_imm">Advanced SIMD one register and modified immediate</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VSHL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSHL_i/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="L" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSHL_i_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSHL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSHL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I</text><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [0-{syntax{&lt;size&gt;}}-1] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSHL_i_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSHL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSHL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I</text><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [0-{syntax{&lt;size&gt;}}-1] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSHL_i/T1A1_A.txt" mylink="aarch32.instrs.VSHL_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (L:imm6) IN {'0000xxx'} then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case L:imm6 of</line>
<line>    when '0001xxx'  esize = 8;  elements = 8;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 8;</line>
<line>    when '001xxxx'  esize = 16;  elements = 4;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 16;</line>
<line>    when '01xxxxx'  esize = 32;  elements = 2;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 32;</line>
<line>    when '1xxxxxx'  esize = 64;  elements = 1;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VSHL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSHL_i/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="L" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSHL_i_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSHL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSHL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I</text><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [0-{syntax{&lt;size&gt;}}-1] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSHL_i_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSHL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSHL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I</text><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [0-{syntax{&lt;size&gt;}}-1] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSHL_i/T1A1_A.txt" mylink="aarch32.instrs.VSHL_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (L:imm6) IN {'0000xxx'} then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case L:imm6 of</line>
<line>    when '0001xxx'  esize = 8;  elements = 8;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 8;</line>
<line>    when '001xxxx'  esize = 16;  elements = 4;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 16;</line>
<line>    when '01xxxxx'  esize = 32;  elements = 2;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 32;</line>
<line>    when '1xxxxxx'  esize = 64;  elements = 1;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSHL_i_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHL_i_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHL_i_A1_Q, VSHL_i_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHL_i_A1_Q, VSHL_i_T1_Q" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="L:imm6&lt;5:3&gt;">
        <intro>Is the data size for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">L</entry>
                <entry class="bitfield">imm6&lt;5:3&gt;</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">001</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01x</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1xx</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">xxx</entry>
                <entry class="symbol">64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VSHL_i_A1_Q, VSHL_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHL_i_A1_Q, VSHL_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHL_i_A1_D, VSHL_i_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHL_i_A1_D, VSHL_i_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHL_i_A1_Q, VSHL_i_T1_Q" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm6">
        <intro>
          <para>Is an immediate value, in the range 0 to <syntax>&lt;size&gt;</syntax>-1, encoded in the "imm6" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VSHL_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], shift_amount);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vshl_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSHL_r" title="VSHL (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VSHL" />
  </docvars>
  <heading>VSHL (register)</heading>
  <desc>
    <brief>
      <para>Vector Shift Left (register)</para>
    </brief>
    <authored>
      <para>Vector Shift Left (register) takes each element in a vector, shifts them by a value from the least significant byte of the corresponding element of a second vector, and places the results in the destination vector. If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift.</para>
      <para>For a rounding shift, see <xref linkend="A32T32-fpsimd.instructions.VRSHL">VRSHL</xref>.</para>
      <para>The first operand and result elements are the same data type, and can be any one of:</para>
      <list type="unordered">
        <listitem><content>8-bit, 16-bit, 32-bit, or 64-bit signed integers.</content></listitem>
        <listitem><content>8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.</content></listitem>
      </list>
      <para>The second operand is always a signed integer of the same size.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VSHL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSHL_r/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSHL_r_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSHL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSHL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSHL_r_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSHL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSHL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSHL_r/T1A1_A.txt" mylink="aarch32.instrs.VSHL_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VSHL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSHL_r/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSHL_r_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSHL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSHL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSHL_r_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSHL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSHL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSHL_r/T1A1_A.txt" mylink="aarch32.instrs.VSHL_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSHL_r_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHL_r_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHL_r_A1_Q, VSHL_r_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHL_r_A1_Q, VSHL_r_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">S64</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">11</entry>
                <entry class="symbol">U64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VSHL_r_A1_Q, VSHL_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHL_r_A1_Q, VSHL_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHL_r_A1_Q, VSHL_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHL_r_A1_D, VSHL_r_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHL_r_A1_D, VSHL_r_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHL_r_A1_D, VSHL_r_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VSHL_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            shift = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize]&lt;7:0&gt;);</line>
<line>            integer result;</line>
<line>            if shift &gt;= 0 then</line>
<line>                result = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], unsigned) &lt;&lt; shift;</line>
<line>            else</line>
<line>                result = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], unsigned) &gt;&gt; -shift;</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result&lt;esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vshll.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSHLL" title="VSHLL -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VSHLL" />
  </docvars>
  <heading>VSHLL</heading>
  <desc>
    <brief>
      <para>Vector Shift Left Long</para>
    </brief>
    <authored>
      <para>Vector Shift Left Long takes each element in a doubleword vector, left shifts them by an immediate value, and places the results in a quadword vector.</para>
      <para>The operand elements can be:</para>
      <list type="unordered">
        <listitem><content>8-bit, 16-bit, or 32-bit signed integers.</content></listitem>
        <listitem><content>8-bit, 16-bit, or 32-bit unsigned integers.</content></listitem>
        <listitem><content>8-bit, 16-bit, or 32-bit untyped integers, maximum shift only.</content></listitem>
      </list>
      <para>The result elements are twice the length of the operand elements.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_1r_imm">Advanced SIMD one register and modified immediate</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd1reg_imm">Advanced SIMD one register and modified immediate</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VSHLL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSHLL/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSHLL_A1" oneofinclass="1" oneof="4" label="A1" bitdiffs="imm6 != 000xxx">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSHLL" />
        </docvars>
        <box hibit="21" width="6" name="imm6">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
        </box>
        <asmtemplate><text>VSHLL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="The data type for elements of operand">&lt;type&gt;</a><a link="sa_size" hover="The data size for elements of operand">&lt;size&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm" hover="The immediate value">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSHLL/T1A1_A.txt" mylink="aarch32.instrs.VSHLL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if imm6 IN {'000xxx'} then SEE "Related encodings";</line>
<line>if Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case imm6 of</line>
<line>    when '001xxx'  esize = 8;  elements = 8;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 8;</line>
<line>    when '01xxxx'  esize = 16;  elements = 4;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 16;</line>
<line>    when '1xxxxx'  esize = 32;  elements = 2;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 32;</line>
<line>if shift_amount == 0 then SEE "VMOVL";</line>
<line>unsigned = (U == '1');  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VSHLL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSHLL/T2A2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSHLL_A2" oneofinclass="1" oneof="4" label="A2">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSHLL" />
        </docvars>
        <asmtemplate><text>VSHLL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="The data type for elements of operand">&lt;type&gt;</a><a link="sa_size" hover="The data size for elements of operand">&lt;size&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm" hover="The immediate value">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSHLL/T2A2_A.txt" mylink="aarch32.instrs.VSHLL.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' || Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;  shift_amount = esize;</line>
<line>unsigned = FALSE;  // Or TRUE without change of functionality</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VSHLL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSHLL/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSHLL_T1" oneofinclass="1" oneof="4" label="T1" bitdiffs="imm6 != 000xxx">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSHLL" />
        </docvars>
        <box hibit="21" width="6" name="imm6">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
        </box>
        <asmtemplate><text>VSHLL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="The data type for elements of operand">&lt;type&gt;</a><a link="sa_size" hover="The data size for elements of operand">&lt;size&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm" hover="The immediate value">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSHLL/T1A1_A.txt" mylink="aarch32.instrs.VSHLL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if imm6 IN {'000xxx'} then SEE "Related encodings";</line>
<line>if Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case imm6 of</line>
<line>    when '001xxx'  esize = 8;  elements = 8;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 8;</line>
<line>    when '01xxxx'  esize = 16;  elements = 4;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 16;</line>
<line>    when '1xxxxx'  esize = 32;  elements = 2;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 32;</line>
<line>if shift_amount == 0 then SEE "VMOVL";</line>
<line>unsigned = (U == '1');  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VSHLL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSHLL/T2A2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSHLL_T2" oneofinclass="1" oneof="4" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSHLL" />
        </docvars>
        <asmtemplate><text>VSHLL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="The data type for elements of operand">&lt;type&gt;</a><a link="sa_size" hover="The data size for elements of operand">&lt;size&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm" hover="The immediate value">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSHLL/T2A2_A.txt" mylink="aarch32.instrs.VSHLL.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' || Vd&lt;0&gt; == '1' then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;  shift_amount = esize;</line>
<line>unsigned = FALSE;  // Or TRUE without change of functionality</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSHLL_A1, VSHLL_A2" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1 and A2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHLL_T1, VSHLL_T2" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHLL_A1, VSHLL_A2, VSHLL_T1, VSHLL_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHLL_A1, VSHLL_A2, VSHLL_T1, VSHLL_T2" symboldefcount="1">
      <symbol link="sa_type">&lt;type&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The data type for the elements of the operand. It must be one of:</para>
          <list type="param">
            <listitem>
              <param>S</param><content>Signed. In encoding T1/A1, encoded as U = 0.</content>
            </listitem>
            <listitem>
              <param>U</param><content>Unsigned. In encoding T1/A1, encoded as U = 1.</content>
            </listitem>
            <listitem>
              <param>I</param><content>Untyped integer, Available only in encoding T2/A2.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHLL_A1, VSHLL_A2, VSHLL_T1, VSHLL_T2" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The data size for the elements of the operand. The following table shows the permitted values and their encodings:</para>
          <table cols="3">
            <tgroup>
              <thead>
                <row>
                  <entry>&lt;size&gt;</entry>
                  <entry>Encoding T1/A1</entry>
                  <entry>Encoding T2/A2</entry>
                </row>
              </thead>
              <tbody>
                <row>
                  <entry><value>8</value></entry>
                  <entry>Encoded as imm6&lt;5:3&gt; = <binarynumber>0b001</binarynumber></entry>
                  <entry>Encoded as size = <binarynumber>0b00</binarynumber></entry>
                </row>
                <row>
                  <entry><value>16</value></entry>
                  <entry>Encoded as imm6&lt;5:4&gt; = <binarynumber>0b01</binarynumber></entry>
                  <entry>Encoded as size = <binarynumber>0b01</binarynumber></entry>
                </row>
                <row>
                  <entry><value>32</value></entry>
                  <entry>Encoded as imm6&lt;5&gt; = 1</entry>
                  <entry>Encoded as size = <binarynumber>0b10</binarynumber></entry>
                </row>
              </tbody>
            </tgroup>
          </table>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHLL_A1, VSHLL_A2, VSHLL_T1, VSHLL_T2" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHLL_A1, VSHLL_A2, VSHLL_T1, VSHLL_T2" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHLL_A1, VSHLL_A2, VSHLL_T1, VSHLL_T2" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The immediate value. <syntax>&lt;imm&gt;</syntax> must lie in the range 1 to <syntax>&lt;size&gt;</syntax>, and:</para>
          <list type="unordered">
            <listitem><content>If <syntax>&lt;size&gt;</syntax> == <syntax>&lt;imm&gt;</syntax>, the encoding is T2/A2.</content></listitem>
            <listitem><content>Otherwise, the encoding is T1/A1, and:<list type="unordered"><listitem><content>If <syntax>&lt;size&gt;</syntax> == 8, <syntax>&lt;imm&gt;</syntax> is encoded in imm6&lt;2:0&gt;.</content></listitem><listitem><content>If <syntax>&lt;size&gt;</syntax> == 16, <syntax>&lt;imm&gt;</syntax> is encoded in imm6&lt;3:0&gt;.</content></listitem><listitem><content>If <syntax>&lt;size&gt;</syntax> == 32, <syntax>&lt;imm&gt;</syntax> is encoded in imm6&lt;4:0&gt;.</content></listitem></list></content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VSHLL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for e = 0 to elements-1</line>
<line>        result = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m],e,esize], unsigned) &lt;&lt; shift_amount;</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = result&lt;2*esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vshr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSHR" title="VSHR -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VSHR" />
  </docvars>
  <heading>VSHR</heading>
  <desc>
    <brief>
      <para>Vector Shift Right</para>
    </brief>
    <authored>
      <para>Vector Shift Right takes each element in a vector, right shifts them by an immediate value, and places the truncated results in the destination vector. For rounded results, see <xref linkend="A32T32-fpsimd.instructions.VRSHR">VRSHR</xref>.</para>
      <para>The operand and result elements must be the same size, and can be any one of:</para>
      <list type="unordered">
        <listitem><content>8-bit, 16-bit, 32-bit, or 64-bit signed integers.</content></listitem>
        <listitem><content>8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.</content></listitem>
      </list>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_1r_imm">Advanced SIMD one register and modified immediate</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd1reg_imm">Advanced SIMD one register and modified immediate</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VSHR" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSHR/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="L" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSHR_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSHR" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSHR</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSHR_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSHR" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSHR</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSHR/T1A1_A.txt" mylink="aarch32.instrs.VSHR.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (L:imm6) IN {'0000xxx'} then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case L:imm6 of</line>
<line>    when '0001xxx'  esize = 8;  elements = 8;  shift_amount = 16 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '001xxxx'  esize = 16;  elements = 4;  shift_amount = 32 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '01xxxxx'  esize = 32;  elements = 2;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '1xxxxxx'  esize = 64;  elements = 1;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>unsigned = (U == '1');  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VSHR" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSHR/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="L" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSHR_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSHR" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSHR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSHR_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSHR" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSHR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSHR/T1A1_A.txt" mylink="aarch32.instrs.VSHR.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (L:imm6) IN {'0000xxx'} then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case L:imm6 of</line>
<line>    when '0001xxx'  esize = 8;  elements = 8;  shift_amount = 16 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '001xxxx'  esize = 16;  elements = 4;  shift_amount = 32 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '01xxxxx'  esize = 32;  elements = 2;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '1xxxxxx'  esize = 64;  elements = 1;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>unsigned = (U == '1');  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSHR_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHR_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHR_A1_Q, VSHR_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHR_A1_Q, VSHR_T1_Q" symboldefcount="1">
      <symbol link="sa_type">&lt;type&gt;</symbol>
      <definition encodedin="U">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">&lt;type&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">S</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">U</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VSHR_A1_Q, VSHR_T1_Q" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="L:imm6&lt;5:3&gt;">
        <intro>Is the data size for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">L</entry>
                <entry class="bitfield">imm6&lt;5:3&gt;</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">001</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01x</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1xx</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">xxx</entry>
                <entry class="symbol">64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VSHR_A1_Q, VSHR_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHR_A1_Q, VSHR_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHR_A1_D, VSHR_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHR_A1_D, VSHR_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHR_A1_Q, VSHR_T1_Q" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm6">
        <intro>
          <para>Is an immediate value, in the range 1 to <syntax>&lt;size&gt;</syntax>, encoded in the "imm6" field as <syntax>&lt;size&gt;</syntax> - <syntax>&lt;imm&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VSHR/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            result = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], unsigned) &gt;&gt; shift_amount;</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result&lt;esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vshr_vorr_r.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSHR_VORR_r" title="VSHR (zero) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="VSHR" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VORR" />
  </docvars>
  <heading>VSHR (zero)</heading>
  <desc>
    <brief>Vector Shift Right</brief>
    <longer> copies the contents of one SIMD register to another</longer>
  </desc>
  <aliasto refiform="vorr_r.xml" iformid="VORR_r">VORR (register)</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VORR" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSHR_VORR_r_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VSHR" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSHR</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dm&gt;</a><text>, #0</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vorr_r.xml#VORR_r_A1_D">VORR</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VSHR_VORR_r_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VSHR" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSHR</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vorr_r.xml#VORR_r_A1_Q">VORR</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VORR" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSHR_VORR_r_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="alias_mnemonic" value="VSHR" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSHR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dm&gt;</a><text>, #0</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vorr_r.xml#VORR_r_T1_D">VORR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="VSHR_VORR_r_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="alias_mnemonic" value="VSHR" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VORR" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSHR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vorr_r.xml#VORR_r_T1_Q">VORR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSHR_VORR_r_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHR_VORR_r_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHR_VORR_r_A1_Q, VSHR_VORR_r_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHR_VORR_r_A1_Q, VSHR_VORR_r_T1_Q" symboldefcount="1">
      <symbol link="sa_dt_2">&lt;dt&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the data type for the elements of the vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHR_VORR_r_A1_Q, VSHR_VORR_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHR_VORR_r_A1_Q, VSHR_VORR_r_T1_Q" symboldefcount="1">
      <symbol link="sa_qm_1">&lt;Qm&gt;</symbol>
      <account encodedin="N:Vn&quot; and &quot;M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "N:Vn" and "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHR_VORR_r_A1_D, VSHR_VORR_r_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHR_VORR_r_A1_D, VSHR_VORR_r_T1_D" symboldefcount="1">
      <symbol link="sa_dm_1">&lt;Dm&gt;</symbol>
      <account encodedin="N:Vn&quot; and &quot;M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "N:Vn" and "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="vshrn.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSHRN" title="VSHRN -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VSHRN" />
  </docvars>
  <heading>VSHRN</heading>
  <desc>
    <brief>
      <para>Vector Shift Right Narrow</para>
    </brief>
    <authored>
      <para>Vector Shift Right Narrow takes each element in a vector, right shifts them by an immediate value, and places the truncated results in the destination vector. For rounded results, see <xref linkend="A32T32-fpsimd.instructions.VRSHRN">VRSHRN</xref>.</para>
      <para>The operand elements can be 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and unsigned integers. The destination elements are half the size of the source elements.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_1r_imm">Advanced SIMD one register and modified immediate</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd1reg_imm">Advanced SIMD one register and modified immediate</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VSHRN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSHRN/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSHRN_A1" oneofinclass="1" oneof="2" label="A1" bitdiffs="imm6 != 000xxx">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSHRN" />
        </docvars>
        <box hibit="21" width="6" name="imm6">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
        </box>
        <asmtemplate><text>VSHRN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I</text><a link="sa_size" hover="Data size for elements of vectors (field &quot;imm6&lt;5:3&gt;&quot;) [16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}/2] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSHRN/T1A1_A.txt" mylink="aarch32.instrs.VSHRN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if imm6 IN {'000xxx'} then SEE "Related encodings";</line>
<line>if Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case imm6 of</line>
<line>    when '001xxx'  esize = 8;  elements = 8;  shift_amount = 16 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '01xxxx'  esize = 16;  elements = 4;  shift_amount = 32 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '1xxxxx'  esize = 32;  elements = 2;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VSHRN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSHRN/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSHRN_T1" oneofinclass="1" oneof="2" label="T1" bitdiffs="imm6 != 000xxx">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSHRN" />
        </docvars>
        <box hibit="21" width="6" name="imm6">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
        </box>
        <asmtemplate><text>VSHRN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.I</text><a link="sa_size" hover="Data size for elements of vectors (field &quot;imm6&lt;5:3&gt;&quot;) [16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}/2] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSHRN/T1A1_A.txt" mylink="aarch32.instrs.VSHRN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if imm6 IN {'000xxx'} then SEE "Related encodings";</line>
<line>if Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case imm6 of</line>
<line>    when '001xxx'  esize = 8;  elements = 8;  shift_amount = 16 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '01xxxx'  esize = 16;  elements = 4;  shift_amount = 32 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '1xxxxx'  esize = 32;  elements = 2;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSHRN_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHRN_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHRN_A1, VSHRN_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHRN_A1, VSHRN_T1" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="imm6&lt;5:3&gt;">
        <intro>Is the data size for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">imm6&lt;5:3&gt;</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">001</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">01x</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">1xx</entry>
                <entry class="symbol">64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VSHRN_A1, VSHRN_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHRN_A1, VSHRN_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHRN_A1, VSHRN_T1" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm6">
        <intro>
          <para>Is an immediate value, in the range 1 to <syntax>&lt;size&gt;</syntax>/2, encoded in the "imm6" field as <syntax>&lt;size&gt;</syntax>/2 - <syntax>&lt;imm&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VSHRN/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for e = 0 to elements-1</line>
<line>        result = <a link="impl-shared.LSR.2" file="shared_pseudocode.xml" hover="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[m&gt;&gt;1],e,2*esize], shift_amount);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d],e,esize] = result&lt;esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vshrn_vmovn.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSHRN_VMOVN" title="VSHRN (zero) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="VSHRN" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMOVN" />
  </docvars>
  <heading>VSHRN (zero)</heading>
  <desc>
    <brief>Vector Shift Right Narrow</brief>
    <longer> takes each element in a vector, right shifts them by an immediate value, and places the truncated results in the destination vector</longer>
  </desc>
  <aliasto refiform="vmovn.xml" iformid="VMOVN">VMOVN</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMOVN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSHRN_VMOVN_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="alias_mnemonic" value="VSHRN" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOVN" />
        </docvars>
        <asmtemplate><text>VSHRN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vmovn.xml#VMOVN_A1">VMOVN</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMOVN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSHRN_VMOVN_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="alias_mnemonic" value="VSHRN" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOVN" />
        </docvars>
        <asmtemplate><text>VSHRN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vmovn.xml#VMOVN_T1">VMOVN</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operand (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSHRN_VMOVN_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHRN_VMOVN_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHRN_VMOVN_A1, VSHRN_VMOVN_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHRN_VMOVN_A1, VSHRN_VMOVN_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operand, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">I16</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">I32</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">I64</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VSHRN_VMOVN_A1, VSHRN_VMOVN_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSHRN_VMOVN_A1, VSHRN_VMOVN_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="vsli.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSLI" title="VSLI -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VSLI" />
  </docvars>
  <heading>VSLI</heading>
  <desc>
    <brief>
      <para>Vector Shift Left and Insert</para>
    </brief>
    <authored>
      <para>Vector Shift Left and Insert takes each element in the operand vector, left shifts them by an immediate value, and inserts the results in the destination vector. Bits shifted out of the left of each element are lost.</para>
      <para>The elements must all be the same size, and can be 8-bit, 16-bit, 32-bit, or 64-bit. There is no distinction between data types.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_1r_imm">Advanced SIMD one register and modified immediate</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd1reg_imm">Advanced SIMD one register and modified immediate</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VSLI" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSLI/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="L" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSLI_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSLI" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSLI</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [0-{syntax{&lt;size&gt;}}-1] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSLI_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSLI" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSLI</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [0-{syntax{&lt;size&gt;}}-1] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSLI/T1A1_A.txt" mylink="aarch32.instrs.VSLI.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (L:imm6) IN {'0000xxx'} then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case L:imm6 of</line>
<line>    when '0001xxx'  esize = 8;  elements = 8;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 8;</line>
<line>    when '001xxxx'  esize = 16;  elements = 4;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 16;</line>
<line>    when '01xxxxx'  esize = 32;  elements = 2;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 32;</line>
<line>    when '1xxxxxx'  esize = 64;  elements = 1;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VSLI" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSLI/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="L" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSLI_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSLI" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSLI</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [0-{syntax{&lt;size&gt;}}-1] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSLI_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSLI" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSLI</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [0-{syntax{&lt;size&gt;}}-1] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSLI/T1A1_A.txt" mylink="aarch32.instrs.VSLI.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (L:imm6) IN {'0000xxx'} then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case L:imm6 of</line>
<line>    when '0001xxx'  esize = 8;  elements = 8;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 8;</line>
<line>    when '001xxxx'  esize = 16;  elements = 4;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 16;</line>
<line>    when '01xxxxx'  esize = 32;  elements = 2;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6) - 32;</line>
<line>    when '1xxxxxx'  esize = 64;  elements = 1;  shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSLI_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSLI_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSLI_A1_Q, VSLI_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSLI_A1_Q, VSLI_T1_Q" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="L:imm6&lt;5:3&gt;">
        <intro>Is the data size for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">L</entry>
                <entry class="bitfield">imm6&lt;5:3&gt;</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">001</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01x</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1xx</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">xxx</entry>
                <entry class="symbol">64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VSLI_A1_Q, VSLI_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSLI_A1_Q, VSLI_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSLI_A1_D, VSLI_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSLI_A1_D, VSLI_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSLI_A1_Q, VSLI_T1_Q" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm6">
        <intro>
          <para>Is an immediate value, in the range 0 to <syntax>&lt;size&gt;</syntax>-1, encoded in the "imm6" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VSLI/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    mask = <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(esize), shift_amount);</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            shifted_op = <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], shift_amount);</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = (<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r],e,esize] AND NOT(mask)) OR shifted_op;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vsmmla.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSMMLA" title="VSMMLA -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VSMMLA" />
    <docvar key="simdvectorsize" value="quad" />
  </docvars>
  <heading>VSMMLA</heading>
  <desc>
    <brief>
      <para>Widening 8-bit signed integer matrix multiply-accumulate into 2x2 matrix</para>
    </brief>
    <authored>
      <para>The widening integer matrix multiply-accumulate instruction multiplies the 2x8 matrix of signed 8-bit integer values held in the first source vector by the 8x2 matrix of signed 8-bit integer values in the second source vector. The resulting 2x2 32-bit integer matrix product is destructively added to the 32-bit integer matrix accumulator held in the destination vector. This is equivalent to performing an 8-way dot product per destination element.</para>
      <para>From Armv8.2, this is an <arm-defined-word>optional</arm-defined-word> instruction. <xref linkend="AArch32.id_isar6">ID_ISAR6</xref>.I8MM indicates whether this instruction is supported in the T32 and A32 instruction sets.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VSMMLA" />
        <docvar key="simdvectorsize" value="quad" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_AA32I8MM" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/MMLA/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="B" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSMMLA_A1_Q" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSMMLA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <asmtemplate><text>VSMMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S8 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP third source and destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MMLA/A1_A.txt" mylink="aarch32.instrs.MMLA.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveAArch32Int8MatMulExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32Int8MatMulExt()">HaveAArch32Int8MatMulExt</a>() then UNDEFINED;</line>
<line>boolean op1_unsigned;</line>
<line>boolean op2_unsigned;</line>
<line>case B:U of</line>
<line>    when '00' op1_unsigned = FALSE; op2_unsigned = FALSE;</line>
<line>    when '01' op1_unsigned = TRUE;  op2_unsigned = TRUE;</line>
<line>    when '10' op1_unsigned = TRUE;  op2_unsigned = FALSE;</line>
<line>    when '11' UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VSMMLA" />
        <docvar key="simdvectorsize" value="quad" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_AA32I8MM" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/MMLA/T1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="B" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSMMLA_T1_Q" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSMMLA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <asmtemplate><text>VSMMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S8 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP third source and destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MMLA/T1_A.txt" mylink="aarch32.instrs.MMLA.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveAArch32Int8MatMulExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32Int8MatMulExt()">HaveAArch32Int8MatMulExt</a>() then UNDEFINED;</line>
<line>boolean op1_unsigned;</line>
<line>boolean op2_unsigned;</line>
<line>case B:U of</line>
<line>    when '00' op1_unsigned = FALSE; op2_unsigned = FALSE;</line>
<line>    when '01' op1_unsigned = TRUE;  op2_unsigned = TRUE;</line>
<line>    when '10' op1_unsigned = TRUE;  op2_unsigned = FALSE;</line>
<line>    when '11' UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSMMLA_A1_Q, VSMMLA_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSMMLA_A1_Q, VSMMLA_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP third source and destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSMMLA_A1_Q, VSMMLA_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSMMLA_A1_Q, VSMMLA_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MMLA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>bits(128) operand1 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[n&gt;&gt;1];</line>
<line>bits(128) operand2 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1];</line>
<line>bits(128) addend   = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[d&gt;&gt;1];</line>
<line></line>
<line><a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = <a link="impl-shared.MatMulAdd.5" file="shared_pseudocode.xml" hover="function: bits(N) MatMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, boolean op1_unsigned, boolean op2_unsigned)">MatMulAdd</a>(addend, operand1, operand2, op1_unsigned, op2_unsigned);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vsqrt.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSQRT" title="VSQRT -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VSQRT" />
  </docvars>
  <heading>VSQRT</heading>
  <desc>
    <brief>
      <para>Square Root</para>
    </brief>
    <authored>
      <para>Square Root calculates the square root of the value in a floating-point register and writes the result to another floating-point register.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VSQRT" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSQRT/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="o3" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSQRT_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSQRT" />
          <docvar key="mnemonic-fpdatasize" value="VSQRT-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VSQRT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSQRT_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSQRT" />
          <docvar key="mnemonic-fpdatasize" value="VSQRT-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VSQRT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSQRT_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSQRT" />
          <docvar key="mnemonic-fpdatasize" value="VSQRT-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VSQRT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSQRT/A1_A.txt" mylink="aarch32.instrs.VSQRT.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VSQRT" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSQRT/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="o3" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSQRT_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSQRT" />
          <docvar key="mnemonic-fpdatasize" value="VSQRT-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VSQRT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSQRT_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSQRT" />
          <docvar key="mnemonic-fpdatasize" value="VSQRT-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VSQRT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSQRT_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSQRT" />
          <docvar key="mnemonic-fpdatasize" value="VSQRT-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VSQRT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSQRT/T1_A.txt" mylink="aarch32.instrs.VSQRT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSQRT_A1_H, VSQRT_T1_H" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSQRT_A1_H, VSQRT_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSQRT_A1_H, VSQRT_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSQRT_A1_H, VSQRT_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSQRT_A1_D, VSQRT_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSQRT_A1_D, VSQRT_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VSQRT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    case esize of</line>
<line>        when 16 <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPSqrt.2" file="shared_pseudocode.xml" hover="function: bits(N) FPSqrt(bits(N) op, FPCRType fpcr)">FPSqrt</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[]);</line>
<line>        when 32 <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPSqrt.2" file="shared_pseudocode.xml" hover="function: bits(N) FPSqrt(bits(N) op, FPCRType fpcr)">FPSqrt</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[]);</line>
<line>        when 64 <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPSqrt.2" file="shared_pseudocode.xml" hover="function: bits(N) FPSqrt(bits(N) op, FPCRType fpcr)">FPSqrt</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vsra.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSRA" title="VSRA -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VSRA" />
  </docvars>
  <heading>VSRA</heading>
  <desc>
    <brief>
      <para>Vector Shift Right and Accumulate</para>
    </brief>
    <authored>
      <para>Vector Shift Right and Accumulate takes each element in a vector, right shifts them by an immediate value, and accumulates the truncated results into the destination vector. For rounded results, see <xref linkend="A32T32-fpsimd.instructions.VRSRA">VRSRA</xref>.</para>
      <para>The operand and result elements must all be the same type, and can be any one of:</para>
      <list type="unordered">
        <listitem><content>8-bit, 16-bit, 32-bit, or 64-bit signed integers.</content></listitem>
        <listitem><content>8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.</content></listitem>
      </list>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_1r_imm">Advanced SIMD one register and modified immediate</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd1reg_imm">Advanced SIMD one register and modified immediate</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VSRA" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSRA/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="L" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSRA_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSRA" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSRA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSRA_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSRA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSRA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSRA/T1A1_A.txt" mylink="aarch32.instrs.VSRA.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (L:imm6) IN {'0000xxx'} then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case L:imm6 of</line>
<line>    when '0001xxx'  esize = 8;  elements = 8;  shift_amount = 16 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '001xxxx'  esize = 16;  elements = 4;  shift_amount = 32 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '01xxxxx'  esize = 32;  elements = 2;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '1xxxxxx'  esize = 64;  elements = 1;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>unsigned = (U == '1');  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VSRA" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSRA/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="L" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSRA_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSRA" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSRA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSRA_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSRA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSRA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSRA/T1A1_A.txt" mylink="aarch32.instrs.VSRA.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (L:imm6) IN {'0000xxx'} then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case L:imm6 of</line>
<line>    when '0001xxx'  esize = 8;  elements = 8;  shift_amount = 16 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '001xxxx'  esize = 16;  elements = 4;  shift_amount = 32 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '01xxxxx'  esize = 32;  elements = 2;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '1xxxxxx'  esize = 64;  elements = 1;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>unsigned = (U == '1');  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSRA_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSRA_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSRA_A1_Q, VSRA_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSRA_A1_Q, VSRA_T1_Q" symboldefcount="1">
      <symbol link="sa_type">&lt;type&gt;</symbol>
      <definition encodedin="U">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">&lt;type&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">S</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">U</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VSRA_A1_Q, VSRA_T1_Q" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="L:imm6&lt;5:3&gt;">
        <intro>Is the data size for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">L</entry>
                <entry class="bitfield">imm6&lt;5:3&gt;</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">001</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01x</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1xx</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">xxx</entry>
                <entry class="symbol">64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VSRA_A1_Q, VSRA_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSRA_A1_Q, VSRA_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSRA_A1_D, VSRA_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSRA_A1_D, VSRA_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSRA_A1_Q, VSRA_T1_Q" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm6">
        <intro>
          <para>Is an immediate value, in the range 1 to <syntax>&lt;size&gt;</syntax>, encoded in the "imm6" field as <syntax>&lt;size&gt;</syntax> - <syntax>&lt;imm&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VSRA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            result = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], unsigned) &gt;&gt; shift_amount;</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r],e,esize] + result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vsri.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSRI" title="VSRI -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VSRI" />
  </docvars>
  <heading>VSRI</heading>
  <desc>
    <brief>
      <para>Vector Shift Right and Insert</para>
    </brief>
    <authored>
      <para>Vector Shift Right and Insert takes each element in the operand vector, right shifts them by an immediate value, and inserts the results in the destination vector. Bits shifted out of the right of each element are lost.</para>
      <para>The elements must all be the same size, and can be 8-bit, 16-bit, 32-bit, or 64-bit. There is no distinction between data types.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_1r_imm">Advanced SIMD one register and modified immediate</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd1reg_imm">Advanced SIMD one register and modified immediate</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VSRI" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSRI/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="L" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSRI_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSRI" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSRI</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSRI_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSRI" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSRI</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSRI/T1A1_A.txt" mylink="aarch32.instrs.VSRI.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (L:imm6) IN {'0000xxx'} then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case L:imm6 of</line>
<line>    when '0001xxx'  esize = 8;  elements = 8;  shift_amount = 16 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '001xxxx'  esize = 16;  elements = 4;  shift_amount = 32 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '01xxxxx'  esize = 32;  elements = 2;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '1xxxxxx'  esize = 64;  elements = 1;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VSRI" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSRI/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="L" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSRI_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSRI" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSRI</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSRI_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="!(imm6 == 000xxx &amp;&amp; L == 0) &amp;&amp; Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSRI" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="21" width="15" name="imm6:L">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
          <c>Z</c>
        </box>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSRI</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size for elements of vectors (field &quot;L:imm6&lt;5:3&gt;&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSRI/T1A1_A.txt" mylink="aarch32.instrs.VSRI.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if (L:imm6) IN {'0000xxx'} then SEE "Related encodings";</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>integer shift_amount;</line>
<line>case L:imm6 of</line>
<line>    when '0001xxx'  esize = 8;  elements = 8;  shift_amount = 16 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '001xxxx'  esize = 16;  elements = 4;  shift_amount = 32 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '01xxxxx'  esize = 32;  elements = 2;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>    when '1xxxxxx'  esize = 64;  elements = 1;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSRI_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSRI_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSRI_A1_Q, VSRI_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSRI_A1_Q, VSRI_T1_Q" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="L:imm6&lt;5:3&gt;">
        <intro>Is the data size for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">L</entry>
                <entry class="bitfield">imm6&lt;5:3&gt;</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">001</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01x</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1xx</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">xxx</entry>
                <entry class="symbol">64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VSRI_A1_Q, VSRI_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSRI_A1_Q, VSRI_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSRI_A1_D, VSRI_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSRI_A1_D, VSRI_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSRI_A1_Q, VSRI_T1_Q" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm6">
        <intro>
          <para>Is an immediate value, in the range 1 to <syntax>&lt;size&gt;</syntax>, encoded in the "imm6" field as <syntax>&lt;size&gt;</syntax> - <syntax>&lt;imm&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VSRI/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    mask = <a link="impl-shared.LSR.2" file="shared_pseudocode.xml" hover="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(esize), shift_amount);</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            shifted_op = <a link="impl-shared.LSR.2" file="shared_pseudocode.xml" hover="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], shift_amount);</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = (<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r],e,esize] AND NOT(mask)) OR shifted_op;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vst1_1.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VST1_1" title="VST1 (single element from one lane) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VST1" />
  </docvars>
  <heading>VST1 (single element from one lane)</heading>
  <desc>
    <brief>
      <para>Store single element from one lane of one register</para>
    </brief>
    <authored>
      <para>Store single element from one lane of one register stores one element to memory from one element of a register. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For more information about the variants of this instruction, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="6">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>, </txt>
      <a href="#iclass_a2">A2</a>
      <txt> and </txt>
      <a href="#iclass_a3">A3</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="6" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VST1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VST1_1/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST1_1_A1_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST1_1_A1_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST1_1_A1_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST1_1/T1A1_A.txt" mylink="aarch32.instrs.VST1_1.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if index_align&lt;0&gt; != '0' then UNDEFINED;</line>
<line>ebytes = 1;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:1&gt;);  alignment = 1;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="6" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VST1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VST1_1/T2A2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST1_1_A2_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST1_1_A2_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST1_1_A2_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST1_1/T2A2_A.txt" mylink="aarch32.instrs.VST1_1.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if index_align&lt;1&gt; != '0' then UNDEFINED;</line>
<line>ebytes = 2;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:2&gt;);</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A3" oneof="6" id="iclass_a3" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VST1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VST1_1/T3A3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST1_1_A3_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST1_1_A3_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST1_1_A3_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST1_1/T3A3_A.txt" mylink="aarch32.instrs.VST1_1.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if index_align&lt;2&gt; != '0' then UNDEFINED;</line>
<line>if index_align&lt;1:0&gt; != '00' &amp;&amp; index_align&lt;1:0&gt; != '11' then UNDEFINED;</line>
<line>ebytes = 4;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3&gt;);</line>
<line>alignment = if index_align&lt;1:0&gt; == '00' then 1 else 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="6" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VST1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VST1_1/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST1_1_T1_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST1_1_T1_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST1_1_T1_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST1_1/T1A1_A.txt" mylink="aarch32.instrs.VST1_1.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if index_align&lt;0&gt; != '0' then UNDEFINED;</line>
<line>ebytes = 1;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:1&gt;);  alignment = 1;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="6" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VST1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VST1_1/T2A2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST1_1_T2_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST1_1_T2_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST1_1_T2_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST1_1/T2A2_A.txt" mylink="aarch32.instrs.VST1_1.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if index_align&lt;1&gt; != '0' then UNDEFINED;</line>
<line>ebytes = 2;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:2&gt;);</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T3" oneof="6" id="iclass_t3" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VST1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VST1_1/T3A3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST1_1_T3_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST1_1_T3_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST1_1_T3_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&amp;FP register holding element (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{&lt;size&gt;}} == 8, {syntax{&lt;align&gt;}} must be omitted, otherwise it is the optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST1_1/T3A3_A.txt" mylink="aarch32.instrs.VST1_1.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if index_align&lt;2&gt; != '0' then UNDEFINED;</line>
<line>if index_align&lt;1:0&gt; != '00' &amp;&amp; index_align&lt;1:0&gt; != '11' then UNDEFINED;</line>
<line>ebytes = 4;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3&gt;);</line>
<line>alignment = if index_align&lt;1:0&gt; == '00' then 1 else 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VST1_1_A1_nowb, VST1_1_A2_nowb, VST1_1_A3_nowb" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1, A2 and A3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST1_1_T1_nowb, VST1_1_T2_nowb, VST1_1_T3_nowb" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1, T2 and T3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST1_1_A1_nowb, VST1_1_A2_nowb, VST1_1_A3_nowb, VST1_1_T1_nowb, VST1_1_T2_nowb, VST1_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST1_1_A1_nowb, VST1_1_A2_nowb, VST1_1_A3_nowb, VST1_1_T1_nowb, VST1_1_T2_nowb, VST1_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data size, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VST1_1_A1_nowb, VST1_1_A2_nowb, VST1_1_A3_nowb, VST1_1_T1_nowb, VST1_1_T2_nowb, VST1_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is a list containing the single 64-bit name of the SIMD&amp;FP register holding the element.</para>
          <para>The list must be <syntax>{ &lt;Dd&gt;[&lt;index&gt;] }</syntax>.</para>
          <para>The register <syntax>&lt;Dd&gt;</syntax> is encoded in the "D:Vd" field.</para>
          <para>The permitted values and encoding of <syntax>&lt;index&gt;</syntax> depend on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 8</param><content><syntax>&lt;index&gt;</syntax> is in the range 0 to 7, encoded in the "index_align&lt;3:1&gt;" field.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content><syntax>&lt;index&gt;</syntax> is in the range 0 to 3, encoded in the "index_align&lt;3:2&gt;" field.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content><syntax>&lt;index&gt;</syntax> is 0 or 1, encoded in the "index_align&lt;3&gt;" field.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST1_1_A1_nowb, VST1_1_A2_nowb, VST1_1_A3_nowb, VST1_1_T1_nowb, VST1_1_T2_nowb, VST1_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST1_1_A1_nowb, VST1_1_A2_nowb, VST1_1_A3_nowb, VST1_1_T1_nowb, VST1_1_T2_nowb, VST1_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_align">&lt;align&gt;</symbol>
      <account encodedin="index_align&lt;0&gt;">
        <intro>
          <para>When <syntax>&lt;size&gt;</syntax> == 8, <syntax>&lt;align&gt;</syntax> must be omitted, otherwise it is the optional alignment.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is omitted, the standard alignment is used, see <xref linkend="Chdijihg">Unaligned data access</xref>, and the encoding depends on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 8</param><content>Encoded in the "index_align&lt;0&gt;" field as <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content>Encoded in the "index_align&lt;1:0&gt;" field as <binarynumber>0b00</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content>Encoded in the "index_align&lt;2:0&gt;" field as <binarynumber>0b000</binarynumber>.</content>
            </listitem>
          </list>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is present, the permitted values and encoding depend on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content><syntax>&lt;align&gt;</syntax> is 16, meaning 16-bit alignment, encoded in the "index_align&lt;1:0&gt;" field as <binarynumber>0b01</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content><syntax>&lt;align&gt;</syntax> is 32, meaning 32-bit alignment, encoded in the "index_align&lt;2:0&gt;" field as <binarynumber>0b011</binarynumber>.</content>
            </listitem>
          </list>
          <para><value>:</value> is the preferred separator before the <syntax>&lt;align&gt;</syntax> value, but the alignment can be specified as <value>@&lt;align&gt;</value>, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST1_1_A1_postr, VST1_1_A2_postr, VST1_1_A3_postr, VST1_1_T1_postr, VST1_1_T2_postr, VST1_1_T3_postr" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VST1_1/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line></line>
<line>    boolean nontemporal = FALSE;</line>
<line>    boolean tagchecked  = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(<a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>, nontemporal, tagchecked);</line>
<line>    if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment) then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,ebytes] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d],index,8*ebytes];</line>
<line>    if wback then</line>
<line>        if register_index then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + ebytes;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vst1_m.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VST1_m" title="VST1 (multiple single elements) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VST1" />
  </docvars>
  <heading>VST1 (multiple single elements)</heading>
  <desc>
    <brief>
      <para>Store multiple single elements from one, two, three, or four registers</para>
    </brief>
    <authored>
      <para>Store multiple single elements from one, two, three, or four registers stores elements to memory from one, two, three, or four registers, without interleaving.  Every element of each register is stored. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGBBHGC">VST1 (multiple single elements)</xref>.</para>
      <para>Related encodings: See <xref linkend="T32.encoding_index.vldst">Advanced SIMD element or structure load/store</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimdls">Advanced SIMD element or structure load/store</xref> for the A32 instruction set.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For more information about <syntax>&lt;Rn&gt;</syntax>, <syntax>!</syntax>, and <syntax>&lt;Rm&gt;</syntax>, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="8">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>, </txt>
      <a href="#iclass_a2">A2</a>
      <txt>, </txt>
      <a href="#iclass_a3">A3</a>
      <txt> and </txt>
      <a href="#iclass_a4">A4</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt>, </txt>
      <a href="#iclass_t3">T3</a>
      <txt> and </txt>
      <a href="#iclass_t4">T4</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="8" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VST1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VST1_m/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST1_m_A1_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST1_m_A1_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST1_m_A1_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST1_m/T1A1_A.txt" mylink="aarch32.instrs.VST1_m.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>regs = 1;  if align&lt;1&gt; == '1' then UNDEFINED;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="8" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VST1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VST1_m/T2A2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST1_m_A2_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST1_m_A2_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST1_m_A2_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST1_m/T2A2_A.txt" mylink="aarch32.instrs.VST1_m.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>regs = 2;  if align == '11' then UNDEFINED;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d+regs &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d+regs &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A3" oneof="8" id="iclass_a3" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VST1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VST1_m/T3A3_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST1_m_A3_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST1_m_A3_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST1_m_A3_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST1_m/T3A3_A.txt" mylink="aarch32.instrs.VST1_m.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>regs = 3;  if align&lt;1&gt; == '1' then UNDEFINED;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d+regs &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d+regs &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A4" oneof="8" id="iclass_a4" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A4" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VST1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VST1_m/T4A4_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST1_m_A4_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A4" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST1_m_A4_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A4" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST1_m_A4_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A4" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST1_m/T4A4_A.txt" mylink="aarch32.instrs.VST1_m.T4A4_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>regs = 4;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d+regs &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A4" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d+regs &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="8" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VST1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VST1_m/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST1_m_T1_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST1_m_T1_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST1_m_T1_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST1_m/T1A1_A.txt" mylink="aarch32.instrs.VST1_m.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>regs = 1;  if align&lt;1&gt; == '1' then UNDEFINED;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="8" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VST1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VST1_m/T2A2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST1_m_T2_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST1_m_T2_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST1_m_T2_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST1_m/T2A2_A.txt" mylink="aarch32.instrs.VST1_m.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>regs = 2;  if align == '11' then UNDEFINED;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d+regs &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d+regs &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T3" oneof="8" id="iclass_t3" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VST1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VST1_m/T3A3_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST1_m_T3_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST1_m_T3_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST1_m_T3_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST1_m/T3A3_A.txt" mylink="aarch32.instrs.VST1_m.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>regs = 3;  if align&lt;1&gt; == '1' then UNDEFINED;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d+regs &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d+regs &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T4" oneof="8" id="iclass_t4" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T4" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VST1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VST1_m/T4A4_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST1_m_T4_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST1_m_T4_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST1_m_T4_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST1_m/T4A4_A.txt" mylink="aarch32.instrs.VST1_m.T4A4_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>regs = 4;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d+regs &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T4" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d+regs &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VST1_m_A1_nowb, VST1_m_A2_nowb, VST1_m_A3_nowb, VST1_m_A4_nowb" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1, A2, A3 and A4: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST1_m_T1_nowb, VST1_m_T2_nowb, VST1_m_T3_nowb, VST1_m_T4_nowb" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1, T2, T3 and T4: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST1_m_A1_nowb, VST1_m_A2_nowb, VST1_m_A3_nowb, VST1_m_A4_nowb, VST1_m_T1_nowb, VST1_m_T2_nowb, VST1_m_T3_nowb, VST1_m_T4_nowb" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST1_m_A1_nowb, VST1_m_A2_nowb, VST1_m_A3_nowb, VST1_m_A4_nowb, VST1_m_T1_nowb, VST1_m_T2_nowb, VST1_m_T3_nowb, VST1_m_T4_nowb" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data size, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VST1_m_A1_nowb, VST1_m_A2_nowb, VST1_m_A3_nowb, VST1_m_A4_nowb, VST1_m_T1_nowb, VST1_m_T2_nowb, VST1_m_T3_nowb, VST1_m_T4_nowb" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is a list containing the 64-bit names of the SIMD&amp;FP registers.</para>
          <para>The list must be one of:</para>
          <list type="param">
            <listitem>
              <param><syntax>{ &lt;Dd&gt; }</syntax></param><content>Single register. Selects the A1 and T1 encodings of the instruction.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+1&gt; }</syntax></param><content>Two single-spaced registers. Selects the A2 and T2 encodings of the instruction.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+1&gt;, &lt;Dd+2&gt; }</syntax></param><content>Three single-spaced registers. Selects the A3 and T3 encodings of the instruction.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+1&gt;, &lt;Dd+2&gt;, &lt;Dd+3&gt; }</syntax></param><content>Four single-spaced registers. Selects the A4 and T4 encodings of the instruction.</content>
            </listitem>
          </list>
          <para>The register <syntax>&lt;Dd&gt;</syntax> is encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST1_m_A1_nowb, VST1_m_A2_nowb, VST1_m_A3_nowb, VST1_m_A4_nowb, VST1_m_T1_nowb, VST1_m_T2_nowb, VST1_m_T3_nowb, VST1_m_T4_nowb" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST1_m_A1_nowb, VST1_m_A2_nowb, VST1_m_A3_nowb, VST1_m_A4_nowb, VST1_m_T1_nowb, VST1_m_T2_nowb, VST1_m_T3_nowb, VST1_m_T4_nowb" symboldefcount="1">
      <symbol link="sa_align">&lt;align&gt;</symbol>
      <account encodedin="align">
        <intro>
          <para>Is the optional alignment.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is omitted, the standard alignment is used, see <xref linkend="Chdijihg">Unaligned data access</xref>, and is encoded in the "align" field as <binarynumber>0b00</binarynumber>.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is present, the permitted values are:</para>
          <list type="param">
            <listitem>
              <param>64</param><content>64-bit alignment, encoded in the "align" field as <binarynumber>0b01</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>128</param><content>128-bit alignment, encoded in the "align" field as <binarynumber>0b10</binarynumber>. Available only if <syntax>&lt;list&gt;</syntax> contains two or four registers.</content>
            </listitem>
            <listitem>
              <param>256</param><content>256-bit alignment, encoded in the "align" field as <binarynumber>0b11</binarynumber>. Available only if <syntax>&lt;list&gt;</syntax> contains four registers.</content>
            </listitem>
          </list>
          <para><value>:</value> is the preferred separator before the <syntax>&lt;align&gt;</syntax> value, but the alignment can be specified as <value>@&lt;align&gt;</value>, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST1_m_A1_postr, VST1_m_A2_postr, VST1_m_A3_postr, VST1_m_A4_postr, VST1_m_T1_postr, VST1_m_T2_postr, VST1_m_T3_postr, VST1_m_T4_postr" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VST1_m/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line></line>
<line>    boolean nontemporal = FALSE;</line>
<line>    boolean tagchecked  = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(<a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>, nontemporal, tagchecked);</line>
<line>    if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment) then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            if ebytes != 8 then</line>
<line>                <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,ebytes] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r],e,8*ebytes];</line>
<line>            else</line>
<line>                if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, ebytes) &amp;&amp; <a link="impl-shared.AlignmentEnforced.0" file="shared_pseudocode.xml" hover="function: boolean AlignmentEnforced()">AlignmentEnforced</a>() then</line>
<line>                    <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>                bits(64) data = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r],e,64];</line>
<line>                if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_ASIMD" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_ASIMD</a>) then</line>
<line>                    <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,4] = data&lt;63:32&gt;;</line>
<line>                    <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address+4,4] = data&lt;31:0&gt;;</line>
<line>                else</line>
<line>                    <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,4] = data&lt;31:0&gt;;</line>
<line>                    <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address+4,4] = data&lt;63:32&gt;;</line>
<line></line>
<line>            address = address + ebytes;</line>
<line>    if wback then</line>
<line>        if register_index then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 8*regs;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vst2_1.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VST2_1" title="VST2 (single 2-element structure from one lane) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VST2" />
  </docvars>
  <heading>VST2 (single 2-element structure from one lane)</heading>
  <desc>
    <brief>
      <para>Store single 2-element structure from one lane of two registers</para>
    </brief>
    <authored>
      <para>Store single 2-element structure from one lane of two registers stores one 2-element structure to memory from corresponding elements of two registers. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGHAIBJ">VST2 (single 2-element structure from one lane)</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For more information about the variants of this instruction, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="6">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>, </txt>
      <a href="#iclass_a2">A2</a>
      <txt> and </txt>
      <a href="#iclass_a3">A3</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="6" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VST2" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VST2_1/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST2_1_A1_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST2_1_A1_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST2_1_A1_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST2_1/T1A1_A.txt" mylink="aarch32.instrs.VST2_1.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>ebytes = 1;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:1&gt;);  inc = 1;</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d2 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d2 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A2" oneof="6" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VST2" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VST2_1/T2A2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST2_1_A2_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST2_1_A2_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST2_1_A2_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST2_1/T2A2_A.txt" mylink="aarch32.instrs.VST2_1.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>ebytes = 2;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:2&gt;);</line>
<line>inc = if index_align&lt;1&gt; == '0' then 1 else 2;</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d2 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d2 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A3" oneof="6" id="iclass_a3" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VST2" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VST2_1/T3A3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST2_1_A3_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST2_1_A3_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST2_1_A3_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST2_1/T3A3_A.txt" mylink="aarch32.instrs.VST2_1.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if index_align&lt;1&gt; != '0' then UNDEFINED;</line>
<line>ebytes = 4;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3&gt;);</line>
<line>inc = if index_align&lt;2&gt; == '0' then 1 else 2;</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 8;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d2 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d2 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="6" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VST2" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VST2_1/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST2_1_T1_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST2_1_T1_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST2_1_T1_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST2_1/T1A1_A.txt" mylink="aarch32.instrs.VST2_1.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>ebytes = 1;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:1&gt;);  inc = 1;</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d2 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d2 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="6" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VST2" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VST2_1/T2A2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST2_1_T2_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST2_1_T2_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST2_1_T2_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST2_1/T2A2_A.txt" mylink="aarch32.instrs.VST2_1.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>ebytes = 2;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:2&gt;);</line>
<line>inc = if index_align&lt;1&gt; == '0' then 1 else 2;</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d2 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d2 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T3" oneof="6" id="iclass_t3" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VST2" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VST2_1/T3A3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST2_1_T3_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST2_1_T3_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST2_1_T3_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of two SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST2_1/T3A3_A.txt" mylink="aarch32.instrs.VST2_1.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if index_align&lt;1&gt; != '0' then UNDEFINED;</line>
<line>ebytes = 4;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3&gt;);</line>
<line>inc = if index_align&lt;2&gt; == '0' then 1 else 2;</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 8;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d2 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d2 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VST2_1_A1_nowb, VST2_1_A2_nowb, VST2_1_A3_nowb" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1, A2 and A3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST2_1_T1_nowb, VST2_1_T2_nowb, VST2_1_T3_nowb" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1, T2 and T3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST2_1_A1_nowb, VST2_1_A2_nowb, VST2_1_A3_nowb, VST2_1_T1_nowb, VST2_1_T2_nowb, VST2_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST2_1_A1_nowb, VST2_1_A2_nowb, VST2_1_A3_nowb, VST2_1_T1_nowb, VST2_1_T2_nowb, VST2_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data size, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VST2_1_A1_nowb, VST2_1_A2_nowb, VST2_1_A3_nowb, VST2_1_T1_nowb, VST2_1_T2_nowb, VST2_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="index_align&lt;1&gt;">
        <intro>
          <para>Is a list containing the 64-bit names of the two SIMD&amp;FP registers holding the element.</para>
          <para>The list must be one of:</para>
          <list type="param">
            <listitem>
              <param><syntax>{ &lt;Dd&gt;[&lt;index&gt;], &lt;Dd+1&gt;[&lt;index&gt;] }</syntax></param><content>Single-spaced registers, encoded as "spacing" = <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;[&lt;index&gt;], &lt;Dd+2&gt;[&lt;index&gt;] }</syntax></param><content>Double-spaced registers, encoded as "spacing" = <binarynumber>1</binarynumber>. Not permitted when <syntax>&lt;size&gt;</syntax> == 8.</content>
            </listitem>
          </list>
          <para>The encoding of "spacing" depends on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content>"spacing" is encoded in the "index_align&lt;1&gt;" field.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content>"spacing" is encoded in the "index_align&lt;2&gt;" field.</content>
            </listitem>
          </list>
          <para>The register <syntax>&lt;Dd&gt;</syntax> is encoded in the "D:Vd" field.</para>
          <para>The permitted values and encoding of <syntax>&lt;index&gt;</syntax> depend on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 8</param><content><syntax>&lt;index&gt;</syntax> is in the range 0 to 7, encoded in the "index_align&lt;3:1&gt;" field.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content><syntax>&lt;index&gt;</syntax> is in the range 0 to 3, encoded in the "index_align&lt;3:2&gt;" field.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content><syntax>&lt;index&gt;</syntax> is 0 or 1, encoded in the "index_align&lt;3&gt;" field.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST2_1_A1_nowb, VST2_1_A2_nowb, VST2_1_A3_nowb, VST2_1_T1_nowb, VST2_1_T2_nowb, VST2_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST2_1_A1_nowb, VST2_1_A2_nowb, VST2_1_A3_nowb, VST2_1_T1_nowb, VST2_1_T2_nowb, VST2_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_align">&lt;align&gt;</symbol>
      <account encodedin="index_align&lt;0&gt;">
        <intro>
          <para>Is the optional alignment.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is omitted, the standard alignment is used, see <xref linkend="Chdijihg">Unaligned data access</xref>, and the encoding depends on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 8</param><content>Encoded in the "index_align&lt;0&gt;" field as <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content>Encoded in the "index_align&lt;0&gt;" field as <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content>Encoded in the "index_align&lt;1:0&gt;" field as <binarynumber>0b00</binarynumber>.</content>
            </listitem>
          </list>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is present, the permitted values and encoding depend on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 8</param><content><syntax>&lt;align&gt;</syntax> is 16, meaning 16-bit alignment, encoded in the "index_align&lt;0&gt;" field as <binarynumber>1</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content><syntax>&lt;align&gt;</syntax> is 32, meaning 32-bit alignment, encoded in the "index_align&lt;0&gt;" field as <binarynumber>1</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content><syntax>&lt;align&gt;</syntax> is 64, meaning 64-bit alignment, encoded in the "index_align&lt;1:0&gt;" field as <binarynumber>0b01</binarynumber>.</content>
            </listitem>
          </list>
          <para><value>:</value> is the preferred separator before the <syntax>&lt;align&gt;</syntax> value, but the alignment can be specified as <value>@&lt;align&gt;</value>, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST2_1_A1_postr, VST2_1_A2_postr, VST2_1_A3_postr, VST2_1_T1_postr, VST2_1_T2_postr, VST2_1_T3_postr" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VST2_1/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line></line>
<line>    boolean nontemporal = FALSE;</line>
<line>    boolean tagchecked  = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(<a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>, nontemporal, tagchecked);</line>
<line>    if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment) then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,       ebytes] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d], index,8*ebytes];</line>
<line>    <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address+ebytes,ebytes] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d2],index,8*ebytes];</line>
<line>    if wback then</line>
<line>        if register_index then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 2*ebytes;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vst2_m.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VST2_m" title="VST2 (multiple 2-element structures) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VST2" />
  </docvars>
  <heading>VST2 (multiple 2-element structures)</heading>
  <desc>
    <brief>
      <para>Store multiple 2-element structures from two or four registers</para>
    </brief>
    <authored>
      <para>Store multiple 2-element structures from two or four registers stores multiple 2-element structures from two or four registers to memory, with interleaving. For more information, see <xref linkend="BABHJAGF">Element and structure load/store instructions</xref>. Every element of each register is saved. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGCHFEF">VST2 (multiple 2-element structures)</xref>.</para>
      <para>Related encodings: See <xref linkend="T32.encoding_index.vldst">Advanced SIMD element or structure load/store</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimdls">Advanced SIMD element or structure load/store</xref> for the A32 instruction set.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For more information about the variants of this instruction, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VST2" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VST2_m/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" usename="1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>x</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST2_m_A1_nowb" oneofinclass="3" oneof="12" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST2_m_A1_posti" oneofinclass="3" oneof="12" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST2_m_A1_postr" oneofinclass="3" oneof="12" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST2_m/T1A1_A.txt" mylink="aarch32.instrs.VST2_m.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>pairs = 1;  if align == '11' then UNDEFINED;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>inc = if itype == '1001' then 2 else 1;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d2+pairs &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d2+pairs &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VST2" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VST2_m/T2A2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST2_m_A2_nowb" oneofinclass="3" oneof="12" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST2_m_A2_posti" oneofinclass="3" oneof="12" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST2_m_A2_postr" oneofinclass="3" oneof="12" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST2_m/T2A2_A.txt" mylink="aarch32.instrs.VST2_m.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>pairs = 2;  inc = 2;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d2+pairs &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d2+pairs &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VST2" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VST2_m/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" usename="1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>x</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST2_m_T1_nowb" oneofinclass="3" oneof="12" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST2_m_T1_posti" oneofinclass="3" oneof="12" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST2_m_T1_postr" oneofinclass="3" oneof="12" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST2_m/T1A1_A.txt" mylink="aarch32.instrs.VST2_m.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>pairs = 1;  if align == '11' then UNDEFINED;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>inc = if itype == '1001' then 2 else 1;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d2+pairs &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d2+pairs &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VST2" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VST2_m/T2A2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST2_m_T2_nowb" oneofinclass="3" oneof="12" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST2_m_T2_posti" oneofinclass="3" oneof="12" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST2_m_T2_postr" oneofinclass="3" oneof="12" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST2" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST2</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST2_m/T2A2_A.txt" mylink="aarch32.instrs.VST2_m.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>pairs = 2;  inc = 2;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d2+pairs &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d2+pairs &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VST2_m_A1_nowb, VST2_m_A2_nowb" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1 and A2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST2_m_T1_nowb, VST2_m_T2_nowb" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST2_m_A1_nowb, VST2_m_A2_nowb, VST2_m_T1_nowb, VST2_m_T2_nowb" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST2_m_A1_nowb, VST2_m_A2_nowb, VST2_m_T1_nowb, VST2_m_T2_nowb" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data size, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VST2_m_A1_nowb, VST2_m_A2_nowb, VST2_m_T1_nowb, VST2_m_T2_nowb" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="itype">
        <intro>
          <para>Is a list containing the 64-bit names of the SIMD&amp;FP registers.</para>
          <para>The list must be one of:</para>
          <list type="param">
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+1&gt; }</syntax></param><content>Two single-spaced registers. Selects the A1 and T1 encodings of the instruction, and encoded in the "itype" field as <binarynumber>0b1000</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+2&gt; }</syntax></param><content>Two double-spaced registers. Selects the A1 and T1 encodings of the instruction, and encoded in the "itype" field as <binarynumber>0b1001</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+1&gt;, &lt;Dd+2&gt;, &lt;Dd+3&gt; }</syntax></param><content>Three single-spaced registers. Selects the A2 and T2 encodings of the instruction.</content>
            </listitem>
          </list>
          <para>The register <syntax>&lt;Dd&gt;</syntax> is encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST2_m_A1_nowb, VST2_m_A2_nowb, VST2_m_T1_nowb, VST2_m_T2_nowb" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST2_m_A1_nowb, VST2_m_A2_nowb, VST2_m_T1_nowb, VST2_m_T2_nowb" symboldefcount="1">
      <symbol link="sa_align">&lt;align&gt;</symbol>
      <account encodedin="align">
        <intro>
          <para>Is the optional alignment.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is omitted, the standard alignment is used, see <xref linkend="Chdijihg">Unaligned data access</xref>, and is encoded in the "align" field as <binarynumber>0b00</binarynumber>.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is present, the permitted values are:</para>
          <list type="param">
            <listitem>
              <param>64</param><content>64-bit alignment, encoded in the "align" field as <binarynumber>0b01</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>128</param><content>128-bit alignment, encoded in the "align" field as <binarynumber>0b10</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>256</param><content>256-bit alignment, encoded in the "align" field as <binarynumber>0b11</binarynumber>. Available only if <syntax>&lt;list&gt;</syntax> contains four registers.</content>
            </listitem>
          </list>
          <para><value>:</value> is the preferred separator before the <syntax>&lt;align&gt;</syntax> value, but the alignment can be specified as <value>@&lt;align&gt;</value>, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST2_m_A1_postr, VST2_m_A2_postr, VST2_m_T1_postr, VST2_m_T2_postr" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VST2_m/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line></line>
<line>    boolean nontemporal = FALSE;</line>
<line>    boolean tagchecked  = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(<a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>, nontemporal, tagchecked);</line>
<line>    if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment) then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    for r = 0 to pairs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,       ebytes] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r], e,8*ebytes];</line>
<line>            <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address+ebytes,ebytes] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d2+r],e,8*ebytes];</line>
<line>            address = address + 2*ebytes;</line>
<line>    if wback then</line>
<line>        if register_index then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 16*pairs;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vst3_1.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VST3_1" title="VST3 (single 3-element structure from one lane) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VST3" />
  </docvars>
  <heading>VST3 (single 3-element structure from one lane)</heading>
  <desc>
    <brief>
      <para>Store single 3-element structure from one lane of three registers</para>
    </brief>
    <authored>
      <para>Store single 3-element structure from one lane of three registers stores one 3-element structure to memory from corresponding elements of three registers. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGJAFCJ">VST3 (single 3-element structure from one lane)</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For more information about the variants of this instruction, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Alignment</para>
      <para>Standard alignment rules apply, see <xref linkend="CHDIDCCI">Alignment support</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="6">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>, </txt>
      <a href="#iclass_a2">A2</a>
      <txt> and </txt>
      <a href="#iclass_a3">A3</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="6" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VST3" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VST3_1/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST3_1_A1_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST3_1_A1_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST3_1_A1_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST3_1/T1A1_A.txt" mylink="aarch32.instrs.VST3_1.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if index_align&lt;0&gt; != '0' then UNDEFINED;</line>
<line>ebytes = 1;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:1&gt;);  inc = 1;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d3 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d3 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A2" oneof="6" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VST3" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VST3_1/T2A2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST3_1_A2_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST3_1_A2_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST3_1_A2_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST3_1/T2A2_A.txt" mylink="aarch32.instrs.VST3_1.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if index_align&lt;0&gt; != '0' then UNDEFINED;</line>
<line>ebytes = 2;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:2&gt;);</line>
<line>inc = if index_align&lt;1&gt; == '0' then 1 else 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d3 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d3 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A3" oneof="6" id="iclass_a3" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VST3" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VST3_1/T3A3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST3_1_A3_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST3_1_A3_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST3_1_A3_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST3_1/T3A3_A.txt" mylink="aarch32.instrs.VST3_1.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if index_align&lt;1:0&gt; != '00' then UNDEFINED;</line>
<line>ebytes = 4;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3&gt;);</line>
<line>inc = if index_align&lt;2&gt; == '0' then 1 else 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d3 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d3 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="6" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VST3" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VST3_1/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST3_1_T1_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST3_1_T1_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST3_1_T1_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST3_1/T1A1_A.txt" mylink="aarch32.instrs.VST3_1.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if index_align&lt;0&gt; != '0' then UNDEFINED;</line>
<line>ebytes = 1;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:1&gt;);  inc = 1;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d3 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d3 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="6" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VST3" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VST3_1/T2A2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST3_1_T2_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST3_1_T2_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST3_1_T2_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST3_1/T2A2_A.txt" mylink="aarch32.instrs.VST3_1.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if index_align&lt;0&gt; != '0' then UNDEFINED;</line>
<line>ebytes = 2;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:2&gt;);</line>
<line>inc = if index_align&lt;1&gt; == '0' then 1 else 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d3 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d3 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T3" oneof="6" id="iclass_t3" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VST3" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VST3_1/T3A3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST3_1_T3_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST3_1_T3_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST3_1_T3_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers holding element (field &quot;index_align&lt;0&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST3_1/T3A3_A.txt" mylink="aarch32.instrs.VST3_1.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if index_align&lt;1:0&gt; != '00' then UNDEFINED;</line>
<line>ebytes = 4;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3&gt;);</line>
<line>inc = if index_align&lt;2&gt; == '0' then 1 else 2;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d3 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d3 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VST3_1_A1_nowb, VST3_1_A2_nowb, VST3_1_A3_nowb" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1, A2 and A3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST3_1_T1_nowb, VST3_1_T2_nowb, VST3_1_T3_nowb" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1, T2 and T3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST3_1_A1_nowb, VST3_1_A2_nowb, VST3_1_A3_nowb, VST3_1_T1_nowb, VST3_1_T2_nowb, VST3_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST3_1_A1_nowb, VST3_1_A2_nowb, VST3_1_A3_nowb, VST3_1_T1_nowb, VST3_1_T2_nowb, VST3_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data size, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VST3_1_A1_nowb, VST3_1_A2_nowb, VST3_1_A3_nowb, VST3_1_T1_nowb, VST3_1_T2_nowb, VST3_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="index_align&lt;0&gt;">
        <intro>
          <para>Is a list containing the 64-bit names of the three SIMD&amp;FP registers holding the element.</para>
          <para>The list must be one of:</para>
          <list type="param">
            <listitem>
              <param><syntax>{ &lt;Dd&gt;[&lt;index&gt;], &lt;Dd+1&gt;[&lt;index&gt;], &lt;Dd+2&gt;[&lt;index&gt;] }</syntax></param><content>Single-spaced registers, encoded as "spacing" = <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;[&lt;index&gt;], &lt;Dd+2&gt;[&lt;index&gt;], &lt;Dd+4&gt;[&lt;index&gt;] }</syntax></param><content>Double-spaced registers, encoded as "spacing" = <binarynumber>1</binarynumber>. Not permitted when <syntax>&lt;size&gt;</syntax> == 8.</content>
            </listitem>
          </list>
          <para>The encoding of "spacing" depends on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 8</param><content>"spacing" is encoded in the "index_align&lt;0&gt;" field.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content>"spacing" is encoded in the "index_align&lt;1&gt;" field, and "index_align&lt;0&gt;" is set to <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content>"spacing" is encoded in the "index_align&lt;2&gt;" field, and "index_align&lt;1:0&gt;" is set to <binarynumber>0b00</binarynumber>.</content>
            </listitem>
          </list>
          <para>The register <syntax>&lt;Dd&gt;</syntax> is encoded in the "D:Vd" field.</para>
          <para>The permitted values and encoding of <syntax>&lt;index&gt;</syntax> depend on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 8</param><content><syntax>&lt;index&gt;</syntax> is in the range 0 to 7, encoded in the "index_align&lt;3:1&gt;" field.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content><syntax>&lt;index&gt;</syntax> is in the range 0 to 3, encoded in the "index_align&lt;3:2&gt;" field.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content><syntax>&lt;index&gt;</syntax> is 0 or 1, encoded in the "index_align&lt;3&gt;" field.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST3_1_A1_nowb, VST3_1_A2_nowb, VST3_1_A3_nowb, VST3_1_T1_nowb, VST3_1_T2_nowb, VST3_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST3_1_A1_postr, VST3_1_A2_postr, VST3_1_A3_postr, VST3_1_T1_postr, VST3_1_T2_postr, VST3_1_T3_postr" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VST3_1/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line>    <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,         ebytes] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d], index,8*ebytes];</line>
<line>    <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address+ebytes,  ebytes] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d2],index,8*ebytes];</line>
<line>    <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address+2*ebytes,ebytes] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d3],index,8*ebytes];</line>
<line>    if wback then</line>
<line>        if register_index then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 3*ebytes;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vst3_m.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VST3_m" title="VST3 (multiple 3-element structures) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VST3" />
  </docvars>
  <heading>VST3 (multiple 3-element structures)</heading>
  <desc>
    <brief>
      <para>Store multiple 3-element structures from three registers</para>
    </brief>
    <authored>
      <para>Store multiple 3-element structures from three registers stores multiple 3-element structures to memory from three registers, with interleaving. For more information, see <xref linkend="BABHJAGF">Element and structure load/store instructions</xref>. Every element of each register is saved. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGFHADE">VST3 (multiple 3-element structures)</xref>.</para>
      <para>Related encodings: See <xref linkend="T32.encoding_index.vldst">Advanced SIMD element or structure load/store</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimdls">Advanced SIMD element or structure load/store</xref> for the A32 instruction set.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For more information about the variants of this instruction, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VST3" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VST3_m/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" usename="1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>x</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST3_m_A1_nowb" oneofinclass="3" oneof="6" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST3_m_A1_posti" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST3_m_A1_postr" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST3_m/T1A1_A.txt" mylink="aarch32.instrs.VST3_m.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' || align&lt;1&gt; == '1' then UNDEFINED;</line>
<line>integer inc;</line>
<line>case itype of</line>
<line>    when '0100'</line>
<line>        inc = 1;</line>
<line>    when '0101'</line>
<line>        inc = 2;</line>
<line>    otherwise</line>
<line>        SEE "Related encodings";</line>
<line>alignment = if align&lt;0&gt; == '0' then 1 else 8;</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d3 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d3 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VST3" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VST3_m/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" usename="1" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>x</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST3_m_T1_nowb" oneofinclass="3" oneof="6" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST3_m_T1_posti" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST3_m_T1_postr" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST3_m/T1A1_A.txt" mylink="aarch32.instrs.VST3_m.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' || align&lt;1&gt; == '1' then UNDEFINED;</line>
<line>integer inc;</line>
<line>case itype of</line>
<line>    when '0100'</line>
<line>        inc = 1;</line>
<line>    when '0101'</line>
<line>        inc = 2;</line>
<line>    otherwise</line>
<line>        SEE "Related encodings";</line>
<line>alignment = if align&lt;0&gt; == '0' then 1 else 8;</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d3 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d3 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VST3_m_A1_nowb" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST3_m_T1_nowb" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST3_m_A1_nowb, VST3_m_T1_nowb" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST3_m_A1_nowb, VST3_m_T1_nowb" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data size, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VST3_m_A1_nowb, VST3_m_T1_nowb" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="itype">
        <intro>
          <para>Is a list containing the 64-bit names of the SIMD&amp;FP registers.</para>
          <para>The list must be one of:</para>
          <list type="param">
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+1&gt;, &lt;Dd+2&gt; }</syntax></param><content>Single-spaced registers, encoded in the "itype" field as <binarynumber>0b0100</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+2&gt;, &lt;Dd+4&gt; }</syntax></param><content>Double-spaced registers, encoded in the "itype" field as <binarynumber>0b0101</binarynumber>.</content>
            </listitem>
          </list>
          <para>The register <syntax>&lt;Dd&gt;</syntax> is encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST3_m_A1_nowb, VST3_m_T1_nowb" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST3_m_A1_nowb, VST3_m_T1_nowb" symboldefcount="1">
      <symbol link="sa_align">&lt;align&gt;</symbol>
      <account encodedin="align">
        <intro>
          <para>Is the optional alignment.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is omitted, the standard alignment is used, see <xref linkend="Chdijihg">Unaligned data access</xref>, and is encoded in the "align" field as <binarynumber>0b00</binarynumber>.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is present, the only permitted values is 64, meaning 64-bit alignment, encoded in the "align" field as <binarynumber>0b01</binarynumber>.</para>
          <para><value>:</value> is the preferred separator before the <syntax>&lt;align&gt;</syntax> value, but the alignment can be specified as <value>@&lt;align&gt;</value>, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST3_m_A1_postr, VST3_m_T1_postr" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VST3_m/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line></line>
<line>    boolean nontemporal = FALSE;</line>
<line>    boolean tagchecked  = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(<a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>, nontemporal, tagchecked);</line>
<line>    if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment) then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    for e = 0 to elements-1</line>
<line>        <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,         ebytes] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d], e,8*ebytes];</line>
<line>        <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address+ebytes,  ebytes] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d2],e,8*ebytes];</line>
<line>        <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address+2*ebytes,ebytes] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d3],e,8*ebytes];</line>
<line>        address = address + 3*ebytes;</line>
<line>    if wback then</line>
<line>        if register_index then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 24;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vst4_1.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VST4_1" title="VST4 (single 4-element structure from one lane) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VST4" />
  </docvars>
  <heading>VST4 (single 4-element structure from one lane)</heading>
  <desc>
    <brief>
      <para>Store single 4-element structure from one lane of four registers</para>
    </brief>
    <authored>
      <para>Store single 4-element structure from one lane of four registers stores one 4-element structure to memory from corresponding elements of four registers. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGHGCJI">VST4 (single 4-element structure from one lane)</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For more information about the variants of this instruction, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="6">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>, </txt>
      <a href="#iclass_a2">A2</a>
      <txt> and </txt>
      <a href="#iclass_a3">A3</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="6" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VST4" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VST4_1/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST4_1_A1_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST4_1_A1_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST4_1_A1_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST4_1/T1A1_A.txt" mylink="aarch32.instrs.VST4_1.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if size != '00' then SEE "Related encodings";</line>
<line>ebytes = 1;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:1&gt;);  inc = 1;</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  d4 = d3 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d4 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d4 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A2" oneof="6" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VST4" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VST4_1/T2A2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST4_1_A2_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST4_1_A2_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST4_1_A2_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST4_1/T2A2_A.txt" mylink="aarch32.instrs.VST4_1.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if size != '01' then SEE "Related encodings";</line>
<line>ebytes = 2;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:2&gt;);</line>
<line>inc = if index_align&lt;1&gt; == '0' then 1 else 2;</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 8;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  d4 = d3 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d4 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d4 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A3" oneof="6" id="iclass_a3" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VST4" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VST4_1/T3A3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST4_1_A3_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST4_1_A3_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST4_1_A3_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST4_1/T3A3_A.txt" mylink="aarch32.instrs.VST4_1.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if size != '10' then SEE "Related encodings";</line>
<line>if index_align&lt;1:0&gt; == '11' then UNDEFINED;</line>
<line>ebytes = 4;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3&gt;);</line>
<line>inc = if index_align&lt;2&gt; == '0' then 1 else 2;</line>
<line>alignment = if index_align&lt;1:0&gt; == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;1:0&gt;);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  d4 = d3 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d4 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d4 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="6" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VST4" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VST4_1/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST4_1_T1_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST4_1_T1_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST4_1_T1_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST4_1/T1A1_A.txt" mylink="aarch32.instrs.VST4_1.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if size != '00' then SEE "Related encodings";</line>
<line>ebytes = 1;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:1&gt;);  inc = 1;</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  d4 = d3 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d4 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d4 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="6" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VST4" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VST4_1/T2A2_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST4_1_T2_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST4_1_T2_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST4_1_T2_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST4_1/T2A2_A.txt" mylink="aarch32.instrs.VST4_1.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if size != '01' then SEE "Related encodings";</line>
<line>ebytes = 2;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3:2&gt;);</line>
<line>inc = if index_align&lt;1&gt; == '0' then 1 else 2;</line>
<line>alignment = if index_align&lt;0&gt; == '0' then 1 else 8;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  d4 = d3 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d4 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d4 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T3" oneof="6" id="iclass_t3" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VST4" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VST4_1/T3A3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" name="size" usename="1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="4" name="index_align" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST4_1_T3_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST4_1_T3_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VST4_1_T3_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of four SIMD&amp;FP registers holding element (field &quot;index_align&lt;1&gt;&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;index_align&lt;0&gt;&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST4_1/T3A3_A.txt" mylink="aarch32.instrs.VST4_1.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if size != '10' then SEE "Related encodings";</line>
<line>if index_align&lt;1:0&gt; == '11' then UNDEFINED;</line>
<line>ebytes = 4;  index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;3&gt;);</line>
<line>inc = if index_align&lt;2&gt; == '0' then 1 else 2;</line>
<line>alignment = if index_align&lt;1:0&gt; == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align&lt;1:0&gt;);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  d4 = d3 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d4 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d4 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VST4_1_A1_nowb, VST4_1_A2_nowb, VST4_1_A3_nowb" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1, A2 and A3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST4_1_T1_nowb, VST4_1_T2_nowb, VST4_1_T3_nowb" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1, T2 and T3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST4_1_A1_nowb, VST4_1_A2_nowb, VST4_1_A3_nowb, VST4_1_T1_nowb, VST4_1_T2_nowb, VST4_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST4_1_A1_nowb, VST4_1_A2_nowb, VST4_1_A3_nowb, VST4_1_T1_nowb, VST4_1_T2_nowb, VST4_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data size, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VST4_1_A1_nowb, VST4_1_A2_nowb, VST4_1_A3_nowb, VST4_1_T1_nowb, VST4_1_T2_nowb, VST4_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="index_align&lt;1&gt;">
        <intro>
          <para>Is a list containing the 64-bit names of the four SIMD&amp;FP registers holding the element.</para>
          <para>The list must be one of:</para>
          <list type="param">
            <listitem>
              <param><syntax>{ &lt;Dd&gt;[&lt;index&gt;], &lt;Dd+1&gt;[&lt;index&gt;], &lt;Dd+2&gt;[&lt;index&gt;], &lt;Dd+3&gt;[&lt;index&gt;] }</syntax></param><content>Single-spaced registers, encoded as "spacing" = <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;[&lt;index&gt;], &lt;Dd+2&gt;[&lt;index&gt;], &lt;Dd+4&gt;[&lt;index&gt;], &lt;Dd+6&gt;[&lt;index&gt;] }</syntax></param><content>Double-spaced registers, encoded as "spacing" = <binarynumber>1</binarynumber>. Not permitted when <syntax>&lt;size&gt;</syntax> == 8.</content>
            </listitem>
          </list>
          <para>The encoding of "spacing" depends on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content>"spacing" is encoded in the "index_align&lt;1&gt;" field.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content>"spacing" is encoded in the "index_align&lt;2&gt;" field.</content>
            </listitem>
          </list>
          <para>The register <syntax>&lt;Dd&gt;</syntax> is encoded in the "D:Vd" field.</para>
          <para>The permitted values and encoding of <syntax>&lt;index&gt;</syntax> depend on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 8</param><content><syntax>&lt;index&gt;</syntax> is in the range 0 to 7, encoded in the "index_align&lt;3:1&gt;" field.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content><syntax>&lt;index&gt;</syntax> is in the range 0 to 3, encoded in the "index_align&lt;3:2&gt;" field.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content><syntax>&lt;index&gt;</syntax> is 0 or 1, encoded in the "index_align&lt;3&gt;" field.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST4_1_A1_nowb, VST4_1_A2_nowb, VST4_1_A3_nowb, VST4_1_T1_nowb, VST4_1_T2_nowb, VST4_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST4_1_A1_nowb, VST4_1_A2_nowb, VST4_1_A3_nowb, VST4_1_T1_nowb, VST4_1_T2_nowb, VST4_1_T3_nowb" symboldefcount="1">
      <symbol link="sa_align">&lt;align&gt;</symbol>
      <account encodedin="index_align&lt;0&gt;">
        <intro>
          <para>Is the optional alignment.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is omitted, the standard alignment is used, see <xref linkend="Chdijihg">Unaligned data access</xref>, and the encoding depends on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 8</param><content>Encoded in the "index_align&lt;0&gt;" field as <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content>Encoded in the "index_align&lt;0&gt;" field as <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content>Encoded in the "index_align&lt;1:0&gt;" field as <binarynumber>0b00</binarynumber>.</content>
            </listitem>
          </list>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is present, the permitted values and encoding depend on <syntax>&lt;size&gt;</syntax>:</para>
          <list type="param">
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 8</param><content><syntax>&lt;align&gt;</syntax> is 32, meaning 32-bit alignment, encoded in the "index_align&lt;0&gt;" field as <binarynumber>1</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 16</param><content><syntax>&lt;align&gt;</syntax> is 64, meaning 64-bit alignment, encoded in the "index_align&lt;0&gt;" field as <binarynumber>1</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>&lt;size&gt;</syntax> == 32</param><content><syntax>&lt;align&gt;</syntax> can be 64 or 128. 64-bit alignment is encoded in the "index_align&lt;1:0&gt;" field as <binarynumber>0b01</binarynumber>, and 128-bit alignment is encoded in the "index_align&lt;1:0&gt;" field as <binarynumber>0b10</binarynumber>.</content>
            </listitem>
          </list>
          <para><value>:</value> is the preferred separator before the <syntax>&lt;align&gt;</syntax> value, but the alignment can be specified as <value>@&lt;align&gt;</value>, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST4_1_A1_postr, VST4_1_A2_postr, VST4_1_A3_postr, VST4_1_T1_postr, VST4_1_T2_postr, VST4_1_T3_postr" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VST4_1/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line></line>
<line>    boolean nontemporal = FALSE;</line>
<line>    boolean tagchecked  = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(<a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>, nontemporal, tagchecked);</line>
<line>    if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment) then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,         ebytes] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d], index,8*ebytes];</line>
<line>    <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address+ebytes,  ebytes] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d2],index,8*ebytes];</line>
<line>    <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address+2*ebytes,ebytes] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d3],index,8*ebytes];</line>
<line>    <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address+3*ebytes,ebytes] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d4],index,8*ebytes];</line>
<line>    if wback then</line>
<line>        if register_index then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 4*ebytes;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vst4_m.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VST4_m" title="VST4 (multiple 4-element structures) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VST4" />
  </docvars>
  <heading>VST4 (multiple 4-element structures)</heading>
  <desc>
    <brief>
      <para>Store multiple 4-element structures from four registers</para>
    </brief>
    <authored>
      <para>Store multiple 4-element structures from four registers stores multiple 4-element structures to memory from four registers, with interleaving. For more information, see <xref linkend="BABHJAGF">Element and structure load/store instructions</xref>. Every element of each register is saved. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGJJDEH">VST4 (multiple 4-element structures)</xref>.</para>
      <para>Related encodings: See <xref linkend="T32.encoding_index.vldst">Advanced SIMD element or structure load/store</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimdls">Advanced SIMD element or structure load/store</xref> for the A32 instruction set.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For more information about the variants of this instruction, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VST4" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VST4_m/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" usename="1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>x</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST4_m_A1_nowb" oneofinclass="3" oneof="6" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST4_m_A1_posti" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST4_m_A1_postr" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST4_m/T1A1_A.txt" mylink="aarch32.instrs.VST4_m.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>integer inc;</line>
<line>case itype of</line>
<line>    when '0000'</line>
<line>        inc = 1;</line>
<line>    when '0001'</line>
<line>        inc = 2;</line>
<line>    otherwise</line>
<line>        SEE "Related encodings";</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  d4 = d3 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d4 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d4 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VST4" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VST4_m/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" usename="1" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>x</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VST4_m_T1_nowb" oneofinclass="3" oneof="6" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VST4_m_T1_posti" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VST4_m_T1_postr" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VST4" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VST4</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;itype&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VST4_m/T1A1_A.txt" mylink="aarch32.instrs.VST4_m.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>integer inc;</line>
<line>case itype of</line>
<line>    when '0000'</line>
<line>        inc = 1;</line>
<line>    when '0001'</line>
<line>        inc = 2;</line>
<line>    otherwise</line>
<line>        SEE "Related encodings";</line>
<line>alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);</line>
<line>ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  d4 = d3 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</line>
<line>wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);</line>
<line>if n == 15 || d4 &gt; 31 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>d4 &gt; 31</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VST4_m_A1_nowb" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST4_m_T1_nowb" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST4_m_A1_nowb, VST4_m_T1_nowb" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST4_m_A1_nowb, VST4_m_T1_nowb" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data size, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VST4_m_A1_nowb, VST4_m_T1_nowb" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="itype">
        <intro>
          <para>Is a list containing the 64-bit names of the SIMD&amp;FP registers.</para>
          <para>The list must be one of:</para>
          <list type="param">
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+1&gt;, &lt;Dd+2&gt;, &lt;Dd+3&gt; }</syntax></param><content>Single-spaced registers, encoded in the "itype" field as <binarynumber>0b0000</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+2&gt;, &lt;Dd+4&gt;, &lt;Dd+6&gt; }</syntax></param><content>Double-spaced registers, encoded in the "itype" field as <binarynumber>0b0001</binarynumber>.</content>
            </listitem>
          </list>
          <para>The register <syntax>&lt;Dd&gt;</syntax> is encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST4_m_A1_nowb, VST4_m_T1_nowb" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST4_m_A1_nowb, VST4_m_T1_nowb" symboldefcount="1">
      <symbol link="sa_align">&lt;align&gt;</symbol>
      <account encodedin="align">
        <intro>
          <para>Is the optional alignment.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is omitted, the standard alignment is used, see <xref linkend="Chdijihg">Unaligned data access</xref>, and is encoded in the "align" field as <binarynumber>0b00</binarynumber>.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is present, the permitted values are:</para>
          <list type="param">
            <listitem>
              <param>64</param><content>64-bit alignment, encoded in the "align" field as <binarynumber>0b01</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>128</param><content>128-bit alignment, encoded in the "align" field as <binarynumber>0b10</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>256</param><content>256-bit alignment, encoded in the "align" field as <binarynumber>0b11</binarynumber>.</content>
            </listitem>
          </list>
          <para><value>:</value> is the preferred separator before the <syntax>&lt;align&gt;</syntax> value, but the alignment can be specified as <value>@&lt;align&gt;</value>, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VST4_m_A1_postr, VST4_m_T1_postr" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VST4_m/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];</line>
<line></line>
<line>    boolean nontemporal = FALSE;</line>
<line>    boolean tagchecked  = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(<a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>, nontemporal, tagchecked);</line>
<line>    if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment) then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    for e = 0 to elements-1</line>
<line>        <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,         ebytes] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d], e,8*ebytes];</line>
<line>        <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address+ebytes,  ebytes] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d2],e,8*ebytes];</line>
<line>        <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address+2*ebytes,ebytes] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d3],e,8*ebytes];</line>
<line>        <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address+3*ebytes,ebytes] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d4],e,8*ebytes];</line>
<line>        address = address + 4*ebytes;</line>
<line>    if wback then</line>
<line>        if register_index then</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 32;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vstm.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSTM" title="VSTM, VSTMDB, VSTMIA -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
  </docvars>
  <heading>VSTM, VSTMDB, VSTMIA</heading>
  <desc>
    <brief>
      <para>Store multiple SIMD&amp;FP registers</para>
    </brief>
    <authored>
      <para>Store multiple SIMD&amp;FP registers stores multiple registers from the Advanced SIMD and floating-point register file to consecutive memory locations using an address from a general-purpose register.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGJEBFH">VSTM</xref>.</para>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simdfp_mov64">Advanced SIMD and floating-point 64-bit move</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.movsimdfpgp64">Advanced SIMD and floating-point 64-bit move</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="1">
    <alias_list_intro>This instruction is used by the alias </alias_list_intro>
    <aliasref aliaspageid="VPUSH_VSTM" aliasfile="vpush_vstm.xml" hover="Push SIMD&amp;FP registers to Stack" punct=".">
      <text>VPUSH</text>
      <aliaspref>P == '1' &amp;&amp; U == '0' &amp;&amp; W == '1' &amp;&amp; Rn == '1101'</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink />
      <text> below for details of when the alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="fpdatasize" value="doubleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSTM/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="7" name="imm8&lt;7:1&gt;" usename="1">
          <c colspan="7"></c>
        </box>
        <box hibit="0" name="imm8&lt;0&gt;" usename="1" settings="1">
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="VSTMDB_A1" oneofinclass="2" oneof="8" label="Decrement Before" bitdiffs="P == 1 &amp;&amp; U == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="VSTMDB" />
          <docvar key="mnemonic-fpdatasize" value="VSTMDB-doubleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>VSTMDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>!, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSTM_A1" oneofinclass="2" oneof="8" label="Increment After" bitdiffs="P == 0 &amp;&amp; U == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="inc-after" />
          <docvar key="mnemonic" value="VSTM" />
          <docvar key="mnemonic-fpdatasize" value="VSTM-doubleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>1</c>
        </box>
        <asmtemplate><text>VSTM</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="Specifies base register writeback (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
        <asmtemplate><text>VSTMIA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="Specifies base register writeback (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSTM/T1A1_A.txt" mylink="aarch32.instrs.VSTM.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; U == '0' &amp;&amp; W == '0' then SEE "Related encodings";</line>
<line>if P == '1' &amp;&amp; W == '0' then SEE "VSTR";</line>
<line>if P == U &amp;&amp; W == '1' then UNDEFINED;</line>
<line>// Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)</line>
<line>single_regs = FALSE;  add = (U == '1');  wback = (W == '1');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
<line>regs = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm8) DIV 2;  // If UInt(imm8) is odd, see "FSTDBMX, FSTMIAX".</line>
<line>if n == 15 &amp;&amp; (wback || <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>) then UNPREDICTABLE;</line>
<line>if regs == 0 || regs &gt; 16 || (d+regs) &gt; 32 then UNPREDICTABLE;</line>
<line>if imm8&lt;0&gt; == '1' &amp;&amp; (d+regs) &gt; 16 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>regs == 0</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction operates as a <instruction>VSTM</instruction> with the same addressing mode but stores no registers.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>regs &gt; 16 || (d+regs) &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="fpdatasize" value="singleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSTM/T2A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="VSTMDB_A2" oneofinclass="2" oneof="8" label="Decrement Before" bitdiffs="P == 1 &amp;&amp; U == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="VSTMDB" />
          <docvar key="mnemonic-fpdatasize" value="VSTMDB-singleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>VSTMDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>!, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSTM_A2" oneofinclass="2" oneof="8" label="Increment After" bitdiffs="P == 0 &amp;&amp; U == 1">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="inc-after" />
          <docvar key="mnemonic" value="VSTM" />
          <docvar key="mnemonic-fpdatasize" value="VSTM-singleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>1</c>
        </box>
        <asmtemplate><text>VSTM</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="Specifies base register writeback (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
        <asmtemplate><text>VSTMIA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="Specifies base register writeback (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSTM/T2A2_A.txt" mylink="aarch32.instrs.VSTM.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; U == '0' &amp;&amp; W == '0' then SEE "Related encodings";</line>
<line>if P == '1' &amp;&amp; W == '0' then SEE "VSTR";</line>
<line>if P == U &amp;&amp; W == '1' then UNDEFINED;</line>
<line>// Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)</line>
<line>single_regs = TRUE;  add = (U == '1');  wback = (W == '1');  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);  regs = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm8);</line>
<line>if n == 15 &amp;&amp; (wback || <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>) then UNPREDICTABLE;</line>
<line>if regs == 0 || (d+regs) &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>regs == 0</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction operates as a <instruction>VSTM</instruction> with the same addressing mode but stores no registers.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>(d+regs) &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="fpdatasize" value="doubleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSTM/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="7" name="imm8&lt;7:1&gt;" usename="1">
          <c colspan="7"></c>
        </box>
        <box hibit="0" name="imm8&lt;0&gt;" usename="1" settings="1">
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="VSTMDB_T1" oneofinclass="2" oneof="8" label="Decrement Before" bitdiffs="P == 1 &amp;&amp; U == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="VSTMDB" />
          <docvar key="mnemonic-fpdatasize" value="VSTMDB-doubleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>VSTMDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>!, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSTM_T1" oneofinclass="2" oneof="8" label="Increment After" bitdiffs="P == 0 &amp;&amp; U == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="ldmstm-mode" value="inc-after" />
          <docvar key="mnemonic" value="VSTM" />
          <docvar key="mnemonic-fpdatasize" value="VSTM-doubleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>1</c>
        </box>
        <asmtemplate><text>VSTM</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="Specifies base register writeback (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
        <asmtemplate><text>VSTMIA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="Specifies base register writeback (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSTM/T1A1_A.txt" mylink="aarch32.instrs.VSTM.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; U == '0' &amp;&amp; W == '0' then SEE "Related encodings";</line>
<line>if P == '1' &amp;&amp; W == '0' then SEE "VSTR";</line>
<line>if P == U &amp;&amp; W == '1' then UNDEFINED;</line>
<line>// Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)</line>
<line>single_regs = FALSE;  add = (U == '1');  wback = (W == '1');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
<line>regs = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm8) DIV 2;  // If UInt(imm8) is odd, see "FSTDBMX, FSTMIAX".</line>
<line>if n == 15 &amp;&amp; (wback || <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>) then UNPREDICTABLE;</line>
<line>if regs == 0 || regs &gt; 16 || (d+regs) &gt; 32 then UNPREDICTABLE;</line>
<line>if imm8&lt;0&gt; == '1' &amp;&amp; (d+regs) &gt; 16 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>regs == 0</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction operates as a <instruction>VSTM</instruction> with the same addressing mode but stores no registers.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>regs &gt; 16 || (d+regs) &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="fpdatasize" value="singleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSTM/T2A2_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="VSTMDB_T2" oneofinclass="2" oneof="8" label="Decrement Before" bitdiffs="P == 1 &amp;&amp; U == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="VSTMDB" />
          <docvar key="mnemonic-fpdatasize" value="VSTMDB-singleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>VSTMDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>!, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSTM_T2" oneofinclass="2" oneof="8" label="Increment After" bitdiffs="P == 0 &amp;&amp; U == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="ldmstm-mode" value="inc-after" />
          <docvar key="mnemonic" value="VSTM" />
          <docvar key="mnemonic-fpdatasize" value="VSTM-singleprec" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="23" width="1" name="U">
          <c>1</c>
        </box>
        <asmtemplate><text>VSTM</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="Specifies base register writeback (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
        <asmtemplate><text>VSTMIA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><a link="sa_0d33" hover="Specifies base register writeback (field &quot;W&quot;)">{!}</a><text>, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSTM/T2A2_A.txt" mylink="aarch32.instrs.VSTM.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if P == '0' &amp;&amp; U == '0' &amp;&amp; W == '0' then SEE "Related encodings";</line>
<line>if P == '1' &amp;&amp; W == '0' then SEE "VSTR";</line>
<line>if P == U &amp;&amp; W == '1' then UNDEFINED;</line>
<line>// Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)</line>
<line>single_regs = TRUE;  add = (U == '1');  wback = (W == '1');  d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);  regs = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm8);</line>
<line>if n == 15 &amp;&amp; (wback || <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>) then UNPREDICTABLE;</line>
<line>if regs == 0 || (d+regs) &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>regs == 0</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction operates as a <instruction>VSTM</instruction> with the same addressing mode but stores no registers.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>(d+regs) &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The memory locations specified by the instruction and the number of registers specified by the instruction become <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, then that register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any other memory locations.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSTM_A1, VSTM_A2, VSTM_T1, VSTM_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSTM_A1, VSTM_A2, VSTM_T1, VSTM_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSTM_A1, VSTM_A2, VSTM_T1, VSTM_T2" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>An optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers being transferred.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSTM_A1, VSTM_A2, VSTM_T1, VSTM_T2" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field. If writeback is not specified, the PC can be used. However, Arm deprecates use of the PC.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSTM_A1, VSTM_A2, VSTM_T1, VSTM_T2" symboldefcount="1">
      <symbol link="sa_0d33">!</symbol>
      <account encodedin="W">
        <intro>
          <para>Specifies base register writeback. Encoded in the "W" field as 1 if present, otherwise 0.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSTM_A2, VSTM_T2" symboldefcount="1">
      <symbol link="sa_sreglist">&lt;sreglist&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the list of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred. The first register in the list is encoded in "Vd:D", and "imm8" is set to the number of registers in the list. The list must contain at least one register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSTM_A1, VSTM_T1" symboldefcount="1">
      <symbol link="sa_dreglist">&lt;dreglist&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the list of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred. The first register in the list is encoded in "D:Vd", and "imm8" is set to twice the number of registers in the list. The list must contain at least one register, and must not contain more than 16 registers.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VSTM/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    address = if add then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]-imm32;</line>
<line>    for r = 0 to regs-1</line>
<line>        if single_regs then</line>
<line>            <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,4] = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d+r];</line>
<line>            address = address+4;</line>
<line>        else</line>
<line>            // Store as two word-aligned words in the correct order for current endianness.</line>
<line>            if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_ASIMD" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_ASIMD</a>) then</line>
<line>                <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,4] =  <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r]&lt;63:32&gt;;</line>
<line>                <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address+4,4] =  <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r]&lt;31:0&gt;;</line>
<line>            else</line>
<line>                <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,4] = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r]&lt;31:0&gt;;</line>
<line>                <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address+4,4] = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r]&lt;63:32&gt;;</line>
<line></line>
<line>            address = address+8;</line>
<line></line>
<line>    if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = if add then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]+imm32 else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]-imm32;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vstr.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSTR" title="VSTR -- AArch32" type="instruction">
  <docvars>
    <docvar key="address-form" value="base-plus-offset" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VSTR" />
  </docvars>
  <heading>VSTR</heading>
  <desc>
    <brief>
      <para>Store SIMD&amp;FP register</para>
    </brief>
    <authored>
      <para>Store SIMD&amp;FP register stores a single register from the Advanced SIMD and floating-point register file to memory, using an address from a general-purpose register, with an optional offset.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VSTR" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSTR/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="VSTR_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSTR" />
          <docvar key="mnemonic-fpdatasize" value="VSTR-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VSTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP source register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VSTR_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSTR" />
          <docvar key="mnemonic-fpdatasize" value="VSTR-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VSTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><a link="sa_32" hover="Optional data size specifier for 32-bit memory accesses that can be used in the assembler source code">{.32}</a><text> </text><a link="sa_sd" hover="32-bit SIMD&amp;FP source register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VSTR_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSTR" />
          <docvar key="mnemonic-fpdatasize" value="VSTR-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VSTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><a link="sa_64" hover="Optional data size specifier for 64-bit memory accesses that can be used in the assembler source code">{.64}</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP source register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSTR/A1_A.txt" mylink="aarch32.instrs.VSTR.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  add = (U == '1');</line>
<line>imm32 = if esize == 16 then <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'0', 32) else <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
<line>integer d;</line>
<line>case size of</line>
<line>    when '01' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '10' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '11' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if n == 15 &amp;&amp; <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VSTR" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSTR/T1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="VSTR_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSTR" />
          <docvar key="mnemonic-fpdatasize" value="VSTR-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VSTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP source register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VSTR_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSTR" />
          <docvar key="mnemonic-fpdatasize" value="VSTR-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VSTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><a link="sa_32" hover="Optional data size specifier for 32-bit memory accesses that can be used in the assembler source code">{.32}</a><text> </text><a link="sa_sd" hover="32-bit SIMD&amp;FP source register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VSTR_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSTR" />
          <docvar key="mnemonic-fpdatasize" value="VSTR-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VSTR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><a link="sa_64" hover="Optional data size specifier for 64-bit memory accesses that can be used in the assembler source code">{.64}</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP source register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSTR/T1_A.txt" mylink="aarch32.instrs.VSTR.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  add = (U == '1');</line>
<line>imm32 = if esize == 16 then <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'0', 32) else <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);</line>
<line>integer d;</line>
<line>case size of</line>
<line>    when '01' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '10' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);</line>
<line>    when '11' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</line>
<line>if n == 15 &amp;&amp; <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSTR_A1_H, VSTR_T1_H" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSTR_A1_H, VSTR_T1_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSTR_A1_D, VSTR_T1_D" symboldefcount="1">
      <symbol link="sa_64">.64</symbol>
      <account encodedin="">
        <intro>
          <para>Is an optional data size specifier for 64-bit memory accesses that can be used in the assembler source code, but is otherwise ignored.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSTR_A1_D, VSTR_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSTR_A1_S, VSTR_T1_S" symboldefcount="1">
      <symbol link="sa_32">.32</symbol>
      <account encodedin="">
        <intro>
          <para>Is an optional data size specifier for 32-bit memory accesses that can be used in the assembler source code, but is otherwise ignored.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSTR_A1_H, VSTR_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSTR_A1_H, VSTR_T1_H" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSTR_A1_H, VSTR_T1_H" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VSTR_A1_H, VSTR_T1_H" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <intro>
          <para>For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset, a multiple of 4, in the range 0 to 1020, defaulting to 0, and encoded in the "imm8" field as &lt;imm&gt;/4.</para>
          <para>For the half-precision scalar variant: is the optional unsigned immediate byte offset, a multiple of 2, in the range 0 to 510, defaulting to 0, and encoded in the "imm8" field as &lt;imm&gt;/2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VSTR/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);</line>
<line>    address = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);</line>
<line>    case esize of</line>
<line>        when 16</line>
<line>            <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,2] = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]&lt;15:0&gt;;</line>
<line>        when 32</line>
<line>            <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,4] = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d];</line>
<line>        when 64</line>
<line>            // Store as two word-aligned words in the correct order for current endianness.</line>
<line>            if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_ASIMD" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_ASIMD</a>) then</line>
<line>                <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,4]   = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d]&lt;63:32&gt;;</line>
<line>                <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address+4,4] = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d]&lt;31:0&gt;;</line>
<line>            else</line>
<line>                <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,4]   = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d]&lt;31:0&gt;;</line>
<line>                <a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address+4,4] = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d]&lt;63:32&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vsub_f.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSUB_f" title="VSUB (floating-point) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VSUB" />
  </docvars>
  <heading>VSUB (floating-point)</heading>
  <desc>
    <brief>
      <para>Vector Subtract (floating-point)</para>
    </brief>
    <authored>
      <para>Vector Subtract (floating-point) subtracts the elements of one vector from the corresponding elements of another vector, and places the results in the destination vector.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VSUB" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSUB_f/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSUB_f_A1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSUB" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSUB</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSUB_f_A1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSUB" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSUB</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSUB_f/A1_A.txt" mylink="aarch32.instrs.VSUB_f.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>advsimd = TRUE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VSUB" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSUB_f/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSUB_f_A2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSUB" />
          <docvar key="mnemonic-fpdatasize" value="VSUB-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VSUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><text>{</text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSUB_f_A2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSUB" />
          <docvar key="mnemonic-fpdatasize" value="VSUB-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VSUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><text>{</text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSUB_f_A2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSUB" />
          <docvar key="mnemonic-fpdatasize" value="VSUB-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VSUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSUB_f/A2_A.txt" mylink="aarch32.instrs.VSUB_f.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; cond != '1110' then UNPREDICTABLE;</line>
<line>advsimd = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; cond != '1110'</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VSUB" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSUB_f/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="sz" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSUB_f_T1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSUB" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSUB_f_T1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSUB" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;sz&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSUB_f/T1_A.txt" mylink="aarch32.instrs.VSUB_f.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;</line>
<line>if sz == '1' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>advsimd = TRUE;</line>
<line>integer esize;</line>
<line>integer elements;</line>
<line>case sz of</line>
<line>    when '0' esize = 32; elements = 2;</line>
<line>    when '1' esize = 16; elements = 4;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>sz == '1' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VSUB" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSUB_f/T2_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o0" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="o1" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSUB_f_T2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSUB" />
          <docvar key="mnemonic-fpdatasize" value="VSUB-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VSUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><text>{</text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSUB_f_T2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSUB" />
          <docvar key="mnemonic-fpdatasize" value="VSUB-singleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>VSUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F32 </text><text>{</text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSUB_f_T2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSUB" />
          <docvar key="mnemonic-fpdatasize" value="VSUB-doubleprec" />
        </docvars>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VSUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F64 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSUB_f/T2_A.txt" mylink="aarch32.instrs.VSUB_f.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;</line>
<line>if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;</line>
<line>if size == '01' &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()  then UNPREDICTABLE;</line>
<line>advsimd = FALSE;</line>
<line>integer esize;</line>
<line>integer d;</line>
<line>integer n;</line>
<line>integer m;</line>
<line>case size of</line>
<line>    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</line>
<line>    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>size == '01' &amp;&amp; InITBlock()</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSUB_f_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUB_f_A2_H, VSUB_f_T1_Q, VSUB_f_T2_H" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For encoding A2, T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUB_f_A1_Q, VSUB_f_A2_H, VSUB_f_T1_Q, VSUB_f_T2_H" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUB_f_A1_Q, VSUB_f_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="sz">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F16</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
      <arch_variants>
        <arch_variant name="ARMv8.2-A" />
      </arch_variants>
    </explanation>
    <explanation enclist="VSUB_f_A1_Q, VSUB_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUB_f_A1_Q, VSUB_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUB_f_A1_Q, VSUB_f_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUB_f_A1_D, VSUB_f_A2_D, VSUB_f_T1_D, VSUB_f_T2_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUB_f_A1_D, VSUB_f_A2_D, VSUB_f_T1_D, VSUB_f_T2_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUB_f_A1_D, VSUB_f_A2_D, VSUB_f_T1_D, VSUB_f_T2_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUB_f_A2_H, VSUB_f_T2_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUB_f_A2_H, VSUB_f_T2_H" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUB_f_A2_H, VSUB_f_T2_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VSUB_f/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDOrVFPEnabled.2" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDOrVFPEnabled(boolean include_fpexc_check, boolean advsimd)">CheckAdvSIMDOrVFPEnabled</a>(TRUE, advsimd);</line>
<line>    if advsimd then  // Advanced SIMD instruction</line>
<line>        for r = 0 to regs-1</line>
<line>            for e = 0 to elements-1</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPSub.3" file="shared_pseudocode.xml" hover="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPSub</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize], <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize],</line>
<line>                                             <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());</line>
<line>    else             // VFP instruction</line>
<line>        case esize of</line>
<line>            when 16</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPSub.3" file="shared_pseudocode.xml" hover="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPSub</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;15:0&gt;, FPSCR[]);</line>
<line>            when 32</line>
<line>                <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPSub.3" file="shared_pseudocode.xml" hover="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPSub</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n], <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[]);</line>
<line>            when 64</line>
<line>                <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPSub.3" file="shared_pseudocode.xml" hover="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPSub</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n], <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[]);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vsub_i.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSUB_i" title="VSUB (integer) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VSUB" />
  </docvars>
  <heading>VSUB (integer)</heading>
  <desc>
    <brief>
      <para>Vector Subtract (integer)</para>
    </brief>
    <authored>
      <para>Vector Subtract (integer) subtracts the elements of one vector from the corresponding elements of another vector, and places the results in the destination vector.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VSUB" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSUB_i/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSUB_i_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSUB" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSUB</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;) [I8,I16,I32,I64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSUB_i_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSUB" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSUB</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;) [I8,I16,I32,I64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSUB_i/T1A1_A.txt" mylink="aarch32.instrs.VSUB_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VSUB" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSUB_i/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSUB_i_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSUB" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;) [I8,I16,I32,I64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSUB_i_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSUB" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;) [I8,I16,I32,I64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSUB_i/T1A1_A.txt" mylink="aarch32.instrs.VSUB_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSUB_i_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUB_i_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUB_i_A1_Q, VSUB_i_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUB_i_A1_Q, VSUB_i_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">I8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">I16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">I32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">I64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VSUB_i_A1_Q, VSUB_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUB_i_A1_Q, VSUB_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUB_i_A1_Q, VSUB_i_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUB_i_A1_D, VSUB_i_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUB_i_A1_D, VSUB_i_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUB_i_A1_D, VSUB_i_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VSUB_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize] - <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize];</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vsubhn.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSUBHN" title="VSUBHN -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VSUBHN" />
  </docvars>
  <heading>VSUBHN</heading>
  <desc>
    <brief>
      <para>Vector Subtract and Narrow, returning High Half</para>
    </brief>
    <authored>
      <para>Vector Subtract and Narrow, returning High Half subtracts the elements of one quadword vector from the corresponding elements of another quadword vector, takes the most significant half of each result, and places the final results in a doubleword vector. The results are truncated. For rounded results, see <xref linkend="A32T32-fpsimd.instructions.VRSUBHN">VRSUBHN</xref>.</para>
      <para>There is no distinction between signed and unsigned integers.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VSUBHN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSUBHN/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSUBHN_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSUBHN" />
        </docvars>
        <asmtemplate><text>VSUBHN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSUBHN/T1A1_A.txt" mylink="aarch32.instrs.VSUBHN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VSUBHN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSUBHN/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSUBHN_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSUBHN" />
        </docvars>
        <asmtemplate><text>VSUBHN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSUBHN/T1A1_A.txt" mylink="aarch32.instrs.VSUBHN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSUBHN_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUBHN_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUBHN_A1, VSUBHN_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUBHN_A1, VSUBHN_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">I16</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">I32</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">I64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VSUBHN_A1, VSUBHN_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUBHN_A1, VSUBHN_T1" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUBHN_A1, VSUBHN_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VSUBHN/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for e = 0 to elements-1</line>
<line>        result = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[n&gt;&gt;1],e,2*esize] - <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[m&gt;&gt;1],e,2*esize];</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d],e,esize] = result&lt;2*esize-1:esize&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vsubl.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSUBL" title="VSUBL -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VSUBL" />
  </docvars>
  <heading>VSUBL</heading>
  <desc>
    <brief>
      <para>Vector Subtract Long</para>
    </brief>
    <authored>
      <para>Vector Subtract Long subtracts the elements of one doubleword vector from the corresponding elements of another doubleword vector, and places the results in a quadword vector. Before subtracting, it sign-extends or zero-extends the elements of both operands.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VSUBL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSUBL/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="8" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSUBL_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSUBL" />
        </docvars>
        <asmtemplate><text>VSUBL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of second operand vector (field &quot;U:size&quot;) [S8,S16,S32,U8,U16,U32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSUBL/T1A1_A.txt" mylink="aarch32.instrs.VSUBL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vd&lt;0&gt; == '1' || (op == '1' &amp;&amp; Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;  is_vsubw = (op == '1');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VSUBL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSUBL/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="8" name="op" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSUBL_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSUBL" />
        </docvars>
        <asmtemplate><text>VSUBL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of second operand vector (field &quot;U:size&quot;) [S8,S16,S32,U8,U16,U32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSUBL/T1A1_A.txt" mylink="aarch32.instrs.VSUBL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vd&lt;0&gt; == '1' || (op == '1' &amp;&amp; Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;  is_vsubw = (op == '1');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSUBL_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUBL_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUBL_A1, VSUBL_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUBL_A1, VSUBL_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the second operand vector, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VSUBL_A1, VSUBL_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUBL_A1, VSUBL_T1" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUBL_A1, VSUBL_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VSUBL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for e = 0 to elements-1</line>
<line>        integer op1;</line>
<line>        if is_vsubw then</line>
<line>            op1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[n&gt;&gt;1],e,2*esize], unsigned);</line>
<line>        else</line>
<line>            op1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n],e,esize], unsigned);</line>
<line>        result = op1 - <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m],e,esize], unsigned);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = result&lt;2*esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vsubw.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSUBW" title="VSUBW -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VSUBW" />
  </docvars>
  <heading>VSUBW</heading>
  <desc>
    <brief>
      <para>Vector Subtract Wide</para>
    </brief>
    <authored>
      <para>Vector Subtract Wide subtracts the elements of a doubleword vector from the corresponding elements of a quadword vector, and places the results in another quadword vector. Before subtracting, it sign-extends or zero-extends the elements of the doubleword operand.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VSUBW" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSUBL/T1A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="8" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSUBW_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSUBW" />
        </docvars>
        <asmtemplate><text>VSUBW</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of second operand vector (field &quot;U:size&quot;) [S8,S16,S32,U8,U16,U32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSUBL/T1A1_A.txt" mylink="aarch32.instrs.VSUBL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vd&lt;0&gt; == '1' || (op == '1' &amp;&amp; Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;  is_vsubw = (op == '1');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VSUBW" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSUBL/T1A1_A.txt" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
          <c colspan="2">!= 11</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="8" name="op" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSUBW_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSUBW" />
        </docvars>
        <asmtemplate><text>VSUBW</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of second operand vector (field &quot;U:size&quot;) [S8,S16,S32,U8,U16,U32]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSUBL/T1A1_A.txt" mylink="aarch32.instrs.VSUBL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then SEE "Related encodings";</line>
<line>if Vd&lt;0&gt; == '1' || (op == '1' &amp;&amp; Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>unsigned = (U == '1');</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;  is_vsubw = (op == '1');</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSUBW_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUBW_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUBW_A1, VSUBW_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUBW_A1, VSUBW_T1" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="U:size">
        <intro>Is the data type for the elements of the second operand vector, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">S8</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">S16</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">S32</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">00</entry>
                <entry class="symbol">U8</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">01</entry>
                <entry class="symbol">U16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">10</entry>
                <entry class="symbol">U32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VSUBW_A1, VSUBW_T1" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUBW_A1, VSUBW_T1" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUBW_A1, VSUBW_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VSUBL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for e = 0 to elements-1</line>
<line>        integer op1;</line>
<line>        if is_vsubw then</line>
<line>            op1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[n&gt;&gt;1],e,2*esize], unsigned);</line>
<line>        else</line>
<line>            op1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n],e,esize], unsigned);</line>
<line>        result = op1 - <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m],e,esize], unsigned);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,2*esize] = result&lt;2*esize-1:0&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vsudot_s.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSUDOT_s" title="VSUDOT (by element) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VSUDOT" />
  </docvars>
  <heading>VSUDOT (by element)</heading>
  <desc>
    <brief>
      <para>Dot Product index form with signed and unsigned integers (by element)</para>
    </brief>
    <authored>
      <para>Dot Product index form with signed and unsigned integers. This instruction performs the dot product of the four signed 8-bit integer values in each 32-bit element of the first source register with the four unsigned 8-bit integer values in an indexed 32-bit element of the second source register, accumulating the result into the corresponding 32-bit element of the destination register.</para>
      <para>From Armv8.2, this is an <arm-defined-word>optional</arm-defined-word> instruction. <xref linkend="AArch32.id_isar6">ID_ISAR6</xref>.I8MM indicates whether this instruction is supported in the T32 and A32 instruction sets.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VSUDOT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_AA32I8MM" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/DOT/A1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="op1" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSUDOT_s_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSUDOT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSUDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U8 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VSUDOT_s_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSUDOT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSUDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U8 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/DOT/A1_A.txt" mylink="aarch32.instrs.DOT.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveAArch32Int8MatMulExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32Int8MatMulExt()">HaveAArch32Int8MatMulExt</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>boolean op1_unsigned = (U == '0');</line>
<line>boolean op2_unsigned = (U == '1');</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);</line>
<line>integer i = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
<line>integer regs = if Q == '1' then 2 else 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VSUDOT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_AA32I8MM" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/DOT/T1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="op1" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSUDOT_s_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSUDOT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSUDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U8 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VSUDOT_s_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSUDOT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSUDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U8 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/DOT/T1_A.txt" mylink="aarch32.instrs.DOT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveAArch32Int8MatMulExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32Int8MatMulExt()">HaveAArch32Int8MatMulExt</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>boolean op1_unsigned = (U == '0');</line>
<line>boolean op2_unsigned = (U == '1');</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);</line>
<line>integer i = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
<line>integer regs = if Q == '1' then 2 else 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSUDOT_s_A1_D, VSUDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUDOT_s_A1_Q, VSUDOT_s_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUDOT_s_A1_Q, VSUDOT_s_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUDOT_s_A1_D, VSUDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUDOT_s_A1_D, VSUDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUDOT_s_A1_D, VSUDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSUDOT_s_A1_D, VSUDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_index">&lt;index&gt;</symbol>
      <account encodedin="M">
        <intro>
          <para>Is the element index in the range 0 to 1, encoded in the "M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/DOT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>bits(64) operand1;</line>
<line>bits(64) operand2;</line>
<line>bits(64) result;</line>
<line></line>
<line>operand2 = <a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m];</line>
<line>for r = 0 to regs-1</line>
<line>    operand1 = <a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r];</line>
<line>    result = <a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r];</line>
<line>    for e = 0 to 1</line>
<line>        bits(32) res = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 32];</line>
<line>        for b = 0 to 3</line>
<line>            element1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 4 * e + b, 8], op1_unsigned);</line>
<line>            element2 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 4 * i + b, 8], op2_unsigned);</line>
<line>            res = res + element1 * element2;</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = res;</line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vswp.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VSWP" title="VSWP -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VSWP" />
  </docvars>
  <heading>VSWP</heading>
  <desc>
    <brief>
      <para>Vector Swap</para>
    </brief>
    <authored>
      <para>Vector Swap exchanges the contents of two vectors. The vectors can be either doubleword or quadword. There is no distinction between data types.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VSWP" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSWP/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSWP_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSWP" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSWP</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSWP_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSWP" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSWP</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSWP/T1A1_A.txt" mylink="aarch32.instrs.VSWP.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size != '00' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VSWP" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSWP/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSWP_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSWP" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VSWP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSWP_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSWP" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VSWP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="An optional data type">&lt;dt&gt;</a><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSWP/T1A1_A.txt" mylink="aarch32.instrs.VSWP.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size != '00' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSWP_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSWP_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSWP_A1_Q, VSWP_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSWP_A1_Q, VSWP_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>An optional data type. It is ignored by assemblers, and does not affect the encoding.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSWP_A1_Q, VSWP_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSWP_A1_Q, VSWP_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSWP_A1_D, VSWP_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSWP_A1_D, VSWP_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VSWP/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        if d == m then</line>
<line>            <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = bits(64) UNKNOWN;</line>
<line>        else</line>
<line>            <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = <a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m+r];</line>
<line>            <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[m+r] = <a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r];</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vtbl.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VTBL" title="VTBL, VTBX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
  </docvars>
  <heading>VTBL, VTBX</heading>
  <desc>
    <brief>
      <para>Vector Table Lookup and Extension</para>
    </brief>
    <authored>
      <para>Vector Table Lookup uses byte indexes in a control vector to look up byte values in a table and generate a new vector. Indexes out of range return 0.</para>
      <para>Vector Table Extension works in the same way, except that indexes out of range leave the destination element unchanged.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VTBL/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="len" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VTBL_A1" oneofinclass="2" oneof="4" label="VTBL" bitdiffs="op == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VTBL" />
        </docvars>
        <box hibit="6" width="1" name="op">
          <c>0</c>
        </box>
        <asmtemplate><text>VTBL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.8 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_list" hover="The vectors containing the table">&lt;list&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register holding indices (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VTBX_A1" oneofinclass="2" oneof="4" label="VTBX" bitdiffs="op == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VTBX" />
        </docvars>
        <box hibit="6" width="1" name="op">
          <c>1</c>
        </box>
        <asmtemplate><text>VTBX</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.8 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_list" hover="The vectors containing the table">&lt;list&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register holding indices (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VTBL/T1A1_A.txt" mylink="aarch32.instrs.VTBL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>is_vtbl = (op == '0');  length = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(len)+1;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>if n+length &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n + length &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VTBL/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="len" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VTBL_T1" oneofinclass="2" oneof="4" label="VTBL" bitdiffs="op == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VTBL" />
        </docvars>
        <box hibit="6" width="1" name="op">
          <c>0</c>
        </box>
        <asmtemplate><text>VTBL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.8 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_list" hover="The vectors containing the table">&lt;list&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register holding indices (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VTBX_T1" oneofinclass="2" oneof="4" label="VTBX" bitdiffs="op == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VTBX" />
        </docvars>
        <box hibit="6" width="1" name="op">
          <c>1</c>
        </box>
        <asmtemplate><text>VTBX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.8 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_list" hover="The vectors containing the table">&lt;list&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register holding indices (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VTBL/T1A1_A.txt" mylink="aarch32.instrs.VTBL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>is_vtbl = (op == '0');  length = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(len)+1;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>if n+length &gt; 32 then UNPREDICTABLE;</line>
</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1"><line>n + length &gt; 32</line>
</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VTBL_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VTBL_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VTBL_A1, VTBL_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VTBL_A1, VTBL_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VTBL_A1, VTBL_T1" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>The vectors containing the table. It must be one of:</para>
          <list type="param">
            <listitem>
              <param>{&lt;Dn&gt;}</param><content>Encoded as len = <binarynumber>0b00</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>{&lt;Dn&gt;, &lt;Dn+1&gt;}</param><content>Encoded as len = <binarynumber>0b01</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>{&lt;Dn&gt;, &lt;Dn+1&gt;, &lt;Dn+2&gt;}</param><content>Encoded as len = <binarynumber>0b10</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>{&lt;Dn&gt;, &lt;Dn+1&gt;, &lt;Dn+2&gt;, &lt;Dn+3&gt;}</param><content>Encoded as len = <binarynumber>0b11</binarynumber>.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VTBL_A1, VTBL_T1" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register holding the indices, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VTBL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line></line>
<line>    // Create 256-bit = 32-byte table variable, with zeros in entries that will not be used.</line>
<line>    table3 = if length == 4 then <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+3] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>    table2 = if length &gt;= 3 then <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+2] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>    table1 = if length &gt;= 2 then <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+1] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>    table = table3 : table2 : table1 : <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n];</line>
<line></line>
<line>    for i = 0 to 7</line>
<line>        index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m],i,8]);</line>
<line>        if index &lt; 8*length then</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d],i,8] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table,index,8];</line>
<line>        else</line>
<line>            if is_vtbl then</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d],i,8] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8);</line>
<line>            // else Elem[D[d],i,8] unchanged</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vtrn.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VTRN" title="VTRN -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VTRN" />
  </docvars>
  <heading>VTRN</heading>
  <desc>
    <brief>
      <para>Vector Transpose</para>
    </brief>
    <authored>
      <para>Vector Transpose treats the elements of its operand vectors as elements of 2 x 2 matrices, and transposes the matrices.</para>
      <para>The elements of the vectors can be 8-bit, 16-bit, or 32-bit. There is no distinction between data types.</para>
      <para><image file="vtrn_doubleword_operation.svg" label="VTRN doubleword operations"></image></para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="2">
    <alias_list_intro>This instruction is used by the aliases </alias_list_intro>
    <aliasref aliaspageid="VUZP_VTRN" aliasfile="vuzp_vtrn.xml" hover="Vector Unzip" punct=" and ">
      <text>VUZP (alias)</text>
      <aliaspref>Never</aliaspref>
    </aliasref>
    <aliasref aliaspageid="VZIP_VTRN" aliasfile="vzip_vtrn.xml" hover="Vector Zip" punct=".">
      <text>VZIP (alias)</text>
      <aliaspref>Never</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink />
      <text> below for details of when each alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VTRN" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VTRN/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VTRN_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VTRN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VTRN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VTRN_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VTRN" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VTRN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VTRN/T1A1_A.txt" mylink="aarch32.instrs.VTRN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VTRN" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VTRN/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VTRN_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VTRN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VTRN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VTRN_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VTRN" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VTRN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VTRN/T1A1_A.txt" mylink="aarch32.instrs.VTRN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VTRN_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VTRN_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VTRN_A1_Q, VTRN_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VTRN_A1_Q, VTRN_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VTRN_A1_Q, VTRN_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VTRN_A1_Q, VTRN_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VTRN_A1_D, VTRN_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VTRN_A1_D, VTRN_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VTRN/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    h = elements DIV 2;</line>
<line></line>
<line>    for r = 0 to regs-1</line>
<line>        if d == m then</line>
<line>            <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = bits(64) UNKNOWN;</line>
<line>        else</line>
<line>            for e = 0 to h-1</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],2*e+1,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m+r],2*e,esize];</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[m+r],2*e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r],2*e+1,esize];</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vtst.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VTST" title="VTST -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VTST" />
  </docvars>
  <heading>VTST</heading>
  <desc>
    <brief>
      <para>Vector Test Bits</para>
    </brief>
    <authored>
      <para>Vector Test Bits takes each element in a vector, and bitwise ANDs it with the corresponding element of a second vector. If the result is not zero, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.</para>
      <para>The operand vector elements can be any one of:</para>
      <list type="unordered">
        <listitem><content>8-bit, 16-bit, or 32-bit fields.</content></listitem>
      </list>
      <para>The result vector elements are fields the same size as the operand vector elements.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VTST" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VTST/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VTST_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VTST" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VTST</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VTST_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VTST" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VTST</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VTST/T1A1_A.txt" mylink="aarch32.instrs.VTST.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VTST" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VTST/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="opc" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VTST_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VTST" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VTST</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VTST_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VTST" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VTST</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VTST/T1A1_A.txt" mylink="aarch32.instrs.VTST.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>if size == '11' then UNDEFINED;</line>
<line>esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 64 DIV esize;</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);  regs = if Q == '0' then 1 else 2;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VTST_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VTST_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VTST_A1_Q, VTST_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VTST_A1_Q, VTST_T1_Q" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data type for the elements of the operands, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VTST_A1_Q, VTST_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VTST_A1_Q, VTST_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VTST_A1_Q, VTST_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VTST_A1_D, VTST_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VTST_A1_D, VTST_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VTST_A1_D, VTST_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VTST/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    for r = 0 to regs-1</line>
<line>        for e = 0 to elements-1</line>
<line>            if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize] AND <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize]) then</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(esize);</line>
<line>            else</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(esize);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vudot.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VUDOT" title="VUDOT (vector) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VUDOT" />
  </docvars>
  <heading>VUDOT (vector)</heading>
  <desc>
    <brief>
      <para>Dot Product vector form with unsigned integers.</para>
    </brief>
    <authored>
      <para>Dot Product vector form with unsigned integers. This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of the corresponding 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.</para>
      <para>In Armv8.2 and Armv8.3, this is an <arm-defined-word>optional</arm-defined-word> instruction. From Armv8.4 it is mandatory for all implementations to support it.</para>
      <note>
        <para><xref linkend="AArch32.id_isar6">ID_ISAR6</xref>.DP indicates whether this instruction is supported.</para>
      </note>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VUDOT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_DotProd" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VDOT/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="op1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VUDOT_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VUDOT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VUDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U8 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VUDOT_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VUDOT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VUDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U8 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VDOT/A1_A.txt" mylink="aarch32.instrs.VDOT.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveDOTPExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDOTPExt()">HaveDOTPExt</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>boolean signed = U=='0';</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>integer esize = 32;</line>
<line>integer regs = if Q == '1' then 2 else 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VUDOT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_DotProd" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VDOT/T1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="op1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VUDOT_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VUDOT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VUDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U8 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VUDOT_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VUDOT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VUDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U8 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VDOT/T1_A.txt" mylink="aarch32.instrs.VDOT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveDOTPExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDOTPExt()">HaveDOTPExt</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>boolean signed = U=='0';</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>integer esize = 32;</line>
<line>integer regs = if Q == '1' then 2 else 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VUDOT_A1_D, VUDOT_T1_D" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUDOT_A1_Q, VUDOT_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUDOT_A1_Q, VUDOT_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUDOT_A1_Q, VUDOT_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUDOT_A1_D, VUDOT_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUDOT_A1_D, VUDOT_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUDOT_A1_D, VUDOT_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VDOT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>bits(64) operand1;</line>
<line>bits(64) operand2;</line>
<line>bits(64) result;</line>
<line><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>for r = 0 to regs-1</line>
<line>    operand1 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r];</line>
<line>    operand2 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r];</line>
<line>    result = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r];</line>
<line>    integer element1, element2;</line>
<line>    for e = 0 to 1</line>
<line>        integer res = 0;</line>
<line>        for i = 0 to 3</line>
<line>            if signed then</line>
<line>                element1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 4 * e + i, esize DIV 4]);</line>
<line>                element2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 4 * e + i, esize DIV 4]);</line>
<line>            else</line>
<line>                element1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 4 * e + i, esize DIV 4]);</line>
<line>                element2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 4 * e + i, esize DIV 4]);</line>
<line>            res = res + element1 * element2;</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + res;</line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vudot_s.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VUDOT_s" title="VUDOT (by element) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VUDOT" />
  </docvars>
  <heading>VUDOT (by element)</heading>
  <desc>
    <brief>
      <para>Dot Product index form with unsigned integers.</para>
    </brief>
    <authored>
      <para>Dot Product index form with unsigned integers. This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.</para>
      <para>In Armv8.2 and Armv8.3, this is an <arm-defined-word>optional</arm-defined-word> instruction. From Armv8.4 it is mandatory for all implementations to support it.</para>
      <note>
        <para><xref linkend="AArch32.id_isar6">ID_ISAR6</xref>.DP indicates whether this instruction is supported.</para>
      </note>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VUDOT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_DotProd" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VDOT_s/A1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="op1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VUDOT_s_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VUDOT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VUDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U8 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VUDOT_s_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VUDOT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VUDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U8 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VDOT_s/A1_A.txt" mylink="aarch32.instrs.VDOT_s.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveDOTPExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDOTPExt()">HaveDOTPExt</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>boolean signed = (U=='0');</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;3:0&gt;);</line>
<line>integer index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
<line>integer esize = 32;</line>
<line>integer regs = if Q == '1' then 2 else 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VUDOT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_DotProd" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VDOT_s/T1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="op1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VUDOT_s_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VUDOT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VUDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U8 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VUDOT_s_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VUDOT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VUDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U8 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VDOT_s/T1_A.txt" mylink="aarch32.instrs.VDOT_s.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveDOTPExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDOTPExt()">HaveDOTPExt</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>boolean signed = (U=='0');</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;3:0&gt;);</line>
<line>integer index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
<line>integer esize = 32;</line>
<line>integer regs = if Q == '1' then 2 else 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VUDOT_s_A1_D, VUDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUDOT_s_A1_Q, VUDOT_s_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUDOT_s_A1_Q, VUDOT_s_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUDOT_s_A1_D, VUDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUDOT_s_A1_D, VUDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUDOT_s_A1_D, VUDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUDOT_s_A1_D, VUDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_index">&lt;index&gt;</symbol>
      <account encodedin="M">
        <intro>
          <para>Is the element index in the range 0 to 1, encoded in the "M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VDOT_s/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>bits(64) operand1;</line>
<line>bits(64) operand2 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m];</line>
<line>bits(64) result;</line>
<line><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>for r = 0 to regs-1</line>
<line>    operand1 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r];</line>
<line>    result = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r];</line>
<line>    integer element1, element2;</line>
<line>    for e = 0 to 1</line>
<line>        integer res = 0;</line>
<line>        for i = 0 to 3</line>
<line>            if signed then</line>
<line>                element1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 4 * e + i, esize DIV 4]);</line>
<line>                element2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 4 * index + i, esize DIV 4]);</line>
<line>            else</line>
<line>                element1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 4 * e + i, esize DIV 4]);</line>
<line>                element2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 4 * index + i, esize DIV 4]);</line>
<line>            res = res + element1 * element2;</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, esize] + res;</line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vummla.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VUMMLA" title="VUMMLA -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VUMMLA" />
    <docvar key="simdvectorsize" value="quad" />
  </docvars>
  <heading>VUMMLA</heading>
  <desc>
    <brief>
      <para>Widening 8-bit unsigned integer matrix multiply-accumulate into 2x2 matrix</para>
    </brief>
    <authored>
      <para>The widening integer matrix multiply-accumulate instruction multiplies the 2x8 matrix of unsigned 8-bit integer values held in the first source vector by the 8x2 matrix of unsigned 8-bit integer values in the second source vector. The resulting 2x2 32-bit integer matrix product is destructively added to the 32-bit integer matrix accumulator held in the destination vector. This is equivalent to performing an 8-way dot product per destination element.</para>
      <para>From Armv8.2, this is an <arm-defined-word>optional</arm-defined-word> instruction. <xref linkend="AArch32.id_isar6">ID_ISAR6</xref>.I8MM indicates whether this instruction is supported in the T32 and A32 instruction sets.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VUMMLA" />
        <docvar key="simdvectorsize" value="quad" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_AA32I8MM" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/MMLA/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="B" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VUMMLA_A1_Q" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VUMMLA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <asmtemplate><text>VUMMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U8 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP third source and destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MMLA/A1_A.txt" mylink="aarch32.instrs.MMLA.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveAArch32Int8MatMulExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32Int8MatMulExt()">HaveAArch32Int8MatMulExt</a>() then UNDEFINED;</line>
<line>boolean op1_unsigned;</line>
<line>boolean op2_unsigned;</line>
<line>case B:U of</line>
<line>    when '00' op1_unsigned = FALSE; op2_unsigned = FALSE;</line>
<line>    when '01' op1_unsigned = TRUE;  op2_unsigned = TRUE;</line>
<line>    when '10' op1_unsigned = TRUE;  op2_unsigned = FALSE;</line>
<line>    when '11' UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VUMMLA" />
        <docvar key="simdvectorsize" value="quad" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_AA32I8MM" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/MMLA/T1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="B" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VUMMLA_T1_Q" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VUMMLA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <asmtemplate><text>VUMMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.U8 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP third source and destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MMLA/T1_A.txt" mylink="aarch32.instrs.MMLA.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveAArch32Int8MatMulExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32Int8MatMulExt()">HaveAArch32Int8MatMulExt</a>() then UNDEFINED;</line>
<line>boolean op1_unsigned;</line>
<line>boolean op2_unsigned;</line>
<line>case B:U of</line>
<line>    when '00' op1_unsigned = FALSE; op2_unsigned = FALSE;</line>
<line>    when '01' op1_unsigned = TRUE;  op2_unsigned = TRUE;</line>
<line>    when '10' op1_unsigned = TRUE;  op2_unsigned = FALSE;</line>
<line>    when '11' UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VUMMLA_A1_Q, VUMMLA_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUMMLA_A1_Q, VUMMLA_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP third source and destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUMMLA_A1_Q, VUMMLA_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUMMLA_A1_Q, VUMMLA_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MMLA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>bits(128) operand1 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[n&gt;&gt;1];</line>
<line>bits(128) operand2 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1];</line>
<line>bits(128) addend   = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[d&gt;&gt;1];</line>
<line></line>
<line><a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = <a link="impl-shared.MatMulAdd.5" file="shared_pseudocode.xml" hover="function: bits(N) MatMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, boolean op1_unsigned, boolean op2_unsigned)">MatMulAdd</a>(addend, operand1, operand2, op1_unsigned, op2_unsigned);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vusdot.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VUSDOT" title="VUSDOT (vector) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VUSDOT" />
  </docvars>
  <heading>VUSDOT (vector)</heading>
  <desc>
    <brief>
      <para>Dot Product vector form with mixed-sign integers</para>
    </brief>
    <authored>
      <para>Dot Product vector form with mixed-sign integers. This instruction performs the dot product of the four unsigned 8-bit integer values in each 32-bit element of the first source register with the four signed 8-bit integer values in the corresponding 32-bit element of the second source register, accumulating the result into the corresponding 32-bit element of the destination register.</para>
      <para>From Armv8.2, this is an <arm-defined-word>optional</arm-defined-word> instruction. <xref linkend="AArch32.id_isar6">ID_ISAR6</xref>.I8MM indicates whether this instruction is supported in the T32 and A32 instruction sets.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VUSDOT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_AA32I8MM" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VUSDOT/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="op1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VUSDOT_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VUSDOT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VUSDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S8 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP third source and destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VUSDOT_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VUSDOT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VUSDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S8 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP third source and destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VUSDOT/A1_A.txt" mylink="aarch32.instrs.VUSDOT.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveAArch32Int8MatMulExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32Int8MatMulExt()">HaveAArch32Int8MatMulExt</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>integer regs = if Q == '1' then 2 else 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VUSDOT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_AA32I8MM" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VUSDOT/T1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="op1" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VUSDOT_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VUSDOT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VUSDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S8 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP third source and destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VUSDOT_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VUSDOT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VUSDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S8 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP third source and destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VUSDOT/T1_A.txt" mylink="aarch32.instrs.VUSDOT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveAArch32Int8MatMulExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32Int8MatMulExt()">HaveAArch32Int8MatMulExt</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
<line>integer regs = if Q == '1' then 2 else 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VUSDOT_A1_D, VUSDOT_T1_D" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUSDOT_A1_Q, VUSDOT_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP third source and destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUSDOT_A1_Q, VUSDOT_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUSDOT_A1_Q, VUSDOT_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUSDOT_A1_D, VUSDOT_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP third source and destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUSDOT_A1_D, VUSDOT_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUSDOT_A1_D, VUSDOT_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VUSDOT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>bits(64) operand1;</line>
<line>bits(64) operand2;</line>
<line>bits(64) result;</line>
<line></line>
<line>for r = 0 to regs-1</line>
<line>    operand1 = <a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r];</line>
<line>    operand2 = <a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m+r];</line>
<line>    result = <a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r];</line>
<line>    for e = 0 to 1</line>
<line>        bits(32) res = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 32];</line>
<line>        for b = 0 to 3</line>
<line>            element1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 4 * e + b, 8]);</line>
<line>            element2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 4 * e + b, 8]);</line>
<line>            res = res + element1 * element2;</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = res;</line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vusdot_s.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VUSDOT_s" title="VUSDOT (by element) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VUSDOT" />
  </docvars>
  <heading>VUSDOT (by element)</heading>
  <desc>
    <brief>
      <para>Dot Product index form with unsigned and signed integers (by element)</para>
    </brief>
    <authored>
      <para>Dot Product index form with unsigned and signed integers. This instruction performs the dot product of the four unsigned 8-bit integer values in each 32-bit element of the first source register with the four signed 8-bit integer values in an indexed 32-bit element of the second source register, accumulating the result into the corresponding 32-bit element of the destination register.</para>
      <para>From Armv8.2, this is an <arm-defined-word>optional</arm-defined-word> instruction. <xref linkend="AArch32.id_isar6">ID_ISAR6</xref>.I8MM indicates whether this instruction is supported in the T32 and A32 instruction sets.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VUSDOT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_AA32I8MM" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/DOT/A1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="op1" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VUSDOT_s_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VUSDOT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VUSDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S8 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VUSDOT_s_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VUSDOT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VUSDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S8 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/DOT/A1_A.txt" mylink="aarch32.instrs.DOT.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveAArch32Int8MatMulExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32Int8MatMulExt()">HaveAArch32Int8MatMulExt</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>boolean op1_unsigned = (U == '0');</line>
<line>boolean op2_unsigned = (U == '1');</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);</line>
<line>integer i = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
<line>integer regs = if Q == '1' then 2 else 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VUSDOT" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_AA32I8MM" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/DOT/T1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="op1" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VUSDOT_s_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VUSDOT" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VUSDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S8 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VUSDOT_s_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VUSDOT" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VUSDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S8 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-1] (field &quot;M&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/DOT/T1_A.txt" mylink="aarch32.instrs.DOT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveAArch32Int8MatMulExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32Int8MatMulExt()">HaveAArch32Int8MatMulExt</a>() then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;</line>
<line>boolean op1_unsigned = (U == '0');</line>
<line>boolean op2_unsigned = (U == '1');</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm);</line>
<line>integer i = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</line>
<line>integer regs = if Q == '1' then 2 else 1;</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VUSDOT_s_A1_D, VUSDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUSDOT_s_A1_Q, VUSDOT_s_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUSDOT_s_A1_Q, VUSDOT_s_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUSDOT_s_A1_D, VUSDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUSDOT_s_A1_D, VUSDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUSDOT_s_A1_D, VUSDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUSDOT_s_A1_D, VUSDOT_s_T1_D" symboldefcount="1">
      <symbol link="sa_index">&lt;index&gt;</symbol>
      <account encodedin="M">
        <intro>
          <para>Is the element index in the range 0 to 1, encoded in the "M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/DOT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>bits(64) operand1;</line>
<line>bits(64) operand2;</line>
<line>bits(64) result;</line>
<line></line>
<line>operand2 = <a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m];</line>
<line>for r = 0 to regs-1</line>
<line>    operand1 = <a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r];</line>
<line>    result = <a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r];</line>
<line>    for e = 0 to 1</line>
<line>        bits(32) res = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 32];</line>
<line>        for b = 0 to 3</line>
<line>            element1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 4 * e + b, 8], op1_unsigned);</line>
<line>            element2 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 4 * i + b, 8], op2_unsigned);</line>
<line>            res = res + element1 * element2;</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = res;</line>
<line>    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = result;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vusmmla.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VUSMMLA" title="VUSMMLA -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VUSMMLA" />
    <docvar key="simdvectorsize" value="quad" />
  </docvars>
  <heading>VUSMMLA</heading>
  <desc>
    <brief>
      <para>Widening 8-bit mixed integer matrix multiply-accumulate into 2x2 matrix</para>
    </brief>
    <authored>
      <para>The widening integer matrix multiply-accumulate instruction multiplies the 2x8 matrix of unsigned 8-bit integer values held in the first source vector by the 8x2 matrix of signed 8-bit integer values in the second source vector. The resulting 2x2 32-bit integer matrix product is destructively added to the 32-bit integer matrix accumulator held in the destination vector. This is equivalent to performing an 8-way dot product per destination element.</para>
      <para>From Armv8.2, this is an <arm-defined-word>optional</arm-defined-word> instruction. <xref linkend="AArch32.id_isar6">ID_ISAR6</xref>.I8MM indicates whether this instruction is supported in the T32 and A32 instruction sets.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VUSMMLA" />
        <docvar key="simdvectorsize" value="quad" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_AA32I8MM" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/MMLA/A1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="B" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VUSMMLA_A1_Q" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VUSMMLA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <asmtemplate><text>VUSMMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S8 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP third source and destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MMLA/A1_A.txt" mylink="aarch32.instrs.MMLA.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if !<a link="impl-shared.HaveAArch32Int8MatMulExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32Int8MatMulExt()">HaveAArch32Int8MatMulExt</a>() then UNDEFINED;</line>
<line>boolean op1_unsigned;</line>
<line>boolean op2_unsigned;</line>
<line>case B:U of</line>
<line>    when '00' op1_unsigned = FALSE; op2_unsigned = FALSE;</line>
<line>    when '01' op1_unsigned = TRUE;  op2_unsigned = TRUE;</line>
<line>    when '10' op1_unsigned = TRUE;  op2_unsigned = FALSE;</line>
<line>    when '11' UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VUSMMLA" />
        <docvar key="simdvectorsize" value="quad" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_AA32I8MM" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/MMLA/T1_A.txt" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="B" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VUSMMLA_T1_Q" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VUSMMLA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <asmtemplate><text>VUSMMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.S8 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP third source and destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MMLA/T1_A.txt" mylink="aarch32.instrs.MMLA.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</line>
<line>if !<a link="impl-shared.HaveAArch32Int8MatMulExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32Int8MatMulExt()">HaveAArch32Int8MatMulExt</a>() then UNDEFINED;</line>
<line>boolean op1_unsigned;</line>
<line>boolean op2_unsigned;</line>
<line>case B:U of</line>
<line>    when '00' op1_unsigned = FALSE; op2_unsigned = FALSE;</line>
<line>    when '01' op1_unsigned = TRUE;  op2_unsigned = TRUE;</line>
<line>    when '10' op1_unsigned = TRUE;  op2_unsigned = FALSE;</line>
<line>    when '11' UNDEFINED;</line>
<line>if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;</line>
<line>integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);</line>
<line>integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);</line>
<line>integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VUSMMLA_A1_Q, VUSMMLA_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUSMMLA_A1_Q, VUSMMLA_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP third source and destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUSMMLA_A1_Q, VUSMMLA_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUSMMLA_A1_Q, VUSMMLA_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MMLA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>bits(128) operand1 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[n&gt;&gt;1];</line>
<line>bits(128) operand2 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1];</line>
<line>bits(128) addend   = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[d&gt;&gt;1];</line>
<line></line>
<line><a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = <a link="impl-shared.MatMulAdd.5" file="shared_pseudocode.xml" hover="function: bits(N) MatMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, boolean op1_unsigned, boolean op2_unsigned)">MatMulAdd</a>(addend, operand1, operand2, op1_unsigned, op2_unsigned);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vuzp.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VUZP" title="VUZP -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VUZP" />
  </docvars>
  <heading>VUZP</heading>
  <desc>
    <brief>
      <para>Vector Unzip</para>
    </brief>
    <authored>
      <para>Vector Unzip de-interleaves the elements of two vectors.</para>
      <para>The elements of the vectors can be 8-bit, 16-bit, or 32-bit. There is no distinction between data types.</para>
      <para><image file="operation_doubleword_vuzp8.svg" label="VUZP doubleword operation for data type 8"></image></para>
      <para><image file="operation_quadword_vuzp32.svg" label="VUZP quadword operation for data type 32"></image></para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VUZP" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VUZP/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VUZP_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VUZP" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VUZP</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VUZP_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VUZP" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VUZP</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VUZP/T1A1_A.txt" mylink="aarch32.instrs.VUZP.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' || (Q == '0' &amp;&amp; size == '10') then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>quadword_operation = (Q == '1');  esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VUZP" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VUZP/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VUZP_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VUZP" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VUZP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VUZP_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VUZP" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VUZP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VUZP/T1A1_A.txt" mylink="aarch32.instrs.VUZP.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' || (Q == '0' &amp;&amp; size == '10') then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>quadword_operation = (Q == '1');  esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VUZP_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUZP_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUZP_A1_Q, VUZP_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUZP_A1_D, VUZP_T1_D" symboldefcount="1">
      <symbol link="sa_dt_1">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>For the 64-bit SIMD vector variant: is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">1x</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VUZP_A1_Q, VUZP_T1_Q" symboldefcount="2">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>For the 128-bit SIMD vector variant: is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VUZP_A1_Q, VUZP_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUZP_A1_Q, VUZP_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUZP_A1_D, VUZP_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUZP_A1_D, VUZP_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VUZP/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    if quadword_operation then</line>
<line>        if d == m then</line>
<line>            <a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = bits(128) UNKNOWN;</line>
<line>        else</line>
<line>            zipped_q = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1]:<a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[d&gt;&gt;1];</line>
<line>            for e = 0 to (128 DIV esize) - 1</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1],e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped_q,2*e,esize];</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[m&gt;&gt;1],e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped_q,2*e+1,esize];</line>
<line>    else</line>
<line>        if d == m then</line>
<line>            <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = bits(64) UNKNOWN;</line>
<line>        else</line>
<line>            zipped_d = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m]:<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d];</line>
<line>            for e = 0 to (64 DIV esize) - 1</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d],e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped_d,2*e,esize];</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[m],e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[zipped_d,2*e+1,esize];</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vuzp_vtrn.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VUZP_VTRN" title="VUZP (alias) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="VUZP" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VTRN" />
    <docvar key="simdvectorsize" value="double" />
  </docvars>
  <heading>VUZP (alias)</heading>
  <desc>
    <brief>Vector Unzip</brief>
    <longer> de-interleaves the elements of two vectors</longer>
  </desc>
  <aliasto refiform="vtrn.xml" iformid="VTRN">VTRN</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VTRN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VUZP_VTRN_A1_D" oneofinclass="1" oneof="2" label="64-bit SIMD vector">
        <docvars>
          <docvar key="alias_mnemonic" value="VUZP" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VTRN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <asmtemplate><text>VUZP</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vtrn.xml#VTRN_A1_D">VTRN</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VTRN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VUZP_VTRN_T1_D" oneofinclass="1" oneof="2" label="64-bit SIMD vector">
        <docvars>
          <docvar key="alias_mnemonic" value="VUZP" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VTRN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <asmtemplate><text>VUZP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vtrn.xml#VTRN_T1_D">VTRN</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VUZP_VTRN_A1_D" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUZP_VTRN_T1_D" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUZP_VTRN_A1_D, VUZP_VTRN_T1_D" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUZP_VTRN_A1_D, VUZP_VTRN_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VUZP_VTRN_A1_D, VUZP_VTRN_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="vzip.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VZIP" title="VZIP -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VZIP" />
  </docvars>
  <heading>VZIP</heading>
  <desc>
    <brief>
      <para>Vector Zip</para>
    </brief>
    <authored>
      <para>Vector Zip interleaves the elements of two vectors.</para>
      <para>The elements of the vectors can be 8-bit, 16-bit, or 32-bit. There is no distinction between data types.</para>
      <para><image file="operation_doubleword_vzip8.svg" label="VZIP doubleword operation for data type 8"></image></para>
      <para><image file="operation_quadword_vzip32.svg" label="VZIP quadword operation for data type 32"></image></para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VZIP" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VZIP/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VZIP_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VZIP" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VZIP</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VZIP_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VZIP" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VZIP</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VZIP/T1A1_A.txt" mylink="aarch32.instrs.VZIP.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' || (Q == '0' &amp;&amp; size == '10') then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>quadword_operation = (Q == '1');  esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VZIP" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VZIP/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VZIP_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VZIP" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VZIP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VZIP_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VZIP" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VZIP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;size&quot;)">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VZIP/T1A1_A.txt" mylink="aarch32.instrs.VZIP.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>if size == '11' || (Q == '0' &amp;&amp; size == '10') then UNDEFINED;</line>
<line>if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;</line>
<line>quadword_operation = (Q == '1');  esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);</line>
<line>d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VZIP_A1_Q" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VZIP_T1_Q" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VZIP_A1_Q, VZIP_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VZIP_A1_D, VZIP_T1_D" symboldefcount="1">
      <symbol link="sa_dt_1">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>For the 64-bit SIMD vector variant: is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">1x</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VZIP_A1_Q, VZIP_T1_Q" symboldefcount="2">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="size">
        <intro>For the 128-bit SIMD vector variant: is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VZIP_A1_Q, VZIP_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VZIP_A1_Q, VZIP_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VZIP_A1_D, VZIP_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VZIP_A1_D, VZIP_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VZIP/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    if quadword_operation then</line>
<line>        if d == m then</line>
<line>            <a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = bits(128) UNKNOWN;</line>
<line>        else</line>
<line>            bits(256) zipped_q;</line>
<line>            for e = 0 to (128 DIV esize) - 1</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[zipped_q,2*e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[d&gt;&gt;1],e,esize];</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[zipped_q,2*e+1,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1],e,esize];</line>
<line>            <a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = zipped_q&lt;127:0&gt;;  <a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[m&gt;&gt;1] = zipped_q&lt;255:128&gt;;</line>
<line>    else</line>
<line>        if d == m then</line>
<line>            <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = bits(64) UNKNOWN;</line>
<line>        else</line>
<line>            bits(128) zipped_d;</line>
<line>            for e = 0 to (64 DIV esize) - 1</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[zipped_d,2*e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d],e,esize];</line>
<line>                <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[zipped_d,2*e+1,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m],e,esize];</line>
<line>            <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = zipped_d&lt;63:0&gt;;  <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[m] = zipped_d&lt;127:64&gt;;</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="vzip_vtrn.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VZIP_VTRN" title="VZIP (alias) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="VZIP" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VTRN" />
    <docvar key="simdvectorsize" value="double" />
  </docvars>
  <heading>VZIP (alias)</heading>
  <desc>
    <brief>Vector Zip</brief>
    <longer> interleaves the elements of two vectors</longer>
  </desc>
  <aliasto refiform="vtrn.xml" iformid="VTRN">VTRN</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VTRN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VZIP_VTRN_A1_D" oneofinclass="1" oneof="2" label="64-bit SIMD vector">
        <docvars>
          <docvar key="alias_mnemonic" value="VZIP" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VTRN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <asmtemplate><text>VZIP</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vtrn.xml#VTRN_A1_D">VTRN</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VTRN" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" width="2" name="opc1" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" width="4" name="opc2" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="6" name="Q" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VZIP_VTRN_T1_D" oneofinclass="1" oneof="2" label="64-bit SIMD vector">
        <docvars>
          <docvar key="alias_mnemonic" value="VZIP" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VTRN" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <asmtemplate><text>VZIP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vtrn.xml#VTRN_T1_D">VTRN</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.32 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dm" hover="64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VZIP_VTRN_A1_D" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VZIP_VTRN_T1_D" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VZIP_VTRN_A1_D, VZIP_VTRN_T1_D" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VZIP_VTRN_A1_D, VZIP_VTRN_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VZIP_VTRN_A1_D, VZIP_VTRN_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
</file>
<file type="instructionsection" file="wfe.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="WFE" title="WFE -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="WFE" />
  </docvars>
  <heading>WFE</heading>
  <desc>
    <brief>
      <para>Wait For Event</para>
    </brief>
    <authored>
      <para>Wait For Event is a hint instruction that indicates that the PE can enter a low-power state and remain there until a wakeup event occurs. Wakeup events include the event signaled as a result of executing the <instruction>SEV</instruction> instruction on any PE in the multiprocessor system. For more information, see <xref linkend="CFIJIIHE">Wait For Event and Send Event</xref>.</para>
      <para>As described in <xref linkend="CFIJIIHE">Wait For Event and Send Event</xref>, the execution of a <instruction>WFE</instruction> instruction that would otherwise cause entry to a low-power state can be trapped to a higher Exception level, see:</para>
      <list type="unordered">
        <listitem><content><xref linkend="CHDJGAIC">Traps to Undefined mode of PL0 execution of WFE and WFI instructions</xref>.</content></listitem>
        <listitem><content><xref linkend="BEIBHJCJ">Traps to Hyp mode of Non-secure EL0 and EL1 execution of WFE and WFI instructions</xref>.</content></listitem>
        <listitem><content><xref linkend="CHDEGCIJ">Traps to Monitor mode of the execution of WFE and WFI instructions in modes other than Monitor mode</xref>.</content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="WFE" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/WFE/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="R" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="2" name="imm4&lt;3:2&gt;" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="17" width="2" name="imm4&lt;1:0&gt;" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" width="12" name="imm12" settings="12">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="WFE_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="WFE" />
        </docvars>
        <asmtemplate><text>WFE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/WFE/A1_A.txt" mylink="aarch32.instrs.WFE.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="WFE" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/WFE/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" width="4" name="hint" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="WFE_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="WFE" />
        </docvars>
        <asmtemplate><text>WFE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/WFE/T1_A.txt" mylink="aarch32.instrs.WFE.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="WFE" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/WFE/T2_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="hint" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="option" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="WFE_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="WFE" />
        </docvars>
        <asmtemplate><text>WFE</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/WFE/T2_A.txt" mylink="aarch32.instrs.WFE.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="WFE_A1, WFE_T1, WFE_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="WFE_A1, WFE_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/WFE/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if <a link="impl-shared.IsEventRegisterSet.0" file="shared_pseudocode.xml" hover="function: boolean IsEventRegisterSet()">IsEventRegisterSet</a>() then</line>
<line>        <a link="impl-shared.ClearEventRegister.0" file="shared_pseudocode.xml" hover="function: ClearEventRegister()">ClearEventRegister</a>();</line>
<line>    else</line>
<line>        if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>            // Check for traps described by the OS.</line>
<line>            <a link="AArch32.CheckForWFxTrap.2" file="shared_pseudocode.xml" hover="function: AArch32.CheckForWFxTrap(bits(2) target_el, WFxType wfxtype)">AArch32.CheckForWFxTrap</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, <a link="WFxType_WFE" file="shared_pseudocode.xml" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFE</a>);</line>
<line>        if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>            // Check for traps described by the Hypervisor.</line>
<line>            <a link="AArch32.CheckForWFxTrap.2" file="shared_pseudocode.xml" hover="function: AArch32.CheckForWFxTrap(bits(2) target_el, WFxType wfxtype)">AArch32.CheckForWFxTrap</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="WFxType_WFE" file="shared_pseudocode.xml" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFE</a>);</line>
<line>        if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; PSTATE.M != <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a> then</line>
<line>            // Check for traps described by the Secure Monitor.</line>
<line>            <a link="AArch32.CheckForWFxTrap.2" file="shared_pseudocode.xml" hover="function: AArch32.CheckForWFxTrap(bits(2) target_el, WFxType wfxtype)">AArch32.CheckForWFxTrap</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="WFxType_WFE" file="shared_pseudocode.xml" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFE</a>);</line>
<line>        integer localtimeout = 1 &lt;&lt; 64;  // No local timeout event is generated</line>
<line>        <a link="impl-shared.WaitForEvent.1" file="shared_pseudocode.xml" hover="function: WaitForEvent(integer localtimeout)">WaitForEvent</a>(localtimeout);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="wfi.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="WFI" title="WFI -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="WFI" />
  </docvars>
  <heading>WFI</heading>
  <desc>
    <brief>
      <para>Wait For Interrupt</para>
    </brief>
    <authored>
      <para>Wait For Interrupt is a hint instruction that indicates that the PE can enter a low-power state and remain there until a wakeup event occurs. For more information, see <xref linkend="CFIBBGJG">Wait For Interrupt</xref>.</para>
      <para>As described in <xref linkend="CFIBBGJG">Wait For Interrupt</xref>, the execution of a <instruction>WFI</instruction> instruction that would otherwise cause entry to a low-power state can be trapped to a higher Exception level, see:</para>
      <list type="unordered">
        <listitem><content><xref linkend="CHDJGAIC">Traps to Undefined mode of PL0 execution of WFE and WFI instructions</xref>.</content></listitem>
        <listitem><content><xref linkend="BEIBHJCJ">Traps to Hyp mode of Non-secure EL0 and EL1 execution of WFE and WFI instructions</xref>.</content></listitem>
        <listitem><content><xref linkend="CHDEGCIJ">Traps to Monitor mode of the execution of WFE and WFI instructions in modes other than Monitor mode</xref>.</content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="WFI" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/WFI/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="R" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="2" name="imm4&lt;3:2&gt;" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="17" width="2" name="imm4&lt;1:0&gt;" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" width="12" name="imm12" settings="12">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="WFI_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="WFI" />
        </docvars>
        <asmtemplate><text>WFI</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/WFI/A1_A.txt" mylink="aarch32.instrs.WFI.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="WFI" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/WFI/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" width="4" name="hint" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="WFI_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="WFI" />
        </docvars>
        <asmtemplate><text>WFI</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/WFI/T1_A.txt" mylink="aarch32.instrs.WFI.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="WFI" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/WFI/T2_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="hint" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="option" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="WFI_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="WFI" />
        </docvars>
        <asmtemplate><text>WFI</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/WFI/T2_A.txt" mylink="aarch32.instrs.WFI.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="WFI_A1, WFI_T1, WFI_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="WFI_A1, WFI_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/WFI/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    if !<a link="impl-shared.InterruptPending.0" file="shared_pseudocode.xml" hover="function: boolean InterruptPending()">InterruptPending</a>() then</line>
<line>        if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>            // Check for traps described by the OS.</line>
<line>            <a link="AArch32.CheckForWFxTrap.2" file="shared_pseudocode.xml" hover="function: AArch32.CheckForWFxTrap(bits(2) target_el, WFxType wfxtype)">AArch32.CheckForWFxTrap</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, <a link="WFxType_WFI" file="shared_pseudocode.xml" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFI</a>);</line>
<line>        if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>            // Check for traps described by the Hypervisor.</line>
<line>            <a link="AArch32.CheckForWFxTrap.2" file="shared_pseudocode.xml" hover="function: AArch32.CheckForWFxTrap(bits(2) target_el, WFxType wfxtype)">AArch32.CheckForWFxTrap</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="WFxType_WFI" file="shared_pseudocode.xml" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFI</a>);</line>
<line>        if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; PSTATE.M != <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a> then</line>
<line>            // Check for traps described by the Secure Monitor.</line>
<line>            <a link="AArch32.CheckForWFxTrap.2" file="shared_pseudocode.xml" hover="function: AArch32.CheckForWFxTrap(bits(2) target_el, WFxType wfxtype)">AArch32.CheckForWFxTrap</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="WFxType_WFI" file="shared_pseudocode.xml" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFI</a>);</line>
<line>        integer localtimeout = 1 &lt;&lt; 64;  // No local timeout event is generated</line>
<line>        <a link="impl-shared.WaitForInterrupt.1" file="shared_pseudocode.xml" hover="function: WaitForInterrupt(integer localtimeout)">WaitForInterrupt</a>(localtimeout);</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
<file type="instructionsection" file="yield.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="YIELD" title="YIELD -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="YIELD" />
  </docvars>
  <heading>YIELD</heading>
  <desc>
    <brief>
      <para>Yield hint</para>
    </brief>
    <authored>
      <para><instruction>YIELD</instruction> is a hint instruction. Software with a multithreading capability can use a <instruction>YIELD</instruction> instruction to indicate to the PE that it is performing a task, for example a spin-lock, that could be swapped out to improve overall system performance. The PE can use this hint to suspend and resume multiple software threads if it supports the capability.</para>
      <para>For more information about the recommended use of this instruction see <xref linkend="CFIGJJJG">The Yield instruction</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="YIELD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/YIELD/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="R" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" width="2" name="imm4&lt;3:2&gt;" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="17" width="2" name="imm4&lt;1:0&gt;" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" width="12" name="imm12" settings="12">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="YIELD_A1" oneofinclass="1" oneof="3" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="YIELD" />
        </docvars>
        <asmtemplate><text>YIELD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/YIELD/A1_A.txt" mylink="aarch32.instrs.YIELD.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="YIELD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/YIELD/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" width="4" name="hint" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="YIELD_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="YIELD" />
        </docvars>
        <asmtemplate><text>YIELD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/YIELD/T1_A.txt" mylink="aarch32.instrs.YIELD.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="YIELD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/YIELD/T2_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="4" name="hint" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="option" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="YIELD_T2" oneofinclass="1" oneof="3" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="YIELD" />
        </docvars>
        <asmtemplate><text>YIELD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/YIELD/T2_A.txt" mylink="aarch32.instrs.YIELD.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode"><line>// No additional decoding required</line>
</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="YIELD_A1, YIELD_T1, YIELD_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="YIELD_A1, YIELD_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/YIELD/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><line>if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then</line>
<line>    EncodingSpecificOperations();</line>
<line>    <a link="impl-shared.Hint_Yield.0" file="shared_pseudocode.xml" hover="function: Hint_Yield()">Hint_Yield</a>();</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
  </sect1>
  <sect1 id="pseudocode">
    <title>Pseudocode library</title>
    <para>This section contains the library of pseudocode functions.</para>
<file type="instructionsection" file="shared_pseudocode.xml">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="shared_pseudocode" title="AArch32 Instruction Summary -- Shared Pseudocode" type="pseudocode">
  <heading>Shared Pseudocode Functions</heading>
  <desc>
    <brief>This page displays common pseudocode functions shared by many pages</brief>
  </desc>
  <ps_section howmany="1677">
    <ps name="aarch32/at/AArch32.AT" mylink="aarch32.at.AArch32.AT" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.AT()</line>
<line>// ============</line>
<line>// Perform address translation as per AT instructions.</line>
<line></line>
<line link="AArch32.AT.4" hover="function: AArch32.AT(bits(32) vaddress, TranslationStage stage_in, bits(2) el, ATAccess ataccess)" conts="AArch32.AT"><anchor link="AArch32.AT.4" hover="function: AArch32.AT(bits(32) vaddress, TranslationStage stage_in, bits(2) el, ATAccess ataccess)">AArch32.AT</anchor>(bits(32) vaddress, <a link="TranslationStage" file="shared_pseudocode.xml" hover="enumeration TranslationStage { TranslationStage_1, TranslationStage_12 }">TranslationStage</a> stage_in, bits(2) el, <a link="ATAccess" file="shared_pseudocode.xml" hover="enumeration ATAccess { ATAccess_Read, ATAccess_Write, ATAccess_ReadPAN, ATAccess_WritePAN }">ATAccess</a> ataccess)</line>
<line>    <a link="TranslationStage" file="shared_pseudocode.xml" hover="enumeration TranslationStage { TranslationStage_1, TranslationStage_12 }">TranslationStage</a> stage = stage_in;</line>
<line>    <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss;</line>
<line>    <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime;</line>
<line>    boolean eae;</line>
<line></line>
<line>    // ATS1Hx instructions</line>
<line>    if el == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>        regime = <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>;</line>
<line>        eae = TRUE;</line>
<line>        ss = <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a>;</line>
<line></line>
<line>    // ATS1Cxx instructions</line>
<line>    elsif stage == <a link="TranslationStage_1" file="shared_pseudocode.xml" hover="enumeration TranslationStage { TranslationStage_1, TranslationStage_12 }">TranslationStage_1</a> || (stage == <a link="TranslationStage_12" file="shared_pseudocode.xml" hover="enumeration TranslationStage { TranslationStage_1, TranslationStage_12 }">TranslationStage_12</a> &amp;&amp; !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>)) then</line>
<line>        stage = <a link="TranslationStage_1" file="shared_pseudocode.xml" hover="enumeration TranslationStage { TranslationStage_1, TranslationStage_12 }">TranslationStage_1</a>;</line>
<line>        ss = <a link="impl-shared.SecurityStateAtEL.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)">SecurityStateAtEL</a>(PSTATE.EL);</line>
<line>        regime = if ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> &amp;&amp; <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then <a link="Regime_EL30" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL30</a> else <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a>;</line>
<line>        eae = TTBCR.EAE == '1';</line>
<line></line>
<line>    // ATS12NSOxx instructions</line>
<line>    else</line>
<line>        regime = <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a>;</line>
<line>        eae = if <a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then TTBCR_NS.EAE == '1' else TTBCR.EAE == '1';</line>
<line>        ss = <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a>;</line>
<line></line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> addrdesc;</line>
<line>    <a link="SDFType" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType</a> sdftype;</line>
<line>    boolean aligned = TRUE;</line>
<line>    bit supersection = '0';</line>
<line></line>
<line>    boolean write = ataccess IN {<a link="ATAccess_WritePAN" file="shared_pseudocode.xml" hover="enumeration ATAccess { ATAccess_Read, ATAccess_Write, ATAccess_ReadPAN, ATAccess_WritePAN }">ATAccess_WritePAN</a>, <a link="ATAccess_Write" file="shared_pseudocode.xml" hover="enumeration ATAccess { ATAccess_Read, ATAccess_Write, ATAccess_ReadPAN, ATAccess_WritePAN }">ATAccess_Write</a>};</line>
<line>    boolean pan   = ataccess IN {<a link="ATAccess_WritePAN" file="shared_pseudocode.xml" hover="enumeration ATAccess { ATAccess_Read, ATAccess_Write, ATAccess_ReadPAN, ATAccess_WritePAN }">ATAccess_WritePAN</a>, <a link="ATAccess_ReadPAN" file="shared_pseudocode.xml" hover="enumeration ATAccess { ATAccess_Read, ATAccess_Write, ATAccess_ReadPAN, ATAccess_WritePAN }">ATAccess_ReadPAN</a>};</line>
<line>    accdesc = <a link="impl-shared.CreateAccDescAT.4" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescAT(SecurityState ss, bits(2) el, boolean write, boolean pan)">CreateAccDescAT</a>(ss, el, write, pan);</line>
<line></line>
<line>    // Prepare fault fields in case a fault is detected</line>
<line>    fault = <a link="impl-shared.NoFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord NoFault(AccessDescriptor accdesc)">NoFault</a>(accdesc);</line>
<line></line>
<line>    if eae then</line>
<line>        (fault, addrdesc) = <a link="AArch32.S1TranslateLD.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, AddressDescriptor) AArch32.S1TranslateLD(FaultRecord fault_in, Regime regime, bits(32) va, boolean aligned, AccessDescriptor accdesc)">AArch32.S1TranslateLD</a>(fault, regime, vaddress, aligned, accdesc);</line>
<line>    else</line>
<line>        (fault, addrdesc, sdftype) = <a link="AArch32.S1TranslateSD.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, AddressDescriptor, SDFType) AArch32.S1TranslateSD(FaultRecord fault_in, Regime regime, bits(32) va, boolean aligned, AccessDescriptor accdesc)">AArch32.S1TranslateSD</a>(fault, regime, vaddress, aligned,</line>
<line>                                                           accdesc);</line>
<line>        supersection = if sdftype == <a link="SDFType_Supersection" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_Supersection</a> then '1' else '0';</line>
<line></line>
<line>    // ATS12NSOxx instructions</line>
<line>    if stage == <a link="TranslationStage_12" file="shared_pseudocode.xml" hover="enumeration TranslationStage { TranslationStage_1, TranslationStage_12 }">TranslationStage_12</a> &amp;&amp; fault.statuscode == <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>        (fault, addrdesc) = <a link="AArch32.S2Translate.4" file="shared_pseudocode.xml" hover="function: (FaultRecord, AddressDescriptor) AArch32.S2Translate(FaultRecord fault_in, AddressDescriptor ipa, boolean aligned, AccessDescriptor accdesc)">AArch32.S2Translate</a>(fault, addrdesc, aligned, accdesc);</line>
<line></line>
<line>    if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>        // Take exception on External abort or when a fault occurs on translation table walk</line>
<line>        if <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault) || (PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; fault.s2fs1walk) then</line>
<line>            PAR = bits(64) UNKNOWN;</line>
<line>            <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(vaddress, fault);</line>
<line></line>
<line>    addrdesc.fault = fault;</line>
<line></line>
<line>    if (eae || (stage == <a link="TranslationStage_12" file="shared_pseudocode.xml" hover="enumeration TranslationStage { TranslationStage_1, TranslationStage_12 }">TranslationStage_12</a> &amp;&amp; (HCR.VM == '1' || HCR.DC == '1'))</line>
<line>            || (stage == <a link="TranslationStage_1" file="shared_pseudocode.xml" hover="enumeration TranslationStage { TranslationStage_1, TranslationStage_12 }">TranslationStage_1</a> &amp;&amp; el != <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> &amp;&amp; PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>)) then</line>
<line>        <a link="AArch32.EncodePARLD.2" file="shared_pseudocode.xml" hover="function: AArch32.EncodePARLD(AddressDescriptor addrdesc, SecurityState ss)">AArch32.EncodePARLD</a>(addrdesc, ss);</line>
<line>    else</line>
<line>        <a link="AArch32.EncodePARSD.3" file="shared_pseudocode.xml" hover="function: AArch32.EncodePARSD(AddressDescriptor addrdesc_in, bit supersection, SecurityState ss)">AArch32.EncodePARSD</a>(addrdesc, supersection, ss);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/at/AArch32.EncodePARLD" mylink="aarch32.at.AArch32.EncodePARLD" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.EncodePARLD()</line>
<line>// =====================</line>
<line>// Returns 64-bit format PAR on address translation instruction.</line>
<line></line>
<line link="AArch32.EncodePARLD.2" hover="function: AArch32.EncodePARLD(AddressDescriptor addrdesc, SecurityState ss)" conts="AArch32.EncodePARLD"><anchor link="AArch32.EncodePARLD.2" hover="function: AArch32.EncodePARLD(AddressDescriptor addrdesc, SecurityState ss)">AArch32.EncodePARLD</anchor>(<a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> addrdesc, <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss)</line>
<line></line>
<line>    if !<a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(addrdesc) then</line>
<line>        bit ns;</line>
<line>        if ss == <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> then</line>
<line>            ns = bit UNKNOWN;</line>
<line>        elsif addrdesc.paddress.paspace == <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a> then</line>
<line>            ns = '0';</line>
<line>        else</line>
<line>            ns = '1';</line>
<line>        PAR.F      = '0';</line>
<line>        PAR.SH     = <a link="impl-shared.ReportedPARShareability.1" file="shared_pseudocode.xml" hover="function: bits(2) ReportedPARShareability(bits(2) sh)">ReportedPARShareability</a>(<a link="impl-shared.PAREncodeShareability.1" file="shared_pseudocode.xml" hover="function: bits(2) PAREncodeShareability(MemoryAttributes memattrs)">PAREncodeShareability</a>(addrdesc.memattrs));</line>
<line>        PAR.NS     = ns;</line>
<line>        PAR&lt;10&gt;    = bit IMPLEMENTATION_DEFINED "Non-Faulting PAR";               // IMPDEF</line>
<line>        PAR.LPAE   = '1';</line>
<line>        PAR.PA     = addrdesc.paddress.address&lt;39:12&gt;;</line>
<line>        PAR.ATTR   = <a link="impl-shared.ReportedPARAttrs.1" file="shared_pseudocode.xml" hover="function: bits(8) ReportedPARAttrs(bits(8) parattrs)">ReportedPARAttrs</a>(<a link="impl-shared.EncodePARAttrs.1" file="shared_pseudocode.xml" hover="function: bits(8) EncodePARAttrs(MemoryAttributes memattrs)">EncodePARAttrs</a>(addrdesc.memattrs));</line>
<line>    else</line>
<line>        PAR.F      = '1';</line>
<line>        PAR.FST    = <a link="AArch32.PARFaultStatusLD.1" file="shared_pseudocode.xml" hover="function: bits(6) AArch32.PARFaultStatusLD(FaultRecord fault)">AArch32.PARFaultStatusLD</a>(addrdesc.fault);</line>
<line>        PAR.S2WLK  = if addrdesc.fault.s2fs1walk then '1' else '0';</line>
<line>        PAR.FSTAGE = if addrdesc.fault.secondstage then '1' else '0';</line>
<line>        PAR.LPAE   = '1';</line>
<line>        PAR&lt;63:48&gt; = bits(16) IMPLEMENTATION_DEFINED "Faulting PAR";              // IMPDEF</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/at/AArch32.EncodePARSD" mylink="aarch32.at.AArch32.EncodePARSD" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.EncodePARSD()</line>
<line>// =====================</line>
<line>// Returns 32-bit format PAR on address translation instruction.</line>
<line></line>
<line link="AArch32.EncodePARSD.3" hover="function: AArch32.EncodePARSD(AddressDescriptor addrdesc_in, bit supersection, SecurityState ss)" conts="AArch32.EncodePARSD"><anchor link="AArch32.EncodePARSD.3" hover="function: AArch32.EncodePARSD(AddressDescriptor addrdesc_in, bit supersection, SecurityState ss)">AArch32.EncodePARSD</anchor>(<a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> addrdesc_in, bit supersection, <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss)</line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> addrdesc = addrdesc_in;</line>
<line>    if !<a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(addrdesc) then</line>
<line>        if (addrdesc.memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> ||</line>
<line>                (addrdesc.memattrs.inner.attrs == <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a> &amp;&amp;</line>
<line>                 addrdesc.memattrs.outer.attrs == <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a>)) then</line>
<line>            addrdesc.memattrs.shareability = <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a>;</line>
<line>        bit ns;</line>
<line>        if ss == <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> then</line>
<line>            ns = bit UNKNOWN;</line>
<line>        elsif addrdesc.paddress.paspace == <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a> then</line>
<line>            ns = '0';</line>
<line>        else</line>
<line>            ns = '1';</line>
<line>        bits(2) sh = if addrdesc.memattrs.shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then '01' else '00';</line>
<line>        PAR.F      = '0';</line>
<line>        PAR.SS     = supersection;</line>
<line>        PAR.Outer  = <a link="AArch32.ReportedOuterAttrs.1" file="shared_pseudocode.xml" hover="function: bits(2) AArch32.ReportedOuterAttrs(bits(2) attrs)">AArch32.ReportedOuterAttrs</a>(<a link="AArch32.PAROuterAttrs.1" file="shared_pseudocode.xml" hover="function: bits(2) AArch32.PAROuterAttrs(MemoryAttributes memattrs)">AArch32.PAROuterAttrs</a>(addrdesc.memattrs));</line>
<line>        PAR.Inner  = <a link="AArch32.ReportedInnerAttrs.1" file="shared_pseudocode.xml" hover="function: bits(3) AArch32.ReportedInnerAttrs(bits(3) attrs)">AArch32.ReportedInnerAttrs</a>(<a link="AArch32.PARInnerAttrs.1" file="shared_pseudocode.xml" hover="function: bits(3) AArch32.PARInnerAttrs(MemoryAttributes memattrs)">AArch32.PARInnerAttrs</a>(addrdesc.memattrs));</line>
<line>        PAR.SH     = <a link="impl-shared.ReportedPARShareability.1" file="shared_pseudocode.xml" hover="function: bits(2) ReportedPARShareability(bits(2) sh)">ReportedPARShareability</a>(sh);</line>
<line>        PAR&lt;8&gt;     = bit IMPLEMENTATION_DEFINED "Non-Faulting PAR";               // IMPDEF</line>
<line>        PAR.NS     = ns;</line>
<line>        PAR.NOS    = if addrdesc.memattrs.shareability == <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a> then '0' else '1';</line>
<line>        PAR.LPAE   = '0';</line>
<line>        PAR.PA     = addrdesc.paddress.address&lt;39:12&gt;;</line>
<line>    else</line>
<line>        PAR.F      = '1';</line>
<line>        PAR.FST    = <a link="AArch32.PARFaultStatusSD.1" file="shared_pseudocode.xml" hover="function: bits(6) AArch32.PARFaultStatusSD(FaultRecord fault)">AArch32.PARFaultStatusSD</a>(addrdesc.fault);</line>
<line>        PAR.LPAE   = '0';</line>
<line>        PAR&lt;31:16&gt; = bits(16) IMPLEMENTATION_DEFINED "Faulting PAR";              // IMPDEF</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/at/AArch32.PARFaultStatusLD" mylink="aarch32.at.AArch32.PARFaultStatusLD" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.PARFaultStatusLD()</line>
<line>// ==========================</line>
<line>// Fault status field decoding of 64-bit PAR</line>
<line></line>
<line link="AArch32.PARFaultStatusLD.1" hover="function: bits(6) AArch32.PARFaultStatusLD(FaultRecord fault)" conts="AArch32.PARFaultStatusLD">bits(6) <anchor link="AArch32.PARFaultStatusLD.1" hover="function: bits(6) AArch32.PARFaultStatusLD(FaultRecord fault)">AArch32.PARFaultStatusLD</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    bits(6) syndrome;</line>
<line></line>
<line>    if fault.statuscode == <a link="Fault_Domain" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Domain</a> then</line>
<line>        // Report Domain fault</line>
<line>        assert fault.level IN {1,2};</line>
<line>        syndrome&lt;1:0&gt; = if fault.level == 1 then '01' else '10';</line>
<line>        syndrome&lt;5:2&gt; = '1111';</line>
<line>    else</line>
<line>        syndrome = <a link="impl-shared.EncodeLDFSC.2" file="shared_pseudocode.xml" hover="function: bits(6) EncodeLDFSC(Fault statuscode, integer level)">EncodeLDFSC</a>(fault.statuscode, fault.level);</line>
<line>    return syndrome;</line>
</pstext>
    </ps>
    <ps name="aarch32/at/AArch32.PARFaultStatusSD" mylink="aarch32.at.AArch32.PARFaultStatusSD" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.PARFaultStatusSD()</line>
<line>// ==========================</line>
<line>// Fault status field decoding of 32-bit PAR.</line>
<line></line>
<line link="AArch32.PARFaultStatusSD.1" hover="function: bits(6) AArch32.PARFaultStatusSD(FaultRecord fault)" conts="AArch32.PARFaultStatusSD">bits(6) <anchor link="AArch32.PARFaultStatusSD.1" hover="function: bits(6) AArch32.PARFaultStatusSD(FaultRecord fault)">AArch32.PARFaultStatusSD</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    bits(6) syndrome;</line>
<line></line>
<line>    syndrome&lt;5&gt; = if <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault) then fault.extflag else '0';</line>
<line>    syndrome&lt;4:0&gt; = <a link="impl-aarch32.EncodeSDFSC.2" file="shared_pseudocode.xml" hover="function: bits(5) EncodeSDFSC(Fault statuscode, integer level)">EncodeSDFSC</a>(fault.statuscode, fault.level);</line>
<line>    return syndrome;</line>
</pstext>
    </ps>
    <ps name="aarch32/at/AArch32.PARInnerAttrs" mylink="aarch32.at.AArch32.PARInnerAttrs" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.PARInnerAttrs()</line>
<line>// =======================</line>
<line>// Convert orthogonal attributes and hints to 32-bit PAR Inner field.</line>
<line></line>
<line link="AArch32.PARInnerAttrs.1" hover="function: bits(3) AArch32.PARInnerAttrs(MemoryAttributes memattrs)" conts="AArch32.PARInnerAttrs">bits(3) <anchor link="AArch32.PARInnerAttrs.1" hover="function: bits(3) AArch32.PARInnerAttrs(MemoryAttributes memattrs)">AArch32.PARInnerAttrs</anchor>(<a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs)</line>
<line>    bits(3) result;</line>
<line></line>
<line>    if memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> then</line>
<line>        if memattrs.device == <a link="DeviceType_nGnRnE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGnRnE</a> then</line>
<line>            result = '001'; // Non-cacheable</line>
<line>        elsif memattrs.device == <a link="DeviceType_nGnRE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGnRE</a> then</line>
<line>            result = '011'; // Non-cacheable</line>
<line>    else</line>
<line>        <a link="MemAttrHints" file="shared_pseudocode.xml" hover="type MemAttrHints is ( bits(2) attrs, bits(2) hints, boolean transient )">MemAttrHints</a> inner = memattrs.inner;</line>
<line>        if inner.attrs == <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a> then</line>
<line>            result = '000'; // Non-cacheable</line>
<line>        elsif inner.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a> &amp;&amp; inner.hints&lt;0&gt; == '1' then</line>
<line>            result = '101'; // Write-Back, Write-Allocate</line>
<line>        elsif inner.attrs == <a link="MemAttr_WT" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WT = '10'">MemAttr_WT</a> then</line>
<line>            result = '110'; // Write-Through</line>
<line>        elsif inner.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a> &amp;&amp; inner.hints&lt;0&gt; == '0' then</line>
<line>            result = '111'; // Write-Back, no Write-Allocate</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch32/at/AArch32.PAROuterAttrs" mylink="aarch32.at.AArch32.PAROuterAttrs" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.PAROuterAttrs()</line>
<line>// =======================</line>
<line>// Convert orthogonal attributes and hints to 32-bit PAR Outer field.</line>
<line></line>
<line link="AArch32.PAROuterAttrs.1" hover="function: bits(2) AArch32.PAROuterAttrs(MemoryAttributes memattrs)" conts="AArch32.PAROuterAttrs">bits(2) <anchor link="AArch32.PAROuterAttrs.1" hover="function: bits(2) AArch32.PAROuterAttrs(MemoryAttributes memattrs)">AArch32.PAROuterAttrs</anchor>(<a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs)</line>
<line>    bits(2) result;</line>
<line></line>
<line>    if memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> then</line>
<line>        result = bits(2) UNKNOWN;</line>
<line>    else</line>
<line>        <a link="MemAttrHints" file="shared_pseudocode.xml" hover="type MemAttrHints is ( bits(2) attrs, bits(2) hints, boolean transient )">MemAttrHints</a> outer = memattrs.outer;</line>
<line>        if outer.attrs == <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a> then</line>
<line>            result = '00'; // Non-cacheable</line>
<line>        elsif outer.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a> &amp;&amp; outer.hints&lt;0&gt; == '1' then</line>
<line>            result = '01'; // Write-Back, Write-Allocate</line>
<line>        elsif outer.attrs == <a link="MemAttr_WT" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WT = '10'">MemAttr_WT</a> &amp;&amp; outer.hints&lt;0&gt; == '0' then</line>
<line>            result = '10'; // Write-Through, no Write-Allocate</line>
<line>        elsif outer.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a> &amp;&amp; outer.hints&lt;0&gt; == '0' then</line>
<line>            result = '11'; // Write-Back, no Write-Allocate</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch32/at/AArch32.ReportedInnerAttrs" mylink="aarch32.at.AArch32.ReportedInnerAttrs" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.ReportedInnerAttrs()</line>
<line>// ============================</line>
<line>// The value returned in this field can be the resulting attribute, as determined by any permitted</line>
<line>// implementation choices and any applicable configuration bits, instead of the value that appears</line>
<line>// in the translation table descriptor.</line>
<line></line>
<line link="AArch32.ReportedInnerAttrs.1" hover="function: bits(3) AArch32.ReportedInnerAttrs(bits(3) attrs)" conts="AArch32.ReportedInnerAttrs">bits(3) <anchor link="AArch32.ReportedInnerAttrs.1" hover="function: bits(3) AArch32.ReportedInnerAttrs(bits(3) attrs)">AArch32.ReportedInnerAttrs</anchor>(bits(3) attrs);</line>
</pstext>
    </ps>
    <ps name="aarch32/at/AArch32.ReportedOuterAttrs" mylink="aarch32.at.AArch32.ReportedOuterAttrs" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.ReportedOuterAttrs()</line>
<line>// ============================</line>
<line>// The value returned in this field can be the resulting attribute, as determined by any permitted</line>
<line>// implementation choices and any applicable configuration bits, instead of the value that appears</line>
<line>// in the translation table descriptor.</line>
<line></line>
<line link="AArch32.ReportedOuterAttrs.1" hover="function: bits(2) AArch32.ReportedOuterAttrs(bits(2) attrs)" conts="AArch32.ReportedOuterAttrs">bits(2) <anchor link="AArch32.ReportedOuterAttrs.1" hover="function: bits(2) AArch32.ReportedOuterAttrs(bits(2) attrs)">AArch32.ReportedOuterAttrs</anchor>(bits(2) attrs);</line>
</pstext>
    </ps>
    <ps name="aarch32/dc/AArch32.DC" mylink="aarch32.dc.AArch32.DC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.DC()</line>
<line>// ============</line>
<line>// Perform Data Cache Operation.</line>
<line></line>
<line link="AArch32.DC.3" hover="function: AArch32.DC(bits(32) regval, CacheOp cacheop, CacheOpScope opscope)" conts="AArch32.DC"><anchor link="AArch32.DC.3" hover="function: AArch32.DC(bits(32) regval, CacheOp cacheop, CacheOpScope opscope)">AArch32.DC</anchor>(bits(32) regval, <a link="CacheOp" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp</a> cacheop, <a link="CacheOpScope" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope</a> opscope)</line>
<line>    <a link="CacheRecord" file="shared_pseudocode.xml" hover="type CacheRecord is ( AccessType acctype, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, bits(64) regval, FullAddress paddress, bits(64) vaddress, integer set, integer way, integer level, Shareability shareability, boolean translated, boolean is_vmid_valid, bits(16) vmid, boolean is_asid_valid, bits(16) asid, SecurityState security, CachePASpace cpas )">CacheRecord</a> cache;</line>
<line></line>
<line>    cache.acctype   = <a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>;</line>
<line>    cache.cacheop   = cacheop;</line>
<line>    cache.opscope   = opscope;</line>
<line>    cache.cachetype = <a link="CacheType_Data" file="shared_pseudocode.xml" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }">CacheType_Data</a>;</line>
<line>    cache.security  = <a link="impl-shared.SecurityStateAtEL.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)">SecurityStateAtEL</a>(PSTATE.EL);</line>
<line></line>
<line>    if opscope == <a link="CacheOpScope_SetWay" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_SetWay</a> then</line>
<line>        cache.shareability = <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a>;</line>
<line>        (cache.set, cache.way, cache.level) = <a link="impl-shared.DecodeSW.2" file="shared_pseudocode.xml" hover="function: (integer, integer, integer) DecodeSW(bits(64) regval, CacheType cachetype)">DecodeSW</a>(<a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(regval, 64), <a link="CacheType_Data" file="shared_pseudocode.xml" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }">CacheType_Data</a>);</line>
<line></line>
<line>        if (cacheop == <a link="CacheOp_Invalidate" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_Invalidate</a> &amp;&amp; PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>            ((!<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; (HCR_EL2.SWIO == '1' || HCR_EL2.&lt;DC,VM&gt; != '00')) ||</line>
<line>              (<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; (HCR.SWIO == '1' || HCR.&lt;DC,VM&gt; != '00')))) then</line>
<line>            cache.cacheop = <a link="CacheOp_CleanInvalidate" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_CleanInvalidate</a>;</line>
<line>        <a link="impl-shared.CACHE_OP.1" file="shared_pseudocode.xml" hover="function: CACHE_OP(CacheRecord cache)">CACHE_OP</a>(cache);</line>
<line>        return;</line>
<line></line>
<line>    if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} then</line>
<line>            cache.is_vmid_valid = TRUE;</line>
<line>            cache.vmid          = VMID[];</line>
<line>        else</line>
<line>            cache.is_vmid_valid = FALSE;</line>
<line>    else</line>
<line>        cache.is_vmid_valid = FALSE;</line>
<line></line>
<line>    if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        cache.is_asid_valid = TRUE;</line>
<line>        cache.asid          = <a link="impl-shared.ASID.read.0" file="shared_pseudocode.xml" hover="accessor: bits(16) ASID[]">ASID</a>[];</line>
<line>    else</line>
<line>        cache.is_asid_valid = FALSE;</line>
<line></line>
<line>    need_translate = <a link="impl-shared.DCInstNeedsTranslation.1" file="shared_pseudocode.xml" hover="function: boolean DCInstNeedsTranslation(CacheOpScope opscope)">DCInstNeedsTranslation</a>(opscope);</line>
<line>    vaddress = regval;</line>
<line></line>
<line>    size = 0;        // by default no watchpoint address</line>
<line>    if cacheop == <a link="CacheOp_Invalidate" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_Invalidate</a> then</line>
<line>        size = integer IMPLEMENTATION_DEFINED "Data Cache Invalidate Watchpoint Size";</line>
<line>        assert size &gt;= 4*(2^(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(CTR_EL0.DminLine))) &amp;&amp; size &lt;= 2048;</line>
<line>        assert <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size&lt;32:0&gt; AND (size-1)&lt;32:0&gt;) == 0; // size is power of 2</line>
<line>        vaddress = <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(regval, size);</line>
<line></line>
<line>    cache.translated = need_translate;</line>
<line>    cache.vaddress   = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(vaddress, 64);</line>
<line></line>
<line>    if need_translate then</line>
<line>        boolean aligned = TRUE;</line>
<line>        <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescDC.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescDC(CacheRecord cache)">CreateAccDescDC</a>(cache);</line>
<line>        <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc = <a link="AArch32.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch32.TranslateAddress(bits(32) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch32.TranslateAddress</a>(vaddress, accdesc, aligned, size);</line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>            <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(regval, memaddrdesc.fault);</line>
<line></line>
<line>        cache.paddress = memaddrdesc.paddress;</line>
<line>        if opscope == <a link="CacheOpScope_PoC" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_PoC</a> then</line>
<line>            cache.shareability = memaddrdesc.memattrs.shareability;</line>
<line>        else</line>
<line>            cache.shareability = <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a>;</line>
<line>    else</line>
<line>        cache.shareability = <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> UNKNOWN;</line>
<line>        cache.paddress     = <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> UNKNOWN;</line>
<line></line>
<line>    if (cacheop == <a link="CacheOp_Invalidate" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_Invalidate</a> &amp;&amp; PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>            ((!<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; HCR_EL2.&lt;DC,VM&gt; != '00') ||</line>
<line>              (<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; HCR.&lt;DC,VM&gt; != '00'))) then</line>
<line>        cache.cacheop = <a link="CacheOp_CleanInvalidate" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_CleanInvalidate</a>;</line>
<line></line>
<line>    <a link="impl-shared.CACHE_OP.1" file="shared_pseudocode.xml" hover="function: CACHE_OP(CacheRecord cache)">CACHE_OP</a>(cache);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/debug/VCRMatch/AArch32.VCRMatch" mylink="aarch32.debug.VCRMatch.AArch32.VCRMatch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.VCRMatch()</line>
<line>// ==================</line>
<line></line>
<line link="AArch32.VCRMatch.1" hover="function: boolean AArch32.VCRMatch(bits(32) vaddress)" conts="AArch32.VCRMatch">boolean <anchor link="AArch32.VCRMatch.1" hover="function: boolean AArch32.VCRMatch(bits(32) vaddress)">AArch32.VCRMatch</anchor>(bits(32) vaddress)</line>
<line></line>
<line>    boolean match;</line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) &amp;&amp; PSTATE.EL != <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>        // Each bit position in this string corresponds to a bit in DBGVCR and an exception vector.</line>
<line>        match_word = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32);</line>
<line></line>
<line>        ss = <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>();</line>
<line>        if vaddress&lt;31:5&gt; == <a link="impl-aarch32.ExcVectorBase.0" file="shared_pseudocode.xml" hover="function: bits(32) ExcVectorBase()">ExcVectorBase</a>()&lt;31:5&gt; then</line>
<line>            if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; ss == <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> then</line>
<line>                match_word&lt;<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(vaddress&lt;4:2&gt;) + 24&gt; = '1';     // Non-secure vectors</line>
<line>            else</line>
<line>                match_word&lt;<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(vaddress&lt;4:2&gt;) + 0&gt; = '1';      // Secure vectors (or no EL3)</line>
<line></line>
<line>        if (<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; vaddress&lt;31:5&gt; == MVBAR&lt;31:5&gt; &amp;&amp;</line>
<line>            ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>) then</line>
<line>            match_word&lt;<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(vaddress&lt;4:2&gt;) + 8&gt; = '1';          // Monitor vectors</line>
<line></line>
<line>        // Mask out bits not corresponding to vectors.</line>
<line>        bits(32) mask;</line>
<line>        if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>            mask = '00000000':'00000000':'00000000':'11011110'; // DBGVCR[31:8] are RES0</line>
<line>        elsif !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>            mask = '11011110':'00000000':'00000000':'11011110'; // DBGVCR[15:8] are RES0</line>
<line>        else</line>
<line>            mask = '11011110':'00000000':'11011100':'11011110';</line>
<line></line>
<line>        match_word = match_word AND DBGVCR AND mask;</line>
<line>        match = !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(match_word);</line>
<line></line>
<line>        // Check for UNPREDICTABLE case - match on Prefetch Abort and Data Abort vectors</line>
<line>        if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(match_word&lt;28:27,12:11,4:3&gt;) &amp;&amp; <a link="impl-shared.DebugTarget.0" file="shared_pseudocode.xml" hover="function: bits(2) DebugTarget()">DebugTarget</a>() == PSTATE.EL then</line>
<line>            match = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_VCMATCHDAPA" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_VCMATCHDAPA</a>);</line>
<line></line>
<line>        if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(vaddress&lt;1:0&gt;) &amp;&amp; match then</line>
<line>            match = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_VCMATCHHALF" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_VCMATCHHALF</a>);</line>
<line>    else</line>
<line>        match = FALSE;</line>
<line></line>
<line>    return match;</line>
</pstext>
    </ps>
    <ps name="aarch32/debug/authentication/AArch32.SelfHostedSecurePrivilegedInvasiveDebugEnabled" mylink="aarch32.debug.authentication.AArch32.SelfHostedSecurePrivilegedInvasiveDebugEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.SelfHostedSecurePrivilegedInvasiveDebugEnabled()</line>
<line>// ========================================================</line>
<line></line>
<line link="AArch32.SelfHostedSecurePrivilegedInvasiveDebugEnabled.0" hover="function: boolean AArch32.SelfHostedSecurePrivilegedInvasiveDebugEnabled()" conts="AArch32.SelfHostedSecurePrivilegedInvasiveDebugEnabled">boolean <anchor link="AArch32.SelfHostedSecurePrivilegedInvasiveDebugEnabled.0" hover="function: boolean AArch32.SelfHostedSecurePrivilegedInvasiveDebugEnabled()">AArch32.SelfHostedSecurePrivilegedInvasiveDebugEnabled</anchor>()</line>
<line>    // The definition of this function is IMPLEMENTATION DEFINED.</line>
<line>    // In the recommended interface, AArch32.SelfHostedSecurePrivilegedInvasiveDebugEnabled returns</line>
<line>    // the state of the (DBGEN AND SPIDEN) signal.</line>
<line>    if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.NonSecureOnlyImplementation.0" file="shared_pseudocode.xml" hover="function: boolean NonSecureOnlyImplementation()">NonSecureOnlyImplementation</a>() then return FALSE;</line>
<line>    return DBGEN == HIGH &amp;&amp; SPIDEN == HIGH;</line>
</pstext>
    </ps>
    <ps name="aarch32/debug/breakpoint/AArch32.BreakpointMatch" mylink="aarch32.debug.breakpoint.AArch32.BreakpointMatch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.BreakpointMatch()</line>
<line>// =========================</line>
<line>// Breakpoint matching in an AArch32 translation regime.</line>
<line></line>
<line link="AArch32.BreakpointMatch.4" hover="function: (boolean,boolean) AArch32.BreakpointMatch(integer n, bits(32) vaddress, AccessDescriptor accdesc, integer size)" conts="AArch32.BreakpointMatch">(boolean,boolean) <anchor link="AArch32.BreakpointMatch.4" hover="function: (boolean,boolean) AArch32.BreakpointMatch(integer n, bits(32) vaddress, AccessDescriptor accdesc, integer size)">AArch32.BreakpointMatch</anchor>(integer n, bits(32) vaddress, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc,</line>
<line>                                          integer size)</line>
<line>    assert <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>());</line>
<line>    assert n &lt; <a link="impl-shared.NumBreakpointsImplemented.0" file="shared_pseudocode.xml" hover="function: integer NumBreakpointsImplemented()">NumBreakpointsImplemented</a>();</line>
<line></line>
<line>    enabled    = DBGBCR[n].E == '1';</line>
<line>    isbreakpnt = TRUE;</line>
<line>    linked     = DBGBCR[n].BT IN {'0x01'};</line>
<line>    linked_to  = FALSE;</line>
<line></line>
<line>    state_match = <a link="AArch32.StateMatch.7" file="shared_pseudocode.xml" hover="function: boolean AArch32.StateMatch(bits(2) ssc_in,  bit hmc_in, bits(2) pxc_in, boolean linked_in, bits(4) lbn, boolean isbreakpnt, AccessDescriptor accdesc)">AArch32.StateMatch</a>(DBGBCR[n].SSC, DBGBCR[n].HMC, DBGBCR[n].PMC,</line>
<line>                                     linked, DBGBCR[n].LBN, isbreakpnt,  accdesc);</line>
<line>    (value_match, value_mismatch) = <a link="AArch32.BreakpointValueMatch.3" file="shared_pseudocode.xml" hover="function: (boolean, boolean) AArch32.BreakpointValueMatch(integer n_in, bits(32) vaddress, boolean linked_to)">AArch32.BreakpointValueMatch</a>(n, vaddress, linked_to);</line>
<line></line>
<line>    if size == 4 then                    // Check second halfword</line>
<line>        // If the breakpoint address and BAS of an Address breakpoint match the address of the</line>
<line>        // second halfword of an instruction, but not the address of the first halfword, it is</line>
<line>        // CONSTRAINED UNPREDICTABLE whether or not this breakpoint generates a Breakpoint debug</line>
<line>        // event.</line>
<line>        (match_i, mismatch_i) = <a link="AArch32.BreakpointValueMatch.3" file="shared_pseudocode.xml" hover="function: (boolean, boolean) AArch32.BreakpointValueMatch(integer n_in, bits(32) vaddress, boolean linked_to)">AArch32.BreakpointValueMatch</a>(n, vaddress + 2, linked_to);</line>
<line></line>
<line>        if !value_match &amp;&amp; match_i then</line>
<line>            value_match = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_BPMATCHHALF" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BPMATCHHALF</a>);</line>
<line></line>
<line>        if value_mismatch &amp;&amp; !mismatch_i then</line>
<line>            value_mismatch = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_BPMISMATCHHALF" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BPMISMATCHHALF</a>);</line>
<line></line>
<line>    if vaddress&lt;1&gt; == '1' &amp;&amp; DBGBCR[n].BAS == '1111' then</line>
<line>        // The above notwithstanding, if DBGBCR[n].BAS == '1111', then it is CONSTRAINED</line>
<line>        // UNPREDICTABLE whether or not a Breakpoint debug event is generated for an instruction</line>
<line>        // at the address DBGBVR[n]+2.</line>
<line>        if value_match then</line>
<line>            value_match = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_BPMATCHHALF" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BPMATCHHALF</a>);</line>
<line></line>
<line>        if !value_mismatch then</line>
<line>            value_mismatch = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_BPMISMATCHHALF" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BPMISMATCHHALF</a>);</line>
<line></line>
<line>    match    = value_match &amp;&amp; state_match &amp;&amp; enabled;</line>
<line>    mismatch = value_mismatch &amp;&amp; state_match &amp;&amp; enabled;</line>
<line></line>
<line>    return (match, mismatch);</line>
</pstext>
    </ps>
    <ps name="aarch32/debug/breakpoint/AArch32.BreakpointValueMatch" mylink="aarch32.debug.breakpoint.AArch32.BreakpointValueMatch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.BreakpointValueMatch()</line>
<line>// ==============================</line>
<line>// The first result is whether an Address Match or Context breakpoint is programmed on the</line>
<line>// instruction at "address". The second result is whether an Address Mismatch breakpoint is</line>
<line>// programmed on the instruction, that is, whether the instruction should be stepped.</line>
<line></line>
<line link="AArch32.BreakpointValueMatch.3" hover="function: (boolean, boolean) AArch32.BreakpointValueMatch(integer n_in, bits(32) vaddress, boolean linked_to)" conts="AArch32.BreakpointValueMatch">(boolean, boolean) <anchor link="AArch32.BreakpointValueMatch.3" hover="function: (boolean, boolean) AArch32.BreakpointValueMatch(integer n_in, bits(32) vaddress, boolean linked_to)">AArch32.BreakpointValueMatch</anchor>(integer n_in, bits(32) vaddress, boolean linked_to)</line>
<line></line>
<line>    // "n" is the identity of the breakpoint unit to match against.</line>
<line>    // "vaddress" is the current instruction address, ignored if linked_to is TRUE and for Context</line>
<line>    //   matching breakpoints.</line>
<line>    // "linked_to" is TRUE if this is a call from StateMatch for linking.</line>
<line>    integer n = n_in;</line>
<line></line>
<line>    // If a non-existent breakpoint then it is CONSTRAINED UNPREDICTABLE whether this gives</line>
<line>    // no match or the breakpoint is mapped to another UNKNOWN implemented breakpoint.</line>
<line>    if n &gt;= <a link="impl-shared.NumBreakpointsImplemented.0" file="shared_pseudocode.xml" hover="function: integer NumBreakpointsImplemented()">NumBreakpointsImplemented</a>() then</line>
<line>        <a link="Constraint" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint</a> c;</line>
<line>        (c, n) = <a link="impl-shared.ConstrainUnpredictableInteger.3" file="shared_pseudocode.xml" hover="function: (Constraint,integer) ConstrainUnpredictableInteger(integer low, integer high, Unpredictable which)">ConstrainUnpredictableInteger</a>(0, <a link="impl-shared.NumBreakpointsImplemented.0" file="shared_pseudocode.xml" hover="function: integer NumBreakpointsImplemented()">NumBreakpointsImplemented</a>() - 1,</line>
<line>                                               <a link="Unpredictable_BPNOTIMPL" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BPNOTIMPL</a>);</line>
<line>        assert c IN {<a link="Constraint_DISABLED" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_DISABLED</a>, <a link="Constraint_UNKNOWN" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNKNOWN</a>};</line>
<line>        if c == <a link="Constraint_DISABLED" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_DISABLED</a> then return (FALSE, FALSE);</line>
<line></line>
<line>    // If this breakpoint is not enabled, it cannot generate a match. (This could also happen on a</line>
<line>    // call from StateMatch for linking).</line>
<line>    if DBGBCR[n].E == '0' then return (FALSE, FALSE);</line>
<line></line>
<line>    context_aware = (n &gt;= (<a link="impl-shared.NumBreakpointsImplemented.0" file="shared_pseudocode.xml" hover="function: integer NumBreakpointsImplemented()">NumBreakpointsImplemented</a>() - <a link="impl-shared.NumContextAwareBreakpointsImplemented.0" file="shared_pseudocode.xml" hover="function: integer NumContextAwareBreakpointsImplemented()">NumContextAwareBreakpointsImplemented</a>()));</line>
<line></line>
<line>    // If BT is set to a reserved type, behaves either as disabled or as a not-reserved type.</line>
<line>    dbgtype = DBGBCR[n].BT;</line>
<line></line>
<line>    if ((dbgtype IN {'011x','11xx'} &amp;&amp; !<a link="impl-shared.HaveVirtHostExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</a>() &amp;&amp; !<a link="impl-shared.HaveV82Debug.0" file="shared_pseudocode.xml" hover="function: boolean HaveV82Debug()">HaveV82Debug</a>()) || // Context matching</line>
<line>          (dbgtype IN {'010x'} &amp;&amp; <a link="impl-shared.HaltOnBreakpointOrWatchpoint.0" file="shared_pseudocode.xml" hover="function: boolean HaltOnBreakpointOrWatchpoint()">HaltOnBreakpointOrWatchpoint</a>()) ||             // Address mismatch</line>
<line>          (!(dbgtype IN {'0x0x'}) &amp;&amp; !context_aware) ||                          // Context matching</line>
<line>          (dbgtype IN {'1xxx'} &amp;&amp; !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>))) then                            // EL2 extension</line>
<line>        <a link="Constraint" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint</a> c;</line>
<line>        (c, dbgtype) = <a link="impl-shared.ConstrainUnpredictableBits.2" file="shared_pseudocode.xml" hover="function: (Constraint,bits(width)) ConstrainUnpredictableBits(Unpredictable which, integer width)">ConstrainUnpredictableBits</a>(<a link="Unpredictable_RESBPTYPE" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESBPTYPE</a>, 4);</line>
<line>        assert c IN {<a link="Constraint_DISABLED" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_DISABLED</a>, <a link="Constraint_UNKNOWN" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNKNOWN</a>};</line>
<line>        if c == <a link="Constraint_DISABLED" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_DISABLED</a> then return (FALSE, FALSE);</line>
<line>        // Otherwise the value returned by ConstrainUnpredictableBits must be a not-reserved value</line>
<line></line>
<line>    // Determine what to compare against.</line>
<line>    match_addr = (dbgtype IN {'0x0x'});</line>
<line>    mismatch   = (dbgtype IN {'010x'});</line>
<line>    match_vmid = (dbgtype IN {'10xx'});</line>
<line>    match_cid1 = (dbgtype IN {'xx1x'});</line>
<line>    match_cid2 = (dbgtype IN {'11xx'});</line>
<line>    linked     = (dbgtype IN {'xxx1'});</line>
<line></line>
<line>    // If this is a call from StateMatch, return FALSE if the breakpoint is not programmed for a</line>
<line>    // VMID and/or context ID match, of if not context-aware. The above assertions mean that the</line>
<line>    // code can just test for match_addr == TRUE to confirm all these things.</line>
<line>    if linked_to &amp;&amp; (!linked || match_addr) then return (FALSE, FALSE);</line>
<line></line>
<line>    // If called from BreakpointMatch return FALSE for Linked context ID and/or VMID matches.</line>
<line>    if !linked_to &amp;&amp; linked &amp;&amp; !match_addr then return (FALSE, FALSE);</line>
<line></line>
<line>    boolean bvr_match  = FALSE;</line>
<line>    boolean bxvr_match = FALSE;</line>
<line></line>
<line>    // Do the comparison.</line>
<line>    if match_addr then</line>
<line>        integer byte = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(vaddress&lt;1:0&gt;);</line>
<line>        assert byte IN {0,2};                     // "vaddress" is halfword aligned</line>
<line></line>
<line>        boolean byte_select_match = (DBGBCR[n].BAS&lt;byte&gt; == '1');</line>
<line>        integer top = 31;</line>
<line>        bvr_match = (vaddress&lt;top:2&gt; == DBGBVR[n]&lt;top:2&gt;) &amp;&amp; byte_select_match;</line>
<line></line>
<line>    elsif match_cid1 then</line>
<line>        bvr_match = (PSTATE.EL != <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> &amp;&amp; CONTEXTIDR == DBGBVR[n]&lt;31:0&gt;);</line>
<line></line>
<line>    if match_vmid then</line>
<line>        bits(16) vmid;</line>
<line>        bits(16) bvr_vmid;</line>
<line></line>
<line>        if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>            vmid = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(VTTBR.VMID, 16);</line>
<line>            bvr_vmid = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(DBGBXVR[n]&lt;7:0&gt;, 16);</line>
<line>        elsif !<a link="impl-shared.Have16bitVMID.0" file="shared_pseudocode.xml" hover="function: boolean Have16bitVMID()">Have16bitVMID</a>() || VTCR_EL2.VS == '0' then</line>
<line>            vmid = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(VTTBR_EL2.VMID&lt;7:0&gt;, 16);</line>
<line>            bvr_vmid = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(DBGBXVR[n]&lt;7:0&gt;, 16);</line>
<line>        else</line>
<line>            vmid = VTTBR_EL2.VMID;</line>
<line>            bvr_vmid = DBGBXVR[n]&lt;15:0&gt;;</line>
<line></line>
<line>        bxvr_match = (PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; vmid == bvr_vmid);</line>
<line></line>
<line>    elsif match_cid2 then</line>
<line>        bxvr_match = (PSTATE.EL != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp;</line>
<line>                      DBGBXVR[n]&lt;31:0&gt; == CONTEXTIDR_EL2&lt;31:0&gt;);</line>
<line></line>
<line>    bvr_match_valid  = (match_addr || match_cid1);</line>
<line>    bxvr_match_valid = (match_vmid || match_cid2);</line>
<line></line>
<line>    match = (!bxvr_match_valid || bxvr_match) &amp;&amp; (!bvr_match_valid || bvr_match);</line>
<line></line>
<line>    return (match &amp;&amp; !mismatch, !match &amp;&amp; mismatch);</line>
</pstext>
    </ps>
    <ps name="aarch32/debug/breakpoint/AArch32.StateMatch" mylink="aarch32.debug.breakpoint.AArch32.StateMatch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.StateMatch()</line>
<line>// ====================</line>
<line>// Determine whether a breakpoint or watchpoint is enabled in the current mode and state.</line>
<line></line>
<line link="AArch32.StateMatch.7" hover="function: boolean AArch32.StateMatch(bits(2) ssc_in,  bit hmc_in, bits(2) pxc_in, boolean linked_in, bits(4) lbn, boolean isbreakpnt, AccessDescriptor accdesc)" conts="AArch32.StateMatch">boolean <anchor link="AArch32.StateMatch.7" hover="function: boolean AArch32.StateMatch(bits(2) ssc_in,  bit hmc_in, bits(2) pxc_in, boolean linked_in, bits(4) lbn, boolean isbreakpnt, AccessDescriptor accdesc)">AArch32.StateMatch</anchor>(bits(2) ssc_in,  bit hmc_in, bits(2) pxc_in, boolean linked_in,</line>
<line>                           bits(4) lbn, boolean isbreakpnt, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line></line>
<line>    // "ssc_in","hmc_in","pxc_in" are the control fields from the DBGBCR[n] or DBGWCR[n] register.</line>
<line>    // "linked_in" is TRUE if this is a linked breakpoint/watchpoint type.</line>
<line>    // "lbn" is the linked breakpoint number from the DBGBCR[n] or DBGWCR[n] register.</line>
<line>    // "isbreakpnt" is TRUE for breakpoints, FALSE for watchpoints.</line>
<line>    // "accdesc" describes the properties of the access being matched.</line>
<line>    bits(2) ssc    = ssc_in;</line>
<line>    bit hmc        = hmc_in;</line>
<line>    bits(2) pxc    = pxc_in;</line>
<line>    boolean linked = linked_in;</line>
<line></line>
<line>    // If parameters are set to a reserved type, behaves as either disabled or a defined type</line>
<line>    <a link="Constraint" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint</a> c;</line>
<line>    // SSCE value discarded as there is no SSCE bit in AArch32.</line>
<line>    (c, ssc, -, hmc, pxc) = <a link="impl-shared.CheckValidStateMatch.5" file="shared_pseudocode.xml" hover="function: (Constraint, bits(2), bit, bit, bits(2)) CheckValidStateMatch(bits(2) ssc_in, bit ssce_in, bit hmc_in, bits(2) pxc_in, boolean isbreakpnt)">CheckValidStateMatch</a>(ssc, '0', hmc, pxc, isbreakpnt);</line>
<line>    if c == <a link="Constraint_DISABLED" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_DISABLED</a> then return FALSE;</line>
<line>    // Otherwise the hmc,ssc,pxc values are either valid or the values returned by</line>
<line>    // CheckValidStateMatch are valid.</line>
<line></line>
<line>    pl2_match = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; ((hmc == '1' &amp;&amp; (ssc:pxc != '1000')) || ssc == '11');</line>
<line>    pl1_match = pxc&lt;0&gt; == '1';</line>
<line>    pl0_match = pxc&lt;1&gt; == '1';</line>
<line>    ssu_match = isbreakpnt &amp;&amp; hmc == '0' &amp;&amp; pxc == '00' &amp;&amp; ssc != '11';</line>
<line></line>
<line>    boolean priv_match;</line>
<line>    if ssu_match then</line>
<line>        priv_match = PSTATE.M IN {<a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a>,<a link="M32_Svc" file="shared_pseudocode.xml" hover="constant bits(5) M32_Svc = '10011'">M32_Svc</a>,<a link="M32_System" file="shared_pseudocode.xml" hover="constant bits(5) M32_System = '11111'">M32_System</a>};</line>
<line>    else</line>
<line>        case accdesc.el of</line>
<line>            when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> priv_match = pl1_match;           // EL3 and EL1 are both PL1</line>
<line>            when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> priv_match = pl2_match;</line>
<line>            when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> priv_match = pl1_match;</line>
<line>            when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> priv_match = pl0_match;</line>
<line></line>
<line>    // Security state match</line>
<line>    boolean ss_match;</line>
<line>    case ssc of</line>
<line>        when '00' ss_match = TRUE;                                     // Both</line>
<line>        when '01' ss_match = accdesc.ss == <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a>;               // Non-secure only</line>
<line>        when '10' ss_match = accdesc.ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>;                  // Secure only</line>
<line>        when '11' ss_match = (hmc == '1' || accdesc.ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>);  // HMC=1 -&gt; Both,</line>
<line>                                                                       // HMC=0 -&gt; Secure only</line>
<line></line>
<line>    boolean linked_match = FALSE;</line>
<line></line>
<line>    if linked then</line>
<line>        // "lbn" must be an enabled context-aware breakpoint unit. If it is not context-aware then</line>
<line>        // it is CONSTRAINED UNPREDICTABLE whether this gives no match, gives a match without</line>
<line>        // linking, or lbn is mapped to some UNKNOWN breakpoint that is context-aware.</line>
<line>        integer int_lbn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(lbn);</line>
<line>        first_ctx_cmp = <a link="impl-shared.NumBreakpointsImplemented.0" file="shared_pseudocode.xml" hover="function: integer NumBreakpointsImplemented()">NumBreakpointsImplemented</a>() - <a link="impl-shared.NumContextAwareBreakpointsImplemented.0" file="shared_pseudocode.xml" hover="function: integer NumContextAwareBreakpointsImplemented()">NumContextAwareBreakpointsImplemented</a>();</line>
<line>        last_ctx_cmp = <a link="impl-shared.NumBreakpointsImplemented.0" file="shared_pseudocode.xml" hover="function: integer NumBreakpointsImplemented()">NumBreakpointsImplemented</a>() - 1;</line>
<line></line>
<line>        if (int_lbn &lt; first_ctx_cmp || int_lbn &gt; last_ctx_cmp) then</line>
<line>            (c, int_lbn) = <a link="impl-shared.ConstrainUnpredictableInteger.3" file="shared_pseudocode.xml" hover="function: (Constraint,integer) ConstrainUnpredictableInteger(integer low, integer high, Unpredictable which)">ConstrainUnpredictableInteger</a>(first_ctx_cmp, last_ctx_cmp,</line>
<line>                                                         <a link="Unpredictable_BPNOTCTXCMP" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BPNOTCTXCMP</a>);</line>
<line>            assert c IN {<a link="Constraint_DISABLED" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_DISABLED</a>, <a link="Constraint_NONE" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NONE</a>, <a link="Constraint_UNKNOWN" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNKNOWN</a>};</line>
<line></line>
<line>            case c of</line>
<line>                when <a link="Constraint_DISABLED" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_DISABLED</a>  return FALSE;      // Disabled</line>
<line>                when <a link="Constraint_NONE" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NONE</a>      linked = FALSE;    // No linking</line>
<line>                // Otherwise ConstrainUnpredictableInteger returned a context-aware breakpoint</line>
<line></line>
<line>        vaddress  = bits(32) UNKNOWN;</line>
<line>        linked_to = TRUE;</line>
<line>        (linked_match,-) = <a link="AArch32.BreakpointValueMatch.3" file="shared_pseudocode.xml" hover="function: (boolean, boolean) AArch32.BreakpointValueMatch(integer n_in, bits(32) vaddress, boolean linked_to)">AArch32.BreakpointValueMatch</a>(int_lbn, vaddress, linked_to);</line>
<line></line>
<line>    return priv_match &amp;&amp; ss_match &amp;&amp; (!linked || linked_match);</line>
</pstext>
    </ps>
    <ps name="aarch32/debug/enables/AArch32.GenerateDebugExceptions" mylink="aarch32.debug.enables.AArch32.GenerateDebugExceptions" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.GenerateDebugExceptions()</line>
<line>// =================================</line>
<line></line>
<line link="AArch32.GenerateDebugExceptions.0" hover="function: boolean AArch32.GenerateDebugExceptions()" conts="AArch32.GenerateDebugExceptions">boolean <anchor link="AArch32.GenerateDebugExceptions.0" hover="function: boolean AArch32.GenerateDebugExceptions()">AArch32.GenerateDebugExceptions</anchor>()</line>
<line>    ss = <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>();</line>
<line>    return <a link="AArch32.GenerateDebugExceptionsFrom.2" file="shared_pseudocode.xml" hover="function: boolean AArch32.GenerateDebugExceptionsFrom(bits(2) from_el, SecurityState from_state)">AArch32.GenerateDebugExceptionsFrom</a>(PSTATE.EL, ss);</line>
</pstext>
    </ps>
    <ps name="aarch32/debug/enables/AArch32.GenerateDebugExceptionsFrom" mylink="aarch32.debug.enables.AArch32.GenerateDebugExceptionsFrom" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.GenerateDebugExceptionsFrom()</line>
<line>// =====================================</line>
<line></line>
<line link="AArch32.GenerateDebugExceptionsFrom.2" hover="function: boolean AArch32.GenerateDebugExceptionsFrom(bits(2) from_el, SecurityState from_state)" conts="AArch32.GenerateDebugExceptionsFrom">boolean <anchor link="AArch32.GenerateDebugExceptionsFrom.2" hover="function: boolean AArch32.GenerateDebugExceptionsFrom(bits(2) from_el, SecurityState from_state)">AArch32.GenerateDebugExceptionsFrom</anchor>(bits(2) from_el, <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> from_state)</line>
<line></line>
<line>    if !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="impl-shared.DebugTargetFrom.1" file="shared_pseudocode.xml" hover="function: bits(2) DebugTargetFrom(SecurityState from_state)">DebugTargetFrom</a>(from_state)) then</line>
<line>        mask = '0';    // No PSTATE.D in AArch32 state</line>
<line>        return <a link="AArch64.GenerateDebugExceptionsFrom.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.GenerateDebugExceptionsFrom(bits(2) from_el, SecurityState from_state, bit mask)">AArch64.GenerateDebugExceptionsFrom</a>(from_el, from_state, mask);</line>
<line></line>
<line>    if DBGOSLSR.OSLK == '1' || <a link="impl-shared.DoubleLockStatus.0" file="shared_pseudocode.xml" hover="function: boolean DoubleLockStatus()">DoubleLockStatus</a>() || <a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() then</line>
<line>        return FALSE;</line>
<line></line>
<line>    boolean enabled;</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; from_state == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>        assert from_el != <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;    // Secure EL2 always uses AArch64</line>
<line>        if <a link="impl-shared.IsSecureEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsSecureEL2Enabled()">IsSecureEL2Enabled</a>() then</line>
<line>            // Implies that EL3 and EL2 both using AArch64</line>
<line>            enabled = MDCR_EL3.SDD == '0';</line>
<line>        else</line>
<line>            spd = if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then SDCR.SPD else MDCR_EL3.SPD32;</line>
<line>            if spd&lt;1&gt; == '1' then</line>
<line>                enabled = spd&lt;0&gt; == '1';</line>
<line>            else</line>
<line>                // SPD == 0b01 is reserved, but behaves the same as 0b00.</line>
<line>                enabled = <a link="AArch32.SelfHostedSecurePrivilegedInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean AArch32.SelfHostedSecurePrivilegedInvasiveDebugEnabled()">AArch32.SelfHostedSecurePrivilegedInvasiveDebugEnabled</a>();</line>
<line>        if from_el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then enabled = enabled || SDER.SUIDEN == '1';</line>
<line>    else</line>
<line>        enabled = from_el != <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line></line>
<line>    return enabled;</line>
</pstext>
    </ps>
    <ps name="aarch32/debug/pmu/AArch32.ClearEventCounters" mylink="aarch32.debug.pmu.AArch32.ClearEventCounters" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.ClearEventCounters()</line>
<line>// ============================</line>
<line>// Zero all the event counters.</line>
<line></line>
<line link="AArch32.ClearEventCounters.0" hover="function: AArch32.ClearEventCounters()" conts="AArch32.ClearEventCounters"><anchor link="AArch32.ClearEventCounters.0" hover="function: AArch32.ClearEventCounters()">AArch32.ClearEventCounters</anchor>()</line>
<line>    if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then</line>
<line>        // Force the counter to be cleared as a 64-bit counter.</line>
<line>        <a link="AArch64.ClearEventCounters.0" file="shared_pseudocode.xml" hover="function: AArch64.ClearEventCounters()">AArch64.ClearEventCounters</a>();</line>
<line>        return;</line>
<line></line>
<line>    integer counters = <a link="AArch32.GetNumEventCountersAccessible.0" file="shared_pseudocode.xml" hover="function: integer AArch32.GetNumEventCountersAccessible()">AArch32.GetNumEventCountersAccessible</a>();</line>
<line>    if counters != 0 then</line>
<line>        for idx = 0 to counters - 1</line>
<line>            PMEVCNTR[idx] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32);</line>
</pstext>
    </ps>
    <ps name="aarch32/debug/pmu/AArch32.GetNumEventCountersAccessible" mylink="aarch32.debug.pmu.AArch32.GetNumEventCountersAccessible" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.GetNumEventCountersAccessible()</line>
<line>// =======================================</line>
<line>// Return the number of event counters that can be accessed at the current Exception level.</line>
<line></line>
<line link="AArch32.GetNumEventCountersAccessible.0" hover="function: integer AArch32.GetNumEventCountersAccessible()" conts="AArch32.GetNumEventCountersAccessible">integer <anchor link="AArch32.GetNumEventCountersAccessible.0" hover="function: integer AArch32.GetNumEventCountersAccessible()">AArch32.GetNumEventCountersAccessible</anchor>()</line>
<line>    integer n;</line>
<line>    integer total_counters = <a link="impl-shared.GetNumEventCounters.0" file="shared_pseudocode.xml" hover="function: integer GetNumEventCounters()">GetNumEventCounters</a>();</line>
<line>    // Software can reserve some counters for EL2</line>
<line>    if PSTATE.EL IN {<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(if !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then MDCR_EL2.HPMN else HDCR.HPMN);</line>
<line>        if n &gt; total_counters || (!<a link="impl-shared.HaveFeatHPMN0.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatHPMN0()">HaveFeatHPMN0</a>() &amp;&amp; n == 0) then</line>
<line>            (-, n) = <a link="impl-shared.ConstrainUnpredictableInteger.3" file="shared_pseudocode.xml" hover="function: (Constraint,integer) ConstrainUnpredictableInteger(integer low, integer high, Unpredictable which)">ConstrainUnpredictableInteger</a>(0, total_counters,</line>
<line>                                                   <a link="Unpredictable_PMUEVENTCOUNTER" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_PMUEVENTCOUNTER</a>);</line>
<line>    else</line>
<line>        n = total_counters;</line>
<line></line>
<line>    return n;</line>
</pstext>
    </ps>
    <ps name="aarch32/debug/pmu/AArch32.IncrementCycleCounter" mylink="aarch32.debug.pmu.AArch32.IncrementCycleCounter" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.IncrementCycleCounter()</line>
<line>// ===============================</line>
<line>// Increment the cycle counter and possibly set overflow bits.</line>
<line></line>
<line link="AArch32.IncrementCycleCounter.0" hover="function: AArch32.IncrementCycleCounter()" conts="AArch32.IncrementCycleCounter"><anchor link="AArch32.IncrementCycleCounter.0" hover="function: AArch32.IncrementCycleCounter()">AArch32.IncrementCycleCounter</anchor>()</line>
<line>    if (<a link="impl-shared.CountPMUEvents.1" file="shared_pseudocode.xml" hover="function: boolean CountPMUEvents(integer idx)">CountPMUEvents</a>(<a link="CYCLE_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer CYCLE_COUNTER_ID = 31">CYCLE_COUNTER_ID</a>) &amp;&amp;</line>
<line>        (PMCR.LC == '1' || PMCR.D == '0' || <a link="impl-shared.HasElapsed64Cycles.0" file="shared_pseudocode.xml" hover="function: boolean HasElapsed64Cycles()">HasElapsed64Cycles</a>())) then</line>
<line>        integer old_value = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PMCCNTR);</line>
<line>        integer new_value = old_value + 1;</line>
<line>        PMCCNTR = new_value&lt;63:0&gt;;</line>
<line></line>
<line>        integer ovflw = if PMCR.LC == '1' then 64 else 32;</line>
<line></line>
<line>        if old_value&lt;64:ovflw&gt; != new_value&lt;64:ovflw&gt; then</line>
<line>            PMOVSSET.C = '1';</line>
<line>            PMOVSR.C = '1';</line>
</pstext>
    </ps>
    <ps name="aarch32/debug/pmu/AArch32.IncrementEventCounter" mylink="aarch32.debug.pmu.AArch32.IncrementEventCounter" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.IncrementEventCounter()</line>
<line>// ===============================</line>
<line>// Increment the specified event counter by the specified amount.</line>
<line></line>
<line link="AArch32.IncrementEventCounter.2" hover="function: AArch32.IncrementEventCounter(integer idx, integer increment)" conts="AArch32.IncrementEventCounter"><anchor link="AArch32.IncrementEventCounter.2" hover="function: AArch32.IncrementEventCounter(integer idx, integer increment)">AArch32.IncrementEventCounter</anchor>(integer idx, integer increment)</line>
<line>    if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then</line>
<line>        // Force the counter to be incremented as a 64-bit counter.</line>
<line>        <a link="AArch64.IncrementEventCounter.2" file="shared_pseudocode.xml" hover="function: AArch64.IncrementEventCounter(integer idx, integer increment)">AArch64.IncrementEventCounter</a>(idx, increment);</line>
<line>        return;</line>
<line></line>
<line>    // In this model, event counters in an AArch32-only implementation are 32 bits and</line>
<line>    // the LP bits are RES0 in this model, even if FEAT_PMUv3p5 is implemented.</line>
<line>    integer old_value;</line>
<line>    integer new_value;</line>
<line>    integer ovflw;</line>
<line>    bit lp;</line>
<line>    old_value = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PMEVCNTR[idx]);</line>
<line>    new_value = old_value + <a link="impl-shared.PMUCountValue.2" file="shared_pseudocode.xml" hover="function: integer PMUCountValue(integer n, integer Vb)">PMUCountValue</a>(idx, increment);</line>
<line></line>
<line>    PMEVCNTR[idx] = new_value&lt;31:0&gt;;</line>
<line>    ovflw = 32;</line>
<line></line>
<line>    if old_value&lt;64:ovflw&gt; != new_value&lt;64:ovflw&gt; then</line>
<line>        PMOVSSET&lt;idx&gt; = '1';</line>
<line>        PMOVSR&lt;idx&gt; = '1';</line>
<line>        // Check for the CHAIN event from an even counter</line>
<line>        if idx&lt;0&gt; == '0' &amp;&amp; idx + 1 &lt; <a link="impl-shared.GetNumEventCounters.0" file="shared_pseudocode.xml" hover="function: integer GetNumEventCounters()">GetNumEventCounters</a>() then</line>
<line>            <a link="impl-shared.PMUEvent.3" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event, integer increment, integer idx)">PMUEvent</a>(PMU_EVENT_CHAIN, 1, idx + 1);</line>
</pstext>
    </ps>
    <ps name="aarch32/debug/pmu/AArch32.PMUCycle" mylink="aarch32.debug.pmu.AArch32.PMUCycle" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.PMUCycle()</line>
<line>// ==================</line>
<line>// Called at the end of each cycle to increment event counters and</line>
<line>// check for PMU overflow. In pseudocode, a cycle ends after the</line>
<line>// execution of the operational pseudocode.</line>
<line></line>
<line link="AArch32.PMUCycle.0" hover="function: AArch32.PMUCycle()" conts="AArch32.PMUCycle"><anchor link="AArch32.PMUCycle.0" hover="function: AArch32.PMUCycle()">AArch32.PMUCycle</anchor>()</line>
<line>    if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then</line>
<line>        <a link="AArch64.PMUCycle.0" file="shared_pseudocode.xml" hover="function: AArch64.PMUCycle()">AArch64.PMUCycle</a>();</line>
<line>        return;</line>
<line></line>
<line>    if !<a link="impl-shared.HavePMUv3.0" file="shared_pseudocode.xml" hover="function: boolean HavePMUv3()">HavePMUv3</a>() then</line>
<line>        return;</line>
<line></line>
<line>    <a link="impl-shared.PMUEvent.1" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event)">PMUEvent</a>(PMU_EVENT_CPU_CYCLES);</line>
<line></line>
<line>    integer counters = <a link="impl-shared.GetNumEventCounters.0" file="shared_pseudocode.xml" hover="function: integer GetNumEventCounters()">GetNumEventCounters</a>();</line>
<line>    if counters != 0 then</line>
<line>        for idx = 0 to counters - 1</line>
<line>            if <a link="impl-shared.CountPMUEvents.1" file="shared_pseudocode.xml" hover="function: boolean CountPMUEvents(integer idx)">CountPMUEvents</a>(idx) then</line>
<line>                integer accumulated = PMUEventAccumulator[idx];</line>
<line>                <a link="AArch32.IncrementEventCounter.2" file="shared_pseudocode.xml" hover="function: AArch32.IncrementEventCounter(integer idx, integer increment)">AArch32.IncrementEventCounter</a>(idx, accumulated);</line>
<line>            PMUEventAccumulator[idx] = 0;</line>
<line></line>
<line>    <a link="AArch32.IncrementCycleCounter.0" file="shared_pseudocode.xml" hover="function: AArch32.IncrementCycleCounter()">AArch32.IncrementCycleCounter</a>();</line>
<line>    <a link="impl-shared.CheckForPMUOverflow.0" file="shared_pseudocode.xml" hover="function: CheckForPMUOverflow()">CheckForPMUOverflow</a>();</line>
</pstext>
    </ps>
    <ps name="aarch32/debug/pmu/AArch32.PMUSwIncrement" mylink="aarch32.debug.pmu.AArch32.PMUSwIncrement" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.PMUSwIncrement()</line>
<line>// ========================</line>
<line>// Generate PMU Events on a write to PMSWINC.</line>
<line></line>
<line link="AArch32.PMUSwIncrement.1" hover="function: AArch32.PMUSwIncrement(bits(32) sw_incr)" conts="AArch32.PMUSwIncrement"><anchor link="AArch32.PMUSwIncrement.1" hover="function: AArch32.PMUSwIncrement(bits(32) sw_incr)">AArch32.PMUSwIncrement</anchor>(bits(32) sw_incr)</line>
<line>    integer counters = <a link="AArch32.GetNumEventCountersAccessible.0" file="shared_pseudocode.xml" hover="function: integer AArch32.GetNumEventCountersAccessible()">AArch32.GetNumEventCountersAccessible</a>();</line>
<line>    if counters != 0 then</line>
<line>        for idx = 0 to counters - 1</line>
<line>            if sw_incr&lt;idx&gt; == '1' then</line>
<line>                <a link="impl-shared.PMUEvent.3" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event, integer increment, integer idx)">PMUEvent</a>(PMU_EVENT_SW_INCR, 1, idx);</line>
</pstext>
    </ps>
    <ps name="aarch32/debug/takeexceptiondbg/AArch32.EnterHypModeInDebugState" mylink="aarch32.debug.takeexceptiondbg.AArch32.EnterHypModeInDebugState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.EnterHypModeInDebugState()</line>
<line>// ==================================</line>
<line>// Take an exception in Debug state to Hyp mode.</line>
<line></line>
<line link="AArch32.EnterHypModeInDebugState.1" hover="function: AArch32.EnterHypModeInDebugState(ExceptionRecord exception)" conts="AArch32.EnterHypModeInDebugState"><anchor link="AArch32.EnterHypModeInDebugState.1" hover="function: AArch32.EnterHypModeInDebugState(ExceptionRecord exception)">AArch32.EnterHypModeInDebugState</anchor>(<a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception)</line>
<line>    <a link="impl-shared.SynchronizeContext.0" file="shared_pseudocode.xml" hover="function: SynchronizeContext()">SynchronizeContext</a>();</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() == <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> &amp;&amp; <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line></line>
<line>    <a link="AArch32.ReportHypEntry.1" file="shared_pseudocode.xml" hover="function: AArch32.ReportHypEntry(ExceptionRecord exception)">AArch32.ReportHypEntry</a>(exception);</line>
<line>    <a link="AArch32.WriteMode.1" file="shared_pseudocode.xml" hover="function: AArch32.WriteMode(bits(5) mode)">AArch32.WriteMode</a>(<a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a>);</line>
<line>    <a link="impl-shared.SPSR.write.0" file="shared_pseudocode.xml" hover="accessor: SPSR[] = bits(N) value">SPSR</a>[] = bits(32) UNKNOWN;</line>
<line>    ELR_hyp = bits(32) UNKNOWN;</line>
<line>    // In Debug state, the PE always execute T32 instructions when in AArch32 state, and</line>
<line>    // PSTATE.{SS,A,I,F} are not observable so behave as UNKNOWN.</line>
<line>    PSTATE.T = '1';                             // PSTATE.J is RES0</line>
<line>    PSTATE.&lt;SS,A,I,F&gt; = bits(4) UNKNOWN;</line>
<line>    DLR = bits(32) UNKNOWN;</line>
<line>    DSPSR = bits(32) UNKNOWN;</line>
<line>    PSTATE.E = HSCTLR.EE;</line>
<line>    PSTATE.IL = '0';</line>
<line>    PSTATE.IT = '00000000';</line>
<line>    if <a link="impl-shared.HaveSSBSExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveSSBSExt()">HaveSSBSExt</a>() then PSTATE.SSBS = bit UNKNOWN;</line>
<line>    EDSCR.ERR = '1';</line>
<line>    <a link="impl-shared.UpdateEDSCRFields.0" file="shared_pseudocode.xml" hover="function: UpdateEDSCRFields()">UpdateEDSCRFields</a>();</line>
<line></line>
<line>    <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
</pstext>
    </ps>
    <ps name="aarch32/debug/takeexceptiondbg/AArch32.EnterModeInDebugState" mylink="aarch32.debug.takeexceptiondbg.AArch32.EnterModeInDebugState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.EnterModeInDebugState()</line>
<line>// ===============================</line>
<line>// Take an exception in Debug state to a mode other than Monitor and Hyp mode.</line>
<line></line>
<line link="AArch32.EnterModeInDebugState.1" hover="function: AArch32.EnterModeInDebugState(bits(5) target_mode)" conts="AArch32.EnterModeInDebugState"><anchor link="AArch32.EnterModeInDebugState.1" hover="function: AArch32.EnterModeInDebugState(bits(5) target_mode)">AArch32.EnterModeInDebugState</anchor>(bits(5) target_mode)</line>
<line>    <a link="impl-shared.SynchronizeContext.0" file="shared_pseudocode.xml" hover="function: SynchronizeContext()">SynchronizeContext</a>();</line>
<line>    assert <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) &amp;&amp; PSTATE.EL != <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line></line>
<line>    if PSTATE.M == <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a> then SCR.NS = '0';</line>
<line>    <a link="AArch32.WriteMode.1" file="shared_pseudocode.xml" hover="function: AArch32.WriteMode(bits(5) mode)">AArch32.WriteMode</a>(target_mode);</line>
<line>    <a link="impl-shared.SPSR.write.0" file="shared_pseudocode.xml" hover="accessor: SPSR[] = bits(N) value">SPSR</a>[] = bits(32) UNKNOWN;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[14] = bits(32) UNKNOWN;</line>
<line>    // In Debug state, the PE always execute T32 instructions when in AArch32 state, and</line>
<line>    // PSTATE.{SS,A,I,F} are not observable so behave as UNKNOWN.</line>
<line>    PSTATE.T = '1';                             // PSTATE.J is RES0</line>
<line>    PSTATE.&lt;SS,A,I,F&gt; = bits(4) UNKNOWN;</line>
<line>    DLR = bits(32) UNKNOWN;</line>
<line>    DSPSR = bits(32) UNKNOWN;</line>
<line>    PSTATE.E = SCTLR.EE;</line>
<line>    PSTATE.IL = '0';</line>
<line>    PSTATE.IT = '00000000';</line>
<line>    if <a link="impl-shared.HavePANExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePANExt()">HavePANExt</a>() &amp;&amp; SCTLR.SPAN == '0' then PSTATE.PAN = '1';</line>
<line>    if <a link="impl-shared.HaveSSBSExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveSSBSExt()">HaveSSBSExt</a>() then PSTATE.SSBS = bit UNKNOWN;</line>
<line>    EDSCR.ERR = '1';</line>
<line>    <a link="impl-shared.UpdateEDSCRFields.0" file="shared_pseudocode.xml" hover="function: UpdateEDSCRFields()">UpdateEDSCRFields</a>();                        // Update EDSCR processor state flags.</line>
<line></line>
<line>    <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
</pstext>
    </ps>
    <ps name="aarch32/debug/takeexceptiondbg/AArch32.EnterMonitorModeInDebugState" mylink="aarch32.debug.takeexceptiondbg.AArch32.EnterMonitorModeInDebugState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.EnterMonitorModeInDebugState()</line>
<line>// ======================================</line>
<line>// Take an exception in Debug state to Monitor mode.</line>
<line></line>
<line link="AArch32.EnterMonitorModeInDebugState.0" hover="function: AArch32.EnterMonitorModeInDebugState()" conts="AArch32.EnterMonitorModeInDebugState"><anchor link="AArch32.EnterMonitorModeInDebugState.0" hover="function: AArch32.EnterMonitorModeInDebugState()">AArch32.EnterMonitorModeInDebugState</anchor>()</line>
<line>    <a link="impl-shared.SynchronizeContext.0" file="shared_pseudocode.xml" hover="function: SynchronizeContext()">SynchronizeContext</a>();</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>    from_secure = <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>;</line>
<line>    if PSTATE.M == <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a> then SCR.NS = '0';</line>
<line>    <a link="AArch32.WriteMode.1" file="shared_pseudocode.xml" hover="function: AArch32.WriteMode(bits(5) mode)">AArch32.WriteMode</a>(<a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a>);</line>
<line>    <a link="impl-shared.SPSR.write.0" file="shared_pseudocode.xml" hover="accessor: SPSR[] = bits(N) value">SPSR</a>[] = bits(32) UNKNOWN;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[14] = bits(32) UNKNOWN;</line>
<line>    // In Debug state, the PE always execute T32 instructions when in AArch32 state, and</line>
<line>    // PSTATE.{SS,A,I,F} are not observable so behave as UNKNOWN.</line>
<line>    PSTATE.T = '1';                             // PSTATE.J is RES0</line>
<line>    PSTATE.&lt;SS,A,I,F&gt; = bits(4) UNKNOWN;</line>
<line>    PSTATE.E = SCTLR.EE;</line>
<line>    PSTATE.IL = '0';</line>
<line>    PSTATE.IT = '00000000';</line>
<line>    if <a link="impl-shared.HavePANExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePANExt()">HavePANExt</a>() then</line>
<line>        if !from_secure then</line>
<line>            PSTATE.PAN = '0';</line>
<line>        elsif SCTLR.SPAN == '0' then</line>
<line>            PSTATE.PAN = '1';</line>
<line>    if <a link="impl-shared.HaveSSBSExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveSSBSExt()">HaveSSBSExt</a>() then PSTATE.SSBS = bit UNKNOWN;</line>
<line>    DLR = bits(32) UNKNOWN;</line>
<line>    DSPSR = bits(32) UNKNOWN;</line>
<line>    EDSCR.ERR = '1';</line>
<line>    <a link="impl-shared.UpdateEDSCRFields.0" file="shared_pseudocode.xml" hover="function: UpdateEDSCRFields()">UpdateEDSCRFields</a>();                        // Update EDSCR processor state flags.</line>
<line></line>
<line>    <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
</pstext>
    </ps>
    <ps name="aarch32/debug/watchpoint/AArch32.WatchpointByteMatch" mylink="aarch32.debug.watchpoint.AArch32.WatchpointByteMatch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.WatchpointByteMatch()</line>
<line>// =============================</line>
<line></line>
<line link="AArch32.WatchpointByteMatch.2" hover="function: boolean AArch32.WatchpointByteMatch(integer n, bits(32) vaddress)" conts="AArch32.WatchpointByteMatch">boolean <anchor link="AArch32.WatchpointByteMatch.2" hover="function: boolean AArch32.WatchpointByteMatch(integer n, bits(32) vaddress)">AArch32.WatchpointByteMatch</anchor>(integer n, bits(32) vaddress)</line>
<line></line>
<line>    integer top = 31;</line>
<line>    bottom = if DBGWVR[n]&lt;2&gt; == '1' then 2 else 3;            // Word or doubleword</line>
<line>    byte_select_match = (DBGWCR[n].BAS&lt;<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(vaddress&lt;bottom-1:0&gt;)&gt; != '0');</line>
<line>    mask = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(DBGWCR[n].MASK);</line>
<line></line>
<line>    // If DBGWCR[n].MASK is non-zero value and DBGWCR[n].BAS is not set to '11111111', or</line>
<line>    // DBGWCR[n].BAS specifies a non-contiguous set of bytes behavior is CONSTRAINED</line>
<line>    // UNPREDICTABLE.</line>
<line>    if mask &gt; 0 &amp;&amp; !<a link="impl-shared.IsOnes.1" file="shared_pseudocode.xml" hover="function: boolean IsOnes(bits(N) x)">IsOnes</a>(DBGWCR[n].BAS) then</line>
<line>        byte_select_match = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_WPMASKANDBAS" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_WPMASKANDBAS</a>);</line>
<line>    else</line>
<line>        LSB = (DBGWCR[n].BAS AND NOT(DBGWCR[n].BAS - 1));  MSB = (DBGWCR[n].BAS + LSB);</line>
<line>        if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(MSB AND (MSB - 1)) then                     // Not contiguous</line>
<line>            byte_select_match = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_WPBASCONTIGUOUS" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_WPBASCONTIGUOUS</a>);</line>
<line>            bottom = 3;                                        // For the whole doubleword</line>
<line></line>
<line>    // If the address mask is set to a reserved value, the behavior is CONSTRAINED UNPREDICTABLE.</line>
<line>    if mask &gt; 0 &amp;&amp; mask &lt;= 2 then</line>
<line>        <a link="Constraint" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint</a> c;</line>
<line>        (c, mask) = <a link="impl-shared.ConstrainUnpredictableInteger.3" file="shared_pseudocode.xml" hover="function: (Constraint,integer) ConstrainUnpredictableInteger(integer low, integer high, Unpredictable which)">ConstrainUnpredictableInteger</a>(3, 31, <a link="Unpredictable_RESWPMASK" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESWPMASK</a>);</line>
<line>        assert c IN {<a link="Constraint_DISABLED" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_DISABLED</a>, <a link="Constraint_NONE" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NONE</a>, <a link="Constraint_UNKNOWN" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNKNOWN</a>};</line>
<line>        case c of</line>
<line>            when <a link="Constraint_DISABLED" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_DISABLED</a>  return FALSE;            // Disabled</line>
<line>            when <a link="Constraint_NONE" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NONE</a>      mask = 0;                // No masking</line>
<line>            // Otherwise the value returned by ConstrainUnpredictableInteger is a not-reserved value</line>
<line></line>
<line>    boolean WVR_match;</line>
<line>    if mask &gt; bottom then</line>
<line>        WVR_match = (vaddress&lt;top:mask&gt; == DBGWVR[n]&lt;top:mask&gt;);</line>
<line>        // If masked bits of DBGWVR_EL1[n] are not zero, the behavior is CONSTRAINED UNPREDICTABLE.</line>
<line>        if WVR_match &amp;&amp; !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(DBGWVR[n]&lt;mask-1:bottom&gt;) then</line>
<line>            WVR_match = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_WPMASKEDBITS" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_WPMASKEDBITS</a>);</line>
<line>    else</line>
<line>        WVR_match = vaddress&lt;top:bottom&gt; == DBGWVR[n]&lt;top:bottom&gt;;</line>
<line></line>
<line>    return WVR_match &amp;&amp; byte_select_match;</line>
</pstext>
    </ps>
    <ps name="aarch32/debug/watchpoint/AArch32.WatchpointMatch" mylink="aarch32.debug.watchpoint.AArch32.WatchpointMatch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.WatchpointMatch()</line>
<line>// =========================</line>
<line>// Watchpoint matching in an AArch32 translation regime.</line>
<line></line>
<line link="AArch32.WatchpointMatch.4" hover="function: boolean AArch32.WatchpointMatch(integer n, bits(32) vaddress, integer size, AccessDescriptor accdesc)" conts="AArch32.WatchpointMatch">boolean <anchor link="AArch32.WatchpointMatch.4" hover="function: boolean AArch32.WatchpointMatch(integer n, bits(32) vaddress, integer size, AccessDescriptor accdesc)">AArch32.WatchpointMatch</anchor>(integer n, bits(32) vaddress, integer size,</line>
<line>                                <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    assert <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>());</line>
<line>    assert n &lt; <a link="impl-shared.NumWatchpointsImplemented.0" file="shared_pseudocode.xml" hover="function: integer NumWatchpointsImplemented()">NumWatchpointsImplemented</a>();</line>
<line></line>
<line>    enabled = DBGWCR[n].E == '1';</line>
<line>    linked = DBGWCR[n].WT == '1';</line>
<line>    isbreakpnt = FALSE;</line>
<line></line>
<line>    state_match = <a link="AArch32.StateMatch.7" file="shared_pseudocode.xml" hover="function: boolean AArch32.StateMatch(bits(2) ssc_in,  bit hmc_in, bits(2) pxc_in, boolean linked_in, bits(4) lbn, boolean isbreakpnt, AccessDescriptor accdesc)">AArch32.StateMatch</a>(DBGWCR[n].SSC, DBGWCR[n].HMC, DBGWCR[n].PAC,</line>
<line>                                     linked, DBGWCR[n].LBN, isbreakpnt, accdesc);</line>
<line></line>
<line>    boolean ls_match;</line>
<line>    case DBGWCR[n].LSC&lt;1:0&gt; of</line>
<line>        when '00' ls_match = FALSE;</line>
<line>        when '01' ls_match = accdesc.read;</line>
<line>        when '10' ls_match = accdesc.write || accdesc.acctype == <a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>;</line>
<line>        when '11' ls_match = TRUE;</line>
<line></line>
<line>    value_match = FALSE;</line>
<line>    for byte = 0 to size - 1</line>
<line>        value_match = value_match || <a link="AArch32.WatchpointByteMatch.2" file="shared_pseudocode.xml" hover="function: boolean AArch32.WatchpointByteMatch(integer n, bits(32) vaddress)">AArch32.WatchpointByteMatch</a>(n, vaddress + byte);</line>
<line></line>
<line>    return value_match &amp;&amp; state_match &amp;&amp; ls_match &amp;&amp; enabled;</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/aborts/AArch32.Abort" mylink="aarch32.exceptions.aborts.AArch32.Abort" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.Abort()</line>
<line>// ===============</line>
<line>// Abort and Debug exception handling in an AArch32 translation regime.</line>
<line></line>
<line link="AArch32.Abort.2" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)" conts="AArch32.Abort"><anchor link="AArch32.Abort.2" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</anchor>(bits(32) vaddress, <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line></line>
<line>    // Check if routed to AArch64 state</line>
<line>    route_to_aarch64 = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line></line>
<line>    if !route_to_aarch64 &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>        route_to_aarch64 = (HCR_EL2.TGE == '1' || <a link="impl-shared.IsSecondStage.1" file="shared_pseudocode.xml" hover="function: boolean IsSecondStage(FaultRecord fault)">IsSecondStage</a>(fault) ||</line>
<line>                            (<a link="impl-shared.HaveRASExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveRASExt()">HaveRASExt</a>() &amp;&amp; HCR_EL2.TEA == '1' &amp;&amp; <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault)) ||</line>
<line>                            (<a link="impl-shared.IsDebugException.1" file="shared_pseudocode.xml" hover="function: boolean IsDebugException(FaultRecord fault)">IsDebugException</a>(fault) &amp;&amp; MDCR_EL2.TDE == '1'));</line>
<line></line>
<line>    if !route_to_aarch64 &amp;&amp; <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        route_to_aarch64 = <a link="impl-shared.EffectiveEA.0" file="shared_pseudocode.xml" hover="function: bit EffectiveEA()">EffectiveEA</a>() == '1' &amp;&amp; <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault);</line>
<line></line>
<line>    if route_to_aarch64 then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(<a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(vaddress,  64), fault);</line>
<line>    elsif fault.access.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> then</line>
<line>        <a link="AArch32.TakePrefetchAbortException.2" file="shared_pseudocode.xml" hover="function: AArch32.TakePrefetchAbortException(bits(32) vaddress, FaultRecord fault)">AArch32.TakePrefetchAbortException</a>(vaddress, fault);</line>
<line>    else</line>
<line>        <a link="AArch32.TakeDataAbortException.2" file="shared_pseudocode.xml" hover="function: AArch32.TakeDataAbortException(bits(32) vaddress, FaultRecord fault)">AArch32.TakeDataAbortException</a>(vaddress, fault);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/aborts/AArch32.AbortSyndrome" mylink="aarch32.exceptions.aborts.AArch32.AbortSyndrome" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.AbortSyndrome()</line>
<line>// =======================</line>
<line>// Creates an exception syndrome record for Abort  exceptions</line>
<line>// taken to Hyp mode</line>
<line>// from an AArch32 translation regime.</line>
<line></line>
<line link="AArch32.AbortSyndrome.4" hover="function: ExceptionRecord AArch32.AbortSyndrome(Exception exceptype, FaultRecord fault, bits(32) vaddress, bits(2) target_el)" conts="AArch32.AbortSyndrome">ExceptionRecord <anchor link="AArch32.AbortSyndrome.4" hover="function: ExceptionRecord AArch32.AbortSyndrome(Exception exceptype, FaultRecord fault, bits(32) vaddress, bits(2) target_el)">AArch32.AbortSyndrome</anchor>(<a link="Exception" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception</a> exceptype, <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault,</line>
<line>                                      bits(32) vaddress, bits(2) target_el)</line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(exceptype);</line>
<line></line>
<line>    d_side = exceptype == <a link="Exception_DataAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_DataAbort</a>;</line>
<line></line>
<line>    exception.syndrome = <a link="AArch32.FaultSyndrome.2" file="shared_pseudocode.xml" hover="function: bits(25) AArch32.FaultSyndrome(boolean d_side, FaultRecord fault)">AArch32.FaultSyndrome</a>(d_side, fault);</line>
<line>    exception.vaddress = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(vaddress, 64);</line>
<line></line>
<line>    if <a link="impl-shared.IPAValid.1" file="shared_pseudocode.xml" hover="function: boolean IPAValid(FaultRecord fault)">IPAValid</a>(fault) then</line>
<line>        exception.ipavalid = TRUE;</line>
<line>        exception.NS = if fault.ipaddress.paspace == <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a> then '1' else '0';</line>
<line>        exception.ipaddress = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(fault.ipaddress.address,  56);</line>
<line>    else</line>
<line>        exception.ipavalid = FALSE;</line>
<line></line>
<line>    return exception;</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/aborts/AArch32.CheckPCAlignment" mylink="aarch32.exceptions.aborts.AArch32.CheckPCAlignment" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.CheckPCAlignment()</line>
<line>// ==========================</line>
<line></line>
<line link="AArch32.CheckPCAlignment.0" hover="function: AArch32.CheckPCAlignment()" conts="AArch32.CheckPCAlignment"><anchor link="AArch32.CheckPCAlignment.0" hover="function: AArch32.CheckPCAlignment()">AArch32.CheckPCAlignment</anchor>()</line>
<line>    bits(32) pc = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(32);</line>
<line></line>
<line>    if (<a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> &amp;&amp; pc&lt;1&gt; == '1') || pc&lt;0&gt; == '1' then</line>
<line>        if <a link="AArch32.GeneralExceptionsToAArch64.0" file="shared_pseudocode.xml" hover="function: boolean AArch32.GeneralExceptionsToAArch64()">AArch32.GeneralExceptionsToAArch64</a>() then <a link="AArch64.PCAlignmentFault.0" file="shared_pseudocode.xml" hover="function: AArch64.PCAlignmentFault()">AArch64.PCAlignmentFault</a>();</line>
<line></line>
<line>        <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescIFetch.0" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescIFetch()">CreateAccDescIFetch</a>();</line>
<line>        <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = <a link="impl-shared.NoFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord NoFault(AccessDescriptor accdesc)">NoFault</a>(accdesc);</line>
<line>        // Generate an Alignment fault Prefetch Abort exception</line>
<line>        fault.statuscode = <a link="Fault_Alignment" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Alignment</a>;</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(pc, fault);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/aborts/AArch32.CommonFaultStatus" mylink="aarch32.exceptions.aborts.AArch32.CommonFaultStatus" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.CommonFaultStatus()</line>
<line>// ===========================</line>
<line>// Return the common part of the fault status on reporting a Data</line>
<line>// or Prefetch Abort.</line>
<line></line>
<line link="AArch32.CommonFaultStatus.2" hover="function: bits(32) AArch32.CommonFaultStatus(FaultRecord fault, boolean long_format)" conts="AArch32.CommonFaultStatus">bits(32) <anchor link="AArch32.CommonFaultStatus.2" hover="function: bits(32) AArch32.CommonFaultStatus(FaultRecord fault, boolean long_format)">AArch32.CommonFaultStatus</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault, boolean long_format)</line>
<line>    bits(32) target = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32);</line>
<line>    if <a link="impl-shared.HaveRASExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveRASExt()">HaveRASExt</a>() &amp;&amp; <a link="impl-shared.IsAsyncAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsAsyncAbort(Fault statuscode)">IsAsyncAbort</a>(fault) then</line>
<line>        <a link="ErrorState" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState</a> errstate = <a link="AArch32.PEErrorState.1" file="shared_pseudocode.xml" hover="function: ErrorState AArch32.PEErrorState(FaultRecord fault)">AArch32.PEErrorState</a>(fault);</line>
<line>        target&lt;15:14&gt; = <a link="AArch32.EncodeAsyncErrorSyndrome.1" file="shared_pseudocode.xml" hover="function: bits(2) AArch32.EncodeAsyncErrorSyndrome(ErrorState errorstate)">AArch32.EncodeAsyncErrorSyndrome</a>(errstate);   // AET</line>
<line>    if <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault) then target&lt;12&gt; = fault.extflag;        // ExT</line>
<line>    target&lt;9&gt; = if long_format then '1' else '0';                     // LPAE</line>
<line>    if long_format then                                               // Long-descriptor format</line>
<line>        target&lt;5:0&gt;    = <a link="impl-shared.EncodeLDFSC.2" file="shared_pseudocode.xml" hover="function: bits(6) EncodeLDFSC(Fault statuscode, integer level)">EncodeLDFSC</a>(fault.statuscode, fault.level);  // STATUS</line>
<line>    else                                                              // Short-descriptor format</line>
<line>        target&lt;10,3:0&gt; = <a link="impl-aarch32.EncodeSDFSC.2" file="shared_pseudocode.xml" hover="function: bits(5) EncodeSDFSC(Fault statuscode, integer level)">EncodeSDFSC</a>(fault.statuscode, fault.level);  // FS</line>
<line>    return target;</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/aborts/AArch32.ReportDataAbort" mylink="aarch32.exceptions.aborts.AArch32.ReportDataAbort" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.ReportDataAbort()</line>
<line>// =========================</line>
<line>// Report syndrome information for aborts taken to modes other than Hyp mode.</line>
<line></line>
<line link="AArch32.ReportDataAbort.3" hover="function: AArch32.ReportDataAbort(boolean route_to_monitor, FaultRecord fault, bits(32) vaddress)" conts="AArch32.ReportDataAbort"><anchor link="AArch32.ReportDataAbort.3" hover="function: AArch32.ReportDataAbort(boolean route_to_monitor, FaultRecord fault, bits(32) vaddress)">AArch32.ReportDataAbort</anchor>(boolean route_to_monitor, <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault,</line>
<line>                        bits(32) vaddress)</line>
<line>    long_format = FALSE;</line>
<line>    if route_to_monitor &amp;&amp; <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() != <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>        long_format = ((TTBCR_S.EAE == '1') ||</line>
<line>                       (<a link="impl-shared.IsExternalSyncAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalSyncAbort(Fault statuscode)">IsExternalSyncAbort</a>(fault) &amp;&amp; ((PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || TTBCR.EAE == '1') ||</line>
<line>                        (fault.secondstage &amp;&amp; (boolean IMPLEMENTATION_DEFINED</line>
<line>                                               "Report abort using Long-descriptor format")))));</line>
<line>    else</line>
<line>        long_format = TTBCR.EAE == '1';</line>
<line>    bits(32) syndrome = <a link="AArch32.CommonFaultStatus.2" file="shared_pseudocode.xml" hover="function: bits(32) AArch32.CommonFaultStatus(FaultRecord fault, boolean long_format)">AArch32.CommonFaultStatus</a>(fault, long_format);</line>
<line></line>
<line>    // bits of syndrome that are not common to I and D side</line>
<line>    if fault.access.acctype IN {<a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>, <a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a>, <a link="AccessType_AT" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_AT</a>} then</line>
<line>        syndrome&lt;13&gt; = '1';                              // CM</line>
<line>        syndrome&lt;11&gt; = '1';                              // WnR</line>
<line>    else</line>
<line>        syndrome&lt;11&gt; = if fault.write then '1' else '0'; // WnR</line>
<line></line>
<line>    if !long_format then</line>
<line>        syndrome&lt;7:4&gt; = fault.domain;                    // Domain</line>
<line></line>
<line>    if fault.access.acctype == <a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a> then</line>
<line>        bits(32) i_syndrome;</line>
<line>        if (!long_format &amp;&amp;</line>
<line>            boolean IMPLEMENTATION_DEFINED "Report I-cache maintenance fault in IFSR") then</line>
<line>            i_syndrome = syndrome;</line>
<line>            syndrome&lt;10,3:0&gt; = <a link="impl-aarch32.EncodeSDFSC.2" file="shared_pseudocode.xml" hover="function: bits(5) EncodeSDFSC(Fault statuscode, integer level)">EncodeSDFSC</a>(<a link="Fault_ICacheMaint" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_ICacheMaint</a>, 1);</line>
<line>        else</line>
<line>            i_syndrome = bits(32) UNKNOWN;</line>
<line>        if route_to_monitor then</line>
<line>            IFSR_S = i_syndrome;</line>
<line>        else</line>
<line>            IFSR = i_syndrome;</line>
<line></line>
<line>    if route_to_monitor then</line>
<line>        DFSR_S = syndrome;</line>
<line>        DFAR_S = vaddress;</line>
<line>    else</line>
<line>        DFSR = syndrome;</line>
<line>        DFAR = vaddress;</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/aborts/AArch32.ReportPrefetchAbort" mylink="aarch32.exceptions.aborts.AArch32.ReportPrefetchAbort" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.ReportPrefetchAbort()</line>
<line>// =============================</line>
<line>// Report syndrome information for aborts taken to modes other than Hyp mode.</line>
<line></line>
<line link="AArch32.ReportPrefetchAbort.3" hover="function: AArch32.ReportPrefetchAbort(boolean route_to_monitor, FaultRecord fault, bits(32) vaddress)" conts="AArch32.ReportPrefetchAbort"><anchor link="AArch32.ReportPrefetchAbort.3" hover="function: AArch32.ReportPrefetchAbort(boolean route_to_monitor, FaultRecord fault, bits(32) vaddress)">AArch32.ReportPrefetchAbort</anchor>(boolean route_to_monitor, <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault, bits(32) vaddress)</line>
<line>    // The encoding used in the IFSR can be Long-descriptor format or Short-descriptor format.</line>
<line>    // Normally, the current translation table format determines the format. For an abort from</line>
<line>    // Non-secure state to Monitor mode, the IFSR uses the Long-descriptor format if any of the</line>
<line>    // following applies:</line>
<line>    // * The Secure TTBCR.EAE is set to 1.</line>
<line>    // * It is taken from Hyp mode.</line>
<line>    // * It is taken from EL1 or EL0, and the Non-secure TTBCR.EAE is set to 1.</line>
<line>    long_format = FALSE;</line>
<line>    if route_to_monitor &amp;&amp; <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() != <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>        long_format = TTBCR_S.EAE == '1' || PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || TTBCR.EAE == '1';</line>
<line>    else</line>
<line>        long_format = TTBCR.EAE == '1';</line>
<line></line>
<line>    bits(32) fsr = <a link="AArch32.CommonFaultStatus.2" file="shared_pseudocode.xml" hover="function: bits(32) AArch32.CommonFaultStatus(FaultRecord fault, boolean long_format)">AArch32.CommonFaultStatus</a>(fault, long_format);</line>
<line></line>
<line>    if route_to_monitor then</line>
<line>        IFSR_S = fsr;</line>
<line>        IFAR_S = vaddress;</line>
<line>    else</line>
<line>        IFSR = fsr;</line>
<line>        IFAR = vaddress;</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/aborts/AArch32.TakeDataAbortException" mylink="aarch32.exceptions.aborts.AArch32.TakeDataAbortException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TakeDataAbortException()</line>
<line>// ================================</line>
<line></line>
<line link="AArch32.TakeDataAbortException.2" hover="function: AArch32.TakeDataAbortException(bits(32) vaddress, FaultRecord fault)" conts="AArch32.TakeDataAbortException"><anchor link="AArch32.TakeDataAbortException.2" hover="function: AArch32.TakeDataAbortException(bits(32) vaddress, FaultRecord fault)">AArch32.TakeDataAbortException</anchor>(bits(32) vaddress, <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    route_to_monitor = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.EffectiveEA.0" file="shared_pseudocode.xml" hover="function: bit EffectiveEA()">EffectiveEA</a>() == '1' &amp;&amp; <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault);</line>
<line>    route_to_hyp = (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp;</line>
<line>                    (HCR.TGE == '1' ||</line>
<line>                     (<a link="impl-shared.HaveRASExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveRASExt()">HaveRASExt</a>() &amp;&amp; HCR2.TEA == '1' &amp;&amp; <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault)) ||</line>
<line>                     (<a link="impl-shared.IsDebugException.1" file="shared_pseudocode.xml" hover="function: boolean IsDebugException(FaultRecord fault)">IsDebugException</a>(fault) &amp;&amp; HDCR.TDE == '1') ||</line>
<line>                     <a link="impl-shared.IsSecondStage.1" file="shared_pseudocode.xml" hover="function: boolean IsSecondStage(FaultRecord fault)">IsSecondStage</a>(fault)));</line>
<line></line>
<line>    bits(32) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(32);</line>
<line>    vect_offset = 0x10;</line>
<line>    lr_offset = 8;</line>
<line></line>
<line>    if <a link="impl-shared.IsDebugException.1" file="shared_pseudocode.xml" hover="function: boolean IsDebugException(FaultRecord fault)">IsDebugException</a>(fault) then DBGDSCRext.MOE = fault.debugmoe;</line>
<line>    if route_to_monitor then</line>
<line>        <a link="AArch32.ReportDataAbort.3" file="shared_pseudocode.xml" hover="function: AArch32.ReportDataAbort(boolean route_to_monitor, FaultRecord fault, bits(32) vaddress)">AArch32.ReportDataAbort</a>(route_to_monitor, fault, vaddress);</line>
<line>        <a link="AArch32.EnterMonitorMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterMonitorMode(bits(32) preferred_exception_return, integer lr_offset, integer vect_offset)">AArch32.EnterMonitorMode</a>(preferred_exception_return, lr_offset, vect_offset);</line>
<line>    elsif PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || route_to_hyp then</line>
<line>        exception = <a link="AArch32.AbortSyndrome.4" file="shared_pseudocode.xml" hover="function: ExceptionRecord AArch32.AbortSyndrome(Exception exceptype, FaultRecord fault, bits(32) vaddress, bits(2) target_el)">AArch32.AbortSyndrome</a>(<a link="Exception_DataAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_DataAbort</a>, fault, vaddress, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>        if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>            <a link="AArch32.EnterHypMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterHypMode(ExceptionRecord exception, bits(32) preferred_exception_return, integer vect_offset)">AArch32.EnterHypMode</a>(exception, preferred_exception_return, vect_offset);</line>
<line>        else</line>
<line>            <a link="AArch32.EnterHypMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterHypMode(ExceptionRecord exception, bits(32) preferred_exception_return, integer vect_offset)">AArch32.EnterHypMode</a>(exception, preferred_exception_return, 0x14);</line>
<line>    else</line>
<line>        <a link="AArch32.ReportDataAbort.3" file="shared_pseudocode.xml" hover="function: AArch32.ReportDataAbort(boolean route_to_monitor, FaultRecord fault, bits(32) vaddress)">AArch32.ReportDataAbort</a>(route_to_monitor, fault, vaddress);</line>
<line>        <a link="AArch32.EnterMode.4" file="shared_pseudocode.xml" hover="function: AArch32.EnterMode(bits(5) target_mode, bits(32) preferred_exception_return, integer lr_offset, integer vect_offset)">AArch32.EnterMode</a>(<a link="M32_Abort" file="shared_pseudocode.xml" hover="constant bits(5) M32_Abort = '10111'">M32_Abort</a>, preferred_exception_return, lr_offset, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/aborts/AArch32.TakePrefetchAbortException" mylink="aarch32.exceptions.aborts.AArch32.TakePrefetchAbortException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TakePrefetchAbortException()</line>
<line>// ====================================</line>
<line></line>
<line link="AArch32.TakePrefetchAbortException.2" hover="function: AArch32.TakePrefetchAbortException(bits(32) vaddress, FaultRecord fault)" conts="AArch32.TakePrefetchAbortException"><anchor link="AArch32.TakePrefetchAbortException.2" hover="function: AArch32.TakePrefetchAbortException(bits(32) vaddress, FaultRecord fault)">AArch32.TakePrefetchAbortException</anchor>(bits(32) vaddress, <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    route_to_monitor = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.EffectiveEA.0" file="shared_pseudocode.xml" hover="function: bit EffectiveEA()">EffectiveEA</a>() == '1' &amp;&amp; <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault);</line>
<line></line>
<line>    route_to_hyp = (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp;</line>
<line>                    (HCR.TGE == '1' ||</line>
<line>                     (<a link="impl-shared.HaveRASExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveRASExt()">HaveRASExt</a>() &amp;&amp; HCR2.TEA == '1' &amp;&amp; <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault)) ||</line>
<line>                     (<a link="impl-shared.IsDebugException.1" file="shared_pseudocode.xml" hover="function: boolean IsDebugException(FaultRecord fault)">IsDebugException</a>(fault) &amp;&amp; HDCR.TDE == '1') ||</line>
<line>                     <a link="impl-shared.IsSecondStage.1" file="shared_pseudocode.xml" hover="function: boolean IsSecondStage(FaultRecord fault)">IsSecondStage</a>(fault)));</line>
<line></line>
<line>    <a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception;</line>
<line>    bits(32) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(32);</line>
<line>    vect_offset = 0x0C;</line>
<line>    lr_offset = 4;</line>
<line></line>
<line>    if <a link="impl-shared.IsDebugException.1" file="shared_pseudocode.xml" hover="function: boolean IsDebugException(FaultRecord fault)">IsDebugException</a>(fault) then DBGDSCRext.MOE = fault.debugmoe;</line>
<line>    if route_to_monitor then</line>
<line>        <a link="AArch32.ReportPrefetchAbort.3" file="shared_pseudocode.xml" hover="function: AArch32.ReportPrefetchAbort(boolean route_to_monitor, FaultRecord fault, bits(32) vaddress)">AArch32.ReportPrefetchAbort</a>(route_to_monitor, fault, vaddress);</line>
<line>        <a link="AArch32.EnterMonitorMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterMonitorMode(bits(32) preferred_exception_return, integer lr_offset, integer vect_offset)">AArch32.EnterMonitorMode</a>(preferred_exception_return, lr_offset, vect_offset);</line>
<line>    elsif PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || route_to_hyp then</line>
<line>        if fault.statuscode == <a link="Fault_Alignment" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Alignment</a> then             // PC Alignment fault</line>
<line>            exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_PCAlignment" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_PCAlignment</a>);</line>
<line>            exception.vaddress = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>        else</line>
<line>            exception = <a link="AArch32.AbortSyndrome.4" file="shared_pseudocode.xml" hover="function: ExceptionRecord AArch32.AbortSyndrome(Exception exceptype, FaultRecord fault, bits(32) vaddress, bits(2) target_el)">AArch32.AbortSyndrome</a>(<a link="Exception_InstructionAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_InstructionAbort</a>, fault, vaddress, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>        if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>            <a link="AArch32.EnterHypMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterHypMode(ExceptionRecord exception, bits(32) preferred_exception_return, integer vect_offset)">AArch32.EnterHypMode</a>(exception, preferred_exception_return, vect_offset);</line>
<line>        else</line>
<line>            <a link="AArch32.EnterHypMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterHypMode(ExceptionRecord exception, bits(32) preferred_exception_return, integer vect_offset)">AArch32.EnterHypMode</a>(exception, preferred_exception_return, 0x14);</line>
<line>    else</line>
<line>        <a link="AArch32.ReportPrefetchAbort.3" file="shared_pseudocode.xml" hover="function: AArch32.ReportPrefetchAbort(boolean route_to_monitor, FaultRecord fault, bits(32) vaddress)">AArch32.ReportPrefetchAbort</a>(route_to_monitor, fault, vaddress);</line>
<line>        <a link="AArch32.EnterMode.4" file="shared_pseudocode.xml" hover="function: AArch32.EnterMode(bits(5) target_mode, bits(32) preferred_exception_return, integer lr_offset, integer vect_offset)">AArch32.EnterMode</a>(<a link="M32_Abort" file="shared_pseudocode.xml" hover="constant bits(5) M32_Abort = '10111'">M32_Abort</a>, preferred_exception_return, lr_offset, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/async/AArch32.TakePhysicalFIQException" mylink="aarch32.exceptions.async.AArch32.TakePhysicalFIQException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TakePhysicalFIQException()</line>
<line>// ==================================</line>
<line></line>
<line link="AArch32.TakePhysicalFIQException.0" hover="function: AArch32.TakePhysicalFIQException()" conts="AArch32.TakePhysicalFIQException"><anchor link="AArch32.TakePhysicalFIQException.0" hover="function: AArch32.TakePhysicalFIQException()">AArch32.TakePhysicalFIQException</anchor>()</line>
<line></line>
<line>    // Check if routed to AArch64 state</line>
<line>    route_to_aarch64 = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line>    if !route_to_aarch64 &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>        route_to_aarch64 = HCR_EL2.TGE == '1' || (HCR_EL2.FMO == '1' &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>());</line>
<line></line>
<line>    if !route_to_aarch64 &amp;&amp; <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        route_to_aarch64 = SCR_EL3.FIQ == '1';</line>
<line></line>
<line>    if route_to_aarch64 then <a link="AArch64.TakePhysicalFIQException.0" file="shared_pseudocode.xml" hover="function: AArch64.TakePhysicalFIQException()">AArch64.TakePhysicalFIQException</a>();</line>
<line>    route_to_monitor = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR.FIQ == '1';</line>
<line>    route_to_hyp = (PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>                    (HCR.TGE == '1' || HCR.FMO == '1'));</line>
<line>    bits(32) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(32);</line>
<line>    vect_offset = 0x1C;</line>
<line>    lr_offset = 4;</line>
<line>    if route_to_monitor then</line>
<line>        <a link="AArch32.EnterMonitorMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterMonitorMode(bits(32) preferred_exception_return, integer lr_offset, integer vect_offset)">AArch32.EnterMonitorMode</a>(preferred_exception_return, lr_offset, vect_offset);</line>
<line>    elsif PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || route_to_hyp then</line>
<line>        exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_FIQ" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FIQ</a>);</line>
<line>        <a link="AArch32.EnterHypMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterHypMode(ExceptionRecord exception, bits(32) preferred_exception_return, integer vect_offset)">AArch32.EnterHypMode</a>(exception, preferred_exception_return, vect_offset);</line>
<line>    else</line>
<line>        <a link="AArch32.EnterMode.4" file="shared_pseudocode.xml" hover="function: AArch32.EnterMode(bits(5) target_mode, bits(32) preferred_exception_return, integer lr_offset, integer vect_offset)">AArch32.EnterMode</a>(<a link="M32_FIQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_FIQ = '10001'">M32_FIQ</a>, preferred_exception_return, lr_offset, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/async/AArch32.TakePhysicalIRQException" mylink="aarch32.exceptions.async.AArch32.TakePhysicalIRQException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TakePhysicalIRQException()</line>
<line>// ==================================</line>
<line>// Take an enabled physical IRQ exception.</line>
<line></line>
<line link="AArch32.TakePhysicalIRQException.0" hover="function: AArch32.TakePhysicalIRQException()" conts="AArch32.TakePhysicalIRQException"><anchor link="AArch32.TakePhysicalIRQException.0" hover="function: AArch32.TakePhysicalIRQException()">AArch32.TakePhysicalIRQException</anchor>()</line>
<line></line>
<line>    // Check if routed to AArch64 state</line>
<line>    route_to_aarch64 = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line>    if !route_to_aarch64 &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>        route_to_aarch64 = HCR_EL2.TGE == '1' || (HCR_EL2.IMO == '1' &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>());</line>
<line>    if !route_to_aarch64 &amp;&amp; <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        route_to_aarch64 = SCR_EL3.IRQ == '1';</line>
<line></line>
<line>    if route_to_aarch64 then <a link="AArch64.TakePhysicalIRQException.0" file="shared_pseudocode.xml" hover="function: AArch64.TakePhysicalIRQException()">AArch64.TakePhysicalIRQException</a>();</line>
<line></line>
<line>    route_to_monitor = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR.IRQ == '1';</line>
<line>    route_to_hyp = (PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>                    (HCR.TGE == '1' || HCR.IMO == '1'));</line>
<line>    bits(32) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(32);</line>
<line>    vect_offset = 0x18;</line>
<line>    lr_offset = 4;</line>
<line>    if route_to_monitor then</line>
<line>        <a link="AArch32.EnterMonitorMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterMonitorMode(bits(32) preferred_exception_return, integer lr_offset, integer vect_offset)">AArch32.EnterMonitorMode</a>(preferred_exception_return, lr_offset, vect_offset);</line>
<line>    elsif PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || route_to_hyp then</line>
<line>        exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_IRQ" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_IRQ</a>);</line>
<line>        <a link="AArch32.EnterHypMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterHypMode(ExceptionRecord exception, bits(32) preferred_exception_return, integer vect_offset)">AArch32.EnterHypMode</a>(exception, preferred_exception_return, vect_offset);</line>
<line>    else</line>
<line>        <a link="AArch32.EnterMode.4" file="shared_pseudocode.xml" hover="function: AArch32.EnterMode(bits(5) target_mode, bits(32) preferred_exception_return, integer lr_offset, integer vect_offset)">AArch32.EnterMode</a>(<a link="M32_IRQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_IRQ = '10010'">M32_IRQ</a>, preferred_exception_return, lr_offset, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/async/AArch32.TakePhysicalSErrorException" mylink="aarch32.exceptions.async.AArch32.TakePhysicalSErrorException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TakePhysicalSErrorException()</line>
<line>// =====================================</line>
<line></line>
<line link="AArch32.TakePhysicalSErrorException.1" hover="function: AArch32.TakePhysicalSErrorException(boolean implicit_esb)" conts="AArch32.TakePhysicalSErrorException"><anchor link="AArch32.TakePhysicalSErrorException.1" hover="function: AArch32.TakePhysicalSErrorException(boolean implicit_esb)">AArch32.TakePhysicalSErrorException</anchor>(boolean implicit_esb)</line>
<line>    // Check if routed to AArch64 state</line>
<line>    route_to_aarch64 = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line></line>
<line>    if !route_to_aarch64 &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>        route_to_aarch64 = (HCR_EL2.TGE == '1' || (!<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() &amp;&amp; HCR_EL2.AMO == '1'));</line>
<line>    if !route_to_aarch64 &amp;&amp; <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        route_to_aarch64 = <a link="impl-shared.EffectiveEA.0" file="shared_pseudocode.xml" hover="function: bit EffectiveEA()">EffectiveEA</a>() == '1';</line>
<line></line>
<line>    if route_to_aarch64 then</line>
<line>        <a link="AArch64.TakePhysicalSErrorException.1" file="shared_pseudocode.xml" hover="function: AArch64.TakePhysicalSErrorException(boolean implicit_esb)">AArch64.TakePhysicalSErrorException</a>(implicit_esb);</line>
<line></line>
<line>    route_to_monitor = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR.EA == '1';</line>
<line>    route_to_hyp = (PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>                    (HCR.TGE == '1' || HCR.AMO == '1'));</line>
<line>    bits(32) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(32);</line>
<line>    vect_offset = 0x10;</line>
<line>    lr_offset = 8;</line>
<line></line>
<line>    bits(2) target_el;</line>
<line>    if route_to_monitor then</line>
<line>        target_el = <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line>    elsif PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || route_to_hyp then</line>
<line>        target_el = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>    else</line>
<line>        target_el = <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line></line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = <a link="impl-shared.GetPendingPhysicalSError.0" file="shared_pseudocode.xml" hover="function: FaultRecord GetPendingPhysicalSError()">GetPendingPhysicalSError</a>();</line>
<line>    vaddress = bits(32) UNKNOWN;</line>
<line>    exception = <a link="AArch32.AbortSyndrome.4" file="shared_pseudocode.xml" hover="function: ExceptionRecord AArch32.AbortSyndrome(Exception exceptype, FaultRecord fault, bits(32) vaddress, bits(2) target_el)">AArch32.AbortSyndrome</a>(<a link="Exception_DataAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_DataAbort</a>, fault, vaddress, target_el);</line>
<line></line>
<line>    if <a link="impl-shared.IsSErrorEdgeTriggered.0" file="shared_pseudocode.xml" hover="function: boolean IsSErrorEdgeTriggered()">IsSErrorEdgeTriggered</a>() then</line>
<line>        <a link="impl-shared.ClearPendingPhysicalSError.0" file="shared_pseudocode.xml" hover="function: ClearPendingPhysicalSError()">ClearPendingPhysicalSError</a>();</line>
<line>    case target_el of</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            <a link="AArch32.ReportDataAbort.3" file="shared_pseudocode.xml" hover="function: AArch32.ReportDataAbort(boolean route_to_monitor, FaultRecord fault, bits(32) vaddress)">AArch32.ReportDataAbort</a>(route_to_monitor, fault, vaddress);</line>
<line>            <a link="AArch32.EnterMonitorMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterMonitorMode(bits(32) preferred_exception_return, integer lr_offset, integer vect_offset)">AArch32.EnterMonitorMode</a>(preferred_exception_return, lr_offset, vect_offset);</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>                <a link="AArch32.EnterHypMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterHypMode(ExceptionRecord exception, bits(32) preferred_exception_return, integer vect_offset)">AArch32.EnterHypMode</a>(exception, preferred_exception_return, vect_offset);</line>
<line>            else</line>
<line>                <a link="AArch32.EnterHypMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterHypMode(ExceptionRecord exception, bits(32) preferred_exception_return, integer vect_offset)">AArch32.EnterHypMode</a>(exception, preferred_exception_return, 0x14);</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            <a link="AArch32.ReportDataAbort.3" file="shared_pseudocode.xml" hover="function: AArch32.ReportDataAbort(boolean route_to_monitor, FaultRecord fault, bits(32) vaddress)">AArch32.ReportDataAbort</a>(route_to_monitor, fault, vaddress);</line>
<line>            <a link="AArch32.EnterMode.4" file="shared_pseudocode.xml" hover="function: AArch32.EnterMode(bits(5) target_mode, bits(32) preferred_exception_return, integer lr_offset, integer vect_offset)">AArch32.EnterMode</a>(<a link="M32_Abort" file="shared_pseudocode.xml" hover="constant bits(5) M32_Abort = '10111'">M32_Abort</a>, preferred_exception_return, lr_offset, vect_offset);</line>
<line>        otherwise</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/async/AArch32.TakeVirtualFIQException" mylink="aarch32.exceptions.async.AArch32.TakeVirtualFIQException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TakeVirtualFIQException()</line>
<line>// =================================</line>
<line></line>
<line link="AArch32.TakeVirtualFIQException.0" hover="function: AArch32.TakeVirtualFIQException()" conts="AArch32.TakeVirtualFIQException"><anchor link="AArch32.TakeVirtualFIQException.0" hover="function: AArch32.TakeVirtualFIQException()">AArch32.TakeVirtualFIQException</anchor>()</line>
<line>    assert PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>();</line>
<line>    if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then  // Virtual IRQ enabled if TGE==0 and FMO==1</line>
<line>        assert HCR.TGE == '0' &amp;&amp; HCR.FMO == '1';</line>
<line>    else</line>
<line>        assert HCR_EL2.TGE == '0' &amp;&amp; HCR_EL2.FMO == '1';</line>
<line>    // Check if routed to AArch64 state</line>
<line>    if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then <a link="AArch64.TakeVirtualFIQException.0" file="shared_pseudocode.xml" hover="function: AArch64.TakeVirtualFIQException()">AArch64.TakeVirtualFIQException</a>();</line>
<line></line>
<line>    bits(32) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(32);</line>
<line>    vect_offset = 0x1C;</line>
<line>    lr_offset = 4;</line>
<line></line>
<line>    <a link="AArch32.EnterMode.4" file="shared_pseudocode.xml" hover="function: AArch32.EnterMode(bits(5) target_mode, bits(32) preferred_exception_return, integer lr_offset, integer vect_offset)">AArch32.EnterMode</a>(<a link="M32_FIQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_FIQ = '10001'">M32_FIQ</a>, preferred_exception_return, lr_offset, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/async/AArch32.TakeVirtualIRQException" mylink="aarch32.exceptions.async.AArch32.TakeVirtualIRQException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TakeVirtualIRQException()</line>
<line>// =================================</line>
<line></line>
<line link="AArch32.TakeVirtualIRQException.0" hover="function: AArch32.TakeVirtualIRQException()" conts="AArch32.TakeVirtualIRQException"><anchor link="AArch32.TakeVirtualIRQException.0" hover="function: AArch32.TakeVirtualIRQException()">AArch32.TakeVirtualIRQException</anchor>()</line>
<line>    assert PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>();</line>
<line></line>
<line>    if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then   // Virtual IRQs enabled if TGE==0 and IMO==1</line>
<line>        assert HCR.TGE == '0' &amp;&amp; HCR.IMO == '1';</line>
<line>    else</line>
<line>        assert HCR_EL2.TGE == '0' &amp;&amp; HCR_EL2.IMO == '1';</line>
<line></line>
<line>    // Check if routed to AArch64 state</line>
<line>    if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then <a link="AArch64.TakeVirtualIRQException.0" file="shared_pseudocode.xml" hover="function: AArch64.TakeVirtualIRQException()">AArch64.TakeVirtualIRQException</a>();</line>
<line></line>
<line>    bits(32) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(32);</line>
<line>    vect_offset = 0x18;</line>
<line>    lr_offset = 4;</line>
<line></line>
<line>    <a link="AArch32.EnterMode.4" file="shared_pseudocode.xml" hover="function: AArch32.EnterMode(bits(5) target_mode, bits(32) preferred_exception_return, integer lr_offset, integer vect_offset)">AArch32.EnterMode</a>(<a link="M32_IRQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_IRQ = '10010'">M32_IRQ</a>, preferred_exception_return, lr_offset, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/async/AArch32.TakeVirtualSErrorException" mylink="aarch32.exceptions.async.AArch32.TakeVirtualSErrorException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TakeVirtualSErrorException()</line>
<line>// ====================================</line>
<line></line>
<line link="AArch32.TakeVirtualSErrorException.0" hover="function: AArch32.TakeVirtualSErrorException()" conts="AArch32.TakeVirtualSErrorException"><anchor link="AArch32.TakeVirtualSErrorException.0" hover="function: AArch32.TakeVirtualSErrorException()">AArch32.TakeVirtualSErrorException</anchor>()</line>
<line></line>
<line>    assert PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>();</line>
<line>    if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then   // Virtual SError enabled if TGE==0 and AMO==1</line>
<line>        assert HCR.TGE == '0' &amp;&amp; HCR.AMO == '1';</line>
<line>    else</line>
<line>        assert HCR_EL2.TGE == '0' &amp;&amp; HCR_EL2.AMO == '1';</line>
<line>    // Check if routed to AArch64 state</line>
<line>    if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then <a link="AArch64.TakeVirtualSErrorException.0" file="shared_pseudocode.xml" hover="function: AArch64.TakeVirtualSErrorException()">AArch64.TakeVirtualSErrorException</a>();</line>
<line>    route_to_monitor = FALSE;</line>
<line></line>
<line>    bits(32) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(32);</line>
<line>    vect_offset = 0x10;</line>
<line>    lr_offset = 8;</line>
<line></line>
<line>    vaddress = bits(32) UNKNOWN;</line>
<line>    parity = FALSE;</line>
<line>    <a link="Fault" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault</a> fault = <a link="Fault_AsyncExternal" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncExternal</a>;</line>
<line>    integer level = integer UNKNOWN;</line>
<line>    bits(32) fsr = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32);</line>
<line>    if <a link="impl-shared.HaveRASExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveRASExt()">HaveRASExt</a>() then</line>
<line>        if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>            fsr&lt;15:14&gt; =  VDFSR.AET;</line>
<line>            fsr&lt;12&gt; =  VDFSR.ExT;</line>
<line>        else</line>
<line>            fsr&lt;15:14&gt; =  VSESR_EL2.AET;</line>
<line>            fsr&lt;12&gt; =  VSESR_EL2.ExT;</line>
<line>    else</line>
<line>        fsr&lt;12&gt; = bit IMPLEMENTATION_DEFINED "Virtual External abort type";</line>
<line>    if TTBCR.EAE == '1' then // Long-descriptor format</line>
<line>        fsr&lt;9&gt; = '1';</line>
<line>        fsr&lt;5:0&gt; = <a link="impl-shared.EncodeLDFSC.2" file="shared_pseudocode.xml" hover="function: bits(6) EncodeLDFSC(Fault statuscode, integer level)">EncodeLDFSC</a>(fault, level);</line>
<line>    else                     // Short-descriptor format</line>
<line>        fsr&lt;9&gt; = '0';</line>
<line>        fsr&lt;10,3:0&gt; = <a link="impl-aarch32.EncodeSDFSC.2" file="shared_pseudocode.xml" hover="function: bits(5) EncodeSDFSC(Fault statuscode, integer level)">EncodeSDFSC</a>(fault, level);</line>
<line>    DFSR = fsr;</line>
<line>    DFAR = bits(32) UNKNOWN;</line>
<line>    <a link="impl-shared.ClearPendingVirtualSError.0" file="shared_pseudocode.xml" hover="function: ClearPendingVirtualSError()">ClearPendingVirtualSError</a>();</line>
<line>    <a link="AArch32.EnterMode.4" file="shared_pseudocode.xml" hover="function: AArch32.EnterMode(bits(5) target_mode, bits(32) preferred_exception_return, integer lr_offset, integer vect_offset)">AArch32.EnterMode</a>(<a link="M32_Abort" file="shared_pseudocode.xml" hover="constant bits(5) M32_Abort = '10111'">M32_Abort</a>, preferred_exception_return, lr_offset, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/debug/AArch32.SoftwareBreakpoint" mylink="aarch32.exceptions.debug.AArch32.SoftwareBreakpoint" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.SoftwareBreakpoint()</line>
<line>// ============================</line>
<line></line>
<line link="AArch32.SoftwareBreakpoint.1" hover="function: AArch32.SoftwareBreakpoint(bits(16) immediate)" conts="AArch32.SoftwareBreakpoint"><anchor link="AArch32.SoftwareBreakpoint.1" hover="function: AArch32.SoftwareBreakpoint(bits(16) immediate)">AArch32.SoftwareBreakpoint</anchor>(bits(16) immediate)</line>
<line></line>
<line>    if (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp;</line>
<line>        (HCR_EL2.TGE == '1' || MDCR_EL2.TDE == '1')) || !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>        <a link="AArch64.SoftwareBreakpoint.1" file="shared_pseudocode.xml" hover="function: AArch64.SoftwareBreakpoint(bits(16) immediate)">AArch64.SoftwareBreakpoint</a>(immediate);</line>
<line></line>
<line>    accdesc  = <a link="impl-shared.CreateAccDescIFetch.0" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescIFetch()">CreateAccDescIFetch</a>();</line>
<line>    fault    = <a link="impl-shared.NoFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord NoFault(AccessDescriptor accdesc)">NoFault</a>(accdesc);</line>
<line>    vaddress = bits(32) UNKNOWN;</line>
<line></line>
<line>    fault.statuscode = <a link="Fault_Debug" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Debug</a>;</line>
<line>    fault.debugmoe   = <a link="DebugException_BKPT" file="shared_pseudocode.xml" hover="constant bits(4) DebugException_BKPT = '0011'">DebugException_BKPT</a>;</line>
<line></line>
<line>    <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(vaddress, fault);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/debug/DebugException" mylink="aarch32.exceptions.debug.DebugException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="DebugException_Breakpoint" hover="constant bits(4) DebugException_Breakpoint = '0001'" conts="DebugException_Breakpoint">constant bits(4) <anchor link="DebugException_Breakpoint" hover="constant bits(4) DebugException_Breakpoint = '0001'">DebugException_Breakpoint</anchor>  = '0001';</line>
<line link="DebugException_BKPT" hover="constant bits(4) DebugException_BKPT = '0011'" conts="DebugException_BKPT">constant bits(4) <anchor link="DebugException_BKPT" hover="constant bits(4) DebugException_BKPT = '0011'">DebugException_BKPT</anchor>        = '0011';</line>
<line link="DebugException_VectorCatch" hover="constant bits(4) DebugException_VectorCatch = '0101'" conts="DebugException_VectorCatch">constant bits(4) <anchor link="DebugException_VectorCatch" hover="constant bits(4) DebugException_VectorCatch = '0101'">DebugException_VectorCatch</anchor> = '0101';</line>
<line link="DebugException_Watchpoint" hover="constant bits(4) DebugException_Watchpoint = '1010'" conts="DebugException_Watchpoint">constant bits(4) <anchor link="DebugException_Watchpoint" hover="constant bits(4) DebugException_Watchpoint = '1010'">DebugException_Watchpoint</anchor>  = '1010';</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/exceptions/AArch32.CheckAdvSIMDOrFPRegisterTraps" mylink="aarch32.exceptions.exceptions.AArch32.CheckAdvSIMDOrFPRegisterTraps" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.CheckAdvSIMDOrFPRegisterTraps()</line>
<line>// =======================================</line>
<line>// Check if an instruction that accesses an Advanced SIMD and</line>
<line>// floating-point System register is trapped by an appropriate HCR.TIDx</line>
<line>// ID group trap control.</line>
<line></line>
<line link="AArch32.CheckAdvSIMDOrFPRegisterTraps.1" hover="function: AArch32.CheckAdvSIMDOrFPRegisterTraps(bits(4) reg)" conts="AArch32.CheckAdvSIMDOrFPRegisterTraps"><anchor link="AArch32.CheckAdvSIMDOrFPRegisterTraps.1" hover="function: AArch32.CheckAdvSIMDOrFPRegisterTraps(bits(4) reg)">AArch32.CheckAdvSIMDOrFPRegisterTraps</anchor>(bits(4) reg)</line>
<line></line>
<line>    if PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        tid0 = if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then HCR.TID0 else HCR_EL2.TID0;</line>
<line>        tid3 = if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then HCR.TID3 else HCR_EL2.TID3;</line>
<line></line>
<line>        if ((tid0 == '1' &amp;&amp; reg == '0000') ||                            // FPSID</line>
<line>              (tid3 == '1' &amp;&amp; reg IN {'0101', '0110', '0111'})) then     // MVFRx</line>
<line>            if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>                <a link="AArch32.SystemAccessTrap.2" file="shared_pseudocode.xml" hover="function: AArch32.SystemAccessTrap(bits(5) mode, integer ec)">AArch32.SystemAccessTrap</a>(<a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a>, 0x8);</line>
<line>            else</line>
<line>                <a link="AArch64.AArch32SystemAccessTrap.2" file="shared_pseudocode.xml" hover="function: AArch64.AArch32SystemAccessTrap(bits(2) target_el, integer ec)">AArch64.AArch32SystemAccessTrap</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, 0x8);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/exceptions/AArch32.ExceptionClass" mylink="aarch32.exceptions.exceptions.AArch32.ExceptionClass" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.ExceptionClass()</line>
<line>// ========================</line>
<line>// Returns the Exception Class and Instruction Length fields to be reported in HSR</line>
<line></line>
<line link="AArch32.ExceptionClass.1" hover="function: (integer,bit) AArch32.ExceptionClass(Exception exceptype)" conts="AArch32.ExceptionClass">(integer,bit) <anchor link="AArch32.ExceptionClass.1" hover="function: (integer,bit) AArch32.ExceptionClass(Exception exceptype)">AArch32.ExceptionClass</anchor>(<a link="Exception" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception</a> exceptype)</line>
<line></line>
<line>    il_is_valid = TRUE;</line>
<line>    integer ec;</line>
<line>    case exceptype of</line>
<line>        when <a link="Exception_Uncategorized" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Uncategorized</a>         ec = 0x00; il_is_valid = FALSE;</line>
<line>        when <a link="Exception_WFxTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_WFxTrap</a>               ec = 0x01;</line>
<line>        when <a link="Exception_CP15RTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP15RTTrap</a>            ec = 0x03;</line>
<line>        when <a link="Exception_CP15RRTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP15RRTTrap</a>           ec = 0x04;</line>
<line>        when <a link="Exception_CP14RTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14RTTrap</a>            ec = 0x05;</line>
<line>        when <a link="Exception_CP14DTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14DTTrap</a>            ec = 0x06;</line>
<line>        when <a link="Exception_AdvSIMDFPAccessTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_AdvSIMDFPAccessTrap</a>   ec = 0x07;</line>
<line>        when <a link="Exception_FPIDTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FPIDTrap</a>              ec = 0x08;</line>
<line>        when <a link="Exception_PACTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_PACTrap</a>               ec = 0x09;</line>
<line>        when <a link="Exception_TSTARTAccessTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_TSTARTAccessTrap</a>      ec = 0x1B;</line>
<line>        when <a link="Exception_GPC" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_GPC</a>                   ec = 0x1E;</line>
<line>        when <a link="Exception_CP14RRTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14RRTTrap</a>           ec = 0x0C;</line>
<line>        when <a link="Exception_BranchTarget" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_BranchTarget</a>          ec = 0x0D;</line>
<line>        when <a link="Exception_IllegalState" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_IllegalState</a>          ec = 0x0E; il_is_valid = FALSE;</line>
<line>        when <a link="Exception_SupervisorCall" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SupervisorCall</a>        ec = 0x11;</line>
<line>        when <a link="Exception_HypervisorCall" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_HypervisorCall</a>        ec = 0x12;</line>
<line>        when <a link="Exception_MonitorCall" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_MonitorCall</a>           ec = 0x13;</line>
<line>        when <a link="Exception_InstructionAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_InstructionAbort</a>      ec = 0x20; il_is_valid = FALSE;</line>
<line>        when <a link="Exception_PCAlignment" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_PCAlignment</a>           ec = 0x22; il_is_valid = FALSE;</line>
<line>        when <a link="Exception_DataAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_DataAbort</a>             ec = 0x24;</line>
<line>        when <a link="Exception_NV2DataAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_NV2DataAbort</a>          ec = 0x25;</line>
<line>        when <a link="Exception_FPTrappedException" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FPTrappedException</a>    ec = 0x28;</line>
<line>        otherwise                            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    if ec IN {0x20,0x24} &amp;&amp; PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>        ec = ec + 1;</line>
<line>    bit il;</line>
<line>    if il_is_valid then</line>
<line>        il = if <a link="impl-shared.ThisInstrLength.0" file="shared_pseudocode.xml" hover="function: integer ThisInstrLength()">ThisInstrLength</a>() == 32 then '1' else '0';</line>
<line>    else</line>
<line>        il = '1';</line>
<line></line>
<line>    return (ec,il);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/exceptions/AArch32.GeneralExceptionsToAArch64" mylink="aarch32.exceptions.exceptions.AArch32.GeneralExceptionsToAArch64" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.GeneralExceptionsToAArch64()</line>
<line>// ====================================</line>
<line>// Returns TRUE if exceptions normally routed to EL1 are being handled at an Exception</line>
<line>// level using AArch64, because either EL1 is using AArch64 or TGE is in force and EL2</line>
<line>// is using AArch64.</line>
<line></line>
<line link="AArch32.GeneralExceptionsToAArch64.0" hover="function: boolean AArch32.GeneralExceptionsToAArch64()" conts="AArch32.GeneralExceptionsToAArch64">boolean <anchor link="AArch32.GeneralExceptionsToAArch64.0" hover="function: boolean AArch32.GeneralExceptionsToAArch64()">AArch32.GeneralExceptionsToAArch64</anchor>()</line>
<line>    return ((PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>)) ||</line>
<line>            (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; HCR_EL2.TGE == '1'));</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/exceptions/AArch32.ReportHypEntry" mylink="aarch32.exceptions.exceptions.AArch32.ReportHypEntry" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.ReportHypEntry()</line>
<line>// ========================</line>
<line>// Report syndrome information to Hyp mode registers.</line>
<line></line>
<line link="AArch32.ReportHypEntry.1" hover="function: AArch32.ReportHypEntry(ExceptionRecord exception)" conts="AArch32.ReportHypEntry"><anchor link="AArch32.ReportHypEntry.1" hover="function: AArch32.ReportHypEntry(ExceptionRecord exception)">AArch32.ReportHypEntry</anchor>(<a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception)</line>
<line></line>
<line>    <a link="Exception" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception</a> exceptype = exception.exceptype;</line>
<line></line>
<line>    (ec,il) = <a link="AArch32.ExceptionClass.1" file="shared_pseudocode.xml" hover="function: (integer,bit) AArch32.ExceptionClass(Exception exceptype)">AArch32.ExceptionClass</a>(exceptype);</line>
<line>    iss  = exception.syndrome;</line>
<line>    iss2 = exception.syndrome2;</line>
<line></line>
<line>    // IL is not valid for Data Abort exceptions without valid instruction syndrome information</line>
<line>    if ec IN {0x24,0x25} &amp;&amp; iss&lt;24&gt; == '0' then</line>
<line>        il = '1';</line>
<line></line>
<line>    HSR = ec&lt;5:0&gt;:il:iss;</line>
<line></line>
<line>    if exceptype IN {<a link="Exception_InstructionAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_InstructionAbort</a>, <a link="Exception_PCAlignment" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_PCAlignment</a>} then</line>
<line>        HIFAR = exception.vaddress&lt;31:0&gt;;</line>
<line>        HDFAR = bits(32) UNKNOWN;</line>
<line>    elsif exceptype == <a link="Exception_DataAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_DataAbort</a> then</line>
<line>        HIFAR = bits(32) UNKNOWN;</line>
<line>        HDFAR = exception.vaddress&lt;31:0&gt;;</line>
<line></line>
<line>    if exception.ipavalid then</line>
<line>        HPFAR&lt;31:4&gt; = exception.ipaddress&lt;39:12&gt;;</line>
<line>    else</line>
<line>        HPFAR&lt;31:4&gt; = bits(28) UNKNOWN;</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/exceptions/AArch32.ResetControlRegisters" mylink="aarch32.exceptions.exceptions.AArch32.ResetControlRegisters" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.ResetControlRegisters()</line>
<line>// ===============================</line>
<line>// Resets System registers and memory-mapped control registers that have architecturally-defined</line>
<line>// reset values to those values.</line>
<line></line>
<line link="AArch32.ResetControlRegisters.1" hover="function: AArch32.ResetControlRegisters(boolean cold_reset)" conts="AArch32.ResetControlRegisters"><anchor link="AArch32.ResetControlRegisters.1" hover="function: AArch32.ResetControlRegisters(boolean cold_reset)">AArch32.ResetControlRegisters</anchor>(boolean cold_reset);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/exceptions/AArch32.TakeReset" mylink="aarch32.exceptions.exceptions.AArch32.TakeReset" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TakeReset()</line>
<line>// ===================</line>
<line>// Reset into AArch32 state</line>
<line></line>
<line link="AArch32.TakeReset.1" hover="function: AArch32.TakeReset(boolean cold_reset)" conts="AArch32.TakeReset"><anchor link="AArch32.TakeReset.1" hover="function: AArch32.TakeReset(boolean cold_reset)">AArch32.TakeReset</anchor>(boolean cold_reset)</line>
<line>    assert !<a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>();</line>
<line></line>
<line>    // Enter the highest implemented Exception level in AArch32 state</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        <a link="AArch32.WriteMode.1" file="shared_pseudocode.xml" hover="function: AArch32.WriteMode(bits(5) mode)">AArch32.WriteMode</a>(<a link="M32_Svc" file="shared_pseudocode.xml" hover="constant bits(5) M32_Svc = '10011'">M32_Svc</a>);</line>
<line>        SCR.NS = '0';                     // Secure state</line>
<line>    elsif <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>        <a link="AArch32.WriteMode.1" file="shared_pseudocode.xml" hover="function: AArch32.WriteMode(bits(5) mode)">AArch32.WriteMode</a>(<a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a>);</line>
<line>    else</line>
<line>        <a link="AArch32.WriteMode.1" file="shared_pseudocode.xml" hover="function: AArch32.WriteMode(bits(5) mode)">AArch32.WriteMode</a>(<a link="M32_Svc" file="shared_pseudocode.xml" hover="constant bits(5) M32_Svc = '10011'">M32_Svc</a>);</line>
<line></line>
<line>    // Reset System registers in the coproc=0b111x encoding space</line>
<line>    // and other system components</line>
<line>    <a link="AArch32.ResetControlRegisters.1" file="shared_pseudocode.xml" hover="function: AArch32.ResetControlRegisters(boolean cold_reset)">AArch32.ResetControlRegisters</a>(cold_reset);</line>
<line>    FPEXC.EN = '0';</line>
<line></line>
<line>    // Reset all other PSTATE fields, including instruction set and endianness according to the</line>
<line>    // SCTLR values produced by the above call to ResetControlRegisters()</line>
<line>    PSTATE.&lt;A,I,F&gt; = '111';             // All asynchronous exceptions masked</line>
<line>    PSTATE.IT = '00000000';             // IT block state reset</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        PSTATE.T = HSCTLR.TE;           // Instruction set: TE=0:A32, TE=1:T32. PSTATE.J is RES0.</line>
<line>        PSTATE.E = HSCTLR.EE;           // Endianness: EE=0: little-endian, EE=1: big-endian.</line>
<line>    else</line>
<line>        PSTATE.T = SCTLR.TE;            // Instruction set: TE=0:A32, TE=1:T32. PSTATE.J is RES0.</line>
<line>        PSTATE.E = SCTLR.EE;            // Endianness: EE=0: little-endian, EE=1: big-endian.</line>
<line>    PSTATE.IL = '0';                    // Clear Illegal Execution state bit</line>
<line></line>
<line>    // All registers, bits and fields not reset by the above pseudocode or by the BranchTo() call</line>
<line>    // below are UNKNOWN bitstrings after reset. In particular, the return information registers</line>
<line>    // R14 or ELR_hyp and SPSR have UNKNOWN values, so that it</line>
<line>    // is impossible to return from a reset in an architecturally defined way.</line>
<line>    <a link="AArch32.ResetGeneralRegisters.0" file="shared_pseudocode.xml" hover="function: AArch32.ResetGeneralRegisters()">AArch32.ResetGeneralRegisters</a>();</line>
<line>    <a link="AArch32.ResetSIMDFPRegisters.0" file="shared_pseudocode.xml" hover="function: AArch32.ResetSIMDFPRegisters()">AArch32.ResetSIMDFPRegisters</a>();</line>
<line>    <a link="AArch32.ResetSpecialRegisters.0" file="shared_pseudocode.xml" hover="function: AArch32.ResetSpecialRegisters()">AArch32.ResetSpecialRegisters</a>();</line>
<line>    <a link="impl-shared.ResetExternalDebugRegisters.1" file="shared_pseudocode.xml" hover="function: ResetExternalDebugRegisters(boolean cold_reset)">ResetExternalDebugRegisters</a>(cold_reset);</line>
<line></line>
<line>    bits(32) rv;                      // IMPLEMENTATION DEFINED reset vector</line>
<line></line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        if MVBAR&lt;0&gt; == '1' then           // Reset vector in MVBAR</line>
<line>            rv = MVBAR&lt;31:1&gt;:'0';</line>
<line>        else</line>
<line>            rv = bits(32) IMPLEMENTATION_DEFINED "reset vector address";</line>
<line>    else</line>
<line>        rv = RVBAR&lt;31:1&gt;:'0';</line>
<line></line>
<line>    // The reset vector must be correctly aligned</line>
<line>    assert rv&lt;0&gt; == '0' &amp;&amp; (PSTATE.T == '1' || rv&lt;1&gt; == '0');</line>
<line></line>
<line>    boolean branch_conditional = FALSE;</line>
<line>    <a link="impl-shared.BranchTo.3" file="shared_pseudocode.xml" hover="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(rv, <a link="BranchType_RESET" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_RESET</a>, branch_conditional);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/exceptions/ExcVectorBase" mylink="aarch32.exceptions.exceptions.ExcVectorBase" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExcVectorBase()</line>
<line>// ===============</line>
<line></line>
<line link="impl-aarch32.ExcVectorBase.0" hover="function: bits(32) ExcVectorBase()" conts="ExcVectorBase">bits(32) <anchor link="impl-aarch32.ExcVectorBase.0" hover="function: bits(32) ExcVectorBase()">ExcVectorBase</anchor>()</line>
<line>    if SCTLR.V == '1' then  // Hivecs selected, base = 0xFFFF0000</line>
<line>        return <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(16):<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>    else</line>
<line>        return VBAR&lt;31:5&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(5);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/ieeefp/AArch32.FPTrappedException" mylink="aarch32.exceptions.ieeefp.AArch32.FPTrappedException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.FPTrappedException()</line>
<line>// ============================</line>
<line></line>
<line link="AArch32.FPTrappedException.1" hover="function: AArch32.FPTrappedException(bits(8) accumulated_exceptions)" conts="AArch32.FPTrappedException"><anchor link="AArch32.FPTrappedException.1" hover="function: AArch32.FPTrappedException(bits(8) accumulated_exceptions)">AArch32.FPTrappedException</anchor>(bits(8) accumulated_exceptions)</line>
<line>    if <a link="AArch32.GeneralExceptionsToAArch64.0" file="shared_pseudocode.xml" hover="function: boolean AArch32.GeneralExceptionsToAArch64()">AArch32.GeneralExceptionsToAArch64</a>() then</line>
<line>        is_ase = FALSE;</line>
<line>        element = 0;</line>
<line>        <a link="AArch64.FPTrappedException.2" file="shared_pseudocode.xml" hover="function: AArch64.FPTrappedException(boolean is_ase, bits(8) accumulated_exceptions)">AArch64.FPTrappedException</a>(is_ase, accumulated_exceptions);</line>
<line>    FPEXC.DEX    = '1';</line>
<line>    FPEXC.TFV    = '1';</line>
<line>    FPEXC&lt;7,4:0&gt; = accumulated_exceptions&lt;7,4:0&gt;;                  // IDF,IXF,UFF,OFF,DZF,IOF</line>
<line>    FPEXC&lt;10:8&gt;  = '111';                                          // VECITR is RES1</line>
<line></line>
<line>    <a link="AArch32.TakeUndefInstrException.0" file="shared_pseudocode.xml" hover="function: AArch32.TakeUndefInstrException()">AArch32.TakeUndefInstrException</a>();</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/syscalls/AArch32.CallHypervisor" mylink="aarch32.exceptions.syscalls.AArch32.CallHypervisor" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.CallHypervisor()</line>
<line>// ========================</line>
<line>// Performs a HVC call</line>
<line></line>
<line link="AArch32.CallHypervisor.1" hover="function: AArch32.CallHypervisor(bits(16) immediate)" conts="AArch32.CallHypervisor"><anchor link="AArch32.CallHypervisor.1" hover="function: AArch32.CallHypervisor(bits(16) immediate)">AArch32.CallHypervisor</anchor>(bits(16) immediate)</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line></line>
<line>    if !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>        <a link="AArch64.CallHypervisor.1" file="shared_pseudocode.xml" hover="function: AArch64.CallHypervisor(bits(16) immediate)">AArch64.CallHypervisor</a>(immediate);</line>
<line>    else</line>
<line>        <a link="AArch32.TakeHVCException.1" file="shared_pseudocode.xml" hover="function: AArch32.TakeHVCException(bits(16) immediate)">AArch32.TakeHVCException</a>(immediate);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/syscalls/AArch32.CallSupervisor" mylink="aarch32.exceptions.syscalls.AArch32.CallSupervisor" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.CallSupervisor()</line>
<line>// ========================</line>
<line>// Calls the Supervisor</line>
<line></line>
<line link="AArch32.CallSupervisor.1" hover="function: AArch32.CallSupervisor(bits(16) immediate_in)" conts="AArch32.CallSupervisor"><anchor link="AArch32.CallSupervisor.1" hover="function: AArch32.CallSupervisor(bits(16) immediate_in)">AArch32.CallSupervisor</anchor>(bits(16) immediate_in)</line>
<line>    bits(16) immediate = immediate_in;</line>
<line>    if <a link="AArch32.CurrentCond.0" file="shared_pseudocode.xml" hover="function: bits(4) AArch32.CurrentCond()">AArch32.CurrentCond</a>() != '1110' then</line>
<line>        immediate = bits(16) UNKNOWN;</line>
<line>    if <a link="AArch32.GeneralExceptionsToAArch64.0" file="shared_pseudocode.xml" hover="function: boolean AArch32.GeneralExceptionsToAArch64()">AArch32.GeneralExceptionsToAArch64</a>() then</line>
<line>        <a link="AArch64.CallSupervisor.1" file="shared_pseudocode.xml" hover="function: AArch64.CallSupervisor(bits(16) immediate_in)">AArch64.CallSupervisor</a>(immediate);</line>
<line>    else</line>
<line>        <a link="AArch32.TakeSVCException.1" file="shared_pseudocode.xml" hover="function: AArch32.TakeSVCException(bits(16) immediate)">AArch32.TakeSVCException</a>(immediate);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/syscalls/AArch32.TakeHVCException" mylink="aarch32.exceptions.syscalls.AArch32.TakeHVCException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TakeHVCException()</line>
<line>// ==========================</line>
<line></line>
<line link="AArch32.TakeHVCException.1" hover="function: AArch32.TakeHVCException(bits(16) immediate)" conts="AArch32.TakeHVCException"><anchor link="AArch32.TakeHVCException.1" hover="function: AArch32.TakeHVCException(bits(16) immediate)">AArch32.TakeHVCException</anchor>(bits(16) immediate)</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line></line>
<line>    <a link="AArch32.ITAdvance.0" file="shared_pseudocode.xml" hover="function: AArch32.ITAdvance()">AArch32.ITAdvance</a>();</line>
<line>    <a link="impl-shared.SSAdvance.0" file="shared_pseudocode.xml" hover="function: SSAdvance()">SSAdvance</a>();</line>
<line>    bits(32) preferred_exception_return = <a link="impl-shared.NextInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) NextInstrAddr(integer N)">NextInstrAddr</a>(32);</line>
<line>    vect_offset = 0x08;</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_HypervisorCall" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_HypervisorCall</a>);</line>
<line>    exception.syndrome&lt;15:0&gt; = immediate;</line>
<line></line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>        <a link="AArch32.EnterHypMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterHypMode(ExceptionRecord exception, bits(32) preferred_exception_return, integer vect_offset)">AArch32.EnterHypMode</a>(exception, preferred_exception_return, vect_offset);</line>
<line>    else</line>
<line>        <a link="AArch32.EnterHypMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterHypMode(ExceptionRecord exception, bits(32) preferred_exception_return, integer vect_offset)">AArch32.EnterHypMode</a>(exception, preferred_exception_return, 0x14);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/syscalls/AArch32.TakeSMCException" mylink="aarch32.exceptions.syscalls.AArch32.TakeSMCException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TakeSMCException()</line>
<line>// ==========================</line>
<line></line>
<line link="AArch32.TakeSMCException.0" hover="function: AArch32.TakeSMCException()" conts="AArch32.TakeSMCException"><anchor link="AArch32.TakeSMCException.0" hover="function: AArch32.TakeSMCException()">AArch32.TakeSMCException</anchor>()</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>    <a link="AArch32.ITAdvance.0" file="shared_pseudocode.xml" hover="function: AArch32.ITAdvance()">AArch32.ITAdvance</a>();</line>
<line>    <a link="impl-shared.SSAdvance.0" file="shared_pseudocode.xml" hover="function: SSAdvance()">SSAdvance</a>();</line>
<line>    bits(32) preferred_exception_return = <a link="impl-shared.NextInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) NextInstrAddr(integer N)">NextInstrAddr</a>(32);</line>
<line>    vect_offset = 0x08;</line>
<line>    lr_offset = 0;</line>
<line></line>
<line>    <a link="AArch32.EnterMonitorMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterMonitorMode(bits(32) preferred_exception_return, integer lr_offset, integer vect_offset)">AArch32.EnterMonitorMode</a>(preferred_exception_return, lr_offset, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/syscalls/AArch32.TakeSVCException" mylink="aarch32.exceptions.syscalls.AArch32.TakeSVCException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TakeSVCException()</line>
<line>// ==========================</line>
<line></line>
<line link="AArch32.TakeSVCException.1" hover="function: AArch32.TakeSVCException(bits(16) immediate)" conts="AArch32.TakeSVCException"><anchor link="AArch32.TakeSVCException.1" hover="function: AArch32.TakeSVCException(bits(16) immediate)">AArch32.TakeSVCException</anchor>(bits(16) immediate)</line>
<line></line>
<line>    <a link="AArch32.ITAdvance.0" file="shared_pseudocode.xml" hover="function: AArch32.ITAdvance()">AArch32.ITAdvance</a>();</line>
<line>    <a link="impl-shared.SSAdvance.0" file="shared_pseudocode.xml" hover="function: SSAdvance()">SSAdvance</a>();</line>
<line>    route_to_hyp = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR.TGE == '1';</line>
<line></line>
<line>    bits(32) preferred_exception_return = <a link="impl-shared.NextInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) NextInstrAddr(integer N)">NextInstrAddr</a>(32);</line>
<line>    vect_offset = 0x08;</line>
<line>    lr_offset = 0;</line>
<line></line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || route_to_hyp then</line>
<line>        exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_SupervisorCall" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SupervisorCall</a>);</line>
<line>        exception.syndrome&lt;15:0&gt; = immediate;</line>
<line>        if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>            <a link="AArch32.EnterHypMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterHypMode(ExceptionRecord exception, bits(32) preferred_exception_return, integer vect_offset)">AArch32.EnterHypMode</a>(exception, preferred_exception_return, vect_offset);</line>
<line>        else</line>
<line>            <a link="AArch32.EnterHypMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterHypMode(ExceptionRecord exception, bits(32) preferred_exception_return, integer vect_offset)">AArch32.EnterHypMode</a>(exception, preferred_exception_return, 0x14);</line>
<line>    else</line>
<line>        <a link="AArch32.EnterMode.4" file="shared_pseudocode.xml" hover="function: AArch32.EnterMode(bits(5) target_mode, bits(32) preferred_exception_return, integer lr_offset, integer vect_offset)">AArch32.EnterMode</a>(<a link="M32_Svc" file="shared_pseudocode.xml" hover="constant bits(5) M32_Svc = '10011'">M32_Svc</a>, preferred_exception_return, lr_offset, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/takeexception/AArch32.EnterHypMode" mylink="aarch32.exceptions.takeexception.AArch32.EnterHypMode" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.EnterHypMode()</line>
<line>// ======================</line>
<line>// Take an exception to Hyp mode.</line>
<line></line>
<line link="AArch32.EnterHypMode.3" hover="function: AArch32.EnterHypMode(ExceptionRecord exception, bits(32) preferred_exception_return, integer vect_offset)" conts="AArch32.EnterHypMode"><anchor link="AArch32.EnterHypMode.3" hover="function: AArch32.EnterHypMode(ExceptionRecord exception, bits(32) preferred_exception_return, integer vect_offset)">AArch32.EnterHypMode</anchor>(<a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception, bits(32) preferred_exception_return,</line>
<line>                     integer vect_offset)</line>
<line>    <a link="impl-shared.SynchronizeContext.0" file="shared_pseudocode.xml" hover="function: SynchronizeContext()">SynchronizeContext</a>();</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() == <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> &amp;&amp; <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line></line>
<line>    if <a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() then</line>
<line>        <a link="AArch32.EnterHypModeInDebugState.1" file="shared_pseudocode.xml" hover="function: AArch32.EnterHypModeInDebugState(ExceptionRecord exception)">AArch32.EnterHypModeInDebugState</a>(exception);</line>
<line>        return;</line>
<line>    bits(32) spsr = <a link="impl-shared.GetPSRFromPSTATE.2" file="shared_pseudocode.xml" hover="function: bits(N) GetPSRFromPSTATE(ExceptionalOccurrenceTargetState targetELState, integer N)">GetPSRFromPSTATE</a>(<a link="AArch32_NonDebugState" file="shared_pseudocode.xml" hover="enumeration ExceptionalOccurrenceTargetState { AArch32_NonDebugState, AArch64_NonDebugState, DebugState }">AArch32_NonDebugState</a>, 32);</line>
<line>    if !(exception.exceptype IN {<a link="Exception_IRQ" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_IRQ</a>, <a link="Exception_FIQ" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FIQ</a>}) then</line>
<line>        <a link="AArch32.ReportHypEntry.1" file="shared_pseudocode.xml" hover="function: AArch32.ReportHypEntry(ExceptionRecord exception)">AArch32.ReportHypEntry</a>(exception);</line>
<line>    <a link="AArch32.WriteMode.1" file="shared_pseudocode.xml" hover="function: AArch32.WriteMode(bits(5) mode)">AArch32.WriteMode</a>(<a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a>);</line>
<line>    <a link="impl-shared.SPSR.write.0" file="shared_pseudocode.xml" hover="accessor: SPSR[] = bits(N) value">SPSR</a>[] = spsr;</line>
<line>    ELR_hyp = preferred_exception_return;</line>
<line>    PSTATE.T = HSCTLR.TE;                       // PSTATE.J is RES0</line>
<line>    PSTATE.SS = '0';</line>
<line>    if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) || <a link="impl-shared.SCR_GEN.read.0" file="shared_pseudocode.xml" hover="accessor: SCRType SCR_GEN[]">SCR_GEN</a>[].EA == '0' then PSTATE.A = '1';</line>
<line>    if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) || <a link="impl-shared.SCR_GEN.read.0" file="shared_pseudocode.xml" hover="accessor: SCRType SCR_GEN[]">SCR_GEN</a>[].IRQ == '0' then PSTATE.I = '1';</line>
<line>    if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) || <a link="impl-shared.SCR_GEN.read.0" file="shared_pseudocode.xml" hover="accessor: SCRType SCR_GEN[]">SCR_GEN</a>[].FIQ == '0' then PSTATE.F = '1';</line>
<line>    PSTATE.E = HSCTLR.EE;</line>
<line>    PSTATE.IL = '0';</line>
<line>    PSTATE.IT = '00000000';</line>
<line>    if <a link="impl-shared.HaveSSBSExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveSSBSExt()">HaveSSBSExt</a>() then PSTATE.SSBS = HSCTLR.DSSBS;</line>
<line>    boolean branch_conditional = FALSE;</line>
<line>    <a link="impl-shared.BranchTo.3" file="shared_pseudocode.xml" hover="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(HVBAR&lt;31:5&gt;:vect_offset&lt;4:0&gt;, <a link="BranchType_EXCEPTION" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_EXCEPTION</a>, branch_conditional);</line>
<line></line>
<line>    <a link="impl-shared.CheckExceptionCatch.1" file="shared_pseudocode.xml" hover="function: CheckExceptionCatch(boolean exception_entry)">CheckExceptionCatch</a>(TRUE);                  // Check for debug event on exception entry</line>
<line></line>
<line>    <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/takeexception/AArch32.EnterMode" mylink="aarch32.exceptions.takeexception.AArch32.EnterMode" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.EnterMode()</line>
<line>// ===================</line>
<line>// Take an exception to a mode other than Monitor and Hyp mode.</line>
<line></line>
<line link="AArch32.EnterMode.4" hover="function: AArch32.EnterMode(bits(5) target_mode, bits(32) preferred_exception_return, integer lr_offset, integer vect_offset)" conts="AArch32.EnterMode"><anchor link="AArch32.EnterMode.4" hover="function: AArch32.EnterMode(bits(5) target_mode, bits(32) preferred_exception_return, integer lr_offset, integer vect_offset)">AArch32.EnterMode</anchor>(bits(5) target_mode, bits(32) preferred_exception_return, integer lr_offset,</line>
<line>                  integer vect_offset)</line>
<line>    <a link="impl-shared.SynchronizeContext.0" file="shared_pseudocode.xml" hover="function: SynchronizeContext()">SynchronizeContext</a>();</line>
<line>    assert <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) &amp;&amp; PSTATE.EL != <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line></line>
<line>    if <a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() then</line>
<line>        <a link="AArch32.EnterModeInDebugState.1" file="shared_pseudocode.xml" hover="function: AArch32.EnterModeInDebugState(bits(5) target_mode)">AArch32.EnterModeInDebugState</a>(target_mode);</line>
<line>        return;</line>
<line>    bits(32) spsr = <a link="impl-shared.GetPSRFromPSTATE.2" file="shared_pseudocode.xml" hover="function: bits(N) GetPSRFromPSTATE(ExceptionalOccurrenceTargetState targetELState, integer N)">GetPSRFromPSTATE</a>(<a link="AArch32_NonDebugState" file="shared_pseudocode.xml" hover="enumeration ExceptionalOccurrenceTargetState { AArch32_NonDebugState, AArch64_NonDebugState, DebugState }">AArch32_NonDebugState</a>, 32);</line>
<line>    if PSTATE.M == <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a> then SCR.NS = '0';</line>
<line>    <a link="AArch32.WriteMode.1" file="shared_pseudocode.xml" hover="function: AArch32.WriteMode(bits(5) mode)">AArch32.WriteMode</a>(target_mode);</line>
<line>    <a link="impl-shared.SPSR.write.0" file="shared_pseudocode.xml" hover="accessor: SPSR[] = bits(N) value">SPSR</a>[] = spsr;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[14] = preferred_exception_return + lr_offset;</line>
<line>    PSTATE.T = SCTLR.TE;                        // PSTATE.J is RES0</line>
<line>    PSTATE.SS = '0';</line>
<line>    if target_mode == <a link="M32_FIQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_FIQ = '10001'">M32_FIQ</a> then</line>
<line>        PSTATE.&lt;A,I,F&gt; = '111';</line>
<line>    elsif target_mode IN {<a link="M32_Abort" file="shared_pseudocode.xml" hover="constant bits(5) M32_Abort = '10111'">M32_Abort</a>, <a link="M32_IRQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_IRQ = '10010'">M32_IRQ</a>} then</line>
<line>        PSTATE.&lt;A,I&gt; = '11';</line>
<line>    else</line>
<line>        PSTATE.I = '1';</line>
<line>    PSTATE.E = SCTLR.EE;</line>
<line>    PSTATE.IL = '0';</line>
<line>    PSTATE.IT = '00000000';</line>
<line>    if <a link="impl-shared.HavePANExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePANExt()">HavePANExt</a>() &amp;&amp; SCTLR.SPAN == '0' then PSTATE.PAN = '1';</line>
<line>    if <a link="impl-shared.HaveSSBSExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveSSBSExt()">HaveSSBSExt</a>() then PSTATE.SSBS = SCTLR.DSSBS;</line>
<line>    boolean branch_conditional = FALSE;</line>
<line>    <a link="impl-shared.BranchTo.3" file="shared_pseudocode.xml" hover="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(<a link="impl-aarch32.ExcVectorBase.0" file="shared_pseudocode.xml" hover="function: bits(32) ExcVectorBase()">ExcVectorBase</a>()&lt;31:5&gt;:vect_offset&lt;4:0&gt;, <a link="BranchType_EXCEPTION" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_EXCEPTION</a>, branch_conditional);</line>
<line></line>
<line>    <a link="impl-shared.CheckExceptionCatch.1" file="shared_pseudocode.xml" hover="function: CheckExceptionCatch(boolean exception_entry)">CheckExceptionCatch</a>(TRUE);                  // Check for debug event on exception entry</line>
<line></line>
<line>    <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/takeexception/AArch32.EnterMonitorMode" mylink="aarch32.exceptions.takeexception.AArch32.EnterMonitorMode" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.EnterMonitorMode()</line>
<line>// ==========================</line>
<line>// Take an exception to Monitor mode.</line>
<line></line>
<line link="AArch32.EnterMonitorMode.3" hover="function: AArch32.EnterMonitorMode(bits(32) preferred_exception_return, integer lr_offset, integer vect_offset)" conts="AArch32.EnterMonitorMode"><anchor link="AArch32.EnterMonitorMode.3" hover="function: AArch32.EnterMonitorMode(bits(32) preferred_exception_return, integer lr_offset, integer vect_offset)">AArch32.EnterMonitorMode</anchor>(bits(32) preferred_exception_return, integer lr_offset,</line>
<line>                         integer vect_offset)</line>
<line>    <a link="impl-shared.SynchronizeContext.0" file="shared_pseudocode.xml" hover="function: SynchronizeContext()">SynchronizeContext</a>();</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>    from_secure = <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>;</line>
<line>    if <a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() then</line>
<line>        <a link="AArch32.EnterMonitorModeInDebugState.0" file="shared_pseudocode.xml" hover="function: AArch32.EnterMonitorModeInDebugState()">AArch32.EnterMonitorModeInDebugState</a>();</line>
<line>        return;</line>
<line>    bits(32) spsr = <a link="impl-shared.GetPSRFromPSTATE.2" file="shared_pseudocode.xml" hover="function: bits(N) GetPSRFromPSTATE(ExceptionalOccurrenceTargetState targetELState, integer N)">GetPSRFromPSTATE</a>(<a link="AArch32_NonDebugState" file="shared_pseudocode.xml" hover="enumeration ExceptionalOccurrenceTargetState { AArch32_NonDebugState, AArch64_NonDebugState, DebugState }">AArch32_NonDebugState</a>, 32);</line>
<line>    if PSTATE.M == <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a> then SCR.NS = '0';</line>
<line>    <a link="AArch32.WriteMode.1" file="shared_pseudocode.xml" hover="function: AArch32.WriteMode(bits(5) mode)">AArch32.WriteMode</a>(<a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a>);</line>
<line>    <a link="impl-shared.SPSR.write.0" file="shared_pseudocode.xml" hover="accessor: SPSR[] = bits(N) value">SPSR</a>[] = spsr;</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[14] = preferred_exception_return + lr_offset;</line>
<line>    PSTATE.T = SCTLR.TE;                        // PSTATE.J is RES0</line>
<line>    PSTATE.SS = '0';</line>
<line>    PSTATE.&lt;A,I,F&gt; = '111';</line>
<line>    PSTATE.E = SCTLR.EE;</line>
<line>    PSTATE.IL = '0';</line>
<line>    PSTATE.IT = '00000000';</line>
<line>    if <a link="impl-shared.HavePANExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePANExt()">HavePANExt</a>() then</line>
<line>        if !from_secure then</line>
<line>            PSTATE.PAN = '0';</line>
<line>        elsif SCTLR.SPAN == '0' then</line>
<line>            PSTATE.PAN = '1';</line>
<line>    if <a link="impl-shared.HaveSSBSExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveSSBSExt()">HaveSSBSExt</a>() then PSTATE.SSBS = SCTLR.DSSBS;</line>
<line>    boolean branch_conditional = FALSE;</line>
<line>    <a link="impl-shared.BranchTo.3" file="shared_pseudocode.xml" hover="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(MVBAR&lt;31:5&gt;:vect_offset&lt;4:0&gt;, <a link="BranchType_EXCEPTION" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_EXCEPTION</a>, branch_conditional);</line>
<line></line>
<line>    <a link="impl-shared.CheckExceptionCatch.1" file="shared_pseudocode.xml" hover="function: CheckExceptionCatch(boolean exception_entry)">CheckExceptionCatch</a>(TRUE);                  // Check for debug event on exception entry</line>
<line></line>
<line>    <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/traps/AArch32.CheckAdvSIMDOrFPEnabled" mylink="aarch32.exceptions.traps.AArch32.CheckAdvSIMDOrFPEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.CheckAdvSIMDOrFPEnabled()</line>
<line>// =================================</line>
<line>// Check against CPACR, FPEXC, HCPTR, NSACR, and CPTR_EL3.</line>
<line></line>
<line link="AArch32.CheckAdvSIMDOrFPEnabled.2" hover="function: AArch32.CheckAdvSIMDOrFPEnabled(boolean fpexc_check, boolean advsimd)" conts="AArch32.CheckAdvSIMDOrFPEnabled"><anchor link="AArch32.CheckAdvSIMDOrFPEnabled.2" hover="function: AArch32.CheckAdvSIMDOrFPEnabled(boolean fpexc_check, boolean advsimd)">AArch32.CheckAdvSIMDOrFPEnabled</anchor>(boolean fpexc_check, boolean advsimd)</line>
<line>    if (PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) &amp;&amp;</line>
<line>          (!<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() || (!<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; HCR_EL2.TGE == '0'))) then</line>
<line>        // The PE behaves as if FPEXC.EN is 1</line>
<line>        <a link="AArch64.CheckFPEnabled.0" file="shared_pseudocode.xml" hover="function: AArch64.CheckFPEnabled()">AArch64.CheckFPEnabled</a>();</line>
<line>        <a link="AArch64.CheckFPAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();</line>
<line>    elsif (PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>             !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; HCR_EL2.TGE == '1' &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>)) then</line>
<line>        if fpexc_check &amp;&amp; HCR_EL2.RW == '0' then</line>
<line>            fpexc_en = bits(1) IMPLEMENTATION_DEFINED "FPEXC.EN value when TGE==1 and RW==0";</line>
<line>            if fpexc_en == '0' then UNDEFINED;</line>
<line>        <a link="AArch64.CheckFPEnabled.0" file="shared_pseudocode.xml" hover="function: AArch64.CheckFPEnabled()">AArch64.CheckFPEnabled</a>();</line>
<line>    else</line>
<line>        cpacr_asedis = CPACR.ASEDIS;</line>
<line>        cpacr_cp10 = CPACR.cp10;</line>
<line></line>
<line>        if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() == <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> then</line>
<line>            // Check if access disabled in NSACR</line>
<line>            if NSACR.NSASEDIS == '1' then cpacr_asedis = '1';</line>
<line>            if NSACR.cp10 == '0' then cpacr_cp10 = '00';</line>
<line></line>
<line>        if PSTATE.EL != <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>            // Check if Advanced SIMD disabled in CPACR</line>
<line>            if advsimd &amp;&amp; cpacr_asedis == '1' then UNDEFINED;</line>
<line></line>
<line>            // Check if access disabled in CPACR</line>
<line>            boolean disabled;</line>
<line>            case cpacr_cp10 of</line>
<line>                when '00' disabled = TRUE;</line>
<line>                when '01' disabled = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;</line>
<line>                when '10' disabled = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_RESCPACR" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESCPACR</a>);</line>
<line>                when '11' disabled = FALSE;</line>
<line>            if disabled then UNDEFINED;</line>
<line></line>
<line>        // If required, check FPEXC enabled bit.</line>
<line>        if fpexc_check &amp;&amp; FPEXC.EN == '0' then UNDEFINED;</line>
<line></line>
<line>        <a link="AArch32.CheckFPAdvSIMDTrap.1" file="shared_pseudocode.xml" hover="function: AArch32.CheckFPAdvSIMDTrap(boolean advsimd)">AArch32.CheckFPAdvSIMDTrap</a>(advsimd);    // Also check against HCPTR and CPTR_EL3</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/traps/AArch32.CheckFPAdvSIMDTrap" mylink="aarch32.exceptions.traps.AArch32.CheckFPAdvSIMDTrap" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.CheckFPAdvSIMDTrap()</line>
<line>// ============================</line>
<line>// Check against CPTR_EL2 and CPTR_EL3.</line>
<line></line>
<line link="AArch32.CheckFPAdvSIMDTrap.1" hover="function: AArch32.CheckFPAdvSIMDTrap(boolean advsimd)" conts="AArch32.CheckFPAdvSIMDTrap"><anchor link="AArch32.CheckFPAdvSIMDTrap.1" hover="function: AArch32.CheckFPAdvSIMDTrap(boolean advsimd)">AArch32.CheckFPAdvSIMDTrap</anchor>(boolean advsimd)</line>
<line>    if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>        <a link="AArch64.CheckFPAdvSIMDTrap.0" file="shared_pseudocode.xml" hover="function: AArch64.CheckFPAdvSIMDTrap()">AArch64.CheckFPAdvSIMDTrap</a>();</line>
<line>    else</line>
<line>        if (<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp;</line>
<line>            CPTR_EL3.TFP == '1' &amp;&amp; <a link="impl-shared.EL3SDDUndefPriority.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndefPriority()">EL3SDDUndefPriority</a>()) then</line>
<line>            UNDEFINED;</line>
<line></line>
<line>        ss = <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>();</line>
<line>        if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; ss != <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>            hcptr_tase = HCPTR.TASE;</line>
<line>            hcptr_cp10 = HCPTR.TCP10;</line>
<line></line>
<line>            if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>                // Check if access disabled in NSACR</line>
<line>                if NSACR.NSASEDIS == '1' then hcptr_tase = '1';</line>
<line>                if NSACR.cp10 == '0' then hcptr_cp10 = '1';</line>
<line></line>
<line>            // Check if access disabled in HCPTR</line>
<line>            if (advsimd &amp;&amp; hcptr_tase == '1') || hcptr_cp10 == '1' then</line>
<line>                exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_AdvSIMDFPAccessTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_AdvSIMDFPAccessTrap</a>);</line>
<line>                exception.syndrome&lt;24:20&gt; = <a link="impl-shared.ConditionSyndrome.0" file="shared_pseudocode.xml" hover="function: bits(5) ConditionSyndrome()">ConditionSyndrome</a>();</line>
<line></line>
<line>                if advsimd then</line>
<line>                    exception.syndrome&lt;5&gt; = '1';</line>
<line>                else</line>
<line>                    exception.syndrome&lt;5&gt; = '0';</line>
<line>                    exception.syndrome&lt;3:0&gt; = '1010';         // coproc field, always 0xA</line>
<line></line>
<line>                if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>                    <a link="AArch32.TakeUndefInstrException.1" file="shared_pseudocode.xml" hover="function: AArch32.TakeUndefInstrException(ExceptionRecord exception)">AArch32.TakeUndefInstrException</a>(exception);</line>
<line>                else</line>
<line>                    <a link="AArch32.TakeHypTrapException.1" file="shared_pseudocode.xml" hover="function: AArch32.TakeHypTrapException(integer ec)">AArch32.TakeHypTrapException</a>(exception);</line>
<line></line>
<line>        if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>            // Check if access disabled in CPTR_EL3</line>
<line>            if CPTR_EL3.TFP == '1' then</line>
<line>                if <a link="impl-shared.EL3SDDUndef.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndef()">EL3SDDUndef</a>() then</line>
<line>                    UNDEFINED;</line>
<line>                else</line>
<line>                    <a link="AArch64.AdvSIMDFPAccessTrap.1" file="shared_pseudocode.xml" hover="function: AArch64.AdvSIMDFPAccessTrap(bits(2) target_el)">AArch64.AdvSIMDFPAccessTrap</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/traps/AArch32.CheckForSMCUndefOrTrap" mylink="aarch32.exceptions.traps.AArch32.CheckForSMCUndefOrTrap" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.CheckForSMCUndefOrTrap()</line>
<line>// ================================</line>
<line>// Check for UNDEFINED or trap on SMC instruction</line>
<line></line>
<line link="AArch32.CheckForSMCUndefOrTrap.0" hover="function: AArch32.CheckForSMCUndefOrTrap()" conts="AArch32.CheckForSMCUndefOrTrap"><anchor link="AArch32.CheckForSMCUndefOrTrap.0" hover="function: AArch32.CheckForSMCUndefOrTrap()">AArch32.CheckForSMCUndefOrTrap</anchor>()</line>
<line>    if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) || PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        UNDEFINED;</line>
<line></line>
<line>    if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>        <a link="AArch64.CheckForSMCUndefOrTrap.1" file="shared_pseudocode.xml" hover="function: AArch64.CheckForSMCUndefOrTrap(bits(16) imm)">AArch64.CheckForSMCUndefOrTrap</a>(<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16));</line>
<line>    else</line>
<line>        route_to_hyp = <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; HCR.TSC == '1';</line>
<line>        if route_to_hyp then</line>
<line>            exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_MonitorCall" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_MonitorCall</a>);</line>
<line>            <a link="AArch32.TakeHypTrapException.1" file="shared_pseudocode.xml" hover="function: AArch32.TakeHypTrapException(integer ec)">AArch32.TakeHypTrapException</a>(exception);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/traps/AArch32.CheckForSVCTrap" mylink="aarch32.exceptions.traps.AArch32.CheckForSVCTrap" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.CheckForSVCTrap()</line>
<line>// =========================</line>
<line>// Check for trap on SVC instruction</line>
<line></line>
<line link="AArch32.CheckForSVCTrap.1" hover="function: AArch32.CheckForSVCTrap(bits(16) immediate)" conts="AArch32.CheckForSVCTrap"><anchor link="AArch32.CheckForSVCTrap.1" hover="function: AArch32.CheckForSVCTrap(bits(16) immediate)">AArch32.CheckForSVCTrap</anchor>(bits(16) immediate)</line>
<line>    if <a link="impl-shared.HaveFGTExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveFGTExt()">HaveFGTExt</a>() then</line>
<line>        route_to_el2 = FALSE;</line>
<line>        if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>            route_to_el2 = (!<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HFGITR_EL2.SVC_EL0 == '1' &amp;&amp;</line>
<line>                           (HCR_EL2.&lt;E2H, TGE&gt; != '11' &amp;&amp; (!<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) || SCR_EL3.FGTEn == '1')));</line>
<line></line>
<line>        if route_to_el2 then</line>
<line>            exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_SupervisorCall" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SupervisorCall</a>);</line>
<line>            exception.syndrome&lt;15:0&gt; = immediate;</line>
<line>            exception.trappedsyscallinst = TRUE;</line>
<line>            bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>            vect_offset = 0x0;</line>
<line></line>
<line>            <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/traps/AArch32.CheckForWFxTrap" mylink="aarch32.exceptions.traps.AArch32.CheckForWFxTrap" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.CheckForWFxTrap()</line>
<line>// =========================</line>
<line>// Check for trap on WFE or WFI instruction</line>
<line></line>
<line link="AArch32.CheckForWFxTrap.2" hover="function: AArch32.CheckForWFxTrap(bits(2) target_el, WFxType wfxtype)" conts="AArch32.CheckForWFxTrap"><anchor link="AArch32.CheckForWFxTrap.2" hover="function: AArch32.CheckForWFxTrap(bits(2) target_el, WFxType wfxtype)">AArch32.CheckForWFxTrap</anchor>(bits(2) target_el, <a link="WFxType" file="shared_pseudocode.xml" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType</a> wfxtype)</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(target_el);</line>
<line></line>
<line>    // Check for routing to AArch64</line>
<line>    if !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(target_el) then</line>
<line>        <a link="AArch64.CheckForWFxTrap.2" file="shared_pseudocode.xml" hover="function: AArch64.CheckForWFxTrap(bits(2) target_el, WFxType wfxtype)">AArch64.CheckForWFxTrap</a>(target_el, wfxtype);</line>
<line>        return;</line>
<line></line>
<line>    boolean is_wfe = wfxtype == <a link="WFxType_WFE" file="shared_pseudocode.xml" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFE</a>;</line>
<line>    boolean trap;</line>
<line>    case target_el of</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            trap = (if is_wfe then SCTLR.nTWE else SCTLR.nTWI) == '0';</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            trap = (if is_wfe then HCR.TWE else HCR.TWI) == '1';</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            trap = (if is_wfe then SCR.TWE else SCR.TWI) == '1';</line>
<line></line>
<line>    if trap then</line>
<line>        if target_el == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; HCR_EL2.TGE == '1' then</line>
<line>            <a link="AArch64.WFxTrap.2" file="shared_pseudocode.xml" hover="function: AArch64.WFxTrap(WFxType wfxtype, bits(2) target_el)">AArch64.WFxTrap</a>(wfxtype, target_el);</line>
<line></line>
<line>        if target_el == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then</line>
<line>            <a link="AArch32.TakeMonitorTrapException.0" file="shared_pseudocode.xml" hover="function: AArch32.TakeMonitorTrapException()">AArch32.TakeMonitorTrapException</a>();</line>
<line>        elsif target_el == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>            exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_WFxTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_WFxTrap</a>);</line>
<line>            exception.syndrome&lt;24:20&gt; = <a link="impl-shared.ConditionSyndrome.0" file="shared_pseudocode.xml" hover="function: bits(5) ConditionSyndrome()">ConditionSyndrome</a>();</line>
<line></line>
<line>            case wfxtype of</line>
<line>                when <a link="WFxType_WFI" file="shared_pseudocode.xml" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFI</a></line>
<line>                    exception.syndrome&lt;0&gt; = '0';</line>
<line>                when <a link="WFxType_WFE" file="shared_pseudocode.xml" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFE</a></line>
<line>                    exception.syndrome&lt;0&gt; = '1';</line>
<line></line>
<line>            <a link="AArch32.TakeHypTrapException.1" file="shared_pseudocode.xml" hover="function: AArch32.TakeHypTrapException(integer ec)">AArch32.TakeHypTrapException</a>(exception);</line>
<line>        else</line>
<line>            <a link="AArch32.TakeUndefInstrException.0" file="shared_pseudocode.xml" hover="function: AArch32.TakeUndefInstrException()">AArch32.TakeUndefInstrException</a>();</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/traps/AArch32.CheckITEnabled" mylink="aarch32.exceptions.traps.AArch32.CheckITEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.CheckITEnabled()</line>
<line>// ========================</line>
<line>// Check whether the T32 IT instruction is disabled.</line>
<line></line>
<line link="AArch32.CheckITEnabled.1" hover="function: AArch32.CheckITEnabled(bits(4) mask)" conts="AArch32.CheckITEnabled"><anchor link="AArch32.CheckITEnabled.1" hover="function: AArch32.CheckITEnabled(bits(4) mask)">AArch32.CheckITEnabled</anchor>(bits(4) mask)</line>
<line>    bit it_disabled;</line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>        it_disabled = HSCTLR.ITD;</line>
<line>    else</line>
<line>        it_disabled = (if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then SCTLR.ITD else SCTLR[].ITD);</line>
<line>    if it_disabled == '1' then</line>
<line>        if mask != '1000' then UNDEFINED;</line>
<line></line>
<line>        accdesc = <a link="impl-shared.CreateAccDescIFetch.0" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescIFetch()">CreateAccDescIFetch</a>();</line>
<line>        aligned = TRUE;</line>
<line>        // Otherwise whether the IT block is allowed depends on hw1 of the next instruction.</line>
<line>        next_instr = <a link="AArch32.MemSingle.read.4" file="shared_pseudocode.xml" hover="accessor: bits(size*8) AArch32.MemSingle[bits(32) address, integer size, AccessDescriptor accdesc, boolean aligned]">AArch32.MemSingle</a>[<a link="impl-shared.NextInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) NextInstrAddr(integer N)">NextInstrAddr</a>(32), 2, accdesc, aligned];</line>
<line></line>
<line>        if next_instr IN {'11xxxxxxxxxxxxxx', '1011xxxxxxxxxxxx', '10100xxxxxxxxxxx',</line>
<line>                          '01001xxxxxxxxxxx', '010001xxx1111xxx', '010001xx1xxxx111'} then</line>
<line>            // It is IMPLEMENTATION DEFINED whether the Undefined Instruction exception is</line>
<line>            // taken on the IT instruction or the next instruction. This is not reflected in</line>
<line>            // the pseudocode, which always takes the exception on the IT instruction. This</line>
<line>            // also does not take into account cases where the next instruction is UNPREDICTABLE.</line>
<line>            UNDEFINED;</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/traps/AArch32.CheckIllegalState" mylink="aarch32.exceptions.traps.AArch32.CheckIllegalState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.CheckIllegalState()</line>
<line>// ===========================</line>
<line>// Check PSTATE.IL bit and generate Illegal Execution state exception if set.</line>
<line></line>
<line link="AArch32.CheckIllegalState.0" hover="function: AArch32.CheckIllegalState()" conts="AArch32.CheckIllegalState"><anchor link="AArch32.CheckIllegalState.0" hover="function: AArch32.CheckIllegalState()">AArch32.CheckIllegalState</anchor>()</line>
<line>    if <a link="AArch32.GeneralExceptionsToAArch64.0" file="shared_pseudocode.xml" hover="function: boolean AArch32.GeneralExceptionsToAArch64()">AArch32.GeneralExceptionsToAArch64</a>() then</line>
<line>        <a link="AArch64.CheckIllegalState.0" file="shared_pseudocode.xml" hover="function: AArch64.CheckIllegalState()">AArch64.CheckIllegalState</a>();</line>
<line>    elsif PSTATE.IL == '1' then</line>
<line>        route_to_hyp = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR.TGE == '1';</line>
<line></line>
<line>        bits(32) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(32);</line>
<line>        vect_offset = 0x04;</line>
<line></line>
<line>        if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || route_to_hyp then</line>
<line>            exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_IllegalState" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_IllegalState</a>);</line>
<line>            if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>                <a link="AArch32.EnterHypMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterHypMode(ExceptionRecord exception, bits(32) preferred_exception_return, integer vect_offset)">AArch32.EnterHypMode</a>(exception, preferred_exception_return, vect_offset);</line>
<line>            else</line>
<line>                <a link="AArch32.EnterHypMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterHypMode(ExceptionRecord exception, bits(32) preferred_exception_return, integer vect_offset)">AArch32.EnterHypMode</a>(exception, preferred_exception_return, 0x14);</line>
<line>        else</line>
<line>            <a link="AArch32.TakeUndefInstrException.0" file="shared_pseudocode.xml" hover="function: AArch32.TakeUndefInstrException()">AArch32.TakeUndefInstrException</a>();</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/traps/AArch32.CheckSETENDEnabled" mylink="aarch32.exceptions.traps.AArch32.CheckSETENDEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.CheckSETENDEnabled()</line>
<line>// ============================</line>
<line>// Check whether the AArch32 SETEND instruction is disabled.</line>
<line></line>
<line link="AArch32.CheckSETENDEnabled.0" hover="function: AArch32.CheckSETENDEnabled()" conts="AArch32.CheckSETENDEnabled"><anchor link="AArch32.CheckSETENDEnabled.0" hover="function: AArch32.CheckSETENDEnabled()">AArch32.CheckSETENDEnabled</anchor>()</line>
<line>    bit setend_disabled;</line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>        setend_disabled = HSCTLR.SED;</line>
<line>    else</line>
<line>        setend_disabled = (if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then SCTLR.SED else SCTLR[].SED);</line>
<line>    if setend_disabled == '1' then</line>
<line>        UNDEFINED;</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/traps/AArch32.SystemAccessTrap" mylink="aarch32.exceptions.traps.AArch32.SystemAccessTrap" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.SystemAccessTrap()</line>
<line>// ==========================</line>
<line>// Trapped  System register access.</line>
<line></line>
<line link="AArch32.SystemAccessTrap.2" hover="function: AArch32.SystemAccessTrap(bits(5) mode, integer ec)" conts="AArch32.SystemAccessTrap"><anchor link="AArch32.SystemAccessTrap.2" hover="function: AArch32.SystemAccessTrap(bits(5) mode, integer ec)">AArch32.SystemAccessTrap</anchor>(bits(5) mode, integer ec)</line>
<line>    (valid, target_el) = <a link="impl-shared.ELFromM32.1" file="shared_pseudocode.xml" hover="function: (boolean,bits(2)) ELFromM32(bits(5) mode)">ELFromM32</a>(mode);</line>
<line>    assert valid &amp;&amp; <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(target_el) &amp;&amp; target_el != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(target_el) &gt;= <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL);</line>
<line></line>
<line>    if target_el == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>        exception = <a link="AArch32.SystemAccessTrapSyndrome.2" file="shared_pseudocode.xml" hover="function: ExceptionRecord AArch32.SystemAccessTrapSyndrome(bits(32) instr, integer ec)">AArch32.SystemAccessTrapSyndrome</a>(<a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>(), ec);</line>
<line>        <a link="AArch32.TakeHypTrapException.1" file="shared_pseudocode.xml" hover="function: AArch32.TakeHypTrapException(integer ec)">AArch32.TakeHypTrapException</a>(exception);</line>
<line>    else</line>
<line>        <a link="AArch32.TakeUndefInstrException.0" file="shared_pseudocode.xml" hover="function: AArch32.TakeUndefInstrException()">AArch32.TakeUndefInstrException</a>();</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/traps/AArch32.SystemAccessTrapSyndrome" mylink="aarch32.exceptions.traps.AArch32.SystemAccessTrapSyndrome" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.SystemAccessTrapSyndrome()</line>
<line>// ==================================</line>
<line>// Returns the syndrome information for traps on AArch32 MCR, MCRR, MRC, MRRC, and VMRS,</line>
<line>// VMSR instructions, other than traps that are due to HCPTR or CPACR.</line>
<line></line>
<line link="AArch32.SystemAccessTrapSyndrome.2" hover="function: ExceptionRecord AArch32.SystemAccessTrapSyndrome(bits(32) instr, integer ec)" conts="AArch32.SystemAccessTrapSyndrome">ExceptionRecord <anchor link="AArch32.SystemAccessTrapSyndrome.2" hover="function: ExceptionRecord AArch32.SystemAccessTrapSyndrome(bits(32) instr, integer ec)">AArch32.SystemAccessTrapSyndrome</anchor>(bits(32) instr, integer ec)</line>
<line>    <a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception;</line>
<line></line>
<line>    case ec of</line>
<line>        when 0x0    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_Uncategorized" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Uncategorized</a>);</line>
<line>        when 0x3    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_CP15RTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP15RTTrap</a>);</line>
<line>        when 0x4    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_CP15RRTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP15RRTTrap</a>);</line>
<line>        when 0x5    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_CP14RTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14RTTrap</a>);</line>
<line>        when 0x6    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_CP14DTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14DTTrap</a>);</line>
<line>        when 0x7    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_AdvSIMDFPAccessTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_AdvSIMDFPAccessTrap</a>);</line>
<line>        when 0x8    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_FPIDTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FPIDTrap</a>);</line>
<line>        when 0xC    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_CP14RRTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14RRTTrap</a>);</line>
<line>        otherwise   <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    bits(20) iss = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(20);</line>
<line></line>
<line>    if exception.exceptype == <a link="Exception_Uncategorized" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Uncategorized</a> then</line>
<line>        return exception;</line>
<line>    elsif exception.exceptype IN {<a link="Exception_FPIDTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FPIDTrap</a>, <a link="Exception_CP14RTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14RTTrap</a>,</line>
<line>                                  <a link="Exception_CP15RTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP15RTTrap</a>} then</line>
<line>        // Trapped MRC/MCR, VMRS on FPSID</line>
<line>        iss&lt;13:10&gt; = instr&lt;19:16&gt;;        // CRn, Reg in case of VMRS</line>
<line>        iss&lt;8:5&gt;   = instr&lt;15:12&gt;;        // Rt</line>
<line>        iss&lt;9&gt;     = '0';                 // RES0</line>
<line></line>
<line>        if exception.exceptype != <a link="Exception_FPIDTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FPIDTrap</a> then    // When trap is not for VMRS</line>
<line>            iss&lt;19:17&gt; = instr&lt;7:5&gt;;          // opc2</line>
<line>            iss&lt;16:14&gt; = instr&lt;23:21&gt;;        // opc1</line>
<line>            iss&lt;4:1&gt;   = instr&lt;3:0&gt;;          //CRm</line>
<line>        else //VMRS Access</line>
<line>            iss&lt;19:17&gt; = '000';               //opc2 - Hardcoded for VMRS</line>
<line>            iss&lt;16:14&gt; = '111';               //opc1 - Hardcoded for VMRS</line>
<line>            iss&lt;4:1&gt;   = '0000';              //CRm  - Hardcoded for VMRS</line>
<line>    elsif exception.exceptype IN {<a link="Exception_CP14RRTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14RRTTrap</a>, <a link="Exception_AdvSIMDFPAccessTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_AdvSIMDFPAccessTrap</a>,</line>
<line>                                  <a link="Exception_CP15RRTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP15RRTTrap</a>} then</line>
<line>        // Trapped MRRC/MCRR, VMRS/VMSR</line>
<line>        iss&lt;19:16&gt; = instr&lt;7:4&gt;;          // opc1</line>
<line>        iss&lt;13:10&gt; = instr&lt;19:16&gt;;        // Rt2</line>
<line>        iss&lt;8:5&gt; = instr&lt;15:12&gt;;          // Rt</line>
<line>        iss&lt;4:1&gt;   = instr&lt;3:0&gt;;         // CRm</line>
<line>    elsif exception.exceptype == <a link="Exception_CP14DTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14DTTrap</a> then</line>
<line>        // Trapped LDC/STC</line>
<line>        iss&lt;19:12&gt; = instr&lt;7:0&gt;;         // imm8</line>
<line>        iss&lt;4&gt;     = instr&lt;23&gt;;          // U</line>
<line>        iss&lt;2:1&gt;   = instr&lt;24,21&gt;;       // P,W</line>
<line>        if instr&lt;19:16&gt; == '1111' then   // Rn==15, LDC(Literal addressing)/STC</line>
<line>            iss&lt;8:5&gt; = bits(4) UNKNOWN;</line>
<line>            iss&lt;3&gt;   = '1';</line>
<line>    iss&lt;0&gt; = instr&lt;20&gt;;                  // Direction</line>
<line></line>
<line>    exception.syndrome&lt;24:20&gt; = <a link="impl-shared.ConditionSyndrome.0" file="shared_pseudocode.xml" hover="function: bits(5) ConditionSyndrome()">ConditionSyndrome</a>();</line>
<line>    exception.syndrome&lt;19:0&gt;  = iss;</line>
<line></line>
<line>    return exception;</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/traps/AArch32.TakeHypTrapException" mylink="aarch32.exceptions.traps.AArch32.TakeHypTrapException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TakeHypTrapException()</line>
<line>// ==============================</line>
<line>// Exceptions routed to Hyp mode as a Hyp Trap exception.</line>
<line></line>
<line link="AArch32.TakeHypTrapException.1" hover="function: AArch32.TakeHypTrapException(integer ec)" conts="AArch32.TakeHypTrapException"><anchor link="AArch32.TakeHypTrapException.1" hover="function: AArch32.TakeHypTrapException(integer ec)">AArch32.TakeHypTrapException</anchor>(integer ec)</line>
<line>    exception = <a link="AArch32.SystemAccessTrapSyndrome.2" file="shared_pseudocode.xml" hover="function: ExceptionRecord AArch32.SystemAccessTrapSyndrome(bits(32) instr, integer ec)">AArch32.SystemAccessTrapSyndrome</a>(<a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>(), ec);</line>
<line>    <a link="AArch32.TakeHypTrapException.1" file="shared_pseudocode.xml" hover="function: AArch32.TakeHypTrapException(integer ec)">AArch32.TakeHypTrapException</a>(exception);</line>
<line></line>
<line>// AArch32.TakeHypTrapException()</line>
<line>// ==============================</line>
<line>// Exceptions routed to Hyp mode as a Hyp Trap exception.</line>
<line></line>
<line><a link="AArch32.TakeHypTrapException.1" file="shared_pseudocode.xml" hover="function: AArch32.TakeHypTrapException(integer ec)">AArch32.TakeHypTrapException</a>(<a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception)</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() == <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> &amp;&amp; <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line></line>
<line>    bits(32) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(32);</line>
<line>    vect_offset = 0x14;</line>
<line></line>
<line>    <a link="AArch32.EnterHypMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterHypMode(ExceptionRecord exception, bits(32) preferred_exception_return, integer vect_offset)">AArch32.EnterHypMode</a>(exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/traps/AArch32.TakeMonitorTrapException" mylink="aarch32.exceptions.traps.AArch32.TakeMonitorTrapException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TakeMonitorTrapException()</line>
<line>// ==================================</line>
<line>// Exceptions routed to Monitor mode as a Monitor Trap exception.</line>
<line></line>
<line link="AArch32.TakeMonitorTrapException.0" hover="function: AArch32.TakeMonitorTrapException()" conts="AArch32.TakeMonitorTrapException"><anchor link="AArch32.TakeMonitorTrapException.0" hover="function: AArch32.TakeMonitorTrapException()">AArch32.TakeMonitorTrapException</anchor>()</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line></line>
<line>    bits(32) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(32);</line>
<line>    vect_offset = 0x04;</line>
<line>    lr_offset = if <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then 4 else 2;</line>
<line></line>
<line>    <a link="AArch32.EnterMonitorMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterMonitorMode(bits(32) preferred_exception_return, integer lr_offset, integer vect_offset)">AArch32.EnterMonitorMode</a>(preferred_exception_return, lr_offset, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/traps/AArch32.TakeUndefInstrException" mylink="aarch32.exceptions.traps.AArch32.TakeUndefInstrException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TakeUndefInstrException()</line>
<line>// =================================</line>
<line></line>
<line link="AArch32.TakeUndefInstrException.0" hover="function: AArch32.TakeUndefInstrException()" conts="AArch32.TakeUndefInstrException"><anchor link="AArch32.TakeUndefInstrException.0" hover="function: AArch32.TakeUndefInstrException()">AArch32.TakeUndefInstrException</anchor>()</line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_Uncategorized" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Uncategorized</a>);</line>
<line>    <a link="AArch32.TakeUndefInstrException.1" file="shared_pseudocode.xml" hover="function: AArch32.TakeUndefInstrException(ExceptionRecord exception)">AArch32.TakeUndefInstrException</a>(exception);</line>
<line></line>
<line>// AArch32.TakeUndefInstrException()</line>
<line>// =================================</line>
<line></line>
<line link="AArch32.TakeUndefInstrException.1" hover="function: AArch32.TakeUndefInstrException(ExceptionRecord exception)" conts="AArch32.TakeUndefInstrException"><anchor link="AArch32.TakeUndefInstrException.1" hover="function: AArch32.TakeUndefInstrException(ExceptionRecord exception)">AArch32.TakeUndefInstrException</anchor>(<a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception)</line>
<line></line>
<line>    route_to_hyp = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR.TGE == '1';</line>
<line>    bits(32) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(32);</line>
<line>    vect_offset = 0x04;</line>
<line>    lr_offset = if <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then 4 else 2;</line>
<line></line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>        <a link="AArch32.EnterHypMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterHypMode(ExceptionRecord exception, bits(32) preferred_exception_return, integer vect_offset)">AArch32.EnterHypMode</a>(exception, preferred_exception_return, vect_offset);</line>
<line>    elsif route_to_hyp then</line>
<line>        <a link="AArch32.EnterHypMode.3" file="shared_pseudocode.xml" hover="function: AArch32.EnterHypMode(ExceptionRecord exception, bits(32) preferred_exception_return, integer vect_offset)">AArch32.EnterHypMode</a>(exception, preferred_exception_return, 0x14);</line>
<line>    else</line>
<line>        <a link="AArch32.EnterMode.4" file="shared_pseudocode.xml" hover="function: AArch32.EnterMode(bits(5) target_mode, bits(32) preferred_exception_return, integer lr_offset, integer vect_offset)">AArch32.EnterMode</a>(<a link="M32_Undef" file="shared_pseudocode.xml" hover="constant bits(5) M32_Undef = '11011'">M32_Undef</a>, preferred_exception_return, lr_offset, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch32/exceptions/traps/AArch32.UndefinedFault" mylink="aarch32.exceptions.traps.AArch32.UndefinedFault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.UndefinedFault()</line>
<line>// ========================</line>
<line></line>
<line link="AArch32.UndefinedFault.0" hover="function: AArch32.UndefinedFault()" conts="AArch32.UndefinedFault"><anchor link="AArch32.UndefinedFault.0" hover="function: AArch32.UndefinedFault()">AArch32.UndefinedFault</anchor>()</line>
<line></line>
<line>    if <a link="AArch32.GeneralExceptionsToAArch64.0" file="shared_pseudocode.xml" hover="function: boolean AArch32.GeneralExceptionsToAArch64()">AArch32.GeneralExceptionsToAArch64</a>() then <a link="AArch64.UndefinedFault.0" file="shared_pseudocode.xml" hover="function: AArch64.UndefinedFault()">AArch64.UndefinedFault</a>();</line>
<line>    <a link="AArch32.TakeUndefInstrException.0" file="shared_pseudocode.xml" hover="function: AArch32.TakeUndefInstrException()">AArch32.TakeUndefInstrException</a>();</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/aborts/AArch32.DomainValid" mylink="aarch32.functions.aborts.AArch32.DomainValid" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.DomainValid()</line>
<line>// =====================</line>
<line>// Returns TRUE if the Domain is valid for a Short-descriptor translation scheme.</line>
<line></line>
<line link="AArch32.DomainValid.2" hover="function: boolean AArch32.DomainValid(Fault statuscode, integer level)" conts="AArch32.DomainValid">boolean <anchor link="AArch32.DomainValid.2" hover="function: boolean AArch32.DomainValid(Fault statuscode, integer level)">AArch32.DomainValid</anchor>(<a link="Fault" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault</a> statuscode, integer level)</line>
<line>    assert statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a>;</line>
<line></line>
<line>    case statuscode of</line>
<line>        when <a link="Fault_Domain" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Domain</a></line>
<line>            return TRUE;</line>
<line>        when <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>, <a link="Fault_AccessFlag" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AccessFlag</a>, <a link="Fault_SyncExternalOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncExternalOnWalk</a>, <a link="Fault_SyncParityOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncParityOnWalk</a></line>
<line>            return level == 2;</line>
<line>        otherwise</line>
<line>            return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/aborts/AArch32.FaultSyndrome" mylink="aarch32.functions.aborts.AArch32.FaultSyndrome" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.FaultSyndrome()</line>
<line>// =======================</line>
<line>// Creates an exception syndrome value for Abort and Watchpoint exceptions taken to</line>
<line>// AArch32 Hyp mode.</line>
<line></line>
<line link="AArch32.FaultSyndrome.2" hover="function: bits(25) AArch32.FaultSyndrome(boolean d_side, FaultRecord fault)" conts="AArch32.FaultSyndrome">bits(25) <anchor link="AArch32.FaultSyndrome.2" hover="function: bits(25) AArch32.FaultSyndrome(boolean d_side, FaultRecord fault)">AArch32.FaultSyndrome</anchor>(boolean d_side, <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    assert fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a>;</line>
<line></line>
<line>    bits(25) iss  = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(25);</line>
<line>    bits(24) iss2 = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(24);</line>
<line></line>
<line>    if <a link="impl-shared.HaveRASExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveRASExt()">HaveRASExt</a>() &amp;&amp; <a link="impl-shared.IsAsyncAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsAsyncAbort(Fault statuscode)">IsAsyncAbort</a>(fault) then</line>
<line>        <a link="ErrorState" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState</a> errstate = <a link="AArch32.PEErrorState.1" file="shared_pseudocode.xml" hover="function: ErrorState AArch32.PEErrorState(FaultRecord fault)">AArch32.PEErrorState</a>(fault);</line>
<line>        iss&lt;11:10&gt; = <a link="AArch32.EncodeAsyncErrorSyndrome.1" file="shared_pseudocode.xml" hover="function: bits(2) AArch32.EncodeAsyncErrorSyndrome(ErrorState errorstate)">AArch32.EncodeAsyncErrorSyndrome</a>(errstate); // AET</line>
<line></line>
<line>    if d_side then</line>
<line>        if (<a link="impl-shared.IsSecondStage.1" file="shared_pseudocode.xml" hover="function: boolean IsSecondStage(FaultRecord fault)">IsSecondStage</a>(fault) &amp;&amp; !fault.s2fs1walk &amp;&amp;</line>
<line>            (!<a link="impl-shared.IsExternalSyncAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalSyncAbort(Fault statuscode)">IsExternalSyncAbort</a>(fault) ||</line>
<line>            (!<a link="impl-shared.HaveRASExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveRASExt()">HaveRASExt</a>() &amp;&amp; fault.access.acctype == <a link="AccessType_TTW" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_TTW</a> &amp;&amp;</line>
<line>            boolean IMPLEMENTATION_DEFINED "ISV on second stage translation table walk"))) then</line>
<line>            iss&lt;24:14&gt; = <a link="impl-shared.LSInstructionSyndrome.0" file="shared_pseudocode.xml" hover="function: bits(11) LSInstructionSyndrome()">LSInstructionSyndrome</a>();</line>
<line></line>
<line>        if fault.access.acctype IN {<a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>, <a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a>, <a link="AccessType_AT" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_AT</a>} then</line>
<line>            iss&lt;8&gt; = '1';</line>
<line></line>
<line>        if fault.access.acctype IN {<a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>, <a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a>, <a link="AccessType_AT" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_AT</a>} then</line>
<line>            iss&lt;6&gt; = '1';</line>
<line>        elsif fault.statuscode IN {<a link="Fault_HWUpdateAccessFlag" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_HWUpdateAccessFlag</a>, <a link="Fault_Exclusive" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Exclusive</a>} then</line>
<line>            iss&lt;6&gt; = bit UNKNOWN;</line>
<line>        elsif fault.access.atomicop &amp;&amp; <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault) then</line>
<line>            iss&lt;6&gt; = bit UNKNOWN;</line>
<line>        else</line>
<line>            iss&lt;6&gt; = if fault.write then '1' else '0';</line>
<line></line>
<line>    if <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault) then iss&lt;9&gt; = fault.extflag;</line>
<line>    iss&lt;7&gt; = if fault.s2fs1walk then '1' else '0';</line>
<line>    iss&lt;5:0&gt; = <a link="impl-shared.EncodeLDFSC.2" file="shared_pseudocode.xml" hover="function: bits(6) EncodeLDFSC(Fault statuscode, integer level)">EncodeLDFSC</a>(fault.statuscode, fault.level);</line>
<line></line>
<line>    return (iss);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/aborts/EncodeSDFSC" mylink="aarch32.functions.aborts.EncodeSDFSC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EncodeSDFSC()</line>
<line>// =============</line>
<line>// Function that gives the Short-descriptor FSR code for different types of Fault</line>
<line></line>
<line link="impl-aarch32.EncodeSDFSC.2" hover="function: bits(5) EncodeSDFSC(Fault statuscode, integer level)" conts="EncodeSDFSC">bits(5) <anchor link="impl-aarch32.EncodeSDFSC.2" hover="function: bits(5) EncodeSDFSC(Fault statuscode, integer level)">EncodeSDFSC</anchor>(<a link="Fault" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault</a> statuscode, integer level)</line>
<line></line>
<line>    bits(5) result;</line>
<line>    case statuscode of</line>
<line>        when <a link="Fault_AccessFlag" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AccessFlag</a></line>
<line>            assert level IN {1,2};</line>
<line>            result = if level == 1 then '00011' else '00110';</line>
<line>        when <a link="Fault_Alignment" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Alignment</a></line>
<line>            result = '00001';</line>
<line>        when <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a></line>
<line>            assert level IN {1,2};</line>
<line>            result = if level == 1 then '01101' else '01111';</line>
<line>        when <a link="Fault_Domain" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Domain</a></line>
<line>            assert level IN {1,2};</line>
<line>            result = if level == 1 then '01001' else '01011';</line>
<line>        when <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a></line>
<line>            assert level IN {1,2};</line>
<line>            result = if level == 1 then '00101' else '00111';</line>
<line>        when <a link="Fault_SyncExternal" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncExternal</a></line>
<line>            result = '01000';</line>
<line>        when <a link="Fault_SyncExternalOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncExternalOnWalk</a></line>
<line>            assert level IN {1,2};</line>
<line>            result = if level == 1 then '01100' else '01110';</line>
<line>        when <a link="Fault_SyncParity" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncParity</a></line>
<line>            result = '11001';</line>
<line>        when <a link="Fault_SyncParityOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncParityOnWalk</a></line>
<line>            assert level IN {1,2};</line>
<line>            result = if level == 1 then '11100' else '11110';</line>
<line>        when <a link="Fault_AsyncParity" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncParity</a></line>
<line>            result = '11000';</line>
<line>        when <a link="Fault_AsyncExternal" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncExternal</a></line>
<line>            result = '10110';</line>
<line>        when <a link="Fault_Debug" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Debug</a></line>
<line>            result = '00010';</line>
<line>        when <a link="Fault_TLBConflict" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_TLBConflict</a></line>
<line>            result = '10000';</line>
<line>        when <a link="Fault_Lockdown" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Lockdown</a></line>
<line>            result = '10100';   // IMPLEMENTATION DEFINED</line>
<line>        when <a link="Fault_Exclusive" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Exclusive</a></line>
<line>            result = '10101';   // IMPLEMENTATION DEFINED</line>
<line>        when <a link="Fault_ICacheMaint" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_ICacheMaint</a></line>
<line>            result = '00100';</line>
<line>        otherwise</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/common/A32ExpandImm" mylink="aarch32.functions.common.A32ExpandImm" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// A32ExpandImm()</line>
<line>// ==============</line>
<line></line>
<line link="impl-aarch32.A32ExpandImm.1" hover="function: bits(32) A32ExpandImm(bits(12) imm12)" conts="A32ExpandImm">bits(32) <anchor link="impl-aarch32.A32ExpandImm.1" hover="function: bits(32) A32ExpandImm(bits(12) imm12)">A32ExpandImm</anchor>(bits(12) imm12)</line>
<line></line>
<line>    // PSTATE.C argument to following function call does not affect the imm32 result.</line>
<line>    (imm32, -) = <a link="impl-aarch32.A32ExpandImm_C.2" file="shared_pseudocode.xml" hover="function: (bits(32), bit) A32ExpandImm_C(bits(12) imm12, bit carry_in)">A32ExpandImm_C</a>(imm12, PSTATE.C);</line>
<line></line>
<line>    return imm32;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/common/A32ExpandImm_C" mylink="aarch32.functions.common.A32ExpandImm_C" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// A32ExpandImm_C()</line>
<line>// ================</line>
<line></line>
<line link="impl-aarch32.A32ExpandImm_C.2" hover="function: (bits(32), bit) A32ExpandImm_C(bits(12) imm12, bit carry_in)" conts="A32ExpandImm_C">(bits(32), bit) <anchor link="impl-aarch32.A32ExpandImm_C.2" hover="function: (bits(32), bit) A32ExpandImm_C(bits(12) imm12, bit carry_in)">A32ExpandImm_C</anchor>(bits(12) imm12, bit carry_in)</line>
<line></line>
<line>    unrotated_value = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12&lt;7:0&gt;, 32);</line>
<line>    (imm32, carry_out) = <a link="impl-aarch32.Shift_C.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift_C</a>(unrotated_value, <a link="SRType_ROR" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_ROR</a>, 2*<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm12&lt;11:8&gt;), carry_in);</line>
<line></line>
<line>    return (imm32, carry_out);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/common/DecodeImmShift" mylink="aarch32.functions.common.DecodeImmShift" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DecodeImmShift()</line>
<line>// ================</line>
<line></line>
<line link="impl-aarch32.DecodeImmShift.2" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)" conts="DecodeImmShift">(SRType, integer) <anchor link="impl-aarch32.DecodeImmShift.2" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</anchor>(bits(2) srtype, bits(5) imm5)</line>
<line></line>
<line>    <a link="SRType" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType</a> shift_t;</line>
<line>    integer shift_n;</line>
<line>    case srtype of</line>
<line>        when '00'</line>
<line>            shift_t = <a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>;  shift_n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm5);</line>
<line>        when '01'</line>
<line>            shift_t = <a link="SRType_LSR" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSR</a>;  shift_n = if imm5 == '00000' then 32 else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm5);</line>
<line>        when '10'</line>
<line>            shift_t = <a link="SRType_ASR" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_ASR</a>;  shift_n = if imm5 == '00000' then 32 else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm5);</line>
<line>        when '11'</line>
<line>            if imm5 == '00000' then</line>
<line>                shift_t = <a link="SRType_RRX" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_RRX</a>;  shift_n = 1;</line>
<line>            else</line>
<line>                shift_t = <a link="SRType_ROR" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_ROR</a>;  shift_n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm5);</line>
<line></line>
<line>    return (shift_t, shift_n);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/common/DecodeRegShift" mylink="aarch32.functions.common.DecodeRegShift" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DecodeRegShift()</line>
<line>// ================</line>
<line></line>
<line link="impl-aarch32.DecodeRegShift.1" hover="function: SRType DecodeRegShift(bits(2) srtype)" conts="DecodeRegShift">SRType <anchor link="impl-aarch32.DecodeRegShift.1" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</anchor>(bits(2) srtype)</line>
<line>    <a link="SRType" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType</a> shift_t;</line>
<line>    case srtype of</line>
<line>        when '00'  shift_t = <a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>;</line>
<line>        when '01'  shift_t = <a link="SRType_LSR" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSR</a>;</line>
<line>        when '10'  shift_t = <a link="SRType_ASR" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_ASR</a>;</line>
<line>        when '11'  shift_t = <a link="SRType_ROR" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_ROR</a>;</line>
<line>    return shift_t;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/common/RRX" mylink="aarch32.functions.common.RRX" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// RRX()</line>
<line>// =====</line>
<line></line>
<line link="impl-aarch32.RRX.2" hover="function: bits(N) RRX(bits(N) x, bit carry_in)" conts="RRX">bits(N) <anchor link="impl-aarch32.RRX.2" hover="function: bits(N) RRX(bits(N) x, bit carry_in)">RRX</anchor>(bits(N) x, bit carry_in)</line>
<line>    (result, -) = <a link="impl-aarch32.RRX_C.2" file="shared_pseudocode.xml" hover="function: (bits(N), bit) RRX_C(bits(N) x, bit carry_in)">RRX_C</a>(x, carry_in);</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/common/RRX_C" mylink="aarch32.functions.common.RRX_C" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// RRX_C()</line>
<line>// =======</line>
<line></line>
<line link="impl-aarch32.RRX_C.2" hover="function: (bits(N), bit) RRX_C(bits(N) x, bit carry_in)" conts="RRX_C">(bits(N), bit) <anchor link="impl-aarch32.RRX_C.2" hover="function: (bits(N), bit) RRX_C(bits(N) x, bit carry_in)">RRX_C</anchor>(bits(N) x, bit carry_in)</line>
<line>    result = carry_in : x&lt;N-1:1&gt;;</line>
<line>    carry_out = x&lt;0&gt;;</line>
<line>    return (result, carry_out);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/common/SRType" mylink="aarch32.functions.common.SRType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SRType</line>
<line>// ======</line>
<line></line>
<line link="SRType" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}" conts="SRType">enumeration <anchor link="SRType" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType</anchor> {<anchor link="SRType_LSL" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</anchor>, <anchor link="SRType_LSR" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSR</anchor>, <anchor link="SRType_ASR" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_ASR</anchor>, <anchor link="SRType_ROR" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_ROR</anchor>, <anchor link="SRType_RRX" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_RRX</anchor>};</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/common/Shift" mylink="aarch32.functions.common.Shift" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Shift()</line>
<line>// =======</line>
<line></line>
<line link="impl-aarch32.Shift.4" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)" conts="Shift">bits(N) <anchor link="impl-aarch32.Shift.4" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</anchor>(bits(N) value, <a link="SRType" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType</a> srtype, integer amount, bit carry_in)</line>
<line>    (result, -) = <a link="impl-aarch32.Shift_C.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift_C</a>(value, srtype, amount, carry_in);</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/common/Shift_C" mylink="aarch32.functions.common.Shift_C" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Shift_C()</line>
<line>// =========</line>
<line></line>
<line link="impl-aarch32.Shift_C.4" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)" conts="Shift_C">(bits(N), bit) <anchor link="impl-aarch32.Shift_C.4" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift_C</anchor>(bits(N) value, <a link="SRType" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType</a> srtype, integer amount, bit carry_in)</line>
<line>    assert !(srtype == <a link="SRType_RRX" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_RRX</a> &amp;&amp; amount != 1);</line>
<line></line>
<line>    bits(N) result;</line>
<line>    bit carry_out;</line>
<line>    if amount == 0 then</line>
<line>        (result, carry_out) = (value, carry_in);</line>
<line>    else</line>
<line>        case srtype of</line>
<line>            when <a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a></line>
<line>                (result, carry_out) = <a link="impl-shared.LSL_C.2" file="shared_pseudocode.xml" hover="function: (bits(N), bit) LSL_C(bits(N) x, integer shift)">LSL_C</a>(value, amount);</line>
<line>            when <a link="SRType_LSR" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSR</a></line>
<line>                (result, carry_out) = <a link="impl-shared.LSR_C.2" file="shared_pseudocode.xml" hover="function: (bits(N), bit) LSR_C(bits(N) x, integer shift)">LSR_C</a>(value, amount);</line>
<line>            when <a link="SRType_ASR" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_ASR</a></line>
<line>                (result, carry_out) = <a link="impl-shared.ASR_C.2" file="shared_pseudocode.xml" hover="function: (bits(N), bit) ASR_C(bits(N) x, integer shift)">ASR_C</a>(value, amount);</line>
<line>            when <a link="SRType_ROR" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_ROR</a></line>
<line>                (result, carry_out) = <a link="impl-shared.ROR_C.2" file="shared_pseudocode.xml" hover="function: (bits(N), bit) ROR_C(bits(N) x, integer shift)">ROR_C</a>(value, amount);</line>
<line>            when <a link="SRType_RRX" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_RRX</a></line>
<line>                (result, carry_out) = <a link="impl-aarch32.RRX_C.2" file="shared_pseudocode.xml" hover="function: (bits(N), bit) RRX_C(bits(N) x, bit carry_in)">RRX_C</a>(value, carry_in);</line>
<line></line>
<line>    return (result, carry_out);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/common/T32ExpandImm" mylink="aarch32.functions.common.T32ExpandImm" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// T32ExpandImm()</line>
<line>// ==============</line>
<line></line>
<line link="impl-aarch32.T32ExpandImm.1" hover="function: bits(32) T32ExpandImm(bits(12) imm12)" conts="T32ExpandImm">bits(32) <anchor link="impl-aarch32.T32ExpandImm.1" hover="function: bits(32) T32ExpandImm(bits(12) imm12)">T32ExpandImm</anchor>(bits(12) imm12)</line>
<line></line>
<line>    // PSTATE.C argument to following function call does not affect the imm32 result.</line>
<line>    (imm32, -) = <a link="impl-aarch32.T32ExpandImm_C.2" file="shared_pseudocode.xml" hover="function: (bits(32), bit) T32ExpandImm_C(bits(12) imm12, bit carry_in)">T32ExpandImm_C</a>(imm12, PSTATE.C);</line>
<line></line>
<line>    return imm32;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/common/T32ExpandImm_C" mylink="aarch32.functions.common.T32ExpandImm_C" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// T32ExpandImm_C()</line>
<line>// ================</line>
<line></line>
<line link="impl-aarch32.T32ExpandImm_C.2" hover="function: (bits(32), bit) T32ExpandImm_C(bits(12) imm12, bit carry_in)" conts="T32ExpandImm_C">(bits(32), bit) <anchor link="impl-aarch32.T32ExpandImm_C.2" hover="function: (bits(32), bit) T32ExpandImm_C(bits(12) imm12, bit carry_in)">T32ExpandImm_C</anchor>(bits(12) imm12, bit carry_in)</line>
<line>    bits(32) imm32;</line>
<line>    bit carry_out;</line>
<line>    if imm12&lt;11:10&gt; == '00' then</line>
<line>        case imm12&lt;9:8&gt; of</line>
<line>            when '00'</line>
<line>                imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12&lt;7:0&gt;, 32);</line>
<line>            when '01'</line>
<line>                imm32 = '00000000' : imm12&lt;7:0&gt; : '00000000' : imm12&lt;7:0&gt;;</line>
<line>            when '10'</line>
<line>                imm32 = imm12&lt;7:0&gt; : '00000000' : imm12&lt;7:0&gt; : '00000000';</line>
<line>            when '11'</line>
<line>                imm32 = imm12&lt;7:0&gt; : imm12&lt;7:0&gt; : imm12&lt;7:0&gt; : imm12&lt;7:0&gt;;</line>
<line>        carry_out = carry_in;</line>
<line>    else</line>
<line>        unrotated_value = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('1':imm12&lt;6:0&gt;, 32);</line>
<line>        (imm32, carry_out) = <a link="impl-shared.ROR_C.2" file="shared_pseudocode.xml" hover="function: (bits(N), bit) ROR_C(bits(N) x, integer shift)">ROR_C</a>(unrotated_value, <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm12&lt;11:7&gt;));</line>
<line></line>
<line>    return (imm32, carry_out);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/common/VBitOps" mylink="aarch32.functions.common.VBitOps" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// VBitOps</line>
<line>// =======</line>
<line></line>
<line link="VBitOps" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}" conts="VBitOps">enumeration <anchor link="VBitOps" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps</anchor> {<anchor link="VBitOps_VBIF" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBIF</anchor>, <anchor link="VBitOps_VBIT" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBIT</anchor>, <anchor link="VBitOps_VBSL" hover="enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL}">VBitOps_VBSL</anchor>};</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/common/VCGEType" mylink="aarch32.functions.common.VCGEType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// VCGEType</line>
<line>// ========</line>
<line></line>
<line link="VCGEType" hover="enumeration VCGEType {VCGEType_signed, VCGEType_unsigned, VCGEType_fp}" conts="VCGEType">enumeration <anchor link="VCGEType" hover="enumeration VCGEType {VCGEType_signed, VCGEType_unsigned, VCGEType_fp}">VCGEType</anchor> {<anchor link="VCGEType_signed" hover="enumeration VCGEType {VCGEType_signed, VCGEType_unsigned, VCGEType_fp}">VCGEType_signed</anchor>, <anchor link="VCGEType_unsigned" hover="enumeration VCGEType {VCGEType_signed, VCGEType_unsigned, VCGEType_fp}">VCGEType_unsigned</anchor>, <anchor link="VCGEType_fp" hover="enumeration VCGEType {VCGEType_signed, VCGEType_unsigned, VCGEType_fp}">VCGEType_fp</anchor>};</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/common/VCGTtype" mylink="aarch32.functions.common.VCGTtype" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// VCGTtype</line>
<line>// ========</line>
<line></line>
<line link="VCGTtype" hover="enumeration VCGTtype {VCGTtype_signed, VCGTtype_unsigned, VCGTtype_fp}" conts="VCGTtype">enumeration <anchor link="VCGTtype" hover="enumeration VCGTtype {VCGTtype_signed, VCGTtype_unsigned, VCGTtype_fp}">VCGTtype</anchor> {<anchor link="VCGTtype_signed" hover="enumeration VCGTtype {VCGTtype_signed, VCGTtype_unsigned, VCGTtype_fp}">VCGTtype_signed</anchor>, <anchor link="VCGTtype_unsigned" hover="enumeration VCGTtype {VCGTtype_signed, VCGTtype_unsigned, VCGTtype_fp}">VCGTtype_unsigned</anchor>, <anchor link="VCGTtype_fp" hover="enumeration VCGTtype {VCGTtype_signed, VCGTtype_unsigned, VCGTtype_fp}">VCGTtype_fp</anchor>};</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/common/VFPNegMul" mylink="aarch32.functions.common.VFPNegMul" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// VFPNegMul</line>
<line>// =========</line>
<line></line>
<line link="VFPNegMul" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}" conts="VFPNegMul">enumeration <anchor link="VFPNegMul" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul</anchor> {<anchor link="VFPNegMul_VNMLA" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLA</anchor>, <anchor link="VFPNegMul_VNMLS" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMLS</anchor>, <anchor link="VFPNegMul_VNMUL" hover="enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL}">VFPNegMul_VNMUL</anchor>};</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/coproc/AArch32.CheckCP15InstrCoarseTraps" mylink="aarch32.functions.coproc.AArch32.CheckCP15InstrCoarseTraps" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.CheckCP15InstrCoarseTraps()</line>
<line>// ===================================</line>
<line>// Check for coarse-grained  traps to System registers in the</line>
<line>// coproc=0b1111 encoding space by HSTR and HCR.</line>
<line></line>
<line link="AArch32.CheckCP15InstrCoarseTraps.3" hover="function: AArch32.CheckCP15InstrCoarseTraps(integer CRn, integer nreg, integer CRm)" conts="AArch32.CheckCP15InstrCoarseTraps"><anchor link="AArch32.CheckCP15InstrCoarseTraps.3" hover="function: AArch32.CheckCP15InstrCoarseTraps(integer CRn, integer nreg, integer CRm)">AArch32.CheckCP15InstrCoarseTraps</anchor>(integer CRn, integer nreg, integer CRm)</line>
<line>    if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; (!<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) ||</line>
<line>            (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>))) then</line>
<line>        <a link="AArch64.CheckCP15InstrCoarseTraps.3" file="shared_pseudocode.xml" hover="function: AArch64.CheckCP15InstrCoarseTraps(integer CRn, integer nreg, integer CRm)">AArch64.CheckCP15InstrCoarseTraps</a>(CRn, nreg, CRm);</line>
<line></line>
<line>    trapped_encoding = ((CRn == 9  &amp;&amp; CRm IN {0,1,2,    5,6,7,8   }) ||</line>
<line>                        (CRn == 10 &amp;&amp; CRm IN {0,1,    4,      8   }) ||</line>
<line>                        (CRn == 11 &amp;&amp; CRm IN {0,1,2,3,4,5,6,7,8,15}));</line>
<line></line>
<line>    // Check for coarse-grained Hyp traps</line>
<line>    if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        major = if nreg == 1 then CRn else CRm;</line>
<line>        // Check for MCR, MRC, MCRR, and MRRC disabled by HSTR&lt;CRn/CRm&gt;</line>
<line>        // and MRC and MCR disabled by HCR.TIDCP.</line>
<line>        if ((!(major IN {4,14}) &amp;&amp; HSTR&lt;major&gt; == '1') ||</line>
<line>                (HCR.TIDCP == '1' &amp;&amp; nreg == 1 &amp;&amp; trapped_encoding)) then</line>
<line>            if (PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp;</line>
<line>                    boolean IMPLEMENTATION_DEFINED "UNDEF unallocated CP15 access at <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>") then</line>
<line>                UNDEFINED;</line>
<line>            if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>                <a link="AArch32.SystemAccessTrap.2" file="shared_pseudocode.xml" hover="function: AArch32.SystemAccessTrap(bits(5) mode, integer ec)">AArch32.SystemAccessTrap</a>(<a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a>, 0x3);</line>
<line>            else</line>
<line>                <a link="AArch64.AArch32SystemAccessTrap.2" file="shared_pseudocode.xml" hover="function: AArch64.AArch32SystemAccessTrap(bits(2) target_el, integer ec)">AArch64.AArch32SystemAccessTrap</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, 0x3);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/exclusive/AArch32.ExclusiveMonitorsPass" mylink="aarch32.functions.exclusive.AArch32.ExclusiveMonitorsPass" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.ExclusiveMonitorsPass()</line>
<line>// ===============================</line>
<line>// Return TRUE if the Exclusives monitors for the current PE include all of the addresses</line>
<line>// associated with the virtual address region of size bytes starting at address.</line>
<line>// The immediately following memory write must be to the same addresses.</line>
<line></line>
<line link="AArch32.ExclusiveMonitorsPass.2" hover="function: boolean AArch32.ExclusiveMonitorsPass(bits(32) address, integer size)" conts="AArch32.ExclusiveMonitorsPass">boolean <anchor link="AArch32.ExclusiveMonitorsPass.2" hover="function: boolean AArch32.ExclusiveMonitorsPass(bits(32) address, integer size)">AArch32.ExclusiveMonitorsPass</anchor>(bits(32) address, integer size)</line>
<line></line>
<line>    // It is IMPLEMENTATION DEFINED whether the detection of memory aborts happens</line>
<line>    // before or after the check on the local Exclusives monitor. As a result a failure</line>
<line>    // of the local monitor can occur on some implementations even if the memory</line>
<line>    // access would give an memory abort.</line>
<line>    boolean acqrel = FALSE;</line>
<line>    boolean tagchecked = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescExLDST.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescExLDST(MemOp memop, boolean acqrel, boolean tagchecked)">CreateAccDescExLDST</a>(<a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>, acqrel, tagchecked);</line>
<line>    boolean aligned = <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, size);</line>
<line></line>
<line>    if !aligned then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    if !<a link="AArch32.IsExclusiveVA.3" file="shared_pseudocode.xml" hover="function: boolean AArch32.IsExclusiveVA(bits(32) address, integer processorid, integer size)">AArch32.IsExclusiveVA</a>(address, <a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>(), size) then</line>
<line>        return FALSE;</line>
<line></line>
<line>    memaddrdesc = <a link="AArch32.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch32.TranslateAddress(bits(32) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch32.TranslateAddress</a>(address, accdesc, aligned, size);</line>
<line></line>
<line>    // Check for aborts or debug exceptions</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, memaddrdesc.fault);</line>
<line></line>
<line>    passed = <a link="impl-shared.IsExclusiveLocal.3" file="shared_pseudocode.xml" hover="function: boolean IsExclusiveLocal(FullAddress paddress, integer processorid, integer size)">IsExclusiveLocal</a>(memaddrdesc.paddress, <a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>(), size);</line>
<line>    <a link="impl-shared.ClearExclusiveLocal.1" file="shared_pseudocode.xml" hover="function: ClearExclusiveLocal(integer processorid)">ClearExclusiveLocal</a>(<a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>());</line>
<line></line>
<line>    if passed &amp;&amp; memaddrdesc.memattrs.shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then</line>
<line>        passed = <a link="impl-shared.IsExclusiveGlobal.3" file="shared_pseudocode.xml" hover="function: boolean IsExclusiveGlobal(FullAddress paddress, integer processorid, integer size)">IsExclusiveGlobal</a>(memaddrdesc.paddress, <a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>(), size);</line>
<line></line>
<line>    return passed;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/exclusive/AArch32.IsExclusiveVA" mylink="aarch32.functions.exclusive.AArch32.IsExclusiveVA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.IsExclusiveVA()</line>
<line>// =======================</line>
<line>// An optional IMPLEMENTATION DEFINED test for an exclusive access to a virtual</line>
<line>// address region of size bytes starting at address.</line>
<line>//</line>
<line>// It is permitted (but not required) for this function to return FALSE and</line>
<line>// cause a store exclusive to fail if the virtual address region is not</line>
<line>// totally included within the region recorded by MarkExclusiveVA().</line>
<line>//</line>
<line>// It is always safe to return TRUE which will check the physical address only.</line>
<line></line>
<line link="AArch32.IsExclusiveVA.3" hover="function: boolean AArch32.IsExclusiveVA(bits(32) address, integer processorid, integer size)" conts="AArch32.IsExclusiveVA">boolean <anchor link="AArch32.IsExclusiveVA.3" hover="function: boolean AArch32.IsExclusiveVA(bits(32) address, integer processorid, integer size)">AArch32.IsExclusiveVA</anchor>(bits(32) address, integer processorid, integer size);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/exclusive/AArch32.MarkExclusiveVA" mylink="aarch32.functions.exclusive.AArch32.MarkExclusiveVA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.MarkExclusiveVA()</line>
<line>// =========================</line>
<line>// Optionally record an exclusive access to the virtual address region of size bytes</line>
<line>// starting at address for processorid.</line>
<line></line>
<line link="AArch32.MarkExclusiveVA.3" hover="function: AArch32.MarkExclusiveVA(bits(32) address, integer processorid, integer size)" conts="AArch32.MarkExclusiveVA"><anchor link="AArch32.MarkExclusiveVA.3" hover="function: AArch32.MarkExclusiveVA(bits(32) address, integer processorid, integer size)">AArch32.MarkExclusiveVA</anchor>(bits(32) address, integer processorid, integer size);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/exclusive/AArch32.SetExclusiveMonitors" mylink="aarch32.functions.exclusive.AArch32.SetExclusiveMonitors" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.SetExclusiveMonitors()</line>
<line>// ==============================</line>
<line>// Sets the Exclusives monitors for the current PE to record the addresses associated</line>
<line>// with the virtual address region of size bytes starting at address.</line>
<line></line>
<line link="AArch32.SetExclusiveMonitors.2" hover="function: AArch32.SetExclusiveMonitors(bits(32) address, integer size)" conts="AArch32.SetExclusiveMonitors"><anchor link="AArch32.SetExclusiveMonitors.2" hover="function: AArch32.SetExclusiveMonitors(bits(32) address, integer size)">AArch32.SetExclusiveMonitors</anchor>(bits(32) address, integer size)</line>
<line>    boolean acqrel = FALSE;</line>
<line>    boolean tagchecked = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescExLDST.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescExLDST(MemOp memop, boolean acqrel, boolean tagchecked)">CreateAccDescExLDST</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, acqrel, tagchecked);</line>
<line>    boolean aligned = <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, size);</line>
<line></line>
<line>    if !aligned then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    memaddrdesc = <a link="AArch32.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch32.TranslateAddress(bits(32) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch32.TranslateAddress</a>(address, accdesc, aligned, size);</line>
<line></line>
<line>    // Check for aborts or debug exceptions</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>        return;</line>
<line></line>
<line>    if memaddrdesc.memattrs.shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then</line>
<line>        <a link="impl-shared.MarkExclusiveGlobal.3" file="shared_pseudocode.xml" hover="function: MarkExclusiveGlobal(FullAddress paddress, integer processorid, integer size)">MarkExclusiveGlobal</a>(memaddrdesc.paddress, <a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>(), size);</line>
<line></line>
<line>    <a link="impl-shared.MarkExclusiveLocal.3" file="shared_pseudocode.xml" hover="function: MarkExclusiveLocal(FullAddress paddress, integer processorid, integer size)">MarkExclusiveLocal</a>(memaddrdesc.paddress, <a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>(), size);</line>
<line></line>
<line>    <a link="AArch32.MarkExclusiveVA.3" file="shared_pseudocode.xml" hover="function: AArch32.MarkExclusiveVA(bits(32) address, integer processorid, integer size)">AArch32.MarkExclusiveVA</a>(address, <a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>(), size);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/float/CheckAdvSIMDEnabled" mylink="aarch32.functions.float.CheckAdvSIMDEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckAdvSIMDEnabled()</line>
<line>// =====================</line>
<line></line>
<line link="impl-aarch32.CheckAdvSIMDEnabled.0" hover="function: CheckAdvSIMDEnabled()" conts="CheckAdvSIMDEnabled"><anchor link="impl-aarch32.CheckAdvSIMDEnabled.0" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</anchor>()</line>
<line></line>
<line>    fpexc_check = TRUE;</line>
<line>    advsimd = TRUE;</line>
<line></line>
<line>    <a link="AArch32.CheckAdvSIMDOrFPEnabled.2" file="shared_pseudocode.xml" hover="function: AArch32.CheckAdvSIMDOrFPEnabled(boolean fpexc_check, boolean advsimd)">AArch32.CheckAdvSIMDOrFPEnabled</a>(fpexc_check, advsimd);</line>
<line>    // Return from CheckAdvSIMDOrFPEnabled() occurs only if Advanced SIMD access is permitted</line>
<line></line>
<line>    // Make temporary copy of D registers</line>
<line>    // _Dclone[] is used as input data for instruction pseudocode</line>
<line>    for i = 0 to 31</line>
<line>        _Dclone[i] = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[i];</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/float/CheckAdvSIMDOrVFPEnabled" mylink="aarch32.functions.float.CheckAdvSIMDOrVFPEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckAdvSIMDOrVFPEnabled()</line>
<line>// ==========================</line>
<line></line>
<line link="impl-aarch32.CheckAdvSIMDOrVFPEnabled.2" hover="function: CheckAdvSIMDOrVFPEnabled(boolean include_fpexc_check, boolean advsimd)" conts="CheckAdvSIMDOrVFPEnabled"><anchor link="impl-aarch32.CheckAdvSIMDOrVFPEnabled.2" hover="function: CheckAdvSIMDOrVFPEnabled(boolean include_fpexc_check, boolean advsimd)">CheckAdvSIMDOrVFPEnabled</anchor>(boolean include_fpexc_check, boolean advsimd)</line>
<line>    <a link="AArch32.CheckAdvSIMDOrFPEnabled.2" file="shared_pseudocode.xml" hover="function: AArch32.CheckAdvSIMDOrFPEnabled(boolean fpexc_check, boolean advsimd)">AArch32.CheckAdvSIMDOrFPEnabled</a>(include_fpexc_check, advsimd);</line>
<line>    // Return from CheckAdvSIMDOrFPEnabled() occurs only if VFP access is permitted</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/float/CheckCryptoEnabled32" mylink="aarch32.functions.float.CheckCryptoEnabled32" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckCryptoEnabled32()</line>
<line>// ======================</line>
<line></line>
<line link="impl-aarch32.CheckCryptoEnabled32.0" hover="function: CheckCryptoEnabled32()" conts="CheckCryptoEnabled32"><anchor link="impl-aarch32.CheckCryptoEnabled32.0" hover="function: CheckCryptoEnabled32()">CheckCryptoEnabled32</anchor>()</line>
<line>    <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();</line>
<line>    // Return from CheckAdvSIMDEnabled() occurs only if access is permitted</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/float/CheckVFPEnabled" mylink="aarch32.functions.float.CheckVFPEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckVFPEnabled()</line>
<line>// =================</line>
<line></line>
<line link="impl-aarch32.CheckVFPEnabled.1" hover="function: CheckVFPEnabled(boolean include_fpexc_check)" conts="CheckVFPEnabled"><anchor link="impl-aarch32.CheckVFPEnabled.1" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</anchor>(boolean include_fpexc_check)</line>
<line>    advsimd = FALSE;</line>
<line>    <a link="AArch32.CheckAdvSIMDOrFPEnabled.2" file="shared_pseudocode.xml" hover="function: AArch32.CheckAdvSIMDOrFPEnabled(boolean fpexc_check, boolean advsimd)">AArch32.CheckAdvSIMDOrFPEnabled</a>(include_fpexc_check, advsimd);</line>
<line>    // Return from CheckAdvSIMDOrFPEnabled() occurs only if VFP access is permitted</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/float/FPHalvedSub" mylink="aarch32.functions.float.FPHalvedSub" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPHalvedSub()</line>
<line>// =============</line>
<line></line>
<line link="impl-aarch32.FPHalvedSub.3" hover="function: bits(N) FPHalvedSub(bits(N) op1, bits(N) op2, FPCRType fpcr)" conts="FPHalvedSub">bits(N) <anchor link="impl-aarch32.FPHalvedSub.3" hover="function: bits(N) FPHalvedSub(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPHalvedSub</anchor>(bits(N) op1, bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    assert N IN {16,32,64};</line>
<line>    rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(fpcr);</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op1, fpcr);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op2, fpcr);</line>
<line>    (done,result) = <a link="impl-shared.FPProcessNaNs.5" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs(FPType type1, FPType type2, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPProcessNaNs</a>(type1, type2, op1, op2, fpcr);</line>
<line>    if !done then</line>
<line>        inf1 = (type1 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);  inf2 = (type2 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        zero1 = (type1 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);     zero2 = (type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line>        if inf1 &amp;&amp; inf2 &amp;&amp; sign1 == sign2 then</line>
<line>            result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, N);</line>
<line>            <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>        elsif (inf1 &amp;&amp; sign1 == '0') || (inf2 &amp;&amp; sign2 == '1') then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('0', N);</line>
<line>        elsif (inf1 &amp;&amp; sign1 == '1') || (inf2 &amp;&amp; sign2 == '0') then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('1', N);</line>
<line>        elsif zero1 &amp;&amp; zero2 &amp;&amp; sign1 != sign2 then</line>
<line>            result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign1, N);</line>
<line>        else</line>
<line>            result_value = (value1 - value2) / 2.0;</line>
<line>            if result_value == 0.0 then  // Sign of exact zero result depends on rounding mode</line>
<line>                result_sign = if rounding == <a link="FPRounding_NEGINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_NEGINF</a> then '1' else '0';</line>
<line>                result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(result_sign, N);</line>
<line>            else</line>
<line>                result = <a link="impl-shared.FPRound.3" file="shared_pseudocode.xml" hover="function: bits(N) FPRound(real op, FPCRType fpcr, integer N)">FPRound</a>(result_value, fpcr, N);</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/float/FPRSqrtStep" mylink="aarch32.functions.float.FPRSqrtStep" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPRSqrtStep()</line>
<line>// =============</line>
<line></line>
<line link="impl-aarch32.FPRSqrtStep.2" hover="function: bits(N) FPRSqrtStep(bits(N) op1, bits(N) op2)" conts="FPRSqrtStep">bits(N) <anchor link="impl-aarch32.FPRSqrtStep.2" hover="function: bits(N) FPRSqrtStep(bits(N) op1, bits(N) op2)">FPRSqrtStep</anchor>(bits(N) op1, bits(N) op2)</line>
<line>    assert N IN {16,32};</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>();</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op1, fpcr);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op2, fpcr);</line>
<line>    (done,result) = <a link="impl-shared.FPProcessNaNs.5" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs(FPType type1, FPType type2, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPProcessNaNs</a>(type1, type2, op1, op2, fpcr);</line>
<line>    if !done then</line>
<line>        inf1 = (type1 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);  inf2 = (type2 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        zero1 = (type1 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);     zero2 = (type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line>        bits(N) product;</line>
<line>        if (inf1 &amp;&amp; zero2) || (zero1 &amp;&amp; inf2) then</line>
<line>            product = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>('0', N);</line>
<line>        else</line>
<line>            product = <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(op1, op2, fpcr);</line>
<line>        bits(N) three = <a link="impl-shared.FPThree.2" file="shared_pseudocode.xml" hover="function: bits(N) FPThree(bit sign, integer N)">FPThree</a>('0', N);</line>
<line>        result = <a link="impl-aarch32.FPHalvedSub.3" file="shared_pseudocode.xml" hover="function: bits(N) FPHalvedSub(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPHalvedSub</a>(three, product, fpcr);</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/float/FPRecipStep" mylink="aarch32.functions.float.FPRecipStep" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPRecipStep()</line>
<line>// =============</line>
<line></line>
<line link="impl-aarch32.FPRecipStep.2" hover="function: bits(N) FPRecipStep(bits(N) op1, bits(N) op2)" conts="FPRecipStep">bits(N) <anchor link="impl-aarch32.FPRecipStep.2" hover="function: bits(N) FPRecipStep(bits(N) op1, bits(N) op2)">FPRecipStep</anchor>(bits(N) op1, bits(N) op2)</line>
<line>    assert N IN {16,32};</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>();</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op1, fpcr);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op2, fpcr);</line>
<line>    (done,result) = <a link="impl-shared.FPProcessNaNs.5" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs(FPType type1, FPType type2, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPProcessNaNs</a>(type1, type2, op1, op2, fpcr);</line>
<line>    if !done then</line>
<line>        inf1 = (type1 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);  inf2 = (type2 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        zero1 = (type1 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);     zero2 = (type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line>        bits(N) product;</line>
<line>        if (inf1 &amp;&amp; zero2) || (zero1 &amp;&amp; inf2) then</line>
<line>            product = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>('0', N);</line>
<line>        else</line>
<line>            product = <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(op1, op2, fpcr);</line>
<line>        bits(N) two = <a link="impl-shared.FPTwo.2" file="shared_pseudocode.xml" hover="function: bits(N) FPTwo(bit sign, integer N)">FPTwo</a>('0', N);</line>
<line>        result = <a link="impl-shared.FPSub.3" file="shared_pseudocode.xml" hover="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPSub</a>(two, product, fpcr);</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/float/StandardFPSCRValue" mylink="aarch32.functions.float.StandardFPSCRValue" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// StandardFPSCRValue()</line>
<line>// ====================</line>
<line></line>
<line link="impl-aarch32.StandardFPSCRValue.0" hover="function: FPCRType StandardFPSCRValue()" conts="StandardFPSCRValue">FPCRType <anchor link="impl-aarch32.StandardFPSCRValue.0" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</anchor>()</line>
<line>    bits(32) value = '00000' : FPSCR.AHP : '110000' : FPSCR.FZ16 : '0000000000000000000';</line>
<line>    return <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(value, 64);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/memory/AArch32.MemSingle" mylink="aarch32.functions.memory.AArch32.MemSingle" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.MemSingle[] - non-assignment (read) form</line>
<line>// ================================================</line>
<line>// Perform an atomic, little-endian read of 'size' bytes.</line>
<line></line>
<line link="AArch32.MemSingle.read.4" hover="accessor: bits(size*8) AArch32.MemSingle[bits(32) address, integer size, AccessDescriptor accdesc, boolean aligned]" conts="AArch32.MemSingle">bits(size*8) <anchor link="AArch32.MemSingle.read.4" hover="accessor: bits(size*8) AArch32.MemSingle[bits(32) address, integer size, AccessDescriptor accdesc, boolean aligned]">AArch32.MemSingle</anchor>[bits(32) address, integer size,</line>
<line>                               <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, boolean aligned]</line>
<line>    boolean ispair = FALSE;</line>
<line>    return <a link="AArch32.MemSingle.read.5" file="shared_pseudocode.xml" hover="accessor: bits(size*8) AArch32.MemSingle[bits(32) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair]">AArch32.MemSingle</a>[address, size, accdesc, aligned, ispair];</line>
<line></line>
<line>// AArch32.MemSingle[] - non-assignment (read) form</line>
<line>// ================================================</line>
<line>// Perform an atomic, little-endian read of 'size' bytes.</line>
<line></line>
<line link="AArch32.MemSingle.read.5" hover="accessor: bits(size*8) AArch32.MemSingle[bits(32) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair]" conts="AArch32.MemSingle">bits(size*8) <anchor link="AArch32.MemSingle.read.5" hover="accessor: bits(size*8) AArch32.MemSingle[bits(32) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair]">AArch32.MemSingle</anchor>[bits(32) address, integer size, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc_in,</line>
<line>                               boolean aligned, boolean ispair]</line>
<line>    assert size IN {1, 2, 4, 8, 16};</line>
<line>    bits(size*8) value;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = accdesc_in;</line>
<line>    assert <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, size);</line>
<line></line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc;</line>
<line>    memaddrdesc = <a link="AArch32.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch32.TranslateAddress(bits(32) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch32.TranslateAddress</a>(address, accdesc, aligned, size);</line>
<line></line>
<line>    // Check for aborts or debug exceptions</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, memaddrdesc.fault);</line>
<line></line>
<line>    // Memory array access</line>
<line>    if SPESampleInFlight then</line>
<line>        boolean is_load = TRUE;</line>
<line>        SPESampleLoadStore(is_load, accdesc, memaddrdesc);</line>
<line></line>
<line>    <a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> memstatus;</line>
<line>    (memstatus, value) = <a link="impl-shared.PhysMemRead.3" file="shared_pseudocode.xml" hover="function: (PhysMemRetStatus, bits(8*size)) PhysMemRead(AddressDescriptor desc, integer size, AccessDescriptor accdesc)">PhysMemRead</a>(memaddrdesc, size, accdesc);</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>        <a link="impl-shared.HandleExternalReadAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalReadAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalReadAbort</a>(memstatus, memaddrdesc, size, accdesc);</line>
<line>    return value;</line>
<line></line>
<line>// AArch32.MemSingle[] - assignment (write) form</line>
<line>// =============================================</line>
<line></line>
<line link="AArch32.MemSingle.write.4" hover="accessor: AArch32.MemSingle[bits(32) address, integer size, AccessDescriptor accdesc, boolean aligned] = bits(size*8) value" conts="AArch32.MemSingle"><anchor link="AArch32.MemSingle.write.4" hover="accessor: AArch32.MemSingle[bits(32) address, integer size, AccessDescriptor accdesc, boolean aligned] = bits(size*8) value">AArch32.MemSingle</anchor>[bits(32) address, integer size,</line>
<line>                  <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, boolean aligned] = bits(size*8) value</line>
<line>    boolean ispair = FALSE;</line>
<line>    <a link="AArch32.MemSingle.write.5" file="shared_pseudocode.xml" hover="accessor: AArch32.MemSingle[bits(32) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair] = bits(size*8) value">AArch32.MemSingle</a>[address, size, accdesc, aligned, ispair] = value;</line>
<line>    return;</line>
<line></line>
<line>// AArch32.MemSingle[] - assignment (write) form</line>
<line>// =============================================</line>
<line>// Perform an atomic, little-endian write of 'size' bytes.</line>
<line></line>
<line link="AArch32.MemSingle.write.5" hover="accessor: AArch32.MemSingle[bits(32) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair] = bits(size*8) value" conts="AArch32.MemSingle"><anchor link="AArch32.MemSingle.write.5" hover="accessor: AArch32.MemSingle[bits(32) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair] = bits(size*8) value">AArch32.MemSingle</anchor>[bits(32) address, integer size, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc_in,</line>
<line>                  boolean aligned, boolean ispair] = bits(size*8) value</line>
<line>    assert size IN {1, 2, 4, 8, 16};</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = accdesc_in;</line>
<line>    assert <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, size);</line>
<line></line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc;</line>
<line>    memaddrdesc = <a link="AArch32.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch32.TranslateAddress(bits(32) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch32.TranslateAddress</a>(address, accdesc, aligned, size);</line>
<line></line>
<line>    // Check for aborts or debug exceptions</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, memaddrdesc.fault);</line>
<line></line>
<line>    // Effect on exclusives</line>
<line>    if memaddrdesc.memattrs.shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then</line>
<line>        <a link="impl-shared.ClearExclusiveByAddress.3" file="shared_pseudocode.xml" hover="function: ClearExclusiveByAddress(FullAddress paddress, integer processorid, integer size)">ClearExclusiveByAddress</a>(memaddrdesc.paddress, <a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>(), size);</line>
<line></line>
<line>    if SPESampleInFlight then</line>
<line>        boolean is_load = FALSE;</line>
<line>        SPESampleLoadStore(is_load, accdesc, memaddrdesc);</line>
<line></line>
<line>    <a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> memstatus;</line>
<line>    memstatus = <a link="impl-shared.PhysMemWrite.4" file="shared_pseudocode.xml" hover="function: PhysMemRetStatus PhysMemWrite(AddressDescriptor desc, integer size, AccessDescriptor accdesc, bits(8*size) value)">PhysMemWrite</a>(memaddrdesc, size, accdesc, value);</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>        <a link="impl-shared.HandleExternalWriteAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalWriteAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalWriteAbort</a>(memstatus, memaddrdesc, size, accdesc);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/memory/AArch32.UnalignedAccessFaults" mylink="aarch32.functions.memory.AArch32.UnalignedAccessFaults" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.UnalignedAccessFaults()</line>
<line>// ===============================</line>
<line>// Determine whether the unaligned access generates an Alignment fault</line>
<line></line>
<line link="AArch32.UnalignedAccessFaults.1" hover="function: boolean AArch32.UnalignedAccessFaults(AccessDescriptor accdesc)" conts="AArch32.UnalignedAccessFaults">boolean <anchor link="AArch32.UnalignedAccessFaults.1" hover="function: boolean AArch32.UnalignedAccessFaults(AccessDescriptor accdesc)">AArch32.UnalignedAccessFaults</anchor>(<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    return (<a link="impl-shared.AlignmentEnforced.0" file="shared_pseudocode.xml" hover="function: boolean AlignmentEnforced()">AlignmentEnforced</a>() ||</line>
<line>            accdesc.a32lsmd     ||</line>
<line>            accdesc.exclusive   ||</line>
<line>            accdesc.acqsc       ||</line>
<line>            accdesc.relsc);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/memory/Hint_PreloadData" mylink="aarch32.functions.memory.Hint_PreloadData" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Hint_PreloadData()</line>
<line>// ==================</line>
<line></line>
<line link="impl-aarch32.Hint_PreloadData.1" hover="function: Hint_PreloadData(bits(32) address)" conts="Hint_PreloadData"><anchor link="impl-aarch32.Hint_PreloadData.1" hover="function: Hint_PreloadData(bits(32) address)">Hint_PreloadData</anchor>(bits(32) address);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/memory/Hint_PreloadDataForWrite" mylink="aarch32.functions.memory.Hint_PreloadDataForWrite" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Hint_PreloadDataForWrite()</line>
<line>// ==========================</line>
<line></line>
<line link="impl-aarch32.Hint_PreloadDataForWrite.1" hover="function: Hint_PreloadDataForWrite(bits(32) address)" conts="Hint_PreloadDataForWrite"><anchor link="impl-aarch32.Hint_PreloadDataForWrite.1" hover="function: Hint_PreloadDataForWrite(bits(32) address)">Hint_PreloadDataForWrite</anchor>(bits(32) address);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/memory/Hint_PreloadInstr" mylink="aarch32.functions.memory.Hint_PreloadInstr" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Hint_PreloadInstr()</line>
<line>// ===================</line>
<line></line>
<line link="impl-aarch32.Hint_PreloadInstr.1" hover="function: Hint_PreloadInstr(bits(32) address)" conts="Hint_PreloadInstr"><anchor link="impl-aarch32.Hint_PreloadInstr.1" hover="function: Hint_PreloadInstr(bits(32) address)">Hint_PreloadInstr</anchor>(bits(32) address);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/memory/MemA" mylink="aarch32.functions.memory.MemA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemA[] - non-assignment form</line>
<line>// ============================</line>
<line></line>
<line link="impl-aarch32.MemA.read.2" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]" conts="MemA">bits(8*size) <anchor link="impl-aarch32.MemA.read.2" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</anchor>[bits(32) address, integer size]</line>
<line>    boolean acqrel = FALSE;</line>
<line>    boolean tagchecked = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescExLDST.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescExLDST(MemOp memop, boolean acqrel, boolean tagchecked)">CreateAccDescExLDST</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, acqrel, tagchecked);</line>
<line>    return <a link="impl-aarch32.Mem_with_type.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem_with_type[bits(32) address, integer size, AccessDescriptor accdesc]">Mem_with_type</a>[address, size, accdesc];</line>
<line></line>
<line>// MemA[] - assignment form</line>
<line>// ========================</line>
<line></line>
<line link="impl-aarch32.MemA.write.2" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value" conts="MemA"><anchor link="impl-aarch32.MemA.write.2" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</anchor>[bits(32) address, integer size] = bits(8*size) value</line>
<line>    boolean acqrel = FALSE;</line>
<line>    boolean tagchecked = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescExLDST.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescExLDST(MemOp memop, boolean acqrel, boolean tagchecked)">CreateAccDescExLDST</a>(<a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>, acqrel, tagchecked);</line>
<line>    Mem_with_type[address, size, accdesc] = value;</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/memory/MemO" mylink="aarch32.functions.memory.MemO" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemO[] - non-assignment form</line>
<line>// ============================</line>
<line></line>
<line link="impl-aarch32.MemO.read.2" hover="accessor: bits(8*size) MemO[bits(32) address, integer size]" conts="MemO">bits(8*size) <anchor link="impl-aarch32.MemO.read.2" hover="accessor: bits(8*size) MemO[bits(32) address, integer size]">MemO</anchor>[bits(32) address, integer size]</line>
<line>    boolean tagchecked = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescAcqRel.2" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescAcqRel(MemOp memop, boolean tagchecked)">CreateAccDescAcqRel</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, tagchecked);</line>
<line>    return <a link="impl-aarch32.Mem_with_type.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem_with_type[bits(32) address, integer size, AccessDescriptor accdesc]">Mem_with_type</a>[address, size, accdesc];</line>
<line></line>
<line>// MemO[] - assignment form</line>
<line>// ========================</line>
<line></line>
<line link="impl-aarch32.MemO.write.2" hover="accessor: MemO[bits(32) address, integer size] = bits(8*size) value" conts="MemO"><anchor link="impl-aarch32.MemO.write.2" hover="accessor: MemO[bits(32) address, integer size] = bits(8*size) value">MemO</anchor>[bits(32) address, integer size] = bits(8*size) value</line>
<line>    boolean tagchecked = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescAcqRel.2" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescAcqRel(MemOp memop, boolean tagchecked)">CreateAccDescAcqRel</a>(<a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>, tagchecked);</line>
<line>    Mem_with_type[address, size, accdesc] = value;</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/memory/MemS" mylink="aarch32.functions.memory.MemS" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemS[] - non-assignment form</line>
<line>// ============================</line>
<line>// Memory accessor for streaming load multiple instructions</line>
<line></line>
<line link="impl-aarch32.MemS.read.2" hover="accessor: bits(8*size) MemS[bits(32) address, integer size]" conts="MemS">bits(8*size) <anchor link="impl-aarch32.MemS.read.2" hover="accessor: bits(8*size) MemS[bits(32) address, integer size]">MemS</anchor>[bits(32) address, integer size]</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescA32LSMD.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescA32LSMD(MemOp memop)">CreateAccDescA32LSMD</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>);</line>
<line>    return <a link="impl-aarch32.Mem_with_type.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem_with_type[bits(32) address, integer size, AccessDescriptor accdesc]">Mem_with_type</a>[address, size, accdesc];</line>
<line></line>
<line>// MemS[] - assignment form</line>
<line>// ========================</line>
<line>// Memory accessor for streaming store multiple instructions</line>
<line></line>
<line link="impl-aarch32.MemS.write.2" hover="accessor: MemS[bits(32) address, integer size] = bits(8*size) value" conts="MemS"><anchor link="impl-aarch32.MemS.write.2" hover="accessor: MemS[bits(32) address, integer size] = bits(8*size) value">MemS</anchor>[bits(32) address, integer size] = bits(8*size) value</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescA32LSMD.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescA32LSMD(MemOp memop)">CreateAccDescA32LSMD</a>(<a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>);</line>
<line>    Mem_with_type[address, size, accdesc] = value;</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/memory/MemU" mylink="aarch32.functions.memory.MemU" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemU[] - non-assignment form</line>
<line>// ============================</line>
<line></line>
<line link="impl-aarch32.MemU.read.2" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]" conts="MemU">bits(8*size) <anchor link="impl-aarch32.MemU.read.2" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</anchor>[bits(32) address, integer size]</line>
<line>    boolean nontemporal = FALSE;</line>
<line>    boolean privileged = PSTATE.EL != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;</line>
<line>    boolean tagchecked = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescGPR.4" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescGPR(MemOp memop, boolean nontemporal, boolean privileged, boolean tagchecked)">CreateAccDescGPR</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, nontemporal, privileged, tagchecked);</line>
<line>    return <a link="impl-aarch32.Mem_with_type.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem_with_type[bits(32) address, integer size, AccessDescriptor accdesc]">Mem_with_type</a>[address, size, accdesc];</line>
<line></line>
<line>// MemU[] - assignment form</line>
<line>// ========================</line>
<line></line>
<line link="impl-aarch32.MemU.write.2" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value" conts="MemU"><anchor link="impl-aarch32.MemU.write.2" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</anchor>[bits(32) address, integer size] = bits(8*size) value</line>
<line>    boolean nontemporal = FALSE;</line>
<line>    boolean privileged = PSTATE.EL != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;</line>
<line>    boolean tagchecked = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescGPR.4" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescGPR(MemOp memop, boolean nontemporal, boolean privileged, boolean tagchecked)">CreateAccDescGPR</a>(<a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>, nontemporal, privileged, tagchecked);</line>
<line>    Mem_with_type[address, size, accdesc] = value;</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/memory/MemU_unpriv" mylink="aarch32.functions.memory.MemU_unpriv" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemU_unpriv[] - non-assignment form</line>
<line>// ===================================</line>
<line></line>
<line link="impl-aarch32.MemU_unpriv.read.2" hover="accessor: bits(8*size) MemU_unpriv[bits(32) address, integer size]" conts="MemU_unpriv">bits(8*size) <anchor link="impl-aarch32.MemU_unpriv.read.2" hover="accessor: bits(8*size) MemU_unpriv[bits(32) address, integer size]">MemU_unpriv</anchor>[bits(32) address, integer size]</line>
<line>    boolean nontemporal = FALSE;</line>
<line>    boolean privileged = FALSE;</line>
<line>    boolean tagchecked = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescGPR.4" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescGPR(MemOp memop, boolean nontemporal, boolean privileged, boolean tagchecked)">CreateAccDescGPR</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, nontemporal, privileged, tagchecked);</line>
<line>    return <a link="impl-aarch32.Mem_with_type.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem_with_type[bits(32) address, integer size, AccessDescriptor accdesc]">Mem_with_type</a>[address, size, accdesc];</line>
<line></line>
<line>// MemU_unpriv[] - assignment form</line>
<line>// ===============================</line>
<line></line>
<line link="impl-aarch32.MemU_unpriv.write.2" hover="accessor: MemU_unpriv[bits(32) address, integer size] = bits(8*size) value" conts="MemU_unpriv"><anchor link="impl-aarch32.MemU_unpriv.write.2" hover="accessor: MemU_unpriv[bits(32) address, integer size] = bits(8*size) value">MemU_unpriv</anchor>[bits(32) address, integer size] = bits(8*size) value</line>
<line>    boolean nontemporal = FALSE;</line>
<line>    boolean privileged = FALSE;</line>
<line>    boolean tagchecked = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescGPR.4" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescGPR(MemOp memop, boolean nontemporal, boolean privileged, boolean tagchecked)">CreateAccDescGPR</a>(<a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>, nontemporal, privileged, tagchecked);</line>
<line>    Mem_with_type[address, size, accdesc] = value;</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/memory/Mem_with_type" mylink="aarch32.functions.memory.Mem_with_type" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Mem_with_type[] - non-assignment (read) form</line>
<line>// ============================================</line>
<line>// Perform a read of 'size' bytes. The access byte order is reversed for a big-endian access.</line>
<line>// Instruction fetches would call AArch32.MemSingle directly.</line>
<line></line>
<line link="impl-aarch32.Mem_with_type.read.3" hover="accessor: bits(size*8) Mem_with_type[bits(32) address, integer size, AccessDescriptor accdesc]" conts="Mem_with_type">bits(size*8) <anchor link="impl-aarch32.Mem_with_type.read.3" hover="accessor: bits(size*8) Mem_with_type[bits(32) address, integer size, AccessDescriptor accdesc]">Mem_with_type</anchor>[bits(32) address, integer size, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc]</line>
<line>    boolean ispair = FALSE;</line>
<line>    return <a link="impl-aarch32.Mem_with_type.read.4" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem_with_type[bits(32) address, integer size, AccessDescriptor accdesc, boolean ispair]">Mem_with_type</a>[address, size, accdesc, ispair];</line>
<line></line>
<line link="impl-aarch32.Mem_with_type.read.4" hover="accessor: bits(size*8) Mem_with_type[bits(32) address, integer size, AccessDescriptor accdesc, boolean ispair]" conts="Mem_with_type">bits(size*8) <anchor link="impl-aarch32.Mem_with_type.read.4" hover="accessor: bits(size*8) Mem_with_type[bits(32) address, integer size, AccessDescriptor accdesc, boolean ispair]">Mem_with_type</anchor>[bits(32) address, integer size, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, boolean ispair]</line>
<line>    assert size IN {1, 2, 4, 8, 16};</line>
<line>    constant halfsize = size DIV 2;</line>
<line>    bits(size * 8) value;</line>
<line></line>
<line>    // Check alignment on size of element accessed, not overall access size</line>
<line>    integer alignment = if ispair then halfsize else size;</line>
<line>    boolean aligned   = <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment);</line>
<line></line>
<line>    if !aligned &amp;&amp; <a link="AArch32.UnalignedAccessFaults.1" file="shared_pseudocode.xml" hover="function: boolean AArch32.UnalignedAccessFaults(AccessDescriptor accdesc)">AArch32.UnalignedAccessFaults</a>(accdesc) then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    if aligned then</line>
<line>        value = <a link="AArch32.MemSingle.read.5" file="shared_pseudocode.xml" hover="accessor: bits(size*8) AArch32.MemSingle[bits(32) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair]">AArch32.MemSingle</a>[address, size, accdesc, aligned, ispair];</line>
<line>    else</line>
<line>        assert size &gt; 1;</line>
<line>        value&lt;7:0&gt; = <a link="AArch32.MemSingle.read.4" file="shared_pseudocode.xml" hover="accessor: bits(size*8) AArch32.MemSingle[bits(32) address, integer size, AccessDescriptor accdesc, boolean aligned]">AArch32.MemSingle</a>[address, 1, accdesc, aligned];</line>
<line></line>
<line>        // For subsequent bytes it is CONSTRAINED UNPREDICTABLE whether an unaligned Device memory</line>
<line>        // access will generate an Alignment Fault, as to get this far means the first byte did</line>
<line>        // not, so we must be changing to a new translation page.</line>
<line>        c = <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_DEVPAGE2" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_DEVPAGE2</a>);</line>
<line>        assert c IN {<a link="Constraint_FAULT" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_FAULT</a>, <a link="Constraint_NONE" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NONE</a>};</line>
<line>        if c == <a link="Constraint_NONE" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NONE</a> then aligned = TRUE;</line>
<line></line>
<line>        for i = 1 to size-1</line>
<line>            value&lt;8*i+7:8*i&gt; = <a link="AArch32.MemSingle.read.4" file="shared_pseudocode.xml" hover="accessor: bits(size*8) AArch32.MemSingle[bits(32) address, integer size, AccessDescriptor accdesc, boolean aligned]">AArch32.MemSingle</a>[address+i, 1, accdesc, aligned];</line>
<line></line>
<line>    if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(accdesc.acctype) then</line>
<line>        value = <a link="impl-shared.BigEndianReverse.1" file="shared_pseudocode.xml" hover="function: bits(width) BigEndianReverse (bits(width) value)">BigEndianReverse</a>(value);</line>
<line></line>
<line>    return value;</line>
<line></line>
<line>// Mem_with_type[] - assignment (write) form</line>
<line>// =========================================</line>
<line>// Perform a write of 'size' bytes. The byte order is reversed for a big-endian access.</line>
<line></line>
<line>Mem_with_type[bits(32) address, integer size, AccessDescriptor accdesc] = bits(size*8) value_in</line>
<line>    boolean ispair = FALSE;</line>
<line>    Mem_with_type[address, size, accdesc, ispair] = value_in;</line>
<line></line>
<line>Mem_with_type[bits(32) address, integer size, AccessDescriptor accdesc,</line>
<line>        boolean ispair] = bits(size*8) value_in</line>
<line>    constant halfsize = size DIV 2;</line>
<line>    bits(size*8) value = value_in;</line>
<line></line>
<line>    // Check alignment on size of element accessed, not overall access size</line>
<line>    integer alignment = if ispair then halfsize else size;</line>
<line>    boolean aligned   = <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment);</line>
<line></line>
<line>    if !aligned &amp;&amp; <a link="AArch32.UnalignedAccessFaults.1" file="shared_pseudocode.xml" hover="function: boolean AArch32.UnalignedAccessFaults(AccessDescriptor accdesc)">AArch32.UnalignedAccessFaults</a>(accdesc) then</line>
<line>        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(accdesc.acctype) then</line>
<line>        value = <a link="impl-shared.BigEndianReverse.1" file="shared_pseudocode.xml" hover="function: bits(width) BigEndianReverse (bits(width) value)">BigEndianReverse</a>(value);</line>
<line></line>
<line>    if aligned then</line>
<line>        <a link="AArch32.MemSingle.write.5" file="shared_pseudocode.xml" hover="accessor: AArch32.MemSingle[bits(32) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair] = bits(size*8) value">AArch32.MemSingle</a>[address, size, accdesc, aligned, ispair] = value;</line>
<line>    else</line>
<line>        assert size &gt; 1;</line>
<line>        <a link="AArch32.MemSingle.write.4" file="shared_pseudocode.xml" hover="accessor: AArch32.MemSingle[bits(32) address, integer size, AccessDescriptor accdesc, boolean aligned] = bits(size*8) value">AArch32.MemSingle</a>[address, 1, accdesc, aligned] = value&lt;7:0&gt;;</line>
<line></line>
<line>        // For subsequent bytes it is CONSTRAINED UNPREDICTABLE whether an unaligned Device memory</line>
<line>        // access will generate an Alignment Fault, as to get this far means the first byte did</line>
<line>        // not, so we must be changing to a new translation page.</line>
<line></line>
<line>        c = <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_DEVPAGE2" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_DEVPAGE2</a>);</line>
<line>        assert c IN {<a link="Constraint_FAULT" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_FAULT</a>, <a link="Constraint_NONE" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NONE</a>};</line>
<line>        if c == <a link="Constraint_NONE" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NONE</a> then aligned = TRUE;</line>
<line></line>
<line>        for i = 1 to size-1</line>
<line>            <a link="AArch32.MemSingle.write.4" file="shared_pseudocode.xml" hover="accessor: AArch32.MemSingle[bits(32) address, integer size, AccessDescriptor accdesc, boolean aligned] = bits(size*8) value">AArch32.MemSingle</a>[address+i, 1, accdesc, aligned] = value&lt;8*i+7:8*i&gt;;</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/ras/AArch32.ESBOperation" mylink="aarch32.functions.ras.AArch32.ESBOperation" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.ESBOperation()</line>
<line>// ======================</line>
<line>// Perform the AArch32 ESB operation for ESB executed in AArch32 state</line>
<line></line>
<line link="AArch32.ESBOperation.0" hover="function: AArch32.ESBOperation()" conts="AArch32.ESBOperation"><anchor link="AArch32.ESBOperation.0" hover="function: AArch32.ESBOperation()">AArch32.ESBOperation</anchor>()</line>
<line></line>
<line>    // Check if routed to AArch64 state</line>
<line>    route_to_aarch64 = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line>    if !route_to_aarch64 &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>        route_to_aarch64 = HCR_EL2.TGE == '1' || HCR_EL2.AMO == '1';</line>
<line>    if !route_to_aarch64 &amp;&amp; <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        route_to_aarch64 = <a link="impl-shared.EffectiveEA.0" file="shared_pseudocode.xml" hover="function: bit EffectiveEA()">EffectiveEA</a>() == '1';</line>
<line></line>
<line>    if route_to_aarch64 then</line>
<line>        <a link="AArch64.ESBOperation.0" file="shared_pseudocode.xml" hover="function: AArch64.ESBOperation()">AArch64.ESBOperation</a>();</line>
<line>        return;</line>
<line></line>
<line>    route_to_monitor = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.EffectiveEA.0" file="shared_pseudocode.xml" hover="function: bit EffectiveEA()">EffectiveEA</a>() == '1';</line>
<line>    route_to_hyp = PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; (HCR.TGE == '1' || HCR.AMO == '1');</line>
<line></line>
<line>    bits(5) target;</line>
<line>    if route_to_monitor then</line>
<line>        target = <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a>;</line>
<line>    elsif route_to_hyp || PSTATE.M == <a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a> then</line>
<line>        target = <a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a>;</line>
<line>    else</line>
<line>        target = <a link="M32_Abort" file="shared_pseudocode.xml" hover="constant bits(5) M32_Abort = '10111'">M32_Abort</a>;</line>
<line></line>
<line>    boolean mask_active;</line>
<line>    if <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>        mask_active = TRUE;</line>
<line>    elsif target == <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a> then</line>
<line>        mask_active = SCR.AW == '1' &amp;&amp; (!<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) || (HCR.TGE == '0' &amp;&amp; HCR.AMO == '0'));</line>
<line>    else</line>
<line>        mask_active = target == <a link="M32_Abort" file="shared_pseudocode.xml" hover="constant bits(5) M32_Abort = '10111'">M32_Abort</a> || PSTATE.M == <a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a>;</line>
<line></line>
<line>    mask_set = PSTATE.A == '1';</line>
<line>    (-, el)  = <a link="impl-shared.ELFromM32.1" file="shared_pseudocode.xml" hover="function: (boolean,bits(2)) ELFromM32(bits(5) mode)">ELFromM32</a>(target);</line>
<line>    intdis   = <a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() || <a link="impl-shared.ExternalDebugInterruptsDisabled.1" file="shared_pseudocode.xml" hover="function: boolean ExternalDebugInterruptsDisabled(bits(2) target)">ExternalDebugInterruptsDisabled</a>(el);</line>
<line>    masked   = intdis || (mask_active &amp;&amp; mask_set);</line>
<line></line>
<line>    // Check for a masked Physical SError pending that can be synchronized</line>
<line>    // by an Error synchronization event.</line>
<line>    if masked &amp;&amp; <a link="impl-shared.IsSynchronizablePhysicalSErrorPending.0" file="shared_pseudocode.xml" hover="function: boolean IsSynchronizablePhysicalSErrorPending()">IsSynchronizablePhysicalSErrorPending</a>() then</line>
<line>        bits(32) syndrome = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32);</line>
<line>        syndrome&lt;31&gt; = '1';  // A</line>
<line>        syndrome&lt;15:0&gt; = <a link="AArch32.PhysicalSErrorSyndrome.0" file="shared_pseudocode.xml" hover="function: bits(16) AArch32.PhysicalSErrorSyndrome()">AArch32.PhysicalSErrorSyndrome</a>();</line>
<line>        DISR = syndrome;</line>
<line>        <a link="impl-shared.ClearPendingPhysicalSError.0" file="shared_pseudocode.xml" hover="function: ClearPendingPhysicalSError()">ClearPendingPhysicalSError</a>();</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/ras/AArch32.EncodeAsyncErrorSyndrome" mylink="aarch32.functions.ras.AArch32.EncodeAsyncErrorSyndrome" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.EncodeAsyncErrorSyndrome()</line>
<line>// ==================================</line>
<line>// Return the corresponding encoding for ErrorState.</line>
<line></line>
<line link="AArch32.EncodeAsyncErrorSyndrome.1" hover="function: bits(2) AArch32.EncodeAsyncErrorSyndrome(ErrorState errorstate)" conts="AArch32.EncodeAsyncErrorSyndrome">bits(2) <anchor link="AArch32.EncodeAsyncErrorSyndrome.1" hover="function: bits(2) AArch32.EncodeAsyncErrorSyndrome(ErrorState errorstate)">AArch32.EncodeAsyncErrorSyndrome</anchor>(<a link="ErrorState" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState</a> errorstate)</line>
<line>    case errorstate of</line>
<line>        when <a link="ErrorState_UC" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UC</a>   return '00';</line>
<line>        when <a link="ErrorState_UEU" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UEU</a>  return '01';</line>
<line>        when <a link="ErrorState_UEO" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UEO</a>  return '10';</line>
<line>        when <a link="ErrorState_UER" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UER</a>  return '11';</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/ras/AArch32.PhysicalSErrorSyndrome" mylink="aarch32.functions.ras.AArch32.PhysicalSErrorSyndrome" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.PhysicalSErrorSyndrome()</line>
<line>// ================================</line>
<line>// Generate SError syndrome.</line>
<line></line>
<line link="AArch32.PhysicalSErrorSyndrome.0" hover="function: bits(16) AArch32.PhysicalSErrorSyndrome()" conts="AArch32.PhysicalSErrorSyndrome">bits(16) <anchor link="AArch32.PhysicalSErrorSyndrome.0" hover="function: bits(16) AArch32.PhysicalSErrorSyndrome()">AArch32.PhysicalSErrorSyndrome</anchor>()</line>
<line>    bits(32) syndrome = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32);</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = <a link="impl-shared.GetPendingPhysicalSError.0" file="shared_pseudocode.xml" hover="function: FaultRecord GetPendingPhysicalSError()">GetPendingPhysicalSError</a>();</line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>        <a link="ErrorState" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState</a> errstate = <a link="AArch32.PEErrorState.1" file="shared_pseudocode.xml" hover="function: ErrorState AArch32.PEErrorState(FaultRecord fault)">AArch32.PEErrorState</a>(fault);</line>
<line>        syndrome&lt;11:10&gt; = <a link="AArch32.EncodeAsyncErrorSyndrome.1" file="shared_pseudocode.xml" hover="function: bits(2) AArch32.EncodeAsyncErrorSyndrome(ErrorState errorstate)">AArch32.EncodeAsyncErrorSyndrome</a>(errstate);   // AET</line>
<line>        syndrome&lt;9&gt;     = fault.extflag;                                // EA</line>
<line>        syndrome&lt;5:0&gt;   = '010001';                                     // DFSC</line>
<line>    else</line>
<line>        boolean long_format = TTBCR.EAE == '1';</line>
<line>        syndrome = <a link="AArch32.CommonFaultStatus.2" file="shared_pseudocode.xml" hover="function: bits(32) AArch32.CommonFaultStatus(FaultRecord fault, boolean long_format)">AArch32.CommonFaultStatus</a>(fault, long_format);</line>
<line>    return syndrome&lt;15:0&gt;;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/ras/AArch32.vESBOperation" mylink="aarch32.functions.ras.AArch32.vESBOperation" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.vESBOperation()</line>
<line>// =======================</line>
<line>// Perform the ESB operation for virtual SError interrupts executed in AArch32 state</line>
<line></line>
<line link="AArch32.vESBOperation.0" hover="function: AArch32.vESBOperation()" conts="AArch32.vESBOperation"><anchor link="AArch32.vESBOperation.0" hover="function: AArch32.vESBOperation()">AArch32.vESBOperation</anchor>()</line>
<line>    assert PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>();</line>
<line></line>
<line>    // Check for EL2 using AArch64 state</line>
<line>    if !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>        <a link="AArch64.vESBOperation.0" file="shared_pseudocode.xml" hover="function: AArch64.vESBOperation()">AArch64.vESBOperation</a>();</line>
<line>        return;</line>
<line></line>
<line>    // If physical SError interrupts are routed to Hyp mode, and TGE is not set,</line>
<line>    // then a virtual SError interrupt might be pending</line>
<line>    vSEI_enabled = HCR.TGE == '0' &amp;&amp; HCR.AMO == '1';</line>
<line>    vSEI_pending = vSEI_enabled &amp;&amp; HCR.VA == '1';</line>
<line>    vintdis      = <a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() || <a link="impl-shared.ExternalDebugInterruptsDisabled.1" file="shared_pseudocode.xml" hover="function: boolean ExternalDebugInterruptsDisabled(bits(2) target)">ExternalDebugInterruptsDisabled</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line>    vmasked      = vintdis || PSTATE.A == '1';</line>
<line></line>
<line>    // Check for a masked virtual SError pending</line>
<line>    if vSEI_pending &amp;&amp; vmasked then</line>
<line>        bits(32) syndrome = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32);</line>
<line>        syndrome&lt;31&gt; = '1';              // A</line>
<line>        syndrome&lt;15:14&gt; = VDFSR&lt;15:14&gt;;  // AET</line>
<line>        syndrome&lt;12&gt;    = VDFSR&lt;12&gt;;     // ExT</line>
<line>        syndrome&lt;9&gt;     = TTBCR.EAE;     // LPAE</line>
<line>        if TTBCR.EAE == '1' then         // Long-descriptor format</line>
<line>            syndrome&lt;5:0&gt;    = '010001'; // STATUS</line>
<line>        else                             // Short-descriptor format</line>
<line>            syndrome&lt;10,3:0&gt; = '10110';  // FS</line>
<line>        VDISR = syndrome;</line>
<line>        HCR.VA = '0';                    // Clear pending virtual SError</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/AArch32.ResetGeneralRegisters" mylink="aarch32.functions.registers.AArch32.ResetGeneralRegisters" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.ResetGeneralRegisters()</line>
<line>// ===============================</line>
<line></line>
<line link="AArch32.ResetGeneralRegisters.0" hover="function: AArch32.ResetGeneralRegisters()" conts="AArch32.ResetGeneralRegisters"><anchor link="AArch32.ResetGeneralRegisters.0" hover="function: AArch32.ResetGeneralRegisters()">AArch32.ResetGeneralRegisters</anchor>()</line>
<line></line>
<line>    for i = 0 to 7</line>
<line>        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[i] = bits(32) UNKNOWN;</line>
<line>    for i = 8 to 12</line>
<line>        <a link="impl-aarch32.Rmode.write.2" file="shared_pseudocode.xml" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</a>[i, <a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a>] = bits(32) UNKNOWN;</line>
<line>        <a link="impl-aarch32.Rmode.write.2" file="shared_pseudocode.xml" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</a>[i, <a link="M32_FIQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_FIQ = '10001'">M32_FIQ</a>] = bits(32) UNKNOWN;</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then <a link="impl-aarch32.Rmode.write.2" file="shared_pseudocode.xml" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</a>[13, <a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a>] = bits(32) UNKNOWN;   // No R14_hyp</line>
<line>    for i = 13 to 14</line>
<line>        <a link="impl-aarch32.Rmode.write.2" file="shared_pseudocode.xml" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</a>[i, <a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a>] = bits(32) UNKNOWN;</line>
<line>        <a link="impl-aarch32.Rmode.write.2" file="shared_pseudocode.xml" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</a>[i, <a link="M32_FIQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_FIQ = '10001'">M32_FIQ</a>] = bits(32) UNKNOWN;</line>
<line>        <a link="impl-aarch32.Rmode.write.2" file="shared_pseudocode.xml" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</a>[i, <a link="M32_IRQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_IRQ = '10010'">M32_IRQ</a>] = bits(32) UNKNOWN;</line>
<line>        <a link="impl-aarch32.Rmode.write.2" file="shared_pseudocode.xml" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</a>[i, <a link="M32_Svc" file="shared_pseudocode.xml" hover="constant bits(5) M32_Svc = '10011'">M32_Svc</a>] = bits(32) UNKNOWN;</line>
<line>        <a link="impl-aarch32.Rmode.write.2" file="shared_pseudocode.xml" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</a>[i, <a link="M32_Abort" file="shared_pseudocode.xml" hover="constant bits(5) M32_Abort = '10111'">M32_Abort</a>] = bits(32) UNKNOWN;</line>
<line>        <a link="impl-aarch32.Rmode.write.2" file="shared_pseudocode.xml" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</a>[i, <a link="M32_Undef" file="shared_pseudocode.xml" hover="constant bits(5) M32_Undef = '11011'">M32_Undef</a>] = bits(32) UNKNOWN;</line>
<line>        if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then <a link="impl-aarch32.Rmode.write.2" file="shared_pseudocode.xml" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</a>[i, <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a>] = bits(32) UNKNOWN;</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/AArch32.ResetSIMDFPRegisters" mylink="aarch32.functions.registers.AArch32.ResetSIMDFPRegisters" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.ResetSIMDFPRegisters()</line>
<line>// ==============================</line>
<line></line>
<line link="AArch32.ResetSIMDFPRegisters.0" hover="function: AArch32.ResetSIMDFPRegisters()" conts="AArch32.ResetSIMDFPRegisters"><anchor link="AArch32.ResetSIMDFPRegisters.0" hover="function: AArch32.ResetSIMDFPRegisters()">AArch32.ResetSIMDFPRegisters</anchor>()</line>
<line></line>
<line>    for i = 0 to 15</line>
<line>        <a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[i] = bits(128) UNKNOWN;</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/AArch32.ResetSpecialRegisters" mylink="aarch32.functions.registers.AArch32.ResetSpecialRegisters" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.ResetSpecialRegisters()</line>
<line>// ===============================</line>
<line></line>
<line link="AArch32.ResetSpecialRegisters.0" hover="function: AArch32.ResetSpecialRegisters()" conts="AArch32.ResetSpecialRegisters"><anchor link="AArch32.ResetSpecialRegisters.0" hover="function: AArch32.ResetSpecialRegisters()">AArch32.ResetSpecialRegisters</anchor>()</line>
<line></line>
<line>    // AArch32 special registers</line>
<line>    SPSR_fiq&lt;31:0&gt; = bits(32) UNKNOWN;</line>
<line>    SPSR_irq&lt;31:0&gt; = bits(32) UNKNOWN;</line>
<line>    SPSR_svc&lt;31:0&gt; = bits(32) UNKNOWN;</line>
<line>    SPSR_abt&lt;31:0&gt; = bits(32) UNKNOWN;</line>
<line>    SPSR_und&lt;31:0&gt; = bits(32) UNKNOWN;</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>        SPSR_hyp = bits(32) UNKNOWN;</line>
<line>        ELR_hyp = bits(32) UNKNOWN;</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        SPSR_mon = bits(32) UNKNOWN;</line>
<line></line>
<line>    // External debug special registers</line>
<line>    DLR = bits(32) UNKNOWN;</line>
<line>    DSPSR = bits(32) UNKNOWN;</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/AArch32.ResetSystemRegisters" mylink="aarch32.functions.registers.AArch32.ResetSystemRegisters" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.ResetSystemRegisters()</line>
<line>// ==============================</line>
<line></line>
<line link="AArch32.ResetSystemRegisters.1" hover="function: AArch32.ResetSystemRegisters(boolean cold_reset)" conts="AArch32.ResetSystemRegisters"><anchor link="AArch32.ResetSystemRegisters.1" hover="function: AArch32.ResetSystemRegisters(boolean cold_reset)">AArch32.ResetSystemRegisters</anchor>(boolean cold_reset);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/ALUExceptionReturn" mylink="aarch32.functions.registers.ALUExceptionReturn" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ALUExceptionReturn()</line>
<line>// ====================</line>
<line></line>
<line link="impl-aarch32.ALUExceptionReturn.1" hover="function: ALUExceptionReturn(bits(32) address)" conts="ALUExceptionReturn"><anchor link="impl-aarch32.ALUExceptionReturn.1" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</anchor>(bits(32) address)</line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>        UNDEFINED;</line>
<line>    elsif PSTATE.M IN {<a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a>,<a link="M32_System" file="shared_pseudocode.xml" hover="constant bits(5) M32_System = '11111'">M32_System</a>} then</line>
<line>        <a link="Constraint" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint</a> c = <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_ALUEXCEPTIONRETURN" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_ALUEXCEPTIONRETURN</a>);</line>
<line>        assert c IN {<a link="Constraint_UNDEF" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNDEF</a>, <a link="Constraint_NOP" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NOP</a>};</line>
<line>        case c of</line>
<line>            when <a link="Constraint_UNDEF" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNDEF</a></line>
<line>                UNDEFINED;</line>
<line>            when <a link="Constraint_NOP" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NOP</a></line>
<line>                <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
<line>    else</line>
<line>        <a link="AArch32.ExceptionReturn.2" file="shared_pseudocode.xml" hover="function: AArch32.ExceptionReturn(bits(32) new_pc_in, bits(32) spsr)">AArch32.ExceptionReturn</a>(address, <a link="impl-shared.SPSR.read.0" file="shared_pseudocode.xml" hover="accessor: bits(N) SPSR[]">SPSR</a>[]);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/ALUWritePC" mylink="aarch32.functions.registers.ALUWritePC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ALUWritePC()</line>
<line>// ============</line>
<line></line>
<line link="impl-aarch32.ALUWritePC.1" hover="function: ALUWritePC(bits(32) address)" conts="ALUWritePC"><anchor link="impl-aarch32.ALUWritePC.1" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</anchor>(bits(32) address)</line>
<line>    if <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then</line>
<line>        <a link="impl-aarch32.BXWritePC.2" file="shared_pseudocode.xml" hover="function: BXWritePC(bits(32) address_in, BranchType branch_type)">BXWritePC</a>(address, <a link="BranchType_INDIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDIR</a>);</line>
<line>    else</line>
<line>        <a link="impl-aarch32.BranchWritePC.2" file="shared_pseudocode.xml" hover="function: BranchWritePC(bits(32) address_in, BranchType branch_type)">BranchWritePC</a>(address, <a link="BranchType_INDIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDIR</a>);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/BXWritePC" mylink="aarch32.functions.registers.BXWritePC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BXWritePC()</line>
<line>// ===========</line>
<line></line>
<line link="impl-aarch32.BXWritePC.2" hover="function: BXWritePC(bits(32) address_in, BranchType branch_type)" conts="BXWritePC"><anchor link="impl-aarch32.BXWritePC.2" hover="function: BXWritePC(bits(32) address_in, BranchType branch_type)">BXWritePC</anchor>(bits(32) address_in, <a link="BranchType" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType</a> branch_type)</line>
<line>    bits(32) address = address_in;</line>
<line>    if address&lt;0&gt; == '1' then</line>
<line>        <a link="impl-aarch32.SelectInstrSet.1" file="shared_pseudocode.xml" hover="function: SelectInstrSet(InstrSet iset)">SelectInstrSet</a>(<a link="InstrSet_T32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_T32</a>);</line>
<line>        address&lt;0&gt; = '0';</line>
<line>    else</line>
<line>        <a link="impl-aarch32.SelectInstrSet.1" file="shared_pseudocode.xml" hover="function: SelectInstrSet(InstrSet iset)">SelectInstrSet</a>(<a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>);</line>
<line>        // For branches to an unaligned PC counter in A32 state, the processor takes the branch</line>
<line>        // and does one of:</line>
<line>        // * Forces the address to be aligned</line>
<line>        // * Leaves the PC unaligned, meaning the target generates a PC Alignment fault.</line>
<line>        if address&lt;1&gt; == '1' &amp;&amp; <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_A32FORCEALIGNPC" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_A32FORCEALIGNPC</a>) then</line>
<line>            address&lt;1&gt; = '0';</line>
<line>    boolean branch_conditional = !(<a link="AArch32.CurrentCond.0" file="shared_pseudocode.xml" hover="function: bits(4) AArch32.CurrentCond()">AArch32.CurrentCond</a>() IN {'111x'});</line>
<line>    <a link="impl-shared.BranchTo.3" file="shared_pseudocode.xml" hover="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(address, branch_type, branch_conditional);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/BranchWritePC" mylink="aarch32.functions.registers.BranchWritePC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BranchWritePC()</line>
<line>// ===============</line>
<line></line>
<line link="impl-aarch32.BranchWritePC.2" hover="function: BranchWritePC(bits(32) address_in, BranchType branch_type)" conts="BranchWritePC"><anchor link="impl-aarch32.BranchWritePC.2" hover="function: BranchWritePC(bits(32) address_in, BranchType branch_type)">BranchWritePC</anchor>(bits(32) address_in, <a link="BranchType" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType</a> branch_type)</line>
<line>    bits(32) address = address_in;</line>
<line>    if <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then</line>
<line>        address&lt;1:0&gt; = '00';</line>
<line>    else</line>
<line>        address&lt;0&gt; = '0';</line>
<line>    boolean branch_conditional = !(<a link="AArch32.CurrentCond.0" file="shared_pseudocode.xml" hover="function: bits(4) AArch32.CurrentCond()">AArch32.CurrentCond</a>() IN {'111x'});</line>
<line>    <a link="impl-shared.BranchTo.3" file="shared_pseudocode.xml" hover="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(address, branch_type, branch_conditional);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/CBWritePC" mylink="aarch32.functions.registers.CBWritePC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CBWritePC()</line>
<line>// ===========</line>
<line>// Takes a branch from a CBNZ/CBZ instruction.</line>
<line></line>
<line link="impl-aarch32.CBWritePC.1" hover="function: CBWritePC(bits(32) address_in)" conts="CBWritePC"><anchor link="impl-aarch32.CBWritePC.1" hover="function: CBWritePC(bits(32) address_in)">CBWritePC</anchor>(bits(32) address_in)</line>
<line>    bits(32) address = address_in;</line>
<line>    assert <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_T32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_T32</a>;</line>
<line>    address&lt;0&gt; = '0';</line>
<line>    boolean branch_conditional = TRUE;</line>
<line>    <a link="impl-shared.BranchTo.3" file="shared_pseudocode.xml" hover="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(address, <a link="BranchType_DIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</a>, branch_conditional);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/D" mylink="aarch32.functions.registers.D" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// D[] - non-assignment form</line>
<line>// =========================</line>
<line></line>
<line link="impl-aarch32.D.read.1" hover="accessor: bits(64) D[integer n]" conts="D">bits(64) <anchor link="impl-aarch32.D.read.1" hover="accessor: bits(64) D[integer n]">D</anchor>[integer n]</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt;= 31;</line>
<line>    base = (n MOD 2) * 64;</line>
<line>    bits(128) vreg = V[n DIV 2, 128];</line>
<line>    return vreg&lt;base+63:base&gt;;</line>
<line></line>
<line>// D[] - assignment form</line>
<line>// =====================</line>
<line></line>
<line link="impl-aarch32.D.write.1" hover="accessor: D[integer n] = bits(64) value" conts="D"><anchor link="impl-aarch32.D.write.1" hover="accessor: D[integer n] = bits(64) value">D</anchor>[integer n] = bits(64) value</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt;= 31;</line>
<line>    base = (n MOD 2) * 64;</line>
<line>    bits(128) vreg = V[n DIV 2, 128];</line>
<line>    vreg&lt;base+63:base&gt; = value;</line>
<line>    V[n DIV 2, 128] = vreg;</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/Din" mylink="aarch32.functions.registers.Din" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Din[] - non-assignment form</line>
<line>// ===========================</line>
<line></line>
<line link="impl-aarch32.Din.read.1" hover="accessor: bits(64) Din[integer n]" conts="Din">bits(64) <anchor link="impl-aarch32.Din.read.1" hover="accessor: bits(64) Din[integer n]">Din</anchor>[integer n]</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt;= 31;</line>
<line>    return _Dclone[n];</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/LR" mylink="aarch32.functions.registers.LR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// LR - assignment form</line>
<line>// ====================</line>
<line></line>
<line link="impl-aarch32.LR.write.none" hover="accessor: LR = bits(32) value" conts="LR"><anchor link="impl-aarch32.LR.write.none" hover="accessor: LR = bits(32) value">LR</anchor> = bits(32) value</line>
<line>    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[14] = value;</line>
<line>    return;</line>
<line></line>
<line>// LR - non-assignment form</line>
<line>// ========================</line>
<line></line>
<line link="impl-aarch32.LR.read.none" hover="accessor: bits(32) LR" conts="LR">bits(32) <anchor link="impl-aarch32.LR.read.none" hover="accessor: bits(32) LR">LR</anchor></line>
<line>    return <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[14];</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/LoadWritePC" mylink="aarch32.functions.registers.LoadWritePC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// LoadWritePC()</line>
<line>// =============</line>
<line></line>
<line link="impl-aarch32.LoadWritePC.1" hover="function: LoadWritePC(bits(32) address)" conts="LoadWritePC"><anchor link="impl-aarch32.LoadWritePC.1" hover="function: LoadWritePC(bits(32) address)">LoadWritePC</anchor>(bits(32) address)</line>
<line>    <a link="impl-aarch32.BXWritePC.2" file="shared_pseudocode.xml" hover="function: BXWritePC(bits(32) address_in, BranchType branch_type)">BXWritePC</a>(address, <a link="BranchType_INDIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDIR</a>);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/LookUpRIndex" mylink="aarch32.functions.registers.LookUpRIndex" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// LookUpRIndex()</line>
<line>// ==============</line>
<line></line>
<line link="impl-aarch32.LookUpRIndex.2" hover="function: integer LookUpRIndex(integer n, bits(5) mode)" conts="LookUpRIndex">integer <anchor link="impl-aarch32.LookUpRIndex.2" hover="function: integer LookUpRIndex(integer n, bits(5) mode)">LookUpRIndex</anchor>(integer n, bits(5) mode)</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt;= 14;</line>
<line></line>
<line>    integer result;</line>
<line>    case n of  // Select  index by mode:     usr fiq irq svc abt und hyp</line>
<line>        when 8     result = <a link="impl-aarch32.RBankSelect.8" file="shared_pseudocode.xml" hover="function: integer RBankSelect(bits(5) mode, integer usr, integer fiq, integer irq, integer svc, integer abt, integer und, integer hyp)">RBankSelect</a>(mode,  8, 24,  8,  8,  8,  8,  8);</line>
<line>        when 9     result = <a link="impl-aarch32.RBankSelect.8" file="shared_pseudocode.xml" hover="function: integer RBankSelect(bits(5) mode, integer usr, integer fiq, integer irq, integer svc, integer abt, integer und, integer hyp)">RBankSelect</a>(mode,  9, 25,  9,  9,  9,  9,  9);</line>
<line>        when 10    result = <a link="impl-aarch32.RBankSelect.8" file="shared_pseudocode.xml" hover="function: integer RBankSelect(bits(5) mode, integer usr, integer fiq, integer irq, integer svc, integer abt, integer und, integer hyp)">RBankSelect</a>(mode, 10, 26, 10, 10, 10, 10, 10);</line>
<line>        when 11    result = <a link="impl-aarch32.RBankSelect.8" file="shared_pseudocode.xml" hover="function: integer RBankSelect(bits(5) mode, integer usr, integer fiq, integer irq, integer svc, integer abt, integer und, integer hyp)">RBankSelect</a>(mode, 11, 27, 11, 11, 11, 11, 11);</line>
<line>        when 12    result = <a link="impl-aarch32.RBankSelect.8" file="shared_pseudocode.xml" hover="function: integer RBankSelect(bits(5) mode, integer usr, integer fiq, integer irq, integer svc, integer abt, integer und, integer hyp)">RBankSelect</a>(mode, 12, 28, 12, 12, 12, 12, 12);</line>
<line>        when 13    result = <a link="impl-aarch32.RBankSelect.8" file="shared_pseudocode.xml" hover="function: integer RBankSelect(bits(5) mode, integer usr, integer fiq, integer irq, integer svc, integer abt, integer und, integer hyp)">RBankSelect</a>(mode, 13, 29, 17, 19, 21, 23, 15);</line>
<line>        when 14    result = <a link="impl-aarch32.RBankSelect.8" file="shared_pseudocode.xml" hover="function: integer RBankSelect(bits(5) mode, integer usr, integer fiq, integer irq, integer svc, integer abt, integer und, integer hyp)">RBankSelect</a>(mode, 14, 30, 16, 18, 20, 22, 14);</line>
<line>        otherwise  result = n;</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/Monitor_mode_registers" mylink="aarch32.functions.registers.Monitor_mode_registers" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>bits(32) SP_mon;</line>
<line link="impl-aarch32.LR.read.none_2" hover="accessor: bits(32) LR" conts="LR">bits(32) <anchor link="impl-aarch32.LR.read.none_2" hover="accessor: bits(32) LR">LR</anchor>_mon;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/PC" mylink="aarch32.functions.registers.PC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PC - non-assignment form</line>
<line>// ========================</line>
<line></line>
<line link="impl-aarch32.PC.read.none" hover="accessor: bits(32) PC" conts="PC">bits(32) <anchor link="impl-aarch32.PC.read.none" hover="accessor: bits(32) PC">PC</anchor></line>
<line>    return <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[15];               // This includes the offset from AArch32 state</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/PCStoreValue" mylink="aarch32.functions.registers.PCStoreValue" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PCStoreValue()</line>
<line>// ==============</line>
<line></line>
<line link="impl-aarch32.PCStoreValue.0" hover="function: bits(32) PCStoreValue()" conts="PCStoreValue">bits(32) <anchor link="impl-aarch32.PCStoreValue.0" hover="function: bits(32) PCStoreValue()">PCStoreValue</anchor>()</line>
<line>    // This function returns the PC value. On architecture versions before Armv7, it</line>
<line>    // is permitted to instead return PC+4, provided it does so consistently. It is</line>
<line>    // used only to describe A32 instructions, so it returns the address of the current</line>
<line>    // instruction plus 8 (normally) or 12 (when the alternative is permitted).</line>
<line>    return <a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/Q" mylink="aarch32.functions.registers.Q" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Q[] - non-assignment form</line>
<line>// =========================</line>
<line></line>
<line link="impl-aarch32.Q.read.1" hover="accessor: bits(128) Q[integer n]" conts="Q">bits(128) <anchor link="impl-aarch32.Q.read.1" hover="accessor: bits(128) Q[integer n]">Q</anchor>[integer n]</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt;= 15;</line>
<line>    return V[n, 128];</line>
<line></line>
<line>// Q[] - assignment form</line>
<line>// =====================</line>
<line></line>
<line link="impl-aarch32.Q.write.1" hover="accessor: Q[integer n] = bits(128) value" conts="Q"><anchor link="impl-aarch32.Q.write.1" hover="accessor: Q[integer n] = bits(128) value">Q</anchor>[integer n] = bits(128) value</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt;= 15;</line>
<line>    V[n, 128] = value;</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/Qin" mylink="aarch32.functions.registers.Qin" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Qin[] - non-assignment form</line>
<line>// ===========================</line>
<line></line>
<line link="impl-aarch32.Qin.read.1" hover="accessor: bits(128) Qin[integer n]" conts="Qin">bits(128) <anchor link="impl-aarch32.Qin.read.1" hover="accessor: bits(128) Qin[integer n]">Qin</anchor>[integer n]</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt;= 15;</line>
<line>    return <a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[2*n+1]:<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[2*n];</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/R" mylink="aarch32.functions.registers.R" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// R[] - assignment form</line>
<line>// =====================</line>
<line></line>
<line link="impl-aarch32.R.write.1" hover="accessor: R[integer n] = bits(32) value" conts="R"><anchor link="impl-aarch32.R.write.1" hover="accessor: R[integer n] = bits(32) value">R</anchor>[integer n] = bits(32) value</line>
<line>    <a link="impl-aarch32.Rmode.write.2" file="shared_pseudocode.xml" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</a>[n, PSTATE.M] = value;</line>
<line>    return;</line>
<line></line>
<line>// R[] - non-assignment form</line>
<line>// =========================</line>
<line></line>
<line link="impl-aarch32.R.read.1" hover="accessor: bits(32) R[integer n]" conts="R">bits(32) <anchor link="impl-aarch32.R.read.1" hover="accessor: bits(32) R[integer n]">R</anchor>[integer n]</line>
<line>    if n == 15 then</line>
<line>        offset = (if <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then 8 else 4);</line>
<line>        return _PC&lt;31:0&gt; + offset;</line>
<line>    else</line>
<line>        return <a link="impl-aarch32.Rmode.read.2" file="shared_pseudocode.xml" hover="accessor: bits(32) Rmode[integer n, bits(5) mode]">Rmode</a>[n, PSTATE.M];</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/RBankSelect" mylink="aarch32.functions.registers.RBankSelect" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// RBankSelect()</line>
<line>// =============</line>
<line></line>
<line link="impl-aarch32.RBankSelect.8" hover="function: integer RBankSelect(bits(5) mode, integer usr, integer fiq, integer irq, integer svc, integer abt, integer und, integer hyp)" conts="RBankSelect">integer <anchor link="impl-aarch32.RBankSelect.8" hover="function: integer RBankSelect(bits(5) mode, integer usr, integer fiq, integer irq, integer svc, integer abt, integer und, integer hyp)">RBankSelect</anchor>(bits(5) mode, integer usr, integer fiq, integer irq,</line>
<line>                    integer svc, integer abt, integer und, integer hyp)</line>
<line></line>
<line>    integer result;</line>
<line>    case mode of</line>
<line>        when <a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a>    result = usr;  // User mode</line>
<line>        when <a link="M32_FIQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_FIQ = '10001'">M32_FIQ</a>     result = fiq;  // FIQ mode</line>
<line>        when <a link="M32_IRQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_IRQ = '10010'">M32_IRQ</a>     result = irq;  // IRQ mode</line>
<line>        when <a link="M32_Svc" file="shared_pseudocode.xml" hover="constant bits(5) M32_Svc = '10011'">M32_Svc</a>     result = svc;  // Supervisor mode</line>
<line>        when <a link="M32_Abort" file="shared_pseudocode.xml" hover="constant bits(5) M32_Abort = '10111'">M32_Abort</a>   result = abt;  // Abort mode</line>
<line>        when <a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a>     result = hyp;  // Hyp mode</line>
<line>        when <a link="M32_Undef" file="shared_pseudocode.xml" hover="constant bits(5) M32_Undef = '11011'">M32_Undef</a>   result = und;  // Undefined mode</line>
<line>        when <a link="M32_System" file="shared_pseudocode.xml" hover="constant bits(5) M32_System = '11111'">M32_System</a>  result = usr;  // System mode uses User mode registers</line>
<line>        otherwise        <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>(); // Monitor mode</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/Rmode" mylink="aarch32.functions.registers.Rmode" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Rmode[] - non-assignment form</line>
<line>// =============================</line>
<line></line>
<line link="impl-aarch32.Rmode.read.2" hover="accessor: bits(32) Rmode[integer n, bits(5) mode]" conts="Rmode">bits(32) <anchor link="impl-aarch32.Rmode.read.2" hover="accessor: bits(32) Rmode[integer n, bits(5) mode]">Rmode</anchor>[integer n, bits(5) mode]</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt;= 14;</line>
<line></line>
<line>    // Check for attempted use of Monitor mode in Non-secure state.</line>
<line>    if <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() != <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then assert mode != <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a>;</line>
<line>    assert !<a link="impl-aarch32.BadMode.1" file="shared_pseudocode.xml" hover="function: boolean BadMode(bits(5) mode)">BadMode</a>(mode);</line>
<line></line>
<line>    if mode == <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a> then</line>
<line>        if n == 13 then return SP_mon;</line>
<line>        elsif n == 14 then return LR_mon;</line>
<line>        else return _R[n]&lt;31:0&gt;;</line>
<line>    else</line>
<line>        return _R[<a link="impl-aarch32.LookUpRIndex.2" file="shared_pseudocode.xml" hover="function: integer LookUpRIndex(integer n, bits(5) mode)">LookUpRIndex</a>(n, mode)]&lt;31:0&gt;;</line>
<line></line>
<line>// Rmode[] - assignment form</line>
<line>// =========================</line>
<line></line>
<line link="impl-aarch32.Rmode.write.2" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value" conts="Rmode"><anchor link="impl-aarch32.Rmode.write.2" hover="accessor: Rmode[integer n, bits(5) mode] = bits(32) value">Rmode</anchor>[integer n, bits(5) mode] = bits(32) value</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt;= 14;</line>
<line></line>
<line>    // Check for attempted use of Monitor mode in Non-secure state.</line>
<line>    if <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() != <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then assert mode != <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a>;</line>
<line>    assert !<a link="impl-aarch32.BadMode.1" file="shared_pseudocode.xml" hover="function: boolean BadMode(bits(5) mode)">BadMode</a>(mode);</line>
<line></line>
<line>    if mode == <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a> then</line>
<line>        if n == 13 then SP_mon = value;</line>
<line>        elsif n == 14 then LR_mon = value;</line>
<line>        else _R[n]&lt;31:0&gt; = value;</line>
<line>    else</line>
<line>        // It is CONSTRAINED UNPREDICTABLE whether the upper 32 bits of the X</line>
<line>        // register are unchanged or set to zero. This is also tested for on</line>
<line>        // exception entry, as this applies to all AArch32 registers.</line>
<line>        if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() &amp;&amp; <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_ZEROUPPER" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_ZEROUPPER</a>) then</line>
<line>            _R[<a link="impl-aarch32.LookUpRIndex.2" file="shared_pseudocode.xml" hover="function: integer LookUpRIndex(integer n, bits(5) mode)">LookUpRIndex</a>(n, mode)] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(value, 64);</line>
<line>        else</line>
<line>            _R[<a link="impl-aarch32.LookUpRIndex.2" file="shared_pseudocode.xml" hover="function: integer LookUpRIndex(integer n, bits(5) mode)">LookUpRIndex</a>(n, mode)]&lt;31:0&gt; = value;</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/S" mylink="aarch32.functions.registers.S" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// S[] - non-assignment form</line>
<line>// =========================</line>
<line></line>
<line link="impl-aarch32.S.read.1" hover="accessor: bits(32) S[integer n]" conts="S">bits(32) <anchor link="impl-aarch32.S.read.1" hover="accessor: bits(32) S[integer n]">S</anchor>[integer n]</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt;= 31;</line>
<line>    base = (n MOD 4) * 32;</line>
<line>    bits(128) vreg = V[n DIV 4, 128];</line>
<line>    return vreg&lt;base+31:base&gt;;</line>
<line></line>
<line>// S[] - assignment form</line>
<line>// =====================</line>
<line></line>
<line link="impl-aarch32.S.write.1" hover="accessor: S[integer n] = bits(32) value" conts="S"><anchor link="impl-aarch32.S.write.1" hover="accessor: S[integer n] = bits(32) value">S</anchor>[integer n] = bits(32) value</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt;= 31;</line>
<line>    base = (n MOD 4) * 32;</line>
<line>    bits(128) vreg = V[n DIV 4, 128];</line>
<line>    vreg&lt;base+31:base&gt; = value;</line>
<line>    V[n DIV 4, 128] = vreg;</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/registers/_Dclone" mylink="aarch32.functions.registers._Dclone" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// _Dclone[]</line>
<line>// =========</line>
<line>// Clone the 64-bit Advanced SIMD and VFP extension register bank for use as input to</line>
<line>// instruction pseudocode, to avoid read-after-write for Advanced SIMD and VFP operations.</line>
<line></line>
<line>array bits(64) _Dclone[0..31];</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/system/AArch32.ExceptionReturn" mylink="aarch32.functions.system.AArch32.ExceptionReturn" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.ExceptionReturn()</line>
<line>// =========================</line>
<line></line>
<line link="AArch32.ExceptionReturn.2" hover="function: AArch32.ExceptionReturn(bits(32) new_pc_in, bits(32) spsr)" conts="AArch32.ExceptionReturn"><anchor link="AArch32.ExceptionReturn.2" hover="function: AArch32.ExceptionReturn(bits(32) new_pc_in, bits(32) spsr)">AArch32.ExceptionReturn</anchor>(bits(32) new_pc_in, bits(32) spsr)</line>
<line>    bits(32) new_pc = new_pc_in;</line>
<line>    <a link="impl-shared.SynchronizeContext.0" file="shared_pseudocode.xml" hover="function: SynchronizeContext()">SynchronizeContext</a>();</line>
<line>    // Attempts to change to an illegal mode or state will invoke the Illegal Execution state</line>
<line>    // mechanism</line>
<line>    <a link="impl-shared.SetPSTATEFromPSR.1" file="shared_pseudocode.xml" hover="function: SetPSTATEFromPSR(bits(N) spsr)">SetPSTATEFromPSR</a>(spsr);</line>
<line>    <a link="impl-shared.ClearExclusiveLocal.1" file="shared_pseudocode.xml" hover="function: ClearExclusiveLocal(integer processorid)">ClearExclusiveLocal</a>(<a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>());</line>
<line>    <a link="impl-shared.SendEventLocal.0" file="shared_pseudocode.xml" hover="function: SendEventLocal()">SendEventLocal</a>();</line>
<line></line>
<line>    if PSTATE.IL == '1' then</line>
<line>        // If the exception return is illegal, PC[1:0] are UNKNOWN</line>
<line>        new_pc&lt;1:0&gt; = bits(2) UNKNOWN;</line>
<line>    else</line>
<line>        // LR[1:0] or LR[0] are treated as being 0, depending on the target instruction set state</line>
<line>        if PSTATE.T == '1' then</line>
<line>            new_pc&lt;0&gt; = '0';                 // T32</line>
<line>        else</line>
<line>            new_pc&lt;1:0&gt; = '00';              // A32</line>
<line></line>
<line>    boolean branch_conditional = !(<a link="AArch32.CurrentCond.0" file="shared_pseudocode.xml" hover="function: bits(4) AArch32.CurrentCond()">AArch32.CurrentCond</a>() IN {'111x'});</line>
<line>    <a link="impl-shared.BranchTo.3" file="shared_pseudocode.xml" hover="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(new_pc, <a link="BranchType_ERET" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_ERET</a>, branch_conditional);</line>
<line></line>
<line>    <a link="impl-shared.CheckExceptionCatch.1" file="shared_pseudocode.xml" hover="function: CheckExceptionCatch(boolean exception_entry)">CheckExceptionCatch</a>(FALSE);              // Check for debug event on exception return</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/system/AArch32.ExecutingCP10or11Instr" mylink="aarch32.functions.system.AArch32.ExecutingCP10or11Instr" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.ExecutingCP10or11Instr()</line>
<line>// ================================</line>
<line></line>
<line link="AArch32.ExecutingCP10or11Instr.0" hover="function: boolean AArch32.ExecutingCP10or11Instr()" conts="AArch32.ExecutingCP10or11Instr">boolean <anchor link="AArch32.ExecutingCP10or11Instr.0" hover="function: boolean AArch32.ExecutingCP10or11Instr()">AArch32.ExecutingCP10or11Instr</anchor>()</line>
<line>    instr =  <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>();</line>
<line>    instr_set = <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>();</line>
<line>    assert instr_set IN {<a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>, <a link="InstrSet_T32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_T32</a>};</line>
<line></line>
<line>    if instr_set == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then</line>
<line>        return ((instr&lt;27:24&gt; == '1110' || instr&lt;27:25&gt; == '110') &amp;&amp; instr&lt;11:8&gt; IN {'101x'});</line>
<line>    else // InstrSet_T32</line>
<line>        return (instr&lt;31:28&gt; IN {'111x'} &amp;&amp; (instr&lt;27:24&gt; == '1110' || instr&lt;27:25&gt; == '110') &amp;&amp;</line>
<line>                instr&lt;11:8&gt; IN {'101x'});</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/system/AArch32.ITAdvance" mylink="aarch32.functions.system.AArch32.ITAdvance" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.ITAdvance()</line>
<line>// ===================</line>
<line></line>
<line link="AArch32.ITAdvance.0" hover="function: AArch32.ITAdvance()" conts="AArch32.ITAdvance"><anchor link="AArch32.ITAdvance.0" hover="function: AArch32.ITAdvance()">AArch32.ITAdvance</anchor>()</line>
<line>    if PSTATE.IT&lt;2:0&gt; == '000' then</line>
<line>        PSTATE.IT = '00000000';</line>
<line>    else</line>
<line>        PSTATE.IT&lt;4:0&gt; = <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(PSTATE.IT&lt;4:0&gt;, 1);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/system/AArch32.SysRegRead" mylink="aarch32.functions.system.AArch32.SysRegRead" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.SysRegRead()</line>
<line>// ====================</line>
<line>// Read from a 32-bit AArch32 System register and write the register's contents to R[t].</line>
<line></line>
<line link="AArch32.SysRegRead.3" hover="function: AArch32.SysRegRead(integer cp_num, bits(32) instr, integer t)" conts="AArch32.SysRegRead"><anchor link="AArch32.SysRegRead.3" hover="function: AArch32.SysRegRead(integer cp_num, bits(32) instr, integer t)">AArch32.SysRegRead</anchor>(integer cp_num, bits(32) instr, integer t);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/system/AArch32.SysRegRead64" mylink="aarch32.functions.system.AArch32.SysRegRead64" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.SysRegRead64()</line>
<line>// ======================</line>
<line>// Read from a 64-bit AArch32 System register and write the register's contents to R[t] and R[t2].</line>
<line></line>
<line link="AArch32.SysRegRead64.4" hover="function: AArch32.SysRegRead64(integer cp_num, bits(32) instr, integer t, integer t2)" conts="AArch32.SysRegRead64"><anchor link="AArch32.SysRegRead64.4" hover="function: AArch32.SysRegRead64(integer cp_num, bits(32) instr, integer t, integer t2)">AArch32.SysRegRead64</anchor>(integer cp_num, bits(32) instr, integer t, integer t2);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/system/AArch32.SysRegReadCanWriteAPSR" mylink="aarch32.functions.system.AArch32.SysRegReadCanWriteAPSR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.SysRegReadCanWriteAPSR()</line>
<line>// ================================</line>
<line>// Determines whether the AArch32 System register read instruction can write to APSR flags.</line>
<line></line>
<line link="AArch32.SysRegReadCanWriteAPSR.2" hover="function: boolean AArch32.SysRegReadCanWriteAPSR(integer cp_num, bits(32) instr)" conts="AArch32.SysRegReadCanWriteAPSR">boolean <anchor link="AArch32.SysRegReadCanWriteAPSR.2" hover="function: boolean AArch32.SysRegReadCanWriteAPSR(integer cp_num, bits(32) instr)">AArch32.SysRegReadCanWriteAPSR</anchor>(integer cp_num, bits(32) instr)</line>
<line>    assert <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>();</line>
<line>    assert (cp_num IN {14,15});</line>
<line>    assert cp_num == <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(instr&lt;11:8&gt;);</line>
<line></line>
<line>    opc1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(instr&lt;23:21&gt;);</line>
<line>    opc2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(instr&lt;7:5&gt;);</line>
<line>    CRn  = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(instr&lt;19:16&gt;);</line>
<line>    CRm  = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(instr&lt;3:0&gt;);</line>
<line></line>
<line>    if cp_num == 14 &amp;&amp; opc1 == 0 &amp;&amp; CRn == 0 &amp;&amp; CRm == 1 &amp;&amp; opc2 == 0 then // DBGDSCRint</line>
<line>        return TRUE;</line>
<line></line>
<line>    return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/system/AArch32.SysRegWrite" mylink="aarch32.functions.system.AArch32.SysRegWrite" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.SysRegWrite()</line>
<line>// =====================</line>
<line>// Read the contents of R[t] and write to a 32-bit AArch32 System register.</line>
<line></line>
<line link="AArch32.SysRegWrite.3" hover="function: AArch32.SysRegWrite(integer cp_num, bits(32) instr, integer t)" conts="AArch32.SysRegWrite"><anchor link="AArch32.SysRegWrite.3" hover="function: AArch32.SysRegWrite(integer cp_num, bits(32) instr, integer t)">AArch32.SysRegWrite</anchor>(integer cp_num, bits(32) instr, integer t);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/system/AArch32.SysRegWrite64" mylink="aarch32.functions.system.AArch32.SysRegWrite64" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.SysRegWrite64()</line>
<line>// =======================</line>
<line>// Read the contents of R[t] and R[t2] and write to a 64-bit AArch32 System register.</line>
<line></line>
<line link="AArch32.SysRegWrite64.4" hover="function: AArch32.SysRegWrite64(integer cp_num, bits(32) instr, integer t, integer t2)" conts="AArch32.SysRegWrite64"><anchor link="AArch32.SysRegWrite64.4" hover="function: AArch32.SysRegWrite64(integer cp_num, bits(32) instr, integer t, integer t2)">AArch32.SysRegWrite64</anchor>(integer cp_num, bits(32) instr, integer t, integer t2);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/system/AArch32.SysRegWriteM" mylink="aarch32.functions.system.AArch32.SysRegWriteM" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.SysRegWriteM()</line>
<line>// ======================</line>
<line>// Read a value from a virtual address and write it to an AArch32 System register.</line>
<line></line>
<line link="AArch32.SysRegWriteM.3" hover="function: AArch32.SysRegWriteM(integer cp_num, bits(32) instr, bits(32) address)" conts="AArch32.SysRegWriteM"><anchor link="AArch32.SysRegWriteM.3" hover="function: AArch32.SysRegWriteM(integer cp_num, bits(32) instr, bits(32) address)">AArch32.SysRegWriteM</anchor>(integer cp_num, bits(32) instr, bits(32) address);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/system/AArch32.WriteMode" mylink="aarch32.functions.system.AArch32.WriteMode" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.WriteMode()</line>
<line>// ===================</line>
<line>// Function for dealing with writes to PSTATE.M from AArch32 state only.</line>
<line>// This ensures that PSTATE.EL and PSTATE.SP are always valid.</line>
<line></line>
<line link="AArch32.WriteMode.1" hover="function: AArch32.WriteMode(bits(5) mode)" conts="AArch32.WriteMode"><anchor link="AArch32.WriteMode.1" hover="function: AArch32.WriteMode(bits(5) mode)">AArch32.WriteMode</anchor>(bits(5) mode)</line>
<line>    (valid,el) = <a link="impl-shared.ELFromM32.1" file="shared_pseudocode.xml" hover="function: (boolean,bits(2)) ELFromM32(bits(5) mode)">ELFromM32</a>(mode);</line>
<line>    assert valid;</line>
<line>    PSTATE.M   = mode;</line>
<line>    PSTATE.EL  = el;</line>
<line>    PSTATE.nRW = '1';</line>
<line>    PSTATE.SP  = (if mode IN {<a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a>,<a link="M32_System" file="shared_pseudocode.xml" hover="constant bits(5) M32_System = '11111'">M32_System</a>} then '0' else '1');</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/system/AArch32.WriteModeByInstr" mylink="aarch32.functions.system.AArch32.WriteModeByInstr" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.WriteModeByInstr()</line>
<line>// ==========================</line>
<line>// Function for dealing with writes to PSTATE.M from an AArch32 instruction, and ensuring that</line>
<line>// illegal state changes are correctly flagged in PSTATE.IL.</line>
<line></line>
<line link="AArch32.WriteModeByInstr.1" hover="function: AArch32.WriteModeByInstr(bits(5) mode)" conts="AArch32.WriteModeByInstr"><anchor link="AArch32.WriteModeByInstr.1" hover="function: AArch32.WriteModeByInstr(bits(5) mode)">AArch32.WriteModeByInstr</anchor>(bits(5) mode)</line>
<line>    (valid,el) = <a link="impl-shared.ELFromM32.1" file="shared_pseudocode.xml" hover="function: (boolean,bits(2)) ELFromM32(bits(5) mode)">ELFromM32</a>(mode);</line>
<line></line>
<line>    // 'valid' is set to FALSE if' mode' is invalid for this implementation or the current value</line>
<line>    // of SCR.NS/SCR_EL3.NS. Additionally, it is illegal for an instruction to write 'mode' to</line>
<line>    // PSTATE.EL if it would result in any of:</line>
<line>    // * A change to a mode that would cause entry to a higher Exception level.</line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(el) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL) then</line>
<line>        valid = FALSE;</line>
<line></line>
<line>    // * A change to or from Hyp mode.</line>
<line>    if (PSTATE.M == <a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a> || mode == <a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a>) &amp;&amp; PSTATE.M != mode then</line>
<line>        valid = FALSE;</line>
<line></line>
<line>    // * When EL2 is implemented, the value of HCR.TGE is '1', a change to a Non-secure EL1 mode.</line>
<line>    if PSTATE.M == <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a> &amp;&amp; <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; el == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; SCR.NS == '1' &amp;&amp; HCR.TGE == '1' then</line>
<line>        valid = FALSE;</line>
<line></line>
<line>    if !valid then</line>
<line>        PSTATE.IL = '1';</line>
<line>    else</line>
<line>        <a link="AArch32.WriteMode.1" file="shared_pseudocode.xml" hover="function: AArch32.WriteMode(bits(5) mode)">AArch32.WriteMode</a>(mode);</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/system/BadMode" mylink="aarch32.functions.system.BadMode" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BadMode()</line>
<line>// =========</line>
<line></line>
<line link="impl-aarch32.BadMode.1" hover="function: boolean BadMode(bits(5) mode)" conts="BadMode">boolean <anchor link="impl-aarch32.BadMode.1" hover="function: boolean BadMode(bits(5) mode)">BadMode</anchor>(bits(5) mode)</line>
<line>    // Return TRUE if 'mode' encodes a mode that is not valid for this implementation</line>
<line>    boolean valid;</line>
<line>    case mode of</line>
<line>        when <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a></line>
<line>            valid = <a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>        when <a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a></line>
<line>            valid = <a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>        when <a link="M32_FIQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_FIQ = '10001'">M32_FIQ</a>, <a link="M32_IRQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_IRQ = '10010'">M32_IRQ</a>, <a link="M32_Svc" file="shared_pseudocode.xml" hover="constant bits(5) M32_Svc = '10011'">M32_Svc</a>, <a link="M32_Abort" file="shared_pseudocode.xml" hover="constant bits(5) M32_Abort = '10111'">M32_Abort</a>, <a link="M32_Undef" file="shared_pseudocode.xml" hover="constant bits(5) M32_Undef = '11011'">M32_Undef</a>, <a link="M32_System" file="shared_pseudocode.xml" hover="constant bits(5) M32_System = '11111'">M32_System</a></line>
<line>            // If EL3 is implemented and using AArch32, then these modes are EL3 modes in Secure</line>
<line>            // state, and EL1 modes in Non-secure state. If EL3 is not implemented or is using</line>
<line>            // AArch64, then these modes are EL1 modes.</line>
<line>            // Therefore it is sufficient to test this implementation supports EL1 using AArch32.</line>
<line>            valid = <a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line>        when <a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a></line>
<line>            valid = <a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>);</line>
<line>        otherwise</line>
<line>            valid = FALSE;           // Passed an illegal mode value</line>
<line>    return !valid;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/system/BankedRegisterAccessValid" mylink="aarch32.functions.system.BankedRegisterAccessValid" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BankedRegisterAccessValid()</line>
<line>// ===========================</line>
<line>// Checks for MRS (Banked register) or MSR (Banked register) accesses to registers</line>
<line>// other than the SPSRs that are invalid. This includes ELR_hyp accesses.</line>
<line></line>
<line link="impl-aarch32.BankedRegisterAccessValid.2" hover="function: BankedRegisterAccessValid(bits(5) SYSm, bits(5) mode)" conts="BankedRegisterAccessValid"><anchor link="impl-aarch32.BankedRegisterAccessValid.2" hover="function: BankedRegisterAccessValid(bits(5) SYSm, bits(5) mode)">BankedRegisterAccessValid</anchor>(bits(5) SYSm, bits(5) mode)</line>
<line></line>
<line>    case SYSm of</line>
<line>        when '000xx', '00100'                          // R8_usr to R12_usr</line>
<line>            if mode != <a link="M32_FIQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_FIQ = '10001'">M32_FIQ</a> then UNPREDICTABLE;</line>
<line>        when '00101'                                   // SP_usr</line>
<line>            if mode == <a link="M32_System" file="shared_pseudocode.xml" hover="constant bits(5) M32_System = '11111'">M32_System</a> then UNPREDICTABLE;</line>
<line>        when '00110'                                   // LR_usr</line>
<line>            if mode IN {<a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a>,<a link="M32_System" file="shared_pseudocode.xml" hover="constant bits(5) M32_System = '11111'">M32_System</a>} then UNPREDICTABLE;</line>
<line>        when '010xx', '0110x', '01110'                 // R8_fiq to R12_fiq, SP_fiq, LR_fiq</line>
<line>            if mode == <a link="M32_FIQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_FIQ = '10001'">M32_FIQ</a> then UNPREDICTABLE;</line>
<line>        when '1000x'                                   // LR_irq, SP_irq</line>
<line>            if mode == <a link="M32_IRQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_IRQ = '10010'">M32_IRQ</a> then UNPREDICTABLE;</line>
<line>        when '1001x'                                   // LR_svc, SP_svc</line>
<line>            if mode == <a link="M32_Svc" file="shared_pseudocode.xml" hover="constant bits(5) M32_Svc = '10011'">M32_Svc</a> then UNPREDICTABLE;</line>
<line>        when '1010x'                                   // LR_abt, SP_abt</line>
<line>            if mode == <a link="M32_Abort" file="shared_pseudocode.xml" hover="constant bits(5) M32_Abort = '10111'">M32_Abort</a> then UNPREDICTABLE;</line>
<line>        when '1011x'                                   // LR_und, SP_und</line>
<line>            if mode == <a link="M32_Undef" file="shared_pseudocode.xml" hover="constant bits(5) M32_Undef = '11011'">M32_Undef</a> then UNPREDICTABLE;</line>
<line>        when '1110x'                                   // LR_mon, SP_mon</line>
<line>            if (!<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) || <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() != <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> ||</line>
<line>                mode == <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a>) then UNPREDICTABLE;</line>
<line>        when '11110'                                   // ELR_hyp, only from Monitor or Hyp mode</line>
<line>            if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) || !(mode IN {<a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a>,<a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a>}) then UNPREDICTABLE;</line>
<line>        when '11111'                                   // SP_hyp, only from Monitor mode</line>
<line>            if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) || mode != <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a> then UNPREDICTABLE;</line>
<line>        otherwise</line>
<line>            UNPREDICTABLE;</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/system/CPSRWriteByInstr" mylink="aarch32.functions.system.CPSRWriteByInstr" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CPSRWriteByInstr()</line>
<line>// ==================</line>
<line>// Update PSTATE.&lt;N,Z,C,V,Q,GE,E,A,I,F,M&gt; from a CPSR value written by an MSR instruction.</line>
<line></line>
<line link="impl-aarch32.CPSRWriteByInstr.2" hover="function: CPSRWriteByInstr(bits(32) value, bits(4) bytemask)" conts="CPSRWriteByInstr"><anchor link="impl-aarch32.CPSRWriteByInstr.2" hover="function: CPSRWriteByInstr(bits(32) value, bits(4) bytemask)">CPSRWriteByInstr</anchor>(bits(32) value, bits(4) bytemask)</line>
<line>    privileged = PSTATE.EL != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;              // PSTATE.&lt;A,I,F,M&gt; are not writable at EL0</line>
<line></line>
<line>    // Write PSTATE from 'value', ignoring bytes masked by 'bytemask'</line>
<line>    if bytemask&lt;3&gt; == '1' then</line>
<line>        PSTATE.&lt;N,Z,C,V,Q&gt; = value&lt;31:27&gt;;</line>
<line>        // Bits &lt;26:24&gt; are ignored</line>
<line></line>
<line>    if bytemask&lt;2&gt; == '1' then</line>
<line>        if <a link="impl-shared.HaveSSBSExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveSSBSExt()">HaveSSBSExt</a>() then</line>
<line>            PSTATE.SSBS = value&lt;23&gt;;</line>
<line>        if privileged then</line>
<line>            PSTATE.PAN = value&lt;22&gt;;</line>
<line>        if <a link="impl-shared.HaveDITExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDITExt()">HaveDITExt</a>() then</line>
<line>            PSTATE.DIT = value&lt;21&gt;;</line>
<line>        // Bit &lt;20&gt; is RES0</line>
<line>        PSTATE.GE = value&lt;19:16&gt;;</line>
<line></line>
<line>    if bytemask&lt;1&gt; == '1' then</line>
<line>        // Bits &lt;15:10&gt; are RES0</line>
<line>        PSTATE.E = value&lt;9&gt;;                    // PSTATE.E is writable at EL0</line>
<line>        if privileged then</line>
<line>            PSTATE.A = value&lt;8&gt;;</line>
<line></line>
<line>    if bytemask&lt;0&gt; == '1' then</line>
<line>        if privileged then</line>
<line>            PSTATE.&lt;I,F&gt; = value&lt;7:6&gt;;</line>
<line>            // Bit &lt;5&gt; is RES0</line>
<line>            // AArch32.WriteModeByInstr() sets PSTATE.IL to 1 if this is an illegal mode change.</line>
<line>            <a link="AArch32.WriteModeByInstr.1" file="shared_pseudocode.xml" hover="function: AArch32.WriteModeByInstr(bits(5) mode)">AArch32.WriteModeByInstr</a>(value&lt;4:0&gt;);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/system/ConditionPassed" mylink="aarch32.functions.system.ConditionPassed" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ConditionPassed()</line>
<line>// =================</line>
<line></line>
<line link="impl-aarch32.ConditionPassed.0" hover="function: boolean ConditionPassed()" conts="ConditionPassed">boolean <anchor link="impl-aarch32.ConditionPassed.0" hover="function: boolean ConditionPassed()">ConditionPassed</anchor>()</line>
<line>    return <a link="impl-shared.ConditionHolds.1" file="shared_pseudocode.xml" hover="function: boolean ConditionHolds(bits(4) cond)">ConditionHolds</a>(<a link="AArch32.CurrentCond.0" file="shared_pseudocode.xml" hover="function: bits(4) AArch32.CurrentCond()">AArch32.CurrentCond</a>());</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/system/CurrentCond" mylink="aarch32.functions.system.CurrentCond" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CurrentCond()</line>
<line>// =============</line>
<line></line>
<line link="AArch32.CurrentCond.0" hover="function: bits(4) AArch32.CurrentCond()" conts="AArch32.CurrentCond">bits(4) <anchor link="AArch32.CurrentCond.0" hover="function: bits(4) AArch32.CurrentCond()">AArch32.CurrentCond</anchor>();</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/system/InITBlock" mylink="aarch32.functions.system.InITBlock" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// InITBlock()</line>
<line>// ===========</line>
<line></line>
<line link="impl-aarch32.InITBlock.0" hover="function: boolean InITBlock()" conts="InITBlock">boolean <anchor link="impl-aarch32.InITBlock.0" hover="function: boolean InITBlock()">InITBlock</anchor>()</line>
<line>    if <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_T32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_T32</a> then</line>
<line>        return PSTATE.IT&lt;3:0&gt; != '0000';</line>
<line>    else</line>
<line>        return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/system/LastInITBlock" mylink="aarch32.functions.system.LastInITBlock" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// LastInITBlock()</line>
<line>// ===============</line>
<line></line>
<line link="impl-aarch32.LastInITBlock.0" hover="function: boolean LastInITBlock()" conts="LastInITBlock">boolean <anchor link="impl-aarch32.LastInITBlock.0" hover="function: boolean LastInITBlock()">LastInITBlock</anchor>()</line>
<line>    return (PSTATE.IT&lt;3:0&gt; == '1000');</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/system/SPSRWriteByInstr" mylink="aarch32.functions.system.SPSRWriteByInstr" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPSRWriteByInstr()</line>
<line>// ==================</line>
<line></line>
<line link="impl-aarch32.SPSRWriteByInstr.2" hover="function: SPSRWriteByInstr(bits(32) value, bits(4) bytemask)" conts="SPSRWriteByInstr"><anchor link="impl-aarch32.SPSRWriteByInstr.2" hover="function: SPSRWriteByInstr(bits(32) value, bits(4) bytemask)">SPSRWriteByInstr</anchor>(bits(32) value, bits(4) bytemask)</line>
<line></line>
<line>    bits(32) new_spsr = <a link="impl-shared.SPSR.read.0" file="shared_pseudocode.xml" hover="accessor: bits(N) SPSR[]">SPSR</a>[];</line>
<line></line>
<line>    if bytemask&lt;3&gt; == '1' then</line>
<line>        new_spsr&lt;31:24&gt; = value&lt;31:24&gt;;  // N,Z,C,V,Q flags, IT[1:0],J bits</line>
<line></line>
<line>    if bytemask&lt;2&gt; == '1' then</line>
<line>        new_spsr&lt;23:16&gt; = value&lt;23:16&gt;;  // IL bit, GE[3:0] flags</line>
<line></line>
<line>    if bytemask&lt;1&gt; == '1' then</line>
<line>        new_spsr&lt;15:8&gt; = value&lt;15:8&gt;;    // IT[7:2] bits, E bit, A interrupt mask</line>
<line></line>
<line>    if bytemask&lt;0&gt; == '1' then</line>
<line>        new_spsr&lt;7:0&gt; = value&lt;7:0&gt;;      // I,F interrupt masks, T bit, Mode bits</line>
<line></line>
<line>    <a link="impl-shared.SPSR.write.0" file="shared_pseudocode.xml" hover="accessor: SPSR[] = bits(N) value">SPSR</a>[] = new_spsr;                   // UNPREDICTABLE if User or System mode</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/system/SPSRaccessValid" mylink="aarch32.functions.system.SPSRaccessValid" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPSRaccessValid()</line>
<line>// =================</line>
<line>// Checks for MRS (Banked register) or MSR (Banked register) accesses to the SPSRs</line>
<line>// that are UNPREDICTABLE</line>
<line></line>
<line link="impl-aarch32.SPSRaccessValid.2" hover="function: SPSRaccessValid(bits(5) SYSm, bits(5) mode)" conts="SPSRaccessValid"><anchor link="impl-aarch32.SPSRaccessValid.2" hover="function: SPSRaccessValid(bits(5) SYSm, bits(5) mode)">SPSRaccessValid</anchor>(bits(5) SYSm, bits(5) mode)</line>
<line>    case SYSm of</line>
<line>        when '01110'                                                   // SPSR_fiq</line>
<line>            if mode == <a link="M32_FIQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_FIQ = '10001'">M32_FIQ</a>   then UNPREDICTABLE;</line>
<line>        when '10000'                                                   // SPSR_irq</line>
<line>            if mode == <a link="M32_IRQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_IRQ = '10010'">M32_IRQ</a>   then UNPREDICTABLE;</line>
<line>        when '10010'                                                   // SPSR_svc</line>
<line>            if mode == <a link="M32_Svc" file="shared_pseudocode.xml" hover="constant bits(5) M32_Svc = '10011'">M32_Svc</a>   then UNPREDICTABLE;</line>
<line>        when '10100'                                                   // SPSR_abt</line>
<line>            if mode == <a link="M32_Abort" file="shared_pseudocode.xml" hover="constant bits(5) M32_Abort = '10111'">M32_Abort</a> then UNPREDICTABLE;</line>
<line>        when '10110'                                                   // SPSR_und</line>
<line>            if mode == <a link="M32_Undef" file="shared_pseudocode.xml" hover="constant bits(5) M32_Undef = '11011'">M32_Undef</a> then UNPREDICTABLE;</line>
<line>        when '11100'                                                   // SPSR_mon</line>
<line>            if (!<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) || mode == <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a> ||</line>
<line>                <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() != <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>) then UNPREDICTABLE;</line>
<line>        when '11110'                                                   // SPSR_hyp</line>
<line>            if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) || mode != <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a> then UNPREDICTABLE;</line>
<line>        otherwise</line>
<line>            UNPREDICTABLE;</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/system/SelectInstrSet" mylink="aarch32.functions.system.SelectInstrSet" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SelectInstrSet()</line>
<line>// ================</line>
<line></line>
<line link="impl-aarch32.SelectInstrSet.1" hover="function: SelectInstrSet(InstrSet iset)" conts="SelectInstrSet"><anchor link="impl-aarch32.SelectInstrSet.1" hover="function: SelectInstrSet(InstrSet iset)">SelectInstrSet</anchor>(<a link="InstrSet" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet</a> iset)</line>
<line>    assert <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() IN {<a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>, <a link="InstrSet_T32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_T32</a>};</line>
<line>    assert iset IN {<a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>, <a link="InstrSet_T32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_T32</a>};</line>
<line></line>
<line>    PSTATE.T = if iset == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then '0' else '1';</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/tlbi/AArch32.DTLBI_ALL" mylink="aarch32.functions.tlbi.AArch32.DTLBI_ALL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.DTLBI_ALL()</line>
<line>// ===================</line>
<line>// Invalidate all data TLB entries for the indicated translation regime with the</line>
<line>// the indicated security state for all TLBs within the indicated shareability domain.</line>
<line>// Invalidation applies to all applicable stage 1 and stage 2 entries.</line>
<line></line>
<line link="AArch32.DTLBI_ALL.4" hover="function: AArch32.DTLBI_ALL(SecurityState security, Regime regime, Shareability shareability, TLBIMemAttr attr)" conts="AArch32.DTLBI_ALL"><anchor link="AArch32.DTLBI_ALL.4" hover="function: AArch32.DTLBI_ALL(SecurityState security, Regime regime, Shareability shareability, TLBIMemAttr attr)">AArch32.DTLBI_ALL</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability,</line>
<line>                  <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_DALL" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_DALL</a>;</line>
<line>    r.from_aarch64 = FALSE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.level        = <a link="TLBILevel_Any" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel_Any</a>;</line>
<line>    r.attr         = attr;</line>
<line></line>
<line>    TLBI(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then Broadcast(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/tlbi/AArch32.DTLBI_ASID" mylink="aarch32.functions.tlbi.AArch32.DTLBI_ASID" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.DTLBI_ASID()</line>
<line>// ====================</line>
<line>// Invalidate all data TLB stage 1 entries matching the indicated VMID (where regime supports)</line>
<line>// and ASID in the parameter Rt in the indicated translation regime with the</line>
<line>// indicated security state for all TLBs within the indicated shareability domain.</line>
<line>// Note: stage 1 and stage 2 combined entries are in the scope of this operation.</line>
<line></line>
<line link="AArch32.DTLBI_ASID.6" hover="function: AArch32.DTLBI_ASID(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBIMemAttr attr, bits(32) Rt)" conts="AArch32.DTLBI_ASID"><anchor link="AArch32.DTLBI_ASID.6" hover="function: AArch32.DTLBI_ASID(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBIMemAttr attr, bits(32) Rt)">AArch32.DTLBI_ASID</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                   <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr, bits(32) Rt)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_DASID" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_DASID</a>;</line>
<line>    r.from_aarch64 = FALSE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.level        = <a link="TLBILevel_Any" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel_Any</a>;</line>
<line>    r.attr         = attr;</line>
<line>    r.asid         = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8) : Rt&lt;7:0&gt;;</line>
<line></line>
<line>    TLBI(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then Broadcast(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/tlbi/AArch32.DTLBI_VA" mylink="aarch32.functions.tlbi.AArch32.DTLBI_VA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.DTLBI_VA()</line>
<line>// ==================</line>
<line>// Invalidate by VA all stage 1 data TLB entries in the indicated shareability domain</line>
<line>// matching the indicated VMID and ASID (where regime supports VMID, ASID) in the indicated regime</line>
<line>// with the indicated security state.</line>
<line>// ASID, VA and related parameters are derived from Rt.</line>
<line>// Note: stage 1 and stage 2 combined entries are in the scope of this operation.</line>
<line></line>
<line link="AArch32.DTLBI_VA.7" hover="function: AArch32.DTLBI_VA(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level,  TLBIMemAttr attr, bits(32) Rt)" conts="AArch32.DTLBI_VA"><anchor link="AArch32.DTLBI_VA.7" hover="function: AArch32.DTLBI_VA(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level,  TLBIMemAttr attr, bits(32) Rt)">AArch32.DTLBI_VA</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                 <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBILevel" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel</a> level,  <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr, bits(32) Rt)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_DVA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_DVA</a>;</line>
<line>    r.from_aarch64 = FALSE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.level        = level;</line>
<line>    r.attr         = attr;</line>
<line>    r.asid         = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8) : Rt&lt;7:0&gt;;</line>
<line>    r.address      = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32) : Rt&lt;31:12&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12);</line>
<line></line>
<line>    TLBI(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then Broadcast(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/tlbi/AArch32.ITLBI_ALL" mylink="aarch32.functions.tlbi.AArch32.ITLBI_ALL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.ITLBI_ALL()</line>
<line>// ===================</line>
<line>// Invalidate all instruction TLB entries for the indicated translation regime with the</line>
<line>// the indicated security state for all TLBs within the indicated shareability domain.</line>
<line>// Invalidation applies to all applicable stage 1 and stage 2 entries.</line>
<line></line>
<line link="AArch32.ITLBI_ALL.4" hover="function: AArch32.ITLBI_ALL(SecurityState security, Regime regime, Shareability shareability, TLBIMemAttr attr)" conts="AArch32.ITLBI_ALL"><anchor link="AArch32.ITLBI_ALL.4" hover="function: AArch32.ITLBI_ALL(SecurityState security, Regime regime, Shareability shareability, TLBIMemAttr attr)">AArch32.ITLBI_ALL</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability,</line>
<line>                  <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_IALL" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_IALL</a>;</line>
<line>    r.from_aarch64 = FALSE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.level        = <a link="TLBILevel_Any" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel_Any</a>;</line>
<line>    r.attr         = attr;</line>
<line></line>
<line>    TLBI(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then Broadcast(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/tlbi/AArch32.ITLBI_ASID" mylink="aarch32.functions.tlbi.AArch32.ITLBI_ASID" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.ITLBI_ASID()</line>
<line>// ====================</line>
<line>// Invalidate all instruction TLB stage 1 entries matching the indicated VMID</line>
<line>// (where regime supports) and ASID in the parameter Rt in the indicated translation</line>
<line>// regime with the indicated security state for all TLBs within the indicated shareability domain.</line>
<line>// Note: stage 1 and stage 2 combined entries are in the scope of this operation.</line>
<line></line>
<line link="AArch32.ITLBI_ASID.6" hover="function: AArch32.ITLBI_ASID(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBIMemAttr attr, bits(32) Rt)" conts="AArch32.ITLBI_ASID"><anchor link="AArch32.ITLBI_ASID.6" hover="function: AArch32.ITLBI_ASID(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBIMemAttr attr, bits(32) Rt)">AArch32.ITLBI_ASID</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                   <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr, bits(32) Rt)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_IASID" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_IASID</a>;</line>
<line>    r.from_aarch64 = FALSE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.level        = <a link="TLBILevel_Any" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel_Any</a>;</line>
<line>    r.attr         = attr;</line>
<line>    r.asid         = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8) : Rt&lt;7:0&gt;;</line>
<line></line>
<line>    TLBI(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then Broadcast(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/tlbi/AArch32.ITLBI_VA" mylink="aarch32.functions.tlbi.AArch32.ITLBI_VA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.ITLBI_VA()</line>
<line>// ==================</line>
<line>// Invalidate by VA all stage 1 instruction TLB entries in the indicated shareability domain</line>
<line>// matching the indicated VMID and ASID (where regime supports VMID, ASID) in the indicated regime</line>
<line>// with the indicated security state.</line>
<line>// ASID, VA and related parameters are derived from Rt.</line>
<line>// Note: stage 1 and stage 2 combined entries are in the scope of this operation.</line>
<line></line>
<line link="AArch32.ITLBI_VA.7" hover="function: AArch32.ITLBI_VA(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level,  TLBIMemAttr attr, bits(32) Rt)" conts="AArch32.ITLBI_VA"><anchor link="AArch32.ITLBI_VA.7" hover="function: AArch32.ITLBI_VA(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level,  TLBIMemAttr attr, bits(32) Rt)">AArch32.ITLBI_VA</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                 <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBILevel" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel</a> level,  <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr, bits(32) Rt)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_IVA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_IVA</a>;</line>
<line>    r.from_aarch64 = FALSE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.level        = level;</line>
<line>    r.attr         = attr;</line>
<line>    r.asid         = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8) : Rt&lt;7:0&gt;;</line>
<line>    r.address      = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32) : Rt&lt;31:12&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12);</line>
<line></line>
<line>    TLBI(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then Broadcast(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/tlbi/AArch32.TLBI_ALL" mylink="aarch32.functions.tlbi.AArch32.TLBI_ALL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TLBI_ALL()</line>
<line>// ==================</line>
<line>// Invalidate all entries for the indicated translation regime with the</line>
<line>// the indicated security state for all TLBs within the indicated shareability domain.</line>
<line>// Invalidation applies to all applicable stage 1 and stage 2 entries.</line>
<line></line>
<line link="AArch32.TLBI_ALL.4" hover="function: AArch32.TLBI_ALL(SecurityState security, Regime regime, Shareability shareability, TLBIMemAttr attr)" conts="AArch32.TLBI_ALL"><anchor link="AArch32.TLBI_ALL.4" hover="function: AArch32.TLBI_ALL(SecurityState security, Regime regime, Shareability shareability, TLBIMemAttr attr)">AArch32.TLBI_ALL</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_ALL" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_ALL</a>;</line>
<line>    r.from_aarch64 = FALSE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.level        = <a link="TLBILevel_Any" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel_Any</a>;</line>
<line>    r.attr         = attr;</line>
<line></line>
<line>    TLBI(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then Broadcast(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/tlbi/AArch32.TLBI_ASID" mylink="aarch32.functions.tlbi.AArch32.TLBI_ASID" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TLBI_ASID()</line>
<line>// ===================</line>
<line>// Invalidate all stage 1 entries matching the indicated VMID (where regime supports)</line>
<line>// and ASID in the parameter Rt in the indicated translation regime with the</line>
<line>// indicated security state for all TLBs within the indicated shareability domain.</line>
<line>// Note: stage 1 and stage 2 combined entries are in the scope of this operation.</line>
<line></line>
<line link="AArch32.TLBI_ASID.6" hover="function: AArch32.TLBI_ASID(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBIMemAttr attr, bits(32) Rt)" conts="AArch32.TLBI_ASID"><anchor link="AArch32.TLBI_ASID.6" hover="function: AArch32.TLBI_ASID(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBIMemAttr attr, bits(32) Rt)">AArch32.TLBI_ASID</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                  <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr, bits(32) Rt)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_ASID" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_ASID</a>;</line>
<line>    r.from_aarch64 = FALSE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.level        = <a link="TLBILevel_Any" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel_Any</a>;</line>
<line>    r.attr         = attr;</line>
<line>    r.asid         = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8) : Rt&lt;7:0&gt;;</line>
<line></line>
<line>    TLBI(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then Broadcast(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/tlbi/AArch32.TLBI_IPAS2" mylink="aarch32.functions.tlbi.AArch32.TLBI_IPAS2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TLBI_IPAS2()</line>
<line>// ====================</line>
<line>// Invalidate by IPA all stage 2 only TLB entries in the indicated shareability</line>
<line>// domain matching the indicated VMID in the indicated regime with the indicated security state.</line>
<line>// Note: stage 1 and stage 2 combined entries are not in the scope of this operation.</line>
<line>// IPA and related parameters of the are derived from Rt.</line>
<line></line>
<line link="AArch32.TLBI_IPAS2.7" hover="function: AArch32.TLBI_IPAS2(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr, bits(32) Rt)" conts="AArch32.TLBI_IPAS2"><anchor link="AArch32.TLBI_IPAS2.7" hover="function: AArch32.TLBI_IPAS2(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr, bits(32) Rt)">AArch32.TLBI_IPAS2</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                   <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBILevel" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel</a> level, <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr, bits(32) Rt)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>};</line>
<line>    assert security == <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a>;</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_IPAS2" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_IPAS2</a>;</line>
<line>    r.from_aarch64 = FALSE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.level        = level;</line>
<line>    r.attr         = attr;</line>
<line>    r.address      = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(24) : Rt&lt;27:0&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12);</line>
<line>    r.ipaspace     = <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line></line>
<line>    TLBI(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then Broadcast(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/tlbi/AArch32.TLBI_VA" mylink="aarch32.functions.tlbi.AArch32.TLBI_VA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TLBI_VA()</line>
<line>// =================</line>
<line>// Invalidate by VA all stage 1 TLB entries in the indicated shareability domain</line>
<line>// matching the indicated VMID and ASID (where regime supports VMID, ASID) in the indicated regime</line>
<line>// with the indicated security state.</line>
<line>// ASID, VA and related parameters are derived from Rt.</line>
<line>// Note: stage 1 and stage 2 combined entries are in the scope of this operation.</line>
<line></line>
<line link="AArch32.TLBI_VA.7" hover="function: AArch32.TLBI_VA(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level,  TLBIMemAttr attr, bits(32) Rt)" conts="AArch32.TLBI_VA"><anchor link="AArch32.TLBI_VA.7" hover="function: AArch32.TLBI_VA(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level,  TLBIMemAttr attr, bits(32) Rt)">AArch32.TLBI_VA</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBILevel" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel</a> level,  <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr, bits(32) Rt)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_VA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_VA</a>;</line>
<line>    r.from_aarch64 = FALSE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.level        = level;</line>
<line>    r.attr         = attr;</line>
<line>    r.asid         = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8) : Rt&lt;7:0&gt;;</line>
<line>    r.address      = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32) : Rt&lt;31:12&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12);</line>
<line></line>
<line>    TLBI(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then Broadcast(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/tlbi/AArch32.TLBI_VAA" mylink="aarch32.functions.tlbi.AArch32.TLBI_VAA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TLBI_VAA()</line>
<line>// ==================</line>
<line>// Invalidate by VA all stage 1 TLB entries in the indicated shareability domain</line>
<line>// matching the indicated VMID (where regime supports VMID) and all ASID in the indicated regime</line>
<line>// with the indicated security state.</line>
<line>// VA and related parameters are derived from Rt.</line>
<line>// Note: stage 1 and stage 2 combined entries are in the scope of this operation.</line>
<line></line>
<line link="AArch32.TLBI_VAA.7" hover="function: AArch32.TLBI_VAA(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr,  bits(32) Rt)" conts="AArch32.TLBI_VAA"><anchor link="AArch32.TLBI_VAA.7" hover="function: AArch32.TLBI_VAA(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr,  bits(32) Rt)">AArch32.TLBI_VAA</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                 <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBILevel" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel</a> level, <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr,  bits(32) Rt)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_VAA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_VAA</a>;</line>
<line>    r.from_aarch64 = FALSE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.level        = level;</line>
<line>    r.attr         = attr;</line>
<line>    r.address      = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32) : Rt&lt;31:12&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12);</line>
<line></line>
<line>    TLBI(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then Broadcast(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/tlbi/AArch32.TLBI_VMALL" mylink="aarch32.functions.tlbi.AArch32.TLBI_VMALL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TLBI_VMALL()</line>
<line>// ====================</line>
<line>// Invalidate all stage 1 entries for the indicated translation regime with the</line>
<line>// the indicated security state for all TLBs within the indicated shareability</line>
<line>// domain that match the indicated VMID (where applicable).</line>
<line>// Note: stage 1 and stage 2 combined entries are in the scope of this operation.</line>
<line>// Note: stage 2 only entries are not in the scope of this operation.</line>
<line></line>
<line link="AArch32.TLBI_VMALL.5" hover="function: AArch32.TLBI_VMALL(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBIMemAttr attr)" conts="AArch32.TLBI_VMALL"><anchor link="AArch32.TLBI_VMALL.5" hover="function: AArch32.TLBI_VMALL(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBIMemAttr attr)">AArch32.TLBI_VMALL</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                   <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_VMALL" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_VMALL</a>;</line>
<line>    r.from_aarch64 = FALSE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.level        = <a link="TLBILevel_Any" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel_Any</a>;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.attr         = attr;</line>
<line></line>
<line>    TLBI(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then Broadcast(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/tlbi/AArch32.TLBI_VMALLS12" mylink="aarch32.functions.tlbi.AArch32.TLBI_VMALLS12" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TLBI_VMALLS12()</line>
<line>// =======================</line>
<line>// Invalidate all stage 1 and stage 2 entries for the indicated translation</line>
<line>// regime with the indicated security state for all TLBs within the indicated</line>
<line>// shareability domain that match the indicated VMID.</line>
<line></line>
<line link="AArch32.TLBI_VMALLS12.5" hover="function: AArch32.TLBI_VMALLS12(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBIMemAttr attr)" conts="AArch32.TLBI_VMALLS12"><anchor link="AArch32.TLBI_VMALLS12.5" hover="function: AArch32.TLBI_VMALLS12(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBIMemAttr attr)">AArch32.TLBI_VMALLS12</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                      <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_VMALLS12" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_VMALLS12</a>;</line>
<line>    r.from_aarch64 = FALSE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.level        = <a link="TLBILevel_Any" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel_Any</a>;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.attr         = attr;</line>
<line></line>
<line>    TLBI(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then Broadcast(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/v6simd/Sat" mylink="aarch32.functions.v6simd.Sat" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Sat()</line>
<line>// =====</line>
<line></line>
<line link="impl-aarch32.Sat.3" hover="function: bits(N) Sat(integer i, integer N, boolean unsigned)" conts="Sat">bits(N) <anchor link="impl-aarch32.Sat.3" hover="function: bits(N) Sat(integer i, integer N, boolean unsigned)">Sat</anchor>(integer i, integer N, boolean unsigned)</line>
<line>    result = if unsigned then <a link="impl-aarch32.UnsignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) UnsignedSat(integer i, integer N)">UnsignedSat</a>(i, N) else <a link="impl-aarch32.SignedSat.2" file="shared_pseudocode.xml" hover="function: bits(N) SignedSat(integer i, integer N)">SignedSat</a>(i, N);</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/v6simd/SignedSat" mylink="aarch32.functions.v6simd.SignedSat" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SignedSat()</line>
<line>// ===========</line>
<line></line>
<line link="impl-aarch32.SignedSat.2" hover="function: bits(N) SignedSat(integer i, integer N)" conts="SignedSat">bits(N) <anchor link="impl-aarch32.SignedSat.2" hover="function: bits(N) SignedSat(integer i, integer N)">SignedSat</anchor>(integer i, integer N)</line>
<line>    (result, -) = <a link="impl-shared.SignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(i, N);</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch32/functions/v6simd/UnsignedSat" mylink="aarch32.functions.v6simd.UnsignedSat" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// UnsignedSat()</line>
<line>// =============</line>
<line></line>
<line link="impl-aarch32.UnsignedSat.2" hover="function: bits(N) UnsignedSat(integer i, integer N)" conts="UnsignedSat">bits(N) <anchor link="impl-aarch32.UnsignedSat.2" hover="function: bits(N) UnsignedSat(integer i, integer N)">UnsignedSat</anchor>(integer i, integer N)</line>
<line>    (result, -) = <a link="impl-shared.UnsignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(i, N);</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch32/ic/AArch32.IC" mylink="aarch32.ic.AArch32.IC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.IC()</line>
<line>// ============</line>
<line>// Perform Instruction Cache Operation.</line>
<line></line>
<line link="AArch32.IC.1" hover="function: AArch32.IC(CacheOpScope opscope)" conts="AArch32.IC"><anchor link="AArch32.IC.1" hover="function: AArch32.IC(CacheOpScope opscope)">AArch32.IC</anchor>(<a link="CacheOpScope" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope</a> opscope)</line>
<line>    regval = bits(32) UNKNOWN;</line>
<line>    <a link="AArch32.IC.2" file="shared_pseudocode.xml" hover="function: AArch32.IC(bits(32) regval, CacheOpScope opscope)">AArch32.IC</a>(regval, opscope);</line>
<line></line>
<line>// AArch32.IC()</line>
<line>// ============</line>
<line>// Perform Instruction Cache Operation.</line>
<line></line>
<line link="AArch32.IC.2" hover="function: AArch32.IC(bits(32) regval, CacheOpScope opscope)" conts="AArch32.IC"><anchor link="AArch32.IC.2" hover="function: AArch32.IC(bits(32) regval, CacheOpScope opscope)">AArch32.IC</anchor>(bits(32) regval, <a link="CacheOpScope" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope</a> opscope)</line>
<line>    <a link="CacheRecord" file="shared_pseudocode.xml" hover="type CacheRecord is ( AccessType acctype, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, bits(64) regval, FullAddress paddress, bits(64) vaddress, integer set, integer way, integer level, Shareability shareability, boolean translated, boolean is_vmid_valid, bits(16) vmid, boolean is_asid_valid, bits(16) asid, SecurityState security, CachePASpace cpas )">CacheRecord</a> cache;</line>
<line></line>
<line>    cache.acctype   = <a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a>;</line>
<line>    cache.cachetype = <a link="CacheType_Instruction" file="shared_pseudocode.xml" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }">CacheType_Instruction</a>;</line>
<line>    cache.cacheop   = <a link="CacheOp_Invalidate" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_Invalidate</a>;</line>
<line>    cache.opscope   = opscope;</line>
<line>    cache.security  = <a link="impl-shared.SecurityStateAtEL.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)">SecurityStateAtEL</a>(PSTATE.EL);</line>
<line></line>
<line>    if opscope IN {<a link="CacheOpScope_ALLU" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_ALLU</a>, <a link="CacheOpScope_ALLUIS" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_ALLUIS</a>} then</line>
<line>        if opscope == <a link="CacheOpScope_ALLUIS" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_ALLUIS</a> || (opscope == <a link="CacheOpScope_ALLU" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_ALLU</a> &amp;&amp; PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>                &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR.FB == '1') then</line>
<line>            cache.shareability = <a link="Shareability_ISH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_ISH</a>;</line>
<line>        else</line>
<line>            cache.shareability = <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a>;</line>
<line>        cache.regval = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(regval, 64);</line>
<line>        <a link="impl-shared.CACHE_OP.1" file="shared_pseudocode.xml" hover="function: CACHE_OP(CacheRecord cache)">CACHE_OP</a>(cache);</line>
<line>    else</line>
<line>        assert opscope == <a link="CacheOpScope_PoU" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_PoU</a>;</line>
<line></line>
<line>        if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>            if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} then</line>
<line>                cache.is_vmid_valid = TRUE;</line>
<line>                cache.vmid          = VMID[];</line>
<line>            else</line>
<line>                cache.is_vmid_valid = FALSE;</line>
<line>        else</line>
<line>            cache.is_vmid_valid = FALSE;</line>
<line></line>
<line>        if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>            cache.is_asid_valid = TRUE;</line>
<line>            cache.asid          = <a link="impl-shared.ASID.read.0" file="shared_pseudocode.xml" hover="accessor: bits(16) ASID[]">ASID</a>[];</line>
<line>        else</line>
<line>            cache.is_asid_valid = FALSE;</line>
<line></line>
<line>        need_translate = <a link="impl-shared.ICInstNeedsTranslation.1" file="shared_pseudocode.xml" hover="function: boolean ICInstNeedsTranslation(CacheOpScope opscope)">ICInstNeedsTranslation</a>(opscope);</line>
<line></line>
<line>        cache.shareability = <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a>;</line>
<line>        cache.vaddress     = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(regval, 64);</line>
<line>        cache.translated   = need_translate;</line>
<line></line>
<line>        if !need_translate then</line>
<line>            cache.paddress = <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> UNKNOWN;</line>
<line>            <a link="impl-shared.CACHE_OP.1" file="shared_pseudocode.xml" hover="function: CACHE_OP(CacheRecord cache)">CACHE_OP</a>(cache);</line>
<line>            return;</line>
<line></line>
<line>        integer size    = 0;</line>
<line>        boolean aligned = TRUE;</line>
<line>        <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescIC.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescIC(CacheRecord cache)">CreateAccDescIC</a>(cache);</line>
<line>        <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc = <a link="AArch32.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch32.TranslateAddress(bits(32) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch32.TranslateAddress</a>(regval, accdesc, aligned, size);</line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>            <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(regval, memaddrdesc.fault);</line>
<line></line>
<line>        cache.paddress = memaddrdesc.paddress;</line>
<line>        <a link="impl-shared.CACHE_OP.1" file="shared_pseudocode.xml" hover="function: CACHE_OP(CacheRecord cache)">CACHE_OP</a>(cache);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch32/predictionrestrict/AArch32.RestrictPrediction" mylink="aarch32.predictionrestrict.AArch32.RestrictPrediction" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.RestrictPrediction()</line>
<line>// ============================</line>
<line>// Clear all predictions in the context.</line>
<line></line>
<line link="AArch32.RestrictPrediction.2" hover="function: AArch32.RestrictPrediction(bits(32) val, RestrictType restriction)" conts="AArch32.RestrictPrediction"><anchor link="AArch32.RestrictPrediction.2" hover="function: AArch32.RestrictPrediction(bits(32) val, RestrictType restriction)">AArch32.RestrictPrediction</anchor>(bits(32) val, <a link="RestrictType" file="shared_pseudocode.xml" hover="enumeration RestrictType { RestrictType_DataValue, RestrictType_ControlFlow, RestrictType_CachePrefetch, RestrictType_Other }">RestrictType</a> restriction)</line>
<line></line>
<line>    <a link="ExecutionCntxt" file="shared_pseudocode.xml" hover="type ExecutionCntxt is ( boolean is_vmid_valid, boolean all_vmid, bits(16) vmid, boolean is_asid_valid, boolean all_asid, bits(16) asid, bits(2) target_el, SecurityState security, RestrictType restriction )">ExecutionCntxt</a> c;</line>
<line>    target_el    = val&lt;25:24&gt;;</line>
<line></line>
<line>    // If the target EL is not implemented or the instruction is executed at an</line>
<line>    // EL lower than the specified level, the instruction is treated as a NOP.</line>
<line>    if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(target_el) || <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(target_el) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL) then <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
<line></line>
<line>    bit ns  = val&lt;26&gt;;</line>
<line>    bit nse = bit UNKNOWN;</line>
<line>    ss = <a link="impl-shared.TargetSecurityState.2" file="shared_pseudocode.xml" hover="function: SecurityState TargetSecurityState(bit NS, bit NSE)">TargetSecurityState</a>(ns, nse);</line>
<line></line>
<line>    c.security  = ss;</line>
<line>    c.target_el = target_el;</line>
<line></line>
<line>    if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} then</line>
<line>            c.is_vmid_valid = TRUE;</line>
<line>            c.all_vmid      = FALSE;</line>
<line>            c.vmid          = VMID[];</line>
<line></line>
<line>        elsif target_el IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} then</line>
<line>            c.is_vmid_valid = TRUE;</line>
<line>            c.all_vmid      = val&lt;27&gt; == '1';</line>
<line>            c.vmid          = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(val&lt;23:16&gt;, 16);      // Only valid if  val&lt;27&gt; == '0';</line>
<line>        else</line>
<line>            c.is_vmid_valid = FALSE;</line>
<line>    else</line>
<line>        c.is_vmid_valid = FALSE;</line>
<line></line>
<line>    if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        c.is_asid_valid = TRUE;</line>
<line>        c.all_asid      = FALSE;</line>
<line>        c.asid          = <a link="impl-shared.ASID.read.0" file="shared_pseudocode.xml" hover="accessor: bits(16) ASID[]">ASID</a>[];</line>
<line></line>
<line>    elsif target_el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        c.is_asid_valid = TRUE;</line>
<line>        c.all_asid      = val&lt;8&gt; == '1';</line>
<line>        c.asid          = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(val&lt;7:0&gt;, 16);            // Only valid if  val&lt;8&gt; == '0';</line>
<line></line>
<line>    else</line>
<line>        c.is_asid_valid = FALSE;</line>
<line></line>
<line>    c.restriction = restriction;</line>
<line>    <a link="impl-shared.RESTRICT_PREDICTIONS.1" file="shared_pseudocode.xml" hover="function: RESTRICT_PREDICTIONS(ExecutionCntxt c)">RESTRICT_PREDICTIONS</a>(c);</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/attrs/AArch32.DefaultTEXDecode" mylink="aarch32.translation.attrs.AArch32.DefaultTEXDecode" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.DefaultTEXDecode()</line>
<line>// ==========================</line>
<line>// Apply short-descriptor format memory region attributes, without TEX remap</line>
<line></line>
<line link="AArch32.DefaultTEXDecode.4" hover="function: MemoryAttributes AArch32.DefaultTEXDecode(bits(3) TEX_in, bit C_in, bit B_in, bit s)" conts="AArch32.DefaultTEXDecode">MemoryAttributes <anchor link="AArch32.DefaultTEXDecode.4" hover="function: MemoryAttributes AArch32.DefaultTEXDecode(bits(3) TEX_in, bit C_in, bit B_in, bit s)">AArch32.DefaultTEXDecode</anchor>(bits(3) TEX_in, bit C_in, bit B_in, bit s)</line>
<line>    <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs;</line>
<line>    bits(3) TEX = TEX_in;</line>
<line>    bit C = C_in;</line>
<line>    bit B = B_in;</line>
<line></line>
<line>    // Reserved values map to allocated values</line>
<line>    if (TEX == '001' &amp;&amp; C:B == '01') || (TEX == '010' &amp;&amp; C:B != '00') || TEX == '011' then</line>
<line>        bits(5) texcb;</line>
<line>        (-, texcb) = <a link="impl-shared.ConstrainUnpredictableBits.2" file="shared_pseudocode.xml" hover="function: (Constraint,bits(width)) ConstrainUnpredictableBits(Unpredictable which, integer width)">ConstrainUnpredictableBits</a>(<a link="Unpredictable_RESTEXCB" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESTEXCB</a>, 5);</line>
<line>        TEX = texcb&lt;4:2&gt;;  C = texcb&lt;1&gt;;  B = texcb&lt;0&gt;;</line>
<line></line>
<line>    // Distinction between Inner Shareable and Outer Shareable is not supported in this format</line>
<line>    // A memory region is either Non-shareable or Outer Shareable</line>
<line>    case TEX:C:B of</line>
<line>        when '00000'</line>
<line>            // Device-nGnRnE</line>
<line>            memattrs.memtype      = <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a>;</line>
<line>            memattrs.device       = <a link="DeviceType_nGnRnE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGnRnE</a>;</line>
<line>            memattrs.shareability = <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a>;</line>
<line>        when '00001', '01000'</line>
<line>            // Device-nGnRE</line>
<line>            memattrs.memtype      = <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a>;</line>
<line>            memattrs.device       = <a link="DeviceType_nGnRE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGnRE</a>;</line>
<line>            memattrs.shareability = <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a>;</line>
<line>        when '00010'</line>
<line>            // Write-through Read allocate</line>
<line>            memattrs.memtype      = <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>;</line>
<line>            memattrs.inner.attrs  = <a link="MemAttr_WT" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WT = '10'">MemAttr_WT</a>;</line>
<line>            memattrs.inner.hints  = <a link="MemHint_RA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RA = '10'">MemHint_RA</a>;</line>
<line>            memattrs.outer.attrs  = <a link="MemAttr_WT" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WT = '10'">MemAttr_WT</a>;</line>
<line>            memattrs.outer.hints  = <a link="MemHint_RA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RA = '10'">MemHint_RA</a>;</line>
<line>            memattrs.shareability = if s == '1' then <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a> else <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a>;</line>
<line>        when '00011'</line>
<line>            // Write-back Read allocate</line>
<line>            memattrs.memtype      = <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>;</line>
<line>            memattrs.inner.attrs  = <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>;</line>
<line>            memattrs.inner.hints  = <a link="MemHint_RA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RA = '10'">MemHint_RA</a>;</line>
<line>            memattrs.outer.attrs  = <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>;</line>
<line>            memattrs.outer.hints  = <a link="MemHint_RA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RA = '10'">MemHint_RA</a>;</line>
<line>            memattrs.shareability = if s == '1' then <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a> else <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a>;</line>
<line>        when '00100'</line>
<line>            // Non-cacheable</line>
<line>            memattrs.memtype      = <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>;</line>
<line>            memattrs.inner.attrs  = <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a>;</line>
<line>            memattrs.outer.attrs  = <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a>;</line>
<line>            memattrs.shareability = <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a>;</line>
<line>        when '00110'</line>
<line>            memattrs = <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> IMPLEMENTATION_DEFINED;</line>
<line>        when '00111'</line>
<line>            // Write-back Read and Write allocate</line>
<line>            memattrs.memtype      = <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>;</line>
<line>            memattrs.inner.attrs  = <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>;</line>
<line>            memattrs.inner.hints  = <a link="MemHint_RWA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RWA = '11'">MemHint_RWA</a>;</line>
<line>            memattrs.outer.attrs  = <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>;</line>
<line>            memattrs.outer.hints  = <a link="MemHint_RWA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RWA = '11'">MemHint_RWA</a>;</line>
<line>            memattrs.shareability = if s == '1' then <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a> else <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a>;</line>
<line>        when '1xxxx'</line>
<line>            // Cacheable, TEX&lt;1:0&gt; = Outer attrs, {C,B} = Inner attrs</line>
<line>            memattrs.memtype = <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>;</line>
<line>            memattrs.inner   = <a link="impl-shared.DecodeSDFAttr.1" file="shared_pseudocode.xml" hover="function: MemAttrHints DecodeSDFAttr(bits(2) rgn)">DecodeSDFAttr</a>(C:B);</line>
<line>            memattrs.outer   = <a link="impl-shared.DecodeSDFAttr.1" file="shared_pseudocode.xml" hover="function: MemAttrHints DecodeSDFAttr(bits(2) rgn)">DecodeSDFAttr</a>(TEX&lt;1:0&gt;);</line>
<line></line>
<line>            if memattrs.inner.attrs == <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a> &amp;&amp; memattrs.outer.attrs == <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a> then</line>
<line>                memattrs.shareability = <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a>;</line>
<line>            else</line>
<line>                memattrs.shareability = if s == '1' then <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a> else <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a>;</line>
<line>        otherwise</line>
<line>            // Reserved, handled above</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    // The Transient hint is not supported in this format</line>
<line>    memattrs.inner.transient = FALSE;</line>
<line>    memattrs.outer.transient = FALSE;</line>
<line>    memattrs.tags            = <a link="MemTag_Untagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_Untagged</a>;</line>
<line></line>
<line>    if memattrs.inner.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a> &amp;&amp; memattrs.outer.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a> then</line>
<line>        memattrs.xs = '0';</line>
<line>    else</line>
<line>        memattrs.xs = '1';</line>
<line></line>
<line>    return memattrs;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/attrs/AArch32.MAIRAttr" mylink="aarch32.translation.attrs.AArch32.MAIRAttr" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.MAIRAttr()</line>
<line>// ==================</line>
<line>// Retrieve the memory attribute encoding indexed in the given MAIR</line>
<line></line>
<line>bits(8) AArch32.MAIRAttr(integer index, MAIRType mair)</line>
<line>    assert (index &lt; 8);</line>
<line>    bit_index = 8 * index;</line>
<line>    return mair&lt;bit_index+7:bit_index&gt;;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/attrs/AArch32.RemappedTEXDecode" mylink="aarch32.translation.attrs.AArch32.RemappedTEXDecode" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.RemappedTEXDecode()</line>
<line>// ===========================</line>
<line>// Apply short-descriptor format memory region attributes, with TEX remap</line>
<line></line>
<line link="AArch32.RemappedTEXDecode.5" hover="function: MemoryAttributes AArch32.RemappedTEXDecode(Regime regime, bits(3) TEX, bit C, bit B, bit s)" conts="AArch32.RemappedTEXDecode">MemoryAttributes <anchor link="AArch32.RemappedTEXDecode.5" hover="function: MemoryAttributes AArch32.RemappedTEXDecode(Regime regime, bits(3) TEX, bit C, bit B, bit s)">AArch32.RemappedTEXDecode</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(3) TEX, bit C, bit B, bit s)</line>
<line></line>
<line>    <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs;</line>
<line>    PRRR_Type prrr;</line>
<line>    NMRR_Type nmrr;</line>
<line></line>
<line>    region = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(TEX&lt;0&gt;:C:B);         // TEX&lt;2:1&gt; are ignored in this mapping scheme</line>
<line>    if region == 6 then</line>
<line>        return <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> IMPLEMENTATION_DEFINED;</line>
<line></line>
<line>    if regime == <a link="Regime_EL30" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL30</a> then</line>
<line>        prrr = PRRR_S;</line>
<line>        nmrr = NMRR_S;</line>
<line>    elsif <a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        prrr = PRRR_NS;</line>
<line>        nmrr = NMRR_NS;</line>
<line>    else</line>
<line>        prrr = PRRR;</line>
<line>        nmrr = NMRR;</line>
<line></line>
<line>    base = 2 * region;</line>
<line>    attrfield = prrr&lt;base+1:base&gt;;</line>
<line></line>
<line>    if attrfield == '11' then      // Reserved, maps to allocated value</line>
<line>        (-, attrfield) = <a link="impl-shared.ConstrainUnpredictableBits.2" file="shared_pseudocode.xml" hover="function: (Constraint,bits(width)) ConstrainUnpredictableBits(Unpredictable which, integer width)">ConstrainUnpredictableBits</a>(<a link="Unpredictable_RESPRRR" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESPRRR</a>, 2);</line>
<line></line>
<line>    case attrfield of</line>
<line>        when '00'                  // Device-nGnRnE</line>
<line>            memattrs.memtype      = <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a>;</line>
<line>            memattrs.device       = <a link="DeviceType_nGnRnE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGnRnE</a>;</line>
<line>            memattrs.shareability = <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a>;</line>
<line>        when '01'                  // Device-nGnRE</line>
<line>            memattrs.memtype      = <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a>;</line>
<line>            memattrs.device       = <a link="DeviceType_nGnRE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGnRE</a>;</line>
<line>            memattrs.shareability = <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a>;</line>
<line>        when '10'</line>
<line>            NSn  = if s == '0' then prrr.NS0 else prrr.NS1;</line>
<line>            NOSm = prrr&lt;region+24&gt; AND NSn;</line>
<line>            IRn  = nmrr&lt;base+1:base&gt;;</line>
<line>            ORn  = nmrr&lt;base+17:base+16&gt;;</line>
<line></line>
<line>            memattrs.memtype = <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>;</line>
<line>            memattrs.inner   = <a link="impl-shared.DecodeSDFAttr.1" file="shared_pseudocode.xml" hover="function: MemAttrHints DecodeSDFAttr(bits(2) rgn)">DecodeSDFAttr</a>(IRn);</line>
<line>            memattrs.outer   = <a link="impl-shared.DecodeSDFAttr.1" file="shared_pseudocode.xml" hover="function: MemAttrHints DecodeSDFAttr(bits(2) rgn)">DecodeSDFAttr</a>(ORn);</line>
<line>            if memattrs.inner.attrs == <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a> &amp;&amp; memattrs.outer.attrs == <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a> then</line>
<line>                memattrs.shareability = <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a>;</line>
<line>            else</line>
<line>                bits(2) sh = NSn:NOSm;</line>
<line>                memattrs.shareability = <a link="impl-shared.DecodeShareability.1" file="shared_pseudocode.xml" hover="function: Shareability DecodeShareability(bits(2) sh)">DecodeShareability</a>(sh);</line>
<line>        when '11'</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    // The Transient hint is not supported in this format</line>
<line>    memattrs.inner.transient = FALSE;</line>
<line>    memattrs.outer.transient = FALSE;</line>
<line>    memattrs.tags            = <a link="MemTag_Untagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_Untagged</a>;</line>
<line></line>
<line>    if memattrs.inner.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a> &amp;&amp; memattrs.outer.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a> then</line>
<line>        memattrs.xs = '0';</line>
<line>    else</line>
<line>        memattrs.xs = '1';</line>
<line></line>
<line>    return memattrs;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/debug/AArch32.CheckBreakpoint" mylink="aarch32.translation.debug.AArch32.CheckBreakpoint" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.CheckBreakpoint()</line>
<line>// =========================</line>
<line>// Called before executing the instruction of length "size" bytes at "vaddress" in an AArch32</line>
<line>// translation regime, when either debug exceptions are enabled, or halting debug is enabled</line>
<line>// and halting is allowed.</line>
<line></line>
<line link="AArch32.CheckBreakpoint.4" hover="function: FaultRecord AArch32.CheckBreakpoint(FaultRecord fault_in, bits(32) vaddress, AccessDescriptor accdesc, integer size)" conts="AArch32.CheckBreakpoint">FaultRecord <anchor link="AArch32.CheckBreakpoint.4" hover="function: FaultRecord AArch32.CheckBreakpoint(FaultRecord fault_in, bits(32) vaddress, AccessDescriptor accdesc, integer size)">AArch32.CheckBreakpoint</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault_in, bits(32) vaddress,</line>
<line>                                    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, integer size)</line>
<line>    assert <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>());</line>
<line>    assert size IN {2,4};</line>
<line></line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = fault_in;</line>
<line>    match = FALSE;</line>
<line>    mismatch = FALSE;</line>
<line></line>
<line>    for i = 0 to <a link="impl-shared.NumBreakpointsImplemented.0" file="shared_pseudocode.xml" hover="function: integer NumBreakpointsImplemented()">NumBreakpointsImplemented</a>() - 1</line>
<line>        (match_i, mismatch_i) = <a link="AArch32.BreakpointMatch.4" file="shared_pseudocode.xml" hover="function: (boolean,boolean) AArch32.BreakpointMatch(integer n, bits(32) vaddress, AccessDescriptor accdesc, integer size)">AArch32.BreakpointMatch</a>(i, vaddress, accdesc, size);</line>
<line>        match = match || match_i;</line>
<line>        mismatch = mismatch || mismatch_i;</line>
<line></line>
<line>    if match &amp;&amp; <a link="impl-shared.HaltOnBreakpointOrWatchpoint.0" file="shared_pseudocode.xml" hover="function: boolean HaltOnBreakpointOrWatchpoint()">HaltOnBreakpointOrWatchpoint</a>() then</line>
<line>        reason = <a link="DebugHalt_Breakpoint" file="shared_pseudocode.xml" hover="constant bits(6) DebugHalt_Breakpoint = '000111'">DebugHalt_Breakpoint</a>;</line>
<line>        <a link="impl-shared.Halt.1" file="shared_pseudocode.xml" hover="function: Halt(bits(6) reason)">Halt</a>(reason);</line>
<line>    elsif (match || mismatch) then</line>
<line>        fault.statuscode = <a link="Fault_Debug" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Debug</a>;</line>
<line>        fault.debugmoe   = <a link="DebugException_Breakpoint" file="shared_pseudocode.xml" hover="constant bits(4) DebugException_Breakpoint = '0001'">DebugException_Breakpoint</a>;</line>
<line></line>
<line>    return fault;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/debug/AArch32.CheckDebug" mylink="aarch32.translation.debug.AArch32.CheckDebug" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.CheckDebug()</line>
<line>// ====================</line>
<line>// Called on each access to check for a debug exception or entry to Debug state.</line>
<line></line>
<line link="AArch32.CheckDebug.3" hover="function: FaultRecord AArch32.CheckDebug(bits(32) vaddress, AccessDescriptor accdesc, integer size)" conts="AArch32.CheckDebug">FaultRecord <anchor link="AArch32.CheckDebug.3" hover="function: FaultRecord AArch32.CheckDebug(bits(32) vaddress, AccessDescriptor accdesc, integer size)">AArch32.CheckDebug</anchor>(bits(32) vaddress, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, integer size)</line>
<line></line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = <a link="impl-shared.NoFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord NoFault(AccessDescriptor accdesc)">NoFault</a>(accdesc);</line>
<line></line>
<line>    boolean d_side = (<a link="impl-shared.IsDataAccess.1" file="shared_pseudocode.xml" hover="function: boolean IsDataAccess(AccessType acctype)">IsDataAccess</a>(accdesc.acctype) || accdesc.acctype == <a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>);</line>
<line>    boolean i_side = (accdesc.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a>);</line>
<line>    generate_exception = <a link="AArch32.GenerateDebugExceptions.0" file="shared_pseudocode.xml" hover="function: boolean AArch32.GenerateDebugExceptions()">AArch32.GenerateDebugExceptions</a>() &amp;&amp; DBGDSCRext.MDBGen == '1';</line>
<line>    halt = <a link="impl-shared.HaltOnBreakpointOrWatchpoint.0" file="shared_pseudocode.xml" hover="function: boolean HaltOnBreakpointOrWatchpoint()">HaltOnBreakpointOrWatchpoint</a>();</line>
<line>    // Relative priority of Vector Catch and Breakpoint exceptions not defined in the architecture</line>
<line>    vector_catch_first = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_BPVECTORCATCHPRI" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BPVECTORCATCHPRI</a>);</line>
<line></line>
<line>    if i_side &amp;&amp; vector_catch_first &amp;&amp; generate_exception then</line>
<line>        fault = <a link="AArch32.CheckVectorCatch.3" file="shared_pseudocode.xml" hover="function: FaultRecord AArch32.CheckVectorCatch(FaultRecord fault_in, bits(32) vaddress, integer size)">AArch32.CheckVectorCatch</a>(fault, vaddress, size);</line>
<line></line>
<line>    if fault.statuscode == <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> &amp;&amp; (generate_exception || halt) then</line>
<line>        if d_side then</line>
<line>            fault = <a link="AArch32.CheckWatchpoint.4" file="shared_pseudocode.xml" hover="function: FaultRecord AArch32.CheckWatchpoint(FaultRecord fault_in, bits(32) vaddress, AccessDescriptor accdesc, integer size)">AArch32.CheckWatchpoint</a>(fault, vaddress, accdesc, size);</line>
<line>        elsif i_side then</line>
<line>            fault = <a link="AArch32.CheckBreakpoint.4" file="shared_pseudocode.xml" hover="function: FaultRecord AArch32.CheckBreakpoint(FaultRecord fault_in, bits(32) vaddress, AccessDescriptor accdesc, integer size)">AArch32.CheckBreakpoint</a>(fault, vaddress, accdesc, size);</line>
<line></line>
<line>    if fault.statuscode == <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> &amp;&amp; i_side &amp;&amp; !vector_catch_first &amp;&amp; generate_exception then</line>
<line>        return <a link="AArch32.CheckVectorCatch.3" file="shared_pseudocode.xml" hover="function: FaultRecord AArch32.CheckVectorCatch(FaultRecord fault_in, bits(32) vaddress, integer size)">AArch32.CheckVectorCatch</a>(fault, vaddress, size);</line>
<line></line>
<line>    return fault;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/debug/AArch32.CheckVectorCatch" mylink="aarch32.translation.debug.AArch32.CheckVectorCatch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.CheckVectorCatch()</line>
<line>// ==========================</line>
<line>// Called before executing the instruction of length "size" bytes at "vaddress" in an AArch32</line>
<line>// translation regime, when debug exceptions are enabled.</line>
<line></line>
<line link="AArch32.CheckVectorCatch.3" hover="function: FaultRecord AArch32.CheckVectorCatch(FaultRecord fault_in, bits(32) vaddress, integer size)" conts="AArch32.CheckVectorCatch">FaultRecord <anchor link="AArch32.CheckVectorCatch.3" hover="function: FaultRecord AArch32.CheckVectorCatch(FaultRecord fault_in, bits(32) vaddress, integer size)">AArch32.CheckVectorCatch</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault_in, bits(32) vaddress, integer size)</line>
<line>    assert <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>());</line>
<line></line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = fault_in;</line>
<line>    match = <a link="AArch32.VCRMatch.1" file="shared_pseudocode.xml" hover="function: boolean AArch32.VCRMatch(bits(32) vaddress)">AArch32.VCRMatch</a>(vaddress);</line>
<line>    if size == 4 &amp;&amp; !match &amp;&amp; <a link="AArch32.VCRMatch.1" file="shared_pseudocode.xml" hover="function: boolean AArch32.VCRMatch(bits(32) vaddress)">AArch32.VCRMatch</a>(vaddress + 2) then</line>
<line>        match = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_VCMATCHHALF" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_VCMATCHHALF</a>);</line>
<line></line>
<line>    if match then</line>
<line>        fault.statuscode = <a link="Fault_Debug" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Debug</a>;</line>
<line>        fault.debugmoe   = <a link="DebugException_VectorCatch" file="shared_pseudocode.xml" hover="constant bits(4) DebugException_VectorCatch = '0101'">DebugException_VectorCatch</a>;</line>
<line></line>
<line>    return fault;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/debug/AArch32.CheckWatchpoint" mylink="aarch32.translation.debug.AArch32.CheckWatchpoint" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.CheckWatchpoint()</line>
<line>// =========================</line>
<line>// Called before accessing the memory location of "size" bytes at "address",</line>
<line>// when either debug exceptions are enabled for the access, or halting debug</line>
<line>// is enabled and halting is allowed.</line>
<line></line>
<line link="AArch32.CheckWatchpoint.4" hover="function: FaultRecord AArch32.CheckWatchpoint(FaultRecord fault_in, bits(32) vaddress, AccessDescriptor accdesc, integer size)" conts="AArch32.CheckWatchpoint">FaultRecord <anchor link="AArch32.CheckWatchpoint.4" hover="function: FaultRecord AArch32.CheckWatchpoint(FaultRecord fault_in, bits(32) vaddress, AccessDescriptor accdesc, integer size)">AArch32.CheckWatchpoint</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault_in, bits(32) vaddress,</line>
<line>                                    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, integer size)</line>
<line>    assert <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>());</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = fault_in;</line>
<line></line>
<line>    if accdesc.acctype == <a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a> then</line>
<line>        if accdesc.cacheop != <a link="CacheOp_Invalidate" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_Invalidate</a> then</line>
<line>            return fault;</line>
<line>        elsif !(boolean IMPLEMENTATION_DEFINED "DCIMVAC generates watchpoint") then</line>
<line>            return fault;</line>
<line>    elsif !<a link="impl-shared.IsDataAccess.1" file="shared_pseudocode.xml" hover="function: boolean IsDataAccess(AccessType acctype)">IsDataAccess</a>(accdesc.acctype) then</line>
<line>        return fault;</line>
<line></line>
<line>    match = FALSE;</line>
<line>    for i = 0 to <a link="impl-shared.NumWatchpointsImplemented.0" file="shared_pseudocode.xml" hover="function: integer NumWatchpointsImplemented()">NumWatchpointsImplemented</a>() - 1</line>
<line>        if <a link="AArch32.WatchpointMatch.4" file="shared_pseudocode.xml" hover="function: boolean AArch32.WatchpointMatch(integer n, bits(32) vaddress, integer size, AccessDescriptor accdesc)">AArch32.WatchpointMatch</a>(i, vaddress, size, accdesc) then</line>
<line>            match = TRUE;</line>
<line></line>
<line>    if match &amp;&amp; <a link="impl-shared.HaltOnBreakpointOrWatchpoint.0" file="shared_pseudocode.xml" hover="function: boolean HaltOnBreakpointOrWatchpoint()">HaltOnBreakpointOrWatchpoint</a>() then</line>
<line>        reason = <a link="DebugHalt_Watchpoint" file="shared_pseudocode.xml" hover="constant bits(6) DebugHalt_Watchpoint = '101011'">DebugHalt_Watchpoint</a>;</line>
<line>        EDWAR = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(vaddress, 64);</line>
<line>        <a link="impl-shared.Halt.1" file="shared_pseudocode.xml" hover="function: Halt(bits(6) reason)">Halt</a>(reason);</line>
<line>    elsif match then</line>
<line>        fault.statuscode = <a link="Fault_Debug" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Debug</a>;</line>
<line>        fault.debugmoe   = <a link="DebugException_Watchpoint" file="shared_pseudocode.xml" hover="constant bits(4) DebugException_Watchpoint = '1010'">DebugException_Watchpoint</a>;</line>
<line></line>
<line>    return fault;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/faults/AArch32.IPAIsOutOfRange" mylink="aarch32.translation.faults.AArch32.IPAIsOutOfRange" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.IPAIsOutOfRange()</line>
<line>// =========================</line>
<line>// Check intermediate physical address bits not resolved by translation are ZERO</line>
<line></line>
<line>boolean AArch32.IPAIsOutOfRange(S2TTWParams walkparams, bits(40) ipa)</line>
<line>    // Input Address size</line>
<line>    iasize = <a link="AArch32.S2IASize.1" file="shared_pseudocode.xml" hover="function: integer AArch32.S2IASize(bits(4) t0sz)">AArch32.S2IASize</a>(walkparams.t0sz);</line>
<line></line>
<line>    return iasize &lt; 40 &amp;&amp; !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(ipa&lt;39:iasize&gt;);</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/faults/AArch32.S1HasAlignmentFault" mylink="aarch32.translation.faults.AArch32.S1HasAlignmentFault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.S1HasAlignmentFault()</line>
<line>// =============================</line>
<line>// Returns whether stage 1 output fails alignment requirement on data accesses</line>
<line>// to Device memory</line>
<line></line>
<line link="AArch32.S1HasAlignmentFault.4" hover="function: boolean AArch32.S1HasAlignmentFault(AccessDescriptor accdesc, boolean aligned, bit ntlsmd, MemoryAttributes memattrs)" conts="AArch32.S1HasAlignmentFault">boolean <anchor link="AArch32.S1HasAlignmentFault.4" hover="function: boolean AArch32.S1HasAlignmentFault(AccessDescriptor accdesc, boolean aligned, bit ntlsmd, MemoryAttributes memattrs)">AArch32.S1HasAlignmentFault</anchor>(<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, boolean aligned,</line>
<line>                                    bit ntlsmd, <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs)</line>
<line>    if accdesc.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> then</line>
<line>        return FALSE;</line>
<line>    elsif accdesc.a32lsmd &amp;&amp; ntlsmd == '0' then</line>
<line>        return memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> &amp;&amp;  memattrs.device != <a link="DeviceType_GRE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_GRE</a>;</line>
<line>    elsif accdesc.acctype == <a link="AccessType_DCZero" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DCZero</a> then</line>
<line>        return memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a>;</line>
<line>    else</line>
<line>        return memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> &amp;&amp; !aligned;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/faults/AArch32.S1LDHasPermissionsFault" mylink="aarch32.translation.faults.AArch32.S1LDHasPermissionsFault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.S1LDHasPermissionsFault()</line>
<line>// =================================</line>
<line>// Returns whether an access using stage 1 long-descriptor translation</line>
<line>// violates permissions of target memory</line>
<line></line>
<line>boolean AArch32.S1LDHasPermissionsFault(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, S1TTWParams walkparams, <a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> perms,</line>
<line>                                        <a link="MemType" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType</a> memtype, <a link="PASpace" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PASpace</a> paspace, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    bit  r,  w,  x;</line>
<line>    bit pr, pw;</line>
<line>    bit ur, uw;</line>
<line>    bit xn;</line>
<line>    if <a link="impl-shared.HasUnprivileged.1" file="shared_pseudocode.xml" hover="function: boolean HasUnprivileged(Regime regime)">HasUnprivileged</a>(regime) then</line>
<line>        // Apply leaf permissions</line>
<line>        case perms.ap&lt;2:1&gt; of</line>
<line>            when '00' (pr,pw,ur,uw) = ('1','1','0','0'); // R/W at PL1 only</line>
<line>            when '01' (pr,pw,ur,uw) = ('1','1','1','1'); // R/W at any PL</line>
<line>            when '10' (pr,pw,ur,uw) = ('1','0','0','0'); // RO at PL1 only</line>
<line>            when '11' (pr,pw,ur,uw) = ('1','0','1','0'); // RO at any PL</line>
<line></line>
<line>        // Apply hierarchical permissions</line>
<line>        case perms.ap_table of</line>
<line>            when '00' (pr,pw,ur,uw) = ( pr, pw, ur, uw); // No effect</line>
<line>            when '01' (pr,pw,ur,uw) = ( pr, pw,'0','0'); // Privileged access</line>
<line>            when '10' (pr,pw,ur,uw) = ( pr,'0', ur,'0'); // Read-only</line>
<line>            when '11' (pr,pw,ur,uw) = ( pr,'0','0','0'); // Read-only, privileged access</line>
<line></line>
<line>        xn   = perms.xn OR perms.xn_table;</line>
<line>        pxn  = perms.pxn OR perms.pxn_table;</line>
<line></line>
<line>        ux = ur AND NOT(xn OR (uw AND walkparams.wxn));</line>
<line>        px = pr AND NOT(xn OR pxn OR (pw AND walkparams.wxn) OR (uw AND walkparams.uwxn));</line>
<line></line>
<line>        if <a link="impl-shared.HavePANExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePANExt()">HavePANExt</a>() &amp;&amp; accdesc.pan then</line>
<line>            pan = PSTATE.PAN AND (ur OR uw);</line>
<line>            pr  = pr AND NOT(pan);</line>
<line>            pw  = pw AND NOT(pan);</line>
<line></line>
<line>        (r,w,x) = if accdesc.el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then (ur,uw,ux) else (pr,pw,px);</line>
<line></line>
<line>        // Prevent execution from Non-secure space by PE in Secure state if SIF is set</line>
<line>        if accdesc.ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> &amp;&amp; paspace == <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a> then</line>
<line>            x = x AND NOT(walkparams.sif);</line>
<line>    else</line>
<line>        // Apply leaf permissions</line>
<line>        case perms.ap&lt;2&gt; of</line>
<line>            when '0' (r,w) = ('1','1'); // No effect</line>
<line>            when '1' (r,w) = ('1','0'); // Read-only</line>
<line></line>
<line>        // Apply hierarchical permissions</line>
<line>        case perms.ap_table&lt;1&gt; of</line>
<line>            when '0' (r,w) = ( r , w ); // No effect</line>
<line>            when '1' (r,w) = ( r ,'0'); // Read-only</line>
<line></line>
<line>        xn = perms.xn OR perms.xn_table;</line>
<line>        x  = NOT(xn OR (w AND walkparams.wxn));</line>
<line></line>
<line>    if accdesc.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> then</line>
<line>        constraint = <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_INSTRDEVICE" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_INSTRDEVICE</a>);</line>
<line>        if constraint == <a link="Constraint_FAULT" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_FAULT</a> &amp;&amp; memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> then</line>
<line>            return TRUE;</line>
<line>        else</line>
<line>            return x == '0';</line>
<line>    elsif accdesc.acctype IN {<a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a>, <a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>} then</line>
<line>        return FALSE;</line>
<line>    elsif accdesc.write then</line>
<line>        return w == '0';</line>
<line>    else</line>
<line>        return r == '0';</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/faults/AArch32.S1SDHasPermissionsFault" mylink="aarch32.translation.faults.AArch32.S1SDHasPermissionsFault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.S1SDHasPermissionsFault()</line>
<line>// =================================</line>
<line>// Returns whether an access using stage 1 short-descriptor translation</line>
<line>// violates permissions of target memory</line>
<line></line>
<line link="AArch32.S1SDHasPermissionsFault.5" hover="function: boolean AArch32.S1SDHasPermissionsFault(Regime regime, Permissions perms_in, MemType memtype, PASpace paspace, AccessDescriptor accdesc)" conts="AArch32.S1SDHasPermissionsFault">boolean <anchor link="AArch32.S1SDHasPermissionsFault.5" hover="function: boolean AArch32.S1SDHasPermissionsFault(Regime regime, Permissions perms_in, MemType memtype, PASpace paspace, AccessDescriptor accdesc)">AArch32.S1SDHasPermissionsFault</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, <a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> perms_in, <a link="MemType" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType</a> memtype,</line>
<line>                                        <a link="PASpace" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PASpace</a> paspace, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    <a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> perms = perms_in;</line>
<line>    bit pr, pw;</line>
<line>    bit ur, uw;</line>
<line>    SCTLR_Type sctlr;</line>
<line>    if regime == <a link="Regime_EL30" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL30</a> then</line>
<line>        sctlr = SCTLR_S;</line>
<line>    elsif <a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        sctlr = SCTLR_NS;</line>
<line>    else</line>
<line>        sctlr = SCTLR;</line>
<line></line>
<line>    if sctlr.AFE == '0' then</line>
<line>        // Map Reserved encoding '100'</line>
<line>        if perms.ap == '100' then</line>
<line>            perms.ap = bits(3) IMPLEMENTATION_DEFINED "Reserved short descriptor AP encoding";</line>
<line></line>
<line>        case perms.ap of</line>
<line>            when '000' (pr,pw,ur,uw) = ('0','0','0','0'); // No access</line>
<line>            when '001' (pr,pw,ur,uw) = ('1','1','0','0'); // R/W at PL1 only</line>
<line>            when '010' (pr,pw,ur,uw) = ('1','1','1','0'); // R/W at PL1, RO at PL0</line>
<line>            when '011' (pr,pw,ur,uw) = ('1','1','1','1'); // R/W at any PL</line>
<line>            //   '100' is reserved</line>
<line>            when '101' (pr,pw,ur,uw) = ('1','0','0','0'); // RO at PL1 only</line>
<line>            when '110' (pr,pw,ur,uw) = ('1','0','1','0'); // RO at any PL (deprecated)</line>
<line>            when '111' (pr,pw,ur,uw) = ('1','0','1','0'); // RO at any PL</line>
<line>    else // Simplified access permissions model</line>
<line>        case perms.ap&lt;2:1&gt; of</line>
<line>            when '00' (pr,pw,ur,uw) = ('1','1','0','0'); // R/W at PL1 only</line>
<line>            when '01' (pr,pw,ur,uw) = ('1','1','1','1'); // R/W at any PL</line>
<line>            when '10' (pr,pw,ur,uw) = ('1','0','0','0'); // RO at PL1 only</line>
<line>            when '11' (pr,pw,ur,uw) = ('1','0','1','0'); // RO at any PL</line>
<line></line>
<line>    ux = ur AND NOT(perms.xn OR (uw AND sctlr.WXN));</line>
<line>    px = pr AND NOT(perms.xn OR perms.pxn OR (pw AND sctlr.WXN) OR (uw AND sctlr.UWXN));</line>
<line></line>
<line>    if <a link="impl-shared.HavePANExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePANExt()">HavePANExt</a>() &amp;&amp; accdesc.pan then</line>
<line>        pan = PSTATE.PAN AND (ur OR uw);</line>
<line>        pr  = pr AND NOT(pan);</line>
<line>        pw  = pw AND NOT(pan);</line>
<line></line>
<line>    (r,w,x) = if accdesc.el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then (ur,uw,ux) else (pr,pw,px);</line>
<line></line>
<line>    // Prevent execution from Non-secure space by PE in Secure state if SIF is set</line>
<line>    if accdesc.ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> &amp;&amp; paspace == <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a> then</line>
<line>        x = x AND NOT(if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then SCR.SIF else SCR_EL3.SIF);</line>
<line></line>
<line>    if accdesc.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> then</line>
<line>        if (memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> &amp;&amp;</line>
<line>                <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_INSTRDEVICE" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_INSTRDEVICE</a>) == <a link="Constraint_FAULT" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_FAULT</a>) then</line>
<line>            return TRUE;</line>
<line>        else</line>
<line>            return x == '0';</line>
<line>    elsif accdesc.acctype IN {<a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a>, <a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>} then</line>
<line>        return FALSE;</line>
<line>    elsif accdesc.write then</line>
<line>        return w == '0';</line>
<line>    else</line>
<line>        return r == '0';</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/faults/AArch32.S2HasAlignmentFault" mylink="aarch32.translation.faults.AArch32.S2HasAlignmentFault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.S2HasAlignmentFault()</line>
<line>// =============================</line>
<line>// Returns whether stage 2 output fails alignment requirement on data accesses</line>
<line>// to Device memory</line>
<line></line>
<line link="AArch32.S2HasAlignmentFault.3" hover="function: boolean AArch32.S2HasAlignmentFault(AccessDescriptor accdesc, boolean aligned, MemoryAttributes memattrs)" conts="AArch32.S2HasAlignmentFault">boolean <anchor link="AArch32.S2HasAlignmentFault.3" hover="function: boolean AArch32.S2HasAlignmentFault(AccessDescriptor accdesc, boolean aligned, MemoryAttributes memattrs)">AArch32.S2HasAlignmentFault</anchor>(<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, boolean aligned,</line>
<line>                                    <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs)</line>
<line>    if accdesc.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> then</line>
<line>        return FALSE;</line>
<line>    elsif accdesc.acctype == <a link="AccessType_DCZero" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DCZero</a> then</line>
<line>        return memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a>;</line>
<line>    else</line>
<line>        return memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> &amp;&amp; !aligned;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/faults/AArch32.S2HasPermissionsFault" mylink="aarch32.translation.faults.AArch32.S2HasPermissionsFault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.S2HasPermissionsFault()</line>
<line>// ===============================</line>
<line>// Returns whether stage 2 access violates permissions of target memory</line>
<line></line>
<line>boolean AArch32.S2HasPermissionsFault(S2TTWParams walkparams, <a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> perms, <a link="MemType" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType</a> memtype,</line>
<line>                                      <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    bit px;</line>
<line>    bit ux;</line>
<line>    r = perms.s2ap&lt;0&gt;;</line>
<line>    w = perms.s2ap&lt;1&gt;;</line>
<line>    bit x;</line>
<line>    if <a link="impl-shared.HaveExtendedExecuteNeverExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveExtendedExecuteNeverExt()">HaveExtendedExecuteNeverExt</a>() then</line>
<line>        case perms.s2xn:perms.s2xnx of</line>
<line>            when '00'  (px, ux) = ( r , r );</line>
<line>            when '01'  (px, ux) = ('0', r );</line>
<line>            when '10'  (px, ux) = ('0','0');</line>
<line>            when '11'  (px, ux) = ( r ,'0');</line>
<line></line>
<line>        x = if accdesc.el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then ux else px;</line>
<line>    else</line>
<line>        x = r AND NOT(perms.s2xn);</line>
<line></line>
<line>    if accdesc.acctype == <a link="AccessType_TTW" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_TTW</a> then</line>
<line>        return (walkparams.ptw == '1' &amp;&amp; memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a>) || r == '0';</line>
<line></line>
<line>    elsif accdesc.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> then</line>
<line>        constraint = <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_INSTRDEVICE" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_INSTRDEVICE</a>);</line>
<line>        return (constraint == <a link="Constraint_FAULT" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_FAULT</a> &amp;&amp; memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a>) || x == '0';</line>
<line></line>
<line>    elsif accdesc.acctype IN {<a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a>, <a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>} then</line>
<line>        return FALSE;</line>
<line></line>
<line>    elsif accdesc.write then</line>
<line>        return w == '0';</line>
<line></line>
<line>    else</line>
<line>        return r == '0';</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/faults/AArch32.S2InconsistentSL" mylink="aarch32.translation.faults.AArch32.S2InconsistentSL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.S2InconsistentSL()</line>
<line>// ==========================</line>
<line>// Detect inconsistent configuration of stage 2 T0SZ and SL fields</line>
<line></line>
<line>boolean AArch32.S2InconsistentSL(S2TTWParams walkparams)</line>
<line>    startlevel  = <a link="AArch32.S2StartLevel.1" file="shared_pseudocode.xml" hover="function: integer AArch32.S2StartLevel(bits(2) sl0)">AArch32.S2StartLevel</a>(walkparams.sl0);</line>
<line>    levels      = <a link="FINAL_LEVEL" file="shared_pseudocode.xml" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</a> - startlevel;</line>
<line>    granulebits = <a link="impl-shared.TGxGranuleBits.1" file="shared_pseudocode.xml" hover="function: integer TGxGranuleBits(TGx tgx)">TGxGranuleBits</a>(walkparams.tgx);</line>
<line>    stride      = granulebits - 3;</line>
<line></line>
<line>    // Input address size must at least be large enough to be resolved from the start level</line>
<line>    sl_min_iasize = (</line>
<line>        levels * stride // Bits resolved by table walk, except initial level</line>
<line>        + granulebits   // Bits directly mapped to output address</line>
<line>        + 1);           // At least 1 more bit to be decoded by initial level</line>
<line></line>
<line>    // Can accomodate 1 more stride in the level + concatenation of up to 2^4 tables</line>
<line>    sl_max_iasize = sl_min_iasize + (stride-1) + 4;</line>
<line>    // Configured Input Address size</line>
<line>    iasize        = <a link="AArch32.S2IASize.1" file="shared_pseudocode.xml" hover="function: integer AArch32.S2IASize(bits(4) t0sz)">AArch32.S2IASize</a>(walkparams.t0sz);</line>
<line></line>
<line>    return iasize &lt; sl_min_iasize || iasize &gt; sl_max_iasize;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/faults/AArch32.VAIsOutOfRange" mylink="aarch32.translation.faults.AArch32.VAIsOutOfRange" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.VAIsOutOfRange()</line>
<line>// ========================</line>
<line>// Check virtual address bits not resolved by translation are identical</line>
<line>// and of accepted value</line>
<line></line>
<line>boolean AArch32.VAIsOutOfRange(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, S1TTWParams walkparams, bits(32) va)</line>
<line>    if regime == <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a> then</line>
<line>        // Input Address size</line>
<line>        iasize = <a link="AArch32.S1IASize.1" file="shared_pseudocode.xml" hover="function: integer AArch32.S1IASize(bits(3) txsz)">AArch32.S1IASize</a>(walkparams.t0sz);</line>
<line>        return walkparams.t0sz != '000' &amp;&amp; !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(va&lt;31:iasize&gt;);</line>
<line>    elsif walkparams.t1sz != '000' &amp;&amp; walkparams.t0sz != '000' then</line>
<line>        // Lower range Input Address size</line>
<line>        lo_iasize = <a link="AArch32.S1IASize.1" file="shared_pseudocode.xml" hover="function: integer AArch32.S1IASize(bits(3) txsz)">AArch32.S1IASize</a>(walkparams.t0sz);</line>
<line>        // Upper range Input Address size</line>
<line>        up_iasize = <a link="AArch32.S1IASize.1" file="shared_pseudocode.xml" hover="function: integer AArch32.S1IASize(bits(3) txsz)">AArch32.S1IASize</a>(walkparams.t1sz);</line>
<line>        return !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(va&lt;31:lo_iasize&gt;) &amp;&amp; !<a link="impl-shared.IsOnes.1" file="shared_pseudocode.xml" hover="function: boolean IsOnes(bits(N) x)">IsOnes</a>(va&lt;31:up_iasize&gt;);</line>
<line>    else</line>
<line>        return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/tlbcontext/AArch32.GetS1TLBContext" mylink="aarch32.translation.tlbcontext.AArch32.GetS1TLBContext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.GetS1TLBContext()</line>
<line>// =========================</line>
<line>// Gather translation context for accesses with VA to match against TLB entries</line>
<line></line>
<line link="AArch32.GetS1TLBContext.3" hover="function: TLBContext AArch32.GetS1TLBContext(Regime regime, SecurityState ss, bits(32) va)" conts="AArch32.GetS1TLBContext">TLBContext <anchor link="AArch32.GetS1TLBContext.3" hover="function: TLBContext AArch32.GetS1TLBContext(Regime regime, SecurityState ss, bits(32) va)">AArch32.GetS1TLBContext</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss, bits(32) va)</line>
<line>    <a link="TLBContext" file="shared_pseudocode.xml" hover="type TLBContext is ( SecurityState ss, Regime regime, bits(16) vmid, bits(16) asid, bit nG, PASpace ipaspace, boolean includes_s1, boolean includes_s2, boolean includes_gpt, bits(64) ia, TGx tg, bit cnp, integer level, boolean isd128, bit xs )">TLBContext</a> tlbcontext;</line>
<line></line>
<line>    case regime of</line>
<line>        when <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>  tlbcontext = <a link="AArch32.TLBContextEL2.1" file="shared_pseudocode.xml" hover="function: TLBContext AArch32.TLBContextEL2(bits(32) va)">AArch32.TLBContextEL2</a>(va);</line>
<line>        when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> tlbcontext = <a link="AArch32.TLBContextEL10.2" file="shared_pseudocode.xml" hover="function: TLBContext AArch32.TLBContextEL10(SecurityState ss, bits(32) va)">AArch32.TLBContextEL10</a>(ss, va);</line>
<line>        when <a link="Regime_EL30" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL30</a> tlbcontext = <a link="AArch32.TLBContextEL30.1" file="shared_pseudocode.xml" hover="function: TLBContext AArch32.TLBContextEL30(bits(32) va)">AArch32.TLBContextEL30</a>(va);</line>
<line></line>
<line>    tlbcontext.includes_s1 = TRUE;</line>
<line>    // The following may be amended for EL1&amp;0 Regime if caching of stage 2 is successful</line>
<line>    tlbcontext.includes_s2 = FALSE;</line>
<line>    return tlbcontext;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/tlbcontext/AArch32.GetS2TLBContext" mylink="aarch32.translation.tlbcontext.AArch32.GetS2TLBContext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.GetS2TLBContext()</line>
<line>// =========================</line>
<line>// Gather translation context for accesses with IPA to match against TLB entries</line>
<line></line>
<line link="AArch32.GetS2TLBContext.1" hover="function: TLBContext AArch32.GetS2TLBContext(FullAddress ipa)" conts="AArch32.GetS2TLBContext">TLBContext <anchor link="AArch32.GetS2TLBContext.1" hover="function: TLBContext AArch32.GetS2TLBContext(FullAddress ipa)">AArch32.GetS2TLBContext</anchor>(<a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> ipa)</line>
<line>    assert ipa.paspace == <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line></line>
<line>    <a link="TLBContext" file="shared_pseudocode.xml" hover="type TLBContext is ( SecurityState ss, Regime regime, bits(16) vmid, bits(16) asid, bit nG, PASpace ipaspace, boolean includes_s1, boolean includes_s2, boolean includes_gpt, bits(64) ia, TGx tg, bit cnp, integer level, boolean isd128, bit xs )">TLBContext</a> tlbcontext;</line>
<line></line>
<line>    tlbcontext.ss          = <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a>;</line>
<line>    tlbcontext.regime      = <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a>;</line>
<line>    tlbcontext.ipaspace    = ipa.paspace;</line>
<line>    tlbcontext.vmid        = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(VTTBR.VMID, 16);</line>
<line>    tlbcontext.tg          = <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>;</line>
<line>    tlbcontext.includes_s1 = FALSE;</line>
<line>    tlbcontext.includes_s2 = TRUE;</line>
<line>    tlbcontext.ia          = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(ipa.address, 64);</line>
<line>    tlbcontext.cnp         = if <a link="impl-shared.HaveCommonNotPrivateTransExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveCommonNotPrivateTransExt()">HaveCommonNotPrivateTransExt</a>() then VTTBR.CnP else '0';</line>
<line></line>
<line>    return tlbcontext;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/tlbcontext/AArch32.TLBContextEL10" mylink="aarch32.translation.tlbcontext.AArch32.TLBContextEL10" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TLBContextEL10()</line>
<line>// ========================</line>
<line>// Gather translation context for accesses under EL10 regime</line>
<line>// (PL10 when EL3 is A64) to match against TLB entries</line>
<line></line>
<line link="AArch32.TLBContextEL10.2" hover="function: TLBContext AArch32.TLBContextEL10(SecurityState ss, bits(32) va)" conts="AArch32.TLBContextEL10">TLBContext <anchor link="AArch32.TLBContextEL10.2" hover="function: TLBContext AArch32.TLBContextEL10(SecurityState ss, bits(32) va)">AArch32.TLBContextEL10</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss, bits(32) va)</line>
<line>    <a link="TLBContext" file="shared_pseudocode.xml" hover="type TLBContext is ( SecurityState ss, Regime regime, bits(16) vmid, bits(16) asid, bit nG, PASpace ipaspace, boolean includes_s1, boolean includes_s2, boolean includes_gpt, bits(64) ia, TGx tg, bit cnp, integer level, boolean isd128, bit xs )">TLBContext</a> tlbcontext;</line>
<line>    TTBCR_Type ttbcr;</line>
<line>    TTBR0_Type ttbr0;</line>
<line>    TTBR1_Type ttbr1;</line>
<line>    CONTEXTIDR_Type contextidr;</line>
<line></line>
<line>    if <a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        ttbcr      = TTBCR_NS;</line>
<line>        ttbr0      = TTBR0_NS;</line>
<line>        ttbr1      = TTBR1_NS;</line>
<line>        contextidr = CONTEXTIDR_NS;</line>
<line>    else</line>
<line>        ttbcr      = TTBCR;</line>
<line>        ttbr0      = TTBR0;</line>
<line>        ttbr1      = TTBR1;</line>
<line>        contextidr = CONTEXTIDR;</line>
<line></line>
<line>    tlbcontext.ss     = ss;</line>
<line>    tlbcontext.regime = <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a>;</line>
<line></line>
<line>    if <a link="AArch32.EL2Enabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch32.EL2Enabled(SecurityState ss)">AArch32.EL2Enabled</a>(ss) then</line>
<line>        tlbcontext.vmid = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(VTTBR.VMID, 16);</line>
<line></line>
<line>    if ttbcr.EAE == '1' then</line>
<line>        tlbcontext.asid = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(if ttbcr.A1 == '0' then ttbr0.ASID else ttbr1.ASID, 16);</line>
<line>    else</line>
<line>        tlbcontext.asid = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(contextidr.ASID, 16);</line>
<line></line>
<line>    tlbcontext.tg = <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>;</line>
<line>    tlbcontext.ia = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(va, 64);</line>
<line></line>
<line>    if <a link="impl-shared.HaveCommonNotPrivateTransExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveCommonNotPrivateTransExt()">HaveCommonNotPrivateTransExt</a>() &amp;&amp; ttbcr.EAE == '1' then</line>
<line>        if <a link="AArch32.GetVARange.3" file="shared_pseudocode.xml" hover="function: VARange AArch32.GetVARange(bits(32) va, bits(3) t0sz, bits(3) t1sz)">AArch32.GetVARange</a>(va, ttbcr.T0SZ, ttbcr.T1SZ) == <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a> then</line>
<line>            tlbcontext.cnp = ttbr0.CnP;</line>
<line>        else</line>
<line>            tlbcontext.cnp = ttbr1.CnP;</line>
<line>    else</line>
<line>        tlbcontext.cnp = '0';</line>
<line></line>
<line>    return tlbcontext;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/tlbcontext/AArch32.TLBContextEL2" mylink="aarch32.translation.tlbcontext.AArch32.TLBContextEL2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TLBContextEL2()</line>
<line>// =======================</line>
<line>// Gather translation context for accesses under EL2 regime to match against TLB entries</line>
<line></line>
<line link="AArch32.TLBContextEL2.1" hover="function: TLBContext AArch32.TLBContextEL2(bits(32) va)" conts="AArch32.TLBContextEL2">TLBContext <anchor link="AArch32.TLBContextEL2.1" hover="function: TLBContext AArch32.TLBContextEL2(bits(32) va)">AArch32.TLBContextEL2</anchor>(bits(32) va)</line>
<line>    <a link="TLBContext" file="shared_pseudocode.xml" hover="type TLBContext is ( SecurityState ss, Regime regime, bits(16) vmid, bits(16) asid, bit nG, PASpace ipaspace, boolean includes_s1, boolean includes_s2, boolean includes_gpt, bits(64) ia, TGx tg, bit cnp, integer level, boolean isd128, bit xs )">TLBContext</a> tlbcontext;</line>
<line></line>
<line>    tlbcontext.ss     = <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a>;</line>
<line>    tlbcontext.regime = <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>;</line>
<line>    tlbcontext.ia     = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(va, 64);</line>
<line>    tlbcontext.tg     = <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>;</line>
<line>    tlbcontext.cnp    = if <a link="impl-shared.HaveCommonNotPrivateTransExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveCommonNotPrivateTransExt()">HaveCommonNotPrivateTransExt</a>() then HTTBR.CnP else '0';</line>
<line></line>
<line>    return tlbcontext;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/tlbcontext/AArch32.TLBContextEL30" mylink="aarch32.translation.tlbcontext.AArch32.TLBContextEL30" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TLBContextEL30()</line>
<line>// ========================</line>
<line>// Gather translation context for accesses under EL30 regime</line>
<line>// (PL10 in Secure state and EL3 is A32) to match against TLB entries</line>
<line></line>
<line link="AArch32.TLBContextEL30.1" hover="function: TLBContext AArch32.TLBContextEL30(bits(32) va)" conts="AArch32.TLBContextEL30">TLBContext <anchor link="AArch32.TLBContextEL30.1" hover="function: TLBContext AArch32.TLBContextEL30(bits(32) va)">AArch32.TLBContextEL30</anchor>(bits(32) va)</line>
<line>    <a link="TLBContext" file="shared_pseudocode.xml" hover="type TLBContext is ( SecurityState ss, Regime regime, bits(16) vmid, bits(16) asid, bit nG, PASpace ipaspace, boolean includes_s1, boolean includes_s2, boolean includes_gpt, bits(64) ia, TGx tg, bit cnp, integer level, boolean isd128, bit xs )">TLBContext</a> tlbcontext;</line>
<line></line>
<line>    tlbcontext.ss     = <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>;</line>
<line>    tlbcontext.regime = <a link="Regime_EL30" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL30</a>;</line>
<line></line>
<line>    if TTBCR_S.EAE == '1' then</line>
<line>        tlbcontext.asid = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(if TTBCR_S.A1 == '0' then TTBR0_S.ASID else TTBR1_S.ASID, 16);</line>
<line>    else</line>
<line>        tlbcontext.asid = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(CONTEXTIDR_S.ASID, 16);</line>
<line></line>
<line>    tlbcontext.tg = <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>;</line>
<line>    tlbcontext.ia = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(va, 64);</line>
<line></line>
<line>    if <a link="impl-shared.HaveCommonNotPrivateTransExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveCommonNotPrivateTransExt()">HaveCommonNotPrivateTransExt</a>() &amp;&amp; TTBCR_S.EAE == '1' then</line>
<line>        if <a link="AArch32.GetVARange.3" file="shared_pseudocode.xml" hover="function: VARange AArch32.GetVARange(bits(32) va, bits(3) t0sz, bits(3) t1sz)">AArch32.GetVARange</a>(va, TTBCR_S.T0SZ, TTBCR_S.T1SZ) == <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a> then</line>
<line>            tlbcontext.cnp = TTBR0_S.CnP;</line>
<line>        else</line>
<line>            tlbcontext.cnp = TTBR1_S.CnP;</line>
<line>    else</line>
<line>        tlbcontext.cnp = '0';</line>
<line></line>
<line>    return tlbcontext;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/translation/AArch32.EL2Enabled" mylink="aarch32.translation.translation.AArch32.EL2Enabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.EL2Enabled()</line>
<line>// ====================</line>
<line>// Returns whether EL2 is enabled for the given Security State</line>
<line></line>
<line link="AArch32.EL2Enabled.1" hover="function: boolean AArch32.EL2Enabled(SecurityState ss)" conts="AArch32.EL2Enabled">boolean <anchor link="AArch32.EL2Enabled.1" hover="function: boolean AArch32.EL2Enabled(SecurityState ss)">AArch32.EL2Enabled</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss)</line>
<line>    if ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>        if !(<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; <a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>()) then</line>
<line>            return FALSE;</line>
<line>        elsif <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>            return SCR_EL3.EEL2 == '1';</line>
<line>        else</line>
<line>            return boolean IMPLEMENTATION_DEFINED "Secure-only implementation";</line>
<line>    else</line>
<line>        return <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/translation/AArch32.FullTranslate" mylink="aarch32.translation.translation.AArch32.FullTranslate" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.FullTranslate()</line>
<line>// =======================</line>
<line>// Perform address translation as specified by VMSA-A32</line>
<line></line>
<line link="AArch32.FullTranslate.3" hover="function: AddressDescriptor AArch32.FullTranslate(bits(32) va, AccessDescriptor accdesc, boolean aligned)" conts="AArch32.FullTranslate">AddressDescriptor <anchor link="AArch32.FullTranslate.3" hover="function: AddressDescriptor AArch32.FullTranslate(bits(32) va, AccessDescriptor accdesc, boolean aligned)">AArch32.FullTranslate</anchor>(bits(32) va, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, boolean aligned)</line>
<line></line>
<line>    // Prepare fault fields in case a fault is detected</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = <a link="impl-shared.NoFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord NoFault(AccessDescriptor accdesc)">NoFault</a>(accdesc);</line>
<line>    <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime = <a link="impl-shared.TranslationRegime.1" file="shared_pseudocode.xml" hover="function: Regime TranslationRegime(bits(2) el)">TranslationRegime</a>(accdesc.el);</line>
<line></line>
<line>    // First Stage Translation</line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> ipa;</line>
<line>    if regime == <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a> || TTBCR.EAE == '1' then</line>
<line>        (fault, ipa) = <a link="AArch32.S1TranslateLD.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, AddressDescriptor) AArch32.S1TranslateLD(FaultRecord fault_in, Regime regime, bits(32) va, boolean aligned, AccessDescriptor accdesc)">AArch32.S1TranslateLD</a>(fault, regime, va, aligned, accdesc);</line>
<line>    else</line>
<line>        (fault, ipa, -) = <a link="AArch32.S1TranslateSD.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, AddressDescriptor, SDFType) AArch32.S1TranslateSD(FaultRecord fault_in, Regime regime, bits(32) va, boolean aligned, AccessDescriptor accdesc)">AArch32.S1TranslateSD</a>(fault, regime, va, aligned, accdesc);</line>
<line></line>
<line>    if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>        return <a link="impl-shared.CreateFaultyAddressDescriptor.2" file="shared_pseudocode.xml" hover="function: AddressDescriptor CreateFaultyAddressDescriptor(bits(64) va, FaultRecord fault)">CreateFaultyAddressDescriptor</a>(<a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(va, 64), fault);</line>
<line></line>
<line>    if regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        ipa.vaddress = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(va, 64);</line>
<line>        <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> pa;</line>
<line>        (fault, pa) = <a link="AArch32.S2Translate.4" file="shared_pseudocode.xml" hover="function: (FaultRecord, AddressDescriptor) AArch32.S2Translate(FaultRecord fault_in, AddressDescriptor ipa, boolean aligned, AccessDescriptor accdesc)">AArch32.S2Translate</a>(fault, ipa, aligned, accdesc);</line>
<line></line>
<line>        if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>            return <a link="impl-shared.CreateFaultyAddressDescriptor.2" file="shared_pseudocode.xml" hover="function: AddressDescriptor CreateFaultyAddressDescriptor(bits(64) va, FaultRecord fault)">CreateFaultyAddressDescriptor</a>(<a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(va, 64), fault);</line>
<line>        else</line>
<line>            return pa;</line>
<line>    else</line>
<line>        return ipa;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/translation/AArch32.OutputDomain" mylink="aarch32.translation.translation.AArch32.OutputDomain" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.OutputDomain()</line>
<line>// ======================</line>
<line>// Determine the domain the translated output address</line>
<line></line>
<line link="AArch32.OutputDomain.2" hover="function: bits(2) AArch32.OutputDomain(Regime regime, bits(4) domain)" conts="AArch32.OutputDomain">bits(2) <anchor link="AArch32.OutputDomain.2" hover="function: bits(2) AArch32.OutputDomain(Regime regime, bits(4) domain)">AArch32.OutputDomain</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(4) domain)</line>
<line>    bits(2) Dn;</line>
<line>    index = 2 * <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(domain);</line>
<line>    if regime == <a link="Regime_EL30" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL30</a> then</line>
<line>        Dn = DACR_S&lt;index+1:index&gt;;</line>
<line>    elsif <a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        Dn = DACR_NS&lt;index+1:index&gt;;</line>
<line>    else</line>
<line>        Dn = DACR&lt;index+1:index&gt;;</line>
<line></line>
<line>    if Dn == '10' then</line>
<line>        // Reserved value maps to an allocated value</line>
<line>        (-, Dn) = <a link="impl-shared.ConstrainUnpredictableBits.2" file="shared_pseudocode.xml" hover="function: (Constraint,bits(width)) ConstrainUnpredictableBits(Unpredictable which, integer width)">ConstrainUnpredictableBits</a>(<a link="Unpredictable_RESDACR" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESDACR</a>, 2);</line>
<line></line>
<line>    return Dn;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/translation/AArch32.S1DisabledOutput" mylink="aarch32.translation.translation.AArch32.S1DisabledOutput" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.S1DisabledOutput()</line>
<line>// ==========================</line>
<line>// Flat map the VA to IPA/PA, depending on the regime, assigning default memory attributes</line>
<line></line>
<line link="AArch32.S1DisabledOutput.5" hover="function: (FaultRecord, AddressDescriptor) AArch32.S1DisabledOutput(FaultRecord fault_in, Regime regime, bits(32) va, boolean aligned, AccessDescriptor accdesc)" conts="AArch32.S1DisabledOutput">(FaultRecord, AddressDescriptor) <anchor link="AArch32.S1DisabledOutput.5" hover="function: (FaultRecord, AddressDescriptor) AArch32.S1DisabledOutput(FaultRecord fault_in, Regime regime, bits(32) va, boolean aligned, AccessDescriptor accdesc)">AArch32.S1DisabledOutput</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault_in, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime,</line>
<line>                                                          bits(32) va, boolean aligned,</line>
<line>                                                          <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line></line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = fault_in;</line>
<line>    // No memory page is guarded when stage 1 address translation is disabled</line>
<line>    SetInGuardedPage(FALSE);</line>
<line></line>
<line>    <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs;</line>
<line>    bit default_cacheable;</line>
<line>    if regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; <a link="AArch32.EL2Enabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch32.EL2Enabled(SecurityState ss)">AArch32.EL2Enabled</a>(accdesc.ss) then</line>
<line>        if <a link="impl-shared.ELStateUsingAArch32.2" file="shared_pseudocode.xml" hover="function: boolean ELStateUsingAArch32(bits(2) el, boolean secure)">ELStateUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, accdesc.ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>) then</line>
<line>            default_cacheable = HCR.DC;</line>
<line>        else</line>
<line>            default_cacheable = HCR_EL2.DC;</line>
<line>    else</line>
<line>        default_cacheable = '0';</line>
<line></line>
<line>    if default_cacheable == '1' then</line>
<line>        // Use default cacheable settings</line>
<line>        memattrs.memtype      = <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>;</line>
<line>        memattrs.inner.attrs  = <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>;</line>
<line>        memattrs.inner.hints  = <a link="MemHint_RWA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RWA = '11'">MemHint_RWA</a>;</line>
<line>        memattrs.outer.attrs  = <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>;</line>
<line>        memattrs.outer.hints  = <a link="MemHint_RWA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RWA = '11'">MemHint_RWA</a>;</line>
<line>        memattrs.shareability = <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a>;</line>
<line>        if (!<a link="impl-shared.ELStateUsingAArch32.2" file="shared_pseudocode.xml" hover="function: boolean ELStateUsingAArch32(bits(2) el, boolean secure)">ELStateUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, accdesc.ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>) &amp;&amp;</line>
<line>                <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; HCR_EL2.DCT == '1') then</line>
<line>            memattrs.tags     = <a link="MemTag_AllocationTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_AllocationTagged</a>;</line>
<line>        else</line>
<line>            memattrs.tags     = <a link="MemTag_Untagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_Untagged</a>;</line>
<line>        memattrs.xs           = '0';</line>
<line>    elsif accdesc.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> then</line>
<line>        memattrs.memtype      = <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>;</line>
<line>        memattrs.shareability = <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a>;</line>
<line>        memattrs.tags         = <a link="MemTag_Untagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_Untagged</a>;</line>
<line>        if <a link="AArch32.S1ICacheEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch32.S1ICacheEnabled(Regime regime)">AArch32.S1ICacheEnabled</a>(regime) then</line>
<line>            memattrs.inner.attrs = <a link="MemAttr_WT" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WT = '10'">MemAttr_WT</a>;</line>
<line>            memattrs.inner.hints = <a link="MemHint_RA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RA = '10'">MemHint_RA</a>;</line>
<line>            memattrs.outer.attrs = <a link="MemAttr_WT" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WT = '10'">MemAttr_WT</a>;</line>
<line>            memattrs.outer.hints = <a link="MemHint_RA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RA = '10'">MemHint_RA</a>;</line>
<line>        else</line>
<line>            memattrs.inner.attrs = <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a>;</line>
<line>            memattrs.outer.attrs = <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a>;</line>
<line>        memattrs.xs           = '1';</line>
<line>    else</line>
<line>        // Treat memory region as Device</line>
<line>        memattrs.memtype      = <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a>;</line>
<line>        memattrs.device       = <a link="DeviceType_nGnRnE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGnRnE</a>;</line>
<line>        memattrs.shareability = <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a>;</line>
<line>        memattrs.tags         = <a link="MemTag_Untagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_Untagged</a>;</line>
<line>        memattrs.xs           = '1';</line>
<line></line>
<line>    bit ntlsmd;</line>
<line>    if <a link="impl-shared.HaveTrapLoadStoreMultipleDeviceExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTrapLoadStoreMultipleDeviceExt()">HaveTrapLoadStoreMultipleDeviceExt</a>() then</line>
<line>        case regime of</line>
<line>            when <a link="Regime_EL30" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL30</a> ntlsmd = SCTLR_S.nTLSMD;</line>
<line>            when <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>  ntlsmd = HSCTLR.nTLSMD;</line>
<line>            when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> ntlsmd = if <a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then SCTLR_NS.nTLSMD else SCTLR.nTLSMD;</line>
<line>    else</line>
<line>        ntlsmd = '1';</line>
<line></line>
<line>    if <a link="AArch32.S1HasAlignmentFault.4" file="shared_pseudocode.xml" hover="function: boolean AArch32.S1HasAlignmentFault(AccessDescriptor accdesc, boolean aligned, bit ntlsmd, MemoryAttributes memattrs)">AArch32.S1HasAlignmentFault</a>(accdesc, aligned, ntlsmd, memattrs) then</line>
<line>        fault.statuscode  = <a link="Fault_Alignment" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Alignment</a>;</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN);</line>
<line></line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> oa;</line>
<line>    oa.address = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(va, 56);</line>
<line>    oa.paspace = if accdesc.ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a> else <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line>    ipa = <a link="impl-shared.CreateAddressDescriptor.3" file="shared_pseudocode.xml" hover="function: AddressDescriptor CreateAddressDescriptor(bits(64) va, FullAddress pa, MemoryAttributes memattrs)">CreateAddressDescriptor</a>(<a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(va, 64), oa, memattrs);</line>
<line></line>
<line>    return (fault, ipa);</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/translation/AArch32.S1Enabled" mylink="aarch32.translation.translation.AArch32.S1Enabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.S1Enabled()</line>
<line>// ===================</line>
<line>// Returns whether stage 1 translation is enabled for the active translation regime</line>
<line></line>
<line link="AArch32.S1Enabled.2" hover="function: boolean AArch32.S1Enabled(Regime regime, SecurityState ss)" conts="AArch32.S1Enabled">boolean <anchor link="AArch32.S1Enabled.2" hover="function: boolean AArch32.S1Enabled(Regime regime, SecurityState ss)">AArch32.S1Enabled</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss)</line>
<line>    if regime == <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a> then</line>
<line>        return HSCTLR.M == '1';</line>
<line>    elsif regime == <a link="Regime_EL30" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL30</a> then</line>
<line>        return SCTLR_S.M == '1';</line>
<line>    elsif !<a link="AArch32.EL2Enabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch32.EL2Enabled(SecurityState ss)">AArch32.EL2Enabled</a>(ss) then</line>
<line>        return (if <a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then SCTLR_NS.M else SCTLR.M) == '1';</line>
<line>    elsif <a link="impl-shared.ELStateUsingAArch32.2" file="shared_pseudocode.xml" hover="function: boolean ELStateUsingAArch32(bits(2) el, boolean secure)">ELStateUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>) then</line>
<line>        return HCR.&lt;TGE,DC&gt; == '00' &amp;&amp; (if <a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then SCTLR_NS.M else SCTLR.M) == '1';</line>
<line>    else</line>
<line>        return HCR_EL2.&lt;TGE,DC&gt; == '00' &amp;&amp; SCTLR.M == '1';</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/translation/AArch32.S1TranslateLD" mylink="aarch32.translation.translation.AArch32.S1TranslateLD" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.S1TranslateLD()</line>
<line>// =======================</line>
<line>// Perform a stage 1 translation using long-descriptor format mapping VA to IPA/PA</line>
<line>// depending on the regime</line>
<line></line>
<line link="AArch32.S1TranslateLD.5" hover="function: (FaultRecord, AddressDescriptor) AArch32.S1TranslateLD(FaultRecord fault_in, Regime regime, bits(32) va, boolean aligned, AccessDescriptor accdesc)" conts="AArch32.S1TranslateLD">(FaultRecord, AddressDescriptor) <anchor link="AArch32.S1TranslateLD.5" hover="function: (FaultRecord, AddressDescriptor) AArch32.S1TranslateLD(FaultRecord fault_in, Regime regime, bits(32) va, boolean aligned, AccessDescriptor accdesc)">AArch32.S1TranslateLD</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault_in, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime,</line>
<line>                                                       bits(32) va, boolean aligned,</line>
<line>                                                       <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = fault_in;</line>
<line></line>
<line>    if !<a link="AArch32.S1Enabled.2" file="shared_pseudocode.xml" hover="function: boolean AArch32.S1Enabled(Regime regime, SecurityState ss)">AArch32.S1Enabled</a>(regime, accdesc.ss) then</line>
<line>        return <a link="AArch32.S1DisabledOutput.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, AddressDescriptor) AArch32.S1DisabledOutput(FaultRecord fault_in, Regime regime, bits(32) va, boolean aligned, AccessDescriptor accdesc)">AArch32.S1DisabledOutput</a>(fault, regime, va, aligned, accdesc);</line>
<line></line>
<line>    walkparams = AArch32.GetS1TTWParams(regime, va);</line>
<line></line>
<line>    if AArch32.VAIsOutOfRange(regime, walkparams, va) then</line>
<line>        fault.level      = 1;</line>
<line>        fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN);</line>
<line></line>
<line>    <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> walkstate;</line>
<line>    (fault, walkstate) = AArch32.S1WalkLD(fault, regime, walkparams, accdesc, va);</line>
<line></line>
<line>    if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN);</line>
<line></line>
<line>    SetInGuardedPage(FALSE);  // AArch32-VMSA does not guard any pages</line>
<line></line>
<line>    if <a link="AArch32.S1HasAlignmentFault.4" file="shared_pseudocode.xml" hover="function: boolean AArch32.S1HasAlignmentFault(AccessDescriptor accdesc, boolean aligned, bit ntlsmd, MemoryAttributes memattrs)">AArch32.S1HasAlignmentFault</a>(accdesc, aligned, walkparams.ntlsmd, walkstate.memattrs) then</line>
<line>        fault.statuscode = <a link="Fault_Alignment" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Alignment</a>;</line>
<line>    elsif AArch32.S1LDHasPermissionsFault(regime, walkparams,</line>
<line>                                          walkstate.permissions,</line>
<line>                                          walkstate.memattrs.memtype,</line>
<line>                                          walkstate.baseaddress.paspace,</line>
<line>                                          accdesc) then</line>
<line>        fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line></line>
<line>    if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN);</line>
<line></line>
<line>    <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs;</line>
<line>    if ((accdesc.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> &amp;&amp;</line>
<line>            (walkstate.memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> || !<a link="AArch32.S1ICacheEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch32.S1ICacheEnabled(Regime regime)">AArch32.S1ICacheEnabled</a>(regime))) ||</line>
<line>        (accdesc.acctype != <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> &amp;&amp;</line>
<line>             walkstate.memattrs.memtype == <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a> &amp;&amp; !<a link="AArch32.S1DCacheEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch32.S1DCacheEnabled(Regime regime)">AArch32.S1DCacheEnabled</a>(regime))) then</line>
<line>        // Treat memory attributes as Normal Non-Cacheable</line>
<line>        memattrs = <a link="impl-shared.NormalNCMemAttr.0" file="shared_pseudocode.xml" hover="function: MemoryAttributes NormalNCMemAttr()">NormalNCMemAttr</a>();</line>
<line>        memattrs.xs = walkstate.memattrs.xs;</line>
<line>    else</line>
<line>        memattrs = walkstate.memattrs;</line>
<line></line>
<line>    // Shareability value of stage 1 translation subject to stage 2 is IMPLEMENTATION DEFINED</line>
<line>    // to be either effective value or descriptor value</line>
<line>    if (regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; <a link="AArch32.EL2Enabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch32.EL2Enabled(SecurityState ss)">AArch32.EL2Enabled</a>(accdesc.ss) &amp;&amp;</line>
<line>        (if <a link="impl-shared.ELStateUsingAArch32.2" file="shared_pseudocode.xml" hover="function: boolean ELStateUsingAArch32(bits(2) el, boolean secure)">ELStateUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, accdesc.ss==<a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>) then HCR.VM else HCR_EL2.VM) == '1' &amp;&amp;</line>
<line>        !(boolean IMPLEMENTATION_DEFINED "Apply effective shareability at stage 1")) then</line>
<line>        memattrs.shareability = walkstate.memattrs.shareability;</line>
<line>    else</line>
<line>        memattrs.shareability = <a link="impl-shared.EffectiveShareability.1" file="shared_pseudocode.xml" hover="function: Shareability EffectiveShareability(MemoryAttributes memattrs)">EffectiveShareability</a>(memattrs);</line>
<line></line>
<line>    // Output Address</line>
<line>    oa = <a link="impl-shared.StageOA.4" file="shared_pseudocode.xml" hover="function: FullAddress StageOA(bits(64) ia, bit d128, TGx tgx, TTWState walkstate)">StageOA</a>(<a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(va, 64), walkparams.d128, walkparams.tgx, walkstate);</line>
<line>    ipa = <a link="impl-shared.CreateAddressDescriptor.3" file="shared_pseudocode.xml" hover="function: AddressDescriptor CreateAddressDescriptor(bits(64) va, FullAddress pa, MemoryAttributes memattrs)">CreateAddressDescriptor</a>(<a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(va, 64), oa, memattrs);</line>
<line></line>
<line>    return (fault, ipa);</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/translation/AArch32.S1TranslateSD" mylink="aarch32.translation.translation.AArch32.S1TranslateSD" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.S1TranslateSD()</line>
<line>// =======================</line>
<line>// Perform a stage 1 translation using short-descriptor format mapping VA to IPA/PA</line>
<line>// depending on the regime</line>
<line></line>
<line link="AArch32.S1TranslateSD.5" hover="function: (FaultRecord, AddressDescriptor, SDFType) AArch32.S1TranslateSD(FaultRecord fault_in, Regime regime, bits(32) va, boolean aligned, AccessDescriptor accdesc)" conts="AArch32.S1TranslateSD">(FaultRecord, AddressDescriptor, SDFType) <anchor link="AArch32.S1TranslateSD.5" hover="function: (FaultRecord, AddressDescriptor, SDFType) AArch32.S1TranslateSD(FaultRecord fault_in, Regime regime, bits(32) va, boolean aligned, AccessDescriptor accdesc)">AArch32.S1TranslateSD</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault_in, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime,</line>
<line>                                                                bits(32) va, boolean aligned,</line>
<line>                                                                <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line></line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = fault_in;</line>
<line></line>
<line>    if !<a link="AArch32.S1Enabled.2" file="shared_pseudocode.xml" hover="function: boolean AArch32.S1Enabled(Regime regime, SecurityState ss)">AArch32.S1Enabled</a>(regime, accdesc.ss) then</line>
<line>        <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> ipa;</line>
<line>        (fault, ipa) = <a link="AArch32.S1DisabledOutput.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, AddressDescriptor) AArch32.S1DisabledOutput(FaultRecord fault_in, Regime regime, bits(32) va, boolean aligned, AccessDescriptor accdesc)">AArch32.S1DisabledOutput</a>(fault, regime, va, aligned, accdesc);</line>
<line>        return (fault, ipa, <a link="SDFType" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType</a> UNKNOWN);</line>
<line></line>
<line>    <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> walkstate;</line>
<line>    (fault, walkstate) = <a link="AArch32.S1WalkSD.4" file="shared_pseudocode.xml" hover="function: (FaultRecord, TTWState) AArch32.S1WalkSD(FaultRecord fault_in, Regime regime, AccessDescriptor accdesc, bits(32) va)">AArch32.S1WalkSD</a>(fault, regime, accdesc, va);</line>
<line></line>
<line>    if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN, <a link="SDFType" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType</a> UNKNOWN);</line>
<line></line>
<line>    domain = <a link="AArch32.OutputDomain.2" file="shared_pseudocode.xml" hover="function: bits(2) AArch32.OutputDomain(Regime regime, bits(4) domain)">AArch32.OutputDomain</a>(regime, walkstate.domain);</line>
<line>    SetInGuardedPage(FALSE);  // AArch32-VMSA does not guard any pages</line>
<line></line>
<line>    bit ntlsmd;</line>
<line>    if <a link="impl-shared.HaveTrapLoadStoreMultipleDeviceExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTrapLoadStoreMultipleDeviceExt()">HaveTrapLoadStoreMultipleDeviceExt</a>() then</line>
<line>        case regime of</line>
<line>            when <a link="Regime_EL30" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL30</a> ntlsmd = SCTLR_S.nTLSMD;</line>
<line>            when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> ntlsmd = if <a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then SCTLR_NS.nTLSMD else SCTLR.nTLSMD;</line>
<line>    else</line>
<line>        ntlsmd = '1';</line>
<line></line>
<line>    if <a link="AArch32.S1HasAlignmentFault.4" file="shared_pseudocode.xml" hover="function: boolean AArch32.S1HasAlignmentFault(AccessDescriptor accdesc, boolean aligned, bit ntlsmd, MemoryAttributes memattrs)">AArch32.S1HasAlignmentFault</a>(accdesc, aligned, ntlsmd, walkstate.memattrs) then</line>
<line>        fault.statuscode = <a link="Fault_Alignment" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Alignment</a>;</line>
<line>    elsif (!(accdesc.acctype IN {<a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a>, <a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>}) &amp;&amp;</line>
<line>            domain == <a link="Domain_NoAccess" file="shared_pseudocode.xml" hover="constant bits(2) Domain_NoAccess = '00'">Domain_NoAccess</a>) then</line>
<line>        fault.statuscode = <a link="Fault_Domain" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Domain</a>;</line>
<line>    elsif domain == <a link="Domain_Client" file="shared_pseudocode.xml" hover="constant bits(2) Domain_Client = '01'">Domain_Client</a> then</line>
<line>        if <a link="AArch32.S1SDHasPermissionsFault.5" file="shared_pseudocode.xml" hover="function: boolean AArch32.S1SDHasPermissionsFault(Regime regime, Permissions perms_in, MemType memtype, PASpace paspace, AccessDescriptor accdesc)">AArch32.S1SDHasPermissionsFault</a>(regime, walkstate.permissions,</line>
<line>                                           walkstate.memattrs.memtype,</line>
<line>                                           walkstate.baseaddress.paspace,</line>
<line>                                           accdesc) then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line></line>
<line>    if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>        fault.domain = walkstate.domain;</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN, walkstate.sdftype);</line>
<line></line>
<line>    <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs;</line>
<line>    if ((accdesc.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> &amp;&amp;</line>
<line>            (walkstate.memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> || !<a link="AArch32.S1ICacheEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch32.S1ICacheEnabled(Regime regime)">AArch32.S1ICacheEnabled</a>(regime))) ||</line>
<line>        (accdesc.acctype != <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> &amp;&amp;</line>
<line>             walkstate.memattrs.memtype == <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a> &amp;&amp; !<a link="AArch32.S1DCacheEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch32.S1DCacheEnabled(Regime regime)">AArch32.S1DCacheEnabled</a>(regime))) then</line>
<line>        // Treat memory attributes as Normal Non-Cacheable</line>
<line>        memattrs = <a link="impl-shared.NormalNCMemAttr.0" file="shared_pseudocode.xml" hover="function: MemoryAttributes NormalNCMemAttr()">NormalNCMemAttr</a>();</line>
<line>        memattrs.xs = walkstate.memattrs.xs;</line>
<line>    else</line>
<line>        memattrs = walkstate.memattrs;</line>
<line></line>
<line>    // Shareability value of stage 1 translation subject to stage 2 is IMPLEMENTATION DEFINED</line>
<line>    // to be either effective value or descriptor value</line>
<line>    if (regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; <a link="AArch32.EL2Enabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch32.EL2Enabled(SecurityState ss)">AArch32.EL2Enabled</a>(accdesc.ss) &amp;&amp;</line>
<line>        (if <a link="impl-shared.ELStateUsingAArch32.2" file="shared_pseudocode.xml" hover="function: boolean ELStateUsingAArch32(bits(2) el, boolean secure)">ELStateUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, accdesc.ss==<a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>) then HCR.VM else HCR_EL2.VM) == '1' &amp;&amp;</line>
<line>        !(boolean IMPLEMENTATION_DEFINED "Apply effective shareability at stage 1")) then</line>
<line>        memattrs.shareability = walkstate.memattrs.shareability;</line>
<line>    else</line>
<line>        memattrs.shareability = <a link="impl-shared.EffectiveShareability.1" file="shared_pseudocode.xml" hover="function: Shareability EffectiveShareability(MemoryAttributes memattrs)">EffectiveShareability</a>(memattrs);</line>
<line></line>
<line>    // Output Address</line>
<line>    oa = <a link="AArch32.SDStageOA.3" file="shared_pseudocode.xml" hover="function: FullAddress AArch32.SDStageOA(FullAddress baseaddress, bits(32) va, SDFType sdftype)">AArch32.SDStageOA</a>(walkstate.baseaddress, va, walkstate.sdftype);</line>
<line>    ipa = <a link="impl-shared.CreateAddressDescriptor.3" file="shared_pseudocode.xml" hover="function: AddressDescriptor CreateAddressDescriptor(bits(64) va, FullAddress pa, MemoryAttributes memattrs)">CreateAddressDescriptor</a>(<a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(va, 64), oa, memattrs);</line>
<line></line>
<line>    return (fault, ipa, walkstate.sdftype);</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/translation/AArch32.S2Translate" mylink="aarch32.translation.translation.AArch32.S2Translate" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.S2Translate()</line>
<line>// =====================</line>
<line>// Perform a stage 2 translation mapping an IPA to a PA</line>
<line></line>
<line link="AArch32.S2Translate.4" hover="function: (FaultRecord, AddressDescriptor) AArch32.S2Translate(FaultRecord fault_in, AddressDescriptor ipa, boolean aligned, AccessDescriptor accdesc)" conts="AArch32.S2Translate">(FaultRecord, AddressDescriptor) <anchor link="AArch32.S2Translate.4" hover="function: (FaultRecord, AddressDescriptor) AArch32.S2Translate(FaultRecord fault_in, AddressDescriptor ipa, boolean aligned, AccessDescriptor accdesc)">AArch32.S2Translate</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault_in, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> ipa,</line>
<line>                                                     boolean aligned, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line></line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = fault_in;</line>
<line>    assert <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(ipa.paddress.address&lt;55:40&gt;);</line>
<line></line>
<line>    if !<a link="impl-shared.ELStateUsingAArch32.2" file="shared_pseudocode.xml" hover="function: boolean ELStateUsingAArch32(bits(2) el, boolean secure)">ELStateUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, accdesc.ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>) then</line>
<line>        s1aarch64 = FALSE;</line>
<line>        return <a link="AArch64.S2Translate.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, AddressDescriptor) AArch64.S2Translate(FaultRecord fault_in, AddressDescriptor ipa, boolean s1aarch64, boolean aligned, AccessDescriptor accdesc)">AArch64.S2Translate</a>(fault, ipa, s1aarch64, aligned, accdesc);</line>
<line></line>
<line>    // Prepare fault fields in case a fault is detected</line>
<line>    fault.statuscode  = <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a>;</line>
<line>    fault.secondstage = TRUE;</line>
<line>    fault.s2fs1walk   = accdesc.acctype == <a link="AccessType_TTW" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_TTW</a>;</line>
<line>    fault.ipaddress   = ipa.paddress;</line>
<line></line>
<line>    walkparams = AArch32.GetS2TTWParams();</line>
<line></line>
<line>    if walkparams.vm == '0' then</line>
<line>        // Stage 2 is disabled</line>
<line>        return (fault, ipa);</line>
<line></line>
<line>    if AArch32.IPAIsOutOfRange(walkparams, ipa.paddress.address&lt;39:0&gt;) then</line>
<line>        fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>        fault.level      = 1;</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN);</line>
<line></line>
<line>    <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> walkstate;</line>
<line>    (fault, walkstate) = AArch32.S2Walk(fault, walkparams, accdesc, ipa);</line>
<line></line>
<line>    if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN);</line>
<line></line>
<line>    if <a link="AArch32.S2HasAlignmentFault.3" file="shared_pseudocode.xml" hover="function: boolean AArch32.S2HasAlignmentFault(AccessDescriptor accdesc, boolean aligned, MemoryAttributes memattrs)">AArch32.S2HasAlignmentFault</a>(accdesc, aligned, walkstate.memattrs) then</line>
<line>        fault.statuscode = <a link="Fault_Alignment" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Alignment</a>;</line>
<line>    elsif AArch32.S2HasPermissionsFault(walkparams,</line>
<line>                                        walkstate.permissions,</line>
<line>                                        walkstate.memattrs.memtype,</line>
<line>                                        accdesc) then</line>
<line>        fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>    <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> s2_memattrs;</line>
<line>    if ((accdesc.acctype == <a link="AccessType_TTW" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_TTW</a> &amp;&amp;</line>
<line>             walkstate.memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a>) ||</line>
<line>        (accdesc.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> &amp;&amp;</line>
<line>            (walkstate.memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> || HCR2.ID == '1')) ||</line>
<line>        (accdesc.acctype != <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> &amp;&amp;</line>
<line>             walkstate.memattrs.memtype == <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a> &amp;&amp; HCR2.CD == '1')) then</line>
<line>        // Treat memory attributes as Normal Non-Cacheable</line>
<line>        s2_memattrs = <a link="impl-shared.NormalNCMemAttr.0" file="shared_pseudocode.xml" hover="function: MemoryAttributes NormalNCMemAttr()">NormalNCMemAttr</a>();</line>
<line>        s2_memattrs.xs = walkstate.memattrs.xs;</line>
<line>    else</line>
<line>        s2_memattrs = walkstate.memattrs;</line>
<line></line>
<line>    s2aarch64 = FALSE;</line>
<line>    memattrs = <a link="impl-shared.S2CombineS1MemAttrs.3" file="shared_pseudocode.xml" hover="function: MemoryAttributes S2CombineS1MemAttrs(MemoryAttributes s1_memattrs, MemoryAttributes s2_memattrs, boolean s2aarch64)">S2CombineS1MemAttrs</a>(ipa.memattrs, s2_memattrs, s2aarch64);</line>
<line>    ipa_64 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(ipa.paddress.address&lt;39:0&gt;, 64);</line>
<line>    // Output Address</line>
<line>    oa = <a link="impl-shared.StageOA.4" file="shared_pseudocode.xml" hover="function: FullAddress StageOA(bits(64) ia, bit d128, TGx tgx, TTWState walkstate)">StageOA</a>(ipa_64, walkparams.d128, walkparams.tgx, walkstate);</line>
<line>    pa = <a link="impl-shared.CreateAddressDescriptor.3" file="shared_pseudocode.xml" hover="function: AddressDescriptor CreateAddressDescriptor(bits(64) va, FullAddress pa, MemoryAttributes memattrs)">CreateAddressDescriptor</a>(ipa.vaddress, oa, memattrs);</line>
<line></line>
<line>    return (fault, pa);</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/translation/AArch32.SDStageOA" mylink="aarch32.translation.translation.AArch32.SDStageOA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.SDStageOA()</line>
<line>// ===================</line>
<line>// Given the final walk state of a short-descriptor translation walk,</line>
<line>// map the untranslated input address bits to the base output address</line>
<line></line>
<line link="AArch32.SDStageOA.3" hover="function: FullAddress AArch32.SDStageOA(FullAddress baseaddress, bits(32) va, SDFType sdftype)" conts="AArch32.SDStageOA">FullAddress <anchor link="AArch32.SDStageOA.3" hover="function: FullAddress AArch32.SDStageOA(FullAddress baseaddress, bits(32) va, SDFType sdftype)">AArch32.SDStageOA</anchor>(<a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> baseaddress, bits(32) va, <a link="SDFType" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType</a> sdftype)</line>
<line>    integer tsize;</line>
<line>    case sdftype of</line>
<line>        when <a link="SDFType_SmallPage" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_SmallPage</a>      tsize = 12;</line>
<line>        when <a link="SDFType_LargePage" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_LargePage</a>      tsize = 16;</line>
<line>        when <a link="SDFType_Section" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_Section</a>        tsize = 20;</line>
<line>        when <a link="SDFType_Supersection" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_Supersection</a>   tsize = 24;</line>
<line></line>
<line>    // Output Address</line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> oa;</line>
<line>    oa.address = baseaddress.address&lt;55:tsize&gt;:va&lt;tsize-1:0&gt;;</line>
<line>    oa.paspace = baseaddress.paspace;</line>
<line>    return oa;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/translation/AArch32.TranslateAddress" mylink="aarch32.translation.translation.AArch32.TranslateAddress" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TranslateAddress()</line>
<line>// ==========================</line>
<line>// Main entry point for translating an address</line>
<line></line>
<line link="AArch32.TranslateAddress.4" hover="function: AddressDescriptor AArch32.TranslateAddress(bits(32) va, AccessDescriptor accdesc, boolean aligned, integer size)" conts="AArch32.TranslateAddress">AddressDescriptor <anchor link="AArch32.TranslateAddress.4" hover="function: AddressDescriptor AArch32.TranslateAddress(bits(32) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch32.TranslateAddress</anchor>(bits(32) va, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc,</line>
<line>                                           boolean aligned, integer size)</line>
<line></line>
<line>    <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime = <a link="impl-shared.TranslationRegime.1" file="shared_pseudocode.xml" hover="function: Regime TranslationRegime(bits(2) el)">TranslationRegime</a>(PSTATE.EL);</line>
<line>    if !<a link="impl-shared.RegimeUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean RegimeUsingAArch32(Regime regime)">RegimeUsingAArch32</a>(regime) then</line>
<line>        return <a link="AArch64.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch64.TranslateAddress(bits(64) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch64.TranslateAddress</a>(<a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(va, 64), accdesc, aligned, size);</line>
<line></line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> result = <a link="AArch32.FullTranslate.3" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch32.FullTranslate(bits(32) va, AccessDescriptor accdesc, boolean aligned)">AArch32.FullTranslate</a>(va, accdesc, aligned);</line>
<line></line>
<line>    if !<a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(result) then</line>
<line>        result.fault = <a link="AArch32.CheckDebug.3" file="shared_pseudocode.xml" hover="function: FaultRecord AArch32.CheckDebug(bits(32) vaddress, AccessDescriptor accdesc, integer size)">AArch32.CheckDebug</a>(va, accdesc, size);</line>
<line></line>
<line>    // Update virtual address for abort functions</line>
<line>    result.vaddress = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(va, 64);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/walk/AArch32.DecodeDescriptorTypeLD" mylink="aarch32.translation.walk.AArch32.DecodeDescriptorTypeLD" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.DecodeDescriptorTypeLD()</line>
<line>// ================================</line>
<line>// Determine whether the long-descriptor is a page, block or table</line>
<line></line>
<line link="AArch32.DecodeDescriptorTypeLD.2" hover="function: DescriptorType AArch32.DecodeDescriptorTypeLD(bits(64) descriptor, integer level)" conts="AArch32.DecodeDescriptorTypeLD">DescriptorType <anchor link="AArch32.DecodeDescriptorTypeLD.2" hover="function: DescriptorType AArch32.DecodeDescriptorTypeLD(bits(64) descriptor, integer level)">AArch32.DecodeDescriptorTypeLD</anchor>(bits(64) descriptor, integer level)</line>
<line>    if descriptor&lt;1:0&gt; == '11' &amp;&amp; level == <a link="FINAL_LEVEL" file="shared_pseudocode.xml" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</a> then</line>
<line>        return <a link="DescriptorType_Leaf" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Leaf</a>;</line>
<line>    elsif descriptor&lt;1:0&gt; == '11' then</line>
<line>        return <a link="DescriptorType_Table" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Table</a>;</line>
<line>    elsif descriptor&lt;1:0&gt; == '01' &amp;&amp; level != <a link="FINAL_LEVEL" file="shared_pseudocode.xml" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</a> then</line>
<line>        return <a link="DescriptorType_Leaf" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Leaf</a>;</line>
<line>    else</line>
<line>        return <a link="DescriptorType_Invalid" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Invalid</a>;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/walk/AArch32.DecodeDescriptorTypeSD" mylink="aarch32.translation.walk.AArch32.DecodeDescriptorTypeSD" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.DecodeDescriptorTypeSD()</line>
<line>// ================================</line>
<line>// Determine the type of the short-descriptor</line>
<line></line>
<line link="AArch32.DecodeDescriptorTypeSD.2" hover="function: SDFType AArch32.DecodeDescriptorTypeSD(bits(32) descriptor, integer level)" conts="AArch32.DecodeDescriptorTypeSD">SDFType <anchor link="AArch32.DecodeDescriptorTypeSD.2" hover="function: SDFType AArch32.DecodeDescriptorTypeSD(bits(32) descriptor, integer level)">AArch32.DecodeDescriptorTypeSD</anchor>(bits(32) descriptor, integer level)</line>
<line>    if level == 1 &amp;&amp; descriptor&lt;1:0&gt; == '01' then</line>
<line>        return <a link="SDFType_Table" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_Table</a>;</line>
<line>    elsif level == 1 &amp;&amp; descriptor&lt;18,1&gt; == '01' then</line>
<line>        return <a link="SDFType_Section" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_Section</a>;</line>
<line>    elsif level == 1 &amp;&amp; descriptor&lt;18,1&gt; == '11' then</line>
<line>        return <a link="SDFType_Supersection" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_Supersection</a>;</line>
<line>    elsif level == 2 &amp;&amp; descriptor&lt;1:0&gt; == '01' then</line>
<line>        return <a link="SDFType_LargePage" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_LargePage</a>;</line>
<line>    elsif level == 2 &amp;&amp; descriptor&lt;1:0&gt; IN {'1x'} then</line>
<line>        return <a link="SDFType_SmallPage" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_SmallPage</a>;</line>
<line>    else</line>
<line>        return <a link="SDFType_Invalid" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_Invalid</a>;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/walk/AArch32.S1IASize" mylink="aarch32.translation.walk.AArch32.S1IASize" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.S1IASize()</line>
<line>// ==================</line>
<line>// Retrieve the number of bits containing the input address for stage 1 translation</line>
<line></line>
<line link="AArch32.S1IASize.1" hover="function: integer AArch32.S1IASize(bits(3) txsz)" conts="AArch32.S1IASize">integer <anchor link="AArch32.S1IASize.1" hover="function: integer AArch32.S1IASize(bits(3) txsz)">AArch32.S1IASize</anchor>(bits(3) txsz)</line>
<line>    return 32 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(txsz);</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/walk/AArch32.S1WalkLD" mylink="aarch32.translation.walk.AArch32.S1WalkLD" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.S1WalkLD()</line>
<line>// ==================</line>
<line>// Traverse stage 1 translation tables in long format to obtain the final descriptor</line>
<line></line>
<line>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a>, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a>) AArch32.S1WalkLD(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault_in, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime,</line>
<line>                                         S1TTWParams walkparams, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc,</line>
<line>                                         bits(32) va)</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = fault_in;</line>
<line>    bits(3) txsz;</line>
<line>    bits(64) ttbr;</line>
<line>    bit epd;</line>
<line>    <a link="VARange" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange</a> varange;</line>
<line>    if regime == <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a> then</line>
<line>        ttbr = HTTBR;</line>
<line>        txsz = walkparams.t0sz;</line>
<line>        varange = <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a>;</line>
<line>    else</line>
<line>        varange = <a link="AArch32.GetVARange.3" file="shared_pseudocode.xml" hover="function: VARange AArch32.GetVARange(bits(32) va, bits(3) t0sz, bits(3) t1sz)">AArch32.GetVARange</a>(va, walkparams.t0sz, walkparams.t1sz);</line>
<line>        bits(64) ttbr0;</line>
<line>        bits(64) ttbr1;</line>
<line>        TTBCR_Type ttbcr;</line>
<line>        if regime == <a link="Regime_EL30" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL30</a> then</line>
<line>            ttbcr = TTBCR_S;</line>
<line>            ttbr0 = TTBR0_S;</line>
<line>            ttbr1 = TTBR1_S;</line>
<line>        elsif <a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>            ttbcr = TTBCR_NS;</line>
<line>            ttbr0 = TTBR0_NS;</line>
<line>            ttbr1 = TTBR1_NS;</line>
<line>        else</line>
<line>            ttbcr = TTBCR;</line>
<line>            ttbr0 = TTBR0;</line>
<line>            ttbr1 = TTBR1;</line>
<line></line>
<line>        assert ttbcr.EAE == '1';</line>
<line>        if varange == <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a> then</line>
<line>            txsz = walkparams.t0sz;</line>
<line>            ttbr = ttbr0;</line>
<line>            epd  = ttbcr.EPD0;</line>
<line>        else</line>
<line>            txsz = walkparams.t1sz;</line>
<line>            ttbr = ttbr1;</line>
<line>            epd  = ttbcr.EPD1;</line>
<line></line>
<line>    if regime != <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a> &amp;&amp; epd == '1' then</line>
<line>        fault.level      = 1;</line>
<line>        fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>        return (fault, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN);</line>
<line></line>
<line>    // Input Address size</line>
<line>    iasize      = <a link="AArch32.S1IASize.1" file="shared_pseudocode.xml" hover="function: integer AArch32.S1IASize(bits(3) txsz)">AArch32.S1IASize</a>(txsz);</line>
<line>    granulebits = <a link="impl-shared.TGxGranuleBits.1" file="shared_pseudocode.xml" hover="function: integer TGxGranuleBits(TGx tgx)">TGxGranuleBits</a>(walkparams.tgx);</line>
<line>    stride      = granulebits - 3;</line>
<line>    startlevel  = <a link="FINAL_LEVEL" file="shared_pseudocode.xml" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</a> - (((iasize-1) - granulebits) DIV stride);</line>
<line>    levels      = <a link="FINAL_LEVEL" file="shared_pseudocode.xml" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</a> - startlevel;</line>
<line></line>
<line>    if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(ttbr&lt;47:40&gt;) then</line>
<line>        fault.statuscode = <a link="Fault_AddressSize" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AddressSize</a>;</line>
<line>        fault.level      = 0;</line>
<line>        return (fault, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN);</line>
<line></line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> baseaddress;</line>
<line>    baselsb = (iasize - (levels*stride + granulebits)) + 3;</line>
<line>    baseaddress.paspace = if accdesc.ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a> else <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line>    baseaddress.address = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(ttbr&lt;39:baselsb&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(baselsb), 56);</line>
<line></line>
<line>    <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> walkstate;</line>
<line>    walkstate.baseaddress = baseaddress;</line>
<line>    walkstate.level       = startlevel;</line>
<line>    walkstate.istable     = TRUE;</line>
<line>    // In regimes that support global and non-global translations, translation</line>
<line>    // table entries from lookup levels other than the final level of lookup</line>
<line>    // are treated as being non-global</line>
<line>    walkstate.nG          = if <a link="impl-shared.HasUnprivileged.1" file="shared_pseudocode.xml" hover="function: boolean HasUnprivileged(Regime regime)">HasUnprivileged</a>(regime) then '1' else '0';</line>
<line>    walkstate.memattrs    = <a link="impl-shared.WalkMemAttrs.3" file="shared_pseudocode.xml" hover="function: MemoryAttributes WalkMemAttrs(bits(2) sh, bits(2) irgn, bits(2) orgn)">WalkMemAttrs</a>(walkparams.sh, walkparams.irgn, walkparams.orgn);</line>
<line>    walkstate.permissions.ap_table  = '00';</line>
<line>    walkstate.permissions.xn_table  = '0';</line>
<line>    walkstate.permissions.pxn_table = '0';</line>
<line></line>
<line>    indexmsb = iasize - 1;</line>
<line>    bits(64) descriptor;</line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> walkaddress;</line>
<line></line>
<line>    walkaddress.vaddress = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(va, 64);</line>
<line></line>
<line>    if !<a link="AArch32.S1DCacheEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch32.S1DCacheEnabled(Regime regime)">AArch32.S1DCacheEnabled</a>(regime) then</line>
<line>        walkaddress.memattrs = <a link="impl-shared.NormalNCMemAttr.0" file="shared_pseudocode.xml" hover="function: MemoryAttributes NormalNCMemAttr()">NormalNCMemAttr</a>();</line>
<line>        walkaddress.memattrs.xs = walkstate.memattrs.xs;</line>
<line>    else</line>
<line>        walkaddress.memattrs = walkstate.memattrs;</line>
<line></line>
<line>    // Shareability value of stage 1 translation subject to stage 2 is IMPLEMENTATION DEFINED</line>
<line>    // to be either effective value or descriptor value</line>
<line>    if (regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; <a link="AArch32.EL2Enabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch32.EL2Enabled(SecurityState ss)">AArch32.EL2Enabled</a>(accdesc.ss) &amp;&amp;</line>
<line>        (if <a link="impl-shared.ELStateUsingAArch32.2" file="shared_pseudocode.xml" hover="function: boolean ELStateUsingAArch32(bits(2) el, boolean secure)">ELStateUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, accdesc.ss==<a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>) then HCR.VM else HCR_EL2.VM) == '1' &amp;&amp;</line>
<line>        !(boolean IMPLEMENTATION_DEFINED "Apply effective shareability at stage 1")) then</line>
<line>        walkaddress.memattrs.shareability = walkstate.memattrs.shareability;</line>
<line>    else</line>
<line>        walkaddress.memattrs.shareability = <a link="impl-shared.EffectiveShareability.1" file="shared_pseudocode.xml" hover="function: Shareability EffectiveShareability(MemoryAttributes memattrs)">EffectiveShareability</a>(walkaddress.memattrs);</line>
<line></line>
<line>    integer indexlsb;</line>
<line>    <a link="DescriptorType" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType</a> desctype;</line>
<line>    repeat</line>
<line>        fault.level = walkstate.level;</line>
<line>        indexlsb = (<a link="FINAL_LEVEL" file="shared_pseudocode.xml" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</a> - walkstate.level)*stride + granulebits;</line>
<line>        bits(40) index = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(va&lt;indexmsb:indexlsb&gt;:'000', 40);</line>
<line></line>
<line>        walkaddress.paddress.address = walkstate.baseaddress.address OR <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(index, 56);</line>
<line>        walkaddress.paddress.paspace = walkstate.baseaddress.paspace;</line>
<line></line>
<line>        boolean toplevel = walkstate.level == startlevel;</line>
<line>        <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> walkaccess = <a link="impl-shared.CreateAccDescS1TTW.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescS1TTW(boolean toplevel, VARange varange, AccessDescriptor accdesc_in)">CreateAccDescS1TTW</a>(toplevel, varange, accdesc);</line>
<line>        // If there are two stages of translation, then the first stage table walk addresses</line>
<line>        // are themselves subject to translation</line>
<line>        if regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; <a link="AArch32.EL2Enabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch32.EL2Enabled(SecurityState ss)">AArch32.EL2Enabled</a>(accdesc.ss) then</line>
<line>            s2aligned = TRUE;</line>
<line>            (s2fault, s2walkaddress) = <a link="AArch32.S2Translate.4" file="shared_pseudocode.xml" hover="function: (FaultRecord, AddressDescriptor) AArch32.S2Translate(FaultRecord fault_in, AddressDescriptor ipa, boolean aligned, AccessDescriptor accdesc)">AArch32.S2Translate</a>(fault, walkaddress, s2aligned,</line>
<line>                                                           walkaccess);</line>
<line>            // Check for a fault on the stage 2 walk</line>
<line>            if s2fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>                return (s2fault, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN);</line>
<line></line>
<line>            (fault, descriptor) = <a link="impl-shared.FetchDescriptor.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, bits(N)) FetchDescriptor(bit ee, AddressDescriptor walkaddress, AccessDescriptor walkaccess, FaultRecord fault_in, integer N)">FetchDescriptor</a>(walkparams.ee, s2walkaddress, walkaccess,</line>
<line>                                                  fault, 64);</line>
<line>        else</line>
<line>            (fault, descriptor) = <a link="impl-shared.FetchDescriptor.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, bits(N)) FetchDescriptor(bit ee, AddressDescriptor walkaddress, AccessDescriptor walkaccess, FaultRecord fault_in, integer N)">FetchDescriptor</a>(walkparams.ee, walkaddress, walkaccess,</line>
<line>                                                  fault, 64);</line>
<line></line>
<line>        if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>            return (fault, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN);</line>
<line></line>
<line>        desctype = <a link="AArch32.DecodeDescriptorTypeLD.2" file="shared_pseudocode.xml" hover="function: DescriptorType AArch32.DecodeDescriptorTypeLD(bits(64) descriptor, integer level)">AArch32.DecodeDescriptorTypeLD</a>(descriptor, walkstate.level);</line>
<line></line>
<line>        case desctype of</line>
<line>            when <a link="DescriptorType_Table" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Table</a></line>
<line>                if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(descriptor&lt;47:40&gt;) then</line>
<line>                    fault.statuscode = <a link="Fault_AddressSize" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AddressSize</a>;</line>
<line>                    return (fault, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN);</line>
<line></line>
<line>                walkstate.baseaddress.address = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(descriptor&lt;39:12&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12), 56);</line>
<line>                if walkstate.baseaddress.paspace == <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a> &amp;&amp; descriptor&lt;63&gt; == '1' then</line>
<line>                    walkstate.baseaddress.paspace = <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line></line>
<line>                if walkparams.hpd == '0' then</line>
<line>                    walkstate.permissions.xn_table  = (walkstate.permissions.xn_table  OR</line>
<line>                                                        descriptor&lt;60&gt;);</line>
<line>                    walkstate.permissions.ap_table  = (walkstate.permissions.ap_table  OR</line>
<line>                                                        descriptor&lt;62:61&gt;);</line>
<line>                    walkstate.permissions.pxn_table = (walkstate.permissions.pxn_table OR</line>
<line>                                                        descriptor&lt;59&gt;);</line>
<line></line>
<line>                walkstate.level = walkstate.level + 1;</line>
<line>                indexmsb = indexlsb - 1;</line>
<line></line>
<line>            when <a link="DescriptorType_Invalid" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Invalid</a></line>
<line>                fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>                return (fault, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN);</line>
<line></line>
<line>            when <a link="DescriptorType_Leaf" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Leaf</a></line>
<line>                walkstate.istable = FALSE;</line>
<line></line>
<line>    until desctype == <a link="DescriptorType_Leaf" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Leaf</a>;</line>
<line></line>
<line>    // Check the output address is inside the supported range</line>
<line>    if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(descriptor&lt;47:40&gt;) then</line>
<line>        fault.statuscode = <a link="Fault_AddressSize" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AddressSize</a>;</line>
<line>        return (fault, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN);</line>
<line></line>
<line>    // Check the access flag</line>
<line>    if descriptor&lt;10&gt; == '0' then</line>
<line>        fault.statuscode = <a link="Fault_AccessFlag" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AccessFlag</a>;</line>
<line>        return (fault, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN);</line>
<line></line>
<line>    walkstate.permissions.xn  = descriptor&lt;54&gt;;</line>
<line>    walkstate.permissions.pxn = descriptor&lt;53&gt;;</line>
<line>    walkstate.permissions.ap  = descriptor&lt;7:6&gt;:'1';</line>
<line>    walkstate.contiguous      = descriptor&lt;52&gt;;</line>
<line>    if regime == <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a> then</line>
<line>        // All EL2 regime accesses are treated as Global</line>
<line>        walkstate.nG = '0';</line>
<line>    elsif accdesc.ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> &amp;&amp; walkstate.baseaddress.paspace == <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a> then</line>
<line>        // When a PE is using the Long-descriptor translation table format,</line>
<line>        // and is in Secure state, a translation must be treated as non-global,</line>
<line>        // regardless of the value of the nG bit,</line>
<line>        // if NSTable is set to 1 at any level of the translation table walk.</line>
<line>        walkstate.nG = '1';</line>
<line>    else</line>
<line>        walkstate.nG = descriptor&lt;11&gt;;</line>
<line></line>
<line>    walkstate.baseaddress.address = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(descriptor&lt;39:indexlsb&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(indexlsb), 56);</line>
<line>    if walkstate.baseaddress.paspace == <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a> &amp;&amp; descriptor&lt;5&gt; == '1' then</line>
<line>        walkstate.baseaddress.paspace = <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line></line>
<line>    memattr = descriptor&lt;4:2&gt;;</line>
<line>    sh      = descriptor&lt;9:8&gt;;</line>
<line>    attr    = AArch32.MAIRAttr(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(memattr), walkparams.mair);</line>
<line>    s1aarch64 = FALSE;</line>
<line>    walkstate.memattrs = S1DecodeMemAttrs(attr, sh, s1aarch64, walkparams);</line>
<line></line>
<line>    return (fault, walkstate);</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/walk/AArch32.S1WalkSD" mylink="aarch32.translation.walk.AArch32.S1WalkSD" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.S1WalkSD()</line>
<line>// ==================</line>
<line>// Traverse stage 1 translation tables in short format to obtain the final descriptor</line>
<line></line>
<line link="AArch32.S1WalkSD.4" hover="function: (FaultRecord, TTWState) AArch32.S1WalkSD(FaultRecord fault_in, Regime regime, AccessDescriptor accdesc, bits(32) va)" conts="AArch32.S1WalkSD">(FaultRecord, TTWState) <anchor link="AArch32.S1WalkSD.4" hover="function: (FaultRecord, TTWState) AArch32.S1WalkSD(FaultRecord fault_in, Regime regime, AccessDescriptor accdesc, bits(32) va)">AArch32.S1WalkSD</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault_in, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime,</line>
<line>                                         <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, bits(32) va)</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = fault_in;</line>
<line>    SCTLR_Type sctlr;</line>
<line>    TTBCR_Type ttbcr;</line>
<line>    TTBR0_Type ttbr0;</line>
<line>    TTBR1_Type ttbr1;</line>
<line>    // Determine correct translation control registers to use.</line>
<line>    if regime == <a link="Regime_EL30" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL30</a> then</line>
<line>        sctlr = SCTLR_S;</line>
<line>        ttbcr = TTBCR_S;</line>
<line>        ttbr0 = TTBR0_S;</line>
<line>        ttbr1 = TTBR1_S;</line>
<line>    elsif <a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        sctlr = SCTLR_NS;</line>
<line>        ttbcr = TTBCR_NS;</line>
<line>        ttbr0 = TTBR0_NS;</line>
<line>        ttbr1 = TTBR1_NS;</line>
<line>    else</line>
<line>        sctlr = SCTLR;</line>
<line>        ttbcr = TTBCR;</line>
<line>        ttbr0 = TTBR0;</line>
<line>        ttbr1 = TTBR1;</line>
<line></line>
<line>    assert ttbcr.EAE == '0';</line>
<line>    ee  = sctlr.EE;</line>
<line>    afe = sctlr.AFE;</line>
<line>    tre = sctlr.TRE;</line>
<line>    n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(ttbcr.N);</line>
<line>    bits(32) ttb;</line>
<line>    bits(1) pd;</line>
<line>    bits(2) irgn;</line>
<line>    bits(2) rgn;</line>
<line>    bits(1) s;</line>
<line>    bits(1) nos;</line>
<line>    <a link="VARange" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange</a> varange;</line>
<line>    if n == 0 || <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(va&lt;31:(32-n)&gt;) then</line>
<line>        ttb  = ttbr0.TTB0:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(7);</line>
<line>        pd   = ttbcr.PD0;</line>
<line>        irgn = ttbr0.IRGN;</line>
<line>        rgn  = ttbr0.RGN;</line>
<line>        s    = ttbr0.S;</line>
<line>        nos  = ttbr0.NOS;</line>
<line>        varange = <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a>;</line>
<line>    else</line>
<line>        n    = 0;  // TTBR1 translation always treats N as 0</line>
<line>        ttb  = ttbr1.TTB1:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(7);</line>
<line>        pd   = ttbcr.PD1;</line>
<line>        irgn = ttbr1.IRGN;</line>
<line>        rgn  = ttbr1.RGN;</line>
<line>        s    = ttbr1.S;</line>
<line>        nos  = ttbr1.NOS;</line>
<line>        varange = <a link="VARange_UPPER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_UPPER</a>;</line>
<line></line>
<line>    // Check if Translation table walk disabled for translations with this Base register.</line>
<line>    if pd == '1' then</line>
<line>        fault.level      = 1;</line>
<line>        fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>        return (fault, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN);</line>
<line></line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> baseaddress;</line>
<line>    baseaddress.paspace = if accdesc.ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a> else <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line>    baseaddress.address = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(ttb&lt;31:14-n&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(14-n), 56);</line>
<line></line>
<line>    constant integer startlevel = 1;</line>
<line>    <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> walkstate;</line>
<line>    walkstate.baseaddress = baseaddress;</line>
<line>    // In regimes that support global and non-global translations, translation</line>
<line>    // table entries from lookup levels other than the final level of lookup</line>
<line>    // are treated as being non-global. Translations in Short-Descriptor Format</line>
<line>    // always support global &amp; non-global translations.</line>
<line>    walkstate.nG          = '1';</line>
<line>    walkstate.memattrs    = <a link="impl-shared.WalkMemAttrs.3" file="shared_pseudocode.xml" hover="function: MemoryAttributes WalkMemAttrs(bits(2) sh, bits(2) irgn, bits(2) orgn)">WalkMemAttrs</a>(s:nos, irgn, rgn);</line>
<line>    walkstate.level       = startlevel;</line>
<line>    walkstate.istable     = TRUE;</line>
<line></line>
<line>    bits(4) domain;</line>
<line>    bits(32) descriptor;</line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> walkaddress;</line>
<line></line>
<line>    walkaddress.vaddress = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(va, 64);</line>
<line></line>
<line>    if !<a link="AArch32.S1DCacheEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch32.S1DCacheEnabled(Regime regime)">AArch32.S1DCacheEnabled</a>(regime) then</line>
<line>        walkaddress.memattrs = <a link="impl-shared.NormalNCMemAttr.0" file="shared_pseudocode.xml" hover="function: MemoryAttributes NormalNCMemAttr()">NormalNCMemAttr</a>();</line>
<line>        walkaddress.memattrs.xs = walkstate.memattrs.xs;</line>
<line>    else</line>
<line>        walkaddress.memattrs = walkstate.memattrs;</line>
<line></line>
<line>    // Shareability value of stage 1 translation subject to stage 2 is IMPLEMENTATION DEFINED</line>
<line>    // to be either effective value or descriptor value</line>
<line>    if (regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; <a link="AArch32.EL2Enabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch32.EL2Enabled(SecurityState ss)">AArch32.EL2Enabled</a>(accdesc.ss) &amp;&amp;</line>
<line>        (if <a link="impl-shared.ELStateUsingAArch32.2" file="shared_pseudocode.xml" hover="function: boolean ELStateUsingAArch32(bits(2) el, boolean secure)">ELStateUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, accdesc.ss==<a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>) then HCR.VM else HCR_EL2.VM) == '1' &amp;&amp;</line>
<line>        !(boolean IMPLEMENTATION_DEFINED "Apply effective shareability at stage 1")) then</line>
<line>        walkaddress.memattrs.shareability = walkstate.memattrs.shareability;</line>
<line>    else</line>
<line>        walkaddress.memattrs.shareability = <a link="impl-shared.EffectiveShareability.1" file="shared_pseudocode.xml" hover="function: Shareability EffectiveShareability(MemoryAttributes memattrs)">EffectiveShareability</a>(walkaddress.memattrs);</line>
<line></line>
<line>    bit nG;</line>
<line>    bit ns;</line>
<line>    bit pxn;</line>
<line>    bits(3) ap;</line>
<line>    bits(3) tex;</line>
<line>    bit c;</line>
<line>    bit b;</line>
<line>    bit xn;</line>
<line>    repeat</line>
<line>        fault.level = walkstate.level;</line>
<line></line>
<line>        bits(32) index;</line>
<line>        if walkstate.level == 1 then</line>
<line>            index = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(va&lt;31-n:20&gt;:'00', 32);</line>
<line>        else</line>
<line>            index = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(va&lt;19:12&gt;:'00', 32);</line>
<line></line>
<line>        walkaddress.paddress.address = walkstate.baseaddress.address OR <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(index,</line>
<line>                                                                                   56);</line>
<line>        walkaddress.paddress.paspace = walkstate.baseaddress.paspace;</line>
<line></line>
<line>        boolean toplevel = walkstate.level == startlevel;</line>
<line>        <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> walkaccess = <a link="impl-shared.CreateAccDescS1TTW.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescS1TTW(boolean toplevel, VARange varange, AccessDescriptor accdesc_in)">CreateAccDescS1TTW</a>(toplevel, varange, accdesc);</line>
<line>        if regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; <a link="AArch32.EL2Enabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch32.EL2Enabled(SecurityState ss)">AArch32.EL2Enabled</a>(accdesc.ss) then</line>
<line>            s2aligned = TRUE;</line>
<line>            (s2fault, s2walkaddress) = <a link="AArch32.S2Translate.4" file="shared_pseudocode.xml" hover="function: (FaultRecord, AddressDescriptor) AArch32.S2Translate(FaultRecord fault_in, AddressDescriptor ipa, boolean aligned, AccessDescriptor accdesc)">AArch32.S2Translate</a>(fault, walkaddress, s2aligned,</line>
<line>                                                           walkaccess);</line>
<line></line>
<line>            if s2fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>                return (s2fault, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN);</line>
<line></line>
<line>            (fault, descriptor) = <a link="impl-shared.FetchDescriptor.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, bits(N)) FetchDescriptor(bit ee, AddressDescriptor walkaddress, AccessDescriptor walkaccess, FaultRecord fault_in, integer N)">FetchDescriptor</a>(ee, s2walkaddress, walkaccess, fault, 32);</line>
<line>        else</line>
<line>            (fault, descriptor) = <a link="impl-shared.FetchDescriptor.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, bits(N)) FetchDescriptor(bit ee, AddressDescriptor walkaddress, AccessDescriptor walkaccess, FaultRecord fault_in, integer N)">FetchDescriptor</a>(ee, walkaddress, walkaccess, fault, 32);</line>
<line></line>
<line>        if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>            return (fault, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN);</line>
<line></line>
<line>        walkstate.sdftype = <a link="AArch32.DecodeDescriptorTypeSD.2" file="shared_pseudocode.xml" hover="function: SDFType AArch32.DecodeDescriptorTypeSD(bits(32) descriptor, integer level)">AArch32.DecodeDescriptorTypeSD</a>(descriptor, walkstate.level);</line>
<line></line>
<line>        case walkstate.sdftype of</line>
<line>            when <a link="SDFType_Invalid" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_Invalid</a></line>
<line>                fault.domain     = domain;</line>
<line>                fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>                return (fault, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN);</line>
<line></line>
<line>            when <a link="SDFType_Table" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_Table</a></line>
<line>                domain = descriptor&lt;8:5&gt;;</line>
<line>                ns     = descriptor&lt;3&gt;;</line>
<line>                pxn    = descriptor&lt;2&gt;;</line>
<line></line>
<line>                walkstate.baseaddress.address = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(descriptor&lt;31:10&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(10),</line>
<line>                                                           56);</line>
<line>                walkstate.level = 2;</line>
<line></line>
<line>            when <a link="SDFType_SmallPage" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_SmallPage</a></line>
<line>                nG  = descriptor&lt;11&gt;;</line>
<line>                s   = descriptor&lt;10&gt;;</line>
<line>                ap  = descriptor&lt;9,5:4&gt;;</line>
<line>                tex = descriptor&lt;8:6&gt;;</line>
<line>                c   = descriptor&lt;3&gt;;</line>
<line>                b   = descriptor&lt;2&gt;;</line>
<line>                xn  = descriptor&lt;0&gt;;</line>
<line></line>
<line>                walkstate.baseaddress.address = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(descriptor&lt;31:12&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12),</line>
<line>                                                           56);</line>
<line>                walkstate.istable = FALSE;</line>
<line></line>
<line>            when <a link="SDFType_LargePage" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_LargePage</a></line>
<line>                xn  = descriptor&lt;15&gt;;</line>
<line>                tex = descriptor&lt;14:12&gt;;</line>
<line>                nG  = descriptor&lt;11&gt;;</line>
<line>                s   = descriptor&lt;10&gt;;</line>
<line>                ap  = descriptor&lt;9,5:4&gt;;</line>
<line>                c   = descriptor&lt;3&gt;;</line>
<line>                b   = descriptor&lt;2&gt;;</line>
<line></line>
<line>                walkstate.baseaddress.address = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(descriptor&lt;31:16&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16),</line>
<line>                                                           56);</line>
<line>                walkstate.istable = FALSE;</line>
<line></line>
<line>            when <a link="SDFType_Section" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_Section</a></line>
<line>                ns     = descriptor&lt;19&gt;;</line>
<line>                nG     = descriptor&lt;17&gt;;</line>
<line>                s      = descriptor&lt;16&gt;;</line>
<line>                ap     = descriptor&lt;15,11:10&gt;;</line>
<line>                tex    = descriptor&lt;14:12&gt;;</line>
<line>                domain = descriptor&lt;8:5&gt;;</line>
<line>                xn     = descriptor&lt;4&gt;;</line>
<line>                c      = descriptor&lt;3&gt;;</line>
<line>                b      = descriptor&lt;2&gt;;</line>
<line>                pxn    = descriptor&lt;0&gt;;</line>
<line></line>
<line>                walkstate.baseaddress.address = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(descriptor&lt;31:20&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(20),</line>
<line>                                                           56);</line>
<line>                walkstate.istable = FALSE;</line>
<line></line>
<line>            when <a link="SDFType_Supersection" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_Supersection</a></line>
<line>                ns     = descriptor&lt;19&gt;;</line>
<line>                nG     = descriptor&lt;17&gt;;</line>
<line>                s      = descriptor&lt;16&gt;;</line>
<line>                ap     = descriptor&lt;15,11:10&gt;;</line>
<line>                tex    = descriptor&lt;14:12&gt;;</line>
<line>                xn     = descriptor&lt;4&gt;;</line>
<line>                c      = descriptor&lt;3&gt;;</line>
<line>                b      = descriptor&lt;2&gt;;</line>
<line>                pxn    = descriptor&lt;0&gt;;</line>
<line>                domain = '0000';</line>
<line></line>
<line>                walkstate.baseaddress.address = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(descriptor&lt;8:5,23:20,31:24&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(24),</line>
<line>                                                           56);</line>
<line>                walkstate.istable = FALSE;</line>
<line></line>
<line>    until walkstate.sdftype != <a link="SDFType_Table" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_Table</a>;</line>
<line></line>
<line>    if afe == '1' &amp;&amp; ap&lt;0&gt; == '0' then</line>
<line>        fault.domain     = domain;</line>
<line>        fault.statuscode = <a link="Fault_AccessFlag" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AccessFlag</a>;</line>
<line>        return (fault, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN);</line>
<line></line>
<line>    // Decode the TEX, C, B and S bits to produce target memory attributes</line>
<line>    if tre == '1' then</line>
<line>        walkstate.memattrs = <a link="AArch32.RemappedTEXDecode.5" file="shared_pseudocode.xml" hover="function: MemoryAttributes AArch32.RemappedTEXDecode(Regime regime, bits(3) TEX, bit C, bit B, bit s)">AArch32.RemappedTEXDecode</a>(regime, tex, c, b, s);</line>
<line>    elsif <a link="impl-aarch32.RemapRegsHaveResetValues.0" file="shared_pseudocode.xml" hover="function: boolean RemapRegsHaveResetValues()">RemapRegsHaveResetValues</a>() then</line>
<line>        walkstate.memattrs = <a link="AArch32.DefaultTEXDecode.4" file="shared_pseudocode.xml" hover="function: MemoryAttributes AArch32.DefaultTEXDecode(bits(3) TEX_in, bit C_in, bit B_in, bit s)">AArch32.DefaultTEXDecode</a>(tex, c, b, s);</line>
<line>    else</line>
<line>        walkstate.memattrs = <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> IMPLEMENTATION_DEFINED;</line>
<line></line>
<line>    walkstate.permissions.ap  = ap;</line>
<line>    walkstate.permissions.xn  = xn;</line>
<line>    walkstate.permissions.pxn = pxn;</line>
<line>    walkstate.domain = domain;</line>
<line>    walkstate.nG     = nG;</line>
<line></line>
<line>    if accdesc.ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> &amp;&amp; ns == '0' then</line>
<line>        walkstate.baseaddress.paspace = <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a>;</line>
<line>    else</line>
<line>        walkstate.baseaddress.paspace = <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line></line>
<line>    return (fault, walkstate);</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/walk/AArch32.S2IASize" mylink="aarch32.translation.walk.AArch32.S2IASize" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.S2IASize()</line>
<line>// ==================</line>
<line>// Retrieve the number of bits containing the input address for stage 2 translation</line>
<line></line>
<line link="AArch32.S2IASize.1" hover="function: integer AArch32.S2IASize(bits(4) t0sz)" conts="AArch32.S2IASize">integer <anchor link="AArch32.S2IASize.1" hover="function: integer AArch32.S2IASize(bits(4) t0sz)">AArch32.S2IASize</anchor>(bits(4) t0sz)</line>
<line>    return 32 - <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(t0sz);</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/walk/AArch32.S2StartLevel" mylink="aarch32.translation.walk.AArch32.S2StartLevel" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.S2StartLevel()</line>
<line>// ======================</line>
<line>// Determine the initial lookup level when performing a stage 2 translation</line>
<line>// table walk</line>
<line></line>
<line link="AArch32.S2StartLevel.1" hover="function: integer AArch32.S2StartLevel(bits(2) sl0)" conts="AArch32.S2StartLevel">integer <anchor link="AArch32.S2StartLevel.1" hover="function: integer AArch32.S2StartLevel(bits(2) sl0)">AArch32.S2StartLevel</anchor>(bits(2) sl0)</line>
<line>    return 2 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sl0);</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/walk/AArch32.S2Walk" mylink="aarch32.translation.walk.AArch32.S2Walk" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.S2Walk()</line>
<line>// ================</line>
<line>// Traverse stage 2 translation tables in long format to obtain the final descriptor</line>
<line></line>
<line>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a>, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a>) AArch32.S2Walk(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault_in, S2TTWParams walkparams,</line>
<line>                                       <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> ipa)</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = fault_in;</line>
<line></line>
<line>    if walkparams.sl0 IN {'1x'} || AArch32.S2InconsistentSL(walkparams) then</line>
<line>        fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>        fault.level      = 1;</line>
<line>        return (fault, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN);</line>
<line></line>
<line>    // Input Address size</line>
<line>    iasize      = <a link="AArch32.S2IASize.1" file="shared_pseudocode.xml" hover="function: integer AArch32.S2IASize(bits(4) t0sz)">AArch32.S2IASize</a>(walkparams.t0sz);</line>
<line>    startlevel  = <a link="AArch32.S2StartLevel.1" file="shared_pseudocode.xml" hover="function: integer AArch32.S2StartLevel(bits(2) sl0)">AArch32.S2StartLevel</a>(walkparams.sl0);</line>
<line>    levels      = <a link="FINAL_LEVEL" file="shared_pseudocode.xml" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</a> - startlevel;</line>
<line>    granulebits = <a link="impl-shared.TGxGranuleBits.1" file="shared_pseudocode.xml" hover="function: integer TGxGranuleBits(TGx tgx)">TGxGranuleBits</a>(walkparams.tgx);</line>
<line>    stride      = granulebits - 3;</line>
<line></line>
<line>    if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(VTTBR&lt;47:40&gt;) then</line>
<line>        fault.statuscode = <a link="Fault_AddressSize" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AddressSize</a>;</line>
<line>        fault.level      = 0;</line>
<line>        return (fault, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN);</line>
<line></line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> baseaddress;</line>
<line>    baselsb = (iasize - (levels*stride + granulebits)) + 3;</line>
<line>    baseaddress.paspace = <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line>    baseaddress.address = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(VTTBR&lt;39:baselsb&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(baselsb), 56);</line>
<line></line>
<line>    <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> walkstate;</line>
<line>    walkstate.baseaddress = baseaddress;</line>
<line>    walkstate.level       = startlevel;</line>
<line>    walkstate.istable     = TRUE;</line>
<line>    walkstate.memattrs    = <a link="impl-shared.WalkMemAttrs.3" file="shared_pseudocode.xml" hover="function: MemoryAttributes WalkMemAttrs(bits(2) sh, bits(2) irgn, bits(2) orgn)">WalkMemAttrs</a>(walkparams.sh, walkparams.irgn,</line>
<line>                                         walkparams.orgn);</line>
<line></line>
<line>    indexmsb = iasize - 1;</line>
<line>    bits(64) descriptor;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> walkaccess = <a link="impl-shared.CreateAccDescS2TTW.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescS2TTW(AccessDescriptor accdesc_in)">CreateAccDescS2TTW</a>(accdesc);</line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> walkaddress;</line>
<line></line>
<line>    walkaddress.vaddress = ipa.vaddress;</line>
<line></line>
<line>    if HCR2.CD == '1' then</line>
<line>        walkaddress.memattrs = <a link="impl-shared.NormalNCMemAttr.0" file="shared_pseudocode.xml" hover="function: MemoryAttributes NormalNCMemAttr()">NormalNCMemAttr</a>();</line>
<line>        walkaddress.memattrs.xs = walkstate.memattrs.xs;</line>
<line>    else</line>
<line>        walkaddress.memattrs = walkstate.memattrs;</line>
<line></line>
<line>    walkaddress.memattrs.shareability = <a link="impl-shared.EffectiveShareability.1" file="shared_pseudocode.xml" hover="function: Shareability EffectiveShareability(MemoryAttributes memattrs)">EffectiveShareability</a>(walkaddress.memattrs);</line>
<line></line>
<line>    integer indexlsb;</line>
<line>    <a link="DescriptorType" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType</a> desctype;</line>
<line>    repeat</line>
<line>        fault.level = walkstate.level;</line>
<line></line>
<line>        indexlsb = (<a link="FINAL_LEVEL" file="shared_pseudocode.xml" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</a> - walkstate.level)*stride + granulebits;</line>
<line>        bits(40) index = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(ipa.paddress.address&lt;indexmsb:indexlsb&gt;:'000', 40);</line>
<line></line>
<line>        walkaddress.paddress.address = walkstate.baseaddress.address OR <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(index, 56);</line>
<line>        walkaddress.paddress.paspace = walkstate.baseaddress.paspace;</line>
<line></line>
<line>        (fault, descriptor) = <a link="impl-shared.FetchDescriptor.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, bits(N)) FetchDescriptor(bit ee, AddressDescriptor walkaddress, AccessDescriptor walkaccess, FaultRecord fault_in, integer N)">FetchDescriptor</a>(walkparams.ee, walkaddress, walkaccess, fault, 64);</line>
<line></line>
<line>        if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>            return (fault, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN);</line>
<line></line>
<line>        desctype = <a link="AArch32.DecodeDescriptorTypeLD.2" file="shared_pseudocode.xml" hover="function: DescriptorType AArch32.DecodeDescriptorTypeLD(bits(64) descriptor, integer level)">AArch32.DecodeDescriptorTypeLD</a>(descriptor, walkstate.level);</line>
<line></line>
<line>        case desctype of</line>
<line>            when <a link="DescriptorType_Table" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Table</a></line>
<line>                if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(descriptor&lt;47:40&gt;) then</line>
<line>                    fault.statuscode = <a link="Fault_AddressSize" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AddressSize</a>;</line>
<line>                    return (fault, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN);</line>
<line></line>
<line>                walkstate.baseaddress.address = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(descriptor&lt;39:12&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12), 56);</line>
<line>                walkstate.level = walkstate.level + 1;</line>
<line>                indexmsb = indexlsb - 1;</line>
<line></line>
<line>            when <a link="DescriptorType_Invalid" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Invalid</a></line>
<line>                fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>                return (fault, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN);</line>
<line></line>
<line>            when <a link="DescriptorType_Leaf" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Leaf</a></line>
<line>                walkstate.istable = FALSE;</line>
<line></line>
<line>    until desctype IN {<a link="DescriptorType_Leaf" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Leaf</a>};</line>
<line></line>
<line>    // Check the output address is inside the supported range</line>
<line>    if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(descriptor&lt;47:40&gt;) then</line>
<line>        fault.statuscode = <a link="Fault_AddressSize" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AddressSize</a>;</line>
<line>        return (fault, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN);</line>
<line></line>
<line>    // Check the access flag</line>
<line>    if descriptor&lt;10&gt; == '0' then</line>
<line>        fault.statuscode = <a link="Fault_AccessFlag" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AccessFlag</a>;</line>
<line>        return (fault, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN);</line>
<line></line>
<line>    // Unpack the descriptor into address and upper and lower block attributes</line>
<line>    walkstate.baseaddress.address = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(descriptor&lt;39:indexlsb&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(indexlsb), 56);</line>
<line></line>
<line>    walkstate.permissions.s2ap = descriptor&lt;7:6&gt;;</line>
<line>    walkstate.permissions.s2xn = descriptor&lt;54&gt;;</line>
<line>    if <a link="impl-shared.HaveExtendedExecuteNeverExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveExtendedExecuteNeverExt()">HaveExtendedExecuteNeverExt</a>() then</line>
<line>        walkstate.permissions.s2xnx = descriptor&lt;53&gt;;</line>
<line>    else</line>
<line>        walkstate.permissions.s2xnx = '0';</line>
<line></line>
<line>    memattr = descriptor&lt;5:2&gt;;</line>
<line>    sh      = descriptor&lt;9:8&gt;;</line>
<line>    s2aarch64 = FALSE;</line>
<line>    walkstate.memattrs   = <a link="impl-shared.S2DecodeMemAttrs.3" file="shared_pseudocode.xml" hover="function: MemoryAttributes S2DecodeMemAttrs(bits(4) attr, bits(2) sh, boolean s2aarch64)">S2DecodeMemAttrs</a>(memattr, sh, s2aarch64);</line>
<line>    walkstate.contiguous = descriptor&lt;52&gt;;</line>
<line></line>
<line>    return (fault, walkstate);</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/walk/AArch32.TranslationSizeSD" mylink="aarch32.translation.walk.AArch32.TranslationSizeSD" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.TranslationSizeSD()</line>
<line>// ===========================</line>
<line>// Determine the size of the translation</line>
<line></line>
<line link="AArch32.TranslationSizeSD.1" hover="function: integer AArch32.TranslationSizeSD(SDFType sdftype)" conts="AArch32.TranslationSizeSD">integer <anchor link="AArch32.TranslationSizeSD.1" hover="function: integer AArch32.TranslationSizeSD(SDFType sdftype)">AArch32.TranslationSizeSD</anchor>(<a link="SDFType" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType</a> sdftype)</line>
<line>    integer tsize;</line>
<line>    case sdftype of</line>
<line>        when <a link="SDFType_SmallPage" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_SmallPage</a>      tsize = 12;</line>
<line>        when <a link="SDFType_LargePage" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_LargePage</a>      tsize = 16;</line>
<line>        when <a link="SDFType_Section" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_Section</a>        tsize = 20;</line>
<line>        when <a link="SDFType_Supersection" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_Supersection</a>   tsize = 24;</line>
<line></line>
<line>    return tsize;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/walk/RemapRegsHaveResetValues" mylink="aarch32.translation.walk.RemapRegsHaveResetValues" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// RemapRegsHaveResetValues()</line>
<line>// ==========================</line>
<line></line>
<line link="impl-aarch32.RemapRegsHaveResetValues.0" hover="function: boolean RemapRegsHaveResetValues()" conts="RemapRegsHaveResetValues">boolean <anchor link="impl-aarch32.RemapRegsHaveResetValues.0" hover="function: boolean RemapRegsHaveResetValues()">RemapRegsHaveResetValues</anchor>();</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/walkparams/AArch32.GetS1TTWParams" mylink="aarch32.translation.walkparams.AArch32.GetS1TTWParams" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.GetS1TTWParams()</line>
<line>// ========================</line>
<line>// Returns stage 1 translation table walk parameters from respective controlling</line>
<line>// System registers.</line>
<line></line>
<line>S1TTWParams AArch32.GetS1TTWParams(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(32) va)</line>
<line>    S1TTWParams walkparams;</line>
<line></line>
<line>    case regime of</line>
<line>        when <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>  walkparams = AArch32.S1TTWParamsEL2();</line>
<line>        when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> walkparams = AArch32.S1TTWParamsEL10(va);</line>
<line>        when <a link="Regime_EL30" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL30</a> walkparams = AArch32.S1TTWParamsEL30(va);</line>
<line></line>
<line>    return walkparams;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/walkparams/AArch32.GetS2TTWParams" mylink="aarch32.translation.walkparams.AArch32.GetS2TTWParams" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.GetS2TTWParams()</line>
<line>// ========================</line>
<line>// Gather walk parameters for stage 2 translation</line>
<line></line>
<line>S2TTWParams AArch32.GetS2TTWParams()</line>
<line>    S2TTWParams walkparams;</line>
<line></line>
<line>    walkparams.tgx  = <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>;</line>
<line>    walkparams.s    = VTCR.S;</line>
<line>    walkparams.t0sz = VTCR.T0SZ;</line>
<line>    walkparams.sl0  = VTCR.SL0;</line>
<line>    walkparams.irgn = VTCR.IRGN0;</line>
<line>    walkparams.orgn = VTCR.ORGN0;</line>
<line>    walkparams.sh   = VTCR.SH0;</line>
<line>    walkparams.ee   = HSCTLR.EE;</line>
<line>    walkparams.ptw  = HCR.PTW;</line>
<line>    walkparams.vm   = HCR.VM OR HCR.DC;</line>
<line></line>
<line>    // VTCR.S must match VTCR.T0SZ[3]</line>
<line>    if walkparams.s != walkparams.t0sz&lt;3&gt; then</line>
<line>        (-, walkparams.t0sz) = <a link="impl-shared.ConstrainUnpredictableBits.2" file="shared_pseudocode.xml" hover="function: (Constraint,bits(width)) ConstrainUnpredictableBits(Unpredictable which, integer width)">ConstrainUnpredictableBits</a>(<a link="Unpredictable_RESVTCRS" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESVTCRS</a>, 4);</line>
<line></line>
<line>    return walkparams;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/walkparams/AArch32.GetVARange" mylink="aarch32.translation.walkparams.AArch32.GetVARange" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.GetVARange()</line>
<line>// ====================</line>
<line>// Select the translation base address for stage 1 long-descriptor walks</line>
<line></line>
<line link="AArch32.GetVARange.3" hover="function: VARange AArch32.GetVARange(bits(32) va, bits(3) t0sz, bits(3) t1sz)" conts="AArch32.GetVARange">VARange <anchor link="AArch32.GetVARange.3" hover="function: VARange AArch32.GetVARange(bits(32) va, bits(3) t0sz, bits(3) t1sz)">AArch32.GetVARange</anchor>(bits(32) va, bits(3) t0sz, bits(3) t1sz)</line>
<line>    // Lower range Input Address size</line>
<line>    lo_iasize = <a link="AArch32.S1IASize.1" file="shared_pseudocode.xml" hover="function: integer AArch32.S1IASize(bits(3) txsz)">AArch32.S1IASize</a>(t0sz);</line>
<line>    // Upper range Input Address size</line>
<line>    up_iasize = <a link="AArch32.S1IASize.1" file="shared_pseudocode.xml" hover="function: integer AArch32.S1IASize(bits(3) txsz)">AArch32.S1IASize</a>(t1sz);</line>
<line></line>
<line>    if t1sz == '000' &amp;&amp; t0sz == '000' then</line>
<line>        return <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a>;</line>
<line>    elsif t1sz == '000' then</line>
<line>        return if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(va&lt;31:lo_iasize&gt;) then <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a> else <a link="VARange_UPPER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_UPPER</a>;</line>
<line>    elsif t0sz == '000' then</line>
<line>        return if <a link="impl-shared.IsOnes.1" file="shared_pseudocode.xml" hover="function: boolean IsOnes(bits(N) x)">IsOnes</a>(va&lt;31:up_iasize&gt;) then <a link="VARange_UPPER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_UPPER</a> else <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a>;</line>
<line>    elsif <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(va&lt;31:lo_iasize&gt;) then</line>
<line>        return <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a>;</line>
<line>    elsif <a link="impl-shared.IsOnes.1" file="shared_pseudocode.xml" hover="function: boolean IsOnes(bits(N) x)">IsOnes</a>(va&lt;31:up_iasize&gt;) then</line>
<line>        return <a link="VARange_UPPER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_UPPER</a>;</line>
<line>    else</line>
<line>        // Will be reported as a Translation Fault</line>
<line>        return <a link="VARange" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange</a> UNKNOWN;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/walkparams/AArch32.S1DCacheEnabled" mylink="aarch32.translation.walkparams.AArch32.S1DCacheEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.S1DCacheEnabled()</line>
<line>// =========================</line>
<line>// Determine cacheability of stage 1 data accesses</line>
<line></line>
<line link="AArch32.S1DCacheEnabled.1" hover="function: boolean AArch32.S1DCacheEnabled(Regime regime)" conts="AArch32.S1DCacheEnabled">boolean <anchor link="AArch32.S1DCacheEnabled.1" hover="function: boolean AArch32.S1DCacheEnabled(Regime regime)">AArch32.S1DCacheEnabled</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime)</line>
<line>    case regime of</line>
<line>        when <a link="Regime_EL30" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL30</a> return SCTLR_S.C == '1';</line>
<line>        when <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>  return HSCTLR.C == '1';</line>
<line>        when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> return (if <a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then SCTLR_NS.C else SCTLR.C) == '1';</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/walkparams/AArch32.S1ICacheEnabled" mylink="aarch32.translation.walkparams.AArch32.S1ICacheEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.S1ICacheEnabled()</line>
<line>// =========================</line>
<line>// Determine cacheability of stage 1 instruction fetches</line>
<line></line>
<line link="AArch32.S1ICacheEnabled.1" hover="function: boolean AArch32.S1ICacheEnabled(Regime regime)" conts="AArch32.S1ICacheEnabled">boolean <anchor link="AArch32.S1ICacheEnabled.1" hover="function: boolean AArch32.S1ICacheEnabled(Regime regime)">AArch32.S1ICacheEnabled</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime)</line>
<line>    case regime of</line>
<line>        when <a link="Regime_EL30" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL30</a> return SCTLR_S.I == '1';</line>
<line>        when <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>  return HSCTLR.I == '1';</line>
<line>        when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> return (if <a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then SCTLR_NS.I else SCTLR.I) == '1';</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/walkparams/AArch32.S1TTWParamsEL10" mylink="aarch32.translation.walkparams.AArch32.S1TTWParamsEL10" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.S1TTWParamsEL10()</line>
<line>// =========================</line>
<line>// Gather stage 1 translation table walk parameters for EL1&amp;0 regime</line>
<line>// (with EL2 enabled or disabled).</line>
<line></line>
<line>S1TTWParams AArch32.S1TTWParamsEL10(bits(32) va)</line>
<line>    bits(64) mair;</line>
<line>    bit sif;</line>
<line>    TTBCR_Type ttbcr;</line>
<line>    TTBCR2_Type ttbcr2;</line>
<line>    SCTLR_Type sctlr;</line>
<line></line>
<line>    if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        ttbcr  = TTBCR_NS;</line>
<line>        ttbcr2 = TTBCR2_NS;</line>
<line>        sctlr  = SCTLR_NS;</line>
<line>        mair   = MAIR1_NS:MAIR0_NS;</line>
<line>        sif    = SCR.SIF;</line>
<line>    else</line>
<line>        ttbcr  = TTBCR;</line>
<line>        ttbcr2 = TTBCR2;</line>
<line>        sctlr  = SCTLR;</line>
<line>        mair   = MAIR1:MAIR0;</line>
<line>        sif    = if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then SCR_EL3.SIF else '0';</line>
<line></line>
<line>    assert ttbcr.EAE == '1';</line>
<line>    S1TTWParams walkparams;</line>
<line></line>
<line>    walkparams.t0sz   = ttbcr.T0SZ;</line>
<line>    walkparams.t1sz   = ttbcr.T1SZ;</line>
<line>    walkparams.ee     = sctlr.EE;</line>
<line>    walkparams.wxn    = sctlr.WXN;</line>
<line>    walkparams.uwxn   = sctlr.UWXN;</line>
<line>    walkparams.ntlsmd = if <a link="impl-shared.HaveTrapLoadStoreMultipleDeviceExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTrapLoadStoreMultipleDeviceExt()">HaveTrapLoadStoreMultipleDeviceExt</a>() then sctlr.nTLSMD else '1';</line>
<line>    walkparams.mair   = mair;</line>
<line>    walkparams.sif    = sif;</line>
<line></line>
<line>    varange = <a link="AArch32.GetVARange.3" file="shared_pseudocode.xml" hover="function: VARange AArch32.GetVARange(bits(32) va, bits(3) t0sz, bits(3) t1sz)">AArch32.GetVARange</a>(va, walkparams.t0sz, walkparams.t1sz);</line>
<line>    if varange == <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a> then</line>
<line>        walkparams.sh   = ttbcr.SH0;</line>
<line>        walkparams.irgn = ttbcr.IRGN0;</line>
<line>        walkparams.orgn = ttbcr.ORGN0;</line>
<line>        walkparams.hpd  = if <a link="AArch32.HaveHPDExt.0" file="shared_pseudocode.xml" hover="function: boolean AArch32.HaveHPDExt()">AArch32.HaveHPDExt</a>() then ttbcr.T2E AND ttbcr2.HPD0 else '0';</line>
<line>    else</line>
<line>        walkparams.sh   = ttbcr.SH1;</line>
<line>        walkparams.irgn = ttbcr.IRGN1;</line>
<line>        walkparams.orgn = ttbcr.ORGN1;</line>
<line>        walkparams.hpd  = if <a link="AArch32.HaveHPDExt.0" file="shared_pseudocode.xml" hover="function: boolean AArch32.HaveHPDExt()">AArch32.HaveHPDExt</a>() then ttbcr.T2E AND ttbcr2.HPD1 else '0';</line>
<line></line>
<line>    return walkparams;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/walkparams/AArch32.S1TTWParamsEL2" mylink="aarch32.translation.walkparams.AArch32.S1TTWParamsEL2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.S1TTWParamsEL2()</line>
<line>// ========================</line>
<line>// Gather stage 1 translation table walk parameters for EL2 regime</line>
<line></line>
<line>S1TTWParams AArch32.S1TTWParamsEL2()</line>
<line>    S1TTWParams walkparams;</line>
<line></line>
<line>    walkparams.tgx  = <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>;</line>
<line>    walkparams.t0sz = HTCR.T0SZ;</line>
<line>    walkparams.irgn = HTCR.SH0;</line>
<line>    walkparams.orgn = HTCR.IRGN0;</line>
<line>    walkparams.sh   = HTCR.ORGN0;</line>
<line>    walkparams.hpd  = if <a link="AArch32.HaveHPDExt.0" file="shared_pseudocode.xml" hover="function: boolean AArch32.HaveHPDExt()">AArch32.HaveHPDExt</a>() then HTCR.HPD else '0';</line>
<line>    walkparams.ee   = HSCTLR.EE;</line>
<line>    walkparams.wxn  = HSCTLR.WXN;</line>
<line>    if <a link="impl-shared.HaveTrapLoadStoreMultipleDeviceExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTrapLoadStoreMultipleDeviceExt()">HaveTrapLoadStoreMultipleDeviceExt</a>() then</line>
<line>        walkparams.ntlsmd = HSCTLR.nTLSMD;</line>
<line>    else</line>
<line>        walkparams.ntlsmd = '1';</line>
<line></line>
<line>    walkparams.mair = HMAIR1:HMAIR0;</line>
<line></line>
<line>    return walkparams;</line>
</pstext>
    </ps>
    <ps name="aarch32/translation/walkparams/AArch32.S1TTWParamsEL30" mylink="aarch32.translation.walkparams.AArch32.S1TTWParamsEL30" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.S1TTWParamsEL30()</line>
<line>// =========================</line>
<line>// Gather stage 1 translation table walk parameters for EL3&amp;0 regime</line>
<line></line>
<line>S1TTWParams AArch32.S1TTWParamsEL30(bits(32) va)</line>
<line>    assert TTBCR_S.EAE == '1';</line>
<line>    S1TTWParams walkparams;</line>
<line></line>
<line>    walkparams.t0sz   = TTBCR_S.T0SZ;</line>
<line>    walkparams.t1sz   = TTBCR_S.T1SZ;</line>
<line>    walkparams.ee     = SCTLR_S.EE;</line>
<line>    walkparams.wxn    = SCTLR_S.WXN;</line>
<line>    walkparams.uwxn   = SCTLR_S.UWXN;</line>
<line>    walkparams.ntlsmd = if <a link="impl-shared.HaveTrapLoadStoreMultipleDeviceExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTrapLoadStoreMultipleDeviceExt()">HaveTrapLoadStoreMultipleDeviceExt</a>() then SCTLR_S.nTLSMD else '1';</line>
<line>    walkparams.mair   = MAIR1_S:MAIR0_S;</line>
<line>    walkparams.sif    = SCR.SIF;</line>
<line></line>
<line>    varange = <a link="AArch32.GetVARange.3" file="shared_pseudocode.xml" hover="function: VARange AArch32.GetVARange(bits(32) va, bits(3) t0sz, bits(3) t1sz)">AArch32.GetVARange</a>(va, walkparams.t0sz, walkparams.t1sz);</line>
<line>    if varange == <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a> then</line>
<line>        walkparams.sh   = TTBCR_S.SH0;</line>
<line>        walkparams.irgn = TTBCR_S.IRGN0;</line>
<line>        walkparams.orgn = TTBCR_S.ORGN0;</line>
<line>        walkparams.hpd  = if <a link="AArch32.HaveHPDExt.0" file="shared_pseudocode.xml" hover="function: boolean AArch32.HaveHPDExt()">AArch32.HaveHPDExt</a>() then TTBCR_S.T2E AND TTBCR2_S.HPD0 else '0';</line>
<line>    else</line>
<line>        walkparams.sh   = TTBCR_S.SH1;</line>
<line>        walkparams.irgn = TTBCR_S.IRGN1;</line>
<line>        walkparams.orgn = TTBCR_S.ORGN1;</line>
<line>        walkparams.hpd  = if <a link="AArch32.HaveHPDExt.0" file="shared_pseudocode.xml" hover="function: boolean AArch32.HaveHPDExt()">AArch32.HaveHPDExt</a>() then TTBCR_S.T2E AND TTBCR2_S.HPD1 else '0';</line>
<line></line>
<line>    return walkparams;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/BRBCycleCountingEnabled" mylink="aarch64.debug.brbe.BRBCycleCountingEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BRBCycleCountingEnabled()</line>
<line>// =========================</line>
<line>// Returns TRUE if the BRBINF&lt;n&gt;_EL1.{CCU, CC} fields are valid, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.BRBCycleCountingEnabled.0" hover="function: boolean BRBCycleCountingEnabled()" conts="BRBCycleCountingEnabled">boolean <anchor link="impl-aarch64.BRBCycleCountingEnabled.0" hover="function: boolean BRBCycleCountingEnabled()">BRBCycleCountingEnabled</anchor>()</line>
<line>    if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; BRBCR_EL2.CC == '0' then return FALSE;</line>
<line>    if BRBCR_EL1.CC == '0' then return FALSE;</line>
<line>    return TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/BRBEBranch" mylink="aarch64.debug.brbe.BRBEBranch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BRBEBranch()</line>
<line>// ============</line>
<line>// Called to write branch record for the following branches when BRB is active:</line>
<line>// direct branches,</line>
<line>// indirect branches,</line>
<line>// direct branches with link,</line>
<line>// indirect branches with link,</line>
<line>// returns from subroutines.</line>
<line></line>
<line link="impl-aarch64.BRBEBranch.3" hover="function: BRBEBranch(BranchType br_type, boolean cond, bits(64) target_address)" conts="BRBEBranch"><anchor link="impl-aarch64.BRBEBranch.3" hover="function: BRBEBranch(BranchType br_type, boolean cond, bits(64) target_address)">BRBEBranch</anchor>(<a link="BranchType" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType</a> br_type, boolean cond, bits(64) target_address)</line>
<line>    if <a link="impl-aarch64.BranchRecordAllowed.1" file="shared_pseudocode.xml" hover="function: boolean BranchRecordAllowed(bits(2) el)">BranchRecordAllowed</a>(PSTATE.EL) &amp;&amp; <a link="impl-aarch64.FilterBranchRecord.2" file="shared_pseudocode.xml" hover="function: boolean FilterBranchRecord(BranchType br, boolean cond)">FilterBranchRecord</a>(br_type, cond) then</line>
<line>        bits(6) branch_type;</line>
<line>        case br_type of</line>
<line>            when <a link="BranchType_DIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</a></line>
<line>                branch_type = if cond then '001000' else '000000';</line>
<line>            when <a link="BranchType_INDIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDIR</a>      branch_type = '000001';</line>
<line>            when <a link="BranchType_DIRCALL" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIRCALL</a>    branch_type = '000010';</line>
<line>            when <a link="BranchType_INDCALL" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDCALL</a>    branch_type = '000011';</line>
<line>            when <a link="BranchType_RET" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_RET</a>        branch_type = '000101';</line>
<line>            otherwise                  <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>        bit ccu;</line>
<line>        bits(14) cc;</line>
<line>        (ccu, cc) = <a link="impl-aarch64.BranchEncCycleCount.0" file="shared_pseudocode.xml" hover="function: (bit, bits(14)) BranchEncCycleCount()">BranchEncCycleCount</a>();</line>
<line>        bit lastfailed = if <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() then BRBFCR_EL1.LASTFAILED else '0';</line>
<line>        bit transactional = if <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0 then '1' else '0';</line>
<line>        bits(2) el = PSTATE.EL;</line>
<line>        bit mispredict = if <a link="impl-aarch64.BRBEMispredictAllowed.0" file="shared_pseudocode.xml" hover="function: boolean BRBEMispredictAllowed()">BRBEMispredictAllowed</a>() &amp;&amp; <a link="impl-aarch64.BranchMispredict.0" file="shared_pseudocode.xml" hover="function: boolean BranchMispredict()">BranchMispredict</a>() then '1' else '0';</line>
<line></line>
<line>        <a link="impl-aarch64.UpdateBranchRecordBuffer.10" file="shared_pseudocode.xml" hover="function: UpdateBranchRecordBuffer(bit ccu, bits(14) cc, bit lastfailed, bit transactional, bits(6) branch_type, bits(2) el, bit mispredict, bits(2) valid, bits(64) source_address, bits(64) target_address)">UpdateBranchRecordBuffer</a>(ccu, cc, lastfailed, transactional, branch_type, el, mispredict,</line>
<line>                                 '11', <a link="impl-aarch64.PC.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) PC[]">PC</a>[], target_address);</line>
<line></line>
<line>        BRBFCR_EL1.LASTFAILED = '0';</line>
<line></line>
<line>        <a link="impl-shared.PMUEvent.1" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event)">PMUEvent</a>(PMU_EVENT_BRB_FILTRATE);</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/BRBEBranchOnISB" mylink="aarch64.debug.brbe.BRBEBranchOnISB" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BRBEBranchOnISB()</line>
<line>// =================</line>
<line>// Returns TRUE if ISBs generate Branch records, and FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.BRBEBranchOnISB.0" hover="function: boolean BRBEBranchOnISB()" conts="BRBEBranchOnISB">boolean <anchor link="impl-aarch64.BRBEBranchOnISB.0" hover="function: boolean BRBEBranchOnISB()">BRBEBranchOnISB</anchor>()</line>
<line>    return boolean IMPLEMENTATION_DEFINED "ISB generates Branch records";</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/BRBEDebugStateExit" mylink="aarch64.debug.brbe.BRBEDebugStateExit" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BRBEDebugStateExit()</line>
<line>// ====================</line>
<line>// Called to write Debug state exit branch record when BRB is active.</line>
<line></line>
<line link="impl-aarch64.BRBEDebugStateExit.1" hover="function: BRBEDebugStateExit(bits(64) target_address)" conts="BRBEDebugStateExit"><anchor link="impl-aarch64.BRBEDebugStateExit.1" hover="function: BRBEDebugStateExit(bits(64) target_address)">BRBEDebugStateExit</anchor>(bits(64) target_address)</line>
<line>    if <a link="impl-aarch64.BranchRecordAllowed.1" file="shared_pseudocode.xml" hover="function: boolean BranchRecordAllowed(bits(2) el)">BranchRecordAllowed</a>(PSTATE.EL) then</line>
<line>        // Debug state is a prohibited region, therefore ccu=1, cc=0, source_address=0</line>
<line>        bits(6) branch_type = '111001';</line>
<line>        bit ccu = '1';</line>
<line>        bits(14) cc = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(14);</line>
<line>        bit lastfailed = if <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() then BRBFCR_EL1.LASTFAILED else '0';</line>
<line>        bit transactional = '0';</line>
<line>        bits(2) el = PSTATE.EL;</line>
<line>        bit mispredict = '0';</line>
<line></line>
<line>        <a link="impl-aarch64.UpdateBranchRecordBuffer.10" file="shared_pseudocode.xml" hover="function: UpdateBranchRecordBuffer(bit ccu, bits(14) cc, bit lastfailed, bit transactional, bits(6) branch_type, bits(2) el, bit mispredict, bits(2) valid, bits(64) source_address, bits(64) target_address)">UpdateBranchRecordBuffer</a>(ccu, cc, lastfailed, transactional, branch_type, el, mispredict,</line>
<line>                                 '01', <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64), target_address);</line>
<line></line>
<line>        BRBFCR_EL1.LASTFAILED = '0';</line>
<line></line>
<line>        <a link="impl-shared.PMUEvent.1" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event)">PMUEvent</a>(PMU_EVENT_BRB_FILTRATE);</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/BRBEException" mylink="aarch64.debug.brbe.BRBEException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BRBEException()</line>
<line>// ===============</line>
<line>// Called to write exception branch record when BRB is active.</line>
<line></line>
<line link="impl-aarch64.BRBEException.5" hover="function: BRBEException(ExceptionRecord erec, bits(64) preferred_exception_return, bits(64) target_address_in, bits(2) target_el, boolean trappedsyscallinst)" conts="BRBEException"><anchor link="impl-aarch64.BRBEException.5" hover="function: BRBEException(ExceptionRecord erec, bits(64) preferred_exception_return, bits(64) target_address_in, bits(2) target_el, boolean trappedsyscallinst)">BRBEException</anchor>(<a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> erec, bits(64) preferred_exception_return,</line>
<line>              bits(64) target_address_in, bits(2) target_el, boolean trappedsyscallinst)</line>
<line>    bits(64) target_address = target_address_in;</line>
<line>    <a link="Exception" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception</a> exception = erec.exceptype;</line>
<line>    bits(25) iss = erec.syndrome;</line>
<line>    case target_el of</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>  if !<a link="impl-shared.HaveBRBEv1p1.0" file="shared_pseudocode.xml" hover="function: boolean HaveBRBEv1p1()">HaveBRBEv1p1</a>() || (MDCR_EL3.E3BREC == MDCR_EL3.E3BREW) then return;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>  if BRBCR_EL2.EXCEPTION == '0' then return;</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>  if BRBCR_EL1.EXCEPTION == '0' then return;</line>
<line></line>
<line>    boolean source_valid = <a link="impl-aarch64.BranchRecordAllowed.1" file="shared_pseudocode.xml" hover="function: boolean BranchRecordAllowed(bits(2) el)">BranchRecordAllowed</a>(PSTATE.EL);</line>
<line>    boolean target_valid = <a link="impl-aarch64.BranchRecordAllowed.1" file="shared_pseudocode.xml" hover="function: boolean BranchRecordAllowed(bits(2) el)">BranchRecordAllowed</a>(target_el);</line>
<line></line>
<line>    if source_valid || target_valid then</line>
<line>        bits(6) branch_type;</line>
<line>        case exception of</line>
<line>            when <a link="Exception_Uncategorized" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Uncategorized</a>         branch_type = '100011'; // Trap</line>
<line>            when <a link="Exception_WFxTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_WFxTrap</a>               branch_type = '100011'; // Trap</line>
<line>            when <a link="Exception_CP15RTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP15RTTrap</a>            branch_type = '100011'; // Trap</line>
<line>            when <a link="Exception_CP15RRTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP15RRTTrap</a>           branch_type = '100011'; // Trap</line>
<line>            when <a link="Exception_CP14RTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14RTTrap</a>            branch_type = '100011'; // Trap</line>
<line>            when <a link="Exception_CP14DTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14DTTrap</a>            branch_type = '100011'; // Trap</line>
<line>            when <a link="Exception_AdvSIMDFPAccessTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_AdvSIMDFPAccessTrap</a>   branch_type = '100011'; // Trap</line>
<line>            when <a link="Exception_FPIDTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FPIDTrap</a>              branch_type = '100011'; // Trap</line>
<line>            when <a link="Exception_PACTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_PACTrap</a>               branch_type = '100011'; // Trap</line>
<line>            when <a link="Exception_TSTARTAccessTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_TSTARTAccessTrap</a>      branch_type = '100011'; // Trap</line>
<line>            when <a link="Exception_CP14RRTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14RRTTrap</a>           branch_type = '100011'; // Trap</line>
<line>            when <a link="Exception_BranchTarget" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_BranchTarget</a>          branch_type = '101011'; // Inst Fault</line>
<line>            when <a link="Exception_IllegalState" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_IllegalState</a>          branch_type = '100011'; // Trap</line>
<line>            when <a link="Exception_SupervisorCall" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SupervisorCall</a></line>
<line>                if !trappedsyscallinst then      branch_type = '100010'; // Call</line>
<line>                else                             branch_type = '100011'; // Trap</line>
<line>            when <a link="Exception_HypervisorCall" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_HypervisorCall</a>        branch_type = '100010'; // Call</line>
<line>            when <a link="Exception_MonitorCall" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_MonitorCall</a></line>
<line>                if !trappedsyscallinst then      branch_type = '100010'; // Call</line>
<line>                else                             branch_type = '100011'; // Trap</line>
<line>            when <a link="Exception_SystemRegisterTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SystemRegisterTrap</a>    branch_type = '100011'; // Trap</line>
<line>            when <a link="Exception_SystemRegister128Trap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SystemRegister128Trap</a> branch_type = '100011'; // Trap</line>
<line>            when <a link="Exception_SVEAccessTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SVEAccessTrap</a>         branch_type = '100011'; // Trap</line>
<line>            when <a link="Exception_SMEAccessTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SMEAccessTrap</a>         branch_type = '100011'; // Trap</line>
<line>            when <a link="Exception_ERetTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_ERetTrap</a>              branch_type = '100011'; // Trap</line>
<line>            when <a link="Exception_PACFail" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_PACFail</a>               branch_type = '101100'; // Data Fault</line>
<line>            when <a link="Exception_InstructionAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_InstructionAbort</a>      branch_type = '101011'; // Inst Fault</line>
<line>            when <a link="Exception_PCAlignment" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_PCAlignment</a>           branch_type = '101010'; // Alignment</line>
<line>            when <a link="Exception_DataAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_DataAbort</a>             branch_type = '101100'; // Data Fault</line>
<line>            when <a link="Exception_NV2DataAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_NV2DataAbort</a>          branch_type = '101100'; // Data Fault</line>
<line>            when <a link="Exception_SPAlignment" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SPAlignment</a>           branch_type = '101010'; // Alignment</line>
<line>            when <a link="Exception_FPTrappedException" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FPTrappedException</a>    branch_type = '100011'; // Trap</line>
<line>            when <a link="Exception_SError" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SError</a>                branch_type = '100100'; // System Error</line>
<line>            when <a link="Exception_Breakpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Breakpoint</a>            branch_type = '100110'; // Inst debug</line>
<line>            when <a link="Exception_SoftwareStep" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SoftwareStep</a>          branch_type = '100110'; // Inst debug</line>
<line>            when <a link="Exception_Watchpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Watchpoint</a>            branch_type = '100111'; // Data debug</line>
<line>            when <a link="Exception_NV2Watchpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_NV2Watchpoint</a>         branch_type = '100111'; // Data debug</line>
<line>            when <a link="Exception_SoftwareBreakpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SoftwareBreakpoint</a>    branch_type = '100110'; // Inst debug</line>
<line>            when <a link="Exception_IRQ" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_IRQ</a>                   branch_type = '101110'; // IRQ</line>
<line>            when <a link="Exception_FIQ" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FIQ</a>                   branch_type = '101111'; // FIQ</line>
<line>            when <a link="Exception_MemCpyMemSet" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_MemCpyMemSet</a>          branch_type = '100011'; // Trap</line>
<line>            when <a link="Exception_GCSFail" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_GCSFail</a></line>
<line>                if iss&lt;23:20&gt; == '0000' then     branch_type = '101100'; // Data Fault</line>
<line>                elsif iss&lt;23:20&gt; == '0001' then  branch_type = '101011'; // Inst Fault</line>
<line>                elsif iss&lt;23:20&gt; == '0010' then  branch_type = '100011'; // Trap</line>
<line>                else                             <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>            otherwise                            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>        bit ccu;</line>
<line>        bits(14) cc;</line>
<line>        (ccu, cc) = <a link="impl-aarch64.BranchEncCycleCount.0" file="shared_pseudocode.xml" hover="function: (bit, bits(14)) BranchEncCycleCount()">BranchEncCycleCount</a>();</line>
<line>        bit lastfailed = if <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() then BRBFCR_EL1.LASTFAILED else '0';</line>
<line>        bit transactional = if source_valid &amp;&amp; <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0 then '1' else '0';</line>
<line>        bits(2) el = if target_valid then target_el else '00';</line>
<line>        bit mispredict = '0';</line>
<line>        bit sv = if source_valid then '1' else '0';</line>
<line>        bit tv = if target_valid then '1' else '0';</line>
<line>        bits(64) source_address = if source_valid then preferred_exception_return else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line></line>
<line>        if !target_valid then</line>
<line>            target_address = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>        else</line>
<line>            target_address = <a link="AArch64.BranchAddr.2" file="shared_pseudocode.xml" hover="function: bits(64) AArch64.BranchAddr(bits(64) vaddress, bits(2) el)">AArch64.BranchAddr</a>(target_address, target_el);</line>
<line></line>
<line>        <a link="impl-aarch64.UpdateBranchRecordBuffer.10" file="shared_pseudocode.xml" hover="function: UpdateBranchRecordBuffer(bit ccu, bits(14) cc, bit lastfailed, bit transactional, bits(6) branch_type, bits(2) el, bit mispredict, bits(2) valid, bits(64) source_address, bits(64) target_address)">UpdateBranchRecordBuffer</a>(ccu, cc, lastfailed, transactional, branch_type, el, mispredict,</line>
<line>                                 sv:tv, source_address, target_address);</line>
<line></line>
<line>        BRBFCR_EL1.LASTFAILED = '0';</line>
<line></line>
<line>        <a link="impl-shared.PMUEvent.1" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event)">PMUEvent</a>(PMU_EVENT_BRB_FILTRATE);</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/BRBEExceptionReturn" mylink="aarch64.debug.brbe.BRBEExceptionReturn" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BRBEExceptionReturn()</line>
<line>// =====================</line>
<line>// Called to write exception return branch record when BRB is active.</line>
<line></line>
<line link="impl-aarch64.BRBEExceptionReturn.2" hover="function: BRBEExceptionReturn(bits(64) target_address_in, bits(2) source_el)" conts="BRBEExceptionReturn"><anchor link="impl-aarch64.BRBEExceptionReturn.2" hover="function: BRBEExceptionReturn(bits(64) target_address_in, bits(2) source_el)">BRBEExceptionReturn</anchor>(bits(64) target_address_in, bits(2) source_el)</line>
<line>    bits(64) target_address = target_address_in;</line>
<line>    case source_el of</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>  if !<a link="impl-shared.HaveBRBEv1p1.0" file="shared_pseudocode.xml" hover="function: boolean HaveBRBEv1p1()">HaveBRBEv1p1</a>() || (MDCR_EL3.E3BREC == MDCR_EL3.E3BREW) then return;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>  if BRBCR_EL2.ERTN == '0' then return;</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>  if BRBCR_EL1.ERTN == '0' then return;</line>
<line></line>
<line>    boolean source_valid = <a link="impl-aarch64.BranchRecordAllowed.1" file="shared_pseudocode.xml" hover="function: boolean BranchRecordAllowed(bits(2) el)">BranchRecordAllowed</a>(source_el);</line>
<line>    boolean target_valid = <a link="impl-aarch64.BranchRecordAllowed.1" file="shared_pseudocode.xml" hover="function: boolean BranchRecordAllowed(bits(2) el)">BranchRecordAllowed</a>(PSTATE.EL);</line>
<line></line>
<line>    if source_valid || target_valid then</line>
<line>        bits(6) branch_type = '000111';</line>
<line>        bit ccu;</line>
<line>        bits(14) cc;</line>
<line>        (ccu, cc) = <a link="impl-aarch64.BranchEncCycleCount.0" file="shared_pseudocode.xml" hover="function: (bit, bits(14)) BranchEncCycleCount()">BranchEncCycleCount</a>();</line>
<line>        bit lastfailed = if <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() then BRBFCR_EL1.LASTFAILED else '0';</line>
<line>        bit transactional = if source_valid &amp;&amp; <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0 then '1' else '0';</line>
<line>        bits(2) el = if target_valid then PSTATE.EL else '00';</line>
<line>        bit mispredict = if (source_valid &amp;&amp; <a link="impl-aarch64.BRBEMispredictAllowed.0" file="shared_pseudocode.xml" hover="function: boolean BRBEMispredictAllowed()">BRBEMispredictAllowed</a>() &amp;&amp;</line>
<line>                             <a link="impl-aarch64.BranchMispredict.0" file="shared_pseudocode.xml" hover="function: boolean BranchMispredict()">BranchMispredict</a>()) then '1' else '0';</line>
<line>        bit sv = if source_valid then '1' else '0';</line>
<line>        bit tv = if target_valid then '1' else '0';</line>
<line>        bits(64) source_address = if source_valid then <a link="impl-aarch64.PC.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) PC[]">PC</a>[] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>        if !target_valid then</line>
<line>            target_address = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line></line>
<line>        <a link="impl-aarch64.UpdateBranchRecordBuffer.10" file="shared_pseudocode.xml" hover="function: UpdateBranchRecordBuffer(bit ccu, bits(14) cc, bit lastfailed, bit transactional, bits(6) branch_type, bits(2) el, bit mispredict, bits(2) valid, bits(64) source_address, bits(64) target_address)">UpdateBranchRecordBuffer</a>(ccu, cc, lastfailed, transactional, branch_type, el, mispredict,</line>
<line>                                 sv:tv, source_address, target_address);</line>
<line></line>
<line>        BRBFCR_EL1.LASTFAILED = '0';</line>
<line></line>
<line>        <a link="impl-shared.PMUEvent.1" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event)">PMUEvent</a>(PMU_EVENT_BRB_FILTRATE);</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/BRBEFreeze" mylink="aarch64.debug.brbe.BRBEFreeze" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BRBEFreeze()</line>
<line>// ============</line>
<line>// Generates BRBE freeze event.</line>
<line></line>
<line link="impl-aarch64.BRBEFreeze.0" hover="function: BRBEFreeze()" conts="BRBEFreeze"><anchor link="impl-aarch64.BRBEFreeze.0" hover="function: BRBEFreeze()">BRBEFreeze</anchor>()</line>
<line>    BRBFCR_EL1.PAUSED = '1';</line>
<line>    BRBTS_EL1 = <a link="impl-shared.GetTimestamp.1" file="shared_pseudocode.xml" hover="function: bits(64) GetTimestamp(TimeStamp timeStampType)">GetTimestamp</a>(<a link="impl-aarch64.BRBETimeStamp.0" file="shared_pseudocode.xml" hover="function: TimeStamp BRBETimeStamp()">BRBETimeStamp</a>());</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/BRBEISB" mylink="aarch64.debug.brbe.BRBEISB" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BRBEISB()</line>
<line>// =========</line>
<line>// Handles ISB instruction for BRBE.</line>
<line></line>
<line link="impl-aarch64.BRBEISB.0" hover="function: BRBEISB()" conts="BRBEISB"><anchor link="impl-aarch64.BRBEISB.0" hover="function: BRBEISB()">BRBEISB</anchor>()</line>
<line>    boolean branch_conditional = FALSE;</line>
<line>    <a link="impl-aarch64.BRBEBranch.3" file="shared_pseudocode.xml" hover="function: BRBEBranch(BranchType br_type, boolean cond, bits(64) target_address)">BRBEBranch</a>(<a link="BranchType_DIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</a>, branch_conditional, <a link="impl-aarch64.PC.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) PC[]">PC</a>[] + 4);</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/BRBEMispredictAllowed" mylink="aarch64.debug.brbe.BRBEMispredictAllowed" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BRBEMispredictAllowed()</line>
<line>// =======================</line>
<line>// Returns TRUE if the recording of branch misprediction is allowed, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.BRBEMispredictAllowed.0" hover="function: boolean BRBEMispredictAllowed()" conts="BRBEMispredictAllowed">boolean <anchor link="impl-aarch64.BRBEMispredictAllowed.0" hover="function: boolean BRBEMispredictAllowed()">BRBEMispredictAllowed</anchor>()</line>
<line>    if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; BRBCR_EL2.MPRED == '0' then return FALSE;</line>
<line>    if BRBCR_EL1.MPRED == '0' then return FALSE;</line>
<line>    return TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/BRBETimeStamp" mylink="aarch64.debug.brbe.BRBETimeStamp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BRBETimeStamp()</line>
<line>// ===============</line>
<line>// Returns captured timestamp.</line>
<line></line>
<line link="impl-aarch64.BRBETimeStamp.0" hover="function: TimeStamp BRBETimeStamp()" conts="BRBETimeStamp">TimeStamp <anchor link="impl-aarch64.BRBETimeStamp.0" hover="function: TimeStamp BRBETimeStamp()">BRBETimeStamp</anchor>()</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>        TS_el2 = BRBCR_EL2.TS;</line>
<line>        if !<a link="impl-shared.HaveECVExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveECVExt()">HaveECVExt</a>() &amp;&amp; TS_el2 == '10' then</line>
<line>            // Reserved value</line>
<line>            (-, TS_el2) = <a link="impl-shared.ConstrainUnpredictableBits.2" file="shared_pseudocode.xml" hover="function: (Constraint,bits(width)) ConstrainUnpredictableBits(Unpredictable which, integer width)">ConstrainUnpredictableBits</a>(<a link="Unpredictable_EL2TIMESTAMP" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_EL2TIMESTAMP</a>, 2);</line>
<line>        case TS_el2 of</line>
<line>            when '00'</line>
<line>                // Falls out to check BRBCR_EL1.TS</line>
<line>            when '01'</line>
<line>                return <a link="TimeStamp_Virtual" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_Virtual</a>;</line>
<line>            when '10'</line>
<line>                assert <a link="impl-shared.HaveECVExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveECVExt()">HaveECVExt</a>(); // Otherwise ConstrainUnpredictableBits removes this case</line>
<line>                return <a link="TimeStamp_OffsetPhysical" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_OffsetPhysical</a>;</line>
<line>            when '11'</line>
<line>                return <a link="TimeStamp_Physical" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_Physical</a>;</line>
<line></line>
<line>    TS_el1 = BRBCR_EL1.TS;</line>
<line>    if TS_el1 == '00' || (!<a link="impl-shared.HaveECVExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveECVExt()">HaveECVExt</a>() &amp;&amp; TS_el1 == '10') then</line>
<line>        // Reserved value</line>
<line>        (-, TS_el1) = <a link="impl-shared.ConstrainUnpredictableBits.2" file="shared_pseudocode.xml" hover="function: (Constraint,bits(width)) ConstrainUnpredictableBits(Unpredictable which, integer width)">ConstrainUnpredictableBits</a>(<a link="Unpredictable_EL1TIMESTAMP" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_EL1TIMESTAMP</a>, 2);</line>
<line>    case TS_el1 of</line>
<line>        when '01'</line>
<line>            return <a link="TimeStamp_Virtual" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_Virtual</a>;</line>
<line>        when '10'</line>
<line>            return <a link="TimeStamp_OffsetPhysical" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_OffsetPhysical</a>;</line>
<line>        when '11'</line>
<line>            return <a link="TimeStamp_Physical" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_Physical</a>;</line>
<line>        otherwise</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();           // ConstrainUnpredictableBits removes this case</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/BRB_IALL" mylink="aarch64.debug.brbe.BRB_IALL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BRB_IALL()</line>
<line>// ==========</line>
<line>// Called to perform invalidation of branch records</line>
<line></line>
<line link="impl-aarch64.BRB_IALL.0" hover="function: BRB_IALL()" conts="BRB_IALL"><anchor link="impl-aarch64.BRB_IALL.0" hover="function: BRB_IALL()">BRB_IALL</anchor>()</line>
<line>    for i = 0 to <a link="impl-aarch64.GetBRBENumRecords.0" file="shared_pseudocode.xml" hover="function: integer GetBRBENumRecords()">GetBRBENumRecords</a>() - 1</line>
<line>        Records_SRC[i] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>        Records_TGT[i] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>        Records_INF[i] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/BRB_INJ" mylink="aarch64.debug.brbe.BRB_INJ" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BRB_INJ()</line>
<line>// =========</line>
<line>// Called to perform manual injection of branch records.</line>
<line></line>
<line link="impl-aarch64.BRB_INJ.0" hover="function: BRB_INJ()" conts="BRB_INJ"><anchor link="impl-aarch64.BRB_INJ.0" hover="function: BRB_INJ()">BRB_INJ</anchor>()</line>
<line>    <a link="impl-aarch64.UpdateBranchRecordBuffer.10" file="shared_pseudocode.xml" hover="function: UpdateBranchRecordBuffer(bit ccu, bits(14) cc, bit lastfailed, bit transactional, bits(6) branch_type, bits(2) el, bit mispredict, bits(2) valid, bits(64) source_address, bits(64) target_address)">UpdateBranchRecordBuffer</a>(BRBINFINJ_EL1.CCU, BRBINFINJ_EL1.CC, BRBINFINJ_EL1.LASTFAILED,</line>
<line>                             BRBINFINJ_EL1.T, BRBINFINJ_EL1.TYPE, BRBINFINJ_EL1.EL,</line>
<line>                             BRBINFINJ_EL1.MPRED, BRBINFINJ_EL1.VALID, BRBSRCINJ_EL1.ADDRESS,</line>
<line>                             BRBTGTINJ_EL1.ADDRESS);</line>
<line>    BRBINFINJ_EL1 = bits(64) UNKNOWN;</line>
<line>    BRBSRCINJ_EL1 = bits(64) UNKNOWN;</line>
<line>    BRBTGTINJ_EL1 = bits(64) UNKNOWN;</line>
<line></line>
<line>    if <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_BRBFILTRATE" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BRBFILTRATE</a>) then <a link="impl-shared.PMUEvent.1" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event)">PMUEvent</a>(PMU_EVENT_BRB_FILTRATE);</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/Branch" mylink="aarch64.debug.brbe.Branch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="BRBSRCType" hover="type BRBSRCType" conts="BRBSRCType">type <anchor link="BRBSRCType" hover="type BRBSRCType">BRBSRCType</anchor>;</line>
<line link="BRBTGTType" hover="type BRBTGTType" conts="BRBTGTType">type <anchor link="BRBTGTType" hover="type BRBTGTType">BRBTGTType</anchor>;</line>
<line link="BRBINFType" hover="type BRBINFType" conts="BRBINFType">type <anchor link="BRBINFType" hover="type BRBINFType">BRBINFType</anchor>;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/BranchEncCycleCount" mylink="aarch64.debug.brbe.BranchEncCycleCount" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BranchEncCycleCount()</line>
<line>// =====================</line>
<line>// The first return result is '1' if either of the following is true, and '0' otherwise:</line>
<line>// - This is the first Branch record after the PE exited a Prohibited Region.</line>
<line>// - This is the first Branch record after cycle counting has been enabled.</line>
<line>// If the first return return is '0', the second return result is the encoded cycle count</line>
<line>// since the last branch.</line>
<line>// The format of this field uses a mantissa and exponent to express the cycle count value.</line>
<line>//  - bits[7:0] indicate the mantissa M.</line>
<line>//  - bits[13:8] indicate the exponent E.</line>
<line>// The cycle count is expressed using the following function:</line>
<line>//   cycle_count = (if IsZero(E) then UInt(M) else UInt('1':M:Zeros(UInt(E)-1)))</line>
<line>// A value of all ones in both the mantissa and exponent indicates the cycle count value</line>
<line>// exceeded the size of the cycle counter.</line>
<line>// If the cycle count is not known, the second return result is zero.</line>
<line></line>
<line link="impl-aarch64.BranchEncCycleCount.0" hover="function: (bit, bits(14)) BranchEncCycleCount()" conts="BranchEncCycleCount">(bit, bits(14)) <anchor link="impl-aarch64.BranchEncCycleCount.0" hover="function: (bit, bits(14)) BranchEncCycleCount()">BranchEncCycleCount</anchor>();</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/BranchMispredict" mylink="aarch64.debug.brbe.BranchMispredict" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BranchMispredict()</line>
<line>// ==================</line>
<line>// Returns TRUE if the branch being executed was mispredicted, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.BranchMispredict.0" hover="function: boolean BranchMispredict()" conts="BranchMispredict">boolean <anchor link="impl-aarch64.BranchMispredict.0" hover="function: boolean BranchMispredict()">BranchMispredict</anchor>();</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/BranchRawCycleCount" mylink="aarch64.debug.brbe.BranchRawCycleCount" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BranchRawCycleCount()</line>
<line>// =====================</line>
<line>// If the cycle count is known, the return result is the cycle count since the last branch.</line>
<line></line>
<line link="impl-aarch64.BranchRawCycleCount.0" hover="function: integer BranchRawCycleCount()" conts="BranchRawCycleCount">integer <anchor link="impl-aarch64.BranchRawCycleCount.0" hover="function: integer BranchRawCycleCount()">BranchRawCycleCount</anchor>();</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/BranchRecordAllowed" mylink="aarch64.debug.brbe.BranchRecordAllowed" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BranchRecordAllowed()</line>
<line>// =====================</line>
<line>// Returns TRUE if branch recording is allowed, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.BranchRecordAllowed.1" hover="function: boolean BranchRecordAllowed(bits(2) el)" conts="BranchRecordAllowed">boolean <anchor link="impl-aarch64.BranchRecordAllowed.1" hover="function: boolean BranchRecordAllowed(bits(2) el)">BranchRecordAllowed</anchor>(bits(2) el)</line>
<line>    if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(el) then</line>
<line>        return FALSE;</line>
<line></line>
<line>    if BRBFCR_EL1.PAUSED == '1' then</line>
<line>        return FALSE;</line>
<line></line>
<line>    if el == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> &amp;&amp; <a link="impl-shared.HaveBRBEv1p1.0" file="shared_pseudocode.xml" hover="function: boolean HaveBRBEv1p1()">HaveBRBEv1p1</a>() then</line>
<line>        return (MDCR_EL3.E3BREC != MDCR_EL3.E3BREW);</line>
<line></line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; (MDCR_EL3.SBRBE == '00' ||</line>
<line>        (<a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> &amp;&amp; MDCR_EL3.SBRBE == '01')) then</line>
<line>        return FALSE;</line>
<line></line>
<line>    case el of</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>  return FALSE;                // FEAT_BRBEv1p1 not implemented</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>  return BRBCR_EL2.E2BRE == '1';</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>  return BRBCR_EL1.E1BRE == '1';</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>            if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1' then</line>
<line>                return BRBCR_EL2.E0HBRE == '1';</line>
<line>            else</line>
<line>                return BRBCR_EL1.E0BRE == '1';</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/Contents" mylink="aarch64.debug.brbe.Contents" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Contents of the Branch Record Buffer</line>
<line>//=====================================</line>
<line></line>
<line>array [0..63] of <a link="BRBSRCType" file="shared_pseudocode.xml" hover="type BRBSRCType">BRBSRCType</a> Records_SRC;</line>
<line></line>
<line>array [0..63] of <a link="BRBTGTType" file="shared_pseudocode.xml" hover="type BRBTGTType">BRBTGTType</a> Records_TGT;</line>
<line></line>
<line>array [0..63] of <a link="BRBINFType" file="shared_pseudocode.xml" hover="type BRBINFType">BRBINFType</a> Records_INF;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/FilterBranchRecord" mylink="aarch64.debug.brbe.FilterBranchRecord" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FilterBranchRecord()</line>
<line>// ====================</line>
<line>// Returns TRUE if the branch record is not filtered out, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.FilterBranchRecord.2" hover="function: boolean FilterBranchRecord(BranchType br, boolean cond)" conts="FilterBranchRecord">boolean <anchor link="impl-aarch64.FilterBranchRecord.2" hover="function: boolean FilterBranchRecord(BranchType br, boolean cond)">FilterBranchRecord</anchor>(<a link="BranchType" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType</a> br, boolean cond)</line>
<line>    case br of</line>
<line>        when <a link="BranchType_DIRCALL" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIRCALL</a></line>
<line>            return BRBFCR_EL1.DIRCALL != BRBFCR_EL1.EnI;</line>
<line>        when <a link="BranchType_INDCALL" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDCALL</a></line>
<line>            return BRBFCR_EL1.INDCALL != BRBFCR_EL1.EnI;</line>
<line>        when <a link="BranchType_RET" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_RET</a></line>
<line>            return BRBFCR_EL1.RTN != BRBFCR_EL1.EnI;</line>
<line>        when <a link="BranchType_DIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</a></line>
<line>            if cond then</line>
<line>                return BRBFCR_EL1.CONDDIR != BRBFCR_EL1.EnI;</line>
<line>            else</line>
<line>                return BRBFCR_EL1.DIRECT != BRBFCR_EL1.EnI;</line>
<line>        when <a link="BranchType_INDIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDIR</a></line>
<line>            return BRBFCR_EL1.INDIRECT != BRBFCR_EL1.EnI;</line>
<line>        otherwise  <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>    return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/FirstBranchAfterProhibited" mylink="aarch64.debug.brbe.FirstBranchAfterProhibited" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FirstBranchAfterProhibited()</line>
<line>// ============================</line>
<line>// Returns TRUE if branch recorded is the first branch after a prohibited region,</line>
<line>// FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.FirstBranchAfterProhibited.0" hover="function: FirstBranchAfterProhibited()" conts="FirstBranchAfterProhibited"><anchor link="impl-aarch64.FirstBranchAfterProhibited.0" hover="function: FirstBranchAfterProhibited()">FirstBranchAfterProhibited</anchor>();</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/GetBRBENumRecords" mylink="aarch64.debug.brbe.GetBRBENumRecords" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GetBRBENumRecords()</line>
<line>// ===================</line>
<line>// Returns the number of branch records implemented.</line>
<line></line>
<line link="impl-aarch64.GetBRBENumRecords.0" hover="function: integer GetBRBENumRecords()" conts="GetBRBENumRecords">integer <anchor link="impl-aarch64.GetBRBENumRecords.0" hover="function: integer GetBRBENumRecords()">GetBRBENumRecords</anchor>()</line>
<line>    assert <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(BRBIDR0_EL1.NUMREC) IN {0x08, 0x10, 0x20, 0x40};</line>
<line>    return integer IMPLEMENTATION_DEFINED "Number of BRB records";</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/Getter" mylink="aarch64.debug.brbe.Getter" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Getter functions for branch records</line>
<line>// ===================================</line>
<line>// Functions used by MRS instructions that access branch records</line>
<line></line>
<line link="impl-aarch64.BRBSRC_EL1.read.1" hover="accessor: BRBSRCType BRBSRC_EL1[integer n]" conts="BRBSRC_EL1">BRBSRCType <anchor link="impl-aarch64.BRBSRC_EL1.read.1" hover="accessor: BRBSRCType BRBSRC_EL1[integer n]">BRBSRC_EL1</anchor>[integer n]</line>
<line>    assert n IN {0..31};</line>
<line>    integer record = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(BRBFCR_EL1.BANK:n&lt;4:0&gt;);</line>
<line>    if record &lt; <a link="impl-aarch64.GetBRBENumRecords.0" file="shared_pseudocode.xml" hover="function: integer GetBRBENumRecords()">GetBRBENumRecords</a>() then</line>
<line>        return Records_SRC[record];</line>
<line>    else</line>
<line>        return <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line></line>
<line link="impl-aarch64.BRBTGT_EL1.read.1" hover="accessor: BRBTGTType BRBTGT_EL1[integer n]" conts="BRBTGT_EL1">BRBTGTType <anchor link="impl-aarch64.BRBTGT_EL1.read.1" hover="accessor: BRBTGTType BRBTGT_EL1[integer n]">BRBTGT_EL1</anchor>[integer n]</line>
<line>    assert n IN {0..31};</line>
<line>    integer record = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(BRBFCR_EL1.BANK:n&lt;4:0&gt;);</line>
<line>    if record &lt; <a link="impl-aarch64.GetBRBENumRecords.0" file="shared_pseudocode.xml" hover="function: integer GetBRBENumRecords()">GetBRBENumRecords</a>() then</line>
<line>        return Records_TGT[record];</line>
<line>    else</line>
<line>        return <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line></line>
<line link="impl-aarch64.BRBINF_EL1.read.1" hover="accessor: BRBINFType BRBINF_EL1[integer n]" conts="BRBINF_EL1">BRBINFType <anchor link="impl-aarch64.BRBINF_EL1.read.1" hover="accessor: BRBINFType BRBINF_EL1[integer n]">BRBINF_EL1</anchor>[integer n]</line>
<line>    assert n IN {0..31};</line>
<line>    integer record = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(BRBFCR_EL1.BANK:n&lt;4:0&gt;);</line>
<line>    if record &lt; <a link="impl-aarch64.GetBRBENumRecords.0" file="shared_pseudocode.xml" hover="function: integer GetBRBENumRecords()">GetBRBENumRecords</a>() then</line>
<line>        return Records_INF[record];</line>
<line>    else</line>
<line>        return <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/ShouldBRBEFreeze" mylink="aarch64.debug.brbe.ShouldBRBEFreeze" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ShouldBRBEFreeze()</line>
<line>// ==================</line>
<line>// Returns TRUE if the BRBE freeze event conditions have been met, and FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.ShouldBRBEFreeze.0" hover="function: boolean ShouldBRBEFreeze()" conts="ShouldBRBEFreeze">boolean <anchor link="impl-aarch64.ShouldBRBEFreeze.0" hover="function: boolean ShouldBRBEFreeze()">ShouldBRBEFreeze</anchor>()</line>
<line>    if !<a link="impl-aarch64.BranchRecordAllowed.1" file="shared_pseudocode.xml" hover="function: boolean BranchRecordAllowed(bits(2) el)">BranchRecordAllowed</a>(PSTATE.EL) then return FALSE;</line>
<line>    boolean check_e      = FALSE;</line>
<line>    boolean check_cnten  = FALSE;</line>
<line>    boolean check_inten  = FALSE;</line>
<line>    boolean exclude_sync = FALSE;</line>
<line>    boolean exclude_cyc  = TRUE;</line>
<line>    boolean include_lo;</line>
<line>    boolean include_hi;</line>
<line></line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>        include_lo = (BRBCR_EL1.FZP == '1');</line>
<line>        include_hi = (BRBCR_EL2.FZP == '1');</line>
<line>    else</line>
<line>        include_lo = TRUE;</line>
<line>        include_hi = TRUE;</line>
<line></line>
<line>    return <a link="impl-shared.PMUOverflowCondition.7" file="shared_pseudocode.xml" hover="function: boolean PMUOverflowCondition(boolean check_e, boolean check_cnten, boolean check_inten, boolean include_hi, boolean include_lo, boolean exclude_cyc, boolean exclude_sync)">PMUOverflowCondition</a>(check_e, check_cnten, check_inten,</line>
<line>                                include_hi, include_lo, exclude_cyc,</line>
<line>                                exclude_sync);</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/brbe/UpdateBranchRecordBuffer" mylink="aarch64.debug.brbe.UpdateBranchRecordBuffer" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// UpdateBranchRecordBuffer()</line>
<line>// ==========================</line>
<line>// Add a new Branch record to the buffer.</line>
<line></line>
<line link="impl-aarch64.UpdateBranchRecordBuffer.10" hover="function: UpdateBranchRecordBuffer(bit ccu, bits(14) cc, bit lastfailed, bit transactional, bits(6) branch_type, bits(2) el, bit mispredict, bits(2) valid, bits(64) source_address, bits(64) target_address)" conts="UpdateBranchRecordBuffer"><anchor link="impl-aarch64.UpdateBranchRecordBuffer.10" hover="function: UpdateBranchRecordBuffer(bit ccu, bits(14) cc, bit lastfailed, bit transactional, bits(6) branch_type, bits(2) el, bit mispredict, bits(2) valid, bits(64) source_address, bits(64) target_address)">UpdateBranchRecordBuffer</anchor>(bit ccu, bits(14) cc, bit lastfailed, bit transactional,</line>
<line>                         bits(6) branch_type, bits(2) el, bit mispredict, bits(2) valid,</line>
<line>                         bits(64) source_address, bits(64) target_address)</line>
<line>    // Shift the Branch Records in the buffer</line>
<line>    for i = <a link="impl-aarch64.GetBRBENumRecords.0" file="shared_pseudocode.xml" hover="function: integer GetBRBENumRecords()">GetBRBENumRecords</a>() - 1 downto 1</line>
<line>        Records_SRC[i] = Records_SRC[i - 1];</line>
<line>        Records_TGT[i] = Records_TGT[i - 1];</line>
<line>        Records_INF[i] = Records_INF[i - 1];</line>
<line></line>
<line>    Records_INF[0].CCU        = ccu;</line>
<line>    Records_INF[0].CC         = cc;</line>
<line></line>
<line>    Records_INF[0].EL         = el;</line>
<line>    Records_INF[0].VALID      = valid;</line>
<line>    Records_INF[0].T          = transactional;</line>
<line>    Records_INF[0].LASTFAILED = lastfailed;</line>
<line>    Records_INF[0].MPRED      = mispredict;</line>
<line>    Records_INF[0].TYPE       = branch_type;</line>
<line></line>
<line>    Records_SRC[0] = source_address;</line>
<line>    Records_TGT[0] = target_address;</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/breakpoint/AArch64.BreakpointMatch" mylink="aarch64.debug.breakpoint.AArch64.BreakpointMatch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.BreakpointMatch()</line>
<line>// =========================</line>
<line>// Breakpoint matching in an AArch64 translation regime.</line>
<line></line>
<line link="AArch64.BreakpointMatch.4" hover="function: boolean AArch64.BreakpointMatch(integer n, bits(64) vaddress, AccessDescriptor accdesc, integer size)" conts="AArch64.BreakpointMatch">boolean <anchor link="AArch64.BreakpointMatch.4" hover="function: boolean AArch64.BreakpointMatch(integer n, bits(64) vaddress, AccessDescriptor accdesc, integer size)">AArch64.BreakpointMatch</anchor>(integer n, bits(64) vaddress, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc,</line>
<line>                                integer size)</line>
<line>    assert !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>());</line>
<line>    assert n &lt; <a link="impl-shared.NumBreakpointsImplemented.0" file="shared_pseudocode.xml" hover="function: integer NumBreakpointsImplemented()">NumBreakpointsImplemented</a>();</line>
<line></line>
<line>    enabled = <a link="impl-aarch64.IsBreakpointEnabled.1" file="shared_pseudocode.xml" hover="function: boolean IsBreakpointEnabled(integer n)">IsBreakpointEnabled</a>(n);</line>
<line>    linked  = DBGBCR_EL1[n].BT IN {'0x01'};</line>
<line>    isbreakpnt = TRUE;</line>
<line>    linked_to  = FALSE;</line>
<line></line>
<line>    ssce = if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then DBGBCR_EL1[n].SSCE else '0';</line>
<line>    state_match = <a link="AArch64.StateMatch.8" file="shared_pseudocode.xml" hover="function: boolean AArch64.StateMatch(bits(2) ssc_in, bit ssce_in, bit hmc_in, bits(2) pxc_in, boolean linked_in, bits(4) lbn, boolean isbreakpnt, AccessDescriptor accdesc)">AArch64.StateMatch</a>(DBGBCR_EL1[n].SSC, ssce, DBGBCR_EL1[n].HMC, DBGBCR_EL1[n].PMC,</line>
<line>                                     linked, DBGBCR_EL1[n].LBN, isbreakpnt, accdesc);</line>
<line>    value_match = <a link="AArch64.BreakpointValueMatch.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.BreakpointValueMatch(integer n_in, bits(64) vaddress, boolean linked_to)">AArch64.BreakpointValueMatch</a>(n, vaddress, linked_to);</line>
<line></line>
<line>    if <a link="impl-shared.HaveAArch32.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32()">HaveAArch32</a>() &amp;&amp; size == 4 then                    // Check second halfword</line>
<line>        // If the breakpoint address and BAS of an Address breakpoint match the address of the</line>
<line>        // second halfword of an instruction, but not the address of the first halfword, it is</line>
<line>        // CONSTRAINED UNPREDICTABLE whether or not this breakpoint generates a Breakpoint debug</line>
<line>        // event.</line>
<line>        match_i = <a link="AArch64.BreakpointValueMatch.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.BreakpointValueMatch(integer n_in, bits(64) vaddress, boolean linked_to)">AArch64.BreakpointValueMatch</a>(n, vaddress + 2, linked_to);</line>
<line>        if !value_match &amp;&amp; match_i then</line>
<line>            value_match = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_BPMATCHHALF" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BPMATCHHALF</a>);</line>
<line></line>
<line>    if vaddress&lt;1&gt; == '1' &amp;&amp; DBGBCR_EL1[n].BAS == '1111' then</line>
<line>        // The above notwithstanding, if DBGBCR_EL1[n].BAS == '1111', then it is CONSTRAINED</line>
<line>        // UNPREDICTABLE whether or not a Breakpoint debug event is generated for an instruction</line>
<line>        // at the address DBGBVR_EL1[n]+2.</line>
<line>        if value_match then value_match = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_BPMATCHHALF" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BPMATCHHALF</a>);</line>
<line></line>
<line>    match = value_match &amp;&amp; state_match &amp;&amp; enabled;</line>
<line></line>
<line>    return match;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/breakpoint/AArch64.BreakpointValueMatch" mylink="aarch64.debug.breakpoint.AArch64.BreakpointValueMatch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.BreakpointValueMatch()</line>
<line>// ==============================</line>
<line></line>
<line link="AArch64.BreakpointValueMatch.3" hover="function: boolean AArch64.BreakpointValueMatch(integer n_in, bits(64) vaddress, boolean linked_to)" conts="AArch64.BreakpointValueMatch">boolean <anchor link="AArch64.BreakpointValueMatch.3" hover="function: boolean AArch64.BreakpointValueMatch(integer n_in, bits(64) vaddress, boolean linked_to)">AArch64.BreakpointValueMatch</anchor>(integer n_in, bits(64) vaddress, boolean linked_to)</line>
<line></line>
<line>    // "n" is the identity of the breakpoint unit to match against.</line>
<line>    // "vaddress" is the current instruction address, ignored if linked_to is TRUE and for Context</line>
<line>    //   matching breakpoints.</line>
<line>    // "linked_to" is TRUE if this is a call from StateMatch for linking.</line>
<line>    integer n = n_in;</line>
<line></line>
<line>    // If a non-existent breakpoint then it is CONSTRAINED UNPREDICTABLE whether this gives</line>
<line>    // no match or the breakpoint is mapped to another UNKNOWN implemented breakpoint.</line>
<line>    if n &gt;= <a link="impl-shared.NumBreakpointsImplemented.0" file="shared_pseudocode.xml" hover="function: integer NumBreakpointsImplemented()">NumBreakpointsImplemented</a>() then</line>
<line>        <a link="Constraint" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint</a> c;</line>
<line>        (c, n) = <a link="impl-shared.ConstrainUnpredictableInteger.3" file="shared_pseudocode.xml" hover="function: (Constraint,integer) ConstrainUnpredictableInteger(integer low, integer high, Unpredictable which)">ConstrainUnpredictableInteger</a>(0, <a link="impl-shared.NumBreakpointsImplemented.0" file="shared_pseudocode.xml" hover="function: integer NumBreakpointsImplemented()">NumBreakpointsImplemented</a>() - 1,</line>
<line>                                               <a link="Unpredictable_BPNOTIMPL" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BPNOTIMPL</a>);</line>
<line>        assert c IN {<a link="Constraint_DISABLED" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_DISABLED</a>, <a link="Constraint_UNKNOWN" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNKNOWN</a>};</line>
<line>        if c == <a link="Constraint_DISABLED" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_DISABLED</a> then return FALSE;</line>
<line></line>
<line>    // If this breakpoint is not enabled, it cannot generate a match. (This could also happen on a</line>
<line>    // call from StateMatch for linking).</line>
<line>    if !<a link="impl-aarch64.IsBreakpointEnabled.1" file="shared_pseudocode.xml" hover="function: boolean IsBreakpointEnabled(integer n)">IsBreakpointEnabled</a>(n) then return FALSE;</line>
<line></line>
<line>    context_aware = <a link="impl-shared.IsContextMatchingBreakpoint.1" file="shared_pseudocode.xml" hover="function: boolean IsContextMatchingBreakpoint(integer n)">IsContextMatchingBreakpoint</a>(n);</line>
<line></line>
<line>    // If BT is set to a reserved type, behaves either as disabled or as a not-reserved type.</line>
<line>    dbgtype = DBGBCR_EL1[n].BT;</line>
<line></line>
<line>    if ((dbgtype IN {'011x','11xx'} &amp;&amp; !<a link="impl-shared.HaveVirtHostExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</a>() &amp;&amp; !<a link="impl-shared.HaveV82Debug.0" file="shared_pseudocode.xml" hover="function: boolean HaveV82Debug()">HaveV82Debug</a>()) || // Context matching</line>
<line>          dbgtype IN {'010x'} ||                                                 // Reserved</line>
<line>          (!(dbgtype IN {'0x0x'}) &amp;&amp; !context_aware) ||                          // Context matching</line>
<line>          (dbgtype IN {'1xxx'} &amp;&amp; !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>))) then                            // EL2 extension</line>
<line>        <a link="Constraint" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint</a> c;</line>
<line>        (c, dbgtype) = <a link="impl-shared.ConstrainUnpredictableBits.2" file="shared_pseudocode.xml" hover="function: (Constraint,bits(width)) ConstrainUnpredictableBits(Unpredictable which, integer width)">ConstrainUnpredictableBits</a>(<a link="Unpredictable_RESBPTYPE" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESBPTYPE</a>, 4);</line>
<line>        assert c IN {<a link="Constraint_DISABLED" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_DISABLED</a>, <a link="Constraint_UNKNOWN" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNKNOWN</a>};</line>
<line>        if c == <a link="Constraint_DISABLED" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_DISABLED</a> then return FALSE;</line>
<line>        // Otherwise the value returned by ConstrainUnpredictableBits must be a not-reserved value</line>
<line></line>
<line>    // Determine what to compare against.</line>
<line>    match_addr = (dbgtype IN {'0x0x'});</line>
<line>    match_vmid = (dbgtype IN {'10xx'});</line>
<line>    match_cid  = (dbgtype IN {'001x'});</line>
<line>    match_cid1 = (dbgtype IN {'101x', 'x11x'});</line>
<line>    match_cid2 = (dbgtype IN {'11xx'});</line>
<line>    linked     = (dbgtype IN {'xxx1'});</line>
<line></line>
<line>    // If this is a call from StateMatch, return FALSE if the breakpoint is not programmed for a</line>
<line>    // VMID and/or context ID match, of if not context-aware. The above assertions mean that the</line>
<line>    // code can just test for match_addr == TRUE to confirm all these things.</line>
<line>    if linked_to &amp;&amp; (!linked || match_addr) then return FALSE;</line>
<line></line>
<line>    // If called from BreakpointMatch return FALSE for Linked context ID and/or VMID matches.</line>
<line>    if !linked_to &amp;&amp; linked &amp;&amp; !match_addr then return FALSE;</line>
<line></line>
<line>    boolean bvr_match  = FALSE;</line>
<line>    boolean bxvr_match = FALSE;</line>
<line></line>
<line>    // Do the comparison.</line>
<line>    if match_addr then</line>
<line>        boolean byte_select_match;</line>
<line>        integer byte = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(vaddress&lt;1:0&gt;);</line>
<line></line>
<line>        if <a link="impl-shared.HaveAArch32.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32()">HaveAArch32</a>() then</line>
<line>            // T32 instructions can be executed at EL0 in an AArch64 translation regime.</line>
<line>            assert byte IN {0,2};                 // "vaddress" is halfword aligned</line>
<line>            byte_select_match = (DBGBCR_EL1[n].BAS&lt;byte&gt; == '1');</line>
<line>        else</line>
<line>            assert byte == 0;                     // "vaddress" is word aligned</line>
<line>            byte_select_match = TRUE;             // DBGBCR_EL1[n].BAS&lt;byte&gt; is RES1</line>
<line></line>
<line>        // If the DBGBVR_EL1[n].RESS field bits are not a sign extension of the MSB</line>
<line>        // of DBGBVR_EL1[n].VA, it is UNPREDICTABLE whether they appear to be</line>
<line>        // included in the match.</line>
<line>        // If 'vaddress' is outside of the current virtual address space, then the access</line>
<line>        // generates a Translation fault.</line>
<line>        integer top = <a link="impl-aarch64.DebugAddrTop.0" file="shared_pseudocode.xml" hover="function: integer DebugAddrTop()">DebugAddrTop</a>();</line>
<line>        if !<a link="impl-shared.IsOnes.1" file="shared_pseudocode.xml" hover="function: boolean IsOnes(bits(N) x)">IsOnes</a>(DBGBVR_EL1[n]&lt;63:top&gt;) &amp;&amp; !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(DBGBVR_EL1[n]&lt;63:top&gt;) then</line>
<line>            if <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_DBGxVR_RESS" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_DBGxVR_RESS</a>) then</line>
<line>                top = 63;</line>
<line>        bvr_match = (vaddress&lt;top:2&gt; == DBGBVR_EL1[n]&lt;top:2&gt;) &amp;&amp; byte_select_match;</line>
<line></line>
<line>    elsif match_cid then</line>
<line>        if <a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>            bvr_match = (CONTEXTIDR_EL2&lt;31:0&gt; == DBGBVR_EL1[n]&lt;31:0&gt;);</line>
<line>        else</line>
<line>            bvr_match = (PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; CONTEXTIDR_EL1&lt;31:0&gt; == DBGBVR_EL1[n]&lt;31:0&gt;);</line>
<line></line>
<line>    elsif match_cid1 then</line>
<line>        bvr_match = (PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() &amp;&amp;</line>
<line>                     CONTEXTIDR_EL1&lt;31:0&gt; == DBGBVR_EL1[n]&lt;31:0&gt;);</line>
<line></line>
<line>    if match_vmid then</line>
<line>        bits(16) vmid;</line>
<line>        bits(16) bvr_vmid;</line>
<line></line>
<line>        if !<a link="impl-shared.Have16bitVMID.0" file="shared_pseudocode.xml" hover="function: boolean Have16bitVMID()">Have16bitVMID</a>() || VTCR_EL2.VS == '0' then</line>
<line>            vmid = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(VTTBR_EL2.VMID&lt;7:0&gt;, 16);</line>
<line>            bvr_vmid = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(DBGBVR_EL1[n]&lt;39:32&gt;, 16);</line>
<line>        else</line>
<line>            vmid     = VTTBR_EL2.VMID;</line>
<line>            bvr_vmid = DBGBVR_EL1[n]&lt;47:32&gt;;</line>
<line></line>
<line>        bxvr_match = (PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() &amp;&amp; vmid == bvr_vmid);</line>
<line></line>
<line>    elsif match_cid2 then</line>
<line>        bxvr_match = (PSTATE.EL != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>                      DBGBVR_EL1[n]&lt;63:32&gt; == CONTEXTIDR_EL2&lt;31:0&gt;);</line>
<line></line>
<line>    bvr_match_valid  = (match_addr || match_cid || match_cid1);</line>
<line>    bxvr_match_valid = (match_vmid || match_cid2);</line>
<line></line>
<line>    match = (!bxvr_match_valid || bxvr_match) &amp;&amp; (!bvr_match_valid || bvr_match);</line>
<line></line>
<line>    return match;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/breakpoint/AArch64.StateMatch" mylink="aarch64.debug.breakpoint.AArch64.StateMatch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.StateMatch()</line>
<line>// ====================</line>
<line>// Determine whether a breakpoint or watchpoint is enabled in the current mode and state.</line>
<line></line>
<line link="AArch64.StateMatch.8" hover="function: boolean AArch64.StateMatch(bits(2) ssc_in, bit ssce_in, bit hmc_in, bits(2) pxc_in, boolean linked_in, bits(4) lbn, boolean isbreakpnt, AccessDescriptor accdesc)" conts="AArch64.StateMatch">boolean <anchor link="AArch64.StateMatch.8" hover="function: boolean AArch64.StateMatch(bits(2) ssc_in, bit ssce_in, bit hmc_in, bits(2) pxc_in, boolean linked_in, bits(4) lbn, boolean isbreakpnt, AccessDescriptor accdesc)">AArch64.StateMatch</anchor>(bits(2) ssc_in, bit ssce_in, bit hmc_in,</line>
<line>                           bits(2) pxc_in, boolean linked_in, bits(4) lbn,</line>
<line>                           boolean isbreakpnt, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    if !<a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then assert ssce_in == '0';</line>
<line></line>
<line>    // "ssc_in","ssce_in","hmc_in","pxc_in" are the control fields from</line>
<line>    // the DBGBCR_EL1[n] or DBGWCR_EL1[n] register.</line>
<line>    // "linked_in" is TRUE if this is a linked breakpoint/watchpoint type.</line>
<line>    // "lbn" is the linked breakpoint number from the DBGBCR_EL1[n] or DBGWCR_EL1[n] register.</line>
<line>    // "isbreakpnt" is TRUE for breakpoints, FALSE for watchpoints.</line>
<line>    // "accdesc" describes the properties of the access being matched.</line>
<line>    bits(2) ssc = ssc_in;</line>
<line>    bit ssce    = ssce_in;</line>
<line>    bit hmc     = hmc_in;</line>
<line>    bits(2) pxc = pxc_in;</line>
<line>    boolean linked = linked_in;</line>
<line></line>
<line>    // If parameters are set to a reserved type, behaves as either disabled or a defined type</line>
<line>    <a link="Constraint" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint</a> c;</line>
<line>    (c, ssc, ssce, hmc, pxc) = <a link="impl-shared.CheckValidStateMatch.5" file="shared_pseudocode.xml" hover="function: (Constraint, bits(2), bit, bit, bits(2)) CheckValidStateMatch(bits(2) ssc_in, bit ssce_in, bit hmc_in, bits(2) pxc_in, boolean isbreakpnt)">CheckValidStateMatch</a>(ssc, ssce, hmc, pxc, isbreakpnt);</line>
<line>    if c == <a link="Constraint_DISABLED" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_DISABLED</a> then return FALSE;</line>
<line>    // Otherwise the hmc,ssc,ssce,pxc values are either valid or the values returned by</line>
<line>    // CheckValidStateMatch are valid.</line>
<line></line>
<line>    EL3_match = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; hmc == '1' &amp;&amp; ssc&lt;0&gt; == '0';</line>
<line>    EL2_match = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; ((hmc == '1' &amp;&amp; (ssc:pxc != '1000')) || ssc == '11');</line>
<line>    EL1_match = pxc&lt;0&gt; == '1';</line>
<line>    EL0_match = pxc&lt;1&gt; == '1';</line>
<line></line>
<line>    boolean priv_match;</line>
<line>    case accdesc.el of</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>  priv_match = EL3_match;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>  priv_match = EL2_match;</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>  priv_match = EL1_match;</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>  priv_match = EL0_match;</line>
<line></line>
<line>    // Security state match</line>
<line>    boolean ss_match;</line>
<line>    case ssce:ssc of</line>
<line>        when '000' ss_match = hmc == '1' || accdesc.ss != <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>;</line>
<line>        when '001' ss_match = accdesc.ss == <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a>;</line>
<line>        when '010' ss_match = (hmc == '1' &amp;&amp; accdesc.ss == <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>) || accdesc.ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>;</line>
<line>        when '011' ss_match = (hmc == '1' &amp;&amp; accdesc.ss != <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>) || accdesc.ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>;</line>
<line>        when '101' ss_match = accdesc.ss == <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>;</line>
<line></line>
<line>    boolean linked_match = FALSE;</line>
<line></line>
<line>    if linked then</line>
<line>        // "lbn" must be an enabled context-aware breakpoint unit. If it is not context-aware then</line>
<line>        // it is CONSTRAINED UNPREDICTABLE whether this gives no match, gives a match without</line>
<line>        // linking, or lbn is mapped to some UNKNOWN breakpoint that is context-aware.</line>
<line>        integer linked_n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(lbn);</line>
<line></line>
<line>        if !<a link="impl-shared.IsContextMatchingBreakpoint.1" file="shared_pseudocode.xml" hover="function: boolean IsContextMatchingBreakpoint(integer n)">IsContextMatchingBreakpoint</a>(linked_n) then</line>
<line>            (first_ctx_cmp, last_ctx_cmp) = <a link="impl-shared.ContextMatchingBreakpointRange.0" file="shared_pseudocode.xml" hover="function: (integer, integer) ContextMatchingBreakpointRange()">ContextMatchingBreakpointRange</a>();</line>
<line>            (c, linked_n) = <a link="impl-shared.ConstrainUnpredictableInteger.3" file="shared_pseudocode.xml" hover="function: (Constraint,integer) ConstrainUnpredictableInteger(integer low, integer high, Unpredictable which)">ConstrainUnpredictableInteger</a>(first_ctx_cmp, last_ctx_cmp,</line>
<line>                                                         <a link="Unpredictable_BPNOTCTXCMP" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BPNOTCTXCMP</a>);</line>
<line>            assert c IN {<a link="Constraint_DISABLED" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_DISABLED</a>, <a link="Constraint_NONE" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NONE</a>, <a link="Constraint_UNKNOWN" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNKNOWN</a>};</line>
<line></line>
<line>            case c of</line>
<line>                when <a link="Constraint_DISABLED" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_DISABLED</a>  return FALSE;      // Disabled</line>
<line>                when <a link="Constraint_NONE" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NONE</a>      linked = FALSE;    // No linking</line>
<line>                // Otherwise ConstrainUnpredictableInteger returned a context-aware breakpoint</line>
<line></line>
<line>        vaddress  = bits(64) UNKNOWN;</line>
<line>        linked_to = TRUE;</line>
<line>        linked_match = <a link="AArch64.BreakpointValueMatch.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.BreakpointValueMatch(integer n_in, bits(64) vaddress, boolean linked_to)">AArch64.BreakpointValueMatch</a>(linked_n, vaddress, linked_to);</line>
<line></line>
<line>    return priv_match &amp;&amp; ss_match &amp;&amp; (!linked || linked_match);</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/breakpoint/DebugAddrTop" mylink="aarch64.debug.breakpoint.DebugAddrTop" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DebugAddrTop()</line>
<line>// ==============</line>
<line>// Returns the value for the top bit used in Breakpoint and Watchpoint address comparisons.</line>
<line></line>
<line link="impl-aarch64.DebugAddrTop.0" hover="function: integer DebugAddrTop()" conts="DebugAddrTop">integer <anchor link="impl-aarch64.DebugAddrTop.0" hover="function: integer DebugAddrTop()">DebugAddrTop</anchor>()</line>
<line>    if <a link="impl-shared.Have56BitVAExt.0" file="shared_pseudocode.xml" hover="function: boolean Have56BitVAExt()">Have56BitVAExt</a>() then</line>
<line>        return 55;</line>
<line>    elsif <a link="impl-shared.Have52BitVAExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitVAExt()">Have52BitVAExt</a>() then</line>
<line>        return 52;</line>
<line>    else</line>
<line>        return 48;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/breakpoint/EffectiveMDSELR_EL1_BANK" mylink="aarch64.debug.breakpoint.EffectiveMDSELR_EL1_BANK" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EffectiveMDSELR_EL1_BANK()</line>
<line>// ==========================</line>
<line>// Return the effective value of MDSELR_EL1.BANK.</line>
<line></line>
<line link="impl-aarch64.EffectiveMDSELR_EL1_BANK.0" hover="function: bits(2) EffectiveMDSELR_EL1_BANK()" conts="EffectiveMDSELR_EL1_BANK">bits(2) <anchor link="impl-aarch64.EffectiveMDSELR_EL1_BANK.0" hover="function: bits(2) EffectiveMDSELR_EL1_BANK()">EffectiveMDSELR_EL1_BANK</anchor>()</line>
<line>    if !<a link="impl-aarch64.SelfHostedExtendedBPWPEnabled.0" file="shared_pseudocode.xml" hover="function: boolean SelfHostedExtendedBPWPEnabled()">SelfHostedExtendedBPWPEnabled</a>() then</line>
<line>        return '00';</line>
<line></line>
<line>    return MDSELR_EL1.BANK;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/breakpoint/IsBreakpointEnabled" mylink="aarch64.debug.breakpoint.IsBreakpointEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsBreakpointEnabled()</line>
<line>// =====================</line>
<line>// Returns TRUE if the effective value of DBGBCR_EL1[n].E is '1', and FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.IsBreakpointEnabled.1" hover="function: boolean IsBreakpointEnabled(integer n)" conts="IsBreakpointEnabled">boolean <anchor link="impl-aarch64.IsBreakpointEnabled.1" hover="function: boolean IsBreakpointEnabled(integer n)">IsBreakpointEnabled</anchor>(integer n)</line>
<line>    if (n &gt; 15 &amp;&amp;</line>
<line>            ((!<a link="impl-shared.HaltOnBreakpointOrWatchpoint.0" file="shared_pseudocode.xml" hover="function: boolean HaltOnBreakpointOrWatchpoint()">HaltOnBreakpointOrWatchpoint</a>() &amp;&amp; !<a link="impl-aarch64.SelfHostedExtendedBPWPEnabled.0" file="shared_pseudocode.xml" hover="function: boolean SelfHostedExtendedBPWPEnabled()">SelfHostedExtendedBPWPEnabled</a>()) ||</line>
<line>            (<a link="impl-shared.HaltOnBreakpointOrWatchpoint.0" file="shared_pseudocode.xml" hover="function: boolean HaltOnBreakpointOrWatchpoint()">HaltOnBreakpointOrWatchpoint</a>() &amp;&amp; EDSCR2.EBWE == '0'))) then</line>
<line>        return FALSE;</line>
<line></line>
<line>    return DBGBCR_EL1[n].E == '1';</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/breakpoint/SelfHostedExtendedBPWPEnabled" mylink="aarch64.debug.breakpoint.SelfHostedExtendedBPWPEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SelfHostedExtendedBPWPEnabled()</line>
<line>// ===============================</line>
<line>// Returns TRUE if the extended breakpoints and watchpoints are enabled, and FALSE otherwise</line>
<line>// from a self-hosted Debug perspective.</line>
<line></line>
<line link="impl-aarch64.SelfHostedExtendedBPWPEnabled.0" hover="function: boolean SelfHostedExtendedBPWPEnabled()" conts="SelfHostedExtendedBPWPEnabled">boolean <anchor link="impl-aarch64.SelfHostedExtendedBPWPEnabled.0" hover="function: boolean SelfHostedExtendedBPWPEnabled()">SelfHostedExtendedBPWPEnabled</anchor>()</line>
<line>    if <a link="impl-shared.NumBreakpointsImplemented.0" file="shared_pseudocode.xml" hover="function: integer NumBreakpointsImplemented()">NumBreakpointsImplemented</a>() &lt;= 16 &amp;&amp; <a link="impl-shared.NumWatchpointsImplemented.0" file="shared_pseudocode.xml" hover="function: integer NumWatchpointsImplemented()">NumWatchpointsImplemented</a>() &lt;= 16 then</line>
<line>        return FALSE;</line>
<line></line>
<line>    if ((<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; MDCR_EL3.EBWE == '0') ||</line>
<line>            (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; MDCR_EL2.EBWE == '0')) then</line>
<line>        return FALSE;</line>
<line></line>
<line>    return MDSCR_EL1.EBWE == '1';</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/enables/AArch64.GenerateDebugExceptions" mylink="aarch64.debug.enables.AArch64.GenerateDebugExceptions" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.GenerateDebugExceptions()</line>
<line>// =================================</line>
<line></line>
<line link="AArch64.GenerateDebugExceptions.0" hover="function: boolean AArch64.GenerateDebugExceptions()" conts="AArch64.GenerateDebugExceptions">boolean <anchor link="AArch64.GenerateDebugExceptions.0" hover="function: boolean AArch64.GenerateDebugExceptions()">AArch64.GenerateDebugExceptions</anchor>()</line>
<line>    ss = <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>();</line>
<line>    return <a link="AArch64.GenerateDebugExceptionsFrom.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.GenerateDebugExceptionsFrom(bits(2) from_el, SecurityState from_state, bit mask)">AArch64.GenerateDebugExceptionsFrom</a>(PSTATE.EL, ss, PSTATE.D);</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/enables/AArch64.GenerateDebugExceptionsFrom" mylink="aarch64.debug.enables.AArch64.GenerateDebugExceptionsFrom" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.GenerateDebugExceptionsFrom()</line>
<line>// =====================================</line>
<line></line>
<line link="AArch64.GenerateDebugExceptionsFrom.3" hover="function: boolean AArch64.GenerateDebugExceptionsFrom(bits(2) from_el, SecurityState from_state, bit mask)" conts="AArch64.GenerateDebugExceptionsFrom">boolean <anchor link="AArch64.GenerateDebugExceptionsFrom.3" hover="function: boolean AArch64.GenerateDebugExceptionsFrom(bits(2) from_el, SecurityState from_state, bit mask)">AArch64.GenerateDebugExceptionsFrom</anchor>(bits(2) from_el, <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> from_state, bit mask)</line>
<line></line>
<line>    if OSLSR_EL1.OSLK == '1' || <a link="impl-shared.DoubleLockStatus.0" file="shared_pseudocode.xml" hover="function: boolean DoubleLockStatus()">DoubleLockStatus</a>() || <a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() then</line>
<line>        return FALSE;</line>
<line></line>
<line>    route_to_el2 = (<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; (from_state != <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> || <a link="impl-shared.IsSecureEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsSecureEL2Enabled()">IsSecureEL2Enabled</a>()) &amp;&amp;</line>
<line>                   (HCR_EL2.TGE == '1' || MDCR_EL2.TDE == '1'));</line>
<line>    target = (if route_to_el2 then <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> else <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line>    boolean enabled;</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; from_state == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>        enabled = MDCR_EL3.SDD == '0';</line>
<line>        if from_el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>            enabled = enabled || SDER32_EL3.SUIDEN == '1';</line>
<line>    else</line>
<line>        enabled = TRUE;</line>
<line></line>
<line>    if from_el == target then</line>
<line>        enabled = enabled &amp;&amp; MDSCR_EL1.KDE == '1' &amp;&amp; mask == '0';</line>
<line>    else</line>
<line>        enabled = enabled &amp;&amp; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(target) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(from_el);</line>
<line></line>
<line>    return enabled;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/ite/AArch64.TRCIT" mylink="aarch64.debug.ite.AArch64.TRCIT" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TRCIT()</line>
<line>// ===============</line>
<line>// Determines whether an Instrumentation trace packet should</line>
<line>// be generated and then generates an instrumentation trace packet</line>
<line>// containing the value of the register passed as an argument</line>
<line></line>
<line link="AArch64.TRCIT.1" hover="function: AArch64.TRCIT(bits(64) Xt)" conts="AArch64.TRCIT"><anchor link="AArch64.TRCIT.1" hover="function: AArch64.TRCIT(bits(64) Xt)">AArch64.TRCIT</anchor>(bits(64) Xt)</line>
<line>    ss = <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>();</line>
<line>    if <a link="impl-shared.TraceInstrumentationAllowed.2" file="shared_pseudocode.xml" hover="function: boolean TraceInstrumentationAllowed(SecurityState ss, bits(2) el)">TraceInstrumentationAllowed</a>(ss, PSTATE.EL) then</line>
<line>        <a link="impl-aarch64.TraceInstrumentation.1" file="shared_pseudocode.xml" hover="function: TraceInstrumentation(bits(64) Xt)">TraceInstrumentation</a>(Xt);</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/ite/TraceInstrumentation" mylink="aarch64.debug.ite.TraceInstrumentation" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TraceInstrumentation()</line>
<line>// ======================</line>
<line>// Generates an instrumentation trace packet</line>
<line>// containing the value of the register passed as an argument</line>
<line></line>
<line link="impl-aarch64.TraceInstrumentation.1" hover="function: TraceInstrumentation(bits(64) Xt)" conts="TraceInstrumentation"><anchor link="impl-aarch64.TraceInstrumentation.1" hover="function: TraceInstrumentation(bits(64) Xt)">TraceInstrumentation</anchor>(bits(64) Xt);</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/pmu/AArch64.ClearEventCounters" mylink="aarch64.debug.pmu.AArch64.ClearEventCounters" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ClearEventCounters()</line>
<line>// ============================</line>
<line>// Zero all the event counters.</line>
<line></line>
<line link="AArch64.ClearEventCounters.0" hover="function: AArch64.ClearEventCounters()" conts="AArch64.ClearEventCounters"><anchor link="AArch64.ClearEventCounters.0" hover="function: AArch64.ClearEventCounters()">AArch64.ClearEventCounters</anchor>()</line>
<line>    integer counters = <a link="AArch64.GetNumEventCountersAccessible.0" file="shared_pseudocode.xml" hover="function: integer AArch64.GetNumEventCountersAccessible()">AArch64.GetNumEventCountersAccessible</a>();</line>
<line>    if counters != 0 then</line>
<line>        for idx = 0 to counters - 1</line>
<line>            PMEVCNTR_EL0[idx] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/pmu/AArch64.GetNumEventCountersAccessible" mylink="aarch64.debug.pmu.AArch64.GetNumEventCountersAccessible" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.GetNumEventCountersAccessible()</line>
<line>// =======================================</line>
<line>// Return the number of event counters that can be accessed at the current Exception level.</line>
<line></line>
<line link="AArch64.GetNumEventCountersAccessible.0" hover="function: integer AArch64.GetNumEventCountersAccessible()" conts="AArch64.GetNumEventCountersAccessible">integer <anchor link="AArch64.GetNumEventCountersAccessible.0" hover="function: integer AArch64.GetNumEventCountersAccessible()">AArch64.GetNumEventCountersAccessible</anchor>()</line>
<line>    integer n;</line>
<line>    integer total_counters = <a link="impl-shared.GetNumEventCounters.0" file="shared_pseudocode.xml" hover="function: integer GetNumEventCounters()">GetNumEventCounters</a>();</line>
<line>    // Software can reserve some counters for EL2</line>
<line>    if PSTATE.EL IN {<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(MDCR_EL2.HPMN);</line>
<line>        if n &gt; total_counters || (!<a link="impl-shared.HaveFeatHPMN0.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatHPMN0()">HaveFeatHPMN0</a>() &amp;&amp; n == 0) then</line>
<line>            (-, n) = <a link="impl-shared.ConstrainUnpredictableInteger.3" file="shared_pseudocode.xml" hover="function: (Constraint,integer) ConstrainUnpredictableInteger(integer low, integer high, Unpredictable which)">ConstrainUnpredictableInteger</a>(0, total_counters,</line>
<line>                                                   <a link="Unpredictable_PMUEVENTCOUNTER" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_PMUEVENTCOUNTER</a>);</line>
<line>    else</line>
<line>        n = total_counters;</line>
<line></line>
<line>    return n;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/pmu/AArch64.IncrementCycleCounter" mylink="aarch64.debug.pmu.AArch64.IncrementCycleCounter" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.IncrementCycleCounter()</line>
<line>// ===============================</line>
<line>// Increment the cycle counter and possibly set overflow bits.</line>
<line></line>
<line link="AArch64.IncrementCycleCounter.0" hover="function: AArch64.IncrementCycleCounter()" conts="AArch64.IncrementCycleCounter"><anchor link="AArch64.IncrementCycleCounter.0" hover="function: AArch64.IncrementCycleCounter()">AArch64.IncrementCycleCounter</anchor>()</line>
<line>    if (<a link="impl-shared.CountPMUEvents.1" file="shared_pseudocode.xml" hover="function: boolean CountPMUEvents(integer idx)">CountPMUEvents</a>(<a link="CYCLE_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer CYCLE_COUNTER_ID = 31">CYCLE_COUNTER_ID</a>) &amp;&amp;</line>
<line>        (!<a link="impl-shared.HaveAArch32.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32()">HaveAArch32</a>() || PMCR_EL0.LC == '1' || PMCR_EL0.D == '0' || <a link="impl-shared.HasElapsed64Cycles.0" file="shared_pseudocode.xml" hover="function: boolean HasElapsed64Cycles()">HasElapsed64Cycles</a>())) then</line>
<line>        integer old_value = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PMCCNTR_EL0);</line>
<line>        integer new_value = old_value + 1;</line>
<line>        PMCCNTR_EL0 = new_value&lt;63:0&gt;;</line>
<line></line>
<line>        integer ovflw;</line>
<line>        if <a link="impl-shared.HaveAArch32.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32()">HaveAArch32</a>() then</line>
<line>            ovflw = if PMCR_EL0.LC == '1' then 64 else 32;</line>
<line>        else</line>
<line>            ovflw = 64;</line>
<line></line>
<line>        if old_value&lt;64:ovflw&gt; != new_value&lt;64:ovflw&gt; then</line>
<line>            PMOVSSET_EL0.C = '1';</line>
<line>            PMOVSCLR_EL0.C = '1';</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/pmu/AArch64.IncrementEventCounter" mylink="aarch64.debug.pmu.AArch64.IncrementEventCounter" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.IncrementEventCounter()</line>
<line>// ===============================</line>
<line>// Increment the specified event counter by the specified amount.</line>
<line></line>
<line link="AArch64.IncrementEventCounter.2" hover="function: AArch64.IncrementEventCounter(integer idx, integer increment)" conts="AArch64.IncrementEventCounter"><anchor link="AArch64.IncrementEventCounter.2" hover="function: AArch64.IncrementEventCounter(integer idx, integer increment)">AArch64.IncrementEventCounter</anchor>(integer idx, integer increment)</line>
<line>    integer old_value;</line>
<line>    integer new_value;</line>
<line>    integer ovflw;</line>
<line>    bit lp;</line>
<line>    old_value = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PMEVCNTR_EL0[idx]);</line>
<line>    new_value = old_value + <a link="impl-shared.PMUCountValue.2" file="shared_pseudocode.xml" hover="function: integer PMUCountValue(integer n, integer Vb)">PMUCountValue</a>(idx, increment);</line>
<line></line>
<line>    if <a link="impl-shared.HavePMUv3p5.0" file="shared_pseudocode.xml" hover="function: boolean HavePMUv3p5()">HavePMUv3p5</a>() then</line>
<line>        PMEVCNTR_EL0[idx] = new_value&lt;63:0&gt;;</line>
<line>        lp = if <a link="impl-shared.PMUCounterIsHyp.1" file="shared_pseudocode.xml" hover="function: boolean PMUCounterIsHyp(integer n)">PMUCounterIsHyp</a>(idx) then MDCR_EL2.HLP else PMCR_EL0.LP;</line>
<line>        ovflw = if lp == '1' then 64 else 32;</line>
<line>    else</line>
<line>        PMEVCNTR_EL0[idx] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(new_value&lt;31:0&gt;, 64);</line>
<line>        ovflw = 32;</line>
<line></line>
<line>    if old_value&lt;64:ovflw&gt; != new_value&lt;64:ovflw&gt; then</line>
<line>        PMOVSSET_EL0&lt;idx&gt; = '1';</line>
<line>        PMOVSCLR_EL0&lt;idx&gt; = '1';</line>
<line>        // Check for the CHAIN event from an even counter</line>
<line>        if idx&lt;0&gt; == '0' &amp;&amp; idx + 1 &lt; <a link="impl-shared.GetNumEventCounters.0" file="shared_pseudocode.xml" hover="function: integer GetNumEventCounters()">GetNumEventCounters</a>() &amp;&amp; (!<a link="impl-shared.HavePMUv3p5.0" file="shared_pseudocode.xml" hover="function: boolean HavePMUv3p5()">HavePMUv3p5</a>() || lp == '0') then</line>
<line>            <a link="impl-shared.PMUEvent.3" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event, integer increment, integer idx)">PMUEvent</a>(PMU_EVENT_CHAIN, 1, idx + 1);</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/pmu/AArch64.PMUCycle" mylink="aarch64.debug.pmu.AArch64.PMUCycle" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.PMUCycle()</line>
<line>// ==================</line>
<line>// Called at the end of each cycle to increment event counters and</line>
<line>// check for PMU overflow. In pseudocode, a cycle ends after the</line>
<line>// execution of the operational pseudocode.</line>
<line></line>
<line link="AArch64.PMUCycle.0" hover="function: AArch64.PMUCycle()" conts="AArch64.PMUCycle"><anchor link="AArch64.PMUCycle.0" hover="function: AArch64.PMUCycle()">AArch64.PMUCycle</anchor>()</line>
<line>    if !<a link="impl-shared.HavePMUv3.0" file="shared_pseudocode.xml" hover="function: boolean HavePMUv3()">HavePMUv3</a>() then</line>
<line>        return;</line>
<line></line>
<line>    <a link="impl-shared.PMUEvent.1" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event)">PMUEvent</a>(PMU_EVENT_CPU_CYCLES);</line>
<line></line>
<line>    integer counters = <a link="impl-shared.GetNumEventCounters.0" file="shared_pseudocode.xml" hover="function: integer GetNumEventCounters()">GetNumEventCounters</a>();</line>
<line>    if counters != 0 then</line>
<line>        for idx = 0 to counters - 1</line>
<line>            if <a link="impl-shared.CountPMUEvents.1" file="shared_pseudocode.xml" hover="function: boolean CountPMUEvents(integer idx)">CountPMUEvents</a>(idx) then</line>
<line>                integer accumulated = PMUEventAccumulator[idx];</line>
<line>                <a link="AArch64.IncrementEventCounter.2" file="shared_pseudocode.xml" hover="function: AArch64.IncrementEventCounter(integer idx, integer increment)">AArch64.IncrementEventCounter</a>(idx, accumulated);</line>
<line>            PMUEventAccumulator[idx] = 0;</line>
<line></line>
<line>    <a link="AArch64.IncrementCycleCounter.0" file="shared_pseudocode.xml" hover="function: AArch64.IncrementCycleCounter()">AArch64.IncrementCycleCounter</a>();</line>
<line>    <a link="impl-shared.CheckForPMUOverflow.0" file="shared_pseudocode.xml" hover="function: CheckForPMUOverflow()">CheckForPMUOverflow</a>();</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/pmu/AArch64.PMUSwIncrement" mylink="aarch64.debug.pmu.AArch64.PMUSwIncrement" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.PMUSwIncrement()</line>
<line>// ========================</line>
<line>// Generate PMU Events on a write to PMSWINC_EL0.</line>
<line></line>
<line link="AArch64.PMUSwIncrement.1" hover="function: AArch64.PMUSwIncrement(bits(32) sw_incr)" conts="AArch64.PMUSwIncrement"><anchor link="AArch64.PMUSwIncrement.1" hover="function: AArch64.PMUSwIncrement(bits(32) sw_incr)">AArch64.PMUSwIncrement</anchor>(bits(32) sw_incr)</line>
<line>    integer counters = <a link="AArch64.GetNumEventCountersAccessible.0" file="shared_pseudocode.xml" hover="function: integer AArch64.GetNumEventCountersAccessible()">AArch64.GetNumEventCountersAccessible</a>();</line>
<line>    if counters != 0 then</line>
<line>        for idx = 0 to counters - 1</line>
<line>            if sw_incr&lt;idx&gt; == '1' then</line>
<line>                <a link="impl-shared.PMUEvent.3" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event, integer increment, integer idx)">PMUEvent</a>(PMU_EVENT_SW_INCR, 1, idx);</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/CollectContextIDR1" mylink="aarch64.debug.statisticalprofiling.CollectContextIDR1" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CollectContextIDR1()</line>
<line>// ====================</line>
<line></line>
<line link="impl-aarch64.CollectContextIDR1.0" hover="function: boolean CollectContextIDR1()" conts="CollectContextIDR1">boolean <anchor link="impl-aarch64.CollectContextIDR1.0" hover="function: boolean CollectContextIDR1()">CollectContextIDR1</anchor>()</line>
<line>    if !<a link="impl-aarch64.StatisticalProfilingEnabled.0" file="shared_pseudocode.xml" hover="function: boolean StatisticalProfilingEnabled()">StatisticalProfilingEnabled</a>() then return FALSE;</line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then return FALSE;</line>
<line>    if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1' then return FALSE;</line>
<line>    return PMSCR_EL1.CX == '1';</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/CollectContextIDR2" mylink="aarch64.debug.statisticalprofiling.CollectContextIDR2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CollectContextIDR2()</line>
<line>// ====================</line>
<line></line>
<line link="impl-aarch64.CollectContextIDR2.0" hover="function: boolean CollectContextIDR2()" conts="CollectContextIDR2">boolean <anchor link="impl-aarch64.CollectContextIDR2.0" hover="function: boolean CollectContextIDR2()">CollectContextIDR2</anchor>()</line>
<line>    if !<a link="impl-aarch64.StatisticalProfilingEnabled.0" file="shared_pseudocode.xml" hover="function: boolean StatisticalProfilingEnabled()">StatisticalProfilingEnabled</a>() then return FALSE;</line>
<line>    if !<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then return FALSE;</line>
<line>    return PMSCR_EL2.CX == '1';</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/CollectPhysicalAddress" mylink="aarch64.debug.statisticalprofiling.CollectPhysicalAddress" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CollectPhysicalAddress()</line>
<line>// ========================</line>
<line></line>
<line link="impl-aarch64.CollectPhysicalAddress.0" hover="function: boolean CollectPhysicalAddress()" conts="CollectPhysicalAddress">boolean <anchor link="impl-aarch64.CollectPhysicalAddress.0" hover="function: boolean CollectPhysicalAddress()">CollectPhysicalAddress</anchor>()</line>
<line>    if !<a link="impl-aarch64.StatisticalProfilingEnabled.0" file="shared_pseudocode.xml" hover="function: boolean StatisticalProfilingEnabled()">StatisticalProfilingEnabled</a>() then return FALSE;</line>
<line>    (owning_ss, owning_el) = <a link="impl-aarch64.ProfilingBufferOwner.0" file="shared_pseudocode.xml" hover="function: (SecurityState, bits(2)) ProfilingBufferOwner()">ProfilingBufferOwner</a>();</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; (owning_ss != <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> || <a link="impl-shared.IsSecureEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsSecureEL2Enabled()">IsSecureEL2Enabled</a>()) then</line>
<line>        return PMSCR_EL2.PA == '1' &amp;&amp; (owning_el == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || PMSCR_EL1.PA == '1');</line>
<line>    else</line>
<line>        return PMSCR_EL1.PA == '1';</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/CollectTimeStamp" mylink="aarch64.debug.statisticalprofiling.CollectTimeStamp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CollectTimeStamp()</line>
<line>// ==================</line>
<line></line>
<line link="impl-aarch64.CollectTimeStamp.0" hover="function: TimeStamp CollectTimeStamp()" conts="CollectTimeStamp">TimeStamp <anchor link="impl-aarch64.CollectTimeStamp.0" hover="function: TimeStamp CollectTimeStamp()">CollectTimeStamp</anchor>()</line>
<line>    if !<a link="impl-aarch64.StatisticalProfilingEnabled.0" file="shared_pseudocode.xml" hover="function: boolean StatisticalProfilingEnabled()">StatisticalProfilingEnabled</a>() then return <a link="TimeStamp_None" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_None</a>;</line>
<line>    (-, owning_el) = <a link="impl-aarch64.ProfilingBufferOwner.0" file="shared_pseudocode.xml" hover="function: (SecurityState, bits(2)) ProfilingBufferOwner()">ProfilingBufferOwner</a>();</line>
<line></line>
<line>    if owning_el == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>        if PMSCR_EL2.TS == '0' then return <a link="TimeStamp_None" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_None</a>;</line>
<line>    else</line>
<line>        if PMSCR_EL1.TS == '0' then return <a link="TimeStamp_None" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_None</a>;</line>
<line></line>
<line>    bits(2) PCT_el1;</line>
<line>    if !<a link="impl-shared.HaveECVExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveECVExt()">HaveECVExt</a>() then</line>
<line>        PCT_el1 = '0':PMSCR_EL1.PCT&lt;0&gt;;       // PCT&lt;1&gt; is RES0</line>
<line>    else</line>
<line>        PCT_el1 = PMSCR_EL1.PCT;</line>
<line>        if PCT_el1 == '10' then</line>
<line>            // Reserved value</line>
<line>            (-, PCT_el1) = <a link="impl-shared.ConstrainUnpredictableBits.2" file="shared_pseudocode.xml" hover="function: (Constraint,bits(width)) ConstrainUnpredictableBits(Unpredictable which, integer width)">ConstrainUnpredictableBits</a>(<a link="Unpredictable_PMSCR_PCT" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_PMSCR_PCT</a>, 2);</line>
<line>    if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        bits(2) PCT_el2;</line>
<line>        if !<a link="impl-shared.HaveECVExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveECVExt()">HaveECVExt</a>() then</line>
<line>            PCT_el2 = '0':PMSCR_EL2.PCT&lt;0&gt;;   // PCT&lt;1&gt; is RES0</line>
<line>        else</line>
<line>            PCT_el2 = PMSCR_EL2.PCT;</line>
<line>            if PCT_el2 == '10' then</line>
<line>                // Reserved value</line>
<line>                (-, PCT_el2) = <a link="impl-shared.ConstrainUnpredictableBits.2" file="shared_pseudocode.xml" hover="function: (Constraint,bits(width)) ConstrainUnpredictableBits(Unpredictable which, integer width)">ConstrainUnpredictableBits</a>(<a link="Unpredictable_PMSCR_PCT" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_PMSCR_PCT</a>, 2);</line>
<line>        case PCT_el2 of</line>
<line>            when '00'</line>
<line>                return if <a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then <a link="TimeStamp_Physical" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_Physical</a> else <a link="TimeStamp_Virtual" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_Virtual</a>;</line>
<line>            when '01'</line>
<line>                if owning_el == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then return <a link="TimeStamp_Physical" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_Physical</a>;</line>
<line>            when '11'</line>
<line>                assert <a link="impl-shared.HaveECVExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveECVExt()">HaveECVExt</a>();          // FEAT_ECV must be implemented</line>
<line>                if owning_el == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; PCT_el1 == '00' then</line>
<line>                    return if <a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then <a link="TimeStamp_Physical" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_Physical</a> else <a link="TimeStamp_Virtual" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_Virtual</a>;</line>
<line>                else</line>
<line>                    return <a link="TimeStamp_OffsetPhysical" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_OffsetPhysical</a>;</line>
<line>            otherwise</line>
<line>                <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    case PCT_el1 of</line>
<line>        when '00' return if <a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then <a link="TimeStamp_Physical" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_Physical</a> else <a link="TimeStamp_Virtual" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_Virtual</a>;</line>
<line>        when '01' return <a link="TimeStamp_Physical" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_Physical</a>;</line>
<line>        when '11'</line>
<line>            assert <a link="impl-shared.HaveECVExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveECVExt()">HaveECVExt</a>();              // FEAT_ECV must be implemented</line>
<line>            return <a link="TimeStamp_OffsetPhysical" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_OffsetPhysical</a>;</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/OpType" mylink="aarch64.debug.statisticalprofiling.OpType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// OpType</line>
<line>// ======</line>
<line>// Types of operation filtered by SPECollectRecord().</line>
<line></line>
<line link="OpType" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }" conts="OpType">enumeration <anchor link="OpType" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType</anchor> {</line>
<line link="OpType_Load" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }" conts="OpType_Load">    <anchor link="OpType_Load" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_Load</anchor>,        // Any memory-read operation other than atomics, compare-and-swap, and swap</line>
<line link="OpType_Store" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }" conts="OpType_Store">    <anchor link="OpType_Store" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_Store</anchor>,       // Any memory-write operation, including atomics without return</line>
<line link="OpType_LoadAtomic" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }" conts="OpType_LoadAtomic">    <anchor link="OpType_LoadAtomic" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_LoadAtomic</anchor>,  // Atomics with return, compare-and-swap and swap</line>
<line link="OpType_Branch" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }" conts="OpType_Branch">    <anchor link="OpType_Branch" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_Branch</anchor>,      // Software write to the PC</line>
<line link="OpType_Other" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }" conts="OpType_Other">    <anchor link="OpType_Other" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_Other</anchor>        // Any other class of operation</line>
<line>};</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/ProfilingBufferEnabled" mylink="aarch64.debug.statisticalprofiling.ProfilingBufferEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ProfilingBufferEnabled()</line>
<line>// ========================</line>
<line></line>
<line link="impl-aarch64.ProfilingBufferEnabled.0" hover="function: boolean ProfilingBufferEnabled()" conts="ProfilingBufferEnabled">boolean <anchor link="impl-aarch64.ProfilingBufferEnabled.0" hover="function: boolean ProfilingBufferEnabled()">ProfilingBufferEnabled</anchor>()</line>
<line>    if !<a link="impl-shared.HaveStatisticalProfiling.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfiling()">HaveStatisticalProfiling</a>() then return FALSE;</line>
<line>    (owning_ss, owning_el) = <a link="impl-aarch64.ProfilingBufferOwner.0" file="shared_pseudocode.xml" hover="function: (SecurityState, bits(2)) ProfilingBufferOwner()">ProfilingBufferOwner</a>();</line>
<line>    bits(2) state_bits;</line>
<line>    if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then</line>
<line>        state_bits = SCR_EL3.NSE : <a link="impl-shared.EffectiveSCR_EL3_NS.0" file="shared_pseudocode.xml" hover="function: bit EffectiveSCR_EL3_NS()">EffectiveSCR_EL3_NS</a>();</line>
<line>    else</line>
<line>        state_bits = '0' : SCR_EL3.NS;</line>
<line></line>
<line>    boolean state_match;</line>
<line>    case owning_ss of</line>
<line>        when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>    state_match = state_bits == '00';</line>
<line>        when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> state_match = state_bits == '01';</line>
<line>        when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>     state_match = state_bits == '11';</line>
<line>    return (!<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(owning_el) &amp;&amp; state_match &amp;&amp;</line>
<line>            PMBLIMITR_EL1.E == '1' &amp;&amp; PMBSR_EL1.S == '0');</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/ProfilingBufferOwner" mylink="aarch64.debug.statisticalprofiling.ProfilingBufferOwner" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ProfilingBufferOwner()</line>
<line>// ======================</line>
<line></line>
<line link="impl-aarch64.ProfilingBufferOwner.0" hover="function: (SecurityState, bits(2)) ProfilingBufferOwner()" conts="ProfilingBufferOwner">(SecurityState, bits(2)) <anchor link="impl-aarch64.ProfilingBufferOwner.0" hover="function: (SecurityState, bits(2)) ProfilingBufferOwner()">ProfilingBufferOwner</anchor>()</line>
<line>    <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> owning_ss;</line>
<line></line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        bits(3) state_bits;</line>
<line>        if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then</line>
<line>            state_bits = MDCR_EL3.&lt;NSPBE,NSPB&gt;;</line>
<line>            if (state_bits IN {'10x'} ||</line>
<line>                (!<a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>() &amp;&amp; state_bits IN {'00x'})) then</line>
<line>                // Reserved value</line>
<line>                (-, state_bits) = <a link="impl-shared.ConstrainUnpredictableBits.2" file="shared_pseudocode.xml" hover="function: (Constraint,bits(width)) ConstrainUnpredictableBits(Unpredictable which, integer width)">ConstrainUnpredictableBits</a>(<a link="Unpredictable_RESERVEDNSxB" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESERVEDNSxB</a>, 3);</line>
<line>        else</line>
<line>            state_bits = '0' : MDCR_EL3.NSPB;</line>
<line></line>
<line>        case state_bits of</line>
<line>            when '00x' owning_ss = <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>;</line>
<line>            when '01x' owning_ss = <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a>;</line>
<line>            when '11x' owning_ss = <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>;</line>
<line>    else</line>
<line>        owning_ss = if <a link="impl-shared.SecureOnlyImplementation.0" file="shared_pseudocode.xml" hover="function: boolean SecureOnlyImplementation()">SecureOnlyImplementation</a>() then <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> else <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a>;</line>
<line></line>
<line>    bits(2) owning_el;</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; (owning_ss != <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> || <a link="impl-shared.IsSecureEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsSecureEL2Enabled()">IsSecureEL2Enabled</a>()) then</line>
<line>        owning_el = if MDCR_EL2.E2PB == '00' then <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> else <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>    else</line>
<line>        owning_el = <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line></line>
<line>    return (owning_ss, owning_el);</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/ProfilingSynchronizationBarrier" mylink="aarch64.debug.statisticalprofiling.ProfilingSynchronizationBarrier" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ProfilingSynchronizationBarrier()</line>
<line>// =================================</line>
<line>// Barrier to ensure that all existing profiling data has been formatted, and profiling buffer</line>
<line>// addresses have been translated such that writes to the profiling buffer have been initiated.</line>
<line>// A following DSB completes when writes to the profiling buffer have completed.</line>
<line></line>
<line link="impl-aarch64.ProfilingSynchronizationBarrier.0" hover="function: ProfilingSynchronizationBarrier()" conts="ProfilingSynchronizationBarrier"><anchor link="impl-aarch64.ProfilingSynchronizationBarrier.0" hover="function: ProfilingSynchronizationBarrier()">ProfilingSynchronizationBarrier</anchor>();</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEAddByteToRecord" mylink="aarch64.debug.statisticalprofiling.SPEAddByteToRecord" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPEAddByteToRecord()</line>
<line>// ====================</line>
<line>// Add one byte to a record and increase size property appropriately.</line>
<line></line>
<line link="impl-aarch64.SPEAddByteToRecord.1" hover="function: SPEAddByteToRecord(bits(8) b)" conts="SPEAddByteToRecord"><anchor link="impl-aarch64.SPEAddByteToRecord.1" hover="function: SPEAddByteToRecord(bits(8) b)">SPEAddByteToRecord</anchor>(bits(8) b)</line>
<line>    assert SPERecordSize &lt; <a link="SPEMaxRecordSize" file="shared_pseudocode.xml" hover="constant integer SPEMaxRecordSize = 64">SPEMaxRecordSize</a>;</line>
<line>    SPERecordData[SPERecordSize] = b;</line>
<line>    SPERecordSize = SPERecordSize + 1;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEAddPacketToRecord" mylink="aarch64.debug.statisticalprofiling.SPEAddPacketToRecord" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPEAddPacketToRecord()</line>
<line>// ======================</line>
<line>// Add passed header and payload data to the record.</line>
<line>// Payload must be a multiple of 8.</line>
<line></line>
<line link="impl-aarch64.SPEAddPacketToRecord.3" hover="function: SPEAddPacketToRecord(bits(2) header_hi, bits(4) header_lo, bits(N) payload)" conts="SPEAddPacketToRecord"><anchor link="impl-aarch64.SPEAddPacketToRecord.3" hover="function: SPEAddPacketToRecord(bits(2) header_hi, bits(4) header_lo, bits(N) payload)">SPEAddPacketToRecord</anchor>(bits(2) header_hi, bits(4) header_lo,</line>
<line>                        bits(N) payload)</line>
<line>    assert N MOD 8 == 0;</line>
<line>    bits(2) sz;</line>
<line>    case N of</line>
<line>        when 8 sz = '00';</line>
<line>        when 16 sz = '01';</line>
<line>        when 32 sz = '10';</line>
<line>        when 64 sz = '11';</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    bits(8) header = header_hi:sz:header_lo;</line>
<line>    <a link="impl-aarch64.SPEAddByteToRecord.1" file="shared_pseudocode.xml" hover="function: SPEAddByteToRecord(bits(8) b)">SPEAddByteToRecord</a>(header);</line>
<line>    for i = 0 to (N DIV 8)-1</line>
<line>        <a link="impl-aarch64.SPEAddByteToRecord.1" file="shared_pseudocode.xml" hover="function: SPEAddByteToRecord(bits(8) b)">SPEAddByteToRecord</a>(payload&lt;i*8+7:i*8&gt;);</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEBranch" mylink="aarch64.debug.statisticalprofiling.SPEBranch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPEBranch()</line>
<line>// ===========</line>
<line>// Called on every branch if SPE is present. Maintains previous branch target</line>
<line>// and branch related SPE functionality.</line>
<line></line>
<line link="impl-aarch64.SPEBranch.4" hover="function: SPEBranch(bits(N) target, BranchType branch_type, boolean conditional, boolean taken_flag)" conts="SPEBranch"><anchor link="impl-aarch64.SPEBranch.4" hover="function: SPEBranch(bits(N) target, BranchType branch_type, boolean conditional, boolean taken_flag)">SPEBranch</anchor>(bits(N) target, <a link="BranchType" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType</a> branch_type, boolean conditional, boolean taken_flag)</line>
<line>    boolean is_isb = FALSE;</line>
<line>    <a link="impl-aarch64.SPEBranch.5" file="shared_pseudocode.xml" hover="function: SPEBranch(bits(N) target, BranchType branch_type, boolean conditional, boolean taken_flag, boolean is_isb)">SPEBranch</a>(target, branch_type, conditional, taken_flag, is_isb);</line>
<line></line>
<line link="impl-aarch64.SPEBranch.5" hover="function: SPEBranch(bits(N) target, BranchType branch_type, boolean conditional, boolean taken_flag, boolean is_isb)" conts="SPEBranch"><anchor link="impl-aarch64.SPEBranch.5" hover="function: SPEBranch(bits(N) target, BranchType branch_type, boolean conditional, boolean taken_flag, boolean is_isb)">SPEBranch</anchor>(bits(N) target, <a link="BranchType" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType</a> branch_type, boolean conditional, boolean taken_flag,</line>
<line>          boolean is_isb)</line>
<line>    // If the PE implements branch prediction, data about (mis)prediction is collected</line>
<line>    // through the PMU events.</line>
<line></line>
<line>    boolean collect_prev_br;</line>
<line>    boolean collect_prev_br_eret = boolean IMPLEMENTATION_DEFINED "SPE prev br on eret";</line>
<line>    boolean collect_prev_br_exception = boolean IMPLEMENTATION_DEFINED "SPE prev br on exception";</line>
<line>    boolean collect_prev_br_isb = boolean IMPLEMENTATION_DEFINED "SPE prev br on isb";</line>
<line>    case branch_type of</line>
<line>        when <a link="BranchType_EXCEPTION" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_EXCEPTION</a></line>
<line>            collect_prev_br = collect_prev_br_exception;</line>
<line>        when <a link="BranchType_ERET" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_ERET</a></line>
<line>            collect_prev_br = collect_prev_br_eret;</line>
<line>        otherwise</line>
<line>            collect_prev_br = !is_isb || collect_prev_br_isb;</line>
<line></line>
<line>    // Implements previous branch target functionality</line>
<line>    if (taken_flag &amp;&amp; !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(PMSIDR_EL1.PBT) &amp;&amp; <a link="impl-aarch64.StatisticalProfilingEnabled.0" file="shared_pseudocode.xml" hover="function: boolean StatisticalProfilingEnabled()">StatisticalProfilingEnabled</a>() &amp;&amp;</line>
<line>            collect_prev_br) then</line>
<line></line>
<line>        if SPESampleInFlight then</line>
<line>            // Save the target address for it to be added to record.</line>
<line>            bits(64) previous_target = SPESamplePreviousBranchAddress;</line>
<line>            SPESampleAddress[<a link="SPEAddrPosPrevBranchTarget" file="shared_pseudocode.xml" hover="constant integer SPEAddrPosPrevBranchTarget = 4">SPEAddrPosPrevBranchTarget</a>]&lt;63:0&gt; = previous_target&lt;63:0&gt;;</line>
<line>            boolean previous_branch_valid = SPESamplePreviousBranchAddressValid;</line>
<line>            SPESampleAddressValid[<a link="SPEAddrPosPrevBranchTarget" file="shared_pseudocode.xml" hover="constant integer SPEAddrPosPrevBranchTarget = 4">SPEAddrPosPrevBranchTarget</a>] = previous_branch_valid;</line>
<line>        SPESamplePreviousBranchAddress&lt;55:0&gt; = target&lt;55:0&gt;;</line>
<line></line>
<line>        bit ns;</line>
<line>        bit nse;</line>
<line>        case <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() of</line>
<line>            when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a></line>
<line>                ns = '0';</line>
<line>                nse = '0';</line>
<line>            when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a></line>
<line>                ns = '1';</line>
<line>                nse = '0';</line>
<line>            when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a></line>
<line>                ns = '1';</line>
<line>                nse = '1';</line>
<line>            otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>        SPESamplePreviousBranchAddress&lt;63&gt; = ns;</line>
<line>        SPESamplePreviousBranchAddress&lt;60&gt; = nse;</line>
<line>        SPESamplePreviousBranchAddress&lt;62:61&gt; = PSTATE.EL;</line>
<line>        SPESamplePreviousBranchAddressValid = TRUE;</line>
<line></line>
<line>    if !<a link="impl-aarch64.StatisticalProfilingEnabled.0" file="shared_pseudocode.xml" hover="function: boolean StatisticalProfilingEnabled()">StatisticalProfilingEnabled</a>() then</line>
<line>        if taken_flag then</line>
<line>            // Invalidate previous branch address, if profiling is disabled</line>
<line>            // or prohibited.</line>
<line>            SPESamplePreviousBranchAddressValid = FALSE;</line>
<line>        return;</line>
<line></line>
<line>    if SPESampleInFlight then</line>
<line>        is_direct = branch_type IN {<a link="BranchType_DIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</a>, <a link="BranchType_DIRCALL" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIRCALL</a>};</line>
<line>        SPESampleClass = '10';</line>
<line>        SPESampleSubclass&lt;1&gt; = if is_direct then '0' else '1';</line>
<line>        SPESampleSubclass&lt;0&gt; = if conditional then '1' else '0';</line>
<line>        SPESampleOpType = <a link="OpType_Branch" file="shared_pseudocode.xml" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_Branch</a>;</line>
<line></line>
<line>        // Save the target address.</line>
<line>        if taken_flag then</line>
<line>            SPESampleAddress[<a link="SPEAddrPosBranchTarget" file="shared_pseudocode.xml" hover="constant integer SPEAddrPosBranchTarget = 1">SPEAddrPosBranchTarget</a>]&lt;55:0&gt; = target&lt;55:0&gt;;</line>
<line></line>
<line>            bit ns;</line>
<line>            bit nse;</line>
<line>            case <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() of</line>
<line>                when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a></line>
<line>                    ns = '0';</line>
<line>                    nse = '0';</line>
<line>                when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a></line>
<line>                    ns = '1';</line>
<line>                    nse = '0';</line>
<line>                when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a></line>
<line>                    ns = '1';</line>
<line>                    nse = '1';</line>
<line>                otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>            SPESampleAddress[<a link="SPEAddrPosBranchTarget" file="shared_pseudocode.xml" hover="constant integer SPEAddrPosBranchTarget = 1">SPEAddrPosBranchTarget</a>]&lt;63&gt; = ns;</line>
<line>            SPESampleAddress[<a link="SPEAddrPosBranchTarget" file="shared_pseudocode.xml" hover="constant integer SPEAddrPosBranchTarget = 1">SPEAddrPosBranchTarget</a>]&lt;60&gt; = nse;</line>
<line>            SPESampleAddress[<a link="SPEAddrPosBranchTarget" file="shared_pseudocode.xml" hover="constant integer SPEAddrPosBranchTarget = 1">SPEAddrPosBranchTarget</a>]&lt;62:61&gt; = PSTATE.EL;</line>
<line>            SPESampleAddressValid[<a link="SPEAddrPosBranchTarget" file="shared_pseudocode.xml" hover="constant integer SPEAddrPosBranchTarget = 1">SPEAddrPosBranchTarget</a>] = TRUE;</line>
<line></line>
<line>        SPESampleEvents&lt;6&gt; = if !taken_flag then '1' else '0';</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEBufferFilled" mylink="aarch64.debug.statisticalprofiling.SPEBufferFilled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPEBufferFilled()</line>
<line>// =================</line>
<line>// Deal with a full buffer event.</line>
<line></line>
<line link="impl-aarch64.SPEBufferFilled.0" hover="function: SPEBufferFilled()" conts="SPEBufferFilled"><anchor link="impl-aarch64.SPEBufferFilled.0" hover="function: SPEBufferFilled()">SPEBufferFilled</anchor>()</line>
<line>    if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(PMBSR_EL1.S) then</line>
<line>        PMBSR_EL1.S = '1';                          // Assert PMBIRQ</line>
<line>        PMBSR_EL1.EC = '000000';                    // Other buffer management event</line>
<line>        PMBSR_EL1.MSS = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('000001', 16);   // Set buffer full event</line>
<line></line>
<line>    <a link="impl-shared.PMUEvent.1" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event)">PMUEvent</a>(PMU_EVENT_SAMPLE_WRAP);</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEBufferIsFull" mylink="aarch64.debug.statisticalprofiling.SPEBufferIsFull" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPEBufferIsFull()</line>
<line>// =================</line>
<line>// Return true if another full size sample record would not fit in the</line>
<line>// profiling buffer.</line>
<line></line>
<line link="impl-aarch64.SPEBufferIsFull.0" hover="function: boolean SPEBufferIsFull()" conts="SPEBufferIsFull">boolean <anchor link="impl-aarch64.SPEBufferIsFull.0" hover="function: boolean SPEBufferIsFull()">SPEBufferIsFull</anchor>()</line>
<line>    integer write_pointer_limit = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PMBLIMITR_EL1.LIMIT:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12));</line>
<line>    integer current_write_pointer = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PMBPTR_EL1);</line>
<line>    integer record_max_size = 1&lt;&lt;<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PMSIDR_EL1.MaxSize);</line>
<line>    return current_write_pointer &gt; (write_pointer_limit - record_max_size);</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPECollectRecord" mylink="aarch64.debug.statisticalprofiling.SPECollectRecord" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPECollectRecord()</line>
<line>// ==================</line>
<line>// Returns TRUE if the sampled class of instructions or operations, as</line>
<line>// determined by PMSFCR_EL1, are recorded and FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.SPECollectRecord.3" hover="function: boolean SPECollectRecord(bits(64) events, integer total_latency, OpType optype)" conts="SPECollectRecord">boolean <anchor link="impl-aarch64.SPECollectRecord.3" hover="function: boolean SPECollectRecord(bits(64) events, integer total_latency, OpType optype)">SPECollectRecord</anchor>(bits(64) events, integer total_latency, <a link="OpType" file="shared_pseudocode.xml" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType</a> optype)</line>
<line>    assert <a link="impl-aarch64.StatisticalProfilingEnabled.0" file="shared_pseudocode.xml" hover="function: boolean StatisticalProfilingEnabled()">StatisticalProfilingEnabled</a>();</line>
<line></line>
<line>    bits(64) mask = 0xAA&lt;63:0&gt;;                             // Bits [7,5,3,1]</line>
<line>    bits(64) e;</line>
<line>    bits(64) m;</line>
<line>    if <a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() then mask&lt;18:17&gt; = '11';                   // Predicate flags</line>
<line>    if <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() then mask&lt;16&gt; = '1';</line>
<line>    if <a link="impl-shared.HaveStatisticalProfilingv1p1.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p1()">HaveStatisticalProfilingv1p1</a>() then mask&lt;11&gt; = '1';  // Alignment Flag</line>
<line>    if <a link="impl-shared.HaveStatisticalProfilingv1p2.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p2()">HaveStatisticalProfilingv1p2</a>() then mask&lt;6&gt; = '1';   // Not taken flag</line>
<line>    if <a link="impl-shared.HaveStatisticalProfilingv1p4.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p4()">HaveStatisticalProfilingv1p4</a>() then</line>
<line>        mask&lt;10:8,4,2&gt; = '11111';</line>
<line>    else</line>
<line>        bits(5) impdef_mask;</line>
<line>        impdef_mask = bits(5) IMPLEMENTATION_DEFINED "SPE mask 10:8,4,2";</line>
<line>        mask&lt;10:8,4,2&gt; = impdef_mask;</line>
<line></line>
<line>    mask&lt;63:48&gt; = bits(16) IMPLEMENTATION_DEFINED "SPE mask 63:48";</line>
<line>    mask&lt;31:24&gt; = bits(8) IMPLEMENTATION_DEFINED "SPE mask 31:24";</line>
<line>    mask&lt;15:12&gt; = bits(4) IMPLEMENTATION_DEFINED "SPE mask 15:12";</line>
<line></line>
<line>    e = events AND mask;</line>
<line>    boolean is_rejected_nevent = FALSE;</line>
<line>    boolean is_nevt;</line>
<line>    // Filtering by inverse event</line>
<line>    if <a link="impl-shared.HaveStatisticalProfilingv1p2.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p2()">HaveStatisticalProfilingv1p2</a>() then</line>
<line>        m = PMSNEVFR_EL1 AND mask;</line>
<line>        is_nevt = <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(e AND m);</line>
<line>        if PMSFCR_EL1.FnE == '1' then</line>
<line>            // Inverse filtering by event is enabled</line>
<line>            if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(m) then</line>
<line>                // Not UNPREDICTABLE case</line>
<line>                is_rejected_nevent = !is_nevt;</line>
<line>            else</line>
<line>                is_rejected_nevent = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_BADPMSFCR" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BADPMSFCR</a>);</line>
<line>    else</line>
<line>        is_nevt = TRUE; // not implemented</line>
<line></line>
<line>    boolean is_rejected_event = FALSE;</line>
<line></line>
<line>    // Filtering by event</line>
<line>    m = PMSEVFR_EL1 AND mask;</line>
<line>    boolean is_evt = <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(NOT(e) AND m);</line>
<line>    if PMSFCR_EL1.FE == '1' then</line>
<line>        // Filtering by event is enabled</line>
<line>        if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(m) then</line>
<line>            // Not UNPREDICTABLE case</line>
<line>            is_rejected_event = !is_evt;</line>
<line>        else</line>
<line>            is_rejected_event = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_BADPMSFCR" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BADPMSFCR</a>);</line>
<line></line>
<line>    if (<a link="impl-shared.HaveStatisticalProfilingv1p2.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p2()">HaveStatisticalProfilingv1p2</a>() &amp;&amp; PMSFCR_EL1.&lt;FnE,FE&gt; == '11' &amp;&amp;</line>
<line>            !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(PMSEVFR_EL1 AND PMSNEVFR_EL1 AND mask)) then</line>
<line>        // UNPREDICTABLE case due to combination of filter and inverse filter</line>
<line>        is_rejected_nevent = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_BADPMSFCR" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BADPMSFCR</a>);</line>
<line>        is_rejected_event = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_BADPMSFCR" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BADPMSFCR</a>);</line>
<line></line>
<line>    if is_evt &amp;&amp; is_nevt then</line>
<line>        <a link="impl-shared.PMUEvent.1" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event)">PMUEvent</a>(PMU_EVENT_SAMPLE_FEED_EVENT);</line>
<line></line>
<line>    boolean is_op_br = FALSE;</line>
<line>    boolean is_op_ld = FALSE;</line>
<line>    boolean is_op_st = FALSE;</line>
<line></line>
<line>    is_op_br = (optype == <a link="OpType_Branch" file="shared_pseudocode.xml" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_Branch</a>);</line>
<line>    is_op_ld = (optype IN {<a link="OpType_Load" file="shared_pseudocode.xml" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_Load</a>, <a link="OpType_LoadAtomic" file="shared_pseudocode.xml" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_LoadAtomic</a>});</line>
<line>    is_op_st = (optype IN {<a link="OpType_Store" file="shared_pseudocode.xml" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_Store</a>, <a link="OpType_LoadAtomic" file="shared_pseudocode.xml" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_LoadAtomic</a>});</line>
<line></line>
<line>    if is_op_br then <a link="impl-shared.PMUEvent.1" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event)">PMUEvent</a>(PMU_EVENT_SAMPLE_FEED_BR);</line>
<line>    if is_op_ld then <a link="impl-shared.PMUEvent.1" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event)">PMUEvent</a>(PMU_EVENT_SAMPLE_FEED_LD);</line>
<line>    if is_op_st then <a link="impl-shared.PMUEvent.1" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event)">PMUEvent</a>(PMU_EVENT_SAMPLE_FEED_ST);</line>
<line></line>
<line>    boolean is_op = ((is_op_br &amp;&amp; PMSFCR_EL1.B == '1') ||</line>
<line>                    (is_op_ld &amp;&amp; PMSFCR_EL1.LD == '1') ||</line>
<line>                    (is_op_st &amp;&amp; PMSFCR_EL1.ST == '1'));</line>
<line></line>
<line>    if is_op then <a link="impl-shared.PMUEvent.1" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event)">PMUEvent</a>(PMU_EVENT_SAMPLE_FEED_OP);</line>
<line></line>
<line>    // Filter by type</line>
<line>    boolean is_rejected_type = FALSE;</line>
<line>    if PMSFCR_EL1.FT == '1' then</line>
<line>        // Filtering by type is enabled</line>
<line>        if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(PMSFCR_EL1.&lt;B, LD, ST&gt;) then</line>
<line>            // Not an UNPREDICTABLE case</line>
<line>            is_rejected_type = !is_op;</line>
<line>        else</line>
<line>            is_rejected_type = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_BADPMSFCR" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BADPMSFCR</a>);</line>
<line></line>
<line>    // Filter by latency</line>
<line>    boolean is_rejected_latency = FALSE;</line>
<line>    boolean is_lat = (total_latency &lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PMSLATFR_EL1.MINLAT));</line>
<line>    if is_lat then <a link="impl-shared.PMUEvent.1" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event)">PMUEvent</a>(PMU_EVENT_SAMPLE_FEED_LAT);</line>
<line></line>
<line>    if PMSFCR_EL1.FL == '1' then</line>
<line>        // Filtering by latency is enabled</line>
<line>        if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(PMSLATFR_EL1.MINLAT) then</line>
<line>            // Not an UNPREDICTABLE case</line>
<line>            is_rejected_latency = !is_lat;</line>
<line>        else</line>
<line>            is_rejected_latency = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_BADPMSFCR" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BADPMSFCR</a>);</line>
<line></line>
<line>    boolean is_rejected_data_source;</line>
<line>    // Filtering by Data Source</line>
<line>    if (<a link="impl-shared.HaveStatisticalProfilingFDS.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingFDS()">HaveStatisticalProfilingFDS</a>() &amp;&amp; PMSFCR_EL1.FDS == '1' &amp;&amp;</line>
<line>            is_op_ld &amp;&amp; SPESampleDataSourceValid) then</line>
<line>        bits(16) data_source = SPESampleDataSource;</line>
<line>        integer index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(data_source&lt;5:0&gt;);</line>
<line>        is_rejected_data_source = PMSDSFR_EL1&lt;index&gt; == '0';</line>
<line>    else</line>
<line>        is_rejected_data_source = FALSE;</line>
<line></line>
<line>    boolean return_value;</line>
<line>    return_value = !(is_rejected_nevent || is_rejected_event ||</line>
<line>                     is_rejected_type || is_rejected_latency);</line>
<line></line>
<line>    if return_value then</line>
<line>        <a link="impl-shared.PMUEvent.1" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event)">PMUEvent</a>(PMU_EVENT_SAMPLE_FILTRATE);</line>
<line>    return return_value;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEConstructRecord" mylink="aarch64.debug.statisticalprofiling.SPEConstructRecord" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPEConstructRecord()</line>
<line>// ====================</line>
<line>// Create new record and populate it with packets using sample storage data.</line>
<line>// This is an example implementation, packets may appear in</line>
<line>// any order as long as the record ends with an End or Timestamp packet.</line>
<line></line>
<line link="impl-aarch64.SPEConstructRecord.0" hover="function: SPEConstructRecord()" conts="SPEConstructRecord"><anchor link="impl-aarch64.SPEConstructRecord.0" hover="function: SPEConstructRecord()">SPEConstructRecord</anchor>()</line>
<line>    integer payload_size;</line>
<line></line>
<line>    // Empty the record.</line>
<line>    <a link="impl-aarch64.SPEEmptyRecord.0" file="shared_pseudocode.xml" hover="function: SPEEmptyRecord()">SPEEmptyRecord</a>();</line>
<line></line>
<line>    // Add contextEL1 if available</line>
<line>    if SPESampleContextEL1Valid then</line>
<line>        <a link="impl-aarch64.SPEAddPacketToRecord.3" file="shared_pseudocode.xml" hover="function: SPEAddPacketToRecord(bits(2) header_hi, bits(4) header_lo, bits(N) payload)">SPEAddPacketToRecord</a>('01', '0100', SPESampleContextEL1);</line>
<line></line>
<line>     // Add contextEL2 if available</line>
<line>    if SPESampleContextEL2Valid then</line>
<line>        <a link="impl-aarch64.SPEAddPacketToRecord.3" file="shared_pseudocode.xml" hover="function: SPEAddPacketToRecord(bits(2) header_hi, bits(4) header_lo, bits(N) payload)">SPEAddPacketToRecord</a>('01', '0101', SPESampleContextEL2);</line>
<line></line>
<line>    // Add valid counters</line>
<line>    for counter_index = 0 to (<a link="SPEMaxCounters" file="shared_pseudocode.xml" hover="constant integer SPEMaxCounters = 32">SPEMaxCounters</a> - 1)</line>
<line>        if SPESampleCounterValid[counter_index] then</line>
<line>            if counter_index &gt;= 8 then</line>
<line>                // Need extended format</line>
<line>                <a link="impl-aarch64.SPEAddByteToRecord.1" file="shared_pseudocode.xml" hover="function: SPEAddByteToRecord(bits(8) b)">SPEAddByteToRecord</a>('001000':counter_index&lt;4:3&gt;);</line>
<line>            // Check for overflow</line>
<line>            boolean large_counters = boolean IMPLEMENTATION_DEFINED "SPE 16bit counters";</line>
<line>            if SPESampleCounter[counter_index] &gt; 0xFFFF &amp;&amp; large_counters then</line>
<line>                SPESampleCounter[counter_index] = 0xFFFF;</line>
<line>            elsif SPESampleCounter[counter_index] &gt; 0xFFF then</line>
<line>                SPESampleCounter[counter_index] = 0xFFF;</line>
<line></line>
<line>            // Add byte0 for short format (byte1 for extended format)</line>
<line>            <a link="impl-aarch64.SPEAddPacketToRecord.3" file="shared_pseudocode.xml" hover="function: SPEAddPacketToRecord(bits(2) header_hi, bits(4) header_lo, bits(N) payload)">SPEAddPacketToRecord</a>('10', '1':counter_index&lt;2:0&gt;,</line>
<line>                SPESampleCounter[counter_index]&lt;15:0&gt;);</line>
<line></line>
<line>    // Add valid addresses</line>
<line>    if <a link="impl-shared.HaveStatisticalProfilingv1p2.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p2()">HaveStatisticalProfilingv1p2</a>() then</line>
<line>        // Under the some conditions, it is IMPLEMENTATION_DEFINED whether</line>
<line>        // previous branch packet is present.</line>
<line>        boolean include_prev_br = boolean IMPLEMENTATION_DEFINED "SPE get prev br if not br";</line>
<line>        if SPESampleOpType != <a link="OpType_Branch" file="shared_pseudocode.xml" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_Branch</a> &amp;&amp; !include_prev_br then</line>
<line>            SPESampleAddressValid[<a link="SPEAddrPosPrevBranchTarget" file="shared_pseudocode.xml" hover="constant integer SPEAddrPosPrevBranchTarget = 4">SPEAddrPosPrevBranchTarget</a>] = FALSE;</line>
<line></line>
<line>    // Data Virtual address should not be collected if this was an NV2 access and Statistical</line>
<line>    // Profiling is disabled at EL2.</line>
<line>    if !<a link="impl-aarch64.StatisticalProfilingEnabled.1" file="shared_pseudocode.xml" hover="function: boolean StatisticalProfilingEnabled(bits(2) el)">StatisticalProfilingEnabled</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; SPESampleInstIsNV2 then</line>
<line>        SPESampleAddressValid[<a link="SPEAddrPosDataVirtual" file="shared_pseudocode.xml" hover="constant integer SPEAddrPosDataVirtual = 2">SPEAddrPosDataVirtual</a>] = FALSE;</line>
<line></line>
<line>    for address_index = 0 to (<a link="SPEMaxAddrs" file="shared_pseudocode.xml" hover="constant integer SPEMaxAddrs = 32">SPEMaxAddrs</a> - 1)</line>
<line>        if SPESampleAddressValid[address_index] then</line>
<line>            if address_index &gt;= 8 then</line>
<line>                // Need extended format</line>
<line>                <a link="impl-aarch64.SPEAddByteToRecord.1" file="shared_pseudocode.xml" hover="function: SPEAddByteToRecord(bits(8) b)">SPEAddByteToRecord</a>('001000':address_index&lt;4:3&gt;);</line>
<line>            // Add byte0 for short format (byte1 for extended format)</line>
<line>            <a link="impl-aarch64.SPEAddPacketToRecord.3" file="shared_pseudocode.xml" hover="function: SPEAddPacketToRecord(bits(2) header_hi, bits(4) header_lo, bits(N) payload)">SPEAddPacketToRecord</a>('10', '0':address_index&lt;2:0&gt;,</line>
<line>                SPESampleAddress[address_index]);</line>
<line></line>
<line>    // Add Data Source</line>
<line>    if SPESampleDataSourceValid then</line>
<line>        payload_size = <a link="impl-aarch64.SPEGetDataSourcePayloadSize.0" file="shared_pseudocode.xml" hover="function: integer SPEGetDataSourcePayloadSize()">SPEGetDataSourcePayloadSize</a>();</line>
<line>        <a link="impl-aarch64.SPEAddPacketToRecord.3" file="shared_pseudocode.xml" hover="function: SPEAddPacketToRecord(bits(2) header_hi, bits(4) header_lo, bits(N) payload)">SPEAddPacketToRecord</a>('01', '0011', SPESampleDataSource&lt;8*payload_size-1:0&gt;);</line>
<line></line>
<line>    // Add operation details</line>
<line>    <a link="impl-aarch64.SPEAddPacketToRecord.3" file="shared_pseudocode.xml" hover="function: SPEAddPacketToRecord(bits(2) header_hi, bits(4) header_lo, bits(N) payload)">SPEAddPacketToRecord</a>('01', '10':SPESampleClass, SPESampleSubclass);</line>
<line></line>
<line>    // Add events</line>
<line>    // Get size of payload in bytes.</line>
<line>    payload_size = <a link="impl-aarch64.SPEGetEventsPayloadSize.0" file="shared_pseudocode.xml" hover="function: integer SPEGetEventsPayloadSize()">SPEGetEventsPayloadSize</a>();</line>
<line>    <a link="impl-aarch64.SPEAddPacketToRecord.3" file="shared_pseudocode.xml" hover="function: SPEAddPacketToRecord(bits(2) header_hi, bits(4) header_lo, bits(N) payload)">SPEAddPacketToRecord</a>('01', '0010', SPESampleEvents&lt;8*payload_size-1:0&gt;);</line>
<line></line>
<line>    // Add Timestamp to end the record if one is available.</line>
<line>    // Otherwise end with an End packet.</line>
<line>    if SPESampleTimestampValid then</line>
<line>        <a link="impl-aarch64.SPEAddPacketToRecord.3" file="shared_pseudocode.xml" hover="function: SPEAddPacketToRecord(bits(2) header_hi, bits(4) header_lo, bits(N) payload)">SPEAddPacketToRecord</a>('01', '0001', SPESampleTimestamp);</line>
<line>    else</line>
<line>        <a link="impl-aarch64.SPEAddByteToRecord.1" file="shared_pseudocode.xml" hover="function: SPEAddByteToRecord(bits(8) b)">SPEAddByteToRecord</a>('00000001');</line>
<line></line>
<line>    // Add padding</line>
<line>    while SPERecordSize MOD (1&lt;&lt;<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PMBIDR_EL1.Align)) != 0 do</line>
<line>        <a link="impl-aarch64.SPEAddByteToRecord.1" file="shared_pseudocode.xml" hover="function: SPEAddByteToRecord(bits(8) b)">SPEAddByteToRecord</a>(<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8));</line>
<line>    <a link="impl-aarch64.SPEWriteToBuffer.0" file="shared_pseudocode.xml" hover="function: SPEWriteToBuffer()">SPEWriteToBuffer</a>();</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPECycle" mylink="aarch64.debug.statisticalprofiling.SPECycle" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPECycle()</line>
<line>// ==========</line>
<line>// Function called at the end of every cycle. Responsible for asserting interrupts</line>
<line>// and advancing counters.</line>
<line></line>
<line link="impl-aarch64.SPECycle.0" hover="function: SPECycle()" conts="SPECycle"><anchor link="impl-aarch64.SPECycle.0" hover="function: SPECycle()">SPECycle</anchor>()</line>
<line>    if !<a link="impl-shared.HaveStatisticalProfiling.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfiling()">HaveStatisticalProfiling</a>() then</line>
<line>        return;</line>
<line></line>
<line>    // Increment pending counters</line>
<line>    if SPESampleInFlight then</line>
<line>        for i = 0 to (<a link="SPEMaxCounters" file="shared_pseudocode.xml" hover="constant integer SPEMaxCounters = 32">SPEMaxCounters</a> - 1)</line>
<line>            if SPESampleCounterPending[i] then</line>
<line>                SPESampleCounter[i] = SPESampleCounter[i] + 1;</line>
<line></line>
<line>    // Assert PMBIRQ if appropriate.</line>
<line>    SetInterruptRequestLevel(<a link="InterruptID_PMBIRQ" file="shared_pseudocode.xml" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_PMBIRQ</a>, if PMBSR_EL1.S == '1' then HIGH else LOW);</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEEmptyRecord" mylink="aarch64.debug.statisticalprofiling.SPEEmptyRecord" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPEEmptyRecord()</line>
<line>// ================</line>
<line>// Reset record data.</line>
<line></line>
<line link="impl-aarch64.SPEEmptyRecord.0" hover="function: SPEEmptyRecord()" conts="SPEEmptyRecord"><anchor link="impl-aarch64.SPEEmptyRecord.0" hover="function: SPEEmptyRecord()">SPEEmptyRecord</anchor>()</line>
<line>    SPERecordSize = 0;</line>
<line>    for i = 0 to (<a link="SPEMaxRecordSize" file="shared_pseudocode.xml" hover="constant integer SPEMaxRecordSize = 64">SPEMaxRecordSize</a> - 1)</line>
<line>        SPERecordData[i] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8);</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEEvent" mylink="aarch64.debug.statisticalprofiling.SPEEvent" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPEEvent()</line>
<line>// ==========</line>
<line>// Called by PMUEvent if a sample is in flight.</line>
<line>// Sets appropriate bit in SPESampleStorage.events.</line>
<line></line>
<line link="impl-aarch64.SPEEvent.1" hover="function: SPEEvent(bits(16) event)" conts="SPEEvent"><anchor link="impl-aarch64.SPEEvent.1" hover="function: SPEEvent(bits(16) event)">SPEEvent</anchor>(bits(16) event)</line>
<line>    case event of</line>
<line>        when PMU_EVENT_DSNP_HIT_RD</line>
<line>            if <a link="impl-shared.HaveStatisticalProfilingv1p4.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p4()">HaveStatisticalProfilingv1p4</a>() then</line>
<line>                SPESampleEvents&lt;23&gt; = '1';</line>
<line>        when PMU_EVENT_L1D_LFB_HIT_RD</line>
<line>            if <a link="impl-shared.HaveStatisticalProfilingv1p4.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p4()">HaveStatisticalProfilingv1p4</a>() then</line>
<line>                SPESampleEvents&lt;22&gt; = '1';</line>
<line>        when PMU_EVENT_L2D_LFB_HIT_RD</line>
<line>            if <a link="impl-shared.HaveStatisticalProfilingv1p4.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p4()">HaveStatisticalProfilingv1p4</a>() then</line>
<line>                SPESampleEvents&lt;22&gt; = '1';</line>
<line>        when PMU_EVENT_L3D_LFB_HIT_RD</line>
<line>            if <a link="impl-shared.HaveStatisticalProfilingv1p4.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p4()">HaveStatisticalProfilingv1p4</a>() then</line>
<line>                SPESampleEvents&lt;22&gt; = '1';</line>
<line>        when PMU_EVENT_LL_LFB_HIT_RD</line>
<line>            if <a link="impl-shared.HaveStatisticalProfilingv1p4.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p4()">HaveStatisticalProfilingv1p4</a>() then</line>
<line>                SPESampleEvents&lt;22&gt; = '1';</line>
<line>        when PMU_EVENT_L1D_CACHE_HITM_RD</line>
<line>            if <a link="impl-shared.HaveStatisticalProfilingv1p4.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p4()">HaveStatisticalProfilingv1p4</a>() then</line>
<line>                SPESampleEvents&lt;21&gt; = '1';</line>
<line>        when PMU_EVENT_L2D_CACHE_HITM_RD</line>
<line>            if <a link="impl-shared.HaveStatisticalProfilingv1p4.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p4()">HaveStatisticalProfilingv1p4</a>() then</line>
<line>                SPESampleEvents&lt;21&gt; = '1';</line>
<line>        when PMU_EVENT_L3D_CACHE_HITM_RD</line>
<line>            if <a link="impl-shared.HaveStatisticalProfilingv1p4.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p4()">HaveStatisticalProfilingv1p4</a>() then</line>
<line>                SPESampleEvents&lt;21&gt; = '1';</line>
<line>        when PMU_EVENT_LL_CACHE_HITM_RD</line>
<line>            if <a link="impl-shared.HaveStatisticalProfilingv1p4.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p4()">HaveStatisticalProfilingv1p4</a>() then</line>
<line>                SPESampleEvents&lt;21&gt; = '1';</line>
<line>        when PMU_EVENT_L2D_CACHE_LMISS_RD</line>
<line>            if <a link="impl-shared.HaveStatisticalProfilingv1p4.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p4()">HaveStatisticalProfilingv1p4</a>() then</line>
<line>                SPESampleEvents&lt;20&gt; = '1';</line>
<line>        when PMU_EVENT_L2D_CACHE_RD</line>
<line>            if <a link="impl-shared.HaveStatisticalProfilingv1p4.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p4()">HaveStatisticalProfilingv1p4</a>() then</line>
<line>                SPESampleEvents&lt;19&gt; = '1';</line>
<line>        when PMU_EVENT_SVE_PRED_EMPTY_SPEC</line>
<line>            if <a link="impl-shared.HaveStatisticalProfilingv1p1.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p1()">HaveStatisticalProfilingv1p1</a>() then</line>
<line>                SPESampleEvents&lt;18&gt; = '1';</line>
<line>        when PMU_EVENT_SVE_PRED_PARTIAL_SPEC</line>
<line>            if <a link="impl-shared.HaveStatisticalProfilingv1p1.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p1()">HaveStatisticalProfilingv1p1</a>() then</line>
<line>                SPESampleEvents&lt;17&gt; = '1';</line>
<line>        when PMU_EVENT_LDST_ALIGN_LAT</line>
<line>            if <a link="impl-shared.HaveStatisticalProfilingv1p1.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p1()">HaveStatisticalProfilingv1p1</a>() then</line>
<line>                SPESampleEvents&lt;11&gt; = '1';</line>
<line>        when PMU_EVENT_REMOTE_ACCESS         SPESampleEvents&lt;10&gt;  = '1';</line>
<line>        when PMU_EVENT_LL_CACHE_MISS         SPESampleEvents&lt;9&gt;   = '1';</line>
<line>        when PMU_EVENT_LL_CACHE              SPESampleEvents&lt;8&gt;   = '1';</line>
<line>        when PMU_EVENT_BR_MIS_PRED           SPESampleEvents&lt;7&gt;   = '1';</line>
<line>        when PMU_EVENT_BR_MIS_PRED_RETIRED   SPESampleEvents&lt;7&gt;   = '1';</line>
<line>        when PMU_EVENT_DTLB_WALK             SPESampleEvents&lt;5&gt;   = '1';</line>
<line>        when PMU_EVENT_L1D_TLB               SPESampleEvents&lt;4&gt;   = '1';</line>
<line>        when PMU_EVENT_L1D_CACHE_REFILL</line>
<line>            if !<a link="impl-shared.HaveStatisticalProfilingv1p4.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p4()">HaveStatisticalProfilingv1p4</a>() then</line>
<line>                SPESampleEvents&lt;3&gt; = '1';</line>
<line>        when PMU_EVENT_L1D_CACHE_LMISS_RD</line>
<line>            if <a link="impl-shared.HaveStatisticalProfilingv1p4.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p4()">HaveStatisticalProfilingv1p4</a>() then</line>
<line>                SPESampleEvents&lt;3&gt; = '1';</line>
<line>        when PMU_EVENT_L1D_CACHE             SPESampleEvents&lt;2&gt;   = '1';</line>
<line>        when PMU_EVENT_INST_RETIRED          SPESampleEvents&lt;1&gt;   = '1';</line>
<line>        when PMU_EVENT_EXC_TAKEN             SPESampleEvents&lt;0&gt;   = '1';</line>
<line>        otherwise return;</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEGetDataSourcePayloadSize" mylink="aarch64.debug.statisticalprofiling.SPEGetDataSourcePayloadSize" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPEGetDataSourcePayloadSize()</line>
<line>// =============================</line>
<line>// Returns the size of the Data Source payload in bytes.</line>
<line></line>
<line link="impl-aarch64.SPEGetDataSourcePayloadSize.0" hover="function: integer SPEGetDataSourcePayloadSize()" conts="SPEGetDataSourcePayloadSize">integer <anchor link="impl-aarch64.SPEGetDataSourcePayloadSize.0" hover="function: integer SPEGetDataSourcePayloadSize()">SPEGetDataSourcePayloadSize</anchor>()</line>
<line>    return integer IMPLEMENTATION_DEFINED "SPE Data Source packet payload size";</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEGetEventsPayloadSize" mylink="aarch64.debug.statisticalprofiling.SPEGetEventsPayloadSize" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPEGetEventsPayloadSize()</line>
<line>// =========================</line>
<line>// Returns the size in bytes of the Events packet payload as an integer.</line>
<line></line>
<line link="impl-aarch64.SPEGetEventsPayloadSize.0" hover="function: integer SPEGetEventsPayloadSize()" conts="SPEGetEventsPayloadSize">integer <anchor link="impl-aarch64.SPEGetEventsPayloadSize.0" hover="function: integer SPEGetEventsPayloadSize()">SPEGetEventsPayloadSize</anchor>()</line>
<line>    integer size = integer IMPLEMENTATION_DEFINED "SPE Events packet payload size";</line>
<line>    return size;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEGetRandomBoolean" mylink="aarch64.debug.statisticalprofiling.SPEGetRandomBoolean" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPEGetRandomBoolean()</line>
<line>// =====================</line>
<line>// Returns a random or pseudo-random boolean value.</line>
<line></line>
<line link="impl-aarch64.SPEGetRandomBoolean.0" hover="function: boolean SPEGetRandomBoolean()" conts="SPEGetRandomBoolean">boolean <anchor link="impl-aarch64.SPEGetRandomBoolean.0" hover="function: boolean SPEGetRandomBoolean()">SPEGetRandomBoolean</anchor>();</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEGetRandomInterval" mylink="aarch64.debug.statisticalprofiling.SPEGetRandomInterval" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPEGetRandomInterval()</line>
<line>// ======================</line>
<line>// Returns a random or pseudo-random byte for resetting COUNT or ECOUNT.</line>
<line></line>
<line link="impl-aarch64.SPEGetRandomInterval.0" hover="function: bits(8) SPEGetRandomInterval()" conts="SPEGetRandomInterval">bits(8) <anchor link="impl-aarch64.SPEGetRandomInterval.0" hover="function: bits(8) SPEGetRandomInterval()">SPEGetRandomInterval</anchor>();</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEISB" mylink="aarch64.debug.statisticalprofiling.SPEISB" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPEISB()</line>
<line>// ========</line>
<line>// Called by ISB instruction, correctly calls SPEBranch to save previous branches.</line>
<line></line>
<line link="impl-aarch64.SPEISB.0" hover="function: SPEISB()" conts="SPEISB"><anchor link="impl-aarch64.SPEISB.0" hover="function: SPEISB()">SPEISB</anchor>()</line>
<line>    bits(64) address = <a link="impl-aarch64.PC.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) PC[]">PC</a>[] + 4;</line>
<line>    <a link="BranchType" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType</a> branch_type = <a link="BranchType_DIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</a>;</line>
<line>    boolean branch_conditional = FALSE;</line>
<line>    boolean taken = FALSE;</line>
<line>    boolean is_isb = TRUE;</line>
<line></line>
<line>    <a link="impl-aarch64.SPEBranch.5" file="shared_pseudocode.xml" hover="function: SPEBranch(bits(N) target, BranchType branch_type, boolean conditional, boolean taken_flag, boolean is_isb)">SPEBranch</a>(address, branch_type, branch_conditional, taken, is_isb);</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEMaxAddrs" mylink="aarch64.debug.statisticalprofiling.SPEMaxAddrs" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="SPEMaxAddrs" hover="constant integer SPEMaxAddrs = 32" conts="SPEMaxAddrs">constant integer <anchor link="SPEMaxAddrs" hover="constant integer SPEMaxAddrs = 32">SPEMaxAddrs</anchor> = 32;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEMaxCounters" mylink="aarch64.debug.statisticalprofiling.SPEMaxCounters" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="SPEMaxCounters" hover="constant integer SPEMaxCounters = 32" conts="SPEMaxCounters">constant integer <anchor link="SPEMaxCounters" hover="constant integer SPEMaxCounters = 32">SPEMaxCounters</anchor> = 32;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEMaxRecordSize" mylink="aarch64.debug.statisticalprofiling.SPEMaxRecordSize" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="SPEMaxRecordSize" hover="constant integer SPEMaxRecordSize = 64" conts="SPEMaxRecordSize">constant integer <anchor link="SPEMaxRecordSize" hover="constant integer SPEMaxRecordSize = 64">SPEMaxRecordSize</anchor> = 64;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEPostExecution" mylink="aarch64.debug.statisticalprofiling.SPEPostExecution" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="SPEAddrPosPCVirtual" hover="constant integer SPEAddrPosPCVirtual = 0" conts="SPEAddrPosPCVirtual">constant integer <anchor link="SPEAddrPosPCVirtual" hover="constant integer SPEAddrPosPCVirtual = 0">SPEAddrPosPCVirtual</anchor> = 0;</line>
<line link="SPEAddrPosBranchTarget" hover="constant integer SPEAddrPosBranchTarget = 1" conts="SPEAddrPosBranchTarget">constant integer <anchor link="SPEAddrPosBranchTarget" hover="constant integer SPEAddrPosBranchTarget = 1">SPEAddrPosBranchTarget</anchor> = 1;</line>
<line link="SPEAddrPosDataVirtual" hover="constant integer SPEAddrPosDataVirtual = 2" conts="SPEAddrPosDataVirtual">constant integer <anchor link="SPEAddrPosDataVirtual" hover="constant integer SPEAddrPosDataVirtual = 2">SPEAddrPosDataVirtual</anchor> = 2;</line>
<line link="SPEAddrPosDataPhysical" hover="constant integer SPEAddrPosDataPhysical = 3" conts="SPEAddrPosDataPhysical">constant integer <anchor link="SPEAddrPosDataPhysical" hover="constant integer SPEAddrPosDataPhysical = 3">SPEAddrPosDataPhysical</anchor> = 3;</line>
<line link="SPEAddrPosPrevBranchTarget" hover="constant integer SPEAddrPosPrevBranchTarget = 4" conts="SPEAddrPosPrevBranchTarget">constant integer <anchor link="SPEAddrPosPrevBranchTarget" hover="constant integer SPEAddrPosPrevBranchTarget = 4">SPEAddrPosPrevBranchTarget</anchor> = 4;</line>
<line link="SPECounterPosTotalLatency" hover="constant integer SPECounterPosTotalLatency = 0" conts="SPECounterPosTotalLatency">constant integer <anchor link="SPECounterPosTotalLatency" hover="constant integer SPECounterPosTotalLatency = 0">SPECounterPosTotalLatency</anchor> = 0;</line>
<line link="SPECounterPosIssueLatency" hover="constant integer SPECounterPosIssueLatency = 1" conts="SPECounterPosIssueLatency">constant integer <anchor link="SPECounterPosIssueLatency" hover="constant integer SPECounterPosIssueLatency = 1">SPECounterPosIssueLatency</anchor> = 1;</line>
<line link="SPECounterPosTranslationLatency" hover="constant integer SPECounterPosTranslationLatency = 2" conts="SPECounterPosTranslationLatency">constant integer <anchor link="SPECounterPosTranslationLatency" hover="constant integer SPECounterPosTranslationLatency = 2">SPECounterPosTranslationLatency</anchor> = 2;</line>
<line>boolean SPESampleInFlight = FALSE;</line>
<line>bits(32) SPESampleContextEL1;</line>
<line>boolean SPESampleContextEL1Valid;</line>
<line>bits(32) SPESampleContextEL2;</line>
<line>boolean SPESampleContextEL2Valid;</line>
<line>boolean SPESampleInstIsNV2 = FALSE;</line>
<line>bits(64) SPESamplePreviousBranchAddress;</line>
<line>boolean SPESamplePreviousBranchAddressValid;</line>
<line>bits(16) SPESampleDataSource;</line>
<line>boolean SPESampleDataSourceValid;</line>
<line><a link="OpType" file="shared_pseudocode.xml" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType</a> SPESampleOpType;</line>
<line>bits(2) SPESampleClass;</line>
<line>bits(8) SPESampleSubclass;</line>
<line>boolean SPESampleSubclassValid;</line>
<line>bits(64) SPESampleTimestamp;</line>
<line>boolean SPESampleTimestampValid;</line>
<line>bits(64) SPESampleEvents;</line>
<line></line>
<line>// SPEPostExecution()</line>
<line>// ==================</line>
<line>// Called after every executed instruction.</line>
<line></line>
<line link="impl-aarch64.SPEPostExecution.0" hover="function: SPEPostExecution()" conts="SPEPostExecution"><anchor link="impl-aarch64.SPEPostExecution.0" hover="function: SPEPostExecution()">SPEPostExecution</anchor>()</line>
<line>    if SPESampleInFlight then</line>
<line>        SPESampleInFlight = FALSE;</line>
<line>        <a link="impl-shared.PMUEvent.1" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event)">PMUEvent</a>(PMU_EVENT_SAMPLE_FEED);</line>
<line></line>
<line>        // Stop any pending counters</line>
<line>        for counter_index = 0 to (<a link="SPEMaxCounters" file="shared_pseudocode.xml" hover="constant integer SPEMaxCounters = 32">SPEMaxCounters</a> - 1)</line>
<line>            if SPESampleCounterPending[counter_index] then</line>
<line>                <a link="impl-aarch64.SPEStopCounter.1" file="shared_pseudocode.xml" hover="function: SPEStopCounter(integer counter_index)">SPEStopCounter</a>(counter_index);</line>
<line></line>
<line>        boolean discard = FALSE;</line>
<line>        if <a link="impl-shared.HaveStatisticalProfilingv1p2.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfilingv1p2()">HaveStatisticalProfilingv1p2</a>() then</line>
<line>            discard = PMBLIMITR_EL1.FM == '10';</line>
<line>        if <a link="impl-aarch64.SPECollectRecord.3" file="shared_pseudocode.xml" hover="function: boolean SPECollectRecord(bits(64) events, integer total_latency, OpType optype)">SPECollectRecord</a>(SPESampleEvents,</line>
<line>                            SPESampleCounter[<a link="SPECounterPosTotalLatency" file="shared_pseudocode.xml" hover="constant integer SPECounterPosTotalLatency = 0">SPECounterPosTotalLatency</a>],</line>
<line>                            SPESampleOpType) &amp;&amp; !discard then</line>
<line>            <a link="impl-aarch64.SPEConstructRecord.0" file="shared_pseudocode.xml" hover="function: SPEConstructRecord()">SPEConstructRecord</a>();</line>
<line>            if <a link="impl-aarch64.SPEBufferIsFull.0" file="shared_pseudocode.xml" hover="function: boolean SPEBufferIsFull()">SPEBufferIsFull</a>() then</line>
<line>                <a link="impl-aarch64.SPEBufferFilled.0" file="shared_pseudocode.xml" hover="function: SPEBufferFilled()">SPEBufferFilled</a>();</line>
<line></line>
<line>        <a link="impl-aarch64.SPEResetSampleStorage.0" file="shared_pseudocode.xml" hover="function: SPEResetSampleStorage()">SPEResetSampleStorage</a>();</line>
<line></line>
<line>// Counter storage</line>
<line>array [0..<a link="SPEMaxCounters" file="shared_pseudocode.xml" hover="constant integer SPEMaxCounters = 32">SPEMaxCounters</a>-1] of integer SPESampleCounter;</line>
<line></line>
<line>array [0..<a link="SPEMaxCounters" file="shared_pseudocode.xml" hover="constant integer SPEMaxCounters = 32">SPEMaxCounters</a>-1] of boolean SPESampleCounterValid;</line>
<line></line>
<line>array [0..<a link="SPEMaxCounters" file="shared_pseudocode.xml" hover="constant integer SPEMaxCounters = 32">SPEMaxCounters</a>-1] of boolean SPESampleCounterPending;</line>
<line></line>
<line>// Address storage</line>
<line>array [0..<a link="SPEMaxAddrs" file="shared_pseudocode.xml" hover="constant integer SPEMaxAddrs = 32">SPEMaxAddrs</a>-1] of bits(64) SPESampleAddress;</line>
<line></line>
<line>array [0..<a link="SPEMaxAddrs" file="shared_pseudocode.xml" hover="constant integer SPEMaxAddrs = 32">SPEMaxAddrs</a>-1] of boolean SPESampleAddressValid;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEPreExecution" mylink="aarch64.debug.statisticalprofiling.SPEPreExecution" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPEPreExecution()</line>
<line>// =================</line>
<line>// Called prior to execution, for all instructions.</line>
<line></line>
<line link="impl-aarch64.SPEPreExecution.0" hover="function: SPEPreExecution()" conts="SPEPreExecution"><anchor link="impl-aarch64.SPEPreExecution.0" hover="function: SPEPreExecution()">SPEPreExecution</anchor>()</line>
<line>    if <a link="impl-aarch64.StatisticalProfilingEnabled.0" file="shared_pseudocode.xml" hover="function: boolean StatisticalProfilingEnabled()">StatisticalProfilingEnabled</a>() then</line>
<line>        <a link="impl-shared.PMUEvent.1" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event)">PMUEvent</a>(PMU_EVENT_SAMPLE_POP);</line>
<line>        if <a link="impl-aarch64.SPEToCollectSample.0" file="shared_pseudocode.xml" hover="function: boolean SPEToCollectSample()">SPEToCollectSample</a>() then</line>
<line>            if !SPESampleInFlight then</line>
<line>                SPESampleInFlight = TRUE;</line>
<line></line>
<line>                // Start total latency and issue latency counters for SPE</line>
<line>                <a link="impl-aarch64.SPEStartCounter.1" file="shared_pseudocode.xml" hover="function: SPEStartCounter(integer counter_index)">SPEStartCounter</a>(<a link="SPECounterPosTotalLatency" file="shared_pseudocode.xml" hover="constant integer SPECounterPosTotalLatency = 0">SPECounterPosTotalLatency</a>);</line>
<line>                <a link="impl-aarch64.SPEStartCounter.1" file="shared_pseudocode.xml" hover="function: SPEStartCounter(integer counter_index)">SPEStartCounter</a>(<a link="SPECounterPosIssueLatency" file="shared_pseudocode.xml" hover="constant integer SPECounterPosIssueLatency = 1">SPECounterPosIssueLatency</a>);</line>
<line></line>
<line>                <a link="impl-aarch64.SPESampleAddContext.0" file="shared_pseudocode.xml" hover="function: SPESampleAddContext()">SPESampleAddContext</a>();</line>
<line></line>
<line>                <a link="impl-aarch64.SPESampleAddAddressPCVirtual.0" file="shared_pseudocode.xml" hover="function: SPESampleAddAddressPCVirtual()">SPESampleAddAddressPCVirtual</a>();</line>
<line></line>
<line>                // Timestamp may be collected at any point in the sampling operation.</line>
<line>                // Collecting prior to execution is one possible choice.</line>
<line>                // This choice is IMPLEMENTATION_DEFINED.</line>
<line>                <a link="impl-aarch64.SPESampleAddTimeStamp.0" file="shared_pseudocode.xml" hover="function: SPESampleAddTimeStamp()">SPESampleAddTimeStamp</a>();</line>
<line>            else</line>
<line>                <a link="impl-shared.PMUEvent.1" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event)">PMUEvent</a>(PMU_EVENT_SAMPLE_COLLISION);</line>
<line>                PMBSR_EL1.COLL = '1';</line>
<line></line>
<line>            // Many operations are type other and not conditional, can save footprint</line>
<line>            // and overhead by having this as the default and not calling SPESampleAddOpOther</line>
<line>            // if conditional == FALSE</line>
<line>            <a link="impl-aarch64.SPESampleAddOpOther.1" file="shared_pseudocode.xml" hover="function: SPESampleAddOpOther(boolean conditional)">SPESampleAddOpOther</a>(FALSE);</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEResetSampleCounter" mylink="aarch64.debug.statisticalprofiling.SPEResetSampleCounter" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPEResetSampleCounter()</line>
<line>// =======================</line>
<line>// Reset PMSICR_EL1.Counter</line>
<line></line>
<line link="impl-aarch64.SPEResetSampleCounter.0" hover="function: SPEResetSampleCounter()" conts="SPEResetSampleCounter"><anchor link="impl-aarch64.SPEResetSampleCounter.0" hover="function: SPEResetSampleCounter()">SPEResetSampleCounter</anchor>()</line>
<line>    PMSICR_EL1.COUNT&lt;31:8&gt; = PMSIRR_EL1.INTERVAL;</line>
<line>    if PMSIRR_EL1.RND == '1' &amp;&amp; PMSIDR_EL1.ERnd == '0' then</line>
<line>        PMSICR_EL1.COUNT&lt;7:0&gt; = <a link="impl-aarch64.SPEGetRandomInterval.0" file="shared_pseudocode.xml" hover="function: bits(8) SPEGetRandomInterval()">SPEGetRandomInterval</a>();</line>
<line>    else</line>
<line>        PMSICR_EL1.COUNT&lt;7:0&gt; = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8);</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEResetSampleStorage" mylink="aarch64.debug.statisticalprofiling.SPEResetSampleStorage" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>integer SPERecordSize;</line>
<line></line>
<line>// SPEResetSampleStorage()</line>
<line>// =======================</line>
<line>// Reset all variables inside sample storage.</line>
<line></line>
<line link="impl-aarch64.SPEResetSampleStorage.0" hover="function: SPEResetSampleStorage()" conts="SPEResetSampleStorage"><anchor link="impl-aarch64.SPEResetSampleStorage.0" hover="function: SPEResetSampleStorage()">SPEResetSampleStorage</anchor>()</line>
<line>    // Context values</line>
<line>    SPESampleContextEL1 = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32);</line>
<line>    SPESampleContextEL1Valid = FALSE;</line>
<line>    SPESampleContextEL2 = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32);</line>
<line>    SPESampleContextEL2Valid = FALSE;</line>
<line></line>
<line>    // Counter values</line>
<line>    for i = 0 to (<a link="SPEMaxCounters" file="shared_pseudocode.xml" hover="constant integer SPEMaxCounters = 32">SPEMaxCounters</a> - 1)</line>
<line>        SPESampleCounter[i] = 0;</line>
<line>        SPESampleCounterValid[i] = FALSE;</line>
<line>        SPESampleCounterPending[i] = FALSE;</line>
<line></line>
<line>    // Address values</line>
<line>    for i = 0 to (<a link="SPEMaxAddrs" file="shared_pseudocode.xml" hover="constant integer SPEMaxAddrs = 32">SPEMaxAddrs</a> - 1)</line>
<line>        SPESampleAddressValid[i] = FALSE;</line>
<line>        SPESampleAddress[i] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line></line>
<line>    // Data source values</line>
<line>    SPESampleDataSource = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>    SPESampleDataSourceValid = FALSE;</line>
<line></line>
<line>    // Operation values</line>
<line>    SPESampleClass = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(2);</line>
<line>    SPESampleSubclass = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8);</line>
<line>    SPESampleSubclassValid = FALSE;</line>
<line></line>
<line>    // Timestamp values</line>
<line>    SPESampleTimestamp = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>    SPESampleTimestampValid = FALSE;</line>
<line></line>
<line>    // Event values</line>
<line>    SPESampleEvents&lt;63:48&gt; = bits(16) IMPLEMENTATION_DEFINED "SPE EVENTS 63_48";</line>
<line>    SPESampleEvents&lt;47:32&gt; = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>    SPESampleEvents&lt;31:24&gt; = bits(8) IMPLEMENTATION_DEFINED "SPE EVENTS 31_24";</line>
<line>    SPESampleEvents&lt;23:16&gt; = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8);</line>
<line>    SPESampleEvents&lt;15:12&gt; = bits(4) IMPLEMENTATION_DEFINED "SPE EVENTS 15_12";</line>
<line>    SPESampleEvents&lt;11:0&gt; = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12);</line>
<line></line>
<line>    SPESampleInstIsNV2 = FALSE;</line>
<line></line>
<line>array [0..<a link="SPEMaxRecordSize" file="shared_pseudocode.xml" hover="constant integer SPEMaxRecordSize = 64">SPEMaxRecordSize</a>-1] of bits(8) SPERecordData;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPESampleAddAddressPCVirtual" mylink="aarch64.debug.statisticalprofiling.SPESampleAddAddressPCVirtual" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPESampleAddAddressPCVirtual()</line>
<line>// ==============================</line>
<line>// Save the current PC address to sample storage.</line>
<line></line>
<line link="impl-aarch64.SPESampleAddAddressPCVirtual.0" hover="function: SPESampleAddAddressPCVirtual()" conts="SPESampleAddAddressPCVirtual"><anchor link="impl-aarch64.SPESampleAddAddressPCVirtual.0" hover="function: SPESampleAddAddressPCVirtual()">SPESampleAddAddressPCVirtual</anchor>()</line>
<line>    bits(64) this_address = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    SPESampleAddress[<a link="SPEAddrPosPCVirtual" file="shared_pseudocode.xml" hover="constant integer SPEAddrPosPCVirtual = 0">SPEAddrPosPCVirtual</a>]&lt;55:0&gt; = this_address&lt;55:0&gt;;</line>
<line></line>
<line>    bit ns;</line>
<line>    bit nse;</line>
<line>    case <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() of</line>
<line>        when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a></line>
<line>            ns = '0';</line>
<line>            nse = '0';</line>
<line>        when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a></line>
<line>            ns = '1';</line>
<line>            nse = '0';</line>
<line>        when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a></line>
<line>            ns = '1';</line>
<line>            nse = '1';</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    bits(2) el = PSTATE.EL;</line>
<line>    SPESampleAddress[<a link="SPEAddrPosPCVirtual" file="shared_pseudocode.xml" hover="constant integer SPEAddrPosPCVirtual = 0">SPEAddrPosPCVirtual</a>]&lt;63:56&gt; = ns:el:nse:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(4);</line>
<line>    SPESampleAddressValid[<a link="SPEAddrPosPCVirtual" file="shared_pseudocode.xml" hover="constant integer SPEAddrPosPCVirtual = 0">SPEAddrPosPCVirtual</a>] = TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPESampleAddContext" mylink="aarch64.debug.statisticalprofiling.SPESampleAddContext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPESampleAddContext()</line>
<line>// =====================</line>
<line>// Save contexts to sample storage if appropriate.</line>
<line></line>
<line link="impl-aarch64.SPESampleAddContext.0" hover="function: SPESampleAddContext()" conts="SPESampleAddContext"><anchor link="impl-aarch64.SPESampleAddContext.0" hover="function: SPESampleAddContext()">SPESampleAddContext</anchor>()</line>
<line>    if <a link="impl-aarch64.CollectContextIDR1.0" file="shared_pseudocode.xml" hover="function: boolean CollectContextIDR1()">CollectContextIDR1</a>() then</line>
<line>        SPESampleContextEL1 = CONTEXTIDR_EL1&lt;31:0&gt;;</line>
<line>        SPESampleContextEL1Valid = TRUE;</line>
<line>    if <a link="impl-aarch64.CollectContextIDR2.0" file="shared_pseudocode.xml" hover="function: boolean CollectContextIDR2()">CollectContextIDR2</a>() then</line>
<line>        SPESampleContextEL2 = CONTEXTIDR_EL2&lt;31:0&gt;;</line>
<line>        SPESampleContextEL2Valid = TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPESampleAddOpOther" mylink="aarch64.debug.statisticalprofiling.SPESampleAddOpOther" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPESampleAddOpOther()</line>
<line>// =====================</line>
<line>// Add other operation to sample storage.</line>
<line></line>
<line link="impl-aarch64.SPESampleAddOpOther.2" hover="function: SPESampleAddOpOther(boolean conditional, boolean taken)" conts="SPESampleAddOpOther"><anchor link="impl-aarch64.SPESampleAddOpOther.2" hover="function: SPESampleAddOpOther(boolean conditional, boolean taken)">SPESampleAddOpOther</anchor>(boolean conditional, boolean taken)</line>
<line>    SPESampleEvents&lt;6&gt; = if conditional &amp;&amp; !taken then '1' else '0';</line>
<line>    <a link="impl-aarch64.SPESampleAddOpOther.1" file="shared_pseudocode.xml" hover="function: SPESampleAddOpOther(boolean conditional)">SPESampleAddOpOther</a>(conditional);</line>
<line></line>
<line link="impl-aarch64.SPESampleAddOpOther.1" hover="function: SPESampleAddOpOther(boolean conditional)" conts="SPESampleAddOpOther"><anchor link="impl-aarch64.SPESampleAddOpOther.1" hover="function: SPESampleAddOpOther(boolean conditional)">SPESampleAddOpOther</anchor>(boolean conditional)</line>
<line>    SPESampleClass = '00';</line>
<line>    SPESampleSubclass&lt;0&gt; = if conditional then '1' else '0';</line>
<line>    SPESampleOpType = <a link="OpType_Other" file="shared_pseudocode.xml" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_Other</a>;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPESampleAddOpSVELoadStore" mylink="aarch64.debug.statisticalprofiling.SPESampleAddOpSVELoadStore" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPESampleAddOpSVELoadStore()</line>
<line>// ============================</line>
<line>// Sets the subclass of the operation type packet to Load/Store for SVE operations.</line>
<line></line>
<line link="impl-aarch64.SPESampleAddOpSVELoadStore.4" hover="function: SPESampleAddOpSVELoadStore(boolean is_gather_scatter, bits(3) evl, boolean predicated, boolean is_load)" conts="SPESampleAddOpSVELoadStore"><anchor link="impl-aarch64.SPESampleAddOpSVELoadStore.4" hover="function: SPESampleAddOpSVELoadStore(boolean is_gather_scatter, bits(3) evl, boolean predicated, boolean is_load)">SPESampleAddOpSVELoadStore</anchor>(boolean is_gather_scatter, bits(3) evl, boolean predicated,</line>
<line>                           boolean is_load)</line>
<line>    bit sg = if is_gather_scatter then '1' else '0';</line>
<line>    bit pred = if predicated then '1' else '0';</line>
<line>    bit ldst = if is_load then '0' else '1';</line>
<line>    SPESampleClass = '01';</line>
<line>    SPESampleSubclass&lt;7:0&gt; = sg:evl:'1':pred:'0':ldst;</line>
<line>    SPESampleSubclassValid = TRUE;</line>
<line>    SPESampleOpType = if is_load then <a link="OpType_Load" file="shared_pseudocode.xml" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_Load</a> else <a link="OpType_Store" file="shared_pseudocode.xml" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_Store</a>;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPESampleAddOpSVEOther" mylink="aarch64.debug.statisticalprofiling.SPESampleAddOpSVEOther" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPESampleAddOpSVEOther()</line>
<line>// ========================</line>
<line>// Sets the subclass of the operation type packet to Other for SVE operations.</line>
<line></line>
<line link="impl-aarch64.SPESampleAddOpSVEOther.3" hover="function: SPESampleAddOpSVEOther(bits(3) evl, boolean predicated, boolean floating_point)" conts="SPESampleAddOpSVEOther"><anchor link="impl-aarch64.SPESampleAddOpSVEOther.3" hover="function: SPESampleAddOpSVEOther(bits(3) evl, boolean predicated, boolean floating_point)">SPESampleAddOpSVEOther</anchor>(bits(3) evl, boolean predicated, boolean floating_point)</line>
<line>    bit pred = if predicated then '1' else '0';</line>
<line>    bit fp = if floating_point then '1' else '0';</line>
<line>    SPESampleClass = '00';</line>
<line>    SPESampleSubclass&lt;7:0&gt; = '0':evl:'1':pred:fp:'0';</line>
<line>    SPESampleSubclassValid = TRUE;</line>
<line>    SPESampleOpType = <a link="OpType_Other" file="shared_pseudocode.xml" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_Other</a>;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPESampleAddTimeStamp" mylink="aarch64.debug.statisticalprofiling.SPESampleAddTimeStamp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPESampleAddTimeStamp()</line>
<line>// =======================</line>
<line>// Save the appropriate type of timestamp to sample storage.</line>
<line></line>
<line link="impl-aarch64.SPESampleAddTimeStamp.0" hover="function: SPESampleAddTimeStamp()" conts="SPESampleAddTimeStamp"><anchor link="impl-aarch64.SPESampleAddTimeStamp.0" hover="function: SPESampleAddTimeStamp()">SPESampleAddTimeStamp</anchor>()</line>
<line>    <a link="TimeStamp" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp</a> timestamp = <a link="impl-aarch64.CollectTimeStamp.0" file="shared_pseudocode.xml" hover="function: TimeStamp CollectTimeStamp()">CollectTimeStamp</a>();</line>
<line>    case timestamp of</line>
<line>        when <a link="TimeStamp_None" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_None</a></line>
<line>            SPESampleTimestampValid = FALSE;</line>
<line>        otherwise</line>
<line>            SPESampleTimestampValid = TRUE;</line>
<line>            SPESampleTimestamp = <a link="impl-shared.GetTimestamp.1" file="shared_pseudocode.xml" hover="function: bits(64) GetTimestamp(TimeStamp timeStampType)">GetTimestamp</a>(timestamp);</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPESampleExtendedLoadStore" mylink="aarch64.debug.statisticalprofiling.SPESampleExtendedLoadStore" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPESampleExtendedLoadStore()</line>
<line>// ============================</line>
<line>// Sets the subclass of the operation type packet for</line>
<line>// extended load/store operations.</line>
<line></line>
<line link="impl-aarch64.SPESampleExtendedLoadStore.4" hover="function: SPESampleExtendedLoadStore(bit ar, bit excl, bit at, boolean is_load)" conts="SPESampleExtendedLoadStore"><anchor link="impl-aarch64.SPESampleExtendedLoadStore.4" hover="function: SPESampleExtendedLoadStore(bit ar, bit excl, bit at, boolean is_load)">SPESampleExtendedLoadStore</anchor>(bit ar, bit excl, bit at, boolean is_load)</line>
<line>    SPESampleClass = '01';</line>
<line>    bit ldst = if is_load then '0' else '1';</line>
<line>    SPESampleSubclass = '000':ar:excl:at:'1':ldst;</line>
<line></line>
<line>    SPESampleSubclassValid = TRUE;</line>
<line></line>
<line>    if is_load then</line>
<line>        if at == '1' then</line>
<line>            SPESampleOpType = <a link="OpType_LoadAtomic" file="shared_pseudocode.xml" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_LoadAtomic</a>;</line>
<line>        else</line>
<line>            SPESampleOpType = <a link="OpType_Load" file="shared_pseudocode.xml" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_Load</a>;</line>
<line>    else</line>
<line>        SPESampleOpType = <a link="OpType_Store" file="shared_pseudocode.xml" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_Store</a>;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPESampleGeneralPurposeLoadStore" mylink="aarch64.debug.statisticalprofiling.SPESampleGeneralPurposeLoadStore" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPESampleGeneralPurposeLoadStore()</line>
<line>// ==================================</line>
<line>// Sets the subclass of the operation type packet for general</line>
<line>// purpose load/store operations.</line>
<line></line>
<line link="impl-aarch64.SPESampleGeneralPurposeLoadStore.0" hover="function: SPESampleGeneralPurposeLoadStore()" conts="SPESampleGeneralPurposeLoadStore"><anchor link="impl-aarch64.SPESampleGeneralPurposeLoadStore.0" hover="function: SPESampleGeneralPurposeLoadStore()">SPESampleGeneralPurposeLoadStore</anchor>()</line>
<line>    SPESampleClass = '01';</line>
<line></line>
<line>    SPESampleSubclass&lt;7:1&gt; = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(7);</line>
<line>    SPESampleSubclassValid = TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPESampleLoadStore" mylink="aarch64.debug.statisticalprofiling.SPESampleLoadStore" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPESampleLoadStore()</line>
<line>// ====================</line>
<line>// Called if a sample is in flight when writing or reading memory,</line>
<line>// indicating that the operation being sampled is in the Load, Store or atomic category.</line>
<line></line>
<line link="impl-aarch64.SPESampleLoadStore.3" hover="function: SPESampleLoadStore(boolean is_load, AccessDescriptor accdesc, AddressDescriptor addrdesc)" conts="SPESampleLoadStore"><anchor link="impl-aarch64.SPESampleLoadStore.3" hover="function: SPESampleLoadStore(boolean is_load, AccessDescriptor accdesc, AddressDescriptor addrdesc)">SPESampleLoadStore</anchor>(boolean is_load, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> addrdesc)</line>
<line>    // Check if this access type should be sampled.</line>
<line>    if accdesc.acctype IN {<a link="AccessType_SPE" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_SPE</a>,</line>
<line>                           <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a>,</line>
<line>                           <a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>,</line>
<line>                           <a link="AccessType_TTW" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_TTW</a>,</line>
<line>                           <a link="AccessType_AT" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_AT</a>} then</line>
<line>        return;</line>
<line></line>
<line>    // MOPS instructions indicate which operation should be sampled before the</line>
<line>    // operation is executed. Has the instruction indicated that the load should be sampled?</line>
<line>    boolean sample_loads;</line>
<line>    sample_loads = SPESampleSubclass&lt;0&gt; == '0' &amp;&amp; SPESampleSubclassValid;</line>
<line></line>
<line>    // Has the instruction indicated that the store should be sampled?</line>
<line>    boolean sample_stores;</line>
<line>    sample_stores = SPESampleSubclass&lt;0&gt; == '1' &amp;&amp; SPESampleSubclassValid;</line>
<line></line>
<line>    // No valid data has been collected, or this is operation has specifically been selected for</line>
<line>    // sampling.</line>
<line>    if (!SPESampleSubclassValid || (sample_loads &amp;&amp; is_load) ||</line>
<line>            (sample_stores &amp;&amp; !is_load)) then</line>
<line>        // Data access virtual address</line>
<line>        <a link="impl-aarch64.SPESetDataVirtualAddress.1" file="shared_pseudocode.xml" hover="function: SPESetDataVirtualAddress(bits(64) vaddress)">SPESetDataVirtualAddress</a>(addrdesc.vaddress);</line>
<line></line>
<line>        // Data access physical address</line>
<line>        if <a link="impl-aarch64.CollectPhysicalAddress.0" file="shared_pseudocode.xml" hover="function: boolean CollectPhysicalAddress()">CollectPhysicalAddress</a>() then</line>
<line>            <a link="impl-aarch64.SPESetDataPhysicalAddress.2" file="shared_pseudocode.xml" hover="function: SPESetDataPhysicalAddress(AddressDescriptor addrdesc, AccessDescriptor accdesc)">SPESetDataPhysicalAddress</a>(addrdesc, accdesc);</line>
<line></line>
<line>    if !SPESampleSubclassValid then</line>
<line>        // Set as unspecified load/store by default, instructions will overwrite this if it does not</line>
<line>        // apply to them.</line>
<line>        SPESampleClass = '01';</line>
<line>        SPESampleSubclassValid = TRUE;</line>
<line>        SPESampleSubclass&lt;7:1&gt; = '0001000';</line>
<line>        SPESampleSubclass&lt;0&gt; = if is_load then '0' else '1';</line>
<line>        SPESampleOpType = if is_load then <a link="OpType_Load" file="shared_pseudocode.xml" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_Load</a> else <a link="OpType_Store" file="shared_pseudocode.xml" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_Store</a>;</line>
<line></line>
<line>        if accdesc.acctype == <a link="AccessType_NV2" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_NV2</a> then</line>
<line>            // NV2 register load/store</line>
<line>            SPESampleSubclass&lt;7:1&gt; = '0011000';</line>
<line>            SPESampleInstIsNV2 = TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPESampleMemCopy" mylink="aarch64.debug.statisticalprofiling.SPESampleMemCopy" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPESampleMemCopy()</line>
<line>// ==================</line>
<line>// Sets the subclass of the operation type packet for Memory Copy load/store</line>
<line>// operations.</line>
<line></line>
<line link="impl-aarch64.SPESampleMemCopy.0" hover="function: SPESampleMemCopy()" conts="SPESampleMemCopy"><anchor link="impl-aarch64.SPESampleMemCopy.0" hover="function: SPESampleMemCopy()">SPESampleMemCopy</anchor>()</line>
<line>    // MemCopy does a read and a write. If one is filtered out, the other should be recorded.</line>
<line>    // If neither or both are filtered out, pick one in a (pseudo)random way.</line>
<line></line>
<line>    // Are loads allowed by filter?</line>
<line>    boolean loads_pass_filter = PMSFCR_EL1.FT == '1' &amp;&amp; PMSFCR_EL1.LD == '1';</line>
<line>    // Are stores allowed by filter?</line>
<line>    boolean stores_pass_filter = PMSFCR_EL1.FT == '1' &amp;&amp; PMSFCR_EL1.ST == '1';</line>
<line></line>
<line>    boolean record_load;</line>
<line>    if loads_pass_filter &amp;&amp; !stores_pass_filter then</line>
<line>        // Only loads pass filter</line>
<line>        record_load = TRUE;</line>
<line>    elsif !loads_pass_filter &amp;&amp; stores_pass_filter then</line>
<line>        // Only stores pass filter</line>
<line>        record_load = FALSE;</line>
<line>    else</line>
<line>        // Pick randomly between</line>
<line>        record_load = <a link="impl-aarch64.SPEGetRandomBoolean.0" file="shared_pseudocode.xml" hover="function: boolean SPEGetRandomBoolean()">SPEGetRandomBoolean</a>();</line>
<line></line>
<line>    SPESampleClass = '01';</line>
<line>    bit ldst = if record_load then '0' else '1';</line>
<line>    SPESampleSubclass&lt;7:0&gt; = '0010000':ldst;</line>
<line>    SPESampleSubclassValid = TRUE;</line>
<line>    SPESampleOpType = if record_load then <a link="OpType_Load" file="shared_pseudocode.xml" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_Load</a> else <a link="OpType_Store" file="shared_pseudocode.xml" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_Store</a>;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPESampleMemSet" mylink="aarch64.debug.statisticalprofiling.SPESampleMemSet" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPESampleMemSet()</line>
<line>// =================</line>
<line>// Sets the subclass of the operation type packet for Memory Set load/store</line>
<line>// operation.</line>
<line></line>
<line link="impl-aarch64.SPESampleMemSet.0" hover="function: SPESampleMemSet()" conts="SPESampleMemSet"><anchor link="impl-aarch64.SPESampleMemSet.0" hover="function: SPESampleMemSet()">SPESampleMemSet</anchor>()</line>
<line>    SPESampleClass = '01';</line>
<line>    SPESampleSubclass&lt;7:0&gt; = '00100101';</line>
<line>    SPESampleSubclassValid = TRUE;</line>
<line>    SPESampleOpType = <a link="OpType_Store" file="shared_pseudocode.xml" hover="enumeration OpType { OpType_Load, OpType_Store, OpType_LoadAtomic, OpType_Branch, OpType_Other }">OpType_Store</a>;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPESampleSIMDFPLoadStore" mylink="aarch64.debug.statisticalprofiling.SPESampleSIMDFPLoadStore" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPESampleSIMDFPLoadStore()</line>
<line>// ==========================</line>
<line>// Sets the subclass of the operation type packet for SIMD &amp; FP</line>
<line>// load store operations.</line>
<line></line>
<line link="impl-aarch64.SPESampleSIMDFPLoadStore.0" hover="function: SPESampleSIMDFPLoadStore()" conts="SPESampleSIMDFPLoadStore"><anchor link="impl-aarch64.SPESampleSIMDFPLoadStore.0" hover="function: SPESampleSIMDFPLoadStore()">SPESampleSIMDFPLoadStore</anchor>()</line>
<line>    SPESampleClass = '01';</line>
<line></line>
<line>    SPESampleSubclass&lt;7:1&gt; = '0000010';</line>
<line>    SPESampleSubclassValid = TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPESetDataPhysicalAddress" mylink="aarch64.debug.statisticalprofiling.SPESetDataPhysicalAddress" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPESetDataPhysicalAddress()</line>
<line>// ===========================</line>
<line>// Called from SampleLoadStore() to save data physical packet.</line>
<line></line>
<line link="impl-aarch64.SPESetDataPhysicalAddress.2" hover="function: SPESetDataPhysicalAddress(AddressDescriptor addrdesc, AccessDescriptor accdesc)" conts="SPESetDataPhysicalAddress"><anchor link="impl-aarch64.SPESetDataPhysicalAddress.2" hover="function: SPESetDataPhysicalAddress(AddressDescriptor addrdesc, AccessDescriptor accdesc)">SPESetDataPhysicalAddress</anchor>(<a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> addrdesc, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    bit ns;</line>
<line>    bit nse;</line>
<line>    case addrdesc.paddress.paspace of</line>
<line>        when <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a></line>
<line>            ns = '0';</line>
<line>            nse = '0';</line>
<line>        when <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a></line>
<line>            ns = '1';</line>
<line>            nse = '0';</line>
<line>        when <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a></line>
<line>            ns  = '1';</line>
<line>            nse = '1';</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() then</line>
<line>        bits(4) pat;</line>
<line>        if accdesc.tagchecked then</line>
<line>            SPESampleAddress[<a link="SPEAddrPosDataPhysical" file="shared_pseudocode.xml" hover="constant integer SPEAddrPosDataPhysical = 3">SPEAddrPosDataPhysical</a>]&lt;62&gt; = '1'; // CH</line>
<line>            pat = <a link="AArch64.PhysicalTag.1" file="shared_pseudocode.xml" hover="function: bits(4) AArch64.PhysicalTag(bits(64) vaddr)">AArch64.PhysicalTag</a>(addrdesc.vaddress);</line>
<line>        else</line>
<line>            // CH is reset to 0 on each new packet</line>
<line>            // If the access is Unchecked, this is an IMPLEMENTATION_DEFINED choice</line>
<line>            // between 0b0000 and the Physical Address Tag</line>
<line>            boolean zero_unchecked;</line>
<line>            zero_unchecked = boolean IMPLEMENTATION_DEFINED "SPE PAT for tag unchecked access zero";</line>
<line>            if !zero_unchecked then</line>
<line>                pat = <a link="AArch64.PhysicalTag.1" file="shared_pseudocode.xml" hover="function: bits(4) AArch64.PhysicalTag(bits(64) vaddr)">AArch64.PhysicalTag</a>(addrdesc.vaddress);</line>
<line>            else</line>
<line>                pat = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(4);</line>
<line>        SPESampleAddress[<a link="SPEAddrPosDataPhysical" file="shared_pseudocode.xml" hover="constant integer SPEAddrPosDataPhysical = 3">SPEAddrPosDataPhysical</a>]&lt;59:56&gt; = pat;</line>
<line></line>
<line>    bits(56) paddr = addrdesc.paddress.address;</line>
<line>    SPESampleAddress[<a link="SPEAddrPosDataPhysical" file="shared_pseudocode.xml" hover="constant integer SPEAddrPosDataPhysical = 3">SPEAddrPosDataPhysical</a>]&lt;56-1:0&gt; = paddr;</line>
<line>    SPESampleAddress[<a link="SPEAddrPosDataPhysical" file="shared_pseudocode.xml" hover="constant integer SPEAddrPosDataPhysical = 3">SPEAddrPosDataPhysical</a>]&lt;63&gt; = ns;</line>
<line>    SPESampleAddress[<a link="SPEAddrPosDataPhysical" file="shared_pseudocode.xml" hover="constant integer SPEAddrPosDataPhysical = 3">SPEAddrPosDataPhysical</a>]&lt;60&gt; = nse;</line>
<line>    SPESampleAddressValid[<a link="SPEAddrPosDataPhysical" file="shared_pseudocode.xml" hover="constant integer SPEAddrPosDataPhysical = 3">SPEAddrPosDataPhysical</a>] = TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPESetDataVirtualAddress" mylink="aarch64.debug.statisticalprofiling.SPESetDataVirtualAddress" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPESetDataVirtualAddress()</line>
<line>// ==========================</line>
<line>// Called from SampleLoadStore() to save data virtual packet.</line>
<line>// Also used by exclusive load/stores to save virtual addresses if exclusive monitor is lost</line>
<line>// before a read/write is completed.</line>
<line></line>
<line link="impl-aarch64.SPESetDataVirtualAddress.1" hover="function: SPESetDataVirtualAddress(bits(64) vaddress)" conts="SPESetDataVirtualAddress"><anchor link="impl-aarch64.SPESetDataVirtualAddress.1" hover="function: SPESetDataVirtualAddress(bits(64) vaddress)">SPESetDataVirtualAddress</anchor>(bits(64) vaddress)</line>
<line>    bit tbi;</line>
<line>    tbi = <a link="impl-shared.EffectiveTBI.3" file="shared_pseudocode.xml" hover="function: bit EffectiveTBI(bits(64) address, boolean IsInstr, bits(2) el)">EffectiveTBI</a>(vaddress, FALSE, PSTATE.EL);</line>
<line>    boolean non_tbi_is_zeros;</line>
<line>    non_tbi_is_zeros = boolean IMPLEMENTATION_DEFINED "SPE non-tbi tag is zero";</line>
<line>    if tbi == '1' || !non_tbi_is_zeros then</line>
<line>        SPESampleAddress[<a link="SPEAddrPosDataVirtual" file="shared_pseudocode.xml" hover="constant integer SPEAddrPosDataVirtual = 2">SPEAddrPosDataVirtual</a>]&lt;63:0&gt; = vaddress&lt;63:0&gt;;</line>
<line>    else</line>
<line>        SPESampleAddress[<a link="SPEAddrPosDataVirtual" file="shared_pseudocode.xml" hover="constant integer SPEAddrPosDataVirtual = 2">SPEAddrPosDataVirtual</a>]&lt;63:56&gt; = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8);</line>
<line>        SPESampleAddress[<a link="SPEAddrPosDataVirtual" file="shared_pseudocode.xml" hover="constant integer SPEAddrPosDataVirtual = 2">SPEAddrPosDataVirtual</a>]&lt;55:0&gt; = vaddress&lt;55:0&gt;;</line>
<line>    SPESampleAddressValid[<a link="SPEAddrPosDataVirtual" file="shared_pseudocode.xml" hover="constant integer SPEAddrPosDataVirtual = 2">SPEAddrPosDataVirtual</a>] = TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEStartCounter" mylink="aarch64.debug.statisticalprofiling.SPEStartCounter" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPEStartCounter()</line>
<line>// =================</line>
<line>// Enables incrementing of the counter at the passed index when SPECycle is called.</line>
<line></line>
<line link="impl-aarch64.SPEStartCounter.1" hover="function: SPEStartCounter(integer counter_index)" conts="SPEStartCounter"><anchor link="impl-aarch64.SPEStartCounter.1" hover="function: SPEStartCounter(integer counter_index)">SPEStartCounter</anchor>(integer counter_index)</line>
<line>    assert counter_index &lt; <a link="SPEMaxCounters" file="shared_pseudocode.xml" hover="constant integer SPEMaxCounters = 32">SPEMaxCounters</a>;</line>
<line>    SPESampleCounterPending[counter_index] = TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEStopCounter" mylink="aarch64.debug.statisticalprofiling.SPEStopCounter" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPEStopCounter()</line>
<line>// ================</line>
<line>// Disables incrementing of the counter at the passed index when SPECycle is called.</line>
<line></line>
<line link="impl-aarch64.SPEStopCounter.1" hover="function: SPEStopCounter(integer counter_index)" conts="SPEStopCounter"><anchor link="impl-aarch64.SPEStopCounter.1" hover="function: SPEStopCounter(integer counter_index)">SPEStopCounter</anchor>(integer counter_index)</line>
<line>    SPESampleCounterValid[counter_index] = TRUE;</line>
<line>    SPESampleCounterPending[counter_index] = FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEToCollectSample" mylink="aarch64.debug.statisticalprofiling.SPEToCollectSample" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPEToCollectSample()</line>
<line>// ====================</line>
<line>// Returns TRUE if the instruction which is about to be executed should be</line>
<line>// sampled. Returns FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.SPEToCollectSample.0" hover="function: boolean SPEToCollectSample()" conts="SPEToCollectSample">boolean <anchor link="impl-aarch64.SPEToCollectSample.0" hover="function: boolean SPEToCollectSample()">SPEToCollectSample</anchor>()</line>
<line>    if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(PMSICR_EL1.COUNT) then</line>
<line>        <a link="impl-aarch64.SPEResetSampleCounter.0" file="shared_pseudocode.xml" hover="function: SPEResetSampleCounter()">SPEResetSampleCounter</a>();</line>
<line>    else</line>
<line>        PMSICR_EL1.COUNT = PMSICR_EL1.COUNT - 1;</line>
<line>        if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(PMSICR_EL1.COUNT) then</line>
<line>            if PMSIRR_EL1.RND == '1' &amp;&amp; PMSIDR_EL1.ERnd == '1' then</line>
<line>                PMSICR_EL1.ECOUNT = <a link="impl-aarch64.SPEGetRandomInterval.0" file="shared_pseudocode.xml" hover="function: bits(8) SPEGetRandomInterval()">SPEGetRandomInterval</a>();</line>
<line>            else</line>
<line>                return TRUE;</line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PMSICR_EL1.ECOUNT) != 0 then</line>
<line>        PMSICR_EL1.ECOUNT = PMSICR_EL1.ECOUNT - 1;</line>
<line>        if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(PMSICR_EL1.ECOUNT) then</line>
<line>            return TRUE;</line>
<line>    return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/SPEWriteToBuffer" mylink="aarch64.debug.statisticalprofiling.SPEWriteToBuffer" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPEWriteToBuffer()</line>
<line>// ==================</line>
<line>// Write the active record to the Profiling Buffer.</line>
<line></line>
<line link="impl-aarch64.SPEWriteToBuffer.0" hover="function: SPEWriteToBuffer()" conts="SPEWriteToBuffer"><anchor link="impl-aarch64.SPEWriteToBuffer.0" hover="function: SPEWriteToBuffer()">SPEWriteToBuffer</anchor>()</line>
<line>    assert <a link="impl-aarch64.ProfilingBufferEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ProfilingBufferEnabled()">ProfilingBufferEnabled</a>();</line>
<line></line>
<line>    // Check alignment</line>
<line>    boolean aligned = <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(PMBPTR_EL1.PTR&lt;<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PMBIDR_EL1.Align)-1:0&gt;);</line>
<line>    boolean ttw_fault_as_external_abort;</line>
<line>    ttw_fault_as_external_abort = boolean IMPLEMENTATION_DEFINED "SPE TTW fault External abort";</line>
<line></line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault;</line>
<line>    <a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> memstatus;</line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> addrdesc;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc;</line>
<line></line>
<line>    <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> owning_ss;</line>
<line>    bits(2) owning_el;</line>
<line>    (owning_ss, owning_el) = <a link="impl-aarch64.ProfilingBufferOwner.0" file="shared_pseudocode.xml" hover="function: (SecurityState, bits(2)) ProfilingBufferOwner()">ProfilingBufferOwner</a>();</line>
<line>    accdesc = <a link="impl-shared.CreateAccDescSPE.2" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescSPE(SecurityState owning_ss, bits(2) owning_el)">CreateAccDescSPE</a>(owning_ss, owning_el);</line>
<line></line>
<line>    bits(64) start_vaddr = PMBPTR_EL1&lt;63:0&gt;;</line>
<line>    for i = 0 to SPERecordSize - 1</line>
<line>        // If a previous write did not cause an issue</line>
<line>        if PMBSR_EL1.S == '0' then</line>
<line>            (memstatus, addrdesc) = <a link="impl-shared.DebugMemWrite.4" file="shared_pseudocode.xml" hover="function: (PhysMemRetStatus, AddressDescriptor) DebugMemWrite(bits(64) vaddress, AccessDescriptor accdesc, boolean aligned, bits(8) data)">DebugMemWrite</a>(PMBPTR_EL1&lt;63:0&gt;, accdesc, aligned,</line>
<line>                                                  SPERecordData[i]);</line>
<line></line>
<line>            fault = addrdesc.fault;</line>
<line></line>
<line>            boolean ttw_fault;</line>
<line>            ttw_fault = fault.statuscode IN {<a link="Fault_SyncExternalOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncExternalOnWalk</a>, <a link="Fault_SyncParityOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncParityOnWalk</a>};</line>
<line></line>
<line>            if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(fault.statuscode) &amp;&amp; !(ttw_fault &amp;&amp; ttw_fault_as_external_abort) then</line>
<line>                <a link="impl-shared.DebugWriteFault.2" file="shared_pseudocode.xml" hover="function: DebugWriteFault(bits(64) vaddress, FaultRecord fault)">DebugWriteFault</a>(PMBPTR_EL1&lt;63:0&gt;, fault);</line>
<line>            elsif <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) || (ttw_fault &amp;&amp; ttw_fault_as_external_abort) then</line>
<line>                <a link="impl-shared.DebugWriteExternalAbort.3" file="shared_pseudocode.xml" hover="function: DebugWriteExternalAbort(PhysMemRetStatus memstatus, AddressDescriptor addrdesc, bits(64) start_vaddr)">DebugWriteExternalAbort</a>(memstatus, addrdesc, start_vaddr);</line>
<line></line>
<line>            // Move pointer if no Buffer Management Event has been caused.</line>
<line>            if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(PMBSR_EL1.S) then</line>
<line>                PMBPTR_EL1 = PMBPTR_EL1 + 1;</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/StatisticalProfilingEnabled" mylink="aarch64.debug.statisticalprofiling.StatisticalProfilingEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// StatisticalProfilingEnabled()</line>
<line>// =============================</line>
<line>// Return TRUE if Statistical Profiling is Enabled in the current EL, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.StatisticalProfilingEnabled.0" hover="function: boolean StatisticalProfilingEnabled()" conts="StatisticalProfilingEnabled">boolean <anchor link="impl-aarch64.StatisticalProfilingEnabled.0" hover="function: boolean StatisticalProfilingEnabled()">StatisticalProfilingEnabled</anchor>()</line>
<line>    return <a link="impl-aarch64.StatisticalProfilingEnabled.1" file="shared_pseudocode.xml" hover="function: boolean StatisticalProfilingEnabled(bits(2) el)">StatisticalProfilingEnabled</a>(PSTATE.EL);</line>
<line></line>
<line>// StatisticalProfilingEnabled()</line>
<line>// =============================</line>
<line>// Return TRUE if Statistical Profiling is Enabled in the specified EL, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.StatisticalProfilingEnabled.1" hover="function: boolean StatisticalProfilingEnabled(bits(2) el)" conts="StatisticalProfilingEnabled">boolean <anchor link="impl-aarch64.StatisticalProfilingEnabled.1" hover="function: boolean StatisticalProfilingEnabled(bits(2) el)">StatisticalProfilingEnabled</anchor>(bits(2) el)</line>
<line>    if !<a link="impl-shared.HaveStatisticalProfiling.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfiling()">HaveStatisticalProfiling</a>() || <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() || !<a link="impl-aarch64.ProfilingBufferEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ProfilingBufferEnabled()">ProfilingBufferEnabled</a>() then</line>
<line>        return FALSE;</line>
<line></line>
<line>    tge_set = <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1';</line>
<line>    (owning_ss, owning_el) = <a link="impl-aarch64.ProfilingBufferOwner.0" file="shared_pseudocode.xml" hover="function: (SecurityState, bits(2)) ProfilingBufferOwner()">ProfilingBufferOwner</a>();</line>
<line>    if (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(owning_el) &lt;  <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(el) || (tge_set &amp;&amp; owning_el == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) ||</line>
<line>            owning_ss != <a link="impl-shared.SecurityStateAtEL.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)">SecurityStateAtEL</a>(el))  then</line>
<line>        return FALSE;</line>
<line>    bit spe_bit;</line>
<line>    case el of</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>  <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>  spe_bit = PMSCR_EL2.E2SPE;</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>  spe_bit = PMSCR_EL1.E1SPE;</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>  spe_bit = (if tge_set then PMSCR_EL2.E0HSPE else PMSCR_EL1.E0SPE);</line>
<line></line>
<line>    return spe_bit == '1';</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/statisticalprofiling/TimeStamp" mylink="aarch64.debug.statisticalprofiling.TimeStamp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TimeStamp</line>
<line>// =========</line>
<line></line>
<line link="TimeStamp" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }" conts="TimeStamp">enumeration <anchor link="TimeStamp" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp</anchor> {</line>
<line link="TimeStamp_None" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }" conts="TimeStamp_None">    <anchor link="TimeStamp_None" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_None</anchor>,              // No timestamp</line>
<line link="TimeStamp_CoreSight" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }" conts="TimeStamp_CoreSight">    <anchor link="TimeStamp_CoreSight" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_CoreSight</anchor>,         // CoreSight time (IMPLEMENTATION DEFINED)</line>
<line link="TimeStamp_Physical" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }" conts="TimeStamp_Physical">    <anchor link="TimeStamp_Physical" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_Physical</anchor>,          // Physical counter value with no offset</line>
<line link="TimeStamp_OffsetPhysical" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }" conts="TimeStamp_OffsetPhysical">    <anchor link="TimeStamp_OffsetPhysical" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_OffsetPhysical</anchor>,    // Physical counter value minus CNTPOFF_EL2</line>
<line link="TimeStamp_Virtual" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }" conts="TimeStamp_Virtual">    <anchor link="TimeStamp_Virtual" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_Virtual</anchor>  };       // Physical counter value minus CNTVOFF_EL2</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/takeexceptiondbg/AArch64.TakeExceptionInDebugState" mylink="aarch64.debug.takeexceptiondbg.AArch64.TakeExceptionInDebugState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TakeExceptionInDebugState()</line>
<line>// ===================================</line>
<line>// Take an exception in Debug state to an Exception level using AArch64.</line>
<line></line>
<line link="AArch64.TakeExceptionInDebugState.2" hover="function: AArch64.TakeExceptionInDebugState(bits(2) target_el, ExceptionRecord exception_in)" conts="AArch64.TakeExceptionInDebugState"><anchor link="AArch64.TakeExceptionInDebugState.2" hover="function: AArch64.TakeExceptionInDebugState(bits(2) target_el, ExceptionRecord exception_in)">AArch64.TakeExceptionInDebugState</anchor>(bits(2) target_el, <a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception_in)</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(target_el) &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(target_el) &amp;&amp; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(target_el) &gt;= <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL);</line>
<line>    assert target_el != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> || EDSCR.SDD == '0';</line>
<line>    <a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception = exception_in;</line>
<line>    boolean sync_errors;</line>
<line>    boolean iesb_req;</line>
<line>    if <a link="impl-shared.HaveIESB.0" file="shared_pseudocode.xml" hover="function: boolean HaveIESB()">HaveIESB</a>() then</line>
<line>        sync_errors = <a link="impl-aarch64.SCTLR.read.1" file="shared_pseudocode.xml" hover="accessor: SCTLRType SCTLR[bits(2) regime]">SCTLR</a>[target_el].IESB == '1';</line>
<line>        if <a link="impl-shared.HaveDoubleFaultExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDoubleFaultExt()">HaveDoubleFaultExt</a>() then</line>
<line>            sync_errors = sync_errors || (SCR_EL3.&lt;EA,NMEA&gt; == '11' &amp;&amp; target_el == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>        // SCTLR[].IESB and/or SCR_EL3.NMEA (if applicable) might be ignored in Debug state.</line>
<line>        if !<a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_IESBinDebug" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_IESBinDebug</a>) then</line>
<line>            sync_errors = FALSE;</line>
<line>    else</line>
<line>        sync_errors = FALSE;</line>
<line></line>
<line>    if <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0 then</line>
<line>        <a link="TMFailure" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure</a> cause;</line>
<line>        case exception.exceptype of</line>
<line>            when <a link="Exception_SoftwareBreakpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SoftwareBreakpoint</a> cause = <a link="TMFailure_DBG" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_DBG</a>;</line>
<line>            when <a link="Exception_Breakpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Breakpoint</a>         cause = <a link="TMFailure_DBG" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_DBG</a>;</line>
<line>            when <a link="Exception_Watchpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Watchpoint</a>         cause = <a link="TMFailure_DBG" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_DBG</a>;</line>
<line>            when <a link="Exception_SoftwareStep" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SoftwareStep</a>       cause = <a link="TMFailure_DBG" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_DBG</a>;</line>
<line>            otherwise                         cause = <a link="TMFailure_ERR" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_ERR</a>;</line>
<line>        <a link="impl-aarch64.FailTransaction.2" file="shared_pseudocode.xml" hover="function: FailTransaction(TMFailure cause, boolean retry)">FailTransaction</a>(cause, FALSE);</line>
<line></line>
<line>    <a link="impl-shared.SynchronizeContext.0" file="shared_pseudocode.xml" hover="function: SynchronizeContext()">SynchronizeContext</a>();</line>
<line></line>
<line>    // If coming from AArch32 state, the top parts of the X[] registers might be set to zero</line>
<line>    from_32 = <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>();</line>
<line>    if from_32 then <a link="AArch64.MaybeZeroRegisterUppers.0" file="shared_pseudocode.xml" hover="function: AArch64.MaybeZeroRegisterUppers()">AArch64.MaybeZeroRegisterUppers</a>();</line>
<line>    if from_32 &amp;&amp; <a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() &amp;&amp; PSTATE.SM == '1' then</line>
<line>        <a link="impl-aarch64.ResetSVEState.0" file="shared_pseudocode.xml" hover="function: ResetSVEState()">ResetSVEState</a>();</line>
<line>    else</line>
<line>        <a link="impl-aarch64.MaybeZeroSVEUppers.1" file="shared_pseudocode.xml" hover="function: MaybeZeroSVEUppers(bits(2) target_el)">MaybeZeroSVEUppers</a>(target_el);</line>
<line></line>
<line>    <a link="AArch64.ReportException.2" file="shared_pseudocode.xml" hover="function: AArch64.ReportException(ExceptionRecord exception, bits(2) target_el)">AArch64.ReportException</a>(exception, target_el);</line>
<line></line>
<line>    PSTATE.EXLOCK = '0';  // Effective value of GCSCR_ELx.EXLOCKEN is 0 in Debug state</line>
<line></line>
<line>    PSTATE.EL = target_el;</line>
<line>    PSTATE.nRW = '0';</line>
<line>    PSTATE.SP = '1';</line>
<line></line>
<line>    <a link="impl-shared.SPSR.write.0" file="shared_pseudocode.xml" hover="accessor: SPSR[] = bits(N) value">SPSR</a>[] = bits(64) UNKNOWN;</line>
<line>    <a link="impl-aarch64.ELR.write.0" file="shared_pseudocode.xml" hover="accessor: ELR[] = bits(64) value">ELR</a>[] = bits(64) UNKNOWN;</line>
<line></line>
<line>    // PSTATE.{SS,D,A,I,F} are not observable and ignored in Debug state, so behave as if UNKNOWN.</line>
<line>    PSTATE.&lt;SS,D,A,I,F&gt; = bits(5) UNKNOWN;</line>
<line>    PSTATE.IL = '0';</line>
<line>    if from_32 then                             // Coming from AArch32</line>
<line>        PSTATE.IT = '00000000';</line>
<line>        PSTATE.T = '0';                         // PSTATE.J is RES0</line>
<line>    if (<a link="impl-shared.HavePANExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePANExt()">HavePANExt</a>() &amp;&amp; (PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> || (PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> &amp;&amp; <a link="impl-shared.ELIsInHost.1" file="shared_pseudocode.xml" hover="function: boolean ELIsInHost(bits(2) el)">ELIsInHost</a>(<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>))) &amp;&amp;</line>
<line>        <a link="impl-aarch64.SCTLR.read.0" file="shared_pseudocode.xml" hover="accessor: SCTLRType SCTLR[]">SCTLR</a>[].SPAN == '0') then</line>
<line>        PSTATE.PAN = '1';</line>
<line>    if <a link="impl-shared.HaveUAOExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveUAOExt()">HaveUAOExt</a>() then PSTATE.UAO = '0';</line>
<line>    if <a link="impl-shared.HaveBTIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveBTIExt()">HaveBTIExt</a>() then PSTATE.BTYPE = '00';</line>
<line>    if <a link="impl-shared.HaveSSBSExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveSSBSExt()">HaveSSBSExt</a>() then PSTATE.SSBS = bit UNKNOWN;</line>
<line>    if <a link="impl-shared.HaveMTEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEExt()">HaveMTEExt</a>() then PSTATE.TCO = '1';</line>
<line></line>
<line>    DLR_EL0 = bits(64) UNKNOWN;</line>
<line>    DSPSR_EL0 = bits(64) UNKNOWN;</line>
<line></line>
<line>    EDSCR.ERR = '1';</line>
<line>    <a link="impl-shared.UpdateEDSCRFields.0" file="shared_pseudocode.xml" hover="function: UpdateEDSCRFields()">UpdateEDSCRFields</a>();                        // Update EDSCR processor state flags.</line>
<line></line>
<line>    if sync_errors then</line>
<line>        <a link="impl-shared.SynchronizeErrors.0" file="shared_pseudocode.xml" hover="function: SynchronizeErrors()">SynchronizeErrors</a>();</line>
<line></line>
<line>    <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/watchpoint/AArch64.WatchpointByteMatch" mylink="aarch64.debug.watchpoint.AArch64.WatchpointByteMatch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.WatchpointByteMatch()</line>
<line>// =============================</line>
<line></line>
<line link="AArch64.WatchpointByteMatch.2" hover="function: boolean AArch64.WatchpointByteMatch(integer n, bits(64) vaddress)" conts="AArch64.WatchpointByteMatch">boolean <anchor link="AArch64.WatchpointByteMatch.2" hover="function: boolean AArch64.WatchpointByteMatch(integer n, bits(64) vaddress)">AArch64.WatchpointByteMatch</anchor>(integer n, bits(64) vaddress)</line>
<line></line>
<line>    integer top = <a link="impl-aarch64.DebugAddrTop.0" file="shared_pseudocode.xml" hover="function: integer DebugAddrTop()">DebugAddrTop</a>();</line>
<line>    bottom = if DBGWVR_EL1[n]&lt;2&gt; == '1' then 2 else 3;            // Word or doubleword</line>
<line>    byte_select_match = (DBGWCR_EL1[n].BAS&lt;<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(vaddress&lt;bottom-1:0&gt;)&gt; != '0');</line>
<line>    mask = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(DBGWCR_EL1[n].MASK);</line>
<line></line>
<line>    // If DBGWCR_EL1[n].MASK is non-zero value and DBGWCR_EL1[n].BAS is not set to '11111111', or</line>
<line>    // DBGWCR_EL1[n].BAS specifies a non-contiguous set of bytes behavior is CONSTRAINED</line>
<line>    // UNPREDICTABLE.</line>
<line>    if mask &gt; 0 &amp;&amp; !<a link="impl-shared.IsOnes.1" file="shared_pseudocode.xml" hover="function: boolean IsOnes(bits(N) x)">IsOnes</a>(DBGWCR_EL1[n].BAS) then</line>
<line>        byte_select_match = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_WPMASKANDBAS" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_WPMASKANDBAS</a>);</line>
<line>    else</line>
<line>        LSB = (DBGWCR_EL1[n].BAS AND NOT(DBGWCR_EL1[n].BAS - 1));  MSB = (DBGWCR_EL1[n].BAS + LSB);</line>
<line>        if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(MSB AND (MSB - 1)) then                     // Not contiguous</line>
<line>            byte_select_match = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_WPBASCONTIGUOUS" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_WPBASCONTIGUOUS</a>);</line>
<line>            bottom = 3;                                        // For the whole doubleword</line>
<line></line>
<line>    // If the address mask is set to a reserved value, the behavior is CONSTRAINED UNPREDICTABLE.</line>
<line>    if mask &gt; 0 &amp;&amp; mask &lt;= 2 then</line>
<line>        <a link="Constraint" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint</a> c;</line>
<line>        (c, mask) = <a link="impl-shared.ConstrainUnpredictableInteger.3" file="shared_pseudocode.xml" hover="function: (Constraint,integer) ConstrainUnpredictableInteger(integer low, integer high, Unpredictable which)">ConstrainUnpredictableInteger</a>(3, 31, <a link="Unpredictable_RESWPMASK" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESWPMASK</a>);</line>
<line>        assert c IN {<a link="Constraint_DISABLED" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_DISABLED</a>, <a link="Constraint_NONE" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NONE</a>, <a link="Constraint_UNKNOWN" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNKNOWN</a>};</line>
<line>        case c of</line>
<line>            when <a link="Constraint_DISABLED" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_DISABLED</a>  return FALSE;            // Disabled</line>
<line>            when <a link="Constraint_NONE" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NONE</a>      mask = 0;                // No masking</line>
<line>            // Otherwise the value returned by ConstrainUnpredictableInteger is a not-reserved value</line>
<line></line>
<line>    boolean WVR_match;</line>
<line>    if mask &gt; bottom then</line>
<line>        // If the DBGxVR&lt;n&gt;_EL1.RESS field bits are not a sign extension of the MSB</line>
<line>        // of DBGxVR&lt;n&gt;_EL1.VA, it is UNPREDICTABLE whether they appear to be</line>
<line>        // included in the match.</line>
<line>        if !<a link="impl-shared.IsOnes.1" file="shared_pseudocode.xml" hover="function: boolean IsOnes(bits(N) x)">IsOnes</a>(DBGWVR_EL1[n]&lt;63:top&gt;) &amp;&amp; !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(DBGWVR_EL1[n]&lt;63:top&gt;) then</line>
<line>            if <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_DBGxVR_RESS" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_DBGxVR_RESS</a>) then</line>
<line>                top = 63;</line>
<line></line>
<line>        WVR_match = (vaddress&lt;top:mask&gt; == DBGWVR_EL1[n]&lt;top:mask&gt;);</line>
<line>        // If masked bits of DBGWVR_EL1[n] are not zero, the behavior is CONSTRAINED UNPREDICTABLE.</line>
<line>        if WVR_match &amp;&amp; !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(DBGWVR_EL1[n]&lt;mask-1:bottom&gt;) then</line>
<line>            WVR_match = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_WPMASKEDBITS" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_WPMASKEDBITS</a>);</line>
<line>    else</line>
<line>        WVR_match = vaddress&lt;top:bottom&gt; == DBGWVR_EL1[n]&lt;top:bottom&gt;;</line>
<line></line>
<line>    return WVR_match &amp;&amp; byte_select_match;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/watchpoint/AArch64.WatchpointMatch" mylink="aarch64.debug.watchpoint.AArch64.WatchpointMatch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.WatchpointMatch()</line>
<line>// =========================</line>
<line>// Watchpoint matching in an AArch64 translation regime.</line>
<line></line>
<line link="AArch64.WatchpointMatch.4" hover="function: boolean AArch64.WatchpointMatch(integer n, bits(64) vaddress, integer size, AccessDescriptor accdesc)" conts="AArch64.WatchpointMatch">boolean <anchor link="AArch64.WatchpointMatch.4" hover="function: boolean AArch64.WatchpointMatch(integer n, bits(64) vaddress, integer size, AccessDescriptor accdesc)">AArch64.WatchpointMatch</anchor>(integer n, bits(64) vaddress, integer size,</line>
<line>                                <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    assert !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>());</line>
<line>    assert n &lt; <a link="impl-shared.NumWatchpointsImplemented.0" file="shared_pseudocode.xml" hover="function: integer NumWatchpointsImplemented()">NumWatchpointsImplemented</a>();</line>
<line></line>
<line>    enabled = <a link="impl-aarch64.IsWatchpointEnabled.1" file="shared_pseudocode.xml" hover="function: boolean IsWatchpointEnabled(integer n)">IsWatchpointEnabled</a>(n);</line>
<line>    linked = DBGWCR_EL1[n].WT == '1';</line>
<line>    isbreakpnt = FALSE;</line>
<line></line>
<line>    ssce = if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then DBGWCR_EL1[n].SSCE else '0';</line>
<line>    state_match = <a link="AArch64.StateMatch.8" file="shared_pseudocode.xml" hover="function: boolean AArch64.StateMatch(bits(2) ssc_in, bit ssce_in, bit hmc_in, bits(2) pxc_in, boolean linked_in, bits(4) lbn, boolean isbreakpnt, AccessDescriptor accdesc)">AArch64.StateMatch</a>(DBGWCR_EL1[n].SSC, ssce, DBGWCR_EL1[n].HMC, DBGWCR_EL1[n].PAC,</line>
<line>                                     linked, DBGWCR_EL1[n].LBN, isbreakpnt, accdesc);</line>
<line></line>
<line>    boolean ls_match;</line>
<line>    case DBGWCR_EL1[n].LSC&lt;1:0&gt; of</line>
<line>        when '00' ls_match = FALSE;</line>
<line>        when '01' ls_match = accdesc.read;</line>
<line>        when '10' ls_match = accdesc.write || accdesc.acctype == <a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>;</line>
<line>        when '11' ls_match = TRUE;</line>
<line></line>
<line>    value_match = FALSE;</line>
<line>    for byte = 0 to size - 1</line>
<line>        value_match = value_match || <a link="AArch64.WatchpointByteMatch.2" file="shared_pseudocode.xml" hover="function: boolean AArch64.WatchpointByteMatch(integer n, bits(64) vaddress)">AArch64.WatchpointByteMatch</a>(n, vaddress + byte);</line>
<line></line>
<line>    return value_match &amp;&amp; state_match &amp;&amp; ls_match &amp;&amp; enabled;</line>
</pstext>
    </ps>
    <ps name="aarch64/debug/watchpoint/IsWatchpointEnabled" mylink="aarch64.debug.watchpoint.IsWatchpointEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsWatchpointEnabled()</line>
<line>// =====================</line>
<line>// Returns TRUE if the effective value of DBGBCR_EL1[n].E is '1', and FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.IsWatchpointEnabled.1" hover="function: boolean IsWatchpointEnabled(integer n)" conts="IsWatchpointEnabled">boolean <anchor link="impl-aarch64.IsWatchpointEnabled.1" hover="function: boolean IsWatchpointEnabled(integer n)">IsWatchpointEnabled</anchor>(integer n)</line>
<line>    if (n &gt; 15 &amp;&amp;</line>
<line>            ((!<a link="impl-shared.HaltOnBreakpointOrWatchpoint.0" file="shared_pseudocode.xml" hover="function: boolean HaltOnBreakpointOrWatchpoint()">HaltOnBreakpointOrWatchpoint</a>() &amp;&amp; !<a link="impl-aarch64.SelfHostedExtendedBPWPEnabled.0" file="shared_pseudocode.xml" hover="function: boolean SelfHostedExtendedBPWPEnabled()">SelfHostedExtendedBPWPEnabled</a>()) ||</line>
<line>            (<a link="impl-shared.HaltOnBreakpointOrWatchpoint.0" file="shared_pseudocode.xml" hover="function: boolean HaltOnBreakpointOrWatchpoint()">HaltOnBreakpointOrWatchpoint</a>() &amp;&amp; EDSCR2.EBWE == '0'))) then</line>
<line>        return FALSE;</line>
<line>    return DBGWCR_EL1[n].E == '1';</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/aborts/AArch64.Abort" mylink="aarch64.exceptions.aborts.AArch64.Abort" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.Abort()</line>
<line>// ===============</line>
<line>// Abort and Debug exception handling in an AArch64 translation regime.</line>
<line></line>
<line link="AArch64.Abort.2" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)" conts="AArch64.Abort"><anchor link="AArch64.Abort.2" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</anchor>(bits(64) vaddress, <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line></line>
<line>    if <a link="impl-shared.IsDebugException.1" file="shared_pseudocode.xml" hover="function: boolean IsDebugException(FaultRecord fault)">IsDebugException</a>(fault) then</line>
<line>        if fault.access.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> then</line>
<line>            if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fault.debugmoe == <a link="DebugException_VectorCatch" file="shared_pseudocode.xml" hover="constant bits(4) DebugException_VectorCatch = '0101'">DebugException_VectorCatch</a> then</line>
<line>                <a link="AArch64.VectorCatchException.1" file="shared_pseudocode.xml" hover="function: AArch64.VectorCatchException(FaultRecord fault)">AArch64.VectorCatchException</a>(fault);</line>
<line>            else</line>
<line>                <a link="AArch64.BreakpointException.1" file="shared_pseudocode.xml" hover="function: AArch64.BreakpointException(FaultRecord fault)">AArch64.BreakpointException</a>(fault);</line>
<line>        else</line>
<line>            <a link="AArch64.WatchpointException.2" file="shared_pseudocode.xml" hover="function: AArch64.WatchpointException(bits(64) vaddress, FaultRecord fault)">AArch64.WatchpointException</a>(vaddress, fault);</line>
<line>    elsif fault.gpcf.gpf != <a link="GPCF_None" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_None</a> &amp;&amp; <a link="impl-shared.ReportAsGPCException.1" file="shared_pseudocode.xml" hover="function: boolean ReportAsGPCException(FaultRecord fault)">ReportAsGPCException</a>(fault) then</line>
<line>        <a link="impl-aarch64.TakeGPCException.2" file="shared_pseudocode.xml" hover="function: TakeGPCException(bits(64) vaddress, FaultRecord fault)">TakeGPCException</a>(vaddress, fault);</line>
<line>    elsif fault.access.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> then</line>
<line>        <a link="AArch64.InstructionAbort.2" file="shared_pseudocode.xml" hover="function: AArch64.InstructionAbort(bits(64) vaddress, FaultRecord fault)">AArch64.InstructionAbort</a>(vaddress, fault);</line>
<line>    else</line>
<line>        <a link="AArch64.DataAbort.2" file="shared_pseudocode.xml" hover="function: AArch64.DataAbort(bits(64) vaddress, FaultRecord fault)">AArch64.DataAbort</a>(vaddress, fault);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/aborts/AArch64.AbortSyndrome" mylink="aarch64.exceptions.aborts.AArch64.AbortSyndrome" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.AbortSyndrome()</line>
<line>// =======================</line>
<line>// Creates an exception syndrome record for Abort and Watchpoint exceptions</line>
<line>//</line>
<line>// from an AArch64 translation regime.</line>
<line></line>
<line link="AArch64.AbortSyndrome.4" hover="function: ExceptionRecord AArch64.AbortSyndrome(Exception exceptype, FaultRecord fault, bits(64) vaddress, bits(2) target_el)" conts="AArch64.AbortSyndrome">ExceptionRecord <anchor link="AArch64.AbortSyndrome.4" hover="function: ExceptionRecord AArch64.AbortSyndrome(Exception exceptype, FaultRecord fault, bits(64) vaddress, bits(2) target_el)">AArch64.AbortSyndrome</anchor>(<a link="Exception" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception</a> exceptype, <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault,</line>
<line>                                      bits(64) vaddress, bits(2) target_el)</line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(exceptype);</line>
<line></line>
<line>    d_side = exceptype IN {<a link="Exception_DataAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_DataAbort</a>, <a link="Exception_NV2DataAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_NV2DataAbort</a>, <a link="Exception_Watchpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Watchpoint</a>,</line>
<line>                           <a link="Exception_NV2Watchpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_NV2Watchpoint</a>};</line>
<line>    if (<a link="impl-shared.HavePFAR.0" file="shared_pseudocode.xml" hover="function: boolean HavePFAR()">HavePFAR</a>() &amp;&amp;</line>
<line>            ((<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.VM == '1' &amp;&amp; target_el == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) ||</line>
<line>             !<a link="impl-shared.IsExternalSyncAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalSyncAbort(Fault statuscode)">IsExternalSyncAbort</a>(fault))) then</line>
<line>        exception.pavalid = FALSE;</line>
<line>    else</line>
<line>        exception.pavalid = boolean IMPLEMENTATION_DEFINED "PFAR_ELx is valid";</line>
<line></line>
<line>    (exception.syndrome, exception.syndrome2) = <a link="AArch64.FaultSyndrome.3" file="shared_pseudocode.xml" hover="function: (bits(25), bits(24)) AArch64.FaultSyndrome(boolean d_side, FaultRecord fault, boolean pavalid)">AArch64.FaultSyndrome</a>(d_side, fault,</line>
<line>                                                                      exception.pavalid);</line>
<line>    if fault.statuscode == <a link="Fault_TagCheck" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_TagCheck</a> then</line>
<line>        if <a link="impl-shared.HaveMTE4Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE4Ext()">HaveMTE4Ext</a>() then</line>
<line>            exception.vaddress = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(vaddress, 64);</line>
<line>        else</line>
<line>            exception.vaddress = bits(4) UNKNOWN : vaddress&lt;59:0&gt;;</line>
<line>    else</line>
<line>        exception.vaddress = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(vaddress, 64);</line>
<line></line>
<line>    if <a link="impl-shared.IPAValid.1" file="shared_pseudocode.xml" hover="function: boolean IPAValid(FaultRecord fault)">IPAValid</a>(fault) then</line>
<line>        exception.ipavalid = TRUE;</line>
<line>        exception.NS = if fault.ipaddress.paspace == <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a> then '1' else '0';</line>
<line>        exception.ipaddress = fault.ipaddress.address;</line>
<line>    else</line>
<line>        exception.ipavalid = FALSE;</line>
<line></line>
<line>    return exception;</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/aborts/AArch64.CheckPCAlignment" mylink="aarch64.exceptions.aborts.AArch64.CheckPCAlignment" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.CheckPCAlignment()</line>
<line>// ==========================</line>
<line></line>
<line link="AArch64.CheckPCAlignment.0" hover="function: AArch64.CheckPCAlignment()" conts="AArch64.CheckPCAlignment"><anchor link="AArch64.CheckPCAlignment.0" hover="function: AArch64.CheckPCAlignment()">AArch64.CheckPCAlignment</anchor>()</line>
<line>    bits(64) pc = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line></line>
<line>    if pc&lt;1:0&gt; != '00' then</line>
<line>        <a link="AArch64.PCAlignmentFault.0" file="shared_pseudocode.xml" hover="function: AArch64.PCAlignmentFault()">AArch64.PCAlignmentFault</a>();</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/aborts/AArch64.DataAbort" mylink="aarch64.exceptions.aborts.AArch64.DataAbort" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.DataAbort()</line>
<line>// ===================</line>
<line></line>
<line link="AArch64.DataAbort.2" hover="function: AArch64.DataAbort(bits(64) vaddress, FaultRecord fault)" conts="AArch64.DataAbort"><anchor link="AArch64.DataAbort.2" hover="function: AArch64.DataAbort(bits(64) vaddress, FaultRecord fault)">AArch64.DataAbort</anchor>(bits(64) vaddress, <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    bits(2) target_el;</line>
<line>    if <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault) then</line>
<line>        target_el = <a link="AArch64.SyncExternalAbortTarget.1" file="shared_pseudocode.xml" hover="function: bits(2) AArch64.SyncExternalAbortTarget(FaultRecord fault)">AArch64.SyncExternalAbortTarget</a>(fault);</line>
<line>    else</line>
<line>        route_to_el2 = (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp;</line>
<line>                        (HCR_EL2.TGE == '1' ||</line>
<line>                         (<a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() &amp;&amp; fault.gpcf.gpf == <a link="GPCF_Fail" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_Fail</a> &amp;&amp; HCR_EL2.GPF == '1') ||</line>
<line>                         (<a link="impl-shared.HaveNV2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveNV2Ext()">HaveNV2Ext</a>() &amp;&amp; fault.access.acctype == <a link="AccessType_NV2" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_NV2</a>) ||</line>
<line>                         <a link="impl-shared.IsSecondStage.1" file="shared_pseudocode.xml" hover="function: boolean IsSecondStage(FaultRecord fault)">IsSecondStage</a>(fault)));</line>
<line></line>
<line>        if PSTATE.EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then</line>
<line>            target_el = <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line>        elsif PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || route_to_el2 then</line>
<line>            target_el = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>        else</line>
<line>            target_el = <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line></line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    integer vect_offset;</line>
<line></line>
<line>    if <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault) &amp;&amp; <a link="AArch64.RouteToSErrorOffset.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.RouteToSErrorOffset(bits(2) target_el)">AArch64.RouteToSErrorOffset</a>(target_el) then</line>
<line>        vect_offset = 0x180;</line>
<line>    else</line>
<line>        vect_offset = 0x0;</line>
<line></line>
<line>    <a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception;</line>
<line>    if <a link="impl-shared.HaveNV2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveNV2Ext()">HaveNV2Ext</a>() &amp;&amp; fault.access.acctype == <a link="AccessType_NV2" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_NV2</a> then</line>
<line>        exception = <a link="AArch64.AbortSyndrome.4" file="shared_pseudocode.xml" hover="function: ExceptionRecord AArch64.AbortSyndrome(Exception exceptype, FaultRecord fault, bits(64) vaddress, bits(2) target_el)">AArch64.AbortSyndrome</a>(<a link="Exception_NV2DataAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_NV2DataAbort</a>, fault, vaddress, target_el);</line>
<line>    else</line>
<line>        exception = <a link="AArch64.AbortSyndrome.4" file="shared_pseudocode.xml" hover="function: ExceptionRecord AArch64.AbortSyndrome(Exception exceptype, FaultRecord fault, bits(64) vaddress, bits(2) target_el)">AArch64.AbortSyndrome</a>(<a link="Exception_DataAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_DataAbort</a>, fault, vaddress, target_el);</line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(target_el, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/aborts/AArch64.EffectiveTCF" mylink="aarch64.exceptions.aborts.AArch64.EffectiveTCF" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.EffectiveTCF()</line>
<line>// ======================</line>
<line>// Returns the TCF field applied to tag check faults in the given Exception level.</line>
<line></line>
<line link="AArch64.EffectiveTCF.1" hover="function: bits(2) AArch64.EffectiveTCF(bits(2) el)" conts="AArch64.EffectiveTCF">bits(2) <anchor link="AArch64.EffectiveTCF.1" hover="function: bits(2) AArch64.EffectiveTCF(bits(2) el)">AArch64.EffectiveTCF</anchor>(bits(2) el)</line>
<line>    bits(2) tcf;</line>
<line></line>
<line>    <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime = <a link="impl-shared.TranslationRegime.1" file="shared_pseudocode.xml" hover="function: Regime TranslationRegime(bits(2) el)">TranslationRegime</a>(el);</line>
<line></line>
<line>    case regime of</line>
<line>        when <a link="Regime_EL3" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL3</a>  tcf = SCTLR_EL3.TCF;</line>
<line>        when <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>  tcf = SCTLR_EL2.TCF;</line>
<line>        when <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a> tcf = if el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then SCTLR_EL2.TCF0 else SCTLR_EL2.TCF;</line>
<line>        when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> tcf = if el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then SCTLR_EL1.TCF0 else SCTLR_EL1.TCF;</line>
<line>        otherwise        <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    if tcf == '11' then        //reserved value</line>
<line>        if !<a link="impl-shared.HaveMTEAsymFaultExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEAsymFaultExt()">HaveMTEAsymFaultExt</a>() then</line>
<line>            (-,tcf) = <a link="impl-shared.ConstrainUnpredictableBits.2" file="shared_pseudocode.xml" hover="function: (Constraint,bits(width)) ConstrainUnpredictableBits(Unpredictable which, integer width)">ConstrainUnpredictableBits</a>(<a link="Unpredictable_RESTCF" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESTCF</a>, 2);</line>
<line></line>
<line>    return tcf;</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/aborts/AArch64.InstructionAbort" mylink="aarch64.exceptions.aborts.AArch64.InstructionAbort" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.InstructionAbort()</line>
<line>// ==========================</line>
<line></line>
<line link="AArch64.InstructionAbort.2" hover="function: AArch64.InstructionAbort(bits(64) vaddress, FaultRecord fault)" conts="AArch64.InstructionAbort"><anchor link="AArch64.InstructionAbort.2" hover="function: AArch64.InstructionAbort(bits(64) vaddress, FaultRecord fault)">AArch64.InstructionAbort</anchor>(bits(64) vaddress, <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    // External aborts on instruction fetch must be taken synchronously</line>
<line>    if <a link="impl-shared.HaveDoubleFaultExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDoubleFaultExt()">HaveDoubleFaultExt</a>() then assert fault.statuscode != <a link="Fault_AsyncExternal" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncExternal</a>;</line>
<line></line>
<line>    bits(2) target_el;</line>
<line>    if <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault) then</line>
<line>        target_el = <a link="AArch64.SyncExternalAbortTarget.1" file="shared_pseudocode.xml" hover="function: bits(2) AArch64.SyncExternalAbortTarget(FaultRecord fault)">AArch64.SyncExternalAbortTarget</a>(fault);</line>
<line>    else</line>
<line>        route_to_el2 = (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp;</line>
<line>                        (HCR_EL2.TGE == '1' ||</line>
<line>                         (<a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() &amp;&amp; fault.gpcf.gpf == <a link="GPCF_Fail" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_Fail</a> &amp;&amp; HCR_EL2.GPF == '1') ||</line>
<line>                         <a link="impl-shared.IsSecondStage.1" file="shared_pseudocode.xml" hover="function: boolean IsSecondStage(FaultRecord fault)">IsSecondStage</a>(fault)));</line>
<line></line>
<line>        if PSTATE.EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then</line>
<line>            target_el = <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line>        elsif PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || route_to_el2 then</line>
<line>            target_el = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>        else</line>
<line>            target_el = <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line></line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    integer vect_offset;</line>
<line></line>
<line>    if <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault) &amp;&amp; <a link="AArch64.RouteToSErrorOffset.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.RouteToSErrorOffset(bits(2) target_el)">AArch64.RouteToSErrorOffset</a>(target_el) then</line>
<line>        vect_offset = 0x180;</line>
<line>    else</line>
<line>        vect_offset = 0x0;</line>
<line></line>
<line>    <a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception = <a link="AArch64.AbortSyndrome.4" file="shared_pseudocode.xml" hover="function: ExceptionRecord AArch64.AbortSyndrome(Exception exceptype, FaultRecord fault, bits(64) vaddress, bits(2) target_el)">AArch64.AbortSyndrome</a>(<a link="Exception_InstructionAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_InstructionAbort</a>, fault,</line>
<line>                                                      vaddress, target_el);</line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(target_el, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/aborts/AArch64.PCAlignmentFault" mylink="aarch64.exceptions.aborts.AArch64.PCAlignmentFault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.PCAlignmentFault()</line>
<line>// ==========================</line>
<line>// Called on unaligned program counter in AArch64 state.</line>
<line></line>
<line link="AArch64.PCAlignmentFault.0" hover="function: AArch64.PCAlignmentFault()" conts="AArch64.PCAlignmentFault"><anchor link="AArch64.PCAlignmentFault.0" hover="function: AArch64.PCAlignmentFault()">AArch64.PCAlignmentFault</anchor>()</line>
<line></line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x0;</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_PCAlignment" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_PCAlignment</a>);</line>
<line>    exception.vaddress = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    bits(2) target_el = <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>        target_el = PSTATE.EL;</line>
<line>    elsif <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1' then</line>
<line>        target_el = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(target_el, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/aborts/AArch64.PhysicalSErrorTarget" mylink="aarch64.exceptions.aborts.AArch64.PhysicalSErrorTarget" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.PhysicalSErrorTarget()</line>
<line>// ==============================</line>
<line>// Returns a tuple of whether SError exception can be taken and, if so, the target Exception level.</line>
<line></line>
<line link="AArch64.PhysicalSErrorTarget.0" hover="function: (boolean, bits(2)) AArch64.PhysicalSErrorTarget()" conts="AArch64.PhysicalSErrorTarget">(boolean, bits(2)) <anchor link="AArch64.PhysicalSErrorTarget.0" hover="function: (boolean, bits(2)) AArch64.PhysicalSErrorTarget()">AArch64.PhysicalSErrorTarget</anchor>()</line>
<line>    boolean route_to_el3;</line>
<line>    boolean route_to_el2;</line>
<line></line>
<line>    // The exception is explicitly routed to EL3.</line>
<line>    if PSTATE.EL != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then</line>
<line>        route_to_el3 = (<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.EffectiveEA.0" file="shared_pseudocode.xml" hover="function: bit EffectiveEA()">EffectiveEA</a>() == '1');</line>
<line>    else</line>
<line>        route_to_el3 = FALSE;</line>
<line></line>
<line>    // The exception is explicitly routed to EL2.</line>
<line>    if !route_to_el3 &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> then</line>
<line>        route_to_el2 = (HCR_EL2.AMO == '1');</line>
<line>    elsif !route_to_el3 &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        route_to_el2 = (!<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() &amp;&amp; HCR_EL2.&lt;TGE,AMO&gt; != '00');</line>
<line>    else</line>
<line>        route_to_el2 = FALSE;</line>
<line></line>
<line>    // The exception is "masked".</line>
<line>    boolean masked;</line>
<line>    case PSTATE.EL of</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            masked = (<a link="impl-shared.EffectiveEA.0" file="shared_pseudocode.xml" hover="function: bit EffectiveEA()">EffectiveEA</a>()  == '0' || PSTATE.A == '1');</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            masked = (!route_to_el3 &amp;&amp;</line>
<line>                      (HCR_EL2.&lt;TGE,AMO&gt; == '00' || PSTATE.A == '1'));</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>            masked = (!route_to_el3 &amp;&amp; !route_to_el2 &amp;&amp; PSTATE.A == '1');</line>
<line></line>
<line>    // When FEAT_DoubleFault or FEAT_DoubleFault2 is implemented, the mask might be overridden.</line>
<line>    if <a link="impl-shared.HaveDoubleFault2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveDoubleFault2Ext()">HaveDoubleFault2Ext</a>() then</line>
<line>        bit nmea_bit;</line>
<line>        case PSTATE.EL of</line>
<line>            when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>                nmea_bit = SCR_EL3.NMEA;</line>
<line>            when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>                nmea_bit = if <a link="impl-aarch64.IsSCTLR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsSCTLR2EL2Enabled()">IsSCTLR2EL2Enabled</a>() then SCTLR2_EL2.NMEA else '0';</line>
<line>            when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>                nmea_bit = if <a link="impl-aarch64.IsSCTLR2EL1Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsSCTLR2EL1Enabled()">IsSCTLR2EL1Enabled</a>() then SCTLR2_EL1.NMEA else '0';</line>
<line>            when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>                if <a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>                    nmea_bit = if <a link="impl-aarch64.IsSCTLR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsSCTLR2EL2Enabled()">IsSCTLR2EL2Enabled</a>() then SCTLR2_EL2.NMEA else '0';</line>
<line>                else</line>
<line>                    nmea_bit = if <a link="impl-aarch64.IsSCTLR2EL1Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsSCTLR2EL1Enabled()">IsSCTLR2EL1Enabled</a>() then SCTLR2_EL1.NMEA else '0';</line>
<line>        masked = masked &amp;&amp; (nmea_bit == '0');</line>
<line></line>
<line>    elsif <a link="impl-shared.HaveDoubleFaultExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDoubleFaultExt()">HaveDoubleFaultExt</a>() &amp;&amp; PSTATE.EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then</line>
<line>        bit nmea_bit = SCR_EL3.NMEA AND <a link="impl-shared.EffectiveEA.0" file="shared_pseudocode.xml" hover="function: bit EffectiveEA()">EffectiveEA</a>();</line>
<line>        masked = masked &amp;&amp; (nmea_bit == '0');</line>
<line></line>
<line>    boolean route_masked_to_el3;</line>
<line>    boolean route_masked_to_el2;</line>
<line></line>
<line>    if <a link="impl-shared.HaveDoubleFault2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveDoubleFault2Ext()">HaveDoubleFault2Ext</a>() then</line>
<line>        // The masked exception is routed to EL2.</line>
<line>        route_masked_to_el2 = (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !route_to_el3 &amp;&amp;</line>
<line>                               <a link="impl-aarch64.IsHCRXEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsHCRXEL2Enabled()">IsHCRXEL2Enabled</a>() &amp;&amp; HCRX_EL2.TMEA == '1' &amp;&amp;</line>
<line>                               ((PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; (PSTATE.A == '1' || masked)) ||</line>
<line>                               (PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; masked &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>())));</line>
<line></line>
<line>        // The masked exception is routed to EL3.</line>
<line>        route_masked_to_el3 = (<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.TMEA == '1' &amp;&amp;</line>
<line>                               !(route_to_el2 || route_masked_to_el2) &amp;&amp;</line>
<line>                               ((PSTATE.EL IN {<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp;</line>
<line>                                   (PSTATE.A == '1' || masked)) ||</line>
<line>                                   (PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; masked)));</line>
<line>    else</line>
<line>        route_masked_to_el2 = FALSE;</line>
<line>        route_masked_to_el3 = FALSE;</line>
<line></line>
<line>    // The exception is taken at EL3.</line>
<line>    take_in_el3 = PSTATE.EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> &amp;&amp; !masked;</line>
<line></line>
<line>    // The exception is taken at EL2 or in the Host EL0.</line>
<line>    take_in_el2_0 = ((PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || <a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>()) &amp;&amp;</line>
<line>                     !(route_to_el3 || route_masked_to_el3) &amp;&amp; !masked);</line>
<line></line>
<line>    // The exception is taken at EL1 or in the non-Host EL0.</line>
<line>    take_in_el1_0 = ((PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> || (PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>())) &amp;&amp;</line>
<line>                     !(route_to_el2 || route_masked_to_el2) &amp;&amp;</line>
<line>                     !(route_to_el3 || route_masked_to_el3) &amp;&amp; !masked);</line>
<line></line>
<line>    bits(2) target_el;</line>
<line>    if take_in_el3 || route_to_el3 || route_masked_to_el3 then</line>
<line>        masked = FALSE;  target_el = <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line>    elsif take_in_el2_0 || route_to_el2 || route_masked_to_el2 then</line>
<line>        masked = FALSE;  target_el = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>    elsif take_in_el1_0 then</line>
<line>        masked = FALSE;  target_el = <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>    else</line>
<line>        masked = TRUE;  target_el = bits(2) UNKNOWN;</line>
<line></line>
<line>    return (masked, target_el);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/aborts/AArch64.RaiseTagCheckFault" mylink="aarch64.exceptions.aborts.AArch64.RaiseTagCheckFault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.RaiseTagCheckFault()</line>
<line>// ============================</line>
<line>// Raise a tag check fault exception.</line>
<line></line>
<line link="AArch64.RaiseTagCheckFault.2" hover="function: AArch64.RaiseTagCheckFault(bits(64) va, FaultRecord fault)" conts="AArch64.RaiseTagCheckFault"><anchor link="AArch64.RaiseTagCheckFault.2" hover="function: AArch64.RaiseTagCheckFault(bits(64) va, FaultRecord fault)">AArch64.RaiseTagCheckFault</anchor>(bits(64) va, <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    integer vect_offset = 0x0;</line>
<line>    bits(2) target_el = <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>        target_el = PSTATE.EL;</line>
<line>    elsif PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1' then</line>
<line>        target_el = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line></line>
<line>    exception = <a link="AArch64.AbortSyndrome.4" file="shared_pseudocode.xml" hover="function: ExceptionRecord AArch64.AbortSyndrome(Exception exceptype, FaultRecord fault, bits(64) vaddress, bits(2) target_el)">AArch64.AbortSyndrome</a>(<a link="Exception_DataAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_DataAbort</a>, fault, va, target_el);</line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(target_el, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/aborts/AArch64.ReportTagCheckFault" mylink="aarch64.exceptions.aborts.AArch64.ReportTagCheckFault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ReportTagCheckFault()</line>
<line>// =============================</line>
<line>// Records a tag check fault exception into the appropriate TFSR_ELx.</line>
<line></line>
<line link="AArch64.ReportTagCheckFault.2" hover="function: AArch64.ReportTagCheckFault(bits(2) el, bit ttbr)" conts="AArch64.ReportTagCheckFault"><anchor link="AArch64.ReportTagCheckFault.2" hover="function: AArch64.ReportTagCheckFault(bits(2) el, bit ttbr)">AArch64.ReportTagCheckFault</anchor>(bits(2) el, bit ttbr)</line>
<line>    case el of</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> assert ttbr == '0'; TFSR_EL3.TF0   = '1';</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> if ttbr == '0' then TFSR_EL2.TF0   = '1'; else TFSR_EL2.TF1   = '1';</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> if ttbr == '0' then TFSR_EL1.TF0   = '1'; else TFSR_EL1.TF1   = '1';</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> if ttbr == '0' then TFSRE0_EL1.TF0 = '1'; else TFSRE0_EL1.TF1 = '1';</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/aborts/AArch64.RouteToSErrorOffset" mylink="aarch64.exceptions.aborts.AArch64.RouteToSErrorOffset" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.RouteToSErrorOffset()</line>
<line>// =============================</line>
<line>// Returns TRUE if synchronous External abort exceptions are taken to the</line>
<line>// appropriate SError vector offset, and FALSE otherwise.</line>
<line></line>
<line link="AArch64.RouteToSErrorOffset.1" hover="function: boolean AArch64.RouteToSErrorOffset(bits(2) target_el)" conts="AArch64.RouteToSErrorOffset">boolean <anchor link="AArch64.RouteToSErrorOffset.1" hover="function: boolean AArch64.RouteToSErrorOffset(bits(2) target_el)">AArch64.RouteToSErrorOffset</anchor>(bits(2) target_el)</line>
<line>    if !<a link="impl-shared.HaveDoubleFaultExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDoubleFaultExt()">HaveDoubleFaultExt</a>() then return FALSE;</line>
<line></line>
<line>    bit ease_bit;</line>
<line>    case target_el of</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            ease_bit = SCR_EL3.EASE;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            if <a link="impl-shared.HaveDoubleFault2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveDoubleFault2Ext()">HaveDoubleFault2Ext</a>() &amp;&amp; <a link="impl-aarch64.IsSCTLR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsSCTLR2EL2Enabled()">IsSCTLR2EL2Enabled</a>() then</line>
<line>                ease_bit = SCTLR2_EL2.EASE;</line>
<line>            else</line>
<line>                ease_bit = '0';</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            if <a link="impl-shared.HaveDoubleFault2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveDoubleFault2Ext()">HaveDoubleFault2Ext</a>() &amp;&amp; <a link="impl-aarch64.IsSCTLR2EL1Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsSCTLR2EL1Enabled()">IsSCTLR2EL1Enabled</a>() then</line>
<line>                ease_bit = SCTLR2_EL1.EASE;</line>
<line>            else</line>
<line>                ease_bit = '0';</line>
<line></line>
<line>    return (ease_bit == '1');</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/aborts/AArch64.SPAlignmentFault" mylink="aarch64.exceptions.aborts.AArch64.SPAlignmentFault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.SPAlignmentFault()</line>
<line>// ==========================</line>
<line>// Called on an unaligned stack pointer in AArch64 state.</line>
<line></line>
<line link="AArch64.SPAlignmentFault.0" hover="function: AArch64.SPAlignmentFault()" conts="AArch64.SPAlignmentFault"><anchor link="AArch64.SPAlignmentFault.0" hover="function: AArch64.SPAlignmentFault()">AArch64.SPAlignmentFault</anchor>()</line>
<line></line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x0;</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_SPAlignment" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SPAlignment</a>);</line>
<line></line>
<line>    bits(2) target_el = <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>        target_el = PSTATE.EL;</line>
<line>    elsif <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1' then</line>
<line>        target_el = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(target_el, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/aborts/AArch64.SyncExternalAbortTarget" mylink="aarch64.exceptions.aborts.AArch64.SyncExternalAbortTarget" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.SyncExternalAbortTarget()</line>
<line>// =================================</line>
<line>// Returns the target Exception level for a Synchronous External</line>
<line>// Data or Instruction Abort.</line>
<line></line>
<line link="AArch64.SyncExternalAbortTarget.1" hover="function: bits(2) AArch64.SyncExternalAbortTarget(FaultRecord fault)" conts="AArch64.SyncExternalAbortTarget">bits(2) <anchor link="AArch64.SyncExternalAbortTarget.1" hover="function: bits(2) AArch64.SyncExternalAbortTarget(FaultRecord fault)">AArch64.SyncExternalAbortTarget</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    boolean route_to_el3;</line>
<line></line>
<line>    // The exception is explicitly routed to EL3</line>
<line>    if PSTATE.EL != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then</line>
<line>        route_to_el3 = (<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.EffectiveEA.0" file="shared_pseudocode.xml" hover="function: bit EffectiveEA()">EffectiveEA</a>() == '1');</line>
<line>    else</line>
<line>        route_to_el3 = FALSE;</line>
<line></line>
<line>    // The exception is explicitly routed to EL2</line>
<line>    bit tea_bit = (if <a link="impl-shared.HaveRASExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveRASExt()">HaveRASExt</a>() then HCR_EL2.TEA else '0');</line>
<line></line>
<line>    boolean route_to_el2;</line>
<line>    if !route_to_el3 &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> then</line>
<line>        route_to_el2 = (tea_bit == '1' ||</line>
<line>                        fault.access.acctype == <a link="AccessType_NV2" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_NV2</a> ||</line>
<line>                        <a link="impl-shared.IsSecondStage.1" file="shared_pseudocode.xml" hover="function: boolean IsSecondStage(FaultRecord fault)">IsSecondStage</a>(fault));</line>
<line></line>
<line>    elsif !route_to_el3 &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        route_to_el2 = (!<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() &amp;&amp; (HCR_EL2.TGE == '1' || tea_bit == '1' ||</line>
<line>                        <a link="impl-shared.IsSecondStage.1" file="shared_pseudocode.xml" hover="function: boolean IsSecondStage(FaultRecord fault)">IsSecondStage</a>(fault)));</line>
<line>    else</line>
<line>        route_to_el2 = FALSE;</line>
<line></line>
<line>    boolean route_masked_to_el3;</line>
<line>    boolean route_masked_to_el2;</line>
<line></line>
<line>    if <a link="impl-shared.HaveDoubleFault2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveDoubleFault2Ext()">HaveDoubleFault2Ext</a>() then</line>
<line>        // The masked exception is routed to EL2</line>
<line>        route_masked_to_el2 = (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !route_to_el3 &amp;&amp;</line>
<line>                               (PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; PSTATE.A == '1') &amp;&amp;</line>
<line>                               <a link="impl-aarch64.IsHCRXEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsHCRXEL2Enabled()">IsHCRXEL2Enabled</a>() &amp;&amp; HCRX_EL2.TMEA == '1');</line>
<line></line>
<line>        // The masked exception is routed to EL3</line>
<line>        route_masked_to_el3 = (<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp;</line>
<line>                               !(route_to_el2 || route_masked_to_el2) &amp;&amp;</line>
<line>                               (PSTATE.EL IN {<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; PSTATE.A == '1') &amp;&amp;</line>
<line>                               SCR_EL3.TMEA == '1');</line>
<line>    else</line>
<line>        route_masked_to_el2 = FALSE;</line>
<line>        route_masked_to_el3 = FALSE;</line>
<line></line>
<line>    // The exception is taken at EL3</line>
<line>    take_in_el3 = PSTATE.EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line></line>
<line>    // The exception is taken at EL2 or in the Host EL0</line>
<line>    take_in_el2_0 = ((PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || <a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>()) &amp;&amp;</line>
<line>                     !(route_to_el3 || route_masked_to_el3));</line>
<line></line>
<line>    // The exception is taken at EL1 or in the non-Host EL0</line>
<line>    take_in_el1_0 = ((PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> || (PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>())) &amp;&amp;</line>
<line>                     !(route_to_el2 || route_masked_to_el2) &amp;&amp;</line>
<line>                     !(route_to_el3 || route_masked_to_el3));</line>
<line></line>
<line>    bits(2) target_el;</line>
<line>    if take_in_el3 || route_to_el3 || route_masked_to_el3 then</line>
<line>        target_el = <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line>    elsif take_in_el2_0 || route_to_el2 || route_masked_to_el2 then</line>
<line>        target_el = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>    elsif take_in_el1_0 then</line>
<line>        target_el = <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>    else</line>
<line>        assert(FALSE);</line>
<line></line>
<line>    return target_el;</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/aborts/AArch64.TagCheckFault" mylink="aarch64.exceptions.aborts.AArch64.TagCheckFault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TagCheckFault()</line>
<line>// =======================</line>
<line>// Handle a tag check fault condition.</line>
<line></line>
<line link="AArch64.TagCheckFault.2" hover="function: AArch64.TagCheckFault(bits(64) vaddress, AccessDescriptor accdesc)" conts="AArch64.TagCheckFault"><anchor link="AArch64.TagCheckFault.2" hover="function: AArch64.TagCheckFault(bits(64) vaddress, AccessDescriptor accdesc)">AArch64.TagCheckFault</anchor>(bits(64) vaddress, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    bits(2) tcf;</line>
<line></line>
<line>    tcf = <a link="AArch64.EffectiveTCF.1" file="shared_pseudocode.xml" hover="function: bits(2) AArch64.EffectiveTCF(bits(2) el)">AArch64.EffectiveTCF</a>(accdesc.el);</line>
<line></line>
<line>    fault = <a link="impl-shared.NoFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord NoFault(AccessDescriptor accdesc)">NoFault</a>(accdesc);</line>
<line>    fault.statuscode = <a link="Fault_TagCheck" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_TagCheck</a>;</line>
<line></line>
<line>    case tcf of</line>
<line>        when '00'   // Tag Check Faults have no effect on the PE</line>
<line>            return;</line>
<line>        when '01'   // Tag Check Faults cause a synchronous exception</line>
<line>            <a link="AArch64.RaiseTagCheckFault.2" file="shared_pseudocode.xml" hover="function: AArch64.RaiseTagCheckFault(bits(64) va, FaultRecord fault)">AArch64.RaiseTagCheckFault</a>(vaddress, fault);</line>
<line>        when '10'</line>
<line>            if <a link="impl-shared.HaveMTEAsyncExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEAsyncExt()">HaveMTEAsyncExt</a>() then</line>
<line>                // If asynchronous faults are implemented,</line>
<line>                // Tag Check Faults are asynchronously accumulated</line>
<line>                <a link="AArch64.ReportTagCheckFault.2" file="shared_pseudocode.xml" hover="function: AArch64.ReportTagCheckFault(bits(2) el, bit ttbr)">AArch64.ReportTagCheckFault</a>(accdesc.el, vaddress&lt;55&gt;);</line>
<line>            else</line>
<line>                // Otherwise, Tag Check Faults have no effect on the PE.</line>
<line>                return;</line>
<line>        when '11'</line>
<line>            if <a link="impl-shared.HaveMTEAsymFaultExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEAsymFaultExt()">HaveMTEAsymFaultExt</a>() then</line>
<line>                // Tag Check Faults cause a synchronous exception on reads or on</line>
<line>                // a read/write access, and are asynchronously accumulated on writes</line>
<line>                if accdesc.read then</line>
<line>                    <a link="AArch64.RaiseTagCheckFault.2" file="shared_pseudocode.xml" hover="function: AArch64.RaiseTagCheckFault(bits(64) va, FaultRecord fault)">AArch64.RaiseTagCheckFault</a>(vaddress, fault);</line>
<line>                else</line>
<line>                    <a link="AArch64.ReportTagCheckFault.2" file="shared_pseudocode.xml" hover="function: AArch64.ReportTagCheckFault(bits(2) el, bit ttbr)">AArch64.ReportTagCheckFault</a>(accdesc.el, vaddress&lt;55&gt;);</line>
<line>            else</line>
<line>                // Otherwise, Tag Check Faults have no effect on the PE.</line>
<line>                return;</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/aborts/BranchTargetException" mylink="aarch64.exceptions.aborts.BranchTargetException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BranchTargetException()</line>
<line>// =======================</line>
<line>// Raise branch target exception.</line>
<line></line>
<line link="AArch64.BranchTargetException.1" hover="function: AArch64.BranchTargetException(bits(52) vaddress)" conts="AArch64.BranchTargetException"><anchor link="AArch64.BranchTargetException.1" hover="function: AArch64.BranchTargetException(bits(52) vaddress)">AArch64.BranchTargetException</anchor>(bits(52) vaddress)</line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x0;</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_BranchTarget" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_BranchTarget</a>);</line>
<line>    exception.syndrome&lt;1:0&gt;   = PSTATE.BTYPE;</line>
<line>    exception.syndrome&lt;24:2&gt;  = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(23);         // RES0</line>
<line></line>
<line>    bits(2) target_el = <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>        target_el = PSTATE.EL;</line>
<line>    elsif PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1' then</line>
<line>        target_el = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(target_el, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/aborts/TakeGPCException" mylink="aarch64.exceptions.aborts.TakeGPCException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TakeGPCException()</line>
<line>// ==================</line>
<line>// Report Granule Protection Exception faults</line>
<line></line>
<line link="impl-aarch64.TakeGPCException.2" hover="function: TakeGPCException(bits(64) vaddress, FaultRecord fault)" conts="TakeGPCException"><anchor link="impl-aarch64.TakeGPCException.2" hover="function: TakeGPCException(bits(64) vaddress, FaultRecord fault)">TakeGPCException</anchor>(bits(64) vaddress, <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    assert <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>();</line>
<line>    assert <a link="impl-shared.HaveAtomicExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAtomicExt()">HaveAtomicExt</a>();</line>
<line>    assert <a link="impl-shared.HaveAccessFlagUpdateExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAccessFlagUpdateExt()">HaveAccessFlagUpdateExt</a>();</line>
<line>    assert <a link="impl-shared.HaveDirtyBitModifierExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDirtyBitModifierExt()">HaveDirtyBitModifierExt</a>();</line>
<line>    assert <a link="impl-shared.HaveDoubleFaultExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDoubleFaultExt()">HaveDoubleFaultExt</a>();</line>
<line></line>
<line>    <a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception;</line>
<line></line>
<line>    exception.exceptype = <a link="Exception_GPC" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_GPC</a>;</line>
<line>    exception.vaddress  = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(vaddress, 64);</line>
<line>    exception.paddress  = fault.paddress;</line>
<line>    exception.pavalid   = TRUE;</line>
<line></line>
<line>    if <a link="impl-shared.IPAValid.1" file="shared_pseudocode.xml" hover="function: boolean IPAValid(FaultRecord fault)">IPAValid</a>(fault) then</line>
<line>        exception.ipavalid  = TRUE;</line>
<line>        exception.NS        = if fault.ipaddress.paspace == <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a> then '1' else '0';</line>
<line>        exception.ipaddress = fault.ipaddress.address;</line>
<line>    else</line>
<line>        exception.ipavalid = FALSE;</line>
<line></line>
<line>    if fault.access.acctype == <a link="AccessType_GCS" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GCS</a> then</line>
<line>        exception.syndrome2&lt;8&gt; = '1'; //GCS</line>
<line></line>
<line>    // Populate the fields grouped in ISS</line>
<line>    exception.syndrome&lt;24:22&gt; = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(3); // RES0</line>
<line>    exception.syndrome&lt;21&gt;    = if fault.gpcfs2walk then '1' else '0';  // S2PTW</line>
<line>    if fault.access.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> then</line>
<line>        exception.syndrome&lt;20&gt; = '1'; // InD</line>
<line>    else</line>
<line>        exception.syndrome&lt;20&gt; = '0'; // InD</line>
<line>    exception.syndrome&lt;19:14&gt; = <a link="impl-aarch64.EncodeGPCSC.1" file="shared_pseudocode.xml" hover="function: bits(6) EncodeGPCSC(GPCFRecord gpcf)">EncodeGPCSC</a>(fault.gpcf); // GPCSC</line>
<line>    if <a link="impl-shared.HaveNV2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveNV2Ext()">HaveNV2Ext</a>() &amp;&amp; fault.access.acctype == <a link="AccessType_NV2" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_NV2</a> then</line>
<line>        exception.syndrome&lt;13&gt; = '1'; // VNCR</line>
<line>    else</line>
<line>        exception.syndrome&lt;13&gt; = '0'; // VNCR</line>
<line>    exception.syndrome&lt;12:11&gt; = '00'; // RES0</line>
<line>    exception.syndrome&lt;10:9&gt;  = '00'; // RES0</line>
<line></line>
<line>    if fault.access.acctype IN {<a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>, <a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a>, <a link="AccessType_AT" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_AT</a>} then</line>
<line>        exception.syndrome&lt;8&gt; = '1'; // CM</line>
<line>    else</line>
<line>        exception.syndrome&lt;8&gt; = '0';  // CM</line>
<line></line>
<line>    exception.syndrome&lt;7&gt; = if fault.s2fs1walk then '1' else '0'; // S1PTW</line>
<line></line>
<line>    if fault.access.acctype IN {<a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>, <a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a>, <a link="AccessType_AT" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_AT</a>} then</line>
<line>        exception.syndrome&lt;6&gt; = '1';                              // WnR</line>
<line>    elsif fault.statuscode IN {<a link="Fault_HWUpdateAccessFlag" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_HWUpdateAccessFlag</a>, <a link="Fault_Exclusive" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Exclusive</a>} then</line>
<line>        exception.syndrome&lt;6&gt; = bit UNKNOWN;                      // WnR</line>
<line>    elsif fault.access.atomicop &amp;&amp; <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault) then</line>
<line>        exception.syndrome&lt;6&gt; = bit UNKNOWN;                      // WnR</line>
<line>    else</line>
<line>        exception.syndrome&lt;6&gt; = if fault.write then '1' else '0'; // WnR</line>
<line></line>
<line>    exception.syndrome&lt;5:0&gt; = <a link="impl-shared.EncodeLDFSC.2" file="shared_pseudocode.xml" hover="function: bits(6) EncodeLDFSC(Fault statuscode, integer level)">EncodeLDFSC</a>(fault.statuscode, fault.level); // xFSC</line>
<line></line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    bits(2) target_el = <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line></line>
<line>    integer vect_offset;</line>
<line>    if <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault) &amp;&amp; <a link="AArch64.RouteToSErrorOffset.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.RouteToSErrorOffset(bits(2) target_el)">AArch64.RouteToSErrorOffset</a>(target_el) then</line>
<line>        vect_offset = 0x180;</line>
<line>    else</line>
<line>        vect_offset = 0x0;</line>
<line></line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(target_el, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/async/AArch64.TakePhysicalFIQException" mylink="aarch64.exceptions.async.AArch64.TakePhysicalFIQException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TakePhysicalFIQException()</line>
<line>// ==================================</line>
<line></line>
<line link="AArch64.TakePhysicalFIQException.0" hover="function: AArch64.TakePhysicalFIQException()" conts="AArch64.TakePhysicalFIQException"><anchor link="AArch64.TakePhysicalFIQException.0" hover="function: AArch64.TakePhysicalFIQException()">AArch64.TakePhysicalFIQException</anchor>()</line>
<line></line>
<line>    route_to_el3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.FIQ == '1';</line>
<line>    route_to_el2 = (PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>                    (HCR_EL2.TGE == '1' || HCR_EL2.FMO == '1'));</line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x100;</line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_FIQ" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FIQ</a>);</line>
<line></line>
<line>    if route_to_el3 then</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, exception, preferred_exception_return, vect_offset);</line>
<line>    elsif PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || route_to_el2 then</line>
<line>        assert PSTATE.EL != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, exception, preferred_exception_return, vect_offset);</line>
<line>    else</line>
<line>        assert PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/async/AArch64.TakePhysicalIRQException" mylink="aarch64.exceptions.async.AArch64.TakePhysicalIRQException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TakePhysicalIRQException()</line>
<line>// ==================================</line>
<line>// Take an enabled physical IRQ exception.</line>
<line></line>
<line link="AArch64.TakePhysicalIRQException.0" hover="function: AArch64.TakePhysicalIRQException()" conts="AArch64.TakePhysicalIRQException"><anchor link="AArch64.TakePhysicalIRQException.0" hover="function: AArch64.TakePhysicalIRQException()">AArch64.TakePhysicalIRQException</anchor>()</line>
<line></line>
<line>    route_to_el3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.IRQ == '1';</line>
<line>    route_to_el2 = (PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>                    (HCR_EL2.TGE == '1' || HCR_EL2.IMO == '1'));</line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x80;</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_IRQ" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_IRQ</a>);</line>
<line></line>
<line>    if route_to_el3 then</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, exception, preferred_exception_return, vect_offset);</line>
<line>    elsif PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || route_to_el2 then</line>
<line>        assert PSTATE.EL != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, exception, preferred_exception_return, vect_offset);</line>
<line>    else</line>
<line>        assert PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/async/AArch64.TakePhysicalSErrorException" mylink="aarch64.exceptions.async.AArch64.TakePhysicalSErrorException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TakePhysicalSErrorException()</line>
<line>// =====================================</line>
<line></line>
<line link="AArch64.TakePhysicalSErrorException.1" hover="function: AArch64.TakePhysicalSErrorException(boolean implicit_esb)" conts="AArch64.TakePhysicalSErrorException"><anchor link="AArch64.TakePhysicalSErrorException.1" hover="function: AArch64.TakePhysicalSErrorException(boolean implicit_esb)">AArch64.TakePhysicalSErrorException</anchor>(boolean implicit_esb)</line>
<line></line>
<line>    route_to_el3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.EA == '1';</line>
<line>    route_to_el2 = (PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>                    (HCR_EL2.TGE == '1' || (!<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() &amp;&amp; HCR_EL2.AMO == '1')));</line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x180;</line>
<line></line>
<line>    bits(2) target_el;</line>
<line>    if PSTATE.EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> || route_to_el3 then</line>
<line>        target_el = <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line>    elsif PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || route_to_el2 then</line>
<line>        target_el = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>    else</line>
<line>        target_el = <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_SError" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SError</a>);</line>
<line>    bits(25) syndrome = <a link="AArch64.PhysicalSErrorSyndrome.1" file="shared_pseudocode.xml" hover="function: bits(25) AArch64.PhysicalSErrorSyndrome(boolean implicit_esb)">AArch64.PhysicalSErrorSyndrome</a>(implicit_esb);</line>
<line>    if <a link="impl-shared.IsSErrorEdgeTriggered.0" file="shared_pseudocode.xml" hover="function: boolean IsSErrorEdgeTriggered()">IsSErrorEdgeTriggered</a>() then</line>
<line>        <a link="impl-shared.ClearPendingPhysicalSError.0" file="shared_pseudocode.xml" hover="function: ClearPendingPhysicalSError()">ClearPendingPhysicalSError</a>();</line>
<line>    exception.syndrome = syndrome;</line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(target_el, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/async/AArch64.TakeVirtualFIQException" mylink="aarch64.exceptions.async.AArch64.TakeVirtualFIQException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TakeVirtualFIQException()</line>
<line>// =================================</line>
<line></line>
<line link="AArch64.TakeVirtualFIQException.0" hover="function: AArch64.TakeVirtualFIQException()" conts="AArch64.TakeVirtualFIQException"><anchor link="AArch64.TakeVirtualFIQException.0" hover="function: AArch64.TakeVirtualFIQException()">AArch64.TakeVirtualFIQException</anchor>()</line>
<line>    assert PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>();</line>
<line>    assert HCR_EL2.TGE == '0' &amp;&amp; HCR_EL2.FMO == '1';  // Virtual IRQ enabled if TGE==0 and FMO==1</line>
<line></line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x100;</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_FIQ" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FIQ</a>);</line>
<line></line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/async/AArch64.TakeVirtualIRQException" mylink="aarch64.exceptions.async.AArch64.TakeVirtualIRQException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TakeVirtualIRQException()</line>
<line>// =================================</line>
<line></line>
<line link="AArch64.TakeVirtualIRQException.0" hover="function: AArch64.TakeVirtualIRQException()" conts="AArch64.TakeVirtualIRQException"><anchor link="AArch64.TakeVirtualIRQException.0" hover="function: AArch64.TakeVirtualIRQException()">AArch64.TakeVirtualIRQException</anchor>()</line>
<line>    assert PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>();</line>
<line>    assert HCR_EL2.TGE == '0' &amp;&amp; HCR_EL2.IMO == '1';  // Virtual IRQ enabled if TGE==0 and IMO==1</line>
<line></line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x80;</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_IRQ" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_IRQ</a>);</line>
<line></line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/async/AArch64.TakeVirtualSErrorException" mylink="aarch64.exceptions.async.AArch64.TakeVirtualSErrorException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TakeVirtualSErrorException()</line>
<line>// ====================================</line>
<line></line>
<line link="AArch64.TakeVirtualSErrorException.0" hover="function: AArch64.TakeVirtualSErrorException()" conts="AArch64.TakeVirtualSErrorException"><anchor link="AArch64.TakeVirtualSErrorException.0" hover="function: AArch64.TakeVirtualSErrorException()">AArch64.TakeVirtualSErrorException</anchor>()</line>
<line></line>
<line>    assert PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>();</line>
<line>    assert HCR_EL2.TGE == '0' &amp;&amp; HCR_EL2.AMO == '1';  // Virtual SError enabled if TGE==0 and AMO==1</line>
<line></line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x180;</line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_SError" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SError</a>);</line>
<line></line>
<line>    if <a link="impl-shared.HaveRASExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveRASExt()">HaveRASExt</a>() then</line>
<line>        exception.syndrome&lt;24&gt;   = VSESR_EL2.IDS;</line>
<line>        exception.syndrome&lt;23:0&gt; = VSESR_EL2.ISS;</line>
<line>    else</line>
<line>        bits(25) syndrome = bits(25) IMPLEMENTATION_DEFINED "Virtual SError syndrome";</line>
<line>        impdef_syndrome = syndrome&lt;24&gt; == '1';</line>
<line>        if impdef_syndrome then exception.syndrome = syndrome;</line>
<line></line>
<line>    <a link="impl-shared.ClearPendingVirtualSError.0" file="shared_pseudocode.xml" hover="function: ClearPendingVirtualSError()">ClearPendingVirtualSError</a>();</line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/debug/AArch64.BreakpointException" mylink="aarch64.exceptions.debug.AArch64.BreakpointException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.BreakpointException()</line>
<line>// =============================</line>
<line></line>
<line link="AArch64.BreakpointException.1" hover="function: AArch64.BreakpointException(FaultRecord fault)" conts="AArch64.BreakpointException"><anchor link="AArch64.BreakpointException.1" hover="function: AArch64.BreakpointException(FaultRecord fault)">AArch64.BreakpointException</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    assert PSTATE.EL != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line></line>
<line>    route_to_el2 = (PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>                    (HCR_EL2.TGE == '1' || MDCR_EL2.TDE == '1'));</line>
<line></line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    bits(2) target_el;</line>
<line>    vect_offset = 0x0;</line>
<line>    target_el = if (PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || route_to_el2) then <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> else <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line></line>
<line>    vaddress = bits(64) UNKNOWN;</line>
<line>    exception = <a link="AArch64.AbortSyndrome.4" file="shared_pseudocode.xml" hover="function: ExceptionRecord AArch64.AbortSyndrome(Exception exceptype, FaultRecord fault, bits(64) vaddress, bits(2) target_el)">AArch64.AbortSyndrome</a>(<a link="Exception_Breakpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Breakpoint</a>, fault, vaddress, target_el);</line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(target_el, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/debug/AArch64.SoftwareBreakpoint" mylink="aarch64.exceptions.debug.AArch64.SoftwareBreakpoint" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.SoftwareBreakpoint()</line>
<line>// ============================</line>
<line></line>
<line link="AArch64.SoftwareBreakpoint.1" hover="function: AArch64.SoftwareBreakpoint(bits(16) immediate)" conts="AArch64.SoftwareBreakpoint"><anchor link="AArch64.SoftwareBreakpoint.1" hover="function: AArch64.SoftwareBreakpoint(bits(16) immediate)">AArch64.SoftwareBreakpoint</anchor>(bits(16) immediate)</line>
<line></line>
<line>    route_to_el2 = (PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp;</line>
<line>                    <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; (HCR_EL2.TGE == '1' || MDCR_EL2.TDE == '1'));</line>
<line></line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x0;</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_SoftwareBreakpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SoftwareBreakpoint</a>);</line>
<line>    exception.syndrome&lt;15:0&gt; = immediate;</line>
<line></line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(PSTATE.EL, exception, preferred_exception_return, vect_offset);</line>
<line>    elsif route_to_el2 then</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, exception, preferred_exception_return, vect_offset);</line>
<line>    else</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/debug/AArch64.SoftwareStepException" mylink="aarch64.exceptions.debug.AArch64.SoftwareStepException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.SoftwareStepException()</line>
<line>// ===============================</line>
<line></line>
<line link="AArch64.SoftwareStepException.0" hover="function: AArch64.SoftwareStepException()" conts="AArch64.SoftwareStepException"><anchor link="AArch64.SoftwareStepException.0" hover="function: AArch64.SoftwareStepException()">AArch64.SoftwareStepException</anchor>()</line>
<line>    assert PSTATE.EL != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line></line>
<line>    route_to_el2 = (PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>                    (HCR_EL2.TGE == '1' || MDCR_EL2.TDE == '1'));</line>
<line></line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x0;</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_SoftwareStep" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SoftwareStep</a>);</line>
<line>    if <a link="impl-shared.SoftwareStep_DidNotStep.0" file="shared_pseudocode.xml" hover="function: boolean SoftwareStep_DidNotStep()">SoftwareStep_DidNotStep</a>() then</line>
<line>        exception.syndrome&lt;24&gt; = '0';</line>
<line>    else</line>
<line>        exception.syndrome&lt;24&gt; = '1';</line>
<line>        exception.syndrome&lt;6&gt; = if <a link="impl-shared.SoftwareStep_SteppedEX.0" file="shared_pseudocode.xml" hover="function: boolean SoftwareStep_SteppedEX()">SoftwareStep_SteppedEX</a>() then '1' else '0';</line>
<line>    exception.syndrome&lt;5:0&gt; = '100010';                // IFSC = Debug Exception</line>
<line></line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || route_to_el2 then</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, exception, preferred_exception_return, vect_offset);</line>
<line>    else</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/debug/AArch64.VectorCatchException" mylink="aarch64.exceptions.debug.AArch64.VectorCatchException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.VectorCatchException()</line>
<line>// ==============================</line>
<line>// Vector Catch taken from EL0 or EL1 to EL2. This can only be called when debug exceptions are</line>
<line>// being routed to EL2, as Vector Catch is a legacy debug event.</line>
<line></line>
<line link="AArch64.VectorCatchException.1" hover="function: AArch64.VectorCatchException(FaultRecord fault)" conts="AArch64.VectorCatchException"><anchor link="AArch64.VectorCatchException.1" hover="function: AArch64.VectorCatchException(FaultRecord fault)">AArch64.VectorCatchException</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    assert PSTATE.EL != <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>    assert <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; (HCR_EL2.TGE == '1' || MDCR_EL2.TDE == '1');</line>
<line></line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x0;</line>
<line></line>
<line>    vaddress = bits(64) UNKNOWN;</line>
<line>    exception = <a link="AArch64.AbortSyndrome.4" file="shared_pseudocode.xml" hover="function: ExceptionRecord AArch64.AbortSyndrome(Exception exceptype, FaultRecord fault, bits(64) vaddress, bits(2) target_el)">AArch64.AbortSyndrome</a>(<a link="Exception_VectorCatch" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_VectorCatch</a>, fault, vaddress, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line></line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/debug/AArch64.WatchpointException" mylink="aarch64.exceptions.debug.AArch64.WatchpointException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.WatchpointException()</line>
<line>// =============================</line>
<line></line>
<line link="AArch64.WatchpointException.2" hover="function: AArch64.WatchpointException(bits(64) vaddress, FaultRecord fault)" conts="AArch64.WatchpointException"><anchor link="AArch64.WatchpointException.2" hover="function: AArch64.WatchpointException(bits(64) vaddress, FaultRecord fault)">AArch64.WatchpointException</anchor>(bits(64) vaddress, <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    assert PSTATE.EL != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line></line>
<line>    route_to_el2 = (PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>                    (HCR_EL2.TGE == '1' || MDCR_EL2.TDE == '1'));</line>
<line></line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    bits(2) target_el;</line>
<line>    vect_offset = 0x0;</line>
<line>    target_el = if (PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || route_to_el2) then <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> else <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line></line>
<line>    <a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception;</line>
<line>    if <a link="impl-shared.HaveNV2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveNV2Ext()">HaveNV2Ext</a>() &amp;&amp; fault.access.acctype == <a link="AccessType_NV2" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_NV2</a> then</line>
<line>        exception = <a link="AArch64.AbortSyndrome.4" file="shared_pseudocode.xml" hover="function: ExceptionRecord AArch64.AbortSyndrome(Exception exceptype, FaultRecord fault, bits(64) vaddress, bits(2) target_el)">AArch64.AbortSyndrome</a>(<a link="Exception_NV2Watchpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_NV2Watchpoint</a>, fault, vaddress, target_el);</line>
<line>    else</line>
<line>        exception = <a link="AArch64.AbortSyndrome.4" file="shared_pseudocode.xml" hover="function: ExceptionRecord AArch64.AbortSyndrome(Exception exceptype, FaultRecord fault, bits(64) vaddress, bits(2) target_el)">AArch64.AbortSyndrome</a>(<a link="Exception_Watchpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Watchpoint</a>, fault, vaddress, target_el);</line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(target_el, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/exceptions/AArch64.ExceptionClass" mylink="aarch64.exceptions.exceptions.AArch64.ExceptionClass" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ExceptionClass()</line>
<line>// ========================</line>
<line>// Returns the Exception Class and Instruction Length fields to be reported in ESR</line>
<line></line>
<line link="AArch64.ExceptionClass.2" hover="function: (integer,bit) AArch64.ExceptionClass(Exception exceptype, bits(2) target_el)" conts="AArch64.ExceptionClass">(integer,bit) <anchor link="AArch64.ExceptionClass.2" hover="function: (integer,bit) AArch64.ExceptionClass(Exception exceptype, bits(2) target_el)">AArch64.ExceptionClass</anchor>(<a link="Exception" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception</a> exceptype, bits(2) target_el)</line>
<line></line>
<line>    il_is_valid = TRUE;</line>
<line>    from_32 = <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>();</line>
<line>    integer ec;</line>
<line>    case exceptype of</line>
<line>        when <a link="Exception_Uncategorized" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Uncategorized</a>         ec = 0x00; il_is_valid = FALSE;</line>
<line>        when <a link="Exception_WFxTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_WFxTrap</a>               ec = 0x01;</line>
<line>        when <a link="Exception_CP15RTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP15RTTrap</a>            ec = 0x03; assert from_32;</line>
<line>        when <a link="Exception_CP15RRTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP15RRTTrap</a>           ec = 0x04; assert from_32;</line>
<line>        when <a link="Exception_CP14RTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14RTTrap</a>            ec = 0x05; assert from_32;</line>
<line>        when <a link="Exception_CP14DTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14DTTrap</a>            ec = 0x06; assert from_32;</line>
<line>        when <a link="Exception_AdvSIMDFPAccessTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_AdvSIMDFPAccessTrap</a>   ec = 0x07;</line>
<line>        when <a link="Exception_FPIDTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FPIDTrap</a>              ec = 0x08;</line>
<line>        when <a link="Exception_PACTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_PACTrap</a>               ec = 0x09;</line>
<line>        when <a link="Exception_LDST64BTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_LDST64BTrap</a>           ec = 0x0A;</line>
<line>        when <a link="Exception_TSTARTAccessTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_TSTARTAccessTrap</a>      ec = 0x1B;</line>
<line>        when <a link="Exception_GPC" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_GPC</a>                   ec = 0x1E;</line>
<line>        when <a link="Exception_CP14RRTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14RRTTrap</a>           ec = 0x0C; assert from_32;</line>
<line>        when <a link="Exception_BranchTarget" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_BranchTarget</a>          ec = 0x0D;</line>
<line>        when <a link="Exception_IllegalState" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_IllegalState</a>          ec = 0x0E; il_is_valid = FALSE;</line>
<line>        when <a link="Exception_SupervisorCall" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SupervisorCall</a>        ec = 0x11;</line>
<line>        when <a link="Exception_HypervisorCall" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_HypervisorCall</a>        ec = 0x12;</line>
<line>        when <a link="Exception_MonitorCall" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_MonitorCall</a>           ec = 0x13;</line>
<line>        when <a link="Exception_SystemRegisterTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SystemRegisterTrap</a>    ec = 0x18; assert !from_32;</line>
<line>        when <a link="Exception_SystemRegister128Trap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SystemRegister128Trap</a> ec = 0x14; assert !from_32;</line>
<line>        when <a link="Exception_SVEAccessTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SVEAccessTrap</a>         ec = 0x19; assert !from_32;</line>
<line>        when <a link="Exception_ERetTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_ERetTrap</a>              ec = 0x1A; assert !from_32;</line>
<line>        when <a link="Exception_PACFail" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_PACFail</a>               ec = 0x1C; assert !from_32;</line>
<line>        when <a link="Exception_SMEAccessTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SMEAccessTrap</a>         ec = 0x1D; assert !from_32;</line>
<line>        when <a link="Exception_InstructionAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_InstructionAbort</a>      ec = 0x20; il_is_valid = FALSE;</line>
<line>        when <a link="Exception_PCAlignment" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_PCAlignment</a>           ec = 0x22; il_is_valid = FALSE;</line>
<line>        when <a link="Exception_DataAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_DataAbort</a>             ec = 0x24;</line>
<line>        when <a link="Exception_NV2DataAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_NV2DataAbort</a>          ec = 0x25;</line>
<line>        when <a link="Exception_SPAlignment" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SPAlignment</a>           ec = 0x26; il_is_valid = FALSE; assert !from_32;</line>
<line>        when <a link="Exception_MemCpyMemSet" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_MemCpyMemSet</a>          ec = 0x27;</line>
<line>        when <a link="Exception_GCSFail" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_GCSFail</a>               ec = 0x2D; assert !from_32;</line>
<line>        when <a link="Exception_FPTrappedException" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FPTrappedException</a>    ec = 0x28;</line>
<line>        when <a link="Exception_SError" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SError</a>                ec = 0x2F; il_is_valid = FALSE;</line>
<line>        when <a link="Exception_Breakpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Breakpoint</a>            ec = 0x30; il_is_valid = FALSE;</line>
<line>        when <a link="Exception_SoftwareStep" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SoftwareStep</a>          ec = 0x32; il_is_valid = FALSE;</line>
<line>        when <a link="Exception_Watchpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Watchpoint</a>            ec = 0x34; il_is_valid = FALSE;</line>
<line>        when <a link="Exception_NV2Watchpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_NV2Watchpoint</a>         ec = 0x35; il_is_valid = FALSE;</line>
<line>        when <a link="Exception_SoftwareBreakpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SoftwareBreakpoint</a>    ec = 0x38;</line>
<line>        when <a link="Exception_VectorCatch" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_VectorCatch</a>           ec = 0x3A; il_is_valid = FALSE; assert from_32;</line>
<line>        otherwise                            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    if ec IN {0x20,0x24,0x30,0x32,0x34} &amp;&amp; target_el == PSTATE.EL then</line>
<line>        ec = ec + 1;</line>
<line></line>
<line>    if ec IN {0x11,0x12,0x13,0x28,0x38} &amp;&amp; !from_32 then</line>
<line>        ec = ec + 4;</line>
<line>    bit il;</line>
<line>    if il_is_valid then</line>
<line>        il = if <a link="impl-shared.ThisInstrLength.0" file="shared_pseudocode.xml" hover="function: integer ThisInstrLength()">ThisInstrLength</a>() == 32 then '1' else '0';</line>
<line>    else</line>
<line>        il = '1';</line>
<line>    assert from_32 || il == '1';            // AArch64 instructions always 32-bit</line>
<line></line>
<line>    return (ec,il);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/exceptions/AArch64.ReportException" mylink="aarch64.exceptions.exceptions.AArch64.ReportException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ReportException()</line>
<line>// =========================</line>
<line>// Report syndrome information for exception taken to AArch64 state.</line>
<line></line>
<line link="AArch64.ReportException.2" hover="function: AArch64.ReportException(ExceptionRecord exception, bits(2) target_el)" conts="AArch64.ReportException"><anchor link="AArch64.ReportException.2" hover="function: AArch64.ReportException(ExceptionRecord exception, bits(2) target_el)">AArch64.ReportException</anchor>(<a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception, bits(2) target_el)</line>
<line></line>
<line>    <a link="Exception" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception</a> exceptype = exception.exceptype;</line>
<line></line>
<line>    (ec,il) = <a link="AArch64.ExceptionClass.2" file="shared_pseudocode.xml" hover="function: (integer,bit) AArch64.ExceptionClass(Exception exceptype, bits(2) target_el)">AArch64.ExceptionClass</a>(exceptype, target_el);</line>
<line>    iss  = exception.syndrome;</line>
<line>    iss2 = exception.syndrome2;</line>
<line></line>
<line>    // IL is not valid for Data Abort exceptions without valid instruction syndrome information</line>
<line>    if ec IN {0x24,0x25} &amp;&amp; iss&lt;24&gt; == '0' then</line>
<line>        il = '1';</line>
<line></line>
<line>    <a link="impl-aarch64.ESR.write.1" file="shared_pseudocode.xml" hover="accessor: ESR[bits(2) regime] = ESRType value">ESR</a>[target_el] = (<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8)  :   // &lt;63:56&gt;</line>
<line>                      iss2      :   // &lt;55:32&gt;</line>
<line>                      ec&lt;5:0&gt;   :   // &lt;31:26&gt;</line>
<line>                      il        :   // &lt;25&gt;</line>
<line>                      iss);         // &lt;24:0&gt;</line>
<line></line>
<line>    if exceptype IN {</line>
<line>        <a link="Exception_InstructionAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_InstructionAbort</a>,</line>
<line>        <a link="Exception_PCAlignment" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_PCAlignment</a>,</line>
<line>        <a link="Exception_DataAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_DataAbort</a>,</line>
<line>        <a link="Exception_NV2DataAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_NV2DataAbort</a>,</line>
<line>        <a link="Exception_NV2Watchpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_NV2Watchpoint</a>,</line>
<line>        <a link="Exception_GPC" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_GPC</a>,</line>
<line>        <a link="Exception_Watchpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Watchpoint</a></line>
<line>    } then</line>
<line>        <a link="impl-aarch64.FAR.write.1" file="shared_pseudocode.xml" hover="accessor: FAR[bits(2) regime] = bits(64) value">FAR</a>[target_el] = exception.vaddress;</line>
<line>    else</line>
<line>        <a link="impl-aarch64.FAR.write.1" file="shared_pseudocode.xml" hover="accessor: FAR[bits(2) regime] = bits(64) value">FAR</a>[target_el] = bits(64) UNKNOWN;</line>
<line></line>
<line>    if exception.ipavalid then</line>
<line>        HPFAR_EL2&lt;47:4&gt; = exception.ipaddress&lt;55:12&gt;;</line>
<line>        if <a link="impl-shared.IsSecureEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsSecureEL2Enabled()">IsSecureEL2Enabled</a>() &amp;&amp; <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>            HPFAR_EL2.NS = exception.NS;</line>
<line>        else</line>
<line>            HPFAR_EL2.NS = '0';</line>
<line>    elsif target_el == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>        HPFAR_EL2&lt;47:4&gt; = bits(44) UNKNOWN;</line>
<line></line>
<line>    if exception.pavalid then</line>
<line>        MFAR_EL3.FPA = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(exception.paddress.address&lt;<a link="AArch64.PAMax.0" file="shared_pseudocode.xml" hover="function: integer AArch64.PAMax()">AArch64.PAMax</a>()-1:12&gt;, 44);</line>
<line>        case exception.paddress.paspace of</line>
<line>            when <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a>     MFAR_EL3.&lt;NSE,NS&gt; = '00';</line>
<line>            when <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>  MFAR_EL3.&lt;NSE,NS&gt; = '01';</line>
<line>            when <a link="PAS_Root" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Root</a>       MFAR_EL3.&lt;NSE,NS&gt; = '10';</line>
<line>            when <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a>      MFAR_EL3.&lt;NSE,NS&gt; = '11';</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/exceptions/AArch64.ResetControlRegisters" mylink="aarch64.exceptions.exceptions.AArch64.ResetControlRegisters" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ResetControlRegisters()</line>
<line>// ===============================</line>
<line>// Resets System registers and memory-mapped control registers that have architecturally-defined</line>
<line>// reset values to those values.</line>
<line></line>
<line link="AArch64.ResetControlRegisters.1" hover="function: AArch64.ResetControlRegisters(boolean cold_reset)" conts="AArch64.ResetControlRegisters"><anchor link="AArch64.ResetControlRegisters.1" hover="function: AArch64.ResetControlRegisters(boolean cold_reset)">AArch64.ResetControlRegisters</anchor>(boolean cold_reset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/exceptions/AArch64.TakeReset" mylink="aarch64.exceptions.exceptions.AArch64.TakeReset" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TakeReset()</line>
<line>// ===================</line>
<line>// Reset into AArch64 state</line>
<line></line>
<line link="AArch64.TakeReset.1" hover="function: AArch64.TakeReset(boolean cold_reset)" conts="AArch64.TakeReset"><anchor link="AArch64.TakeReset.1" hover="function: AArch64.TakeReset(boolean cold_reset)">AArch64.TakeReset</anchor>(boolean cold_reset)</line>
<line>    assert <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>();</line>
<line></line>
<line>    // Enter the highest implemented Exception level in AArch64 state</line>
<line>    PSTATE.nRW = '0';</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        PSTATE.EL = <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line>    elsif <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>        PSTATE.EL = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>    else</line>
<line>        PSTATE.EL = <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line></line>
<line>    // Reset System registers</line>
<line>    // and other system components</line>
<line>    <a link="AArch64.ResetControlRegisters.1" file="shared_pseudocode.xml" hover="function: AArch64.ResetControlRegisters(boolean cold_reset)">AArch64.ResetControlRegisters</a>(cold_reset);</line>
<line></line>
<line>    // Reset all other PSTATE fields</line>
<line>    PSTATE.SP = '1';                    // Select stack pointer</line>
<line>    PSTATE.&lt;D,A,I,F&gt;  = '1111';         // All asynchronous exceptions masked</line>
<line>    PSTATE.SS = '0';                    // Clear software step bit</line>
<line>    PSTATE.DIT = '0';                   // PSTATE.DIT is reset to 0 when resetting into AArch64</line>
<line>    PSTATE.IL = '0';                    // Clear Illegal Execution state bit</line>
<line></line>
<line>    if <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() then TSTATE.depth = 0;             // Non-transactional state</line>
<line></line>
<line>    // All registers, bits and fields not reset by the above pseudocode or by the BranchTo() call</line>
<line>    // below are UNKNOWN bitstrings after reset. In particular, the return information registers</line>
<line>    // ELR_ELx and SPSR_ELx have UNKNOWN values, so that it</line>
<line>    // is impossible to return from a reset in an architecturally defined way.</line>
<line>    <a link="AArch64.ResetGeneralRegisters.0" file="shared_pseudocode.xml" hover="function: AArch64.ResetGeneralRegisters()">AArch64.ResetGeneralRegisters</a>();</line>
<line>    <a link="AArch64.ResetSIMDFPRegisters.0" file="shared_pseudocode.xml" hover="function: AArch64.ResetSIMDFPRegisters()">AArch64.ResetSIMDFPRegisters</a>();</line>
<line>    <a link="AArch64.ResetSpecialRegisters.0" file="shared_pseudocode.xml" hover="function: AArch64.ResetSpecialRegisters()">AArch64.ResetSpecialRegisters</a>();</line>
<line>    <a link="impl-shared.ResetExternalDebugRegisters.1" file="shared_pseudocode.xml" hover="function: ResetExternalDebugRegisters(boolean cold_reset)">ResetExternalDebugRegisters</a>(cold_reset);</line>
<line></line>
<line>    bits(64) rv;                      // IMPLEMENTATION DEFINED reset vector</line>
<line></line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        rv = RVBAR_EL3;</line>
<line>    elsif <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>        rv = RVBAR_EL2;</line>
<line>    else</line>
<line>        rv = RVBAR_EL1;</line>
<line></line>
<line>    // The reset vector must be correctly aligned</line>
<line>    assert <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(rv&lt;63:<a link="AArch64.PAMax.0" file="shared_pseudocode.xml" hover="function: integer AArch64.PAMax()">AArch64.PAMax</a>()&gt;) &amp;&amp; <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(rv&lt;1:0&gt;);</line>
<line></line>
<line>    boolean branch_conditional = FALSE;</line>
<line>    <a link="impl-shared.BranchTo.3" file="shared_pseudocode.xml" hover="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(rv, <a link="BranchType_RESET" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_RESET</a>, branch_conditional);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/ieeefp/AArch64.FPTrappedException" mylink="aarch64.exceptions.ieeefp.AArch64.FPTrappedException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.FPTrappedException()</line>
<line>// ============================</line>
<line></line>
<line link="AArch64.FPTrappedException.2" hover="function: AArch64.FPTrappedException(boolean is_ase, bits(8) accumulated_exceptions)" conts="AArch64.FPTrappedException"><anchor link="AArch64.FPTrappedException.2" hover="function: AArch64.FPTrappedException(boolean is_ase, bits(8) accumulated_exceptions)">AArch64.FPTrappedException</anchor>(boolean is_ase, bits(8) accumulated_exceptions)</line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_FPTrappedException" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FPTrappedException</a>);</line>
<line>    if is_ase then</line>
<line>        if boolean IMPLEMENTATION_DEFINED "vector instructions set TFV to 1" then</line>
<line>            exception.syndrome&lt;23&gt; = '1';                          // TFV</line>
<line>        else</line>
<line>            exception.syndrome&lt;23&gt; = '0';                          // TFV</line>
<line>    else</line>
<line>        exception.syndrome&lt;23&gt; = '1';                              // TFV</line>
<line>    exception.syndrome&lt;10:8&gt; = bits(3) UNKNOWN;                    // VECITR</line>
<line>    if exception.syndrome&lt;23&gt; == '1' then</line>
<line>        exception.syndrome&lt;7,4:0&gt; = accumulated_exceptions&lt;7,4:0&gt;; // IDF,IXF,UFF,OFF,DZF,IOF</line>
<line>    else</line>
<line>        exception.syndrome&lt;7,4:0&gt; = bits(6) UNKNOWN;</line>
<line></line>
<line>    route_to_el2 = <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1';</line>
<line></line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x0;</line>
<line></line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(PSTATE.EL, exception, preferred_exception_return, vect_offset);</line>
<line>    elsif route_to_el2 then</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, exception, preferred_exception_return, vect_offset);</line>
<line>    else</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/syscalls/AArch64.CallHypervisor" mylink="aarch64.exceptions.syscalls.AArch64.CallHypervisor" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.CallHypervisor()</line>
<line>// ========================</line>
<line>// Performs a HVC call</line>
<line></line>
<line link="AArch64.CallHypervisor.1" hover="function: AArch64.CallHypervisor(bits(16) immediate)" conts="AArch64.CallHypervisor"><anchor link="AArch64.CallHypervisor.1" hover="function: AArch64.CallHypervisor(bits(16) immediate)">AArch64.CallHypervisor</anchor>(bits(16) immediate)</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line></line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then <a link="AArch32.ITAdvance.0" file="shared_pseudocode.xml" hover="function: AArch32.ITAdvance()">AArch32.ITAdvance</a>();</line>
<line>    <a link="impl-shared.SSAdvance.0" file="shared_pseudocode.xml" hover="function: SSAdvance()">SSAdvance</a>();</line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.NextInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) NextInstrAddr(integer N)">NextInstrAddr</a>(64);</line>
<line>    vect_offset = 0x0;</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_HypervisorCall" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_HypervisorCall</a>);</line>
<line>    exception.syndrome&lt;15:0&gt; = immediate;</line>
<line></line>
<line>    if PSTATE.EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, exception, preferred_exception_return, vect_offset);</line>
<line>    else</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/syscalls/AArch64.CallSecureMonitor" mylink="aarch64.exceptions.syscalls.AArch64.CallSecureMonitor" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.CallSecureMonitor()</line>
<line>// ===========================</line>
<line></line>
<line link="AArch64.CallSecureMonitor.1" hover="function: AArch64.CallSecureMonitor(bits(16) immediate)" conts="AArch64.CallSecureMonitor"><anchor link="AArch64.CallSecureMonitor.1" hover="function: AArch64.CallSecureMonitor(bits(16) immediate)">AArch64.CallSecureMonitor</anchor>(bits(16) immediate)</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then <a link="AArch32.ITAdvance.0" file="shared_pseudocode.xml" hover="function: AArch32.ITAdvance()">AArch32.ITAdvance</a>();</line>
<line>    <a link="impl-shared.SSAdvance.0" file="shared_pseudocode.xml" hover="function: SSAdvance()">SSAdvance</a>();</line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.NextInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) NextInstrAddr(integer N)">NextInstrAddr</a>(64);</line>
<line>    vect_offset = 0x0;</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_MonitorCall" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_MonitorCall</a>);</line>
<line>    exception.syndrome&lt;15:0&gt; = immediate;</line>
<line></line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/syscalls/AArch64.CallSupervisor" mylink="aarch64.exceptions.syscalls.AArch64.CallSupervisor" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.CallSupervisor()</line>
<line>// ========================</line>
<line>// Calls the Supervisor</line>
<line></line>
<line link="AArch64.CallSupervisor.1" hover="function: AArch64.CallSupervisor(bits(16) immediate_in)" conts="AArch64.CallSupervisor"><anchor link="AArch64.CallSupervisor.1" hover="function: AArch64.CallSupervisor(bits(16) immediate_in)">AArch64.CallSupervisor</anchor>(bits(16) immediate_in)</line>
<line>    bits(16) immediate = immediate_in;</line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then <a link="AArch32.ITAdvance.0" file="shared_pseudocode.xml" hover="function: AArch32.ITAdvance()">AArch32.ITAdvance</a>();</line>
<line>    <a link="impl-shared.SSAdvance.0" file="shared_pseudocode.xml" hover="function: SSAdvance()">SSAdvance</a>();</line>
<line>    route_to_el2 = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1';</line>
<line></line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.NextInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) NextInstrAddr(integer N)">NextInstrAddr</a>(64);</line>
<line>    vect_offset = 0x0;</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_SupervisorCall" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SupervisorCall</a>);</line>
<line>    exception.syndrome&lt;15:0&gt; = immediate;</line>
<line></line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(PSTATE.EL, exception, preferred_exception_return, vect_offset);</line>
<line>    elsif route_to_el2 then</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, exception, preferred_exception_return, vect_offset);</line>
<line>    else</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/takeexception/AArch64.TakeException" mylink="aarch64.exceptions.takeexception.AArch64.TakeException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TakeException()</line>
<line>// =======================</line>
<line>// Take an exception to an Exception level using AArch64.</line>
<line></line>
<line link="AArch64.TakeException.4" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)" conts="AArch64.TakeException"><anchor link="AArch64.TakeException.4" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</anchor>(bits(2) target_el, <a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception_in,</line>
<line>                      bits(64) preferred_exception_return, integer vect_offset_in)</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(target_el) &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(target_el) &amp;&amp; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(target_el) &gt;= <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL);</line>
<line>    if <a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() then</line>
<line>        <a link="AArch64.TakeExceptionInDebugState.2" file="shared_pseudocode.xml" hover="function: AArch64.TakeExceptionInDebugState(bits(2) target_el, ExceptionRecord exception_in)">AArch64.TakeExceptionInDebugState</a>(target_el, exception_in);</line>
<line>        return;</line>
<line>    <a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception = exception_in;</line>
<line>    boolean sync_errors;</line>
<line>    boolean iesb_req;</line>
<line>    if <a link="impl-shared.HaveIESB.0" file="shared_pseudocode.xml" hover="function: boolean HaveIESB()">HaveIESB</a>() then</line>
<line>        sync_errors = <a link="impl-aarch64.SCTLR.read.1" file="shared_pseudocode.xml" hover="accessor: SCTLRType SCTLR[bits(2) regime]">SCTLR</a>[target_el].IESB == '1';</line>
<line>        if <a link="impl-shared.HaveDoubleFaultExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDoubleFaultExt()">HaveDoubleFaultExt</a>() then</line>
<line>            sync_errors = sync_errors || (SCR_EL3.&lt;EA,NMEA&gt; == '11' &amp;&amp; target_el == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>        if sync_errors &amp;&amp; <a link="impl-shared.InsertIESBBeforeException.1" file="shared_pseudocode.xml" hover="function: boolean InsertIESBBeforeException(bits(2) el)">InsertIESBBeforeException</a>(target_el) then</line>
<line>            <a link="impl-shared.SynchronizeErrors.0" file="shared_pseudocode.xml" hover="function: SynchronizeErrors()">SynchronizeErrors</a>();</line>
<line>            iesb_req = FALSE;</line>
<line>            sync_errors = FALSE;</line>
<line>            <a link="impl-shared.TakeUnmaskedPhysicalSErrorInterrupts.1" file="shared_pseudocode.xml" hover="function: TakeUnmaskedPhysicalSErrorInterrupts(boolean iesb_req)">TakeUnmaskedPhysicalSErrorInterrupts</a>(iesb_req);</line>
<line>    else</line>
<line>        sync_errors = FALSE;</line>
<line></line>
<line>    if <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0 then</line>
<line>        <a link="TMFailure" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure</a> cause;</line>
<line>        case exception.exceptype of</line>
<line>            when <a link="Exception_SoftwareBreakpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SoftwareBreakpoint</a> cause = <a link="TMFailure_DBG" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_DBG</a>;</line>
<line>            when <a link="Exception_Breakpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Breakpoint</a>         cause = <a link="TMFailure_DBG" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_DBG</a>;</line>
<line>            when <a link="Exception_Watchpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Watchpoint</a>         cause = <a link="TMFailure_DBG" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_DBG</a>;</line>
<line>            when <a link="Exception_SoftwareStep" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SoftwareStep</a>       cause = <a link="TMFailure_DBG" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_DBG</a>;</line>
<line>            otherwise                         cause = <a link="TMFailure_ERR" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_ERR</a>;</line>
<line>        <a link="impl-aarch64.FailTransaction.2" file="shared_pseudocode.xml" hover="function: FailTransaction(TMFailure cause, boolean retry)">FailTransaction</a>(cause, FALSE);</line>
<line></line>
<line>    <a link="impl-shared.SynchronizeContext.0" file="shared_pseudocode.xml" hover="function: SynchronizeContext()">SynchronizeContext</a>();</line>
<line></line>
<line>    // If coming from AArch32 state, the top parts of the X[] registers might be set to zero</line>
<line>    from_32 = <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>();</line>
<line>    if from_32 then <a link="AArch64.MaybeZeroRegisterUppers.0" file="shared_pseudocode.xml" hover="function: AArch64.MaybeZeroRegisterUppers()">AArch64.MaybeZeroRegisterUppers</a>();</line>
<line>    if from_32 &amp;&amp; <a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() &amp;&amp; PSTATE.SM == '1' then</line>
<line>        <a link="impl-aarch64.ResetSVEState.0" file="shared_pseudocode.xml" hover="function: ResetSVEState()">ResetSVEState</a>();</line>
<line>    else</line>
<line>        <a link="impl-aarch64.MaybeZeroSVEUppers.1" file="shared_pseudocode.xml" hover="function: MaybeZeroSVEUppers(bits(2) target_el)">MaybeZeroSVEUppers</a>(target_el);</line>
<line></line>
<line>    integer vect_offset = vect_offset_in;</line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(target_el) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL) then</line>
<line>        boolean lower_32;</line>
<line>        if target_el == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then</line>
<line>            if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>                lower_32 = <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>            else</line>
<line>                lower_32 = <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line>        elsif <a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() &amp;&amp; PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; target_el == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>            lower_32 = <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>);</line>
<line>        else</line>
<line>            lower_32 = <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(target_el - 1);</line>
<line>        vect_offset = vect_offset + (if lower_32 then 0x600 else 0x400);</line>
<line></line>
<line>    elsif PSTATE.SP == '1' then</line>
<line>        vect_offset = vect_offset + 0x200;</line>
<line></line>
<line>    bits(64) spsr = <a link="impl-shared.GetPSRFromPSTATE.2" file="shared_pseudocode.xml" hover="function: bits(N) GetPSRFromPSTATE(ExceptionalOccurrenceTargetState targetELState, integer N)">GetPSRFromPSTATE</a>(<a link="AArch64_NonDebugState" file="shared_pseudocode.xml" hover="enumeration ExceptionalOccurrenceTargetState { AArch32_NonDebugState, AArch64_NonDebugState, DebugState }">AArch64_NonDebugState</a>, 64);</line>
<line></line>
<line>    if PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; target_el == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        if <a link="impl-shared.HaveNV2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveNV2Ext()">HaveNV2Ext</a>() &amp;&amp; (HCR_EL2.&lt;NV,NV1,NV2&gt; == '100' || HCR_EL2.&lt;NV,NV1,NV2&gt; == '111') then</line>
<line>            spsr&lt;3:2&gt; = '10';</line>
<line>        else</line>
<line>            if <a link="impl-shared.HaveNVExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveNVExt()">HaveNVExt</a>() &amp;&amp; HCR_EL2.&lt;NV,NV1&gt; == '10' then</line>
<line>                spsr&lt;3:2&gt; = '10';</line>
<line></line>
<line>    if <a link="impl-shared.HaveBTIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveBTIExt()">HaveBTIExt</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        boolean zero_btype;</line>
<line>        // SPSR[].BTYPE is only guaranteed valid for these exception types</line>
<line>        if exception.exceptype IN {<a link="Exception_SError" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SError</a>, <a link="Exception_IRQ" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_IRQ</a>, <a link="Exception_FIQ" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FIQ</a>,</line>
<line>                              <a link="Exception_SoftwareStep" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SoftwareStep</a>, <a link="Exception_PCAlignment" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_PCAlignment</a>,</line>
<line>                              <a link="Exception_InstructionAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_InstructionAbort</a>, <a link="Exception_Breakpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Breakpoint</a>,</line>
<line>                              <a link="Exception_VectorCatch" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_VectorCatch</a>, <a link="Exception_SoftwareBreakpoint" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SoftwareBreakpoint</a>,</line>
<line>                              <a link="Exception_IllegalState" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_IllegalState</a>, <a link="Exception_BranchTarget" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_BranchTarget</a>} then</line>
<line>            zero_btype = FALSE;</line>
<line>        else</line>
<line>            zero_btype = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_ZEROBTYPE" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_ZEROBTYPE</a>);</line>
<line>        if zero_btype then spsr&lt;11:10&gt; = '00';</line>
<line></line>
<line>    if <a link="impl-shared.HaveNV2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveNV2Ext()">HaveNV2Ext</a>() &amp;&amp; exception.exceptype == <a link="Exception_NV2DataAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_NV2DataAbort</a> &amp;&amp; target_el == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then</line>
<line>        // External aborts are configured to be taken to EL3</line>
<line>        exception.exceptype = <a link="Exception_DataAbort" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_DataAbort</a>;</line>
<line>    if !(exception.exceptype IN {<a link="Exception_IRQ" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_IRQ</a>, <a link="Exception_FIQ" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FIQ</a>}) then</line>
<line>        <a link="AArch64.ReportException.2" file="shared_pseudocode.xml" hover="function: AArch64.ReportException(ExceptionRecord exception, bits(2) target_el)">AArch64.ReportException</a>(exception, target_el);</line>
<line></line>
<line>    if <a link="impl-shared.HaveBRBExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveBRBExt()">HaveBRBExt</a>() then</line>
<line>        <a link="impl-aarch64.BRBEException.5" file="shared_pseudocode.xml" hover="function: BRBEException(ExceptionRecord erec, bits(64) preferred_exception_return, bits(64) target_address_in, bits(2) target_el, boolean trappedsyscallinst)">BRBEException</a>(exception, preferred_exception_return,</line>
<line>                      <a link="impl-aarch64.VBAR.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) VBAR[bits(2) regime]">VBAR</a>[target_el]&lt;63:11&gt;:vect_offset&lt;10:0&gt;, target_el,</line>
<line>                      exception.trappedsyscallinst);</line>
<line></line>
<line>    if PSTATE.EL == target_el then</line>
<line>        if <a link="impl-aarch64.GetCurrentEXLOCKEN.0" file="shared_pseudocode.xml" hover="function: boolean GetCurrentEXLOCKEN()">GetCurrentEXLOCKEN</a>() then</line>
<line>            PSTATE.EXLOCK = '1';</line>
<line>        else</line>
<line>            PSTATE.EXLOCK = '0';</line>
<line>    else</line>
<line>        PSTATE.EXLOCK = '0';</line>
<line></line>
<line>    PSTATE.EL = target_el;</line>
<line>    PSTATE.nRW = '0';</line>
<line>    PSTATE.SP = '1';</line>
<line></line>
<line>    <a link="impl-shared.SPSR.write.0" file="shared_pseudocode.xml" hover="accessor: SPSR[] = bits(N) value">SPSR</a>[] = spsr;</line>
<line>    <a link="impl-aarch64.ELR.write.0" file="shared_pseudocode.xml" hover="accessor: ELR[] = bits(64) value">ELR</a>[] = preferred_exception_return;</line>
<line></line>
<line>    PSTATE.SS = '0';</line>
<line>    if <a link="impl-shared.HaveFeatNMI.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatNMI()">HaveFeatNMI</a>() &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(target_el) then PSTATE.ALLINT = NOT <a link="impl-aarch64.SCTLR.read.0" file="shared_pseudocode.xml" hover="accessor: SCTLRType SCTLR[]">SCTLR</a>[].SPINTMASK;</line>
<line>    PSTATE.&lt;D,A,I,F&gt; = '1111';</line>
<line>    PSTATE.IL = '0';</line>
<line>    if from_32 then                             // Coming from AArch32</line>
<line>        PSTATE.IT = '00000000';</line>
<line>        PSTATE.T = '0';                         // PSTATE.J is RES0</line>
<line>    if (<a link="impl-shared.HavePANExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePANExt()">HavePANExt</a>() &amp;&amp; (PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> || (PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> &amp;&amp; <a link="impl-shared.ELIsInHost.1" file="shared_pseudocode.xml" hover="function: boolean ELIsInHost(bits(2) el)">ELIsInHost</a>(<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>))) &amp;&amp;</line>
<line>        <a link="impl-aarch64.SCTLR.read.0" file="shared_pseudocode.xml" hover="accessor: SCTLRType SCTLR[]">SCTLR</a>[].SPAN == '0') then</line>
<line>        PSTATE.PAN = '1';</line>
<line>    if <a link="impl-shared.HaveUAOExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveUAOExt()">HaveUAOExt</a>() then PSTATE.UAO = '0';</line>
<line>    if <a link="impl-shared.HaveBTIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveBTIExt()">HaveBTIExt</a>() then PSTATE.BTYPE = '00';</line>
<line>    if <a link="impl-shared.HaveSSBSExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveSSBSExt()">HaveSSBSExt</a>() then PSTATE.SSBS = <a link="impl-aarch64.SCTLR.read.0" file="shared_pseudocode.xml" hover="accessor: SCTLRType SCTLR[]">SCTLR</a>[].DSSBS;</line>
<line>    if <a link="impl-shared.HaveMTEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEExt()">HaveMTEExt</a>() then PSTATE.TCO = '1';</line>
<line></line>
<line>    boolean branch_conditional = FALSE;</line>
<line>    <a link="impl-shared.BranchTo.3" file="shared_pseudocode.xml" hover="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(<a link="impl-aarch64.VBAR.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) VBAR[]">VBAR</a>[]&lt;63:11&gt;:vect_offset&lt;10:0&gt;, <a link="BranchType_EXCEPTION" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_EXCEPTION</a>, branch_conditional);</line>
<line></line>
<line>    <a link="impl-shared.CheckExceptionCatch.1" file="shared_pseudocode.xml" hover="function: CheckExceptionCatch(boolean exception_entry)">CheckExceptionCatch</a>(TRUE);                  // Check for debug event on exception entry</line>
<line></line>
<line>    if sync_errors then</line>
<line>        <a link="impl-shared.SynchronizeErrors.0" file="shared_pseudocode.xml" hover="function: SynchronizeErrors()">SynchronizeErrors</a>();</line>
<line>        iesb_req = TRUE;</line>
<line>        <a link="impl-shared.TakeUnmaskedPhysicalSErrorInterrupts.1" file="shared_pseudocode.xml" hover="function: TakeUnmaskedPhysicalSErrorInterrupts(boolean iesb_req)">TakeUnmaskedPhysicalSErrorInterrupts</a>(iesb_req);</line>
<line></line>
<line>    <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/AArch64.AArch32SystemAccessTrap" mylink="aarch64.exceptions.traps.AArch64.AArch32SystemAccessTrap" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.AArch32SystemAccessTrap()</line>
<line>// =================================</line>
<line>// Trapped AARCH32 System register access.</line>
<line></line>
<line link="AArch64.AArch32SystemAccessTrap.2" hover="function: AArch64.AArch32SystemAccessTrap(bits(2) target_el, integer ec)" conts="AArch64.AArch32SystemAccessTrap"><anchor link="AArch64.AArch32SystemAccessTrap.2" hover="function: AArch64.AArch32SystemAccessTrap(bits(2) target_el, integer ec)">AArch64.AArch32SystemAccessTrap</anchor>(bits(2) target_el, integer ec)</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(target_el) &amp;&amp; target_el != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(target_el) &gt;= <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL);</line>
<line></line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x0;</line>
<line></line>
<line>    exception = <a link="AArch64.AArch32SystemAccessTrapSyndrome.2" file="shared_pseudocode.xml" hover="function: ExceptionRecord AArch64.AArch32SystemAccessTrapSyndrome(bits(32) instr, integer ec)">AArch64.AArch32SystemAccessTrapSyndrome</a>(<a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>(), ec);</line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(target_el, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/AArch64.AArch32SystemAccessTrapSyndrome" mylink="aarch64.exceptions.traps.AArch64.AArch32SystemAccessTrapSyndrome" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.AArch32SystemAccessTrapSyndrome()</line>
<line>// =========================================</line>
<line>// Returns the syndrome information for traps on AArch32 MCR, MCRR, MRC, MRRC, and VMRS,</line>
<line>// VMSR instructions, other than traps that are due to HCPTR or CPACR.</line>
<line></line>
<line link="AArch64.AArch32SystemAccessTrapSyndrome.2" hover="function: ExceptionRecord AArch64.AArch32SystemAccessTrapSyndrome(bits(32) instr, integer ec)" conts="AArch64.AArch32SystemAccessTrapSyndrome">ExceptionRecord <anchor link="AArch64.AArch32SystemAccessTrapSyndrome.2" hover="function: ExceptionRecord AArch64.AArch32SystemAccessTrapSyndrome(bits(32) instr, integer ec)">AArch64.AArch32SystemAccessTrapSyndrome</anchor>(bits(32) instr, integer ec)</line>
<line>    <a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception;</line>
<line></line>
<line>    case ec of</line>
<line>        when 0x0    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_Uncategorized" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Uncategorized</a>);</line>
<line>        when 0x3    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_CP15RTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP15RTTrap</a>);</line>
<line>        when 0x4    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_CP15RRTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP15RRTTrap</a>);</line>
<line>        when 0x5    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_CP14RTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14RTTrap</a>);</line>
<line>        when 0x6    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_CP14DTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14DTTrap</a>);</line>
<line>        when 0x7    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_AdvSIMDFPAccessTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_AdvSIMDFPAccessTrap</a>);</line>
<line>        when 0x8    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_FPIDTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FPIDTrap</a>);</line>
<line>        when 0xC    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_CP14RRTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14RRTTrap</a>);</line>
<line>        otherwise   <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    bits(20) iss = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(20);</line>
<line></line>
<line>    if exception.exceptype == <a link="Exception_Uncategorized" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Uncategorized</a> then</line>
<line>        return exception;</line>
<line>    elsif exception.exceptype IN {<a link="Exception_FPIDTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FPIDTrap</a>, <a link="Exception_CP14RTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14RTTrap</a>,</line>
<line>                                  <a link="Exception_CP15RTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP15RTTrap</a>} then</line>
<line>        // Trapped MRC/MCR, VMRS on FPSID</line>
<line>        if exception.exceptype != <a link="Exception_FPIDTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FPIDTrap</a> then    // When trap is not for VMRS</line>
<line>            iss&lt;19:17&gt; = instr&lt;7:5&gt;;           // opc2</line>
<line>            iss&lt;16:14&gt; = instr&lt;23:21&gt;;         // opc1</line>
<line>            iss&lt;13:10&gt; = instr&lt;19:16&gt;;         // CRn</line>
<line>            iss&lt;4:1&gt;   = instr&lt;3:0&gt;;           // CRm</line>
<line>        else</line>
<line>            iss&lt;19:17&gt; = '000';</line>
<line>            iss&lt;16:14&gt; = '111';</line>
<line>            iss&lt;13:10&gt; = instr&lt;19:16&gt;;         // reg</line>
<line>            iss&lt;4:1&gt;   = '0000';</line>
<line></line>
<line>        if instr&lt;20&gt; == '1' &amp;&amp; instr&lt;15:12&gt; == '1111' then    // MRC, Rt==15</line>
<line>            iss&lt;9:5&gt; = '11111';</line>
<line>        elsif instr&lt;20&gt; == '0' &amp;&amp; instr&lt;15:12&gt; == '1111' then // MCR, Rt==15</line>
<line>            iss&lt;9:5&gt; = bits(5) UNKNOWN;</line>
<line>        else</line>
<line>            iss&lt;9:5&gt; = LookUpRIndex(UInt(instr&lt;15:12&gt;), PSTATE.M)&lt;4:0&gt;;</line>
<line>    elsif exception.exceptype IN {<a link="Exception_CP14RRTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14RRTTrap</a>, <a link="Exception_AdvSIMDFPAccessTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_AdvSIMDFPAccessTrap</a>,</line>
<line>                                  <a link="Exception_CP15RRTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP15RRTTrap</a>} then</line>
<line>        // Trapped MRRC/MCRR, VMRS/VMSR</line>
<line>        iss&lt;19:16&gt; = instr&lt;7:4&gt;;          // opc1</line>
<line>        if instr&lt;19:16&gt; == '1111' then    // Rt2==15</line>
<line>            iss&lt;14:10&gt; = bits(5) UNKNOWN;</line>
<line>        else</line>
<line>            iss&lt;14:10&gt; = LookUpRIndex(UInt(instr&lt;19:16&gt;), PSTATE.M)&lt;4:0&gt;;</line>
<line></line>
<line>        if instr&lt;15:12&gt; == '1111' then    // Rt==15</line>
<line>            iss&lt;9:5&gt; = bits(5) UNKNOWN;</line>
<line>        else</line>
<line>            iss&lt;9:5&gt; = LookUpRIndex(UInt(instr&lt;15:12&gt;), PSTATE.M)&lt;4:0&gt;;</line>
<line>        iss&lt;4:1&gt;   = instr&lt;3:0&gt;;         // CRm</line>
<line>    elsif exception.exceptype == <a link="Exception_CP14DTTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14DTTrap</a> then</line>
<line>        // Trapped LDC/STC</line>
<line>        iss&lt;19:12&gt; = instr&lt;7:0&gt;;         // imm8</line>
<line>        iss&lt;4&gt;     = instr&lt;23&gt;;          // U</line>
<line>        iss&lt;2:1&gt;   = instr&lt;24,21&gt;;       // P,W</line>
<line>        if instr&lt;19:16&gt; == '1111' then   // Rn==15, LDC(Literal addressing)/STC</line>
<line>            iss&lt;9:5&gt; = bits(5) UNKNOWN;</line>
<line>            iss&lt;3&gt;   = '1';</line>
<line>    iss&lt;0&gt; = instr&lt;20&gt;;                  // Direction</line>
<line></line>
<line>    exception.syndrome&lt;24:20&gt; = <a link="impl-shared.ConditionSyndrome.0" file="shared_pseudocode.xml" hover="function: bits(5) ConditionSyndrome()">ConditionSyndrome</a>();</line>
<line>    exception.syndrome&lt;19:0&gt;  = iss;</line>
<line></line>
<line>    return exception;</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/AArch64.AdvSIMDFPAccessTrap" mylink="aarch64.exceptions.traps.AArch64.AdvSIMDFPAccessTrap" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.AdvSIMDFPAccessTrap()</line>
<line>// =============================</line>
<line>// Trapped access to Advanced SIMD or FP registers due to CPACR[].</line>
<line></line>
<line link="AArch64.AdvSIMDFPAccessTrap.1" hover="function: AArch64.AdvSIMDFPAccessTrap(bits(2) target_el)" conts="AArch64.AdvSIMDFPAccessTrap"><anchor link="AArch64.AdvSIMDFPAccessTrap.1" hover="function: AArch64.AdvSIMDFPAccessTrap(bits(2) target_el)">AArch64.AdvSIMDFPAccessTrap</anchor>(bits(2) target_el)</line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    <a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception;</line>
<line>    vect_offset = 0x0;</line>
<line></line>
<line>    route_to_el2 = (target_el == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1');</line>
<line></line>
<line>    if route_to_el2 then</line>
<line>        exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_Uncategorized" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Uncategorized</a>);</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, exception, preferred_exception_return, vect_offset);</line>
<line>    else</line>
<line>        exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_AdvSIMDFPAccessTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_AdvSIMDFPAccessTrap</a>);</line>
<line>        exception.syndrome&lt;24:20&gt; = <a link="impl-shared.ConditionSyndrome.0" file="shared_pseudocode.xml" hover="function: bits(5) ConditionSyndrome()">ConditionSyndrome</a>();</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(target_el, exception, preferred_exception_return, vect_offset);</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/AArch64.CheckCP15InstrCoarseTraps" mylink="aarch64.exceptions.traps.AArch64.CheckCP15InstrCoarseTraps" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.CheckCP15InstrCoarseTraps()</line>
<line>// ===================================</line>
<line>// Check for coarse-grained AArch32  traps to System registers in the</line>
<line>// coproc=0b1111 encoding space by HSTR_EL2, HCR_EL2, and SCTLR_ELx.</line>
<line></line>
<line link="AArch64.CheckCP15InstrCoarseTraps.3" hover="function: AArch64.CheckCP15InstrCoarseTraps(integer CRn, integer nreg, integer CRm)" conts="AArch64.CheckCP15InstrCoarseTraps"><anchor link="AArch64.CheckCP15InstrCoarseTraps.3" hover="function: AArch64.CheckCP15InstrCoarseTraps(integer CRn, integer nreg, integer CRm)">AArch64.CheckCP15InstrCoarseTraps</anchor>(integer CRn, integer nreg, integer CRm)</line>
<line>    trapped_encoding = ((CRn == 9  &amp;&amp; CRm IN {0,1,2,    5,6,7,8   }) ||</line>
<line>                        (CRn == 10 &amp;&amp; CRm IN {0,1,    4,      8   }) ||</line>
<line>                        (CRn == 11 &amp;&amp; CRm IN {0,1,2,3,4,5,6,7,8,15}));</line>
<line></line>
<line>    // Check for MRC and MCR disabled by SCTLR_EL1.TIDCP.</line>
<line>    if (<a link="impl-shared.HaveFeatTIDCP1.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatTIDCP1()">HaveFeatTIDCP1</a>() &amp;&amp; PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() &amp;&amp;</line>
<line>           !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) &amp;&amp; SCTLR_EL1.TIDCP == '1' &amp;&amp; trapped_encoding) then</line>
<line>        if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1' then</line>
<line>            <a link="AArch64.AArch32SystemAccessTrap.2" file="shared_pseudocode.xml" hover="function: AArch64.AArch32SystemAccessTrap(bits(2) target_el, integer ec)">AArch64.AArch32SystemAccessTrap</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, 0x3);</line>
<line>        else</line>
<line>            <a link="AArch64.AArch32SystemAccessTrap.2" file="shared_pseudocode.xml" hover="function: AArch64.AArch32SystemAccessTrap(bits(2) target_el, integer ec)">AArch64.AArch32SystemAccessTrap</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, 0x3);</line>
<line></line>
<line>    // Check for coarse-grained Hyp traps</line>
<line>    if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        // Check for MRC and MCR disabled by SCTLR_EL2.TIDCP.</line>
<line>        if (<a link="impl-shared.HaveFeatTIDCP1.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatTIDCP1()">HaveFeatTIDCP1</a>() &amp;&amp; PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() &amp;&amp;</line>
<line>                SCTLR_EL2.TIDCP == '1' &amp;&amp; trapped_encoding) then</line>
<line>            <a link="AArch64.AArch32SystemAccessTrap.2" file="shared_pseudocode.xml" hover="function: AArch64.AArch32SystemAccessTrap(bits(2) target_el, integer ec)">AArch64.AArch32SystemAccessTrap</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, 0x3);</line>
<line></line>
<line>        major = if nreg == 1 then CRn else CRm;</line>
<line>        // Check for MCR, MRC, MCRR, and MRRC disabled by HSTR_EL2&lt;CRn/CRm&gt;</line>
<line>        // and MRC and MCR disabled by HCR_EL2.TIDCP.</line>
<line>        if ((!<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() &amp;&amp; !(major IN {4,14}) &amp;&amp; HSTR_EL2&lt;major&gt; == '1') ||</line>
<line>                (HCR_EL2.TIDCP == '1' &amp;&amp; nreg == 1 &amp;&amp; trapped_encoding)) then</line>
<line>            if (PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp;</line>
<line>                    boolean IMPLEMENTATION_DEFINED "UNDEF unallocated CP15 access at <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>") then</line>
<line>                UNDEFINED;</line>
<line>            <a link="AArch64.AArch32SystemAccessTrap.2" file="shared_pseudocode.xml" hover="function: AArch64.AArch32SystemAccessTrap(bits(2) target_el, integer ec)">AArch64.AArch32SystemAccessTrap</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, 0x3);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/AArch64.CheckFPAdvSIMDEnabled" mylink="aarch64.exceptions.traps.AArch64.CheckFPAdvSIMDEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.CheckFPAdvSIMDEnabled()</line>
<line>// ===============================</line>
<line></line>
<line link="AArch64.CheckFPAdvSIMDEnabled.0" hover="function: AArch64.CheckFPAdvSIMDEnabled()" conts="AArch64.CheckFPAdvSIMDEnabled"><anchor link="AArch64.CheckFPAdvSIMDEnabled.0" hover="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</anchor>()</line>
<line>    <a link="AArch64.CheckFPEnabled.0" file="shared_pseudocode.xml" hover="function: AArch64.CheckFPEnabled()">AArch64.CheckFPEnabled</a>();</line>
<line>    // Check for illegal use of Advanced</line>
<line>    // SIMD in Streaming SVE Mode</line>
<line>    if <a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() &amp;&amp; PSTATE.SM == '1' &amp;&amp; !<a link="impl-aarch64.IsFullA64Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsFullA64Enabled()">IsFullA64Enabled</a>() then</line>
<line>        <a link="impl-aarch64.SMEAccessTrap.2" file="shared_pseudocode.xml" hover="function: SMEAccessTrap(SMEExceptionType etype, bits(2) target_el_in)">SMEAccessTrap</a>(<a link="SMEExceptionType_Streaming" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_Streaming</a>, PSTATE.EL);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/AArch64.CheckFPAdvSIMDTrap" mylink="aarch64.exceptions.traps.AArch64.CheckFPAdvSIMDTrap" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.CheckFPAdvSIMDTrap()</line>
<line>// ============================</line>
<line>// Check against CPTR_EL2 and CPTR_EL3.</line>
<line></line>
<line link="AArch64.CheckFPAdvSIMDTrap.0" hover="function: AArch64.CheckFPAdvSIMDTrap()" conts="AArch64.CheckFPAdvSIMDTrap"><anchor link="AArch64.CheckFPAdvSIMDTrap.0" hover="function: AArch64.CheckFPAdvSIMDTrap()">AArch64.CheckFPAdvSIMDTrap</anchor>()</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; CPTR_EL3.TFP == '1' &amp;&amp; <a link="impl-shared.EL3SDDUndefPriority.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndefPriority()">EL3SDDUndefPriority</a>() then</line>
<line>        UNDEFINED;</line>
<line></line>
<line>    if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        // Check if access disabled in CPTR_EL2</line>
<line>        if <a link="impl-shared.HaveVirtHostExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</a>() &amp;&amp; HCR_EL2.E2H == '1' then</line>
<line>            boolean disabled;</line>
<line>            case CPTR_EL2.FPEN of</line>
<line>                when 'x0' disabled = TRUE;</line>
<line>                when '01' disabled = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; HCR_EL2.TGE == '1';</line>
<line>                when '11' disabled = FALSE;</line>
<line>            if disabled then <a link="AArch64.AdvSIMDFPAccessTrap.1" file="shared_pseudocode.xml" hover="function: AArch64.AdvSIMDFPAccessTrap(bits(2) target_el)">AArch64.AdvSIMDFPAccessTrap</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>        else</line>
<line>            if CPTR_EL2.TFP == '1' then <a link="AArch64.AdvSIMDFPAccessTrap.1" file="shared_pseudocode.xml" hover="function: AArch64.AdvSIMDFPAccessTrap(bits(2) target_el)">AArch64.AdvSIMDFPAccessTrap</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line></line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        // Check if access disabled in CPTR_EL3</line>
<line>        if CPTR_EL3.TFP == '1' then</line>
<line>            if <a link="impl-shared.EL3SDDUndef.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndef()">EL3SDDUndef</a>() then</line>
<line>                UNDEFINED;</line>
<line>            else</line>
<line>                <a link="AArch64.AdvSIMDFPAccessTrap.1" file="shared_pseudocode.xml" hover="function: AArch64.AdvSIMDFPAccessTrap(bits(2) target_el)">AArch64.AdvSIMDFPAccessTrap</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/AArch64.CheckFPEnabled" mylink="aarch64.exceptions.traps.AArch64.CheckFPEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.CheckFPEnabled()</line>
<line>// ========================</line>
<line>// Check against CPACR[]</line>
<line></line>
<line link="AArch64.CheckFPEnabled.0" hover="function: AArch64.CheckFPEnabled()" conts="AArch64.CheckFPEnabled"><anchor link="AArch64.CheckFPEnabled.0" hover="function: AArch64.CheckFPEnabled()">AArch64.CheckFPEnabled</anchor>()</line>
<line>    if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>        // Check if access disabled in CPACR_EL1</line>
<line>        boolean disabled;</line>
<line>        case CPACR_EL1.FPEN of</line>
<line>            when 'x0' disabled = TRUE;</line>
<line>            when '01' disabled = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;</line>
<line>            when '11' disabled = FALSE;</line>
<line>        if disabled then <a link="AArch64.AdvSIMDFPAccessTrap.1" file="shared_pseudocode.xml" hover="function: AArch64.AdvSIMDFPAccessTrap(bits(2) target_el)">AArch64.AdvSIMDFPAccessTrap</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line></line>
<line>    <a link="AArch64.CheckFPAdvSIMDTrap.0" file="shared_pseudocode.xml" hover="function: AArch64.CheckFPAdvSIMDTrap()">AArch64.CheckFPAdvSIMDTrap</a>();               // Also check against CPTR_EL2 and CPTR_EL3</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/AArch64.CheckForERetTrap" mylink="aarch64.exceptions.traps.AArch64.CheckForERetTrap" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.CheckForERetTrap()</line>
<line>// ==========================</line>
<line>// Check for trap on ERET, ERETAA, ERETAB instruction</line>
<line></line>
<line link="AArch64.CheckForERetTrap.2" hover="function: AArch64.CheckForERetTrap(boolean eret_with_pac, boolean pac_uses_key_a)" conts="AArch64.CheckForERetTrap"><anchor link="AArch64.CheckForERetTrap.2" hover="function: AArch64.CheckForERetTrap(boolean eret_with_pac, boolean pac_uses_key_a)">AArch64.CheckForERetTrap</anchor>(boolean eret_with_pac, boolean pac_uses_key_a)</line>
<line></line>
<line>    route_to_el2 = FALSE;</line>
<line>    // Non-secure EL1 execution of ERET, ERETAA, ERETAB when either HCR_EL2.NV or</line>
<line>    // HFGITR_EL2.ERET is set, is trapped to EL2</line>
<line>    route_to_el2 = (PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>                    ((<a link="impl-shared.HaveNVExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveNVExt()">HaveNVExt</a>() &amp;&amp; HCR_EL2.NV == '1') ||</line>
<line>                     (<a link="impl-shared.HaveFGTExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveFGTExt()">HaveFGTExt</a>() &amp;&amp; (!<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) || SCR_EL3.FGTEn == '1') &amp;&amp;</line>
<line>                      HFGITR_EL2.ERET == '1')));</line>
<line>    if route_to_el2 then</line>
<line>        <a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception;</line>
<line>        bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>        vect_offset = 0x0;</line>
<line>        exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_ERetTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_ERetTrap</a>);</line>
<line>        if !eret_with_pac then                             // ERET</line>
<line>            exception.syndrome&lt;1&gt; = '0';</line>
<line>            exception.syndrome&lt;0&gt; = '0';                   // RES0</line>
<line>        else</line>
<line>            exception.syndrome&lt;1&gt; = '1';</line>
<line>            if pac_uses_key_a then                         // ERETAA</line>
<line>                exception.syndrome&lt;0&gt; = '0';</line>
<line>            else    // ERETAB</line>
<line>                exception.syndrome&lt;0&gt; = '1';</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/AArch64.CheckForSMCUndefOrTrap" mylink="aarch64.exceptions.traps.AArch64.CheckForSMCUndefOrTrap" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.CheckForSMCUndefOrTrap()</line>
<line>// ================================</line>
<line>// Check for UNDEFINED or trap on SMC instruction</line>
<line></line>
<line link="AArch64.CheckForSMCUndefOrTrap.1" hover="function: AArch64.CheckForSMCUndefOrTrap(bits(16) imm)" conts="AArch64.CheckForSMCUndefOrTrap"><anchor link="AArch64.CheckForSMCUndefOrTrap.1" hover="function: AArch64.CheckForSMCUndefOrTrap(bits(16) imm)">AArch64.CheckForSMCUndefOrTrap</anchor>(bits(16) imm)</line>
<line>    if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then UNDEFINED;</line>
<line>    if (!(PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TSC == '1') &amp;&amp;</line>
<line>        <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.SMD == '1') then</line>
<line>        UNDEFINED;</line>
<line>    route_to_el2 = FALSE;</line>
<line>    if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        if PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>            if <a link="impl-shared.HaveNVExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveNVExt()">HaveNVExt</a>() &amp;&amp; HCR_EL2.NV == '1' &amp;&amp; HCR_EL2.TSC == '1' then</line>
<line>                route_to_el2 = TRUE;</line>
<line>            else</line>
<line>                UNDEFINED;</line>
<line>        else</line>
<line>            UNDEFINED;</line>
<line>    else</line>
<line>        route_to_el2 = PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TSC == '1';</line>
<line>    if route_to_el2 then</line>
<line>        bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>        vect_offset = 0x0;</line>
<line>        exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_MonitorCall" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_MonitorCall</a>);</line>
<line>        exception.syndrome&lt;15:0&gt; = imm;</line>
<line>        exception.trappedsyscallinst = TRUE;</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/AArch64.CheckForSVCTrap" mylink="aarch64.exceptions.traps.AArch64.CheckForSVCTrap" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.CheckForSVCTrap()</line>
<line>// =========================</line>
<line>// Check for trap on SVC instruction</line>
<line></line>
<line link="AArch64.CheckForSVCTrap.1" hover="function: AArch64.CheckForSVCTrap(bits(16) immediate)" conts="AArch64.CheckForSVCTrap"><anchor link="AArch64.CheckForSVCTrap.1" hover="function: AArch64.CheckForSVCTrap(bits(16) immediate)">AArch64.CheckForSVCTrap</anchor>(bits(16) immediate)</line>
<line>    if <a link="impl-shared.HaveFGTExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveFGTExt()">HaveFGTExt</a>() then</line>
<line>        route_to_el2 = FALSE;</line>
<line>        if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>            route_to_el2 = (!<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) &amp;&amp;</line>
<line>                           <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HFGITR_EL2.SVC_EL0 == '1' &amp;&amp;</line>
<line>                           (HCR_EL2.&lt;E2H, TGE&gt; != '11' &amp;&amp; (!<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) || SCR_EL3.FGTEn == '1')));</line>
<line></line>
<line>        elsif PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> then</line>
<line>            route_to_el2 = (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HFGITR_EL2.SVC_EL1 == '1' &amp;&amp;</line>
<line>                           (!<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) || SCR_EL3.FGTEn == '1'));</line>
<line></line>
<line>        if route_to_el2 then</line>
<line>            exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_SupervisorCall" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SupervisorCall</a>);</line>
<line>            exception.syndrome&lt;15:0&gt; = immediate;</line>
<line>            exception.trappedsyscallinst = TRUE;</line>
<line>            bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>            vect_offset = 0x0;</line>
<line></line>
<line>            <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/AArch64.CheckForWFxTrap" mylink="aarch64.exceptions.traps.AArch64.CheckForWFxTrap" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.CheckForWFxTrap()</line>
<line>// =========================</line>
<line>// Check for trap on WFE or WFI instruction</line>
<line></line>
<line link="AArch64.CheckForWFxTrap.2" hover="function: AArch64.CheckForWFxTrap(bits(2) target_el, WFxType wfxtype)" conts="AArch64.CheckForWFxTrap"><anchor link="AArch64.CheckForWFxTrap.2" hover="function: AArch64.CheckForWFxTrap(bits(2) target_el, WFxType wfxtype)">AArch64.CheckForWFxTrap</anchor>(bits(2) target_el, <a link="WFxType" file="shared_pseudocode.xml" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType</a> wfxtype)</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(target_el);</line>
<line></line>
<line>    boolean is_wfe = wfxtype IN {<a link="WFxType_WFE" file="shared_pseudocode.xml" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFE</a>, <a link="WFxType_WFET" file="shared_pseudocode.xml" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFET</a>};</line>
<line>    boolean trap;</line>
<line>    case target_el of</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            trap = (if is_wfe then <a link="impl-aarch64.SCTLR.read.0" file="shared_pseudocode.xml" hover="accessor: SCTLRType SCTLR[]">SCTLR</a>[].nTWE else <a link="impl-aarch64.SCTLR.read.0" file="shared_pseudocode.xml" hover="accessor: SCTLRType SCTLR[]">SCTLR</a>[].nTWI) == '0';</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            trap = (if is_wfe then HCR_EL2.TWE else HCR_EL2.TWI) == '1';</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            trap = (if is_wfe then SCR_EL3.TWE else SCR_EL3.TWI) == '1';</line>
<line></line>
<line>    if trap then</line>
<line>        <a link="AArch64.WFxTrap.2" file="shared_pseudocode.xml" hover="function: AArch64.WFxTrap(WFxType wfxtype, bits(2) target_el)">AArch64.WFxTrap</a>(wfxtype, target_el);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/AArch64.CheckIllegalState" mylink="aarch64.exceptions.traps.AArch64.CheckIllegalState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.CheckIllegalState()</line>
<line>// ===========================</line>
<line>// Check PSTATE.IL bit and generate Illegal Execution state exception if set.</line>
<line></line>
<line link="AArch64.CheckIllegalState.0" hover="function: AArch64.CheckIllegalState()" conts="AArch64.CheckIllegalState"><anchor link="AArch64.CheckIllegalState.0" hover="function: AArch64.CheckIllegalState()">AArch64.CheckIllegalState</anchor>()</line>
<line>    if PSTATE.IL == '1' then</line>
<line>        route_to_el2 = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1';</line>
<line></line>
<line>        bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>        vect_offset = 0x0;</line>
<line></line>
<line>        exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_IllegalState" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_IllegalState</a>);</line>
<line></line>
<line>        if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>            <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(PSTATE.EL, exception, preferred_exception_return, vect_offset);</line>
<line>        elsif route_to_el2 then</line>
<line>            <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, exception, preferred_exception_return, vect_offset);</line>
<line>        else</line>
<line>            <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/AArch64.MonitorModeTrap" mylink="aarch64.exceptions.traps.AArch64.MonitorModeTrap" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.MonitorModeTrap()</line>
<line>// =========================</line>
<line>// Trapped use of Monitor mode features in a Secure EL1 AArch32 mode</line>
<line></line>
<line link="AArch64.MonitorModeTrap.0" hover="function: AArch64.MonitorModeTrap()" conts="AArch64.MonitorModeTrap"><anchor link="AArch64.MonitorModeTrap.0" hover="function: AArch64.MonitorModeTrap()">AArch64.MonitorModeTrap</anchor>()</line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x0;</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_Uncategorized" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Uncategorized</a>);</line>
<line></line>
<line>    if <a link="impl-shared.IsSecureEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsSecureEL2Enabled()">IsSecureEL2Enabled</a>() then</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, exception, preferred_exception_return, vect_offset);</line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/AArch64.SystemAccessTrap" mylink="aarch64.exceptions.traps.AArch64.SystemAccessTrap" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.SystemAccessTrap()</line>
<line>// ==========================</line>
<line>// Trapped access to AArch64 System register or system instruction.</line>
<line></line>
<line link="AArch64.SystemAccessTrap.2" hover="function: AArch64.SystemAccessTrap(bits(2) target_el, integer ec)" conts="AArch64.SystemAccessTrap"><anchor link="AArch64.SystemAccessTrap.2" hover="function: AArch64.SystemAccessTrap(bits(2) target_el, integer ec)">AArch64.SystemAccessTrap</anchor>(bits(2) target_el, integer ec)</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(target_el) &amp;&amp; target_el != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(target_el) &gt;= <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL);</line>
<line></line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x0;</line>
<line></line>
<line>    exception = <a link="AArch64.SystemAccessTrapSyndrome.2" file="shared_pseudocode.xml" hover="function: ExceptionRecord AArch64.SystemAccessTrapSyndrome(bits(32) instr_in, integer ec)">AArch64.SystemAccessTrapSyndrome</a>(<a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>(), ec);</line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(target_el, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/AArch64.SystemAccessTrapSyndrome" mylink="aarch64.exceptions.traps.AArch64.SystemAccessTrapSyndrome" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.SystemAccessTrapSyndrome()</line>
<line>// ==================================</line>
<line>// Returns the syndrome information for traps on AArch64 MSR/MRS instructions.</line>
<line></line>
<line link="AArch64.SystemAccessTrapSyndrome.2" hover="function: ExceptionRecord AArch64.SystemAccessTrapSyndrome(bits(32) instr_in, integer ec)" conts="AArch64.SystemAccessTrapSyndrome">ExceptionRecord <anchor link="AArch64.SystemAccessTrapSyndrome.2" hover="function: ExceptionRecord AArch64.SystemAccessTrapSyndrome(bits(32) instr_in, integer ec)">AArch64.SystemAccessTrapSyndrome</anchor>(bits(32) instr_in, integer ec)</line>
<line>    <a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception;</line>
<line>    bits(32) instr = instr_in;</line>
<line>    case ec of</line>
<line>        when 0x0                         // Trapped access due to unknown reason.</line>
<line>            exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_Uncategorized" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Uncategorized</a>);</line>
<line>        when 0x7                         // Trapped access to SVE, Advance SIMD&amp;FP System register.</line>
<line>            exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_AdvSIMDFPAccessTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_AdvSIMDFPAccessTrap</a>);</line>
<line>            exception.syndrome&lt;24:20&gt; = <a link="impl-shared.ConditionSyndrome.0" file="shared_pseudocode.xml" hover="function: bits(5) ConditionSyndrome()">ConditionSyndrome</a>();</line>
<line>        when 0x14                        // Trapped access to 128-bit System register or</line>
<line>                                         // 128-bit System instruction.</line>
<line>            exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_SystemRegister128Trap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SystemRegister128Trap</a>);</line>
<line>            instr = <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>();</line>
<line>            exception.syndrome&lt;21:20&gt; = instr&lt;20:19&gt;; // Op0</line>
<line>            exception.syndrome&lt;19:17&gt; = instr&lt;7:5&gt;;   // Op2</line>
<line>            exception.syndrome&lt;16:14&gt; = instr&lt;18:16&gt;; // Op1</line>
<line>            exception.syndrome&lt;13:10&gt; = instr&lt;15:12&gt;; // CRn</line>
<line>            exception.syndrome&lt;9:6&gt;   = instr&lt;4:1&gt;;   // Rt</line>
<line>            exception.syndrome&lt;4:1&gt;   = instr&lt;11:8&gt;;  // CRm</line>
<line>            exception.syndrome&lt;0&gt;     = instr&lt;21&gt;;    // Direction</line>
<line>        when 0x18                        // Trapped access to System register or system instruction.</line>
<line>            exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_SystemRegisterTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SystemRegisterTrap</a>);</line>
<line>            instr = <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>();</line>
<line>            exception.syndrome&lt;21:20&gt; = instr&lt;20:19&gt;; // Op0</line>
<line>            exception.syndrome&lt;19:17&gt; = instr&lt;7:5&gt;;   // Op2</line>
<line>            exception.syndrome&lt;16:14&gt; = instr&lt;18:16&gt;; // Op1</line>
<line>            exception.syndrome&lt;13:10&gt; = instr&lt;15:12&gt;; // CRn</line>
<line>            exception.syndrome&lt;9:5&gt;   = instr&lt;4:0&gt;;   // Rt</line>
<line>            exception.syndrome&lt;4:1&gt;   = instr&lt;11:8&gt;;  // CRm</line>
<line>            exception.syndrome&lt;0&gt;     = instr&lt;21&gt;;    // Direction</line>
<line>        when 0x19                        // Trapped access to SVE System register</line>
<line>            exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_SVEAccessTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SVEAccessTrap</a>);</line>
<line>        when 0x1D                        // Trapped access to SME System register</line>
<line>            exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_SMEAccessTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SMEAccessTrap</a>);</line>
<line>        otherwise</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    return exception;</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/AArch64.UndefinedFault" mylink="aarch64.exceptions.traps.AArch64.UndefinedFault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.UndefinedFault()</line>
<line>// ========================</line>
<line></line>
<line link="AArch64.UndefinedFault.0" hover="function: AArch64.UndefinedFault()" conts="AArch64.UndefinedFault"><anchor link="AArch64.UndefinedFault.0" hover="function: AArch64.UndefinedFault()">AArch64.UndefinedFault</anchor>()</line>
<line></line>
<line>    route_to_el2 = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1';</line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x0;</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_Uncategorized" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Uncategorized</a>);</line>
<line></line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(PSTATE.EL, exception, preferred_exception_return, vect_offset);</line>
<line>    elsif route_to_el2 then</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, exception, preferred_exception_return, vect_offset);</line>
<line>    else</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/AArch64.WFxTrap" mylink="aarch64.exceptions.traps.AArch64.WFxTrap" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.WFxTrap()</line>
<line>// =================</line>
<line></line>
<line link="AArch64.WFxTrap.2" hover="function: AArch64.WFxTrap(WFxType wfxtype, bits(2) target_el)" conts="AArch64.WFxTrap"><anchor link="AArch64.WFxTrap.2" hover="function: AArch64.WFxTrap(WFxType wfxtype, bits(2) target_el)">AArch64.WFxTrap</anchor>(<a link="WFxType" file="shared_pseudocode.xml" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType</a> wfxtype, bits(2) target_el)</line>
<line>    assert <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(target_el) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL);</line>
<line></line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x0;</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_WFxTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_WFxTrap</a>);</line>
<line>    exception.syndrome&lt;24:20&gt; = <a link="impl-shared.ConditionSyndrome.0" file="shared_pseudocode.xml" hover="function: bits(5) ConditionSyndrome()">ConditionSyndrome</a>();</line>
<line></line>
<line>    case wfxtype of</line>
<line>        when <a link="WFxType_WFI" file="shared_pseudocode.xml" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFI</a></line>
<line>            exception.syndrome&lt;1:0&gt; = '00';</line>
<line>        when <a link="WFxType_WFE" file="shared_pseudocode.xml" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFE</a></line>
<line>            exception.syndrome&lt;1:0&gt; = '01';</line>
<line>        when <a link="WFxType_WFIT" file="shared_pseudocode.xml" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFIT</a></line>
<line>            exception.syndrome&lt;1:0&gt; = '10';</line>
<line>            exception.syndrome&lt;2&gt;   = '1';   // Register field is valid</line>
<line>            exception.syndrome&lt;9:5&gt; = <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>()&lt;4:0&gt;;</line>
<line>        when <a link="WFxType_WFET" file="shared_pseudocode.xml" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFET</a></line>
<line>            exception.syndrome&lt;1:0&gt; = '11';</line>
<line>            exception.syndrome&lt;2&gt;   = '1';   // Register field is valid</line>
<line>            exception.syndrome&lt;9:5&gt; = <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>()&lt;4:0&gt;;</line>
<line></line>
<line>    if target_el == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1' then</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, exception, preferred_exception_return, vect_offset);</line>
<line>    else</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(target_el, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/CheckFPAdvSIMDEnabled64" mylink="aarch64.exceptions.traps.CheckFPAdvSIMDEnabled64" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckFPAdvSIMDEnabled64()</line>
<line>// =========================</line>
<line>// AArch64 instruction wrapper</line>
<line></line>
<line link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" hover="function: CheckFPAdvSIMDEnabled64()" conts="CheckFPAdvSIMDEnabled64"><anchor link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</anchor>()</line>
<line>    <a link="AArch64.CheckFPAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/CheckFPEnabled64" mylink="aarch64.exceptions.traps.CheckFPEnabled64" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckFPEnabled64()</line>
<line>// ==================</line>
<line>// AArch64 instruction wrapper</line>
<line></line>
<line link="impl-aarch64.CheckFPEnabled64.0" hover="function: CheckFPEnabled64()" conts="CheckFPEnabled64"><anchor link="impl-aarch64.CheckFPEnabled64.0" hover="function: CheckFPEnabled64()">CheckFPEnabled64</anchor>()</line>
<line>    <a link="AArch64.CheckFPEnabled.0" file="shared_pseudocode.xml" hover="function: AArch64.CheckFPEnabled()">AArch64.CheckFPEnabled</a>();</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/CheckLDST64BEnabled" mylink="aarch64.exceptions.traps.CheckLDST64BEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckLDST64BEnabled()</line>
<line>// =====================</line>
<line>// Checks for trap on ST64B and LD64B instructions</line>
<line></line>
<line link="impl-aarch64.CheckLDST64BEnabled.0" hover="function: CheckLDST64BEnabled()" conts="CheckLDST64BEnabled"><anchor link="impl-aarch64.CheckLDST64BEnabled.0" hover="function: CheckLDST64BEnabled()">CheckLDST64BEnabled</anchor>()</line>
<line>    boolean trap = FALSE;</line>
<line>    bits(25) iss = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('10', 25);  // 0x2</line>
<line>    bits(2) target_el;</line>
<line></line>
<line>    if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        if !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>            trap = SCTLR_EL1.EnALS == '0';</line>
<line>            target_el = if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1' then <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> else <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>        else</line>
<line>            trap = SCTLR_EL2.EnALS == '0';</line>
<line>            target_el = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>    else</line>
<line>        target_el = <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line></line>
<line>    if (!trap &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>        ((PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>()) || PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>)) then</line>
<line>        trap = !<a link="impl-aarch64.IsHCRXEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsHCRXEL2Enabled()">IsHCRXEL2Enabled</a>() || HCRX_EL2.EnALS == '0';</line>
<line>        target_el = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line></line>
<line>    if trap then <a link="impl-aarch64.LDST64BTrap.2" file="shared_pseudocode.xml" hover="function: LDST64BTrap(bits(2) target_el, bits(25) iss)">LDST64BTrap</a>(target_el, iss);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/CheckST64BV0Enabled" mylink="aarch64.exceptions.traps.CheckST64BV0Enabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckST64BV0Enabled()</line>
<line>// =====================</line>
<line>// Checks for trap on ST64BV0 instruction</line>
<line></line>
<line link="impl-aarch64.CheckST64BV0Enabled.0" hover="function: CheckST64BV0Enabled()" conts="CheckST64BV0Enabled"><anchor link="impl-aarch64.CheckST64BV0Enabled.0" hover="function: CheckST64BV0Enabled()">CheckST64BV0Enabled</anchor>()</line>
<line>    boolean trap = FALSE;</line>
<line>    bits(25) iss = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('1', 25);  // 0x1</line>
<line>    bits(2) target_el;</line>
<line></line>
<line>    if (PSTATE.EL != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> &amp;&amp; <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp;</line>
<line>        SCR_EL3.EnAS0 == '0' &amp;&amp; <a link="impl-shared.EL3SDDUndefPriority.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndefPriority()">EL3SDDUndefPriority</a>()) then</line>
<line>        UNDEFINED;</line>
<line></line>
<line>    if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        if !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>            trap = SCTLR_EL1.EnAS0 == '0';</line>
<line>            target_el = if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1' then <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> else <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>        else</line>
<line>            trap = SCTLR_EL2.EnAS0 == '0';</line>
<line>            target_el = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line></line>
<line>    if (!trap &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>        ((PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>()) || PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>)) then</line>
<line>        trap = !<a link="impl-aarch64.IsHCRXEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsHCRXEL2Enabled()">IsHCRXEL2Enabled</a>() || HCRX_EL2.EnAS0 == '0';</line>
<line>        target_el = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line></line>
<line>    if !trap &amp;&amp; PSTATE.EL != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then</line>
<line>        trap = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.EnAS0 == '0';</line>
<line>        target_el = <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line></line>
<line>    if trap then</line>
<line>        if target_el == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> &amp;&amp; <a link="impl-shared.EL3SDDUndef.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndef()">EL3SDDUndef</a>() then</line>
<line>            UNDEFINED;</line>
<line>        else</line>
<line>            <a link="impl-aarch64.LDST64BTrap.2" file="shared_pseudocode.xml" hover="function: LDST64BTrap(bits(2) target_el, bits(25) iss)">LDST64BTrap</a>(target_el, iss);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/CheckST64BVEnabled" mylink="aarch64.exceptions.traps.CheckST64BVEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckST64BVEnabled()</line>
<line>// ====================</line>
<line>// Checks for trap on ST64BV instruction</line>
<line></line>
<line link="impl-aarch64.CheckST64BVEnabled.0" hover="function: CheckST64BVEnabled()" conts="CheckST64BVEnabled"><anchor link="impl-aarch64.CheckST64BVEnabled.0" hover="function: CheckST64BVEnabled()">CheckST64BVEnabled</anchor>()</line>
<line>    boolean trap = FALSE;</line>
<line>    bits(25) iss = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(25);</line>
<line>    bits(2) target_el;</line>
<line></line>
<line>    if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        if !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>            trap = SCTLR_EL1.EnASR == '0';</line>
<line>            target_el = if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1' then <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> else <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>        else</line>
<line>            trap = SCTLR_EL2.EnASR == '0';</line>
<line>            target_el = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line></line>
<line>    if (!trap &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>        ((PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>()) || PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>)) then</line>
<line>        trap = !<a link="impl-aarch64.IsHCRXEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsHCRXEL2Enabled()">IsHCRXEL2Enabled</a>() || HCRX_EL2.EnASR == '0';</line>
<line>        target_el = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line></line>
<line>    if trap then <a link="impl-aarch64.LDST64BTrap.2" file="shared_pseudocode.xml" hover="function: LDST64BTrap(bits(2) target_el, bits(25) iss)">LDST64BTrap</a>(target_el, iss);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/LDST64BTrap" mylink="aarch64.exceptions.traps.LDST64BTrap" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// LDST64BTrap()</line>
<line>// =============</line>
<line>// Trapped access to LD64B, ST64B, ST64BV and ST64BV0 instructions</line>
<line></line>
<line link="impl-aarch64.LDST64BTrap.2" hover="function: LDST64BTrap(bits(2) target_el, bits(25) iss)" conts="LDST64BTrap"><anchor link="impl-aarch64.LDST64BTrap.2" hover="function: LDST64BTrap(bits(2) target_el, bits(25) iss)">LDST64BTrap</anchor>(bits(2) target_el, bits(25) iss)</line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x0;</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_LDST64BTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_LDST64BTrap</a>);</line>
<line>    exception.syndrome = iss;</line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(target_el, exception, preferred_exception_return, vect_offset);</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/WFETrapDelay" mylink="aarch64.exceptions.traps.WFETrapDelay" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// WFETrapDelay()</line>
<line>// ==============</line>
<line>// Returns TRUE when delay in trap to WFE is enabled with value to amount of delay,</line>
<line>// FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.WFETrapDelay.1" hover="function: (boolean, integer) WFETrapDelay(bits(2) target_el)" conts="WFETrapDelay">(boolean, integer) <anchor link="impl-aarch64.WFETrapDelay.1" hover="function: (boolean, integer) WFETrapDelay(bits(2) target_el)">WFETrapDelay</anchor>(bits(2) target_el)</line>
<line>    boolean delay_enabled;</line>
<line>    integer delay;</line>
<line>    case target_el of</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            if !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>                delay_enabled = SCTLR_EL1.TWEDEn == '1';</line>
<line>                delay         = 1 &lt;&lt; (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(SCTLR_EL1.TWEDEL) + 8);</line>
<line>            else</line>
<line>                delay_enabled = SCTLR_EL2.TWEDEn == '1';</line>
<line>                delay         = 1 &lt;&lt; (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(SCTLR_EL2.TWEDEL) + 8);</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            assert <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>();</line>
<line>            delay_enabled = HCR_EL2.TWEDEn == '1';</line>
<line>            delay         = 1 &lt;&lt; (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(HCR_EL2.TWEDEL) + 8);</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            delay_enabled = SCR_EL3.TWEDEn == '1';</line>
<line>            delay         = 1 &lt;&lt; (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(SCR_EL3.TWEDEL) + 8);</line>
<line></line>
<line>    return (delay_enabled, delay);</line>
</pstext>
    </ps>
    <ps name="aarch64/exceptions/traps/WaitForEventUntilDelay" mylink="aarch64.exceptions.traps.WaitForEventUntilDelay" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// WaitForEventUntilDelay()</line>
<line>// ========================</line>
<line>// Returns TRUE if WaitForEvent() returns before WFE trap delay expires,</line>
<line>// FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.WaitForEventUntilDelay.2" hover="function: boolean WaitForEventUntilDelay(boolean delay_enabled, integer delay)" conts="WaitForEventUntilDelay">boolean <anchor link="impl-aarch64.WaitForEventUntilDelay.2" hover="function: boolean WaitForEventUntilDelay(boolean delay_enabled, integer delay)">WaitForEventUntilDelay</anchor>(boolean delay_enabled, integer delay);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/aborts/AArch64.FaultSyndrome" mylink="aarch64.functions.aborts.AArch64.FaultSyndrome" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.FaultSyndrome()</line>
<line>// =======================</line>
<line>// Creates an exception syndrome value for Abort and Watchpoint exceptions taken to</line>
<line>// an Exception level using AArch64.</line>
<line></line>
<line link="AArch64.FaultSyndrome.3" hover="function: (bits(25), bits(24)) AArch64.FaultSyndrome(boolean d_side, FaultRecord fault, boolean pavalid)" conts="AArch64.FaultSyndrome">(bits(25), bits(24)) <anchor link="AArch64.FaultSyndrome.3" hover="function: (bits(25), bits(24)) AArch64.FaultSyndrome(boolean d_side, FaultRecord fault, boolean pavalid)">AArch64.FaultSyndrome</anchor>(boolean d_side, <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault, boolean pavalid)</line>
<line>    assert fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a>;</line>
<line></line>
<line>    bits(25) iss  = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(25);</line>
<line>    bits(24) iss2 = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(24);</line>
<line></line>
<line>    if <a link="impl-shared.HaveRASExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveRASExt()">HaveRASExt</a>() &amp;&amp; fault.statuscode == <a link="Fault_SyncExternal" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncExternal</a> then</line>
<line>        <a link="ErrorState" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState</a> errstate = <a link="AArch64.PEErrorState.1" file="shared_pseudocode.xml" hover="function: ErrorState AArch64.PEErrorState(FaultRecord fault)">AArch64.PEErrorState</a>(fault);</line>
<line>        iss&lt;12:11&gt; = <a link="AArch64.EncodeSyncErrorSyndrome.1" file="shared_pseudocode.xml" hover="function: bits(2) AArch64.EncodeSyncErrorSyndrome(ErrorState errorstate)">AArch64.EncodeSyncErrorSyndrome</a>(errstate);  // SET</line>
<line></line>
<line>    if d_side then</line>
<line>        if fault.access.acctype == <a link="AccessType_GCS" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GCS</a> then</line>
<line>            iss2&lt;8&gt; = '1';</line>
<line>        if <a link="impl-shared.HaveFeatLS64.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatLS64()">HaveFeatLS64</a>() &amp;&amp; fault.access.ls64 then</line>
<line>            if (fault.statuscode IN {<a link="Fault_AccessFlag" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AccessFlag</a>, <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>, <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>}) then</line>
<line>                (iss2, iss&lt;24:14&gt;) = <a link="impl-aarch64.LS64InstructionSyndrome.0" file="shared_pseudocode.xml" hover="function: (bits(24), bits(11)) LS64InstructionSyndrome()">LS64InstructionSyndrome</a>();</line>
<line>        elsif (<a link="impl-shared.IsSecondStage.1" file="shared_pseudocode.xml" hover="function: boolean IsSecondStage(FaultRecord fault)">IsSecondStage</a>(fault) &amp;&amp; !fault.s2fs1walk &amp;&amp;</line>
<line>               (!<a link="impl-shared.IsExternalSyncAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalSyncAbort(Fault statuscode)">IsExternalSyncAbort</a>(fault) ||</line>
<line>               (!<a link="impl-shared.HaveRASExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveRASExt()">HaveRASExt</a>() &amp;&amp; fault.access.acctype == <a link="AccessType_TTW" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_TTW</a> &amp;&amp;</line>
<line>               boolean IMPLEMENTATION_DEFINED "ISV on second stage translation table walk"))) then</line>
<line>            iss&lt;24:14&gt; = <a link="impl-shared.LSInstructionSyndrome.0" file="shared_pseudocode.xml" hover="function: bits(11) LSInstructionSyndrome()">LSInstructionSyndrome</a>();</line>
<line></line>
<line>        if <a link="impl-shared.HaveNV2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveNV2Ext()">HaveNV2Ext</a>() &amp;&amp; fault.access.acctype == <a link="AccessType_NV2" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_NV2</a> then</line>
<line>            iss&lt;13&gt; = '1';   // Fault is generated by use of VNCR_EL2</line>
<line></line>
<line>        if <a link="impl-shared.HaveFeatLS64.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatLS64()">HaveFeatLS64</a>() &amp;&amp; fault.statuscode IN {<a link="Fault_AccessFlag" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AccessFlag</a>, <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>,</line>
<line>                                                  <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>} then</line>
<line>            iss&lt;12:11&gt; = <a link="impl-shared.GetLoadStoreType.0" file="shared_pseudocode.xml" hover="function: bits(2) GetLoadStoreType()">GetLoadStoreType</a>();</line>
<line></line>
<line>        if fault.access.acctype IN {<a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>, <a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a>, <a link="AccessType_AT" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_AT</a>} then</line>
<line>            iss&lt;8&gt; = '1';</line>
<line></line>
<line>        if fault.access.acctype IN {<a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>, <a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a>, <a link="AccessType_AT" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_AT</a>} then</line>
<line>            iss&lt;6&gt; = '1';</line>
<line>        elsif fault.statuscode IN {<a link="Fault_HWUpdateAccessFlag" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_HWUpdateAccessFlag</a>, <a link="Fault_Exclusive" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Exclusive</a>} then</line>
<line>            iss&lt;6&gt; = bit UNKNOWN;</line>
<line>        elsif fault.access.atomicop &amp;&amp; <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault) then</line>
<line>            iss&lt;6&gt; = bit UNKNOWN;</line>
<line>        else</line>
<line>            iss&lt;6&gt; = if fault.write then '1' else '0';</line>
<line></line>
<line>        if fault.statuscode == <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a> then</line>
<line>            iss2&lt;5&gt; = if fault.dirtybit then '1' else '0';</line>
<line>            iss2&lt;6&gt; = if fault.overlay then '1' else '0';</line>
<line>            if iss&lt;24&gt; == '0' then</line>
<line>                iss&lt;21&gt; = if fault.toplevel then '1' else '0';</line>
<line>            iss2&lt;7&gt; = if fault.assuredonly then '1' else '0';</line>
<line>            iss2&lt;9&gt; = if fault.tagaccess then '1' else '0';</line>
<line>            iss2&lt;10&gt; = if fault.s1tagnotdata then '1' else '0';</line>
<line></line>
<line>    else</line>
<line>        if fault.access.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> &amp;&amp; fault.statuscode == <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a> then</line>
<line>            iss&lt;21&gt; = if fault.toplevel then '1' else '0';</line>
<line>            iss2&lt;7&gt; = if fault.assuredonly then '1' else '0';</line>
<line>            iss2&lt;6&gt; = if fault.overlay then '1' else '0';</line>
<line>    if <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault) then iss&lt;9&gt; = fault.extflag;</line>
<line>    iss&lt;7&gt; = if fault.s2fs1walk then '1' else '0';</line>
<line>    iss&lt;5:0&gt; = <a link="impl-shared.EncodeLDFSC.2" file="shared_pseudocode.xml" hover="function: bits(6) EncodeLDFSC(Fault statuscode, integer level)">EncodeLDFSC</a>(fault.statuscode, fault.level);</line>
<line></line>
<line>    return (iss, iss2);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/aborts/EncodeGPCSC" mylink="aarch64.functions.aborts.EncodeGPCSC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EncodeGPCSC()</line>
<line>// =============</line>
<line>// Function that gives the GPCSC code for types of GPT Fault</line>
<line></line>
<line link="impl-aarch64.EncodeGPCSC.1" hover="function: bits(6) EncodeGPCSC(GPCFRecord gpcf)" conts="EncodeGPCSC">bits(6) <anchor link="impl-aarch64.EncodeGPCSC.1" hover="function: bits(6) EncodeGPCSC(GPCFRecord gpcf)">EncodeGPCSC</anchor>(<a link="GPCFRecord" file="shared_pseudocode.xml" hover="type GPCFRecord is ( GPCF gpf, integer level )">GPCFRecord</a> gpcf)</line>
<line>    assert gpcf.level IN {0,1};</line>
<line></line>
<line>    case gpcf.gpf of</line>
<line>        when <a link="GPCF_AddressSize" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_AddressSize</a> return '00000':gpcf.level&lt;0&gt;;</line>
<line>        when <a link="GPCF_Walk" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_Walk</a>        return '00010':gpcf.level&lt;0&gt;;</line>
<line>        when <a link="GPCF_Fail" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_Fail</a>        return '00110':gpcf.level&lt;0&gt;;</line>
<line>        when <a link="GPCF_EABT" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_EABT</a>        return '01010':gpcf.level&lt;0&gt;;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/aborts/LS64InstructionSyndrome" mylink="aarch64.functions.aborts.LS64InstructionSyndrome" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// LS64InstructionSyndrome()</line>
<line>// =========================</line>
<line>// Returns the syndrome information and LST for a Data Abort by a</line>
<line>// ST64B, ST64BV, ST64BV0, or LD64B instruction. The syndrome information</line>
<line>// includes the ISS2, extended syndrome field.</line>
<line></line>
<line link="impl-aarch64.LS64InstructionSyndrome.0" hover="function: (bits(24), bits(11)) LS64InstructionSyndrome()" conts="LS64InstructionSyndrome">(bits(24), bits(11)) <anchor link="impl-aarch64.LS64InstructionSyndrome.0" hover="function: (bits(24), bits(11)) LS64InstructionSyndrome()">LS64InstructionSyndrome</anchor>();</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/cache/AArch64.DataMemZero" mylink="aarch64.functions.cache.AArch64.DataMemZero" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.DataMemZero()</line>
<line>// =====================</line>
<line>// Write Zero to data memory.</line>
<line></line>
<line link="AArch64.DataMemZero.4" hover="function: AArch64.DataMemZero(bits(64) regval, bits(64) vaddress, AccessDescriptor accdesc_in, integer size)" conts="AArch64.DataMemZero"><anchor link="AArch64.DataMemZero.4" hover="function: AArch64.DataMemZero(bits(64) regval, bits(64) vaddress, AccessDescriptor accdesc_in, integer size)">AArch64.DataMemZero</anchor>(bits(64) regval, bits(64) vaddress, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc_in, integer size)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = accdesc_in;</line>
<line></line>
<line>    // If the instruction targets tags as a payload, confer with system register configuration</line>
<line>    // which may override this.</line>
<line>    if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; accdesc.tagaccess then</line>
<line>        accdesc.tagaccess = <a link="AArch64.AllocationTagAccessIsEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.AllocationTagAccessIsEnabled(bits(2) el)">AArch64.AllocationTagAccessIsEnabled</a>(accdesc.el);</line>
<line></line>
<line>    // If the instruction encoding permits tag checking, confer with system register configuration</line>
<line>    // which may override this.</line>
<line>    if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; accdesc.tagchecked then</line>
<line>        accdesc.tagchecked = <a link="AArch64.AccessIsTagChecked.2" file="shared_pseudocode.xml" hover="function: boolean AArch64.AccessIsTagChecked(bits(64) vaddr, AccessDescriptor accdesc)">AArch64.AccessIsTagChecked</a>(vaddress, accdesc);</line>
<line></line>
<line>    boolean aligned = TRUE;</line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc = <a link="AArch64.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch64.TranslateAddress(bits(64) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch64.TranslateAddress</a>(vaddress, accdesc, aligned, size);</line>
<line></line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>        if <a link="impl-shared.IsDebugException.1" file="shared_pseudocode.xml" hover="function: boolean IsDebugException(FaultRecord fault)">IsDebugException</a>(memaddrdesc.fault) then</line>
<line>            <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(vaddress, memaddrdesc.fault);</line>
<line>        else</line>
<line>            <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(regval, memaddrdesc.fault);</line>
<line></line>
<line>    if <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() then</line>
<line>        if accdesc.transactional &amp;&amp; !<a link="impl-aarch64.MemHasTransactionalAccess.1" file="shared_pseudocode.xml" hover="function: boolean MemHasTransactionalAccess(MemoryAttributes memattrs)">MemHasTransactionalAccess</a>(memaddrdesc.memattrs) then</line>
<line>            <a link="impl-aarch64.FailTransaction.2" file="shared_pseudocode.xml" hover="function: FailTransaction(TMFailure cause, boolean retry)">FailTransaction</a>(<a link="TMFailure_IMP" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_IMP</a>, FALSE);</line>
<line></line>
<line>    for i = 0 to size-1</line>
<line>        if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; accdesc.tagchecked then</line>
<line>            bits(4) ptag = <a link="AArch64.PhysicalTag.1" file="shared_pseudocode.xml" hover="function: bits(4) AArch64.PhysicalTag(bits(64) vaddr)">AArch64.PhysicalTag</a>(vaddress);</line>
<line>            if !<a link="AArch64.CheckTag.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.CheckTag(AddressDescriptor memaddrdesc, AccessDescriptor accdesc, bits(4) ptag)">AArch64.CheckTag</a>(memaddrdesc, accdesc, ptag) then</line>
<line>                if (boolean IMPLEMENTATION_DEFINED</line>
<line>                      "DC_ZVA tag fault reported with lowest faulting address") then</line>
<line>                    <a link="AArch64.TagCheckFault.2" file="shared_pseudocode.xml" hover="function: AArch64.TagCheckFault(bits(64) vaddress, AccessDescriptor accdesc)">AArch64.TagCheckFault</a>(vaddress, accdesc);</line>
<line>                else</line>
<line>                    <a link="AArch64.TagCheckFault.2" file="shared_pseudocode.xml" hover="function: AArch64.TagCheckFault(bits(64) vaddress, AccessDescriptor accdesc)">AArch64.TagCheckFault</a>(regval, accdesc);</line>
<line>        memstatus = <a link="impl-shared.PhysMemWrite.4" file="shared_pseudocode.xml" hover="function: PhysMemRetStatus PhysMemWrite(AddressDescriptor desc, integer size, AccessDescriptor accdesc, bits(8*size) value)">PhysMemWrite</a>(memaddrdesc, 1, accdesc, <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8));</line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>            <a link="impl-shared.HandleExternalWriteAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalWriteAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalWriteAbort</a>(memstatus, memaddrdesc, 1, accdesc);</line>
<line></line>
<line>        memaddrdesc.paddress.address = memaddrdesc.paddress.address + 1;</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/cache/AArch64.TagMemZero" mylink="aarch64.functions.cache.AArch64.TagMemZero" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TagMemZero()</line>
<line>// ====================</line>
<line>// Write Zero to tag memory.</line>
<line></line>
<line link="AArch64.TagMemZero.4" hover="function: AArch64.TagMemZero(bits(64) regval, bits(64) vaddress, AccessDescriptor accdesc_in, integer size)" conts="AArch64.TagMemZero"><anchor link="AArch64.TagMemZero.4" hover="function: AArch64.TagMemZero(bits(64) regval, bits(64) vaddress, AccessDescriptor accdesc_in, integer size)">AArch64.TagMemZero</anchor>(bits(64) regval, bits(64) vaddress, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc_in, integer size)</line>
<line>    assert accdesc_in.tagaccess &amp;&amp; !accdesc_in.tagchecked;</line>
<line></line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = accdesc_in;</line>
<line></line>
<line>    integer count = size &gt;&gt; <a link="LOG2_TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer LOG2_TAG_GRANULE = 4">LOG2_TAG_GRANULE</a>;</line>
<line>    bits(4) tag = <a link="AArch64.AllocationTagFromAddress.1" file="shared_pseudocode.xml" hover="function: bits(4) AArch64.AllocationTagFromAddress(bits(64) tagged_address)">AArch64.AllocationTagFromAddress</a>(vaddress);</line>
<line>    boolean aligned = <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(vaddress, <a link="TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer TAG_GRANULE = 1 &lt;&lt; LOG2_TAG_GRANULE">TAG_GRANULE</a>);</line>
<line></line>
<line>    // Stores of allocation tags must be aligned</line>
<line>    if !aligned then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(vaddress, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() then</line>
<line>        accdesc.tagaccess = <a link="AArch64.AllocationTagAccessIsEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.AllocationTagAccessIsEnabled(bits(2) el)">AArch64.AllocationTagAccessIsEnabled</a>(accdesc.el);</line>
<line></line>
<line>    memaddrdesc = <a link="AArch64.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch64.TranslateAddress(bits(64) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch64.TranslateAddress</a>(vaddress, accdesc, aligned, size);</line>
<line></line>
<line>    // Check for aborts or debug exceptions</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>        if <a link="impl-shared.IsDebugException.1" file="shared_pseudocode.xml" hover="function: boolean IsDebugException(FaultRecord fault)">IsDebugException</a>(memaddrdesc.fault) then</line>
<line>            <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(vaddress, memaddrdesc.fault);</line>
<line>        else</line>
<line>            <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(regval, memaddrdesc.fault);</line>
<line></line>
<line>    if !accdesc.tagaccess || memaddrdesc.memattrs.tags != <a link="MemTag_AllocationTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_AllocationTagged</a> then</line>
<line>        return;</line>
<line></line>
<line>    for i = 0 to count-1</line>
<line>        memstatus = <a link="impl-aarch64.PhysMemTagWrite.3" file="shared_pseudocode.xml" hover="function: PhysMemRetStatus PhysMemTagWrite(AddressDescriptor desc, AccessDescriptor accdesc, bits (4) value)">PhysMemTagWrite</a>(memaddrdesc, accdesc, tag);</line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>            <a link="impl-shared.HandleExternalWriteAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalWriteAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalWriteAbort</a>(memstatus, memaddrdesc, 1, accdesc);</line>
<line></line>
<line>        memaddrdesc.paddress.address = memaddrdesc.paddress.address + <a link="TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer TAG_GRANULE = 1 &lt;&lt; LOG2_TAG_GRANULE">TAG_GRANULE</a>;</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/d128/IsD128Enabled" mylink="aarch64.functions.d128.IsD128Enabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsD128Enabled()</line>
<line>// ===============</line>
<line>// Returns true if 128-bit page descriptor is enabled</line>
<line></line>
<line link="impl-aarch64.IsD128Enabled.1" hover="function: boolean IsD128Enabled(bits(2) el)" conts="IsD128Enabled">boolean <anchor link="impl-aarch64.IsD128Enabled.1" hover="function: boolean IsD128Enabled(bits(2) el)">IsD128Enabled</anchor>(bits(2) el)</line>
<line>    boolean d128enabled;</line>
<line>    if <a link="impl-shared.Have128BitDescriptorExt.0" file="shared_pseudocode.xml" hover="function: boolean Have128BitDescriptorExt()">Have128BitDescriptorExt</a>() then</line>
<line>        case el of</line>
<line>            when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>                if !<a link="impl-shared.ELIsInHost.1" file="shared_pseudocode.xml" hover="function: boolean ELIsInHost(bits(2) el)">ELIsInHost</a>(<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>) then</line>
<line>                    d128enabled = <a link="impl-aarch64.IsTCR2EL1Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL1Enabled()">IsTCR2EL1Enabled</a>() &amp;&amp; TCR2_EL1.D128 == '1';</line>
<line>                else</line>
<line>                    d128enabled = <a link="impl-aarch64.IsTCR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL2Enabled()">IsTCR2EL2Enabled</a>() &amp;&amp; TCR2_EL2.D128 == '1';</line>
<line>            when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>                d128enabled = <a link="impl-aarch64.IsTCR2EL1Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL1Enabled()">IsTCR2EL1Enabled</a>() &amp;&amp; TCR2_EL1.D128 == '1';</line>
<line>            when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>                d128enabled = <a link="impl-aarch64.IsTCR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL2Enabled()">IsTCR2EL2Enabled</a>() &amp;&amp; HCR_EL2.E2H == '1' &amp;&amp; TCR2_EL2.D128 == '1';</line>
<line>            when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>                d128enabled = TCR_EL3.D128 == '1';</line>
<line>    else</line>
<line>        d128enabled = FALSE;</line>
<line></line>
<line>    return d128enabled;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/exclusive/AArch64.ExclusiveMonitorsPass" mylink="aarch64.functions.exclusive.AArch64.ExclusiveMonitorsPass" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ExclusiveMonitorsPass()</line>
<line>// ===============================</line>
<line>// Return TRUE if the Exclusives monitors for the current PE include all of the addresses</line>
<line>// associated with the virtual address region of size bytes starting at address.</line>
<line>// The immediately following memory write must be to the same addresses.</line>
<line></line>
<line link="AArch64.ExclusiveMonitorsPass.2" hover="function: boolean AArch64.ExclusiveMonitorsPass(bits(64) address, integer size)" conts="AArch64.ExclusiveMonitorsPass">boolean <anchor link="AArch64.ExclusiveMonitorsPass.2" hover="function: boolean AArch64.ExclusiveMonitorsPass(bits(64) address, integer size)">AArch64.ExclusiveMonitorsPass</anchor>(bits(64) address, integer size)</line>
<line></line>
<line>    // It is IMPLEMENTATION DEFINED whether the detection of memory aborts happens</line>
<line>    // before or after the check on the local Exclusives monitor. As a result a failure</line>
<line>    // of the local monitor can occur on some implementations even if the memory</line>
<line>    // access would give an memory abort.</line>
<line>    boolean acqrel = FALSE;</line>
<line>    boolean tagchecked = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescExLDST.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescExLDST(MemOp memop, boolean acqrel, boolean tagchecked)">CreateAccDescExLDST</a>(<a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>, acqrel, tagchecked);</line>
<line>    boolean aligned = <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, size);</line>
<line></line>
<line>    if !aligned &amp;&amp; <a link="AArch64.UnalignedAccessFaults.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.UnalignedAccessFaults(AccessDescriptor accdesc, bits(64) address, integer size)">AArch64.UnalignedAccessFaults</a>(accdesc, address, size) then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    if !<a link="AArch64.IsExclusiveVA.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.IsExclusiveVA(bits(64) address, integer processorid, integer size)">AArch64.IsExclusiveVA</a>(address, <a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>(), size) then</line>
<line>        return FALSE;</line>
<line></line>
<line>    memaddrdesc = <a link="AArch64.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch64.TranslateAddress(bits(64) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch64.TranslateAddress</a>(address, accdesc, aligned, size);</line>
<line></line>
<line>    // Check for aborts or debug exceptions</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, memaddrdesc.fault);</line>
<line></line>
<line>    passed = <a link="impl-shared.IsExclusiveLocal.3" file="shared_pseudocode.xml" hover="function: boolean IsExclusiveLocal(FullAddress paddress, integer processorid, integer size)">IsExclusiveLocal</a>(memaddrdesc.paddress, <a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>(), size);</line>
<line>    <a link="impl-shared.ClearExclusiveLocal.1" file="shared_pseudocode.xml" hover="function: ClearExclusiveLocal(integer processorid)">ClearExclusiveLocal</a>(<a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>());</line>
<line></line>
<line>    if passed &amp;&amp; memaddrdesc.memattrs.shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then</line>
<line>        passed = <a link="impl-shared.IsExclusiveGlobal.3" file="shared_pseudocode.xml" hover="function: boolean IsExclusiveGlobal(FullAddress paddress, integer processorid, integer size)">IsExclusiveGlobal</a>(memaddrdesc.paddress, <a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>(), size);</line>
<line></line>
<line>    return passed;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/exclusive/AArch64.IsExclusiveVA" mylink="aarch64.functions.exclusive.AArch64.IsExclusiveVA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.IsExclusiveVA()</line>
<line>// =======================</line>
<line>// An optional IMPLEMENTATION DEFINED test for an exclusive access to a virtual</line>
<line>// address region of size bytes starting at address.</line>
<line>//</line>
<line>// It is permitted (but not required) for this function to return FALSE and</line>
<line>// cause a store exclusive to fail if the virtual address region is not</line>
<line>// totally included within the region recorded by MarkExclusiveVA().</line>
<line>//</line>
<line>// It is always safe to return TRUE which will check the physical address only.</line>
<line></line>
<line link="AArch64.IsExclusiveVA.3" hover="function: boolean AArch64.IsExclusiveVA(bits(64) address, integer processorid, integer size)" conts="AArch64.IsExclusiveVA">boolean <anchor link="AArch64.IsExclusiveVA.3" hover="function: boolean AArch64.IsExclusiveVA(bits(64) address, integer processorid, integer size)">AArch64.IsExclusiveVA</anchor>(bits(64) address, integer processorid, integer size);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/exclusive/AArch64.MarkExclusiveVA" mylink="aarch64.functions.exclusive.AArch64.MarkExclusiveVA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.MarkExclusiveVA()</line>
<line>// =========================</line>
<line>// Optionally record an exclusive access to the virtual address region of size bytes</line>
<line>// starting at address for processorid.</line>
<line></line>
<line link="AArch64.MarkExclusiveVA.3" hover="function: AArch64.MarkExclusiveVA(bits(64) address, integer processorid, integer size)" conts="AArch64.MarkExclusiveVA"><anchor link="AArch64.MarkExclusiveVA.3" hover="function: AArch64.MarkExclusiveVA(bits(64) address, integer processorid, integer size)">AArch64.MarkExclusiveVA</anchor>(bits(64) address, integer processorid, integer size);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/exclusive/AArch64.SetExclusiveMonitors" mylink="aarch64.functions.exclusive.AArch64.SetExclusiveMonitors" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.SetExclusiveMonitors()</line>
<line>// ==============================</line>
<line>// Sets the Exclusives monitors for the current PE to record the addresses associated</line>
<line>// with the virtual address region of size bytes starting at address.</line>
<line></line>
<line link="AArch64.SetExclusiveMonitors.2" hover="function: AArch64.SetExclusiveMonitors(bits(64) address, integer size)" conts="AArch64.SetExclusiveMonitors"><anchor link="AArch64.SetExclusiveMonitors.2" hover="function: AArch64.SetExclusiveMonitors(bits(64) address, integer size)">AArch64.SetExclusiveMonitors</anchor>(bits(64) address, integer size)</line>
<line>    boolean acqrel = FALSE;</line>
<line>    boolean tagchecked = FALSE;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescExLDST.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescExLDST(MemOp memop, boolean acqrel, boolean tagchecked)">CreateAccDescExLDST</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, acqrel, tagchecked);</line>
<line>    boolean aligned = <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, size);</line>
<line></line>
<line>    if !aligned &amp;&amp; <a link="AArch64.UnalignedAccessFaults.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.UnalignedAccessFaults(AccessDescriptor accdesc, bits(64) address, integer size)">AArch64.UnalignedAccessFaults</a>(accdesc, address, size) then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    memaddrdesc = <a link="AArch64.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch64.TranslateAddress(bits(64) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch64.TranslateAddress</a>(address, accdesc, aligned, size);</line>
<line></line>
<line>    // Check for aborts or debug exceptions</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>        return;</line>
<line></line>
<line>    if memaddrdesc.memattrs.shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then</line>
<line>        <a link="impl-shared.MarkExclusiveGlobal.3" file="shared_pseudocode.xml" hover="function: MarkExclusiveGlobal(FullAddress paddress, integer processorid, integer size)">MarkExclusiveGlobal</a>(memaddrdesc.paddress, <a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>(), size);</line>
<line></line>
<line>    <a link="impl-shared.MarkExclusiveLocal.3" file="shared_pseudocode.xml" hover="function: MarkExclusiveLocal(FullAddress paddress, integer processorid, integer size)">MarkExclusiveLocal</a>(memaddrdesc.paddress, <a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>(), size);</line>
<line></line>
<line>    <a link="AArch64.MarkExclusiveVA.3" file="shared_pseudocode.xml" hover="function: AArch64.MarkExclusiveVA(bits(64) address, integer processorid, integer size)">AArch64.MarkExclusiveVA</a>(address, <a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>(), size);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/fusedrstep/FPRSqrtStepFused" mylink="aarch64.functions.fusedrstep.FPRSqrtStepFused" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPRSqrtStepFused()</line>
<line>// ==================</line>
<line></line>
<line link="impl-aarch64.FPRSqrtStepFused.2" hover="function: bits(N) FPRSqrtStepFused(bits(N) op1_in, bits(N) op2)" conts="FPRSqrtStepFused">bits(N) <anchor link="impl-aarch64.FPRSqrtStepFused.2" hover="function: bits(N) FPRSqrtStepFused(bits(N) op1_in, bits(N) op2)">FPRSqrtStepFused</anchor>(bits(N) op1_in, bits(N) op2)</line>
<line>    assert N IN {16, 32, 64};</line>
<line>    bits(N) result;</line>
<line>    bits(N) op1 = op1_in;</line>
<line>    boolean done;</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = FPCR[];</line>
<line>    op1 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(op1);</line>
<line>    boolean altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; fpcr.AH == '1';</line>
<line>    boolean fpexc = !altfp;                         // Generate no floating-point exceptions</line>
<line>    if altfp then fpcr.&lt;FIZ,FZ&gt; = '11';             // Flush denormal input and output to zero</line>
<line>    if altfp then fpcr.RMode = '00';                // Use RNE rounding mode</line>
<line></line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op1, fpcr, fpexc);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op2, fpcr, fpexc);</line>
<line>    (done,result) = <a link="impl-shared.FPProcessNaNs.6" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs(FPType type1, FPType type2, bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)">FPProcessNaNs</a>(type1, type2, op1, op2, fpcr, fpexc);</line>
<line>    <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(fpcr);</line>
<line></line>
<line>    if !done then</line>
<line>        inf1 = (type1 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        inf2 = (type2 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        zero1 = (type1 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line>        zero2 = (type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line></line>
<line>        if (inf1 &amp;&amp; zero2) || (zero1 &amp;&amp; inf2) then</line>
<line>            result = <a link="impl-shared.FPOnePointFive.2" file="shared_pseudocode.xml" hover="function: bits(N) FPOnePointFive(bit sign, integer N)">FPOnePointFive</a>('0', N);</line>
<line>        elsif inf1 || inf2 then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>(sign1 EOR sign2, N);</line>
<line>        else</line>
<line>            // Fully fused multiply-add and halve</line>
<line>            result_value = (3.0 + (value1 * value2)) / 2.0;</line>
<line>            if result_value == 0.0 then</line>
<line>                // Sign of exact zero result depends on rounding mode</line>
<line>                sign = if rounding == <a link="FPRounding_NEGINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_NEGINF</a> then '1' else '0';</line>
<line>                result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign, N);</line>
<line>            else</line>
<line>                result = <a link="impl-shared.FPRound.5" file="shared_pseudocode.xml" hover="function: bits(N) FPRound(real op, FPCRType fpcr_in, FPRounding rounding, boolean fpexc, integer N)">FPRound</a>(result_value, fpcr, rounding, fpexc, N);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/fusedrstep/FPRecipStepFused" mylink="aarch64.functions.fusedrstep.FPRecipStepFused" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPRecipStepFused()</line>
<line>// ==================</line>
<line></line>
<line link="impl-aarch64.FPRecipStepFused.2" hover="function: bits(N) FPRecipStepFused(bits(N) op1_in, bits(N) op2)" conts="FPRecipStepFused">bits(N) <anchor link="impl-aarch64.FPRecipStepFused.2" hover="function: bits(N) FPRecipStepFused(bits(N) op1_in, bits(N) op2)">FPRecipStepFused</anchor>(bits(N) op1_in, bits(N) op2)</line>
<line>    assert N IN {16, 32, 64};</line>
<line>    bits(N) op1 = op1_in;</line>
<line>    bits(N) result;</line>
<line>    boolean done;</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = FPCR[];</line>
<line>    op1 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(op1);</line>
<line></line>
<line>    boolean altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; fpcr.AH == '1';</line>
<line>    boolean fpexc = !altfp;                         // Generate no floating-point exceptions</line>
<line>    if altfp then fpcr.&lt;FIZ,FZ&gt; = '11';             // Flush denormal input and output to zero</line>
<line>    if altfp then fpcr.RMode    = '00';             // Use RNE rounding mode</line>
<line></line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op1, fpcr, fpexc);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op2, fpcr, fpexc);</line>
<line>    (done,result) = <a link="impl-shared.FPProcessNaNs.6" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs(FPType type1, FPType type2, bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)">FPProcessNaNs</a>(type1, type2, op1, op2, fpcr, fpexc);</line>
<line>    <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(fpcr);</line>
<line></line>
<line>    if !done then</line>
<line>        inf1  = (type1 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        inf2  = (type2 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        zero1 = (type1 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line>        zero2 = (type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line></line>
<line>        if (inf1 &amp;&amp; zero2) || (zero1 &amp;&amp; inf2) then</line>
<line>            result = <a link="impl-shared.FPTwo.2" file="shared_pseudocode.xml" hover="function: bits(N) FPTwo(bit sign, integer N)">FPTwo</a>('0', N);</line>
<line>        elsif inf1 || inf2 then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>(sign1 EOR sign2, N);</line>
<line>        else</line>
<line>            // Fully fused multiply-add</line>
<line>            result_value = 2.0 + (value1 * value2);</line>
<line>            if result_value == 0.0 then</line>
<line>                // Sign of exact zero result depends on rounding mode</line>
<line>                sign = if rounding == <a link="FPRounding_NEGINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_NEGINF</a> then '1' else '0';</line>
<line>                result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign, N);</line>
<line>            else</line>
<line>                result = <a link="impl-shared.FPRound.5" file="shared_pseudocode.xml" hover="function: bits(N) FPRound(real op, FPCRType fpcr_in, FPRounding rounding, boolean fpexc, integer N)">FPRound</a>(result_value, fpcr, rounding, fpexc, N);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/AddGCSExRecord" mylink="aarch64.functions.gcs.AddGCSExRecord" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AddGCSExRecord()</line>
<line>// ================</line>
<line>// Generates and then writes an exception record to the</line>
<line>// current Guarded control stack.</line>
<line></line>
<line link="impl-aarch64.AddGCSExRecord.3" hover="function: AddGCSExRecord(bits(64) elr, bits(64) spsr, bits(64) lr)" conts="AddGCSExRecord"><anchor link="impl-aarch64.AddGCSExRecord.3" hover="function: AddGCSExRecord(bits(64) elr, bits(64) spsr, bits(64) lr)">AddGCSExRecord</anchor>(bits(64) elr, bits(64) spsr, bits(64) lr)</line>
<line>    bits(64) ptr;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescGCS.2" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescGCS(bits(2) el, MemOp memop)">CreateAccDescGCS</a>(PSTATE.EL, <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>);</line>
<line></line>
<line>    ptr = <a link="impl-aarch64.GetCurrentGCSPointer.0" file="shared_pseudocode.xml" hover="function: bits(64) GetCurrentGCSPointer()">GetCurrentGCSPointer</a>();</line>
<line></line>
<line>    // Store the record</line>
<line>    Mem[ptr-8, 8, accdesc] = lr;</line>
<line>    Mem[ptr-16, 8, accdesc] = spsr;</line>
<line>    Mem[ptr-24, 8, accdesc] = elr;</line>
<line>    Mem[ptr-32, 8, accdesc] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(60):'1001';</line>
<line></line>
<line>    // Decrement the pointer value</line>
<line>    ptr = ptr - 32;</line>
<line></line>
<line>    <a link="impl-aarch64.SetCurrentGCSPointer.1" file="shared_pseudocode.xml" hover="function: SetCurrentGCSPointer(bits(64) ptr)">SetCurrentGCSPointer</a>(ptr);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/AddGCSRecord" mylink="aarch64.functions.gcs.AddGCSRecord" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AddGCSRecord()</line>
<line>// ==============</line>
<line>// Generates and then writes a record to the current Guarded</line>
<line>// control stack.</line>
<line></line>
<line link="impl-aarch64.AddGCSRecord.1" hover="function: AddGCSRecord(bits(64) vaddress)" conts="AddGCSRecord"><anchor link="impl-aarch64.AddGCSRecord.1" hover="function: AddGCSRecord(bits(64) vaddress)">AddGCSRecord</anchor>(bits(64) vaddress)</line>
<line>    bits(64) ptr;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescGCS.2" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescGCS(bits(2) el, MemOp memop)">CreateAccDescGCS</a>(PSTATE.EL, <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>);</line>
<line></line>
<line>    ptr = <a link="impl-aarch64.GetCurrentGCSPointer.0" file="shared_pseudocode.xml" hover="function: bits(64) GetCurrentGCSPointer()">GetCurrentGCSPointer</a>();</line>
<line></line>
<line>    // Store the record</line>
<line>    Mem[ptr-8, 8, accdesc] = vaddress;</line>
<line></line>
<line>    // Decrement the pointer value</line>
<line>    ptr = ptr - 8;</line>
<line></line>
<line>    <a link="impl-aarch64.SetCurrentGCSPointer.1" file="shared_pseudocode.xml" hover="function: SetCurrentGCSPointer(bits(64) ptr)">SetCurrentGCSPointer</a>(ptr);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/CheckGCSExRecord" mylink="aarch64.functions.gcs.CheckGCSExRecord" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckGCSExRecord()</line>
<line>// ==================</line>
<line>// Validates the provided values against the top entry of the</line>
<line>// current Guarded control stack.</line>
<line></line>
<line link="impl-aarch64.CheckGCSExRecord.4" hover="function: CheckGCSExRecord(bits(64) elr, bits(64) spsr, bits(64) lr, GCSInstruction gcsinst_type)" conts="CheckGCSExRecord"><anchor link="impl-aarch64.CheckGCSExRecord.4" hover="function: CheckGCSExRecord(bits(64) elr, bits(64) spsr, bits(64) lr, GCSInstruction gcsinst_type)">CheckGCSExRecord</anchor>(bits(64) elr, bits(64) spsr, bits(64) lr, <a link="GCSInstruction" file="shared_pseudocode.xml" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstruction</a> gcsinst_type)</line>
<line>    bits(64) ptr;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescGCS.2" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescGCS(bits(2) el, MemOp memop)">CreateAccDescGCS</a>(PSTATE.EL, <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>);</line>
<line>    ptr = <a link="impl-aarch64.GetCurrentGCSPointer.0" file="shared_pseudocode.xml" hover="function: bits(64) GetCurrentGCSPointer()">GetCurrentGCSPointer</a>();</line>
<line></line>
<line>    // Check the lowest doubleword is correctly formatted</line>
<line>    bits(64) recorded_first_dword = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[ptr, 8, accdesc];</line>
<line>    if recorded_first_dword != <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(60):'1001' then</line>
<line>        <a link="impl-aarch64.GCSDataCheckException.1" file="shared_pseudocode.xml" hover="function: GCSDataCheckException(GCSInstruction gcsinst_type)">GCSDataCheckException</a>(gcsinst_type);</line>
<line></line>
<line>    // Check the ELR matches the recorded value</line>
<line>    bits(64) recorded_elr = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[ptr+8, 8, accdesc];</line>
<line>    if recorded_elr != elr then</line>
<line>        <a link="impl-aarch64.GCSDataCheckException.1" file="shared_pseudocode.xml" hover="function: GCSDataCheckException(GCSInstruction gcsinst_type)">GCSDataCheckException</a>(gcsinst_type);</line>
<line></line>
<line>    // Check the SPSR matches the recorded value</line>
<line>    bits(64) recorded_spsr = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[ptr+16, 8, accdesc];</line>
<line>    if recorded_spsr != spsr then</line>
<line>        <a link="impl-aarch64.GCSDataCheckException.1" file="shared_pseudocode.xml" hover="function: GCSDataCheckException(GCSInstruction gcsinst_type)">GCSDataCheckException</a>(gcsinst_type);</line>
<line></line>
<line>    // Check the LR matches the recorded value</line>
<line>    bits(64) recorded_lr = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[ptr+24, 8, accdesc];</line>
<line>    if recorded_lr != lr then</line>
<line>        <a link="impl-aarch64.GCSDataCheckException.1" file="shared_pseudocode.xml" hover="function: GCSDataCheckException(GCSInstruction gcsinst_type)">GCSDataCheckException</a>(gcsinst_type);</line>
<line></line>
<line>    // Increment the pointer value</line>
<line>    ptr = ptr + 32;</line>
<line></line>
<line>    <a link="impl-aarch64.SetCurrentGCSPointer.1" file="shared_pseudocode.xml" hover="function: SetCurrentGCSPointer(bits(64) ptr)">SetCurrentGCSPointer</a>(ptr);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/CheckGCSSTRTrap" mylink="aarch64.functions.gcs.CheckGCSSTRTrap" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckGCSSTRTrap()</line>
<line>// =================</line>
<line>// Trap GCSSTR or GCSSTTR instruction if trapping is enabled.</line>
<line></line>
<line link="impl-aarch64.CheckGCSSTRTrap.0" hover="function: CheckGCSSTRTrap()" conts="CheckGCSSTRTrap"><anchor link="impl-aarch64.CheckGCSSTRTrap.0" hover="function: CheckGCSSTRTrap()">CheckGCSSTRTrap</anchor>()</line>
<line>    case PSTATE.EL of</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>            if GCSCRE0_EL1.STREn == '0' then</line>
<line>                if HCR_EL2.TGE == '0' then</line>
<line>                    <a link="impl-aarch64.GCSSTRTrapException.1" file="shared_pseudocode.xml" hover="function: GCSSTRTrapException(bits(2) target_el)">GCSSTRTrapException</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line>                else</line>
<line>                    <a link="impl-aarch64.GCSSTRTrapException.1" file="shared_pseudocode.xml" hover="function: GCSSTRTrapException(bits(2) target_el)">GCSSTRTrapException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            if GCSCR_EL1.STREn == '0' then</line>
<line>                <a link="impl-aarch64.GCSSTRTrapException.1" file="shared_pseudocode.xml" hover="function: GCSSTRTrapException(bits(2) target_el)">GCSSTRTrapException</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line>            elsif (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; (!<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) || SCR_EL3.FGTEn == '1') &amp;&amp;</line>
<line>                   HFGITR_EL2.nGCSSTR_EL1 == '0') then</line>
<line>                <a link="impl-aarch64.GCSSTRTrapException.1" file="shared_pseudocode.xml" hover="function: GCSSTRTrapException(bits(2) target_el)">GCSSTRTrapException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            if GCSCR_EL2.STREn == '0' then</line>
<line>                <a link="impl-aarch64.GCSSTRTrapException.1" file="shared_pseudocode.xml" hover="function: GCSSTRTrapException(bits(2) target_el)">GCSSTRTrapException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            if GCSCR_EL3.STREn == '0' then</line>
<line>                <a link="impl-aarch64.GCSSTRTrapException.1" file="shared_pseudocode.xml" hover="function: GCSSTRTrapException(bits(2) target_el)">GCSSTRTrapException</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/EXLOCKException" mylink="aarch64.functions.gcs.EXLOCKException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EXLOCKException()</line>
<line>// =================</line>
<line>// Handle an EXLOCK exception condition.</line>
<line></line>
<line link="impl-aarch64.EXLOCKException.0" hover="function: EXLOCKException()" conts="EXLOCKException"><anchor link="impl-aarch64.EXLOCKException.0" hover="function: EXLOCKException()">EXLOCKException</anchor>()</line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    integer vect_offset = 0x0;</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_GCSFail" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_GCSFail</a>);</line>
<line>    exception.syndrome&lt;24&gt; = Zeros();</line>
<line>    exception.syndrome&lt;23:20&gt; = '0001';</line>
<line>    exception.syndrome&lt;19:0&gt; = Zeros();</line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(PSTATE.EL, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/GCSDataCheckException" mylink="aarch64.functions.gcs.GCSDataCheckException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GCSDataCheckException()</line>
<line>// =======================</line>
<line>// Handle a Guarded Control Stack data check fault condition.</line>
<line></line>
<line link="impl-aarch64.GCSDataCheckException.1" hover="function: GCSDataCheckException(GCSInstruction gcsinst_type)" conts="GCSDataCheckException"><anchor link="impl-aarch64.GCSDataCheckException.1" hover="function: GCSDataCheckException(GCSInstruction gcsinst_type)">GCSDataCheckException</anchor>(<a link="GCSInstruction" file="shared_pseudocode.xml" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstruction</a> gcsinst_type)</line>
<line>    bits(2) target_el;</line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    integer vect_offset = 0x0;</line>
<line>    boolean rn_unknown = FALSE;</line>
<line>    boolean is_ret = FALSE;</line>
<line></line>
<line>    if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        target_el = if HCR_EL2.TGE == '0' then <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> else <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>    else</line>
<line>        target_el = PSTATE.EL;</line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_GCSFail" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_GCSFail</a>);</line>
<line>    case gcsinst_type of</line>
<line>        when <a link="GCSInstType_PRET" file="shared_pseudocode.xml" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstType_PRET</a></line>
<line>            exception.syndrome&lt;4:0&gt; = '00000';</line>
<line>            is_ret = TRUE;</line>
<line>        when <a link="GCSInstType_POPM" file="shared_pseudocode.xml" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstType_POPM</a></line>
<line>            exception.syndrome&lt;4:0&gt; = '00001';</line>
<line>        when <a link="GCSInstType_PRETAA" file="shared_pseudocode.xml" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstType_PRETAA</a></line>
<line>            exception.syndrome&lt;4:0&gt; = '00010';</line>
<line>            is_ret = TRUE;</line>
<line>        when <a link="GCSInstType_PRETAB" file="shared_pseudocode.xml" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstType_PRETAB</a></line>
<line>            exception.syndrome&lt;4:0&gt; = '00011';</line>
<line>            is_ret = TRUE;</line>
<line>        when <a link="GCSInstType_SS1" file="shared_pseudocode.xml" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstType_SS1</a></line>
<line>            exception.syndrome&lt;4:0&gt; = '00100';</line>
<line>        when <a link="GCSInstType_SS2" file="shared_pseudocode.xml" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstType_SS2</a></line>
<line>            exception.syndrome&lt;4:0&gt; = '00101';</line>
<line>            rn_unknown = TRUE;</line>
<line>        when <a link="GCSInstType_POPCX" file="shared_pseudocode.xml" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstType_POPCX</a></line>
<line>            rn_unknown = TRUE;</line>
<line>            exception.syndrome&lt;4:0&gt; = '01000';</line>
<line>        when <a link="GCSInstType_POPX" file="shared_pseudocode.xml" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstType_POPX</a></line>
<line>            exception.syndrome&lt;4:0&gt; = '01001';</line>
<line>    if rn_unknown == TRUE then</line>
<line>        exception.syndrome&lt;9:5&gt; = bits(5) UNKNOWN;</line>
<line>    elsif is_ret == TRUE then</line>
<line>        exception.syndrome&lt;9:5&gt; = <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>()&lt;9:5&gt;;</line>
<line>    else</line>
<line>        exception.syndrome&lt;9:5&gt; = <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>()&lt;4:0&gt;;</line>
<line>    exception.syndrome&lt;24:10&gt; = Zeros();</line>
<line>    exception.vaddress = bits(64) UNKNOWN;</line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(target_el, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/GCSEnabled" mylink="aarch64.functions.gcs.GCSEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GCSEnabled()</line>
<line>// ============</line>
<line>// Returns TRUE if the Guarded control stack is enabled at</line>
<line>// the provided Exception level.</line>
<line></line>
<line link="impl-aarch64.GCSEnabled.1" hover="function: boolean GCSEnabled(bits(2) el)" conts="GCSEnabled">boolean <anchor link="impl-aarch64.GCSEnabled.1" hover="function: boolean GCSEnabled(bits(2) el)">GCSEnabled</anchor>(bits(2) el)</line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        return FALSE;</line>
<line></line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; el != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> &amp;&amp; SCR_EL3.GCSEn == '0' then</line>
<line>        return FALSE;</line>
<line></line>
<line>    if (el IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>        (HCR_EL2.TGE == '0' || HCR_EL2.E2H == '0') &amp;&amp;</line>
<line>        (!<a link="impl-aarch64.IsHCRXEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsHCRXEL2Enabled()">IsHCRXEL2Enabled</a>() || HCRX_EL2.GCSEn == '0')) then</line>
<line>        return FALSE;</line>
<line></line>
<line>    return <a link="impl-aarch64.GCSPCRSelected.1" file="shared_pseudocode.xml" hover="function: boolean GCSPCRSelected(bits(2) el)">GCSPCRSelected</a>(el);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/GCSInstruction" mylink="aarch64.functions.gcs.GCSInstruction" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GCSInstruction</line>
<line>// ==============</line>
<line></line>
<line link="GCSInstruction" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }" conts="GCSInstruction">enumeration <anchor link="GCSInstruction" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstruction</anchor> {</line>
<line link="GCSInstType_PRET" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }" conts="GCSInstType_PRET">    <anchor link="GCSInstType_PRET" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstType_PRET</anchor>,    // Procedure return without Pointer authentication</line>
<line link="GCSInstType_POPM" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }" conts="GCSInstType_POPM">    <anchor link="GCSInstType_POPM" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstType_POPM</anchor>,    // GCSPOPM instruction</line>
<line link="GCSInstType_PRETAA" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }" conts="GCSInstType_PRETAA">    <anchor link="GCSInstType_PRETAA" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstType_PRETAA</anchor>,  // Procedure return with Pointer authentication that used key A</line>
<line link="GCSInstType_PRETAB" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }" conts="GCSInstType_PRETAB">    <anchor link="GCSInstType_PRETAB" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstType_PRETAB</anchor>,  // Procedure return with Pointer authentication that used key B</line>
<line link="GCSInstType_SS1" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }" conts="GCSInstType_SS1">    <anchor link="GCSInstType_SS1" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstType_SS1</anchor>,     // GCSSS1 instruction</line>
<line link="GCSInstType_SS2" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }" conts="GCSInstType_SS2">    <anchor link="GCSInstType_SS2" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstType_SS2</anchor>,     // GCSSS2 instruction</line>
<line link="GCSInstType_POPCX" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }" conts="GCSInstType_POPCX">    <anchor link="GCSInstType_POPCX" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstType_POPCX</anchor>,   // GCSPOPCX instruction</line>
<line link="GCSInstType_POPX" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }" conts="GCSInstType_POPX">    <anchor link="GCSInstType_POPX" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstType_POPX</anchor>     // GCSPOPX instruction</line>
<line>};</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/GCSPCREnabled" mylink="aarch64.functions.gcs.GCSPCREnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GCSPCREnabled()</line>
<line>// ===============</line>
<line>// Returns TRUE if the Guarded control stack is PCR enabled</line>
<line>// at the provided Exception level.</line>
<line></line>
<line link="impl-aarch64.GCSPCREnabled.1" hover="function: boolean GCSPCREnabled(bits(2) el)" conts="GCSPCREnabled">boolean <anchor link="impl-aarch64.GCSPCREnabled.1" hover="function: boolean GCSPCREnabled(bits(2) el)">GCSPCREnabled</anchor>(bits(2) el)</line>
<line>    return <a link="impl-aarch64.GCSPCRSelected.1" file="shared_pseudocode.xml" hover="function: boolean GCSPCRSelected(bits(2) el)">GCSPCRSelected</a>(el) &amp;&amp; <a link="impl-aarch64.GCSEnabled.1" file="shared_pseudocode.xml" hover="function: boolean GCSEnabled(bits(2) el)">GCSEnabled</a>(el);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/GCSPCRSelected" mylink="aarch64.functions.gcs.GCSPCRSelected" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GCSPCRSelected()</line>
<line>// ================</line>
<line>// Returns TRUE if the Guarded control stack is PCR selected</line>
<line>// at the provided Exception level.</line>
<line></line>
<line link="impl-aarch64.GCSPCRSelected.1" hover="function: boolean GCSPCRSelected(bits(2) el)" conts="GCSPCRSelected">boolean <anchor link="impl-aarch64.GCSPCRSelected.1" hover="function: boolean GCSPCRSelected(bits(2) el)">GCSPCRSelected</anchor>(bits(2) el)</line>
<line>    case el of</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> return GCSCRE0_EL1.PCRSEL == '1';</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> return GCSCR_EL1.PCRSEL == '1';</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> return GCSCR_EL2.PCRSEL == '1';</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> return GCSCR_EL3.PCRSEL == '1';</line>
<line>    <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>    return TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/GCSPOPCX" mylink="aarch64.functions.gcs.GCSPOPCX" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GCSPOPCX()</line>
<line>// ==========</line>
<line>// Called to pop and compare a Guarded control stack exception return record.</line>
<line></line>
<line link="impl-aarch64.GCSPOPCX.0" hover="function: GCSPOPCX()" conts="GCSPOPCX"><anchor link="impl-aarch64.GCSPOPCX.0" hover="function: GCSPOPCX()">GCSPOPCX</anchor>()</line>
<line>    bits(64) spsr = <a link="impl-shared.SPSR.read.0" file="shared_pseudocode.xml" hover="accessor: bits(N) SPSR[]">SPSR</a>[];</line>
<line>    if !<a link="impl-aarch64.GCSEnabled.1" file="shared_pseudocode.xml" hover="function: boolean GCSEnabled(bits(2) el)">GCSEnabled</a>(PSTATE.EL) then</line>
<line>        <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
<line>    CheckGCSExRecord(ELR[], spsr, X[30,64], GCSInstType_POPCX);</line>
<line>    PSTATE.EXLOCK = '1';</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/GCSPOPM" mylink="aarch64.functions.gcs.GCSPOPM" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GCSPOPM()</line>
<line>// =========</line>
<line>// Called to pop a Guarded control stack procedure return record.</line>
<line></line>
<line link="impl-aarch64.GCSPOPM.0" hover="function: bits(64) GCSPOPM()" conts="GCSPOPM">bits(64) <anchor link="impl-aarch64.GCSPOPM.0" hover="function: bits(64) GCSPOPM()">GCSPOPM</anchor>()</line>
<line>    bits(64) ptr;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescGCS.2" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescGCS(bits(2) el, MemOp memop)">CreateAccDescGCS</a>(PSTATE.EL, <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>);</line>
<line></line>
<line>    if !<a link="impl-aarch64.GCSEnabled.1" file="shared_pseudocode.xml" hover="function: boolean GCSEnabled(bits(2) el)">GCSEnabled</a>(PSTATE.EL) then <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
<line>    ptr = <a link="impl-aarch64.GetCurrentGCSPointer.0" file="shared_pseudocode.xml" hover="function: bits(64) GetCurrentGCSPointer()">GetCurrentGCSPointer</a>();</line>
<line>    bits(64) entry = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[ptr, 8, accdesc];</line>
<line></line>
<line>    if entry&lt;1:0&gt; != '00' then</line>
<line>        <a link="impl-aarch64.GCSDataCheckException.1" file="shared_pseudocode.xml" hover="function: GCSDataCheckException(GCSInstruction gcsinst_type)">GCSDataCheckException</a>(<a link="GCSInstType_POPM" file="shared_pseudocode.xml" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstType_POPM</a>);</line>
<line></line>
<line>    ptr = ptr + 8;</line>
<line>    <a link="impl-aarch64.SetCurrentGCSPointer.1" file="shared_pseudocode.xml" hover="function: SetCurrentGCSPointer(bits(64) ptr)">SetCurrentGCSPointer</a>(ptr);</line>
<line>    return entry;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/GCSPOPX" mylink="aarch64.functions.gcs.GCSPOPX" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GCSPOPX()</line>
<line>// =========</line>
<line>// Called to pop a Guarded control stack exception return record.</line>
<line></line>
<line link="impl-aarch64.GCSPOPX.0" hover="function: GCSPOPX()" conts="GCSPOPX"><anchor link="impl-aarch64.GCSPOPX.0" hover="function: GCSPOPX()">GCSPOPX</anchor>()</line>
<line>    if !<a link="impl-aarch64.GCSEnabled.1" file="shared_pseudocode.xml" hover="function: boolean GCSEnabled(bits(2) el)">GCSEnabled</a>(PSTATE.EL) then <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
<line></line>
<line>    bits(64) ptr;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescGCS.2" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescGCS(bits(2) el, MemOp memop)">CreateAccDescGCS</a>(PSTATE.EL, <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>);</line>
<line>    ptr = <a link="impl-aarch64.GetCurrentGCSPointer.0" file="shared_pseudocode.xml" hover="function: bits(64) GetCurrentGCSPointer()">GetCurrentGCSPointer</a>();</line>
<line></line>
<line>    // Check the lowest doubleword is correctly formatted</line>
<line>    bits(64) recorded_first_dword = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[ptr, 8, accdesc];</line>
<line>    if recorded_first_dword != <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(60):'1001' then</line>
<line>        <a link="impl-aarch64.GCSDataCheckException.1" file="shared_pseudocode.xml" hover="function: GCSDataCheckException(GCSInstruction gcsinst_type)">GCSDataCheckException</a>(<a link="GCSInstType_POPX" file="shared_pseudocode.xml" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstType_POPX</a>);</line>
<line></line>
<line>    // Ignore these loaded values, however they might have</line>
<line>    // faulted which is why we load them anyway</line>
<line>    bits(64) recorded_elr = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[ptr+8, 8, accdesc];</line>
<line>    bits(64) recorded_spsr = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[ptr+16, 8, accdesc];</line>
<line>    bits(64) recorded_lr = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[ptr+24, 8, accdesc];</line>
<line></line>
<line>    // Increment the pointer value</line>
<line>    ptr = ptr + 32;</line>
<line></line>
<line>    <a link="impl-aarch64.SetCurrentGCSPointer.1" file="shared_pseudocode.xml" hover="function: SetCurrentGCSPointer(bits(64) ptr)">SetCurrentGCSPointer</a>(ptr);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/GCSPUSHM" mylink="aarch64.functions.gcs.GCSPUSHM" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GCSPUSHM()</line>
<line>// ==========</line>
<line>// Called to push a Guarded control stack procedure return record.</line>
<line></line>
<line link="impl-aarch64.GCSPUSHM.1" hover="function: GCSPUSHM(bits(64) value)" conts="GCSPUSHM"><anchor link="impl-aarch64.GCSPUSHM.1" hover="function: GCSPUSHM(bits(64) value)">GCSPUSHM</anchor>(bits(64) value)</line>
<line>    if !<a link="impl-aarch64.GCSEnabled.1" file="shared_pseudocode.xml" hover="function: boolean GCSEnabled(bits(2) el)">GCSEnabled</a>(PSTATE.EL) then <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
<line>    <a link="impl-aarch64.AddGCSRecord.1" file="shared_pseudocode.xml" hover="function: AddGCSRecord(bits(64) vaddress)">AddGCSRecord</a>(value);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/GCSPUSHX" mylink="aarch64.functions.gcs.GCSPUSHX" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GCSPUSHX()</line>
<line>// ==========</line>
<line>// Called to push a Guarded control stack exception return record.</line>
<line></line>
<line link="impl-aarch64.GCSPUSHX.0" hover="function: GCSPUSHX()" conts="GCSPUSHX"><anchor link="impl-aarch64.GCSPUSHX.0" hover="function: GCSPUSHX()">GCSPUSHX</anchor>()</line>
<line>    bits(64) spsr = <a link="impl-shared.SPSR.read.0" file="shared_pseudocode.xml" hover="accessor: bits(N) SPSR[]">SPSR</a>[];</line>
<line>    if !<a link="impl-aarch64.GCSEnabled.1" file="shared_pseudocode.xml" hover="function: boolean GCSEnabled(bits(2) el)">GCSEnabled</a>(PSTATE.EL) then</line>
<line>        <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
<line>    AddGCSExRecord(ELR[], spsr, X[30,64]);</line>
<line>    PSTATE.EXLOCK = '0';</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/GCSReturnValueCheckEnabled" mylink="aarch64.functions.gcs.GCSReturnValueCheckEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GCSReturnValueCheckEnabled()</line>
<line>// ============================</line>
<line>// Returns TRUE if the Guarded control stack has return value</line>
<line>// checking enabled at the current Exception level.</line>
<line></line>
<line link="impl-aarch64.GCSReturnValueCheckEnabled.1" hover="function: boolean GCSReturnValueCheckEnabled(bits(2) el)" conts="GCSReturnValueCheckEnabled">boolean <anchor link="impl-aarch64.GCSReturnValueCheckEnabled.1" hover="function: boolean GCSReturnValueCheckEnabled(bits(2) el)">GCSReturnValueCheckEnabled</anchor>(bits(2) el)</line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        return FALSE;</line>
<line>    case el of</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> return GCSCRE0_EL1.RVCHKEN == '1';</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> return GCSCR_EL1.RVCHKEN == '1';</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> return GCSCR_EL2.RVCHKEN == '1';</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> return GCSCR_EL3.RVCHKEN == '1';</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/GCSSS1" mylink="aarch64.functions.gcs.GCSSS1" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GCSSS1()</line>
<line>// ========</line>
<line>// Operational pseudocode for GCSSS1 instruction.</line>
<line></line>
<line link="impl-aarch64.GCSSS1.1" hover="function: GCSSS1(bits(64) incoming_pointer)" conts="GCSSS1"><anchor link="impl-aarch64.GCSSS1.1" hover="function: GCSSS1(bits(64) incoming_pointer)">GCSSS1</anchor>(bits(64) incoming_pointer)</line>
<line>    bits(64) outgoing_pointer, incoming_value, in_progress_entry;</line>
<line>    if !<a link="impl-aarch64.GCSEnabled.1" file="shared_pseudocode.xml" hover="function: boolean GCSEnabled(bits(2) el)">GCSEnabled</a>(PSTATE.EL) then <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescGCSSS1.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescGCSSS1(bits(2) el)">CreateAccDescGCSSS1</a>(PSTATE.EL);</line>
<line>    outgoing_pointer = <a link="impl-aarch64.GetCurrentGCSPointer.0" file="shared_pseudocode.xml" hover="function: bits(64) GetCurrentGCSPointer()">GetCurrentGCSPointer</a>();</line>
<line></line>
<line>    boolean aligned = <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(incoming_pointer, 8);</line>
<line>    if !aligned then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(incoming_pointer, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc = <a link="AArch64.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch64.TranslateAddress(bits(64) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch64.TranslateAddress</a>(incoming_pointer, accdesc,</line>
<line>                                                             aligned, 64);</line>
<line></line>
<line>    // Check for aborts or debug exceptions</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(incoming_pointer, memaddrdesc.fault);</line>
<line></line>
<line>    // Effect on exclusives</line>
<line>    if memaddrdesc.memattrs.shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then</line>
<line>        <a link="impl-shared.ClearExclusiveByAddress.3" file="shared_pseudocode.xml" hover="function: ClearExclusiveByAddress(FullAddress paddress, integer processorid, integer size)">ClearExclusiveByAddress</a>(memaddrdesc.paddress, <a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>(), 64);</line>
<line></line>
<line>    <a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> memstatus;</line>
<line>    (memstatus, incoming_value) = <a link="impl-shared.PhysMemRead.3" file="shared_pseudocode.xml" hover="function: (PhysMemRetStatus, bits(8*size)) PhysMemRead(AddressDescriptor desc, integer size, AccessDescriptor accdesc)">PhysMemRead</a>(memaddrdesc, 8, accdesc);</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>        <a link="impl-shared.HandleExternalReadAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalReadAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalReadAbort</a>(memstatus, memaddrdesc, 8, accdesc);</line>
<line>    if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(accdesc.acctype) then</line>
<line>        incoming_value = <a link="impl-shared.BigEndianReverse.1" file="shared_pseudocode.xml" hover="function: bits(width) BigEndianReverse (bits(width) value)">BigEndianReverse</a>(incoming_value);</line>
<line></line>
<line>    if incoming_value == incoming_pointer[63:12]:'000000000001' then   // valid entry</line>
<line>        in_progress_entry = outgoing_pointer[63:3]:'101';    //in_progress_token</line>
<line>        if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(accdesc.acctype) then</line>
<line>            in_progress_entry = <a link="impl-shared.BigEndianReverse.1" file="shared_pseudocode.xml" hover="function: bits(width) BigEndianReverse (bits(width) value)">BigEndianReverse</a>(in_progress_entry);</line>
<line>        memstatus = <a link="impl-shared.PhysMemWrite.4" file="shared_pseudocode.xml" hover="function: PhysMemRetStatus PhysMemWrite(AddressDescriptor desc, integer size, AccessDescriptor accdesc, bits(8*size) value)">PhysMemWrite</a>(memaddrdesc, 8, accdesc, in_progress_entry);</line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>            <a link="impl-shared.HandleExternalReadAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalReadAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalReadAbort</a>(memstatus, memaddrdesc, 8, accdesc);</line>
<line>        <a link="impl-aarch64.SetCurrentGCSPointer.1" file="shared_pseudocode.xml" hover="function: SetCurrentGCSPointer(bits(64) ptr)">SetCurrentGCSPointer</a>(incoming_pointer[63:3]:'000');</line>
<line>    else</line>
<line>        <a link="impl-aarch64.GCSDataCheckException.1" file="shared_pseudocode.xml" hover="function: GCSDataCheckException(GCSInstruction gcsinst_type)">GCSDataCheckException</a>(<a link="GCSInstType_SS1" file="shared_pseudocode.xml" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstType_SS1</a>);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/GCSSS2" mylink="aarch64.functions.gcs.GCSSS2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GCSSS2()</line>
<line>// ========</line>
<line>// Operational pseudocode for GCSSS2 instruction.</line>
<line></line>
<line link="impl-aarch64.GCSSS2.0" hover="function: bits(64) GCSSS2()" conts="GCSSS2">bits(64) <anchor link="impl-aarch64.GCSSS2.0" hover="function: bits(64) GCSSS2()">GCSSS2</anchor>()</line>
<line>    bits(64) outgoing_pointer, incoming_pointer, outgoing_value;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc_ld = <a link="impl-shared.CreateAccDescGCS.2" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescGCS(bits(2) el, MemOp memop)">CreateAccDescGCS</a>(PSTATE.EL, <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>);</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc_st = <a link="impl-shared.CreateAccDescGCS.2" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescGCS(bits(2) el, MemOp memop)">CreateAccDescGCS</a>(PSTATE.EL, <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>);</line>
<line>    if !<a link="impl-aarch64.GCSEnabled.1" file="shared_pseudocode.xml" hover="function: boolean GCSEnabled(bits(2) el)">GCSEnabled</a>(PSTATE.EL) then <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
<line>    incoming_pointer = <a link="impl-aarch64.GetCurrentGCSPointer.0" file="shared_pseudocode.xml" hover="function: bits(64) GetCurrentGCSPointer()">GetCurrentGCSPointer</a>();</line>
<line>    outgoing_value = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[incoming_pointer, 8, accdesc_ld];</line>
<line></line>
<line>    if outgoing_value[2:0] == '101' then  //in_progress token</line>
<line>        outgoing_pointer[63:3] = outgoing_value[63:3] - 1;</line>
<line>        outgoing_pointer[2:0] = '000';</line>
<line>        outgoing_value = outgoing_pointer[63:12]: '000000000001';</line>
<line>        Mem[outgoing_pointer, 8, accdesc_st] = outgoing_value;</line>
<line>        <a link="impl-aarch64.SetCurrentGCSPointer.1" file="shared_pseudocode.xml" hover="function: SetCurrentGCSPointer(bits(64) ptr)">SetCurrentGCSPointer</a>(incoming_pointer + 8);</line>
<line>        <a link="impl-aarch64.GCSSynchronizationBarrier.0" file="shared_pseudocode.xml" hover="function: GCSSynchronizationBarrier()">GCSSynchronizationBarrier</a>();</line>
<line>    else</line>
<line>        <a link="impl-aarch64.GCSDataCheckException.1" file="shared_pseudocode.xml" hover="function: GCSDataCheckException(GCSInstruction gcsinst_type)">GCSDataCheckException</a>(<a link="GCSInstType_SS2" file="shared_pseudocode.xml" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstType_SS2</a>);</line>
<line>    return outgoing_pointer;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/GCSSTRTrapException" mylink="aarch64.functions.gcs.GCSSTRTrapException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GCSSTRTrapException()</line>
<line>// =====================</line>
<line>// Handle a trap on GCSSTR instruction condition.</line>
<line></line>
<line link="impl-aarch64.GCSSTRTrapException.1" hover="function: GCSSTRTrapException(bits(2) target_el)" conts="GCSSTRTrapException"><anchor link="impl-aarch64.GCSSTRTrapException.1" hover="function: GCSSTRTrapException(bits(2) target_el)">GCSSTRTrapException</anchor>(bits(2) target_el)</line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    integer vect_offset = 0x0;</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_GCSFail" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_GCSFail</a>);</line>
<line>    exception.syndrome&lt;24&gt; = Zeros();</line>
<line>    exception.syndrome&lt;23:20&gt; = '0010';</line>
<line>    exception.syndrome&lt;19:15&gt; = Zeros();</line>
<line>    exception.syndrome&lt;14:10&gt; = <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>()&lt;9:5&gt;;</line>
<line>    exception.syndrome&lt;9:5&gt; = <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>()&lt;4:0&gt;;</line>
<line>    exception.syndrome&lt;4:0&gt; = Zeros();</line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(target_el, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/GCSSynchronizationBarrier" mylink="aarch64.functions.gcs.GCSSynchronizationBarrier" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GCSSynchronizationBarrier()</line>
<line>// ===========================</line>
<line>// Barrier instruction that synchronizes Guarded Control Stack</line>
<line>// accesses in relation to other load and store accesses</line>
<line></line>
<line link="impl-aarch64.GCSSynchronizationBarrier.0" hover="function: GCSSynchronizationBarrier()" conts="GCSSynchronizationBarrier"><anchor link="impl-aarch64.GCSSynchronizationBarrier.0" hover="function: GCSSynchronizationBarrier()">GCSSynchronizationBarrier</anchor>();</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/GetCurrentEXLOCKEN" mylink="aarch64.functions.gcs.GetCurrentEXLOCKEN" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GetCurrentEXLOCKEN()</line>
<line>// ====================</line>
<line></line>
<line link="impl-aarch64.GetCurrentEXLOCKEN.0" hover="function: boolean GetCurrentEXLOCKEN()" conts="GetCurrentEXLOCKEN">boolean <anchor link="impl-aarch64.GetCurrentEXLOCKEN.0" hover="function: boolean GetCurrentEXLOCKEN()">GetCurrentEXLOCKEN</anchor>()</line>
<line>    case PSTATE.EL of</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            return GCSCR_EL1.EXLOCKEN == '1';</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            return GCSCR_EL2.EXLOCKEN == '1';</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            return GCSCR_EL3.EXLOCKEN == '1';</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/GetCurrentGCSPointer" mylink="aarch64.functions.gcs.GetCurrentGCSPointer" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GetCurrentGCSPointer()</line>
<line>// ======================</line>
<line>// Returns the value of the current Guarded control stack</line>
<line>// pointer register.</line>
<line></line>
<line link="impl-aarch64.GetCurrentGCSPointer.0" hover="function: bits(64) GetCurrentGCSPointer()" conts="GetCurrentGCSPointer">bits(64) <anchor link="impl-aarch64.GetCurrentGCSPointer.0" hover="function: bits(64) GetCurrentGCSPointer()">GetCurrentGCSPointer</anchor>()</line>
<line>    bits(64) ptr;</line>
<line></line>
<line>    case PSTATE.EL of</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>            ptr = GCSPR_EL0.PTR:'000';</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            ptr = GCSPR_EL1.PTR:'000';</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            ptr = GCSPR_EL2.PTR:'000';</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            ptr = GCSPR_EL3.PTR:'000';</line>
<line>    return ptr;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/LoadCheckGCSRecord" mylink="aarch64.functions.gcs.LoadCheckGCSRecord" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// LoadCheckGCSRecord()</line>
<line>// ====================</line>
<line>// Validates the provided address against the top entry of the</line>
<line>// current Guarded control stack.</line>
<line></line>
<line link="impl-aarch64.LoadCheckGCSRecord.2" hover="function: bits(64) LoadCheckGCSRecord(bits(64) vaddress, GCSInstruction gcsinst_type)" conts="LoadCheckGCSRecord">bits(64) <anchor link="impl-aarch64.LoadCheckGCSRecord.2" hover="function: bits(64) LoadCheckGCSRecord(bits(64) vaddress, GCSInstruction gcsinst_type)">LoadCheckGCSRecord</anchor>(bits(64) vaddress, <a link="GCSInstruction" file="shared_pseudocode.xml" hover="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }">GCSInstruction</a> gcsinst_type)</line>
<line>    bits(64) ptr;</line>
<line>    bits(64) recorded_va;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescGCS.2" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescGCS(bits(2) el, MemOp memop)">CreateAccDescGCS</a>(PSTATE.EL, <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>);</line>
<line></line>
<line>    ptr = <a link="impl-aarch64.GetCurrentGCSPointer.0" file="shared_pseudocode.xml" hover="function: bits(64) GetCurrentGCSPointer()">GetCurrentGCSPointer</a>();</line>
<line>    recorded_va = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[ptr, 8, accdesc];</line>
<line>    if <a link="impl-aarch64.GCSReturnValueCheckEnabled.1" file="shared_pseudocode.xml" hover="function: boolean GCSReturnValueCheckEnabled(bits(2) el)">GCSReturnValueCheckEnabled</a>(PSTATE.EL) &amp;&amp; (recorded_va != vaddress) then</line>
<line>        <a link="impl-aarch64.GCSDataCheckException.1" file="shared_pseudocode.xml" hover="function: GCSDataCheckException(GCSInstruction gcsinst_type)">GCSDataCheckException</a>(gcsinst_type);</line>
<line></line>
<line>    return recorded_va;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/gcs/SetCurrentGCSPointer" mylink="aarch64.functions.gcs.SetCurrentGCSPointer" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SetCurrentGCSPointer()</line>
<line>// ======================</line>
<line>// Writes a value to the current Guarded control stack pointer register.</line>
<line></line>
<line link="impl-aarch64.SetCurrentGCSPointer.1" hover="function: SetCurrentGCSPointer(bits(64) ptr)" conts="SetCurrentGCSPointer"><anchor link="impl-aarch64.SetCurrentGCSPointer.1" hover="function: SetCurrentGCSPointer(bits(64) ptr)">SetCurrentGCSPointer</anchor>(bits(64) ptr)</line>
<line>    case PSTATE.EL of</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>            GCSPR_EL0.PTR = ptr&lt;63:3&gt;;</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            GCSPR_EL1.PTR = ptr&lt;63:3&gt;;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            GCSPR_EL2.PTR = ptr&lt;63:3&gt;;</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            GCSPR_EL3.PTR = ptr&lt;63:3&gt;;</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mec/AArch64.S1AMECFault" mylink="aarch64.functions.mec.AArch64.S1AMECFault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1AMECFault()</line>
<line>// =====================</line>
<line>// Returns TRUE if a Translation fault should occur for Realm EL2 and Realm EL2&amp;0</line>
<line>// stage 1 translated addresses to Realm PA space.</line>
<line></line>
<line>boolean AArch64.S1AMECFault(S1TTWParams walkparams, <a link="PASpace" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PASpace</a> paspace, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime,</line>
<line>                            bits(N) descriptor)</line>
<line>    assert N IN {64,128};</line>
<line>    bit descriptor_amec = if walkparams.d128 == '1' then descriptor&lt;103&gt; else descriptor&lt;63&gt;;</line>
<line></line>
<line>    return (walkparams.&lt;emec,amec&gt; == '10' &amp;&amp;</line>
<line>            regime IN {<a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>, <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a>} &amp;&amp;</line>
<line>            paspace == <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a> &amp;&amp;</line>
<line>            descriptor_amec == '1');</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mec/AArch64.S1DisabledOutputMECID" mylink="aarch64.functions.mec.AArch64.S1DisabledOutputMECID" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1DisabledOutputMECID()</line>
<line>// ===============================</line>
<line>// Returns the output MECID when stage 1 address translation is disabled.</line>
<line></line>
<line>bits(16) AArch64.S1DisabledOutputMECID(S1TTWParams walkparams, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, <a link="PASpace" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PASpace</a> paspace)</line>
<line>    if walkparams.emec == '0' then</line>
<line>        return <a link="DEFAULT_MECID" file="shared_pseudocode.xml" hover="constant bits(16) DEFAULT_MECID = Zeros(16)">DEFAULT_MECID</a>;</line>
<line></line>
<line>    if !(regime IN {<a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>, <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a>, <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a>}) then</line>
<line>        return <a link="DEFAULT_MECID" file="shared_pseudocode.xml" hover="constant bits(16) DEFAULT_MECID = Zeros(16)">DEFAULT_MECID</a>;</line>
<line></line>
<line>    if paspace != <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a> then</line>
<line>        return <a link="DEFAULT_MECID" file="shared_pseudocode.xml" hover="constant bits(16) DEFAULT_MECID = Zeros(16)">DEFAULT_MECID</a>;</line>
<line></line>
<line>    if regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> then</line>
<line>        return VMECID_P_EL2.MECID;</line>
<line>    else</line>
<line>        return MECID_P0_EL2.MECID;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mec/AArch64.S1OutputMECID" mylink="aarch64.functions.mec.AArch64.S1OutputMECID" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1OutputMECID()</line>
<line>// =======================</line>
<line>// Returns the output MECID when stage 1 address translation is enabled.</line>
<line></line>
<line>bits(16) AArch64.S1OutputMECID(S1TTWParams walkparams, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, <a link="VARange" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange</a> varange,</line>
<line>                               <a link="PASpace" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PASpace</a> paspace, bits(N) descriptor)</line>
<line>    assert N IN {64,128};</line>
<line></line>
<line>    if walkparams.emec == '0' then</line>
<line>        return <a link="DEFAULT_MECID" file="shared_pseudocode.xml" hover="constant bits(16) DEFAULT_MECID = Zeros(16)">DEFAULT_MECID</a>;</line>
<line></line>
<line>    if paspace != <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a> then</line>
<line>        return <a link="DEFAULT_MECID" file="shared_pseudocode.xml" hover="constant bits(16) DEFAULT_MECID = Zeros(16)">DEFAULT_MECID</a>;</line>
<line></line>
<line>    bit descriptor_amec = if walkparams.d128 == '1' then descriptor&lt;103&gt; else descriptor&lt;63&gt;;</line>
<line>    case regime of</line>
<line>        when <a link="Regime_EL3" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL3</a></line>
<line>            return MECID_RL_A_EL3.MECID;</line>
<line>        when <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a></line>
<line>            if descriptor_amec == '0' then</line>
<line>                return MECID_P0_EL2.MECID;</line>
<line>            else</line>
<line>                return MECID_A0_EL2.MECID;</line>
<line>        when <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a></line>
<line>            if varange == <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a> then</line>
<line>                if descriptor_amec == '0' then</line>
<line>                    return MECID_P0_EL2.MECID;</line>
<line>                else</line>
<line>                    return MECID_A0_EL2.MECID;</line>
<line>            else</line>
<line>                if descriptor_amec == '0' then</line>
<line>                    return MECID_P1_EL2.MECID;</line>
<line>                else</line>
<line>                    return MECID_A1_EL2.MECID;</line>
<line>        when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a></line>
<line>            return VMECID_P_EL2.MECID;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mec/AArch64.S2OutputMECID" mylink="aarch64.functions.mec.AArch64.S2OutputMECID" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S2OutputMECID()</line>
<line>// =======================</line>
<line>// Returns the output MECID for stage 2 address translation.</line>
<line></line>
<line>bits(16) AArch64.S2OutputMECID(S2TTWParams walkparams, <a link="PASpace" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PASpace</a> paspace, bits(N) descriptor)</line>
<line>    assert N IN {64,128};</line>
<line></line>
<line>    if walkparams.emec == '0' then</line>
<line>        return <a link="DEFAULT_MECID" file="shared_pseudocode.xml" hover="constant bits(16) DEFAULT_MECID = Zeros(16)">DEFAULT_MECID</a>;</line>
<line></line>
<line>    if paspace != <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a> then</line>
<line>        return <a link="DEFAULT_MECID" file="shared_pseudocode.xml" hover="constant bits(16) DEFAULT_MECID = Zeros(16)">DEFAULT_MECID</a>;</line>
<line></line>
<line>    bit descriptor_amec = if walkparams.d128 == '1' then descriptor&lt;103&gt; else descriptor&lt;63&gt;;</line>
<line>    if descriptor_amec == '0' then</line>
<line>        return VMECID_P_EL2.MECID;</line>
<line>    else</line>
<line>        return VMECID_A_EL2.MECID;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mec/AArch64.TTWalkMECID" mylink="aarch64.functions.mec.AArch64.TTWalkMECID" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TTWalkMECID()</line>
<line>// =====================</line>
<line>// Returns the associated MECID for the translation table walk of the given</line>
<line>// translation regime and Security state.</line>
<line></line>
<line link="AArch64.TTWalkMECID.3" hover="function: bits(16) AArch64.TTWalkMECID(bit emec, Regime regime, SecurityState ss)" conts="AArch64.TTWalkMECID">bits(16) <anchor link="AArch64.TTWalkMECID.3" hover="function: bits(16) AArch64.TTWalkMECID(bit emec, Regime regime, SecurityState ss)">AArch64.TTWalkMECID</anchor>(bit emec, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss)</line>
<line>    if emec == '0' then</line>
<line>        return <a link="DEFAULT_MECID" file="shared_pseudocode.xml" hover="constant bits(16) DEFAULT_MECID = Zeros(16)">DEFAULT_MECID</a>;</line>
<line></line>
<line>    if ss != <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a> then</line>
<line>        return <a link="DEFAULT_MECID" file="shared_pseudocode.xml" hover="constant bits(16) DEFAULT_MECID = Zeros(16)">DEFAULT_MECID</a>;</line>
<line></line>
<line>    case regime of</line>
<line>        when <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a></line>
<line>            return MECID_P0_EL2.MECID;</line>
<line>        when <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a></line>
<line>            if TCR_EL2.A1 == '0' then</line>
<line>                return MECID_P1_EL2.MECID;</line>
<line>            else</line>
<line>                return MECID_P0_EL2.MECID;</line>
<line>        // This applies to stage 1 and stage 2 translation table walks for</line>
<line>        // Realm EL1&amp;0, but the stage 2 translation for a stage 1 walk</line>
<line>        // might later override the MECID according to AMEC configuration.</line>
<line>        when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a></line>
<line>            return VMECID_P_EL2.MECID;</line>
<line>        otherwise</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mec/DEFAULT_MECID" mylink="aarch64.functions.mec.DEFAULT_MECID" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="DEFAULT_MECID" hover="constant bits(16) DEFAULT_MECID = Zeros(16)" conts="DEFAULT_MECID">constant bits(16) <anchor link="DEFAULT_MECID" hover="constant bits(16) DEFAULT_MECID = Zeros(16)">DEFAULT_MECID</anchor> = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/AArch64.AccessIsTagChecked" mylink="aarch64.functions.memory.AArch64.AccessIsTagChecked" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.AccessIsTagChecked()</line>
<line>// ============================</line>
<line>// TRUE if a given access is tag-checked, FALSE otherwise.</line>
<line></line>
<line link="AArch64.AccessIsTagChecked.2" hover="function: boolean AArch64.AccessIsTagChecked(bits(64) vaddr, AccessDescriptor accdesc)" conts="AArch64.AccessIsTagChecked">boolean <anchor link="AArch64.AccessIsTagChecked.2" hover="function: boolean AArch64.AccessIsTagChecked(bits(64) vaddr, AccessDescriptor accdesc)">AArch64.AccessIsTagChecked</anchor>(bits(64) vaddr, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    assert accdesc.tagchecked;</line>
<line></line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        return FALSE;</line>
<line></line>
<line>    boolean is_instr = FALSE;</line>
<line>    if (<a link="impl-shared.EffectiveMTX.3" file="shared_pseudocode.xml" hover="function: bit EffectiveMTX(bits(64) address, boolean is_instr, bits(2) el)">EffectiveMTX</a>(vaddr, is_instr, PSTATE.EL) == '0' &amp;&amp;</line>
<line>        <a link="impl-shared.EffectiveTBI.3" file="shared_pseudocode.xml" hover="function: bit EffectiveTBI(bits(64) address, boolean IsInstr, bits(2) el)">EffectiveTBI</a>(vaddr, is_instr, PSTATE.EL) == '0') then</line>
<line>        return FALSE;</line>
<line></line>
<line>    if (<a link="impl-shared.EffectiveTCMA.2" file="shared_pseudocode.xml" hover="function: bit EffectiveTCMA(bits(64) address, bits(2) el)">EffectiveTCMA</a>(vaddr, PSTATE.EL) == '1' &amp;&amp;</line>
<line>            (vaddr&lt;59:55&gt; == '00000' || vaddr&lt;59:55&gt; == '11111')) then</line>
<line>        return FALSE;</line>
<line></line>
<line>    if !<a link="AArch64.AllocationTagAccessIsEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.AllocationTagAccessIsEnabled(bits(2) el)">AArch64.AllocationTagAccessIsEnabled</a>(accdesc.el) then</line>
<line>        return FALSE;</line>
<line></line>
<line>    if PSTATE.TCO=='1' then</line>
<line>        return FALSE;</line>
<line></line>
<line>    if <a link="impl-shared.HaveMTEStoreOnlyExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEStoreOnlyExt()">HaveMTEStoreOnlyExt</a>() &amp;&amp; !accdesc.write &amp;&amp; <a link="impl-aarch64.StoreOnlyTagCheckingEnabled.0" file="shared_pseudocode.xml" hover="function: boolean StoreOnlyTagCheckingEnabled()">StoreOnlyTagCheckingEnabled</a>() then</line>
<line>        return FALSE;</line>
<line></line>
<line>    return TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/AArch64.AddressWithAllocationTag" mylink="aarch64.functions.memory.AArch64.AddressWithAllocationTag" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.AddressWithAllocationTag()</line>
<line>// ==================================</line>
<line>// Generate a 64-bit value containing a Logical Address Tag from a 64-bit</line>
<line>// virtual address and an Allocation Tag.</line>
<line>// If the extension is disabled, treats the Allocation Tag as '0000'.</line>
<line></line>
<line link="AArch64.AddressWithAllocationTag.2" hover="function: bits(64) AArch64.AddressWithAllocationTag(bits(64) address, bits(4) allocation_tag)" conts="AArch64.AddressWithAllocationTag">bits(64) <anchor link="AArch64.AddressWithAllocationTag.2" hover="function: bits(64) AArch64.AddressWithAllocationTag(bits(64) address, bits(4) allocation_tag)">AArch64.AddressWithAllocationTag</anchor>(bits(64) address, bits(4) allocation_tag)</line>
<line>    bits(64) result = address;</line>
<line>    bits(4) tag;</line>
<line>    if <a link="AArch64.AllocationTagAccessIsEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.AllocationTagAccessIsEnabled(bits(2) el)">AArch64.AllocationTagAccessIsEnabled</a>(PSTATE.EL) then</line>
<line>        tag = allocation_tag;</line>
<line>    else</line>
<line>        tag = '0000';</line>
<line>    result&lt;59:56&gt; = tag;</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/AArch64.AllocationTagCheck" mylink="aarch64.functions.memory.AArch64.AllocationTagCheck" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.AllocationTagCheck()</line>
<line>// ============================</line>
<line>// Performs an Allocation Tag Check operation for a memory access and</line>
<line>// returns whether the check passed.</line>
<line></line>
<line link="AArch64.AllocationTagCheck.3" hover="function: boolean AArch64.AllocationTagCheck(AddressDescriptor memaddrdesc, AccessDescriptor accdesc, bits(4) ptag)" conts="AArch64.AllocationTagCheck">boolean <anchor link="AArch64.AllocationTagCheck.3" hover="function: boolean AArch64.AllocationTagCheck(AddressDescriptor memaddrdesc, AccessDescriptor accdesc, bits(4) ptag)">AArch64.AllocationTagCheck</anchor>(<a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc,</line>
<line>                                   bits(4) ptag)</line>
<line>    if memaddrdesc.memattrs.tags == <a link="MemTag_AllocationTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_AllocationTagged</a> then</line>
<line>        (memstatus, readtag) = <a link="impl-aarch64.PhysMemTagRead.2" file="shared_pseudocode.xml" hover="function: (PhysMemRetStatus, bits(4)) PhysMemTagRead(AddressDescriptor desc, AccessDescriptor accdesc)">PhysMemTagRead</a>(memaddrdesc, accdesc);</line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>            <a link="impl-shared.HandleExternalReadAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalReadAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalReadAbort</a>(memstatus, memaddrdesc, 1, accdesc);</line>
<line></line>
<line>        return ptag == readtag;</line>
<line>    else</line>
<line>        return TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/AArch64.AllocationTagFromAddress" mylink="aarch64.functions.memory.AArch64.AllocationTagFromAddress" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.AllocationTagFromAddress()</line>
<line>// ==================================</line>
<line>// Generate an Allocation Tag from a 64-bit value containing a Logical Address Tag.</line>
<line></line>
<line link="AArch64.AllocationTagFromAddress.1" hover="function: bits(4) AArch64.AllocationTagFromAddress(bits(64) tagged_address)" conts="AArch64.AllocationTagFromAddress">bits(4) <anchor link="AArch64.AllocationTagFromAddress.1" hover="function: bits(4) AArch64.AllocationTagFromAddress(bits(64) tagged_address)">AArch64.AllocationTagFromAddress</anchor>(bits(64) tagged_address)</line>
<line>    return tagged_address&lt;59:56&gt;;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/AArch64.CanonicalTagCheck" mylink="aarch64.functions.memory.AArch64.CanonicalTagCheck" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.CanonicalTagCheck()</line>
<line>// ===========================</line>
<line>// Performs a Canonical Tag Check operation for a memory access and</line>
<line>// returns whether the check passed.</line>
<line></line>
<line link="AArch64.CanonicalTagCheck.2" hover="function: boolean AArch64.CanonicalTagCheck(AddressDescriptor memaddrdesc, bits(4) ptag)" conts="AArch64.CanonicalTagCheck">boolean <anchor link="AArch64.CanonicalTagCheck.2" hover="function: boolean AArch64.CanonicalTagCheck(AddressDescriptor memaddrdesc, bits(4) ptag)">AArch64.CanonicalTagCheck</anchor>(<a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc, bits(4) ptag)</line>
<line>    expected_tag = if memaddrdesc.vaddress&lt;55&gt; == '0' then '0000' else '1111';</line>
<line>    return ptag == expected_tag;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/AArch64.CheckTag" mylink="aarch64.functions.memory.AArch64.CheckTag" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.CheckTag()</line>
<line>// ==================</line>
<line>// Performs a Tag Check operation for a memory access and returns</line>
<line>// whether the check passed</line>
<line></line>
<line link="AArch64.CheckTag.3" hover="function: boolean AArch64.CheckTag(AddressDescriptor memaddrdesc, AccessDescriptor accdesc, bits(4) ptag)" conts="AArch64.CheckTag">boolean <anchor link="AArch64.CheckTag.3" hover="function: boolean AArch64.CheckTag(AddressDescriptor memaddrdesc, AccessDescriptor accdesc, bits(4) ptag)">AArch64.CheckTag</anchor>(<a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, bits(4) ptag)</line>
<line>    if memaddrdesc.memattrs.tags == <a link="MemTag_AllocationTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_AllocationTagged</a> then</line>
<line>        return <a link="AArch64.AllocationTagCheck.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.AllocationTagCheck(AddressDescriptor memaddrdesc, AccessDescriptor accdesc, bits(4) ptag)">AArch64.AllocationTagCheck</a>(memaddrdesc, accdesc, ptag);</line>
<line>    elsif memaddrdesc.memattrs.tags == <a link="MemTag_CanonicallyTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_CanonicallyTagged</a> then</line>
<line>        return <a link="AArch64.CanonicalTagCheck.2" file="shared_pseudocode.xml" hover="function: boolean AArch64.CanonicalTagCheck(AddressDescriptor memaddrdesc, bits(4) ptag)">AArch64.CanonicalTagCheck</a>(memaddrdesc, ptag);</line>
<line>    else</line>
<line>        return TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/AArch64.MemSingle" mylink="aarch64.functions.memory.AArch64.MemSingle" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.MemSingle[] - non-assignment (read) form</line>
<line>// ================================================</line>
<line>// Perform an atomic, little-endian read of 'size' bytes.</line>
<line></line>
<line link="AArch64.MemSingle.read.4" hover="accessor: bits(size*8) AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc, boolean aligned]" conts="AArch64.MemSingle">bits(size*8) <anchor link="AArch64.MemSingle.read.4" hover="accessor: bits(size*8) AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc, boolean aligned]">AArch64.MemSingle</anchor>[bits(64) address, integer size,</line>
<line>                               <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, boolean aligned]</line>
<line>    boolean ispair = FALSE;</line>
<line>    return <a link="AArch64.MemSingle.read.5" file="shared_pseudocode.xml" hover="accessor: bits(size*8) AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair]">AArch64.MemSingle</a>[address, size, accdesc, aligned, ispair];</line>
<line></line>
<line>// AArch64.MemSingle[] - non-assignment (read) form</line>
<line>// ================================================</line>
<line>// Perform an atomic, little-endian read of 'size' bytes.</line>
<line></line>
<line link="AArch64.MemSingle.read.5" hover="accessor: bits(size*8) AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair]" conts="AArch64.MemSingle">bits(size*8) <anchor link="AArch64.MemSingle.read.5" hover="accessor: bits(size*8) AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair]">AArch64.MemSingle</anchor>[bits(64) address, integer size, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc_in,</line>
<line>                               boolean aligned, boolean ispair]</line>
<line>    assert size IN {1, 2, 4, 8, 16};</line>
<line>    bits(size*8) value;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = accdesc_in;</line>
<line>    if <a link="impl-shared.HaveLSE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveLSE2Ext()">HaveLSE2Ext</a>() then</line>
<line>        assert <a link="impl-aarch64.AllInAlignedQuantity.3" file="shared_pseudocode.xml" hover="function: boolean AllInAlignedQuantity(bits(64) address, integer size, integer alignment)">AllInAlignedQuantity</a>(address, size, 16);</line>
<line>    else</line>
<line>        assert <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, size);</line>
<line></line>
<line>    // If the instruction encoding permits tag checking, confer with system register configuration</line>
<line>    // which may override this.</line>
<line>    if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; accdesc.tagchecked then</line>
<line>        accdesc.tagchecked = <a link="AArch64.AccessIsTagChecked.2" file="shared_pseudocode.xml" hover="function: boolean AArch64.AccessIsTagChecked(bits(64) vaddr, AccessDescriptor accdesc)">AArch64.AccessIsTagChecked</a>(address, accdesc);</line>
<line></line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc;</line>
<line>    memaddrdesc = <a link="AArch64.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch64.TranslateAddress(bits(64) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch64.TranslateAddress</a>(address, accdesc, aligned, size);</line>
<line></line>
<line>    // Check for aborts or debug exceptions</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, memaddrdesc.fault);</line>
<line></line>
<line>    // Memory array access</line>
<line>    if <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() then</line>
<line>        if accdesc.transactional &amp;&amp; !<a link="impl-aarch64.MemHasTransactionalAccess.1" file="shared_pseudocode.xml" hover="function: boolean MemHasTransactionalAccess(MemoryAttributes memattrs)">MemHasTransactionalAccess</a>(memaddrdesc.memattrs) then</line>
<line>            <a link="impl-aarch64.FailTransaction.2" file="shared_pseudocode.xml" hover="function: FailTransaction(TMFailure cause, boolean retry)">FailTransaction</a>(<a link="TMFailure_IMP" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_IMP</a>, FALSE);</line>
<line></line>
<line>    if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; accdesc.tagchecked then</line>
<line>        bits(4) ptag = <a link="AArch64.PhysicalTag.1" file="shared_pseudocode.xml" hover="function: bits(4) AArch64.PhysicalTag(bits(64) vaddr)">AArch64.PhysicalTag</a>(address);</line>
<line>        if !<a link="AArch64.CheckTag.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.CheckTag(AddressDescriptor memaddrdesc, AccessDescriptor accdesc, bits(4) ptag)">AArch64.CheckTag</a>(memaddrdesc, accdesc, ptag) then</line>
<line>            <a link="AArch64.TagCheckFault.2" file="shared_pseudocode.xml" hover="function: AArch64.TagCheckFault(bits(64) vaddress, AccessDescriptor accdesc)">AArch64.TagCheckFault</a>(address, accdesc);</line>
<line></line>
<line>    if SPESampleInFlight then</line>
<line>        boolean is_load = TRUE;</line>
<line>        <a link="impl-aarch64.SPESampleLoadStore.3" file="shared_pseudocode.xml" hover="function: SPESampleLoadStore(boolean is_load, AccessDescriptor accdesc, AddressDescriptor addrdesc)">SPESampleLoadStore</a>(is_load, accdesc, memaddrdesc);</line>
<line></line>
<line>    boolean atomic;</line>
<line>    if (memaddrdesc.memattrs.memtype == <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a> &amp;&amp;</line>
<line>            memaddrdesc.memattrs.inner.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a> &amp;&amp;</line>
<line>            memaddrdesc.memattrs.outer.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>) then</line>
<line>        atomic = TRUE;</line>
<line>    elsif (accdesc.exclusive || accdesc.atomicop ||</line>
<line>            accdesc.acqsc || accdesc.acqpc || accdesc.relsc) then</line>
<line>        if !aligned &amp;&amp; !<a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_MISALIGNEDATOMIC" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_MISALIGNEDATOMIC</a>) then</line>
<line>            <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line>        else</line>
<line>            atomic = TRUE;</line>
<line>    elsif aligned then</line>
<line>        atomic = !ispair;</line>
<line>    else</line>
<line>        // Misaligned accesses within 16 byte aligned memory but</line>
<line>        // not Normal Cacheable Writeback are Atomic</line>
<line>        atomic = boolean IMPLEMENTATION_DEFINED "FEAT_LSE2: access is atomic";</line>
<line></line>
<line>    <a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> memstatus;</line>
<line>    if atomic then</line>
<line>        (memstatus, value) = <a link="impl-shared.PhysMemRead.3" file="shared_pseudocode.xml" hover="function: (PhysMemRetStatus, bits(8*size)) PhysMemRead(AddressDescriptor desc, integer size, AccessDescriptor accdesc)">PhysMemRead</a>(memaddrdesc, size, accdesc);</line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>            <a link="impl-shared.HandleExternalReadAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalReadAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalReadAbort</a>(memstatus, memaddrdesc, size, accdesc);</line>
<line>    elsif aligned &amp;&amp; ispair then</line>
<line>        assert size IN {8, 16};</line>
<line>        constant halfsize = size DIV 2;</line>
<line>        bits(halfsize * 8) lowhalf, highhalf;</line>
<line>        (memstatus, lowhalf) = <a link="impl-shared.PhysMemRead.3" file="shared_pseudocode.xml" hover="function: (PhysMemRetStatus, bits(8*size)) PhysMemRead(AddressDescriptor desc, integer size, AccessDescriptor accdesc)">PhysMemRead</a>(memaddrdesc, halfsize, accdesc);</line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>            <a link="impl-shared.HandleExternalReadAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalReadAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalReadAbort</a>(memstatus, memaddrdesc, halfsize, accdesc);</line>
<line>        memaddrdesc.paddress.address = memaddrdesc.paddress.address + halfsize;</line>
<line>        (memstatus, highhalf) = <a link="impl-shared.PhysMemRead.3" file="shared_pseudocode.xml" hover="function: (PhysMemRetStatus, bits(8*size)) PhysMemRead(AddressDescriptor desc, integer size, AccessDescriptor accdesc)">PhysMemRead</a>(memaddrdesc, halfsize, accdesc);</line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>            <a link="impl-shared.HandleExternalReadAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalReadAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalReadAbort</a>(memstatus, memaddrdesc, halfsize, accdesc);</line>
<line></line>
<line>        value = highhalf:lowhalf;</line>
<line>    else</line>
<line>        for i = 0 to size-1</line>
<line>            (memstatus, value&lt;8*i+7:8*i&gt;) = <a link="impl-shared.PhysMemRead.3" file="shared_pseudocode.xml" hover="function: (PhysMemRetStatus, bits(8*size)) PhysMemRead(AddressDescriptor desc, integer size, AccessDescriptor accdesc)">PhysMemRead</a>(memaddrdesc, 1, accdesc);</line>
<line>            if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>                <a link="impl-shared.HandleExternalReadAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalReadAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalReadAbort</a>(memstatus, memaddrdesc, 1, accdesc);</line>
<line>            memaddrdesc.paddress.address = memaddrdesc.paddress.address + 1;</line>
<line>    return value;</line>
<line></line>
<line>// AArch64.MemSingle[] - assignment (write) form</line>
<line>// =============================================</line>
<line></line>
<line link="AArch64.MemSingle.write.4" hover="accessor: AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc, boolean aligned] = bits(size*8) value" conts="AArch64.MemSingle"><anchor link="AArch64.MemSingle.write.4" hover="accessor: AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc, boolean aligned] = bits(size*8) value">AArch64.MemSingle</anchor>[bits(64) address, integer size,</line>
<line>                  <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, boolean aligned] = bits(size*8) value</line>
<line>    boolean ispair = FALSE;</line>
<line>    <a link="AArch64.MemSingle.write.5" file="shared_pseudocode.xml" hover="accessor: AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair] = bits(size*8) value">AArch64.MemSingle</a>[address, size, accdesc, aligned, ispair] = value;</line>
<line>    return;</line>
<line></line>
<line>// AArch64.MemSingle[] - assignment (write) form</line>
<line>// =============================================</line>
<line>// Perform an atomic, little-endian write of 'size' bytes.</line>
<line></line>
<line link="AArch64.MemSingle.write.5" hover="accessor: AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair] = bits(size*8) value" conts="AArch64.MemSingle"><anchor link="AArch64.MemSingle.write.5" hover="accessor: AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair] = bits(size*8) value">AArch64.MemSingle</anchor>[bits(64) address, integer size, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc_in,</line>
<line>                  boolean aligned, boolean ispair] = bits(size*8) value</line>
<line>    assert size IN {1, 2, 4, 8, 16};</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = accdesc_in;</line>
<line>    if <a link="impl-shared.HaveLSE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveLSE2Ext()">HaveLSE2Ext</a>() then</line>
<line>        assert <a link="impl-aarch64.AllInAlignedQuantity.3" file="shared_pseudocode.xml" hover="function: boolean AllInAlignedQuantity(bits(64) address, integer size, integer alignment)">AllInAlignedQuantity</a>(address, size, 16);</line>
<line>    else</line>
<line>        assert <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, size);</line>
<line></line>
<line>    // If the instruction encoding permits tag checking, confer with system register configuration</line>
<line>    // which may override this.</line>
<line>    if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; accdesc.tagchecked then</line>
<line>        accdesc.tagchecked = <a link="AArch64.AccessIsTagChecked.2" file="shared_pseudocode.xml" hover="function: boolean AArch64.AccessIsTagChecked(bits(64) vaddr, AccessDescriptor accdesc)">AArch64.AccessIsTagChecked</a>(address, accdesc);</line>
<line></line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc;</line>
<line>    memaddrdesc = <a link="AArch64.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch64.TranslateAddress(bits(64) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch64.TranslateAddress</a>(address, accdesc, aligned, size);</line>
<line></line>
<line>    // Check for aborts or debug exceptions</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, memaddrdesc.fault);</line>
<line></line>
<line>    // Effect on exclusives</line>
<line>    if memaddrdesc.memattrs.shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then</line>
<line>        <a link="impl-shared.ClearExclusiveByAddress.3" file="shared_pseudocode.xml" hover="function: ClearExclusiveByAddress(FullAddress paddress, integer processorid, integer size)">ClearExclusiveByAddress</a>(memaddrdesc.paddress, <a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>(), size);</line>
<line></line>
<line>    if <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() then</line>
<line>        if accdesc.transactional &amp;&amp; !<a link="impl-aarch64.MemHasTransactionalAccess.1" file="shared_pseudocode.xml" hover="function: boolean MemHasTransactionalAccess(MemoryAttributes memattrs)">MemHasTransactionalAccess</a>(memaddrdesc.memattrs) then</line>
<line>            <a link="impl-aarch64.FailTransaction.2" file="shared_pseudocode.xml" hover="function: FailTransaction(TMFailure cause, boolean retry)">FailTransaction</a>(<a link="TMFailure_IMP" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_IMP</a>, FALSE);</line>
<line></line>
<line>    if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; accdesc.tagchecked then</line>
<line>        bits(4) ptag = <a link="AArch64.PhysicalTag.1" file="shared_pseudocode.xml" hover="function: bits(4) AArch64.PhysicalTag(bits(64) vaddr)">AArch64.PhysicalTag</a>(address);</line>
<line>        if !<a link="AArch64.CheckTag.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.CheckTag(AddressDescriptor memaddrdesc, AccessDescriptor accdesc, bits(4) ptag)">AArch64.CheckTag</a>(memaddrdesc, accdesc, ptag) then</line>
<line>            <a link="AArch64.TagCheckFault.2" file="shared_pseudocode.xml" hover="function: AArch64.TagCheckFault(bits(64) vaddress, AccessDescriptor accdesc)">AArch64.TagCheckFault</a>(address, accdesc);</line>
<line></line>
<line>    if SPESampleInFlight then</line>
<line>        boolean is_load = FALSE;</line>
<line>        <a link="impl-aarch64.SPESampleLoadStore.3" file="shared_pseudocode.xml" hover="function: SPESampleLoadStore(boolean is_load, AccessDescriptor accdesc, AddressDescriptor addrdesc)">SPESampleLoadStore</a>(is_load, accdesc, memaddrdesc);</line>
<line></line>
<line>    <a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> memstatus;</line>
<line>    boolean atomic;</line>
<line>    if (memaddrdesc.memattrs.memtype == <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a> &amp;&amp;</line>
<line>            memaddrdesc.memattrs.inner.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a> &amp;&amp;</line>
<line>            memaddrdesc.memattrs.outer.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>) then</line>
<line>        atomic = TRUE;</line>
<line>    elsif (accdesc.exclusive || accdesc.atomicop ||</line>
<line>            accdesc.acqsc || accdesc.acqpc || accdesc.relsc) then</line>
<line>        if !aligned &amp;&amp; !<a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_MISALIGNEDATOMIC" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_MISALIGNEDATOMIC</a>) then</line>
<line>            <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line>        else</line>
<line>            atomic = TRUE;</line>
<line>    elsif aligned then</line>
<line>        atomic = !ispair;</line>
<line>    else</line>
<line>        // Misaligned accesses within 16 byte aligned memory but</line>
<line>        // not Normal Cacheable Writeback are Atomic</line>
<line>        atomic = boolean IMPLEMENTATION_DEFINED "FEAT_LSE2: access is atomic";</line>
<line></line>
<line>    if atomic then</line>
<line>        memstatus = <a link="impl-shared.PhysMemWrite.4" file="shared_pseudocode.xml" hover="function: PhysMemRetStatus PhysMemWrite(AddressDescriptor desc, integer size, AccessDescriptor accdesc, bits(8*size) value)">PhysMemWrite</a>(memaddrdesc, size, accdesc, value);</line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>            <a link="impl-shared.HandleExternalWriteAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalWriteAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalWriteAbort</a>(memstatus, memaddrdesc, size, accdesc);</line>
<line>    elsif aligned &amp;&amp; ispair then</line>
<line>        assert size IN {8, 16};</line>
<line>        constant halfsize = size DIV 2;</line>
<line>        bits(halfsize*8) lowhalf, highhalf;</line>
<line>        &lt;highhalf, lowhalf&gt; = value;</line>
<line></line>
<line>        memstatus = <a link="impl-shared.PhysMemWrite.4" file="shared_pseudocode.xml" hover="function: PhysMemRetStatus PhysMemWrite(AddressDescriptor desc, integer size, AccessDescriptor accdesc, bits(8*size) value)">PhysMemWrite</a>(memaddrdesc, halfsize, accdesc, lowhalf);</line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>            <a link="impl-shared.HandleExternalWriteAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalWriteAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalWriteAbort</a>(memstatus, memaddrdesc, halfsize, accdesc);</line>
<line>        memaddrdesc.paddress.address = memaddrdesc.paddress.address + halfsize;</line>
<line>        memstatus = <a link="impl-shared.PhysMemWrite.4" file="shared_pseudocode.xml" hover="function: PhysMemRetStatus PhysMemWrite(AddressDescriptor desc, integer size, AccessDescriptor accdesc, bits(8*size) value)">PhysMemWrite</a>(memaddrdesc, halfsize, accdesc, highhalf);</line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>            <a link="impl-shared.HandleExternalWriteAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalWriteAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalWriteAbort</a>(memstatus, memaddrdesc, halfsize, accdesc);</line>
<line>    else</line>
<line>        for i = 0 to size-1</line>
<line>            memstatus = <a link="impl-shared.PhysMemWrite.4" file="shared_pseudocode.xml" hover="function: PhysMemRetStatus PhysMemWrite(AddressDescriptor desc, integer size, AccessDescriptor accdesc, bits(8*size) value)">PhysMemWrite</a>(memaddrdesc, 1, accdesc, value&lt;8*i+7:8*i&gt;);</line>
<line>            if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>                <a link="impl-shared.HandleExternalWriteAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalWriteAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalWriteAbort</a>(memstatus, memaddrdesc, 1, accdesc);</line>
<line>            memaddrdesc.paddress.address = memaddrdesc.paddress.address + 1;</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/AArch64.MemTag" mylink="aarch64.functions.memory.AArch64.MemTag" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.MemTag[] - non-assignment (read) form</line>
<line>// =============================================</line>
<line>// Load an Allocation Tag from memory.</line>
<line></line>
<line link="AArch64.MemTag.read.2" hover="accessor: bits(4) AArch64.MemTag[bits(64) address, AccessDescriptor accdesc_in]" conts="AArch64.MemTag">bits(4) <anchor link="AArch64.MemTag.read.2" hover="accessor: bits(4) AArch64.MemTag[bits(64) address, AccessDescriptor accdesc_in]">AArch64.MemTag</anchor>[bits(64) address, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc_in]</line>
<line>    assert accdesc_in.tagaccess &amp;&amp; !accdesc_in.tagchecked;</line>
<line></line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = accdesc_in;</line>
<line>    bits(4) value;</line>
<line></line>
<line>    boolean aligned = TRUE;</line>
<line></line>
<line>    if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() then</line>
<line>        accdesc.tagaccess = <a link="AArch64.AllocationTagAccessIsEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.AllocationTagAccessIsEnabled(bits(2) el)">AArch64.AllocationTagAccessIsEnabled</a>(accdesc.el);</line>
<line></line>
<line>    memaddrdesc = <a link="AArch64.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch64.TranslateAddress(bits(64) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch64.TranslateAddress</a>(address, accdesc, aligned, <a link="TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer TAG_GRANULE = 1 &lt;&lt; LOG2_TAG_GRANULE">TAG_GRANULE</a>);</line>
<line></line>
<line>    // Check for aborts or debug exceptions</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, memaddrdesc.fault);</line>
<line></line>
<line>    // Return the granule tag if tagging is enabled...</line>
<line>    if accdesc.tagaccess &amp;&amp; memaddrdesc.memattrs.tags == <a link="MemTag_AllocationTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_AllocationTagged</a> then</line>
<line>        (memstatus, tag) = <a link="impl-aarch64.PhysMemTagRead.2" file="shared_pseudocode.xml" hover="function: (PhysMemRetStatus, bits(4)) PhysMemTagRead(AddressDescriptor desc, AccessDescriptor accdesc)">PhysMemTagRead</a>(memaddrdesc, accdesc);</line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>            <a link="impl-shared.HandleExternalReadAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalReadAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalReadAbort</a>(memstatus, memaddrdesc, 1, accdesc);</line>
<line>        return tag;</line>
<line>    elsif (<a link="impl-shared.HaveMTECanonicalTagCheckingExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTECanonicalTagCheckingExt()">HaveMTECanonicalTagCheckingExt</a>() &amp;&amp;</line>
<line>           accdesc.tagaccess &amp;&amp;</line>
<line>           memaddrdesc.memattrs.tags == <a link="MemTag_CanonicallyTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_CanonicallyTagged</a>) then</line>
<line>        return if address&lt;55&gt; == '0' then '0000' else '1111';</line>
<line>    else</line>
<line>        // ...otherwise read tag as zero.</line>
<line>        return '0000';</line>
<line></line>
<line>// AArch64.MemTag[] - assignment (write) form</line>
<line>// ==========================================</line>
<line>// Store an Allocation Tag to memory.</line>
<line></line>
<line link="AArch64.MemTag.write.2" hover="accessor: AArch64.MemTag[bits(64) address, AccessDescriptor accdesc_in] = bits(4) value" conts="AArch64.MemTag"><anchor link="AArch64.MemTag.write.2" hover="accessor: AArch64.MemTag[bits(64) address, AccessDescriptor accdesc_in] = bits(4) value">AArch64.MemTag</anchor>[bits(64) address, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc_in] = bits(4) value</line>
<line>    assert accdesc_in.tagaccess &amp;&amp; !accdesc_in.tagchecked;</line>
<line></line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = accdesc_in;</line>
<line></line>
<line>    boolean aligned = <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, <a link="TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer TAG_GRANULE = 1 &lt;&lt; LOG2_TAG_GRANULE">TAG_GRANULE</a>);</line>
<line></line>
<line>    // Stores of allocation tags must be aligned</line>
<line>    if !aligned then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() then</line>
<line>        accdesc.tagaccess = <a link="AArch64.AllocationTagAccessIsEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.AllocationTagAccessIsEnabled(bits(2) el)">AArch64.AllocationTagAccessIsEnabled</a>(accdesc.el);</line>
<line></line>
<line>    memaddrdesc = <a link="AArch64.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch64.TranslateAddress(bits(64) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch64.TranslateAddress</a>(address, accdesc, aligned, <a link="TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer TAG_GRANULE = 1 &lt;&lt; LOG2_TAG_GRANULE">TAG_GRANULE</a>);</line>
<line></line>
<line>    // Check for aborts or debug exceptions</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, memaddrdesc.fault);</line>
<line></line>
<line>    // Memory array access</line>
<line>    if accdesc.tagaccess &amp;&amp; memaddrdesc.memattrs.tags == <a link="MemTag_AllocationTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_AllocationTagged</a> then</line>
<line>        memstatus = <a link="impl-aarch64.PhysMemTagWrite.3" file="shared_pseudocode.xml" hover="function: PhysMemRetStatus PhysMemTagWrite(AddressDescriptor desc, AccessDescriptor accdesc, bits (4) value)">PhysMemTagWrite</a>(memaddrdesc, accdesc, value);</line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>            <a link="impl-shared.HandleExternalWriteAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalWriteAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalWriteAbort</a>(memstatus, memaddrdesc, 1, accdesc);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/AArch64.PhysicalTag" mylink="aarch64.functions.memory.AArch64.PhysicalTag" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.PhysicalTag()</line>
<line>// =====================</line>
<line>// Generate a Physical Tag from a Logical Tag in an address</line>
<line></line>
<line link="AArch64.PhysicalTag.1" hover="function: bits(4) AArch64.PhysicalTag(bits(64) vaddr)" conts="AArch64.PhysicalTag">bits(4) <anchor link="AArch64.PhysicalTag.1" hover="function: bits(4) AArch64.PhysicalTag(bits(64) vaddr)">AArch64.PhysicalTag</anchor>(bits(64) vaddr)</line>
<line>    return vaddr&lt;59:56&gt;;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/AArch64.UnalignedAccessFaults" mylink="aarch64.functions.memory.AArch64.UnalignedAccessFaults" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.UnalignedAccessFaults()</line>
<line>// ===============================</line>
<line>// Determine whether the unaligned access generates an Alignment fault</line>
<line></line>
<line link="AArch64.UnalignedAccessFaults.3" hover="function: boolean AArch64.UnalignedAccessFaults(AccessDescriptor accdesc, bits(64) address, integer size)" conts="AArch64.UnalignedAccessFaults">boolean <anchor link="AArch64.UnalignedAccessFaults.3" hover="function: boolean AArch64.UnalignedAccessFaults(AccessDescriptor accdesc, bits(64) address, integer size)">AArch64.UnalignedAccessFaults</anchor>(<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, bits(64) address, integer size)</line>
<line>    if <a link="impl-shared.AlignmentEnforced.0" file="shared_pseudocode.xml" hover="function: boolean AlignmentEnforced()">AlignmentEnforced</a>() then</line>
<line>        return TRUE;</line>
<line>    elsif accdesc.acctype == <a link="AccessType_GCS" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GCS</a> then</line>
<line>        return TRUE;</line>
<line>    elsif accdesc.rcw then</line>
<line>        return TRUE;</line>
<line>    elsif accdesc.ls64 then</line>
<line>        return TRUE;</line>
<line>    elsif accdesc.exclusive || accdesc.atomicop then</line>
<line>        return !<a link="impl-shared.HaveLSE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveLSE2Ext()">HaveLSE2Ext</a>() || !<a link="impl-aarch64.AllInAlignedQuantity.3" file="shared_pseudocode.xml" hover="function: boolean AllInAlignedQuantity(bits(64) address, integer size, integer alignment)">AllInAlignedQuantity</a>(address, size, 16);</line>
<line>    elsif accdesc.acqsc || accdesc.acqpc || accdesc.relsc then</line>
<line>        return !<a link="impl-shared.HaveLSE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveLSE2Ext()">HaveLSE2Ext</a>() || (<a link="impl-aarch64.SCTLR.read.0" file="shared_pseudocode.xml" hover="accessor: SCTLRType SCTLR[]">SCTLR</a>[].nAA == '0' &amp;&amp; !<a link="impl-aarch64.AllInAlignedQuantity.3" file="shared_pseudocode.xml" hover="function: boolean AllInAlignedQuantity(bits(64) address, integer size, integer alignment)">AllInAlignedQuantity</a>(address, size, 16));</line>
<line>    else</line>
<line>        return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/AddressSupportsLS64" mylink="aarch64.functions.memory.AddressSupportsLS64" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AddressSupportsLS64()</line>
<line>// =====================</line>
<line>// Returns TRUE if the 64-byte block following the given address supports the</line>
<line>// LD64B and ST64B instructions, and FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.AddressSupportsLS64.1" hover="function: boolean AddressSupportsLS64(bits(56) paddress)" conts="AddressSupportsLS64">boolean <anchor link="impl-aarch64.AddressSupportsLS64.1" hover="function: boolean AddressSupportsLS64(bits(56) paddress)">AddressSupportsLS64</anchor>(bits(56) paddress);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/AllInAlignedQuantity" mylink="aarch64.functions.memory.AllInAlignedQuantity" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AllInAlignedQuantity()</line>
<line>// ======================</line>
<line>// Returns TRUE if all accessed bytes are within one aligned quantity, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.AllInAlignedQuantity.3" hover="function: boolean AllInAlignedQuantity(bits(64) address, integer size, integer alignment)" conts="AllInAlignedQuantity">boolean <anchor link="impl-aarch64.AllInAlignedQuantity.3" hover="function: boolean AllInAlignedQuantity(bits(64) address, integer size, integer alignment)">AllInAlignedQuantity</anchor>(bits(64) address, integer size, integer alignment)</line>
<line>    assert(size &lt;= alignment);</line>
<line>    return <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>((address+size)-1, alignment) == <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(address, alignment);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/CheckSPAlignment" mylink="aarch64.functions.memory.CheckSPAlignment" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckSPAlignment()</line>
<line>// ==================</line>
<line>// Check correct stack pointer alignment for AArch64 state.</line>
<line></line>
<line link="impl-aarch64.CheckSPAlignment.0" hover="function: CheckSPAlignment()" conts="CheckSPAlignment"><anchor link="impl-aarch64.CheckSPAlignment.0" hover="function: CheckSPAlignment()">CheckSPAlignment</anchor>()</line>
<line>    bits(64) sp = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];</line>
<line>    boolean stack_align_check;</line>
<line>    if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        stack_align_check = (<a link="impl-aarch64.SCTLR.read.0" file="shared_pseudocode.xml" hover="accessor: SCTLRType SCTLR[]">SCTLR</a>[].SA0 != '0');</line>
<line>    else</line>
<line>        stack_align_check = (<a link="impl-aarch64.SCTLR.read.0" file="shared_pseudocode.xml" hover="accessor: SCTLRType SCTLR[]">SCTLR</a>[].SA != '0');</line>
<line></line>
<line>    if stack_align_check &amp;&amp; sp != <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(sp, 16) then</line>
<line>        <a link="AArch64.SPAlignmentFault.0" file="shared_pseudocode.xml" hover="function: AArch64.SPAlignmentFault()">AArch64.SPAlignmentFault</a>();</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/Mem" mylink="aarch64.functions.memory.Mem" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Mem[] - non-assignment (read) form</line>
<line>// ==================================</line>
<line>// Perform a read of 'size' bytes. The access byte order is reversed for a big-endian access.</line>
<line>// Instruction fetches would call AArch64.MemSingle directly.</line>
<line></line>
<line link="impl-aarch64.Mem.read.3" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]" conts="Mem">bits(size*8) <anchor link="impl-aarch64.Mem.read.3" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</anchor>[bits(64) address, integer size, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc]</line>
<line>    boolean ispair = FALSE;</line>
<line>    boolean highestAddressfirst = FALSE;</line>
<line>    return <a link="impl-aarch64.Mem.read.5" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc, boolean ispair, boolean  highestAddressfirst]">Mem</a>[address, size, accdesc, ispair, highestAddressfirst];</line>
<line></line>
<line link="impl-aarch64.Mem.read.4" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc, boolean ispair]" conts="Mem">bits(size*8) <anchor link="impl-aarch64.Mem.read.4" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc, boolean ispair]">Mem</anchor>[bits(64) address, integer size, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, boolean ispair]</line>
<line>    boolean highestAddressfirst = FALSE;</line>
<line>    return <a link="impl-aarch64.Mem.read.5" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc, boolean ispair, boolean  highestAddressfirst]">Mem</a>[address, size, accdesc, ispair, highestAddressfirst];</line>
<line></line>
<line link="impl-aarch64.Mem.read.5" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc, boolean ispair, boolean  highestAddressfirst]" conts="Mem">bits(size*8) <anchor link="impl-aarch64.Mem.read.5" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc, boolean ispair, boolean  highestAddressfirst]">Mem</anchor>[bits(64) address, integer size, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc,</line>
<line>                 boolean ispair, boolean  highestAddressfirst]</line>
<line>    assert size IN {1, 2, 4, 8, 16};</line>
<line>    constant halfsize = size DIV 2;</line>
<line>    bits(size * 8) value;</line>
<line>    bits(halfsize * 8) lowhalf, highhalf;</line>
<line></line>
<line>    // Check alignment on size of element accessed, not overall access size</line>
<line>    integer alignment = if ispair then halfsize else size;</line>
<line>    boolean aligned   = <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment);</line>
<line></line>
<line>    if !aligned &amp;&amp; <a link="AArch64.UnalignedAccessFaults.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.UnalignedAccessFaults(AccessDescriptor accdesc, bits(64) address, integer size)">AArch64.UnalignedAccessFaults</a>(accdesc, address, size) then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    if accdesc.acctype == <a link="AccessType_ASIMD" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_ASIMD</a> &amp;&amp; size == 16 &amp;&amp; <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, 8) then</line>
<line>        // If 128-bit SIMD&amp;FP ordered access are treated as a pair of</line>
<line>        // 64-bit single-copy atomic accesses, then these single copy atomic</line>
<line>        // access can be observed in any order.</line>
<line>        lowhalf = <a link="AArch64.MemSingle.read.5" file="shared_pseudocode.xml" hover="accessor: bits(size*8) AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair]">AArch64.MemSingle</a>[address, halfsize, accdesc, aligned, ispair];</line>
<line>        highhalf = <a link="AArch64.MemSingle.read.5" file="shared_pseudocode.xml" hover="accessor: bits(size*8) AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair]">AArch64.MemSingle</a>[address+halfsize, halfsize, accdesc, aligned, ispair];</line>
<line>        value = highhalf:lowhalf;</line>
<line>    elsif <a link="impl-shared.HaveLSE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveLSE2Ext()">HaveLSE2Ext</a>() &amp;&amp; <a link="impl-aarch64.AllInAlignedQuantity.3" file="shared_pseudocode.xml" hover="function: boolean AllInAlignedQuantity(bits(64) address, integer size, integer alignment)">AllInAlignedQuantity</a>(address, size, 16) then</line>
<line>        value = <a link="AArch64.MemSingle.read.5" file="shared_pseudocode.xml" hover="accessor: bits(size*8) AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair]">AArch64.MemSingle</a>[address, size, accdesc, aligned, ispair];</line>
<line>    elsif ispair &amp;&amp; aligned then</line>
<line>        if <a link="impl-shared.HaveLRCPC3Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveLRCPC3Ext()">HaveLRCPC3Ext</a>() &amp;&amp; highestAddressfirst then</line>
<line>            highhalf = <a link="AArch64.MemSingle.read.4" file="shared_pseudocode.xml" hover="accessor: bits(size*8) AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc, boolean aligned]">AArch64.MemSingle</a>[address+halfsize, halfsize, accdesc, aligned];</line>
<line>            lowhalf  = <a link="AArch64.MemSingle.read.4" file="shared_pseudocode.xml" hover="accessor: bits(size*8) AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc, boolean aligned]">AArch64.MemSingle</a>[address, halfsize, accdesc, aligned];</line>
<line>        else</line>
<line>            lowhalf  = <a link="AArch64.MemSingle.read.4" file="shared_pseudocode.xml" hover="accessor: bits(size*8) AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc, boolean aligned]">AArch64.MemSingle</a>[address, halfsize, accdesc, aligned];</line>
<line>            highhalf = <a link="AArch64.MemSingle.read.4" file="shared_pseudocode.xml" hover="accessor: bits(size*8) AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc, boolean aligned]">AArch64.MemSingle</a>[address+halfsize, halfsize, accdesc, aligned];</line>
<line>        value = highhalf:lowhalf;</line>
<line>    elsif aligned then</line>
<line>        value = <a link="AArch64.MemSingle.read.5" file="shared_pseudocode.xml" hover="accessor: bits(size*8) AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair]">AArch64.MemSingle</a>[address, size, accdesc, aligned, ispair];</line>
<line>    else</line>
<line>        assert size &gt; 1;</line>
<line>        if <a link="impl-shared.HaveLRCPC3Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveLRCPC3Ext()">HaveLRCPC3Ext</a>() &amp;&amp; ispair &amp;&amp; highestAddressfirst then</line>
<line>            // Performing memory accesses from one load or store instruction to Device memory that</line>
<line>            // crosses a boundary corresponding to the smallest translation granule size of the</line>
<line>            // implementation causes CONSTRAINED UNPREDICTABLE behavior.</line>
<line></line>
<line>            for i = 0 to halfsize-1</line>
<line>                // Individual byte access can be observed in any order</line>
<line>                highhalf&lt;8*i+7:8*i&gt; = <a link="AArch64.MemSingle.read.4" file="shared_pseudocode.xml" hover="accessor: bits(size*8) AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc, boolean aligned]">AArch64.MemSingle</a>[address+halfsize +i, 1, accdesc, aligned];</line>
<line>            for i = 0 to halfsize-1</line>
<line>                // Individual byte access can be observed in any order</line>
<line>                lowhalf&lt;8*i+7:8*i&gt; = <a link="AArch64.MemSingle.read.4" file="shared_pseudocode.xml" hover="accessor: bits(size*8) AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc, boolean aligned]">AArch64.MemSingle</a>[address + i, 1, accdesc, aligned];</line>
<line></line>
<line>            value = highhalf:lowhalf;</line>
<line></line>
<line>        else</line>
<line>            value&lt;7:0&gt; = <a link="AArch64.MemSingle.read.4" file="shared_pseudocode.xml" hover="accessor: bits(size*8) AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc, boolean aligned]">AArch64.MemSingle</a>[address, 1, accdesc, aligned];</line>
<line></line>
<line>            // For subsequent bytes it is CONSTRAINED UNPREDICTABLE whether an unaligned Device</line>
<line>            // memory access will generate an Alignment Fault, as to get this far means the first</line>
<line>            // byte did not, so we must be changing to a new translation page.</line>
<line>            c = <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_DEVPAGE2" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_DEVPAGE2</a>);</line>
<line>            assert c IN {<a link="Constraint_FAULT" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_FAULT</a>, <a link="Constraint_NONE" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NONE</a>};</line>
<line>            if c == <a link="Constraint_NONE" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NONE</a> then aligned = TRUE;</line>
<line></line>
<line>            for i = 1 to size-1</line>
<line>                value&lt;8*i+7:8*i&gt; = <a link="AArch64.MemSingle.read.4" file="shared_pseudocode.xml" hover="accessor: bits(size*8) AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc, boolean aligned]">AArch64.MemSingle</a>[address+i, 1, accdesc, aligned];</line>
<line></line>
<line>    if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(accdesc.acctype) then</line>
<line>        value = <a link="impl-shared.BigEndianReverse.1" file="shared_pseudocode.xml" hover="function: bits(width) BigEndianReverse (bits(width) value)">BigEndianReverse</a>(value);</line>
<line></line>
<line>    return value;</line>
<line></line>
<line>// Mem[] - assignment (write) form</line>
<line>// ===============================</line>
<line>// Perform a write of 'size' bytes. The byte order is reversed for a big-endian access.</line>
<line></line>
<line>Mem[bits(64) address, integer size, AccessDescriptor accdesc] = bits(size*8) value_in</line>
<line>    boolean ispair = FALSE;</line>
<line>    boolean highestAddressfirst = FALSE;</line>
<line>    Mem[address, size, accdesc, ispair, highestAddressfirst] = value_in;</line>
<line></line>
<line>Mem[bits(64) address, integer size, AccessDescriptor accdesc,</line>
<line>        boolean ispair] = bits(size*8) value_in</line>
<line>    boolean highestAddressfirst = FALSE;</line>
<line>    Mem[address, size, accdesc, ispair, highestAddressfirst] = value_in;</line>
<line></line>
<line>Mem[bits(64) address, integer size, AccessDescriptor accdesc,</line>
<line>        boolean ispair, boolean highestAddressfirst] = bits(size*8) value_in</line>
<line>    constant halfsize = size DIV 2;</line>
<line>    bits(size*8) value = value_in;</line>
<line>    bits(halfsize*8) lowhalf, highhalf;</line>
<line></line>
<line>    // Check alignment on size of element accessed, not overall access size</line>
<line>    integer alignment = if ispair then halfsize else size;</line>
<line>    boolean aligned   = <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment);</line>
<line></line>
<line>    if !aligned &amp;&amp; <a link="AArch64.UnalignedAccessFaults.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.UnalignedAccessFaults(AccessDescriptor accdesc, bits(64) address, integer size)">AArch64.UnalignedAccessFaults</a>(accdesc, address, size) then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(accdesc.acctype) then</line>
<line>        value = <a link="impl-shared.BigEndianReverse.1" file="shared_pseudocode.xml" hover="function: bits(width) BigEndianReverse (bits(width) value)">BigEndianReverse</a>(value);</line>
<line></line>
<line>    if accdesc.acctype == <a link="AccessType_ASIMD" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_ASIMD</a> &amp;&amp; size == 16 &amp;&amp; <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, 8) then</line>
<line>        // 128-bit SIMD&amp;FP stores are treated as a pair of 64-bit single-copy atomic accesses</line>
<line>        // 64-bit aligned.</line>
<line>        &lt;highhalf, lowhalf&gt; = value;</line>
<line>        <a link="AArch64.MemSingle.write.5" file="shared_pseudocode.xml" hover="accessor: AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair] = bits(size*8) value">AArch64.MemSingle</a>[address, halfsize, accdesc, aligned, ispair] = lowhalf;</line>
<line>        <a link="AArch64.MemSingle.write.5" file="shared_pseudocode.xml" hover="accessor: AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair] = bits(size*8) value">AArch64.MemSingle</a>[address+halfsize, halfsize, accdesc, aligned, ispair] = highhalf;</line>
<line>    elsif <a link="impl-shared.HaveLSE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveLSE2Ext()">HaveLSE2Ext</a>() &amp;&amp; <a link="impl-aarch64.AllInAlignedQuantity.3" file="shared_pseudocode.xml" hover="function: boolean AllInAlignedQuantity(bits(64) address, integer size, integer alignment)">AllInAlignedQuantity</a>(address, size, 16) then</line>
<line>        <a link="AArch64.MemSingle.write.5" file="shared_pseudocode.xml" hover="accessor: AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair] = bits(size*8) value">AArch64.MemSingle</a>[address, size, accdesc, aligned, ispair] = value;</line>
<line>    elsif ispair &amp;&amp; aligned then</line>
<line>        joinedpair = FALSE;</line>
<line>        &lt;highhalf, lowhalf&gt; = value;</line>
<line>        if <a link="impl-shared.HaveLRCPC3Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveLRCPC3Ext()">HaveLRCPC3Ext</a>() &amp;&amp; highestAddressfirst then</line>
<line>            <a link="AArch64.MemSingle.write.5" file="shared_pseudocode.xml" hover="accessor: AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair] = bits(size*8) value">AArch64.MemSingle</a>[address+halfsize, halfsize, accdesc, aligned, joinedpair] = highhalf;</line>
<line>            <a link="AArch64.MemSingle.write.5" file="shared_pseudocode.xml" hover="accessor: AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair] = bits(size*8) value">AArch64.MemSingle</a>[address, halfsize, accdesc, aligned, joinedpair] = lowhalf;</line>
<line>        else</line>
<line>            <a link="AArch64.MemSingle.write.5" file="shared_pseudocode.xml" hover="accessor: AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair] = bits(size*8) value">AArch64.MemSingle</a>[address, halfsize, accdesc, aligned, joinedpair] = lowhalf;</line>
<line>            <a link="AArch64.MemSingle.write.5" file="shared_pseudocode.xml" hover="accessor: AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair] = bits(size*8) value">AArch64.MemSingle</a>[address+halfsize, halfsize, accdesc, aligned, joinedpair] = highhalf;</line>
<line>    elsif aligned then</line>
<line>        <a link="AArch64.MemSingle.write.5" file="shared_pseudocode.xml" hover="accessor: AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned, boolean ispair] = bits(size*8) value">AArch64.MemSingle</a>[address, size, accdesc, aligned, ispair] = value;</line>
<line>    else</line>
<line>        assert size &gt; 1;</line>
<line>        if <a link="impl-shared.HaveLRCPC3Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveLRCPC3Ext()">HaveLRCPC3Ext</a>() &amp;&amp; ispair &amp;&amp; highestAddressfirst then</line>
<line>            // Performing memory accesses from one load or store instruction to Device memory that</line>
<line>            // crosses a boundary corresponding to the smallest translation granule size of the</line>
<line>            // implementation causes CONSTRAINED UNPREDICTABLE behavior.</line>
<line>            &lt;highhalf, lowhalf&gt; = value;</line>
<line>            for i = 0 to halfsize-1</line>
<line>                // Individual byte access can be observed in any order</line>
<line>                <a link="AArch64.MemSingle.write.4" file="shared_pseudocode.xml" hover="accessor: AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc, boolean aligned] = bits(size*8) value">AArch64.MemSingle</a>[address+halfsize+i, 1, accdesc, aligned] = highhalf&lt;8*i+7:8*i&gt;;</line>
<line>            for i = 0 to halfsize-1</line>
<line>                // Individual byte access can be observed in any order, but implies observability</line>
<line>                // of highhalf</line>
<line>                <a link="AArch64.MemSingle.write.4" file="shared_pseudocode.xml" hover="accessor: AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc, boolean aligned] = bits(size*8) value">AArch64.MemSingle</a>[address+i, 1, accdesc, aligned] = lowhalf&lt;8*i+7:8*i&gt;;</line>
<line>        else</line>
<line>            <a link="AArch64.MemSingle.write.4" file="shared_pseudocode.xml" hover="accessor: AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc, boolean aligned] = bits(size*8) value">AArch64.MemSingle</a>[address, 1, accdesc, aligned] = value&lt;7:0&gt;;</line>
<line></line>
<line>            // For subsequent bytes it is CONSTRAINED UNPREDICTABLE whether an unaligned Device</line>
<line>            // memory access will generate an Alignment Fault, as to get this far means the first</line>
<line>            // byte did not, so we must be changing to a new translation page.</line>
<line></line>
<line>            c = <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_DEVPAGE2" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_DEVPAGE2</a>);</line>
<line>            assert c IN {<a link="Constraint_FAULT" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_FAULT</a>, <a link="Constraint_NONE" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NONE</a>};</line>
<line>            if c == <a link="Constraint_NONE" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NONE</a> then aligned = TRUE;</line>
<line></line>
<line>            for i = 1 to size-1</line>
<line>                <a link="AArch64.MemSingle.write.4" file="shared_pseudocode.xml" hover="accessor: AArch64.MemSingle[bits(64) address, integer size, AccessDescriptor accdesc, boolean aligned] = bits(size*8) value">AArch64.MemSingle</a>[address+i, 1, accdesc, aligned] = value&lt;8*i+7:8*i&gt;;</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/MemAtomic" mylink="aarch64.functions.memory.MemAtomic" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemAtomic()</line>
<line>// ===========</line>
<line>// Performs load and store memory operations for a given virtual address.</line>
<line></line>
<line link="impl-aarch64.MemAtomic.4" hover="function: bits(size) MemAtomic(bits(64) address, bits(size) cmpoperand, bits(size) operand, AccessDescriptor accdesc_in)" conts="MemAtomic">bits(size) <anchor link="impl-aarch64.MemAtomic.4" hover="function: bits(size) MemAtomic(bits(64) address, bits(size) cmpoperand, bits(size) operand, AccessDescriptor accdesc_in)">MemAtomic</anchor>(bits(64) address, bits(size) cmpoperand, bits(size) operand,</line>
<line>                     <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc_in)</line>
<line>    assert accdesc_in.atomicop;</line>
<line></line>
<line>    constant integer bytes = size DIV 8;</line>
<line>    assert bytes IN {1, 2, 4, 8, 16};</line>
<line></line>
<line>    bits(size) newvalue;</line>
<line>    bits(size) oldvalue;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = accdesc_in;</line>
<line>    boolean aligned = <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, bytes);</line>
<line></line>
<line>    // If the instruction encoding permits tag checking, confer with system register configuration</line>
<line>    // which may override this.</line>
<line>    if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; accdesc.tagchecked then</line>
<line>        accdesc.tagchecked = <a link="AArch64.AccessIsTagChecked.2" file="shared_pseudocode.xml" hover="function: boolean AArch64.AccessIsTagChecked(bits(64) vaddr, AccessDescriptor accdesc)">AArch64.AccessIsTagChecked</a>(address, accdesc);</line>
<line></line>
<line>    if !aligned &amp;&amp; <a link="AArch64.UnalignedAccessFaults.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.UnalignedAccessFaults(AccessDescriptor accdesc, bits(64) address, integer size)">AArch64.UnalignedAccessFaults</a>(accdesc, address, bytes) then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    // MMU or MPU lookup</line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc = <a link="AArch64.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch64.TranslateAddress(bits(64) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch64.TranslateAddress</a>(address, accdesc, aligned, size);</line>
<line></line>
<line>    // Check for aborts or debug exceptions</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, memaddrdesc.fault);</line>
<line></line>
<line>    // Effect on exclusives</line>
<line>    if memaddrdesc.memattrs.shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then</line>
<line>        <a link="impl-shared.ClearExclusiveByAddress.3" file="shared_pseudocode.xml" hover="function: ClearExclusiveByAddress(FullAddress paddress, integer processorid, integer size)">ClearExclusiveByAddress</a>(memaddrdesc.paddress, <a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>(), size);</line>
<line></line>
<line>    // For Store-only Tag checking, the tag check is performed on the store.</line>
<line>    if (<a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; accdesc.tagchecked &amp;&amp;</line>
<line>        (!<a link="impl-shared.HaveMTEStoreOnlyExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEStoreOnlyExt()">HaveMTEStoreOnlyExt</a>() || !<a link="impl-aarch64.StoreOnlyTagCheckingEnabled.0" file="shared_pseudocode.xml" hover="function: boolean StoreOnlyTagCheckingEnabled()">StoreOnlyTagCheckingEnabled</a>())) then</line>
<line>        bits(4) ptag = <a link="AArch64.PhysicalTag.1" file="shared_pseudocode.xml" hover="function: bits(4) AArch64.PhysicalTag(bits(64) vaddr)">AArch64.PhysicalTag</a>(address);</line>
<line>        if !<a link="AArch64.CheckTag.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.CheckTag(AddressDescriptor memaddrdesc, AccessDescriptor accdesc, bits(4) ptag)">AArch64.CheckTag</a>(memaddrdesc, accdesc, ptag) then</line>
<line>            <a link="AArch64.TagCheckFault.2" file="shared_pseudocode.xml" hover="function: AArch64.TagCheckFault(bits(64) vaddress, AccessDescriptor accdesc)">AArch64.TagCheckFault</a>(address, accdesc);</line>
<line></line>
<line>    // All observers in the shareability domain observe the following load and store atomically.</line>
<line>    <a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> memstatus;</line>
<line>    (memstatus, oldvalue) = <a link="impl-shared.PhysMemRead.3" file="shared_pseudocode.xml" hover="function: (PhysMemRetStatus, bits(8*size)) PhysMemRead(AddressDescriptor desc, integer size, AccessDescriptor accdesc)">PhysMemRead</a>(memaddrdesc, bytes, accdesc);</line>
<line></line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>        <a link="impl-shared.HandleExternalReadAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalReadAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalReadAbort</a>(memstatus, memaddrdesc, bytes, accdesc);</line>
<line>    if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(accdesc.acctype) then</line>
<line>        oldvalue = <a link="impl-shared.BigEndianReverse.1" file="shared_pseudocode.xml" hover="function: bits(width) BigEndianReverse (bits(width) value)">BigEndianReverse</a>(oldvalue);</line>
<line></line>
<line>    boolean cmpfail = FALSE;</line>
<line>    case accdesc.modop of</line>
<line>        when <a link="MemAtomicOp_ADD" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_ADD</a>   newvalue = oldvalue + operand;</line>
<line>        when <a link="MemAtomicOp_BIC" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_BIC</a>   newvalue = oldvalue AND NOT(operand);</line>
<line>        when <a link="MemAtomicOp_EOR" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_EOR</a>   newvalue = oldvalue EOR operand;</line>
<line>        when <a link="MemAtomicOp_ORR" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_ORR</a>   newvalue = oldvalue OR operand;</line>
<line>        when <a link="MemAtomicOp_SMAX" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_SMAX</a>  newvalue = <a link="impl-shared.Max.2" file="shared_pseudocode.xml" hover="function: integer Max(integer a, integer b)">Max</a>(<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(oldvalue), <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand))&lt;size-1:0&gt;;</line>
<line>        when <a link="MemAtomicOp_SMIN" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_SMIN</a>  newvalue = <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(oldvalue), <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand))&lt;size-1:0&gt;;</line>
<line>        when <a link="MemAtomicOp_UMAX" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_UMAX</a>  newvalue = <a link="impl-shared.Max.2" file="shared_pseudocode.xml" hover="function: integer Max(integer a, integer b)">Max</a>(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(oldvalue), <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(operand))&lt;size-1:0&gt;;</line>
<line>        when <a link="MemAtomicOp_UMIN" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_UMIN</a>  newvalue = <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(oldvalue), <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(operand))&lt;size-1:0&gt;;</line>
<line>        when <a link="MemAtomicOp_SWP" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_SWP</a>   newvalue = operand;</line>
<line>        when <a link="MemAtomicOp_CAS" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_CAS</a>   newvalue = operand; cmpfail = cmpoperand != oldvalue;</line>
<line></line>
<line>    if <a link="impl-shared.HaveMTEStoreOnlyExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEStoreOnlyExt()">HaveMTEStoreOnlyExt</a>() &amp;&amp; <a link="impl-aarch64.StoreOnlyTagCheckingEnabled.0" file="shared_pseudocode.xml" hover="function: boolean StoreOnlyTagCheckingEnabled()">StoreOnlyTagCheckingEnabled</a>() then</line>
<line>        // If the compare on a CAS fails, then it is CONSTRAINED UNPREDICTABLE whether the</line>
<line>        // Tag check is performed.</line>
<line>        if accdesc.tagchecked &amp;&amp; cmpfail then</line>
<line>            accdesc.tagchecked = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_STOREONLYTAGCHECKEDCAS" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_STOREONLYTAGCHECKEDCAS</a>);</line>
<line></line>
<line>        if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; accdesc.tagchecked then</line>
<line>            bits(4) ptag = <a link="AArch64.PhysicalTag.1" file="shared_pseudocode.xml" hover="function: bits(4) AArch64.PhysicalTag(bits(64) vaddr)">AArch64.PhysicalTag</a>(address);</line>
<line>            if !<a link="AArch64.CheckTag.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.CheckTag(AddressDescriptor memaddrdesc, AccessDescriptor accdesc, bits(4) ptag)">AArch64.CheckTag</a>(memaddrdesc, accdesc, ptag) then</line>
<line>                accdesc.read = FALSE; // Tag Check Fault on a write.</line>
<line>                <a link="AArch64.TagCheckFault.2" file="shared_pseudocode.xml" hover="function: AArch64.TagCheckFault(bits(64) vaddress, AccessDescriptor accdesc)">AArch64.TagCheckFault</a>(address, accdesc);</line>
<line></line>
<line>    if !cmpfail then</line>
<line>        if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(accdesc.acctype) then</line>
<line>            newvalue = <a link="impl-shared.BigEndianReverse.1" file="shared_pseudocode.xml" hover="function: bits(width) BigEndianReverse (bits(width) value)">BigEndianReverse</a>(newvalue);</line>
<line>        memstatus = <a link="impl-shared.PhysMemWrite.4" file="shared_pseudocode.xml" hover="function: PhysMemRetStatus PhysMemWrite(AddressDescriptor desc, integer size, AccessDescriptor accdesc, bits(8*size) value)">PhysMemWrite</a>(memaddrdesc, bytes, accdesc, newvalue);</line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>            <a link="impl-shared.HandleExternalWriteAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalWriteAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalWriteAbort</a>(memstatus, memaddrdesc, bytes, accdesc);</line>
<line></line>
<line>    if SPESampleInFlight then</line>
<line>        boolean is_load = FALSE;</line>
<line>        <a link="impl-aarch64.SPESampleLoadStore.3" file="shared_pseudocode.xml" hover="function: SPESampleLoadStore(boolean is_load, AccessDescriptor accdesc, AddressDescriptor addrdesc)">SPESampleLoadStore</a>(is_load, accdesc, memaddrdesc);</line>
<line></line>
<line>    // Load operations return the old (pre-operation) value</line>
<line>    return oldvalue;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/MemAtomicRCW" mylink="aarch64.functions.memory.MemAtomicRCW" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemAtomicRCW()</line>
<line>// ==============</line>
<line>// Perform a single-copy-atomic access with Read-Check-Write operation</line>
<line></line>
<line link="impl-aarch64.MemAtomicRCW.4" hover="function: (bits(4), bits(size)) MemAtomicRCW(bits(64) address, bits(size) cmpoperand, bits(size) operand, AccessDescriptor accdesc_in)" conts="MemAtomicRCW">(bits(4), bits(size)) <anchor link="impl-aarch64.MemAtomicRCW.4" hover="function: (bits(4), bits(size)) MemAtomicRCW(bits(64) address, bits(size) cmpoperand, bits(size) operand, AccessDescriptor accdesc_in)">MemAtomicRCW</anchor>(bits(64) address, bits(size) cmpoperand, bits(size) operand,</line>
<line>                                   <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc_in)</line>
<line>    assert accdesc_in.atomicop;</line>
<line>    assert accdesc_in.rcw;</line>
<line></line>
<line>    constant integer bytes = size DIV 8;</line>
<line>    assert bytes IN {8, 16};</line>
<line></line>
<line>    bits(4) nzcv;</line>
<line>    bits(size) oldvalue;</line>
<line>    bits(size) newvalue;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = accdesc_in;</line>
<line>    boolean aligned = <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, bytes);</line>
<line></line>
<line>    // If the instruction encoding permits tag checking, confer with system register configuration</line>
<line>    // which may override this.</line>
<line>    if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; accdesc.tagchecked then</line>
<line>        accdesc.tagchecked = <a link="AArch64.AccessIsTagChecked.2" file="shared_pseudocode.xml" hover="function: boolean AArch64.AccessIsTagChecked(bits(64) vaddr, AccessDescriptor accdesc)">AArch64.AccessIsTagChecked</a>(address, accdesc);</line>
<line></line>
<line>    if !aligned &amp;&amp; <a link="AArch64.UnalignedAccessFaults.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.UnalignedAccessFaults(AccessDescriptor accdesc, bits(64) address, integer size)">AArch64.UnalignedAccessFaults</a>(accdesc, address, bytes) then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    // MMU or MPU lookup</line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc = <a link="AArch64.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch64.TranslateAddress(bits(64) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch64.TranslateAddress</a>(address, accdesc, aligned, size);</line>
<line></line>
<line>    // Check for aborts or debug exceptions</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, memaddrdesc.fault);</line>
<line></line>
<line>    // Effect on exclusives</line>
<line>    if memaddrdesc.memattrs.shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then</line>
<line>        <a link="impl-shared.ClearExclusiveByAddress.3" file="shared_pseudocode.xml" hover="function: ClearExclusiveByAddress(FullAddress paddress, integer processorid, integer size)">ClearExclusiveByAddress</a>(memaddrdesc.paddress, <a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>(), size);</line>
<line></line>
<line>    // For Store-only Tag checking, the tag check is performed on the store.</line>
<line>    if (<a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; accdesc.tagchecked &amp;&amp;</line>
<line>        (!<a link="impl-shared.HaveMTEStoreOnlyExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEStoreOnlyExt()">HaveMTEStoreOnlyExt</a>() || !<a link="impl-aarch64.StoreOnlyTagCheckingEnabled.0" file="shared_pseudocode.xml" hover="function: boolean StoreOnlyTagCheckingEnabled()">StoreOnlyTagCheckingEnabled</a>())) then</line>
<line>        bits(4) ptag = <a link="AArch64.PhysicalTag.1" file="shared_pseudocode.xml" hover="function: bits(4) AArch64.PhysicalTag(bits(64) vaddr)">AArch64.PhysicalTag</a>(address);</line>
<line>        if !<a link="AArch64.CheckTag.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.CheckTag(AddressDescriptor memaddrdesc, AccessDescriptor accdesc, bits(4) ptag)">AArch64.CheckTag</a>(memaddrdesc, accdesc, ptag) then</line>
<line>            <a link="AArch64.TagCheckFault.2" file="shared_pseudocode.xml" hover="function: AArch64.TagCheckFault(bits(64) vaddress, AccessDescriptor accdesc)">AArch64.TagCheckFault</a>(address, accdesc);</line>
<line></line>
<line>    // All observers in the shareability domain observe the following load and store atomically.</line>
<line>    <a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> memstatus;</line>
<line>    (memstatus, oldvalue) = <a link="impl-shared.PhysMemRead.3" file="shared_pseudocode.xml" hover="function: (PhysMemRetStatus, bits(8*size)) PhysMemRead(AddressDescriptor desc, integer size, AccessDescriptor accdesc)">PhysMemRead</a>(memaddrdesc, bytes, accdesc);</line>
<line></line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>        <a link="impl-shared.HandleExternalReadAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalReadAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalReadAbort</a>(memstatus, memaddrdesc, bytes, accdesc);</line>
<line></line>
<line>    if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(accdesc.acctype) then</line>
<line>        oldvalue = <a link="impl-shared.BigEndianReverse.1" file="shared_pseudocode.xml" hover="function: bits(width) BigEndianReverse (bits(width) value)">BigEndianReverse</a>(oldvalue);</line>
<line></line>
<line>    boolean cmpfail = FALSE;</line>
<line>    case accdesc.modop of</line>
<line>        when <a link="MemAtomicOp_BIC" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_BIC</a> newvalue = oldvalue AND NOT(operand);</line>
<line>        when <a link="MemAtomicOp_ORR" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_ORR</a> newvalue = oldvalue OR operand;</line>
<line>        when <a link="MemAtomicOp_SWP" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_SWP</a> newvalue = operand;</line>
<line>        when <a link="MemAtomicOp_CAS" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_CAS</a> newvalue = operand; cmpfail = oldvalue != cmpoperand;</line>
<line></line>
<line>    if cmpfail then</line>
<line>        nzcv = '1010'; // N = 1 indicates compare failure</line>
<line>    else</line>
<line>        nzcv = <a link="impl-aarch64.RCWCheck.3" file="shared_pseudocode.xml" hover="function: bits(4) RCWCheck(bits(N) old, bits(N) new, boolean soft)">RCWCheck</a>(oldvalue, newvalue, accdesc.rcws);</line>
<line></line>
<line>    if <a link="impl-shared.HaveMTEStoreOnlyExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEStoreOnlyExt()">HaveMTEStoreOnlyExt</a>() &amp;&amp; <a link="impl-aarch64.StoreOnlyTagCheckingEnabled.0" file="shared_pseudocode.xml" hover="function: boolean StoreOnlyTagCheckingEnabled()">StoreOnlyTagCheckingEnabled</a>() then</line>
<line>        // If the compare on a CAS fails, then it is CONSTRAINED UNPREDICTABLE whether the</line>
<line>        // Tag check is performed.</line>
<line>        if accdesc.tagchecked &amp;&amp; cmpfail then</line>
<line>            accdesc.tagchecked = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_STOREONLYTAGCHECKEDCAS" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_STOREONLYTAGCHECKEDCAS</a>);</line>
<line></line>
<line>        if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; accdesc.tagchecked then</line>
<line>            bits(4) ptag = <a link="AArch64.PhysicalTag.1" file="shared_pseudocode.xml" hover="function: bits(4) AArch64.PhysicalTag(bits(64) vaddr)">AArch64.PhysicalTag</a>(address);</line>
<line>            if !<a link="AArch64.CheckTag.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.CheckTag(AddressDescriptor memaddrdesc, AccessDescriptor accdesc, bits(4) ptag)">AArch64.CheckTag</a>(memaddrdesc, accdesc, ptag) then</line>
<line>                accdesc.read = FALSE; // Tag Check Fault on a write.</line>
<line>                <a link="AArch64.TagCheckFault.2" file="shared_pseudocode.xml" hover="function: AArch64.TagCheckFault(bits(64) vaddress, AccessDescriptor accdesc)">AArch64.TagCheckFault</a>(address, accdesc);</line>
<line></line>
<line>    if nzcv == '0010' then</line>
<line>        if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(accdesc.acctype) then</line>
<line>            newvalue = <a link="impl-shared.BigEndianReverse.1" file="shared_pseudocode.xml" hover="function: bits(width) BigEndianReverse (bits(width) value)">BigEndianReverse</a>(newvalue);</line>
<line></line>
<line>        memstatus = <a link="impl-shared.PhysMemWrite.4" file="shared_pseudocode.xml" hover="function: PhysMemRetStatus PhysMemWrite(AddressDescriptor desc, integer size, AccessDescriptor accdesc, bits(8*size) value)">PhysMemWrite</a>(memaddrdesc, bytes, accdesc, newvalue);</line>
<line></line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>            <a link="impl-shared.HandleExternalWriteAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalWriteAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalWriteAbort</a>(memstatus, memaddrdesc, bytes, accdesc);</line>
<line></line>
<line>    return (nzcv, oldvalue);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/MemLoad64B" mylink="aarch64.functions.memory.MemLoad64B" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemLoad64B()</line>
<line>// ============</line>
<line>// Performs an atomic 64-byte read from a given virtual address.</line>
<line></line>
<line link="impl-aarch64.MemLoad64B.2" hover="function: bits(512) MemLoad64B(bits(64) address, AccessDescriptor accdesc_in)" conts="MemLoad64B">bits(512) <anchor link="impl-aarch64.MemLoad64B.2" hover="function: bits(512) MemLoad64B(bits(64) address, AccessDescriptor accdesc_in)">MemLoad64B</anchor>(bits(64) address, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc_in)</line>
<line>    bits(512) data;</line>
<line>    constant integer size = 64;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = accdesc_in;</line>
<line>    boolean aligned = <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, size);</line>
<line></line>
<line>    if !aligned &amp;&amp; <a link="AArch64.UnalignedAccessFaults.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.UnalignedAccessFaults(AccessDescriptor accdesc, bits(64) address, integer size)">AArch64.UnalignedAccessFaults</a>(accdesc, address, size) then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    // If the instruction encoding permits tag checking, confer with system register configuration</line>
<line>    // which may override this.</line>
<line>    if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; accdesc.tagchecked then</line>
<line>        accdesc.tagchecked = <a link="AArch64.AccessIsTagChecked.2" file="shared_pseudocode.xml" hover="function: boolean AArch64.AccessIsTagChecked(bits(64) vaddr, AccessDescriptor accdesc)">AArch64.AccessIsTagChecked</a>(address, accdesc);</line>
<line></line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc = <a link="AArch64.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch64.TranslateAddress(bits(64) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch64.TranslateAddress</a>(address, accdesc, aligned, size);</line>
<line></line>
<line>    // Check for aborts or debug exceptions</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, memaddrdesc.fault);</line>
<line></line>
<line>    // Effect on exclusives</line>
<line>    if memaddrdesc.memattrs.shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then</line>
<line>        <a link="impl-shared.ClearExclusiveByAddress.3" file="shared_pseudocode.xml" hover="function: ClearExclusiveByAddress(FullAddress paddress, integer processorid, integer size)">ClearExclusiveByAddress</a>(memaddrdesc.paddress, <a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>(), size);</line>
<line></line>
<line>    if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; accdesc.tagchecked then</line>
<line>        bits(4) ptag = <a link="AArch64.PhysicalTag.1" file="shared_pseudocode.xml" hover="function: bits(4) AArch64.PhysicalTag(bits(64) vaddr)">AArch64.PhysicalTag</a>(address);</line>
<line>        if !<a link="AArch64.CheckTag.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.CheckTag(AddressDescriptor memaddrdesc, AccessDescriptor accdesc, bits(4) ptag)">AArch64.CheckTag</a>(memaddrdesc, accdesc, ptag) then</line>
<line>            <a link="AArch64.TagCheckFault.2" file="shared_pseudocode.xml" hover="function: AArch64.TagCheckFault(bits(64) vaddress, AccessDescriptor accdesc)">AArch64.TagCheckFault</a>(address, accdesc);</line>
<line></line>
<line>    if !<a link="impl-aarch64.AddressSupportsLS64.1" file="shared_pseudocode.xml" hover="function: boolean AddressSupportsLS64(bits(56) paddress)">AddressSupportsLS64</a>(memaddrdesc.paddress.address) then</line>
<line>        c = <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_LS64UNSUPPORTED" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_LS64UNSUPPORTED</a>);</line>
<line>        assert c IN {<a link="Constraint_LIMITED_ATOMICITY" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_LIMITED_ATOMICITY</a>, <a link="Constraint_FAULT" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_FAULT</a>};</line>
<line></line>
<line>        if c == <a link="Constraint_FAULT" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_FAULT</a> then</line>
<line>            // Generate a stage 1 Data Abort reported using the DFSC code of 110101.</line>
<line>            <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, <a link="impl-shared.ExclusiveFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord ExclusiveFault(AccessDescriptor accdesc)">ExclusiveFault</a>(accdesc));</line>
<line>        else</line>
<line>            // Accesses are not single-copy atomic above the byte level.</line>
<line>            for i = 0 to size-1</line>
<line>                <a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> memstatus;</line>
<line>                (memstatus, data&lt;8*i+7:8*i&gt;) = <a link="impl-shared.PhysMemRead.3" file="shared_pseudocode.xml" hover="function: (PhysMemRetStatus, bits(8*size)) PhysMemRead(AddressDescriptor desc, integer size, AccessDescriptor accdesc)">PhysMemRead</a>(memaddrdesc, 1, accdesc);</line>
<line>                if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>                    <a link="impl-shared.HandleExternalReadAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalReadAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalReadAbort</a>(memstatus, memaddrdesc, 1, accdesc);</line>
<line></line>
<line>                memaddrdesc.paddress.address = memaddrdesc.paddress.address + 1;</line>
<line>    else</line>
<line>        <a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> memstatus;</line>
<line>        (memstatus, data) = <a link="impl-shared.PhysMemRead.3" file="shared_pseudocode.xml" hover="function: (PhysMemRetStatus, bits(8*size)) PhysMemRead(AddressDescriptor desc, integer size, AccessDescriptor accdesc)">PhysMemRead</a>(memaddrdesc, size, accdesc);</line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>            <a link="impl-shared.HandleExternalReadAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalReadAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalReadAbort</a>(memstatus, memaddrdesc, size, accdesc);</line>
<line></line>
<line>    return data;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/MemStore64B" mylink="aarch64.functions.memory.MemStore64B" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemStore64B()</line>
<line>// =============</line>
<line>// Performs an atomic 64-byte store to a given virtual address. Function does</line>
<line>// not return the status of the store.</line>
<line></line>
<line link="impl-aarch64.MemStore64B.3" hover="function: MemStore64B(bits(64) address, bits(512) value, AccessDescriptor accdesc_in)" conts="MemStore64B"><anchor link="impl-aarch64.MemStore64B.3" hover="function: MemStore64B(bits(64) address, bits(512) value, AccessDescriptor accdesc_in)">MemStore64B</anchor>(bits(64) address, bits(512) value, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc_in)</line>
<line>    constant integer size = 64;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = accdesc_in;</line>
<line>    boolean aligned = <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, size);</line>
<line></line>
<line>    if !aligned &amp;&amp; <a link="AArch64.UnalignedAccessFaults.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.UnalignedAccessFaults(AccessDescriptor accdesc, bits(64) address, integer size)">AArch64.UnalignedAccessFaults</a>(accdesc, address, size) then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    // If the instruction encoding permits tag checking, confer with system register configuration</line>
<line>    // which may override this.</line>
<line>    if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; accdesc.tagchecked then</line>
<line>        accdesc.tagchecked = <a link="AArch64.AccessIsTagChecked.2" file="shared_pseudocode.xml" hover="function: boolean AArch64.AccessIsTagChecked(bits(64) vaddr, AccessDescriptor accdesc)">AArch64.AccessIsTagChecked</a>(address, accdesc);</line>
<line></line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc = <a link="AArch64.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch64.TranslateAddress(bits(64) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch64.TranslateAddress</a>(address, accdesc, aligned, size);</line>
<line></line>
<line>    // Check for aborts or debug exceptions</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, memaddrdesc.fault);</line>
<line></line>
<line>    // Effect on exclusives</line>
<line>    if memaddrdesc.memattrs.shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then</line>
<line>        <a link="impl-shared.ClearExclusiveByAddress.3" file="shared_pseudocode.xml" hover="function: ClearExclusiveByAddress(FullAddress paddress, integer processorid, integer size)">ClearExclusiveByAddress</a>(memaddrdesc.paddress, <a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>(), 64);</line>
<line></line>
<line>    if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; accdesc.tagchecked then</line>
<line>        bits(4) ptag = <a link="AArch64.PhysicalTag.1" file="shared_pseudocode.xml" hover="function: bits(4) AArch64.PhysicalTag(bits(64) vaddr)">AArch64.PhysicalTag</a>(address);</line>
<line>        if !<a link="AArch64.CheckTag.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.CheckTag(AddressDescriptor memaddrdesc, AccessDescriptor accdesc, bits(4) ptag)">AArch64.CheckTag</a>(memaddrdesc, accdesc, ptag) then</line>
<line>            <a link="AArch64.TagCheckFault.2" file="shared_pseudocode.xml" hover="function: AArch64.TagCheckFault(bits(64) vaddress, AccessDescriptor accdesc)">AArch64.TagCheckFault</a>(address, accdesc);</line>
<line></line>
<line>    if !<a link="impl-aarch64.AddressSupportsLS64.1" file="shared_pseudocode.xml" hover="function: boolean AddressSupportsLS64(bits(56) paddress)">AddressSupportsLS64</a>(memaddrdesc.paddress.address) then</line>
<line>        c = <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_LS64UNSUPPORTED" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_LS64UNSUPPORTED</a>);</line>
<line>        assert c IN {<a link="Constraint_LIMITED_ATOMICITY" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_LIMITED_ATOMICITY</a>, <a link="Constraint_FAULT" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_FAULT</a>};</line>
<line></line>
<line>        if c == <a link="Constraint_FAULT" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_FAULT</a> then</line>
<line>            // Generate a Data Abort reported using the DFSC code of 110101.</line>
<line>            <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, <a link="impl-shared.ExclusiveFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord ExclusiveFault(AccessDescriptor accdesc)">ExclusiveFault</a>(accdesc));</line>
<line>        else</line>
<line>            // Accesses are not single-copy atomic above the byte level.</line>
<line>            for i = 0 to size-1</line>
<line>                memstatus = <a link="impl-shared.PhysMemWrite.4" file="shared_pseudocode.xml" hover="function: PhysMemRetStatus PhysMemWrite(AddressDescriptor desc, integer size, AccessDescriptor accdesc, bits(8*size) value)">PhysMemWrite</a>(memaddrdesc, 1, accdesc, value&lt;8*i+7:8*i&gt;);</line>
<line>                if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>                    <a link="impl-shared.HandleExternalWriteAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalWriteAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalWriteAbort</a>(memstatus, memaddrdesc, 1, accdesc);</line>
<line></line>
<line>                memaddrdesc.paddress.address = memaddrdesc.paddress.address+1;</line>
<line>    else</line>
<line>        memstatus = <a link="impl-shared.PhysMemWrite.4" file="shared_pseudocode.xml" hover="function: PhysMemRetStatus PhysMemWrite(AddressDescriptor desc, integer size, AccessDescriptor accdesc, bits(8*size) value)">PhysMemWrite</a>(memaddrdesc, size, accdesc, value);</line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>            <a link="impl-shared.HandleExternalWriteAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalWriteAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalWriteAbort</a>(memstatus, memaddrdesc, size, accdesc);</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/MemStore64BWithRet" mylink="aarch64.functions.memory.MemStore64BWithRet" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemStore64BWithRet()</line>
<line>// ====================</line>
<line>// Performs an atomic 64-byte store to a given virtual address returning</line>
<line>// the status value of the operation.</line>
<line></line>
<line link="impl-aarch64.MemStore64BWithRet.3" hover="function: bits(64) MemStore64BWithRet(bits(64) address, bits(512) value, AccessDescriptor accdesc_in)" conts="MemStore64BWithRet">bits(64) <anchor link="impl-aarch64.MemStore64BWithRet.3" hover="function: bits(64) MemStore64BWithRet(bits(64) address, bits(512) value, AccessDescriptor accdesc_in)">MemStore64BWithRet</anchor>(bits(64) address, bits(512) value, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc_in)</line>
<line>    constant integer size = 64;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = accdesc_in;</line>
<line>    boolean aligned = <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, size);</line>
<line></line>
<line>    if !aligned &amp;&amp; <a link="AArch64.UnalignedAccessFaults.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.UnalignedAccessFaults(AccessDescriptor accdesc, bits(64) address, integer size)">AArch64.UnalignedAccessFaults</a>(accdesc, address, size) then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));</line>
<line></line>
<line>    // If the instruction encoding permits tag checking, confer with system register configuration</line>
<line>    // which may override this.</line>
<line>    if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; accdesc.tagchecked then</line>
<line>        accdesc.tagchecked = <a link="AArch64.AccessIsTagChecked.2" file="shared_pseudocode.xml" hover="function: boolean AArch64.AccessIsTagChecked(bits(64) vaddr, AccessDescriptor accdesc)">AArch64.AccessIsTagChecked</a>(address, accdesc);</line>
<line></line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc = <a link="AArch64.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch64.TranslateAddress(bits(64) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch64.TranslateAddress</a>(address, accdesc, aligned, size);</line>
<line></line>
<line>    // Check for aborts or debug exceptions</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>        <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, memaddrdesc.fault);</line>
<line>        return <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('1', 64);</line>
<line></line>
<line>    // Effect on exclusives</line>
<line>    if memaddrdesc.memattrs.shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then</line>
<line>        <a link="impl-shared.ClearExclusiveByAddress.3" file="shared_pseudocode.xml" hover="function: ClearExclusiveByAddress(FullAddress paddress, integer processorid, integer size)">ClearExclusiveByAddress</a>(memaddrdesc.paddress, <a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>(), 64);</line>
<line></line>
<line>    if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; accdesc.tagchecked then</line>
<line>        bits(4) ptag = <a link="AArch64.PhysicalTag.1" file="shared_pseudocode.xml" hover="function: bits(4) AArch64.PhysicalTag(bits(64) vaddr)">AArch64.PhysicalTag</a>(address);</line>
<line>        if !<a link="AArch64.CheckTag.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.CheckTag(AddressDescriptor memaddrdesc, AccessDescriptor accdesc, bits(4) ptag)">AArch64.CheckTag</a>(memaddrdesc, accdesc, ptag) then</line>
<line>            <a link="AArch64.TagCheckFault.2" file="shared_pseudocode.xml" hover="function: AArch64.TagCheckFault(bits(64) vaddress, AccessDescriptor accdesc)">AArch64.TagCheckFault</a>(address, accdesc);</line>
<line>            return <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('1', 64);</line>
<line></line>
<line>    <a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> memstatus;</line>
<line>    memstatus = <a link="impl-shared.PhysMemWrite.4" file="shared_pseudocode.xml" hover="function: PhysMemRetStatus PhysMemWrite(AddressDescriptor desc, integer size, AccessDescriptor accdesc, bits(8*size) value)">PhysMemWrite</a>(memaddrdesc, size, accdesc, value);</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>        <a link="impl-shared.HandleExternalWriteAbort.4" file="shared_pseudocode.xml" hover="function: HandleExternalWriteAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalWriteAbort</a>(memstatus, memaddrdesc, size, accdesc);</line>
<line></line>
<line>    return memstatus.store64bstatus;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/MemStore64BWithRetStatus" mylink="aarch64.functions.memory.MemStore64BWithRetStatus" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemStore64BWithRetStatus()</line>
<line>// ==========================</line>
<line>// Generates the return status of memory write with ST64BV or ST64BV0</line>
<line>// instructions. The status indicates if the operation succeeded, failed,</line>
<line>// or was not supported at this memory location.</line>
<line></line>
<line link="impl-aarch64.MemStore64BWithRetStatus.0" hover="function: bits(64) MemStore64BWithRetStatus()" conts="MemStore64BWithRetStatus">bits(64) <anchor link="impl-aarch64.MemStore64BWithRetStatus.0" hover="function: bits(64) MemStore64BWithRetStatus()">MemStore64BWithRetStatus</anchor>();</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/NVMem" mylink="aarch64.functions.memory.NVMem" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// NVMem[] - non-assignment form</line>
<line>// =============================</line>
<line>// This function is the load memory access for the transformed System register read access</line>
<line>// when Enhanced Nested Virtualization is enabled with HCR_EL2.NV2 = 1.</line>
<line>// The address for the load memory access is calculated using</line>
<line>// the formula SignExtend(VNCR_EL2.BADDR : Offset&lt;11:0&gt;, 64) where,</line>
<line>//  * VNCR_EL2.BADDR holds the base address of the memory location, and</line>
<line>//  * Offset is the unique offset value defined architecturally for each System register that</line>
<line>//    supports transformation of register access to memory access.</line>
<line></line>
<line link="impl-aarch64.NVMem.read.1" hover="accessor: bits(64) NVMem[integer offset]" conts="NVMem">bits(64) <anchor link="impl-aarch64.NVMem.read.1" hover="accessor: bits(64) NVMem[integer offset]">NVMem</anchor>[integer offset]</line>
<line>    assert offset &gt; 0;</line>
<line>    constant integer size = 64;</line>
<line>    return <a link="impl-aarch64.NVMem.read.2" file="shared_pseudocode.xml" hover="accessor: bits(N) NVMem[integer offset, integer N]">NVMem</a>[offset, size];</line>
<line></line>
<line link="impl-aarch64.NVMem.read.2" hover="accessor: bits(N) NVMem[integer offset, integer N]" conts="NVMem">bits(N) <anchor link="impl-aarch64.NVMem.read.2" hover="accessor: bits(N) NVMem[integer offset, integer N]">NVMem</anchor>[integer offset, integer N]</line>
<line>    assert offset &gt; 0;</line>
<line>    assert N IN {64,128};</line>
<line>    bits(64) address = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(VNCR_EL2.BADDR:offset&lt;11:0&gt;, 64);</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescNV2.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescNV2(MemOp memop)">CreateAccDescNV2</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>);</line>
<line>    return <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[address, N DIV 8, accdesc];</line>
<line></line>
<line>// NVMem[] - assignment form</line>
<line>// =========================</line>
<line>// This function is the store memory access for the transformed System register write access</line>
<line>// when Enhanced Nested Virtualization is enabled with HCR_EL2.NV2 = 1.</line>
<line>// The address for the store memory access is calculated using</line>
<line>// the formula SignExtend(VNCR_EL2.BADDR : Offset&lt;11:0&gt;, 64) where,</line>
<line>//  * VNCR_EL2.BADDR holds the base address of the memory location, and</line>
<line>//  * Offset is the unique offset value defined architecturally for each System register that</line>
<line>//    supports transformation of register access to memory access.</line>
<line></line>
<line link="impl-aarch64.NVMem.write.1" hover="accessor: NVMem[integer offset] = bits(64) value" conts="NVMem"><anchor link="impl-aarch64.NVMem.write.1" hover="accessor: NVMem[integer offset] = bits(64) value">NVMem</anchor>[integer offset] = bits(64) value</line>
<line>    assert offset &gt; 0;</line>
<line>    constant integer size = 64;</line>
<line>    <a link="impl-aarch64.NVMem.write.2" file="shared_pseudocode.xml" hover="accessor: NVMem[integer offset, integer N] = bits(N) value">NVMem</a>[offset, size] = value;</line>
<line>    return;</line>
<line></line>
<line link="impl-aarch64.NVMem.write.2" hover="accessor: NVMem[integer offset, integer N] = bits(N) value" conts="NVMem"><anchor link="impl-aarch64.NVMem.write.2" hover="accessor: NVMem[integer offset, integer N] = bits(N) value">NVMem</anchor>[integer offset, integer N] = bits(N) value</line>
<line>    assert offset &gt; 0;</line>
<line>    assert N IN {64,128};</line>
<line>    bits(64) address = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(VNCR_EL2.BADDR:offset&lt;11:0&gt;, 64);</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescNV2.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescNV2(MemOp memop)">CreateAccDescNV2</a>(<a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>);</line>
<line>    Mem[address, N DIV 8, accdesc] = value;</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/PhysMemTagRead" mylink="aarch64.functions.memory.PhysMemTagRead" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PhysMemTagRead()</line>
<line>// ================</line>
<line>// This is the hardware operation which perform a single-copy atomic,</line>
<line>// Allocation Tag granule aligned, memory access from the tag in PA space.</line>
<line>//</line>
<line>// The function address the array using desc.paddress which supplies:</line>
<line>// * A 52-bit physical address</line>
<line>// * A single NS bit to select between Secure and Non-secure parts of the array.</line>
<line>//</line>
<line>// The accdesc descriptor describes the access type: normal, exclusive, ordered, streaming,</line>
<line>// etc and other parameters required to access the physical memory or for setting syndrome</line>
<line>// register in the event of an External abort.</line>
<line></line>
<line link="impl-aarch64.PhysMemTagRead.2" hover="function: (PhysMemRetStatus, bits(4)) PhysMemTagRead(AddressDescriptor desc, AccessDescriptor accdesc)" conts="PhysMemTagRead">(PhysMemRetStatus, bits(4)) <anchor link="impl-aarch64.PhysMemTagRead.2" hover="function: (PhysMemRetStatus, bits(4)) PhysMemTagRead(AddressDescriptor desc, AccessDescriptor accdesc)">PhysMemTagRead</anchor>(<a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> desc, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/PhysMemTagWrite" mylink="aarch64.functions.memory.PhysMemTagWrite" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PhysMemTagWrite()</line>
<line>// =================</line>
<line>// This is the hardware operation which perform a single-copy atomic,</line>
<line>// Allocation Tag granule aligned, memory access to the tag in PA space.</line>
<line>//</line>
<line>// The function address the array using desc.paddress which supplies:</line>
<line>// * A 52-bit physical address</line>
<line>// * A single NS bit to select between Secure and Non-secure parts of the array.</line>
<line>//</line>
<line>// The accdesc descriptor describes the access type: normal, exclusive, ordered, streaming,</line>
<line>// etc and other parameters required to access the physical memory or for setting syndrome</line>
<line>// register in the event of an External abort.</line>
<line></line>
<line link="impl-aarch64.PhysMemTagWrite.3" hover="function: PhysMemRetStatus PhysMemTagWrite(AddressDescriptor desc, AccessDescriptor accdesc, bits (4) value)" conts="PhysMemTagWrite">PhysMemRetStatus <anchor link="impl-aarch64.PhysMemTagWrite.3" hover="function: PhysMemRetStatus PhysMemTagWrite(AddressDescriptor desc, AccessDescriptor accdesc, bits (4) value)">PhysMemTagWrite</anchor>(<a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> desc, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, bits (4) value);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/memory/StoreOnlyTagCheckingEnabled" mylink="aarch64.functions.memory.StoreOnlyTagCheckingEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// StoreOnlyTagCheckingEnabled()</line>
<line>// =============================</line>
<line>// Returns TRUE if loads executed at the current Exception level are Tag unchecked.</line>
<line></line>
<line link="impl-aarch64.StoreOnlyTagCheckingEnabled.0" hover="function: boolean StoreOnlyTagCheckingEnabled()" conts="StoreOnlyTagCheckingEnabled">boolean <anchor link="impl-aarch64.StoreOnlyTagCheckingEnabled.0" hover="function: boolean StoreOnlyTagCheckingEnabled()">StoreOnlyTagCheckingEnabled</anchor>()</line>
<line>    assert <a link="impl-shared.HaveMTEStoreOnlyExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEStoreOnlyExt()">HaveMTEStoreOnlyExt</a>();</line>
<line>    bit tcso;</line>
<line></line>
<line>    case PSTATE.EL of</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>            if !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>                tcso = SCTLR_EL1.TCSO0;</line>
<line>            else</line>
<line>                tcso = SCTLR_EL2.TCSO0;</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            tcso = SCTLR_EL1.TCSO;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            tcso = SCTLR_EL2.TCSO;</line>
<line>        otherwise</line>
<line>            tcso = SCTLR_EL3.TCSO;</line>
<line></line>
<line>    return tcso == '1';</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/CPYFOptionA" mylink="aarch64.functions.mops.CPYFOptionA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CPYFOptionA()</line>
<line>// =============</line>
<line>// Returns TRUE if the implementation uses Option A for the</line>
<line>// CPYF* instructions, and FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.CPYFOptionA.0" hover="function: boolean CPYFOptionA()" conts="CPYFOptionA">boolean <anchor link="impl-aarch64.CPYFOptionA.0" hover="function: boolean CPYFOptionA()">CPYFOptionA</anchor>()</line>
<line>    return boolean IMPLEMENTATION_DEFINED "CPYF* instructions use Option A";</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/CPYOptionA" mylink="aarch64.functions.mops.CPYOptionA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CPYOptionA()</line>
<line>// ============</line>
<line>// Returns TRUE if the implementation uses Option A for the</line>
<line>// CPY* instructions, and FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.CPYOptionA.0" hover="function: boolean CPYOptionA()" conts="CPYOptionA">boolean <anchor link="impl-aarch64.CPYOptionA.0" hover="function: boolean CPYOptionA()">CPYOptionA</anchor>()</line>
<line>    return boolean IMPLEMENTATION_DEFINED "CPY* instructions use Option A";</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/CPYPostSizeChoice" mylink="aarch64.functions.mops.CPYPostSizeChoice" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CPYPostSizeChoice()</line>
<line>// ===================</line>
<line>// Returns the size of the copy that is performed by the CPYE* instructions for this</line>
<line>// implementation given the parameters of the destination, source and size of the copy.</line>
<line>// Postsize is encoded as -1*size for an option A implementation if cpysize is negative.</line>
<line></line>
<line link="impl-aarch64.CPYPostSizeChoice.3" hover="function: bits(64) CPYPostSizeChoice(bits(64) toaddress, bits(64) fromaddress, bits(64) cpysize)" conts="CPYPostSizeChoice">bits(64) <anchor link="impl-aarch64.CPYPostSizeChoice.3" hover="function: bits(64) CPYPostSizeChoice(bits(64) toaddress, bits(64) fromaddress, bits(64) cpysize)">CPYPostSizeChoice</anchor>(bits(64) toaddress, bits(64) fromaddress, bits(64) cpysize);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/CPYPreSizeChoice" mylink="aarch64.functions.mops.CPYPreSizeChoice" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CPYPreSizeChoice()</line>
<line>// ==================</line>
<line>// Returns the size of the copy that is performed by the CPYP* instructions for this</line>
<line>// implementation given the parameters of the destination, source and size of the copy.</line>
<line>// Presize is encoded as -1*size for an option A implementation if cpysize is negative.</line>
<line></line>
<line link="impl-aarch64.CPYPreSizeChoice.3" hover="function: bits(64) CPYPreSizeChoice(bits(64) toaddress, bits(64) fromaddress, bits(64) cpysize)" conts="CPYPreSizeChoice">bits(64) <anchor link="impl-aarch64.CPYPreSizeChoice.3" hover="function: bits(64) CPYPreSizeChoice(bits(64) toaddress, bits(64) fromaddress, bits(64) cpysize)">CPYPreSizeChoice</anchor>(bits(64) toaddress, bits(64) fromaddress, bits(64) cpysize);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/CPYSizeChoice" mylink="aarch64.functions.mops.CPYSizeChoice" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CPYSizeChoice()</line>
<line>// ===============</line>
<line>// Returns the size of the block this performed for an iteration of the copy given the</line>
<line>// parameters of the destination, source and size of the copy.</line>
<line></line>
<line link="impl-aarch64.CPYSizeChoice.3" hover="function: integer CPYSizeChoice(bits(64) toaddress, bits(64) fromaddress, bits(64) cpysize)" conts="CPYSizeChoice">integer <anchor link="impl-aarch64.CPYSizeChoice.3" hover="function: integer CPYSizeChoice(bits(64) toaddress, bits(64) fromaddress, bits(64) cpysize)">CPYSizeChoice</anchor>(bits(64) toaddress, bits(64) fromaddress, bits(64) cpysize);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/CheckMOPSEnabled" mylink="aarch64.functions.mops.CheckMOPSEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckMOPSEnabled()</line>
<line>// ==================</line>
<line>// Check for EL0 and EL1 access to the CPY* and SET* instructions.</line>
<line></line>
<line link="impl-aarch64.CheckMOPSEnabled.0" hover="function: CheckMOPSEnabled()" conts="CheckMOPSEnabled"><anchor link="impl-aarch64.CheckMOPSEnabled.0" hover="function: CheckMOPSEnabled()">CheckMOPSEnabled</anchor>()</line>
<line>    if (PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>        (HCR_EL2.TGE == '0' || HCR_EL2.E2H == '0') &amp;&amp;</line>
<line>        (!<a link="impl-aarch64.IsHCRXEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsHCRXEL2Enabled()">IsHCRXEL2Enabled</a>() || HCRX_EL2.MSCEn == '0')) then</line>
<line>        UNDEFINED;</line>
<line></line>
<line>    if (PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; SCTLR_EL1.MSCEn == '0' &amp;&amp;</line>
<line>        (!<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() || HCR_EL2.TGE == '0' || HCR_EL2.E2H == '0')) then</line>
<line>        UNDEFINED;</line>
<line></line>
<line>    if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() &amp;&amp; SCTLR_EL2.MSCEn == '0' then</line>
<line>        UNDEFINED;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/MOPSStage" mylink="aarch64.functions.mops.MOPSStage" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MOPSStage</line>
<line>// =========</line>
<line></line>
<line link="MOPSStage" hover="enumeration MOPSStage { MOPSStage_Prologue, MOPSStage_Main, MOPSStage_Epilogue }" conts="MOPSStage">enumeration <anchor link="MOPSStage" hover="enumeration MOPSStage { MOPSStage_Prologue, MOPSStage_Main, MOPSStage_Epilogue }">MOPSStage</anchor> { <anchor link="MOPSStage_Prologue" hover="enumeration MOPSStage { MOPSStage_Prologue, MOPSStage_Main, MOPSStage_Epilogue }">MOPSStage_Prologue</anchor>, <anchor link="MOPSStage_Main" hover="enumeration MOPSStage { MOPSStage_Prologue, MOPSStage_Main, MOPSStage_Epilogue }">MOPSStage_Main</anchor>, <anchor link="MOPSStage_Epilogue" hover="enumeration MOPSStage { MOPSStage_Prologue, MOPSStage_Main, MOPSStage_Epilogue }">MOPSStage_Epilogue</anchor> };</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/MaxBlockSizeCopiedBytes" mylink="aarch64.functions.mops.MaxBlockSizeCopiedBytes" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MaxBlockSizeCopiedBytes()</line>
<line>// =========================</line>
<line>// Returns the maximum number of bytes that can used in a single block of the copy.</line>
<line></line>
<line link="impl-aarch64.MaxBlockSizeCopiedBytes.0" hover="function: integer MaxBlockSizeCopiedBytes()" conts="MaxBlockSizeCopiedBytes">integer <anchor link="impl-aarch64.MaxBlockSizeCopiedBytes.0" hover="function: integer MaxBlockSizeCopiedBytes()">MaxBlockSizeCopiedBytes</anchor>()</line>
<line>    return integer IMPLEMENTATION_DEFINED "Maximum bytes used in a single block of a copy";</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/MemCpyDirectionChoice" mylink="aarch64.functions.mops.MemCpyDirectionChoice" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemCpyDirectionChoice()</line>
<line>// =======================</line>
<line>// Returns true if in the non-overlapping case of a memcpy of size cpysize bytes</line>
<line>// from the source address fromaddress to destination address toaddress is done</line>
<line>// in the forward direction on this implementation.</line>
<line></line>
<line link="impl-aarch64.MemCpyDirectionChoice.3" hover="function: boolean MemCpyDirectionChoice(bits(64) fromaddress, bits(64) toaddress, bits(64) cpysize)" conts="MemCpyDirectionChoice">boolean <anchor link="impl-aarch64.MemCpyDirectionChoice.3" hover="function: boolean MemCpyDirectionChoice(bits(64) fromaddress, bits(64) toaddress, bits(64) cpysize)">MemCpyDirectionChoice</anchor>(bits(64) fromaddress, bits(64) toaddress, bits(64) cpysize);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/MemCpyParametersIllformedE" mylink="aarch64.functions.mops.MemCpyParametersIllformedE" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemCpyParametersIllformedE()</line>
<line>// ============================</line>
<line>// Returns TRUE if the inputs are not well formed (in terms of their size and/or alignment)</line>
<line>// for a CPYE* instruction for this implementation given the parameters of the destination,</line>
<line>// source and size of the copy.</line>
<line></line>
<line link="impl-aarch64.MemCpyParametersIllformedE.3" hover="function: boolean MemCpyParametersIllformedE(bits(64) toaddress, bits(64) fromaddress, bits(64) cpysize)" conts="MemCpyParametersIllformedE">boolean <anchor link="impl-aarch64.MemCpyParametersIllformedE.3" hover="function: boolean MemCpyParametersIllformedE(bits(64) toaddress, bits(64) fromaddress, bits(64) cpysize)">MemCpyParametersIllformedE</anchor>(bits(64) toaddress, bits(64) fromaddress,</line>
<line>                                   bits(64) cpysize);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/MemCpyParametersIllformedM" mylink="aarch64.functions.mops.MemCpyParametersIllformedM" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemCpyParametersIllformedM()</line>
<line>// ============================</line>
<line>// Returns TRUE if the inputs are not well formed (in terms of their size and/or alignment)</line>
<line>// for a CPYM* instruction for this implementation given the parameters of the destination,</line>
<line>// source and size of the copy.</line>
<line></line>
<line link="impl-aarch64.MemCpyParametersIllformedM.3" hover="function: boolean MemCpyParametersIllformedM(bits(64) toaddress, bits(64) fromaddress, bits(64) cpysize)" conts="MemCpyParametersIllformedM">boolean <anchor link="impl-aarch64.MemCpyParametersIllformedM.3" hover="function: boolean MemCpyParametersIllformedM(bits(64) toaddress, bits(64) fromaddress, bits(64) cpysize)">MemCpyParametersIllformedM</anchor>(bits(64) toaddress, bits(64) fromaddress,</line>
<line>                                   bits(64) cpysize);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/MemCpyZeroSizeCheck" mylink="aarch64.functions.mops.MemCpyZeroSizeCheck" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemCpyZeroSizeCheck()</line>
<line>// =====================</line>
<line>// Returns TRUE if the implementation option is checked on a copy of size zero remaining.</line>
<line></line>
<line link="impl-aarch64.MemCpyZeroSizeCheck.0" hover="function: boolean MemCpyZeroSizeCheck()" conts="MemCpyZeroSizeCheck">boolean <anchor link="impl-aarch64.MemCpyZeroSizeCheck.0" hover="function: boolean MemCpyZeroSizeCheck()">MemCpyZeroSizeCheck</anchor>();</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/MemSetParametersIllformedE" mylink="aarch64.functions.mops.MemSetParametersIllformedE" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemSetParametersIllformedE()</line>
<line>// ============================</line>
<line>// Returns TRUE if the inputs are not well formed (in terms of their size and/or</line>
<line>// alignment) for a SETE* or SETGE* instruction for this implementation given the</line>
<line>// parameters of the destination and size of the set.</line>
<line></line>
<line link="impl-aarch64.MemSetParametersIllformedE.3" hover="function: boolean MemSetParametersIllformedE(bits(64) toaddress, bits(64) setsize, boolean IsSETGE)" conts="MemSetParametersIllformedE">boolean <anchor link="impl-aarch64.MemSetParametersIllformedE.3" hover="function: boolean MemSetParametersIllformedE(bits(64) toaddress, bits(64) setsize, boolean IsSETGE)">MemSetParametersIllformedE</anchor>(bits(64) toaddress, bits(64) setsize,</line>
<line>                                   boolean IsSETGE);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/MemSetParametersIllformedM" mylink="aarch64.functions.mops.MemSetParametersIllformedM" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemSetParametersIllformedM()</line>
<line>// ============================</line>
<line>// Returns TRUE if the inputs are not well formed (in terms of their size and/or</line>
<line>// alignment) for a SETM* or SETGM* instruction for this implementation given the</line>
<line>// parameters of the destination and size of the copy.</line>
<line></line>
<line link="impl-aarch64.MemSetParametersIllformedM.3" hover="function: boolean MemSetParametersIllformedM(bits(64) toaddress, bits(64) setsize, boolean IsSETGM)" conts="MemSetParametersIllformedM">boolean <anchor link="impl-aarch64.MemSetParametersIllformedM.3" hover="function: boolean MemSetParametersIllformedM(bits(64) toaddress, bits(64) setsize, boolean IsSETGM)">MemSetParametersIllformedM</anchor>(bits(64) toaddress, bits(64) setsize,</line>
<line>                                   boolean IsSETGM);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/MemSetZeroSizeCheck" mylink="aarch64.functions.mops.MemSetZeroSizeCheck" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemSetZeroSizeCheck()</line>
<line>// =====================</line>
<line>// Returns TRUE if the implementation option is checked on a copy of size zero remaining.</line>
<line></line>
<line link="impl-aarch64.MemSetZeroSizeCheck.0" hover="function: boolean MemSetZeroSizeCheck()" conts="MemSetZeroSizeCheck">boolean <anchor link="impl-aarch64.MemSetZeroSizeCheck.0" hover="function: boolean MemSetZeroSizeCheck()">MemSetZeroSizeCheck</anchor>();</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/MismatchedCpySetTargetEL" mylink="aarch64.functions.mops.MismatchedCpySetTargetEL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MismatchedCpySetTargetEL()</line>
<line>// ==========================</line>
<line>// Return the target exception level for an Exception_MemCpyMemSet.</line>
<line></line>
<line link="impl-aarch64.MismatchedCpySetTargetEL.0" hover="function: bits(2) MismatchedCpySetTargetEL()" conts="MismatchedCpySetTargetEL">bits(2) <anchor link="impl-aarch64.MismatchedCpySetTargetEL.0" hover="function: bits(2) MismatchedCpySetTargetEL()">MismatchedCpySetTargetEL</anchor>()</line>
<line>    bits(2) target_el;</line>
<line></line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>        target_el = PSTATE.EL;</line>
<line>    elsif PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1' then</line>
<line>        target_el = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>    elsif (PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>        <a link="impl-aarch64.IsHCRXEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsHCRXEL2Enabled()">IsHCRXEL2Enabled</a>() &amp;&amp; HCRX_EL2.MCE2 == '1') then</line>
<line>        target_el = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>    else</line>
<line>        target_el = <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line></line>
<line>    return target_el;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/MismatchedMemCpyException" mylink="aarch64.functions.mops.MismatchedMemCpyException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MismatchedMemCpyException()</line>
<line>// ===========================</line>
<line>// Generates an exception for a CPY* instruction if the version</line>
<line>// is inconsistent with the state of the call.</line>
<line></line>
<line link="impl-aarch64.MismatchedMemCpyException.7" hover="function: MismatchedMemCpyException(boolean option_a, integer destreg, integer srcreg, integer sizereg, boolean wrong_option, boolean from_epilogue, bits(4) options)" conts="MismatchedMemCpyException"><anchor link="impl-aarch64.MismatchedMemCpyException.7" hover="function: MismatchedMemCpyException(boolean option_a, integer destreg, integer srcreg, integer sizereg, boolean wrong_option, boolean from_epilogue, bits(4) options)">MismatchedMemCpyException</anchor>(boolean option_a, integer destreg, integer srcreg, integer sizereg,</line>
<line>                          boolean wrong_option, boolean from_epilogue, bits(4) options)</line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    integer vect_offset = 0x0;</line>
<line>    bits(2) target_el = <a link="impl-aarch64.MismatchedCpySetTargetEL.0" file="shared_pseudocode.xml" hover="function: bits(2) MismatchedCpySetTargetEL()">MismatchedCpySetTargetEL</a>();</line>
<line></line>
<line>    <a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_MemCpyMemSet" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_MemCpyMemSet</a>);</line>
<line>    exception.syndrome&lt;24&gt;    = '0';</line>
<line>    exception.syndrome&lt;23&gt;    = '0';</line>
<line>    exception.syndrome&lt;22:19&gt; = options;</line>
<line>    exception.syndrome&lt;18&gt;    = if from_epilogue then '1' else '0';</line>
<line>    exception.syndrome&lt;17&gt;    = if wrong_option then '1' else '0';</line>
<line>    exception.syndrome&lt;16&gt;    = if option_a then '1' else '0';</line>
<line>    // exception.syndrome&lt;15&gt; is RES0</line>
<line>    exception.syndrome&lt;14:10&gt; = destreg&lt;4:0&gt;;</line>
<line>    exception.syndrome&lt;9:5&gt;   = srcreg&lt;4:0&gt;;</line>
<line>    exception.syndrome&lt;4:0&gt;   = sizereg&lt;4:0&gt;;</line>
<line></line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(target_el, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/MismatchedMemSetException" mylink="aarch64.functions.mops.MismatchedMemSetException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MismatchedMemSetException()</line>
<line>// ===========================</line>
<line>// Generates an exception for a SET* instruction if the version</line>
<line>// is inconsistent with the state of the call.</line>
<line></line>
<line link="impl-aarch64.MismatchedMemSetException.8" hover="function: MismatchedMemSetException(boolean option_a, integer destreg, integer datareg, integer sizereg, boolean wrong_option, boolean from_epilogue, bits(2) options, boolean is_SETG)" conts="MismatchedMemSetException"><anchor link="impl-aarch64.MismatchedMemSetException.8" hover="function: MismatchedMemSetException(boolean option_a, integer destreg, integer datareg, integer sizereg, boolean wrong_option, boolean from_epilogue, bits(2) options, boolean is_SETG)">MismatchedMemSetException</anchor>(boolean option_a, integer destreg, integer datareg, integer sizereg,</line>
<line>                          boolean wrong_option, boolean from_epilogue, bits(2) options,</line>
<line>                          boolean is_SETG)</line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    integer vect_offset = 0x0;</line>
<line>    bits(2) target_el = <a link="impl-aarch64.MismatchedCpySetTargetEL.0" file="shared_pseudocode.xml" hover="function: bits(2) MismatchedCpySetTargetEL()">MismatchedCpySetTargetEL</a>();</line>
<line></line>
<line>    <a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_MemCpyMemSet" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_MemCpyMemSet</a>);</line>
<line>    exception.syndrome&lt;24&gt;    = '1';</line>
<line>    exception.syndrome&lt;23&gt;    = if is_SETG then '1' else '0';</line>
<line>    // exception.syndrome&lt;22:21&gt; is RES0</line>
<line>    exception.syndrome&lt;20:19&gt; = options;</line>
<line>    exception.syndrome&lt;18&gt;    = if from_epilogue then '1' else '0';</line>
<line>    exception.syndrome&lt;17&gt;    = if wrong_option then '1' else '0';</line>
<line>    exception.syndrome&lt;16&gt;    = if option_a then '1' else '0';</line>
<line>    // exception.syndrome&lt;15&gt; is RES0</line>
<line>    exception.syndrome&lt;14:10&gt; = destreg&lt;4:0&gt;;</line>
<line>    exception.syndrome&lt;9:5&gt;   = datareg&lt;4:0&gt;;</line>
<line>    exception.syndrome&lt;4:0&gt;   = sizereg&lt;4:0&gt;;</line>
<line></line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(target_el, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/SETGOptionA" mylink="aarch64.functions.mops.SETGOptionA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SETGOptionA()</line>
<line>// =============</line>
<line>// Returns TRUE if the implementation uses Option A for the</line>
<line>// SETG* instructions, and FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.SETGOptionA.0" hover="function: boolean SETGOptionA()" conts="SETGOptionA">boolean <anchor link="impl-aarch64.SETGOptionA.0" hover="function: boolean SETGOptionA()">SETGOptionA</anchor>()</line>
<line>    return boolean IMPLEMENTATION_DEFINED "SETG* instructions use Option A";</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/SETOptionA" mylink="aarch64.functions.mops.SETOptionA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SETOptionA()</line>
<line>// ============</line>
<line>// Returns TRUE if the implementation uses Option A for the</line>
<line>// SET* instructions, and FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.SETOptionA.0" hover="function: boolean SETOptionA()" conts="SETOptionA">boolean <anchor link="impl-aarch64.SETOptionA.0" hover="function: boolean SETOptionA()">SETOptionA</anchor>()</line>
<line>    return boolean IMPLEMENTATION_DEFINED "SET* instructions use Option A";</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/SETPostSizeChoice" mylink="aarch64.functions.mops.SETPostSizeChoice" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SETPostSizeChoice()</line>
<line>// ===================</line>
<line>// Returns the size of the set that is performed by the SETE* or SETGE* instructions</line>
<line>// for this implementation, given the parameters of the destination and size of the set.</line>
<line>// Postsize is encoded as -1*size for an option A implementation if setsize is negative.</line>
<line></line>
<line link="impl-aarch64.SETPostSizeChoice.3" hover="function: bits(64) SETPostSizeChoice(bits(64) toaddress, bits(64) setsize, boolean IsSETGE)" conts="SETPostSizeChoice">bits(64) <anchor link="impl-aarch64.SETPostSizeChoice.3" hover="function: bits(64) SETPostSizeChoice(bits(64) toaddress, bits(64) setsize, boolean IsSETGE)">SETPostSizeChoice</anchor>(bits(64) toaddress, bits(64) setsize, boolean IsSETGE);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/SETPreSizeChoice" mylink="aarch64.functions.mops.SETPreSizeChoice" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SETPreSizeChoice()</line>
<line>// ==================</line>
<line>// Returns the size of the set that is performed by the SETP* or SETGP* instructions</line>
<line>// for this implementation, given the parameters of the destination and size of the set.</line>
<line>// Presize is encoded as -1*size for an option A implementation if setsize is negative.</line>
<line></line>
<line link="impl-aarch64.SETPreSizeChoice.3" hover="function: bits(64) SETPreSizeChoice(bits(64) toaddress, bits(64) setsize, boolean IsSETGP)" conts="SETPreSizeChoice">bits(64) <anchor link="impl-aarch64.SETPreSizeChoice.3" hover="function: bits(64) SETPreSizeChoice(bits(64) toaddress, bits(64) setsize, boolean IsSETGP)">SETPreSizeChoice</anchor>(bits(64) toaddress, bits(64) setsize, boolean IsSETGP);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/mops/SETSizeChoice" mylink="aarch64.functions.mops.SETSizeChoice" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SETSizeChoice()</line>
<line>// ===============</line>
<line>// Returns the size of the block thisperformed for an iteration of the set given</line>
<line>// the parameters of the destination and size of the set. The size of the block</line>
<line>// is an integer multiple of AlignSize.</line>
<line></line>
<line link="impl-aarch64.SETSizeChoice.3" hover="function: integer SETSizeChoice(bits(64) toaddress, bits(64) setsize, integer AlignSize)" conts="SETSizeChoice">integer <anchor link="impl-aarch64.SETSizeChoice.3" hover="function: integer SETSizeChoice(bits(64) toaddress, bits(64) setsize, integer AlignSize)">SETSizeChoice</anchor>(bits(64) toaddress, bits(64) setsize, integer AlignSize);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/addpac/AddPAC" mylink="aarch64.functions.pac.addpac.AddPAC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AddPAC()</line>
<line>// ========</line>
<line>// Calculates the pointer authentication code for a 64-bit quantity and then</line>
<line>// inserts that into pointer authentication code field of that 64-bit quantity.</line>
<line></line>
<line link="impl-aarch64.AddPAC.4" hover="function: bits(64) AddPAC(bits(64) ptr, bits(64) modifier, bits(128) K, boolean data)" conts="AddPAC">bits(64) <anchor link="impl-aarch64.AddPAC.4" hover="function: bits(64) AddPAC(bits(64) ptr, bits(64) modifier, bits(128) K, boolean data)">AddPAC</anchor>(bits(64) ptr, bits(64) modifier, bits(128) K, boolean data)</line>
<line>    bits(64) PAC;</line>
<line>    bits(64) result;</line>
<line>    bits(64) ext_ptr;</line>
<line>    bits(64) extfield;</line>
<line>    bit selbit;</line>
<line>    boolean isgeneric = FALSE;</line>
<line>    boolean tbi = <a link="impl-shared.EffectiveTBI.3" file="shared_pseudocode.xml" hover="function: bit EffectiveTBI(bits(64) address, boolean IsInstr, bits(2) el)">EffectiveTBI</a>(ptr, !data, PSTATE.EL) == '1';</line>
<line>    boolean mtx = <a link="impl-shared.EffectiveMTX.3" file="shared_pseudocode.xml" hover="function: bit EffectiveMTX(bits(64) address, boolean is_instr, bits(2) el)">EffectiveMTX</a>(ptr, !data, PSTATE.EL) == '1';</line>
<line>    integer top_bit = if tbi then 55 else 63;</line>
<line></line>
<line>    // If tagged pointers are in use for a regime with two TTBRs, use bit&lt;55&gt; of</line>
<line>    // the pointer to select between upper and lower ranges, and preserve this.</line>
<line>    // This handles the awkward case where there is apparently no correct choice between</line>
<line>    // the upper and lower address range - ie an addr of 1xxxxxxx0... with TBI0=0 and TBI1=1</line>
<line>    // and 0xxxxxxx1 with TBI1=0 and TBI0=1:</line>
<line>    if <a link="impl-aarch64.PtrHasUpperAndLowerAddRanges.0" file="shared_pseudocode.xml" hover="function: boolean PtrHasUpperAndLowerAddRanges()">PtrHasUpperAndLowerAddRanges</a>() then</line>
<line>        assert <a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>() IN {<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>};</line>
<line>        if <a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>() == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> then</line>
<line>            // EL1 translation regime registers</line>
<line>            if data then</line>
<line>                if TCR_EL1.TBI1 == '1' || TCR_EL1.TBI0 == '1' then</line>
<line>                    selbit = ptr&lt;55&gt;;</line>
<line>                else</line>
<line>                    selbit = ptr&lt;63&gt;;</line>
<line>            else</line>
<line>                if ((TCR_EL1.TBI1 == '1' &amp;&amp; TCR_EL1.TBID1 == '0') ||</line>
<line>                    (TCR_EL1.TBI0 == '1' &amp;&amp; TCR_EL1.TBID0 == '0')) then</line>
<line>                    selbit = ptr&lt;55&gt;;</line>
<line>                else</line>
<line>                    selbit = ptr&lt;63&gt;;</line>
<line>        else</line>
<line>            // EL2 translation regime registers</line>
<line>            if data then</line>
<line>                if TCR_EL2.TBI1 == '1' || TCR_EL2.TBI0 == '1' then</line>
<line>                    selbit = ptr&lt;55&gt;;</line>
<line>                else</line>
<line>                    selbit = ptr&lt;63&gt;;</line>
<line>            else</line>
<line>                if ((TCR_EL2.TBI1 == '1' &amp;&amp; TCR_EL2.TBID1 == '0') ||</line>
<line>                    (TCR_EL2.TBI0 == '1' &amp;&amp; TCR_EL2.TBID0 == '0')) then</line>
<line>                    selbit = ptr&lt;55&gt;;</line>
<line>                else</line>
<line>                    selbit = ptr&lt;63&gt;;</line>
<line>    else selbit = if tbi then ptr&lt;55&gt; else ptr&lt;63&gt;;</line>
<line></line>
<line>    if <a link="impl-aarch64.HaveEnhancedPAC2.0" file="shared_pseudocode.xml" hover="function: boolean HaveEnhancedPAC2()">HaveEnhancedPAC2</a>() &amp;&amp; <a link="impl-aarch64.ConstPACField.0" file="shared_pseudocode.xml" hover="function: boolean ConstPACField()">ConstPACField</a>() then selbit = ptr&lt;55&gt;;</line>
<line>    integer bottom_PAC_bit = <a link="impl-aarch64.CalculateBottomPACBit.1" file="shared_pseudocode.xml" hover="function: integer CalculateBottomPACBit(bit top_bit)">CalculateBottomPACBit</a>(selbit);</line>
<line></line>
<line>    // If the VA is 56 or 55 bits and Top Byte is Ignored,</line>
<line>    // there are no unused bits left to insert the PAC</line>
<line>    if tbi &amp;&amp; bottom_PAC_bit &gt;= 55 then</line>
<line>        return ptr;</line>
<line></line>
<line>    extfield = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(selbit, 64);</line>
<line></line>
<line>    // Compute the pointer authentication code for a ptr with good extension bits</line>
<line>    if tbi then</line>
<line>        ext_ptr = (ptr&lt;63:56&gt; :</line>
<line>                   extfield&lt;(56-bottom_PAC_bit)-1:0&gt; : ptr&lt;bottom_PAC_bit-1:0&gt;);</line>
<line>    elsif mtx then</line>
<line>        ext_ptr = (extfield&lt;63:60&gt; : ptr&lt;59:56&gt; :</line>
<line>                   extfield&lt;(56-bottom_PAC_bit)-1:0&gt; : ptr&lt;bottom_PAC_bit-1:0&gt;);</line>
<line>    else</line>
<line>        ext_ptr =  extfield&lt;(64-bottom_PAC_bit)-1:0&gt; : ptr&lt;bottom_PAC_bit-1:0&gt;;</line>
<line></line>
<line>    PAC = <a link="impl-aarch64.ComputePAC.5" file="shared_pseudocode.xml" hover="function: bits(64) ComputePAC(bits(64) data, bits(64) modifier, bits(64) key0, bits(64) key1, boolean isgeneric)">ComputePAC</a>(ext_ptr, modifier, K&lt;127:64&gt;, K&lt;63:0&gt;, isgeneric);</line>
<line></line>
<line>    // Check if the ptr has good extension bits and corrupt the pointer authentication code if not</line>
<line>    bits(64) unusedbits_mask = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>    unusedbits_mask&lt;54:bottom_PAC_bit&gt; = <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>((54-bottom_PAC_bit)+1);</line>
<line>    if tbi then</line>
<line>        unusedbits_mask&lt;63:56&gt; = <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(8);</line>
<line>    elsif mtx then</line>
<line>        unusedbits_mask&lt;63:60&gt; = <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(4);</line>
<line>    if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(ptr AND unusedbits_mask) &amp;&amp; ((ptr AND unusedbits_mask) != unusedbits_mask) then</line>
<line>        if <a link="impl-aarch64.HaveEnhancedPAC.0" file="shared_pseudocode.xml" hover="function: boolean HaveEnhancedPAC()">HaveEnhancedPAC</a>() then</line>
<line>            PAC = 0x0000000000000000&lt;63:0&gt;;</line>
<line>        elsif !<a link="impl-aarch64.HaveEnhancedPAC2.0" file="shared_pseudocode.xml" hover="function: boolean HaveEnhancedPAC2()">HaveEnhancedPAC2</a>() then</line>
<line>            PAC&lt;top_bit-1&gt; = NOT(PAC&lt;top_bit-1&gt;);</line>
<line></line>
<line>    // Preserve the determination between upper and lower address at bit&lt;55&gt; and insert PAC into</line>
<line>    // bits that are not used for the address or the tag(s).</line>
<line>    if !<a link="impl-aarch64.HaveEnhancedPAC2.0" file="shared_pseudocode.xml" hover="function: boolean HaveEnhancedPAC2()">HaveEnhancedPAC2</a>() then</line>
<line>        if tbi then</line>
<line>            result = ptr&lt;63:56&gt;:selbit:PAC&lt;54:bottom_PAC_bit&gt;:ptr&lt;bottom_PAC_bit-1:0&gt;;</line>
<line>        else</line>
<line>            result = PAC&lt;63:56&gt;:selbit:PAC&lt;54:bottom_PAC_bit&gt;:ptr&lt;bottom_PAC_bit-1:0&gt;;</line>
<line>            // A compliant implementation of FEAT_MTE4 also implements FEAT_PAuth2</line>
<line>            assert !mtx;</line>
<line>    else</line>
<line>        if tbi then</line>
<line>            result = (ptr&lt;63:56&gt;                               : selbit :</line>
<line>                      (ptr&lt;54:bottom_PAC_bit&gt; EOR PAC&lt;54:bottom_PAC_bit&gt;) :</line>
<line>                      ptr&lt;bottom_PAC_bit-1:0&gt;);</line>
<line>        elsif mtx then</line>
<line>            result = ((ptr&lt;63:60&gt; EOR PAC&lt;63:60&gt;) : ptr&lt;59:56&gt; : selbit :</line>
<line>                      (ptr&lt;54:bottom_PAC_bit&gt; EOR PAC&lt;54:bottom_PAC_bit&gt;) :</line>
<line>                      ptr&lt;bottom_PAC_bit-1:0&gt;);</line>
<line>        else</line>
<line>            result = ((ptr&lt;63:56&gt; EOR PAC&lt;63:56&gt;)              : selbit :</line>
<line>                      (ptr&lt;54:bottom_PAC_bit&gt; EOR PAC&lt;54:bottom_PAC_bit&gt;) :</line>
<line>                      ptr&lt;bottom_PAC_bit-1:0&gt;);</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/addpacda/AddPACDA" mylink="aarch64.functions.pac.addpacda.AddPACDA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AddPACDA()</line>
<line>// ==========</line>
<line>// Returns a 64-bit value containing x, but replacing the pointer authentication code</line>
<line>// field bits with a pointer authentication code, where the pointer authentication</line>
<line>// code is derived using a cryptographic algorithm as a combination of x, y and the</line>
<line>// APDAKey_EL1.</line>
<line></line>
<line link="impl-aarch64.AddPACDA.2" hover="function: bits(64) AddPACDA(bits(64) x, bits(64) y)" conts="AddPACDA">bits(64) <anchor link="impl-aarch64.AddPACDA.2" hover="function: bits(64) AddPACDA(bits(64) x, bits(64) y)">AddPACDA</anchor>(bits(64) x, bits(64) y)</line>
<line>    boolean TrapEL2;</line>
<line>    boolean TrapEL3;</line>
<line>    bits(1)  Enable;</line>
<line>    bits(128) APDAKey_EL1;</line>
<line></line>
<line>    APDAKey_EL1 = APDAKeyHi_EL1&lt;63:0&gt; : APDAKeyLo_EL1&lt;63:0&gt;;</line>
<line>    case PSTATE.EL of</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>            boolean IsEL1Regime = <a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>() == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>            Enable = if IsEL1Regime then SCTLR_EL1.EnDA else SCTLR_EL2.EnDA;</line>
<line>            TrapEL2 = (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.API == '0' &amp;&amp;</line>
<line>                        (HCR_EL2.TGE == '0' || HCR_EL2.E2H == '0'));</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            Enable = SCTLR_EL1.EnDA;</line>
<line>            TrapEL2 = <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.API == '0';</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            Enable = SCTLR_EL2.EnDA;</line>
<line>            TrapEL2 = FALSE;</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            Enable = SCTLR_EL3.EnDA;</line>
<line>            TrapEL2 = FALSE;</line>
<line>            TrapEL3 = FALSE;</line>
<line></line>
<line>    if Enable == '0' then</line>
<line>        return x;</line>
<line>    elsif TrapEL3 &amp;&amp; <a link="impl-shared.EL3SDDUndefPriority.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndefPriority()">EL3SDDUndefPriority</a>() then</line>
<line>        UNDEFINED;</line>
<line>    elsif TrapEL2 then</line>
<line>        <a link="impl-aarch64.TrapPACUse.1" file="shared_pseudocode.xml" hover="function: TrapPACUse(bits(2) target_el)">TrapPACUse</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>    elsif TrapEL3 then</line>
<line>        if <a link="impl-shared.EL3SDDUndef.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndef()">EL3SDDUndef</a>() then</line>
<line>            UNDEFINED;</line>
<line>        else</line>
<line>            <a link="impl-aarch64.TrapPACUse.1" file="shared_pseudocode.xml" hover="function: TrapPACUse(bits(2) target_el)">TrapPACUse</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>    else</line>
<line>        return <a link="impl-aarch64.AddPAC.4" file="shared_pseudocode.xml" hover="function: bits(64) AddPAC(bits(64) ptr, bits(64) modifier, bits(128) K, boolean data)">AddPAC</a>(x, y, APDAKey_EL1, TRUE);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/addpacdb/AddPACDB" mylink="aarch64.functions.pac.addpacdb.AddPACDB" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AddPACDB()</line>
<line>// ==========</line>
<line>// Returns a 64-bit value containing x, but replacing the pointer authentication code</line>
<line>// field bits with a pointer authentication code, where the pointer authentication</line>
<line>// code is derived using a cryptographic algorithm as a combination of x, y and the</line>
<line>// APDBKey_EL1.</line>
<line></line>
<line link="impl-aarch64.AddPACDB.2" hover="function: bits(64) AddPACDB(bits(64) x, bits(64) y)" conts="AddPACDB">bits(64) <anchor link="impl-aarch64.AddPACDB.2" hover="function: bits(64) AddPACDB(bits(64) x, bits(64) y)">AddPACDB</anchor>(bits(64) x, bits(64) y)</line>
<line>    boolean TrapEL2;</line>
<line>    boolean TrapEL3;</line>
<line>    bits(1)  Enable;</line>
<line>    bits(128) APDBKey_EL1;</line>
<line></line>
<line>    APDBKey_EL1 = APDBKeyHi_EL1&lt;63:0&gt; : APDBKeyLo_EL1&lt;63:0&gt;;</line>
<line>    case PSTATE.EL of</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>            boolean IsEL1Regime = <a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>() == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>            Enable = if IsEL1Regime then SCTLR_EL1.EnDB else SCTLR_EL2.EnDB;</line>
<line>            TrapEL2 = (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.API == '0' &amp;&amp;</line>
<line>                       (HCR_EL2.TGE == '0' || HCR_EL2.E2H == '0'));</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            Enable = SCTLR_EL1.EnDB;</line>
<line>            TrapEL2 = <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.API == '0';</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            Enable = SCTLR_EL2.EnDB;</line>
<line>            TrapEL2 = FALSE;</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            Enable = SCTLR_EL3.EnDB;</line>
<line>            TrapEL2 = FALSE;</line>
<line>            TrapEL3 = FALSE;</line>
<line></line>
<line>    if Enable == '0' then</line>
<line>        return x;</line>
<line>    elsif TrapEL3 &amp;&amp; <a link="impl-shared.EL3SDDUndefPriority.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndefPriority()">EL3SDDUndefPriority</a>() then</line>
<line>        UNDEFINED;</line>
<line>    elsif TrapEL2 then</line>
<line>        <a link="impl-aarch64.TrapPACUse.1" file="shared_pseudocode.xml" hover="function: TrapPACUse(bits(2) target_el)">TrapPACUse</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>    elsif TrapEL3 then</line>
<line>        if <a link="impl-shared.EL3SDDUndef.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndef()">EL3SDDUndef</a>() then</line>
<line>            UNDEFINED;</line>
<line>        else</line>
<line>            <a link="impl-aarch64.TrapPACUse.1" file="shared_pseudocode.xml" hover="function: TrapPACUse(bits(2) target_el)">TrapPACUse</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>    else</line>
<line>        return <a link="impl-aarch64.AddPAC.4" file="shared_pseudocode.xml" hover="function: bits(64) AddPAC(bits(64) ptr, bits(64) modifier, bits(128) K, boolean data)">AddPAC</a>(x, y, APDBKey_EL1, TRUE);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/addpacga/AddPACGA" mylink="aarch64.functions.pac.addpacga.AddPACGA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AddPACGA()</line>
<line>// ==========</line>
<line>// Returns a 64-bit value where the lower 32 bits are 0, and the upper 32 bits contain</line>
<line>// a 32-bit pointer authentication code which is derived using a cryptographic</line>
<line>// algorithm as a combination of x, y and the APGAKey_EL1.</line>
<line></line>
<line link="impl-aarch64.AddPACGA.2" hover="function: bits(64) AddPACGA(bits(64) x, bits(64) y)" conts="AddPACGA">bits(64) <anchor link="impl-aarch64.AddPACGA.2" hover="function: bits(64) AddPACGA(bits(64) x, bits(64) y)">AddPACGA</anchor>(bits(64) x, bits(64) y)</line>
<line>    boolean TrapEL2;</line>
<line>    boolean TrapEL3;</line>
<line>    bits(128) APGAKey_EL1;</line>
<line>    boolean isgeneric = TRUE;</line>
<line></line>
<line>    APGAKey_EL1 = APGAKeyHi_EL1&lt;63:0&gt; : APGAKeyLo_EL1&lt;63:0&gt;;</line>
<line>    case PSTATE.EL of</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>            TrapEL2 = (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.API == '0' &amp;&amp;</line>
<line>                        (HCR_EL2.TGE == '0' || HCR_EL2.E2H == '0'));</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            TrapEL2 = <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.API == '0';</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            TrapEL2 = FALSE;</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            TrapEL2 = FALSE;</line>
<line>            TrapEL3 = FALSE;</line>
<line></line>
<line>    if TrapEL3 &amp;&amp; <a link="impl-shared.EL3SDDUndefPriority.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndefPriority()">EL3SDDUndefPriority</a>() then</line>
<line>        UNDEFINED;</line>
<line>    elsif TrapEL2 then</line>
<line>        <a link="impl-aarch64.TrapPACUse.1" file="shared_pseudocode.xml" hover="function: TrapPACUse(bits(2) target_el)">TrapPACUse</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>    elsif TrapEL3 then</line>
<line>        if <a link="impl-shared.EL3SDDUndef.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndef()">EL3SDDUndef</a>() then</line>
<line>            UNDEFINED;</line>
<line>        else</line>
<line>            <a link="impl-aarch64.TrapPACUse.1" file="shared_pseudocode.xml" hover="function: TrapPACUse(bits(2) target_el)">TrapPACUse</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>    else</line>
<line>        return <a link="impl-aarch64.ComputePAC.5" file="shared_pseudocode.xml" hover="function: bits(64) ComputePAC(bits(64) data, bits(64) modifier, bits(64) key0, bits(64) key1, boolean isgeneric)">ComputePAC</a>(x, y, APGAKey_EL1&lt;127:64&gt;, APGAKey_EL1&lt;63:0&gt;, isgeneric)&lt;63:32&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/addpacia/AddPACIA" mylink="aarch64.functions.pac.addpacia.AddPACIA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AddPACIA()</line>
<line>// ==========</line>
<line>// Returns a 64-bit value containing x, but replacing the pointer authentication code</line>
<line>// field bits with a pointer authentication code, where the pointer authentication</line>
<line>// code is derived using a cryptographic algorithm as a combination of x, y, and the</line>
<line>// APIAKey_EL1.</line>
<line></line>
<line link="impl-aarch64.AddPACIA.2" hover="function: bits(64) AddPACIA(bits(64) x, bits(64) y)" conts="AddPACIA">bits(64) <anchor link="impl-aarch64.AddPACIA.2" hover="function: bits(64) AddPACIA(bits(64) x, bits(64) y)">AddPACIA</anchor>(bits(64) x, bits(64) y)</line>
<line>    boolean TrapEL2;</line>
<line>    boolean TrapEL3;</line>
<line>    bits(1)  Enable;</line>
<line>    bits(128) APIAKey_EL1;</line>
<line></line>
<line>    APIAKey_EL1 = APIAKeyHi_EL1&lt;63:0&gt;:APIAKeyLo_EL1&lt;63:0&gt;;</line>
<line>    case PSTATE.EL of</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>            boolean IsEL1Regime = <a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>() == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>            Enable = if IsEL1Regime then SCTLR_EL1.EnIA else SCTLR_EL2.EnIA;</line>
<line>            TrapEL2 = (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.API == '0' &amp;&amp;</line>
<line>                       (HCR_EL2.TGE == '0' || HCR_EL2.E2H == '0'));</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            Enable = SCTLR_EL1.EnIA;</line>
<line>            TrapEL2 = <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.API == '0';</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            Enable = SCTLR_EL2.EnIA;</line>
<line>            TrapEL2 = FALSE;</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            Enable = SCTLR_EL3.EnIA;</line>
<line>            TrapEL2 = FALSE;</line>
<line>            TrapEL3 = FALSE;</line>
<line></line>
<line>    if Enable == '0' then</line>
<line>        return x;</line>
<line>    elsif TrapEL3 &amp;&amp; <a link="impl-shared.EL3SDDUndefPriority.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndefPriority()">EL3SDDUndefPriority</a>() then</line>
<line>        UNDEFINED;</line>
<line>    elsif TrapEL2 then</line>
<line>        <a link="impl-aarch64.TrapPACUse.1" file="shared_pseudocode.xml" hover="function: TrapPACUse(bits(2) target_el)">TrapPACUse</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>    elsif TrapEL3 then</line>
<line>        if <a link="impl-shared.EL3SDDUndef.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndef()">EL3SDDUndef</a>() then</line>
<line>            UNDEFINED;</line>
<line>        else</line>
<line>            <a link="impl-aarch64.TrapPACUse.1" file="shared_pseudocode.xml" hover="function: TrapPACUse(bits(2) target_el)">TrapPACUse</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>    else</line>
<line>        return <a link="impl-aarch64.AddPAC.4" file="shared_pseudocode.xml" hover="function: bits(64) AddPAC(bits(64) ptr, bits(64) modifier, bits(128) K, boolean data)">AddPAC</a>(x, y, APIAKey_EL1, FALSE);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/addpacib/AddPACIB" mylink="aarch64.functions.pac.addpacib.AddPACIB" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AddPACIB()</line>
<line>// ==========</line>
<line>// Returns a 64-bit value containing x, but replacing the pointer authentication code</line>
<line>// field bits with a pointer authentication code, where the pointer authentication</line>
<line>// code is derived using a cryptographic algorithm as a combination of x, y and the</line>
<line>// APIBKey_EL1.</line>
<line></line>
<line link="impl-aarch64.AddPACIB.2" hover="function: bits(64) AddPACIB(bits(64) x, bits(64) y)" conts="AddPACIB">bits(64) <anchor link="impl-aarch64.AddPACIB.2" hover="function: bits(64) AddPACIB(bits(64) x, bits(64) y)">AddPACIB</anchor>(bits(64) x, bits(64) y)</line>
<line>    boolean TrapEL2;</line>
<line>    boolean TrapEL3;</line>
<line>    bits(1)  Enable;</line>
<line>    bits(128) APIBKey_EL1;</line>
<line></line>
<line>    APIBKey_EL1 = APIBKeyHi_EL1&lt;63:0&gt; : APIBKeyLo_EL1&lt;63:0&gt;;</line>
<line>    case PSTATE.EL of</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>            boolean IsEL1Regime = <a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>() == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>            Enable = if IsEL1Regime then SCTLR_EL1.EnIB else SCTLR_EL2.EnIB;</line>
<line>            TrapEL2 = (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.API == '0' &amp;&amp;</line>
<line>                       (HCR_EL2.TGE == '0' || HCR_EL2.E2H == '0'));</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            Enable = SCTLR_EL1.EnIB;</line>
<line>            TrapEL2 = <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.API == '0';</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            Enable = SCTLR_EL2.EnIB;</line>
<line>            TrapEL2 = FALSE;</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            Enable = SCTLR_EL3.EnIB;</line>
<line>            TrapEL2 = FALSE;</line>
<line>            TrapEL3 = FALSE;</line>
<line></line>
<line>    if Enable == '0' then</line>
<line>        return x;</line>
<line>    elsif TrapEL3 &amp;&amp; <a link="impl-shared.EL3SDDUndefPriority.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndefPriority()">EL3SDDUndefPriority</a>() then</line>
<line>        UNDEFINED;</line>
<line>    elsif TrapEL2 then</line>
<line>        <a link="impl-aarch64.TrapPACUse.1" file="shared_pseudocode.xml" hover="function: TrapPACUse(bits(2) target_el)">TrapPACUse</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>    elsif TrapEL3 then</line>
<line>        if <a link="impl-shared.EL3SDDUndef.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndef()">EL3SDDUndef</a>() then</line>
<line>            UNDEFINED;</line>
<line>        else</line>
<line>            <a link="impl-aarch64.TrapPACUse.1" file="shared_pseudocode.xml" hover="function: TrapPACUse(bits(2) target_el)">TrapPACUse</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>    else</line>
<line>        return <a link="impl-aarch64.AddPAC.4" file="shared_pseudocode.xml" hover="function: bits(64) AddPAC(bits(64) ptr, bits(64) modifier, bits(128) K, boolean data)">AddPAC</a>(x, y, APIBKey_EL1, FALSE);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/auth/AArch64.PACFailException" mylink="aarch64.functions.pac.auth.AArch64.PACFailException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.PACFailException()</line>
<line>// ==========================</line>
<line>// Generates a PAC Fail Exception</line>
<line></line>
<line link="AArch64.PACFailException.1" hover="function: AArch64.PACFailException(bits(2) syndrome)" conts="AArch64.PACFailException"><anchor link="AArch64.PACFailException.1" hover="function: AArch64.PACFailException(bits(2) syndrome)">AArch64.PACFailException</anchor>(bits(2) syndrome)</line>
<line>    route_to_el2 = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1';</line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x0;</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_PACFail" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_PACFail</a>);</line>
<line>    exception.syndrome&lt;1:0&gt;   = syndrome;</line>
<line>    exception.syndrome&lt;24:2&gt;  = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(23);                // RES0</line>
<line></line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>) then</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(PSTATE.EL, exception, preferred_exception_return, vect_offset);</line>
<line>    elsif route_to_el2 then</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, exception, preferred_exception_return, vect_offset);</line>
<line>    else</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/auth/Auth" mylink="aarch64.functions.pac.auth.Auth" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Auth()</line>
<line>// ======</line>
<line>// Restores the upper bits of the address to be all zeros or all ones (based on the</line>
<line>// value of bit[55]) and computes and checks the pointer authentication code. If the</line>
<line>// check passes, then the restored address is returned. If the check fails, the</line>
<line>// second-top and third-top bits of the extension bits in the pointer authentication code</line>
<line>// field are corrupted to ensure that accessing the address will give a translation fault.</line>
<line></line>
<line link="impl-aarch64.Auth.6" hover="function: bits(64) Auth(bits(64) ptr, bits(64) modifier, bits(128) K, boolean data, bit key_number, boolean is_combined)" conts="Auth">bits(64) <anchor link="impl-aarch64.Auth.6" hover="function: bits(64) Auth(bits(64) ptr, bits(64) modifier, bits(128) K, boolean data, bit key_number, boolean is_combined)">Auth</anchor>(bits(64) ptr, bits(64) modifier, bits(128) K, boolean data, bit key_number,</line>
<line>              boolean is_combined)</line>
<line>    bits(64) PAC;</line>
<line>    bits(64) result;</line>
<line>    bits(64) original_ptr;</line>
<line>    bits(2) error_code;</line>
<line>    bits(64) extfield;</line>
<line>    boolean isgeneric = FALSE;</line>
<line></line>
<line>    // Reconstruct the extension field used of adding the PAC to the pointer</line>
<line>    boolean tbi = <a link="impl-shared.EffectiveTBI.3" file="shared_pseudocode.xml" hover="function: bit EffectiveTBI(bits(64) address, boolean IsInstr, bits(2) el)">EffectiveTBI</a>(ptr, !data, PSTATE.EL) == '1';</line>
<line>    boolean mtx = <a link="impl-shared.EffectiveMTX.3" file="shared_pseudocode.xml" hover="function: bit EffectiveMTX(bits(64) address, boolean is_instr, bits(2) el)">EffectiveMTX</a>(ptr, !data, PSTATE.EL) == '1';</line>
<line>    integer bottom_PAC_bit = <a link="impl-aarch64.CalculateBottomPACBit.1" file="shared_pseudocode.xml" hover="function: integer CalculateBottomPACBit(bit top_bit)">CalculateBottomPACBit</a>(ptr&lt;55&gt;);</line>
<line>    extfield = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(ptr&lt;55&gt;, 64);</line>
<line></line>
<line>    // If the VA is 56 or 55 bits and Top Byte is Ignored,</line>
<line>    // there are no unused bits left for the PAC</line>
<line>    if tbi &amp;&amp; bottom_PAC_bit &gt;= 55 then</line>
<line>        return ptr;</line>
<line></line>
<line>    if tbi then</line>
<line>        original_ptr = (ptr&lt;63:56&gt; :</line>
<line>                        extfield&lt;(56-bottom_PAC_bit)-1:0&gt; : ptr&lt;bottom_PAC_bit-1:0&gt;);</line>
<line>    elsif mtx then</line>
<line>        original_ptr = (extfield&lt;63:60&gt; : ptr&lt;59:56&gt; :</line>
<line>                        extfield&lt;(56-bottom_PAC_bit)-1:0&gt; : ptr&lt;bottom_PAC_bit-1:0&gt;);</line>
<line>    else</line>
<line>        original_ptr =  extfield&lt;(64-bottom_PAC_bit)-1:0&gt; : ptr&lt;bottom_PAC_bit-1:0&gt;;</line>
<line></line>
<line>    PAC = <a link="impl-aarch64.ComputePAC.5" file="shared_pseudocode.xml" hover="function: bits(64) ComputePAC(bits(64) data, bits(64) modifier, bits(64) key0, bits(64) key1, boolean isgeneric)">ComputePAC</a>(original_ptr, modifier, K&lt;127:64&gt;, K&lt;63:0&gt;, isgeneric);</line>
<line>    // Check pointer authentication code</line>
<line>    if tbi then</line>
<line>        if !<a link="impl-aarch64.HaveEnhancedPAC2.0" file="shared_pseudocode.xml" hover="function: boolean HaveEnhancedPAC2()">HaveEnhancedPAC2</a>() then</line>
<line>            if PAC&lt;54:bottom_PAC_bit&gt; == ptr&lt;54:bottom_PAC_bit&gt; then</line>
<line>                result = original_ptr;</line>
<line>            else</line>
<line>                error_code = key_number:NOT(key_number);</line>
<line>                result = original_ptr&lt;63:55&gt;:error_code:original_ptr&lt;52:0&gt;;</line>
<line>        else</line>
<line>            result = ptr;</line>
<line>            result&lt;54:bottom_PAC_bit&gt; = result&lt;54:bottom_PAC_bit&gt; EOR PAC&lt;54:bottom_PAC_bit&gt;;</line>
<line>            if <a link="impl-aarch64.HaveFPACCombined.0" file="shared_pseudocode.xml" hover="function: boolean HaveFPACCombined()">HaveFPACCombined</a>() || (<a link="impl-aarch64.HaveFPAC.0" file="shared_pseudocode.xml" hover="function: boolean HaveFPAC()">HaveFPAC</a>() &amp;&amp; !is_combined) then</line>
<line>                if result&lt;54:bottom_PAC_bit&gt; != <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(result&lt;55&gt;, (55-bottom_PAC_bit)) then</line>
<line>                    error_code = (if data then '1' else '0'):key_number;</line>
<line>                    <a link="AArch64.PACFailException.1" file="shared_pseudocode.xml" hover="function: AArch64.PACFailException(bits(2) syndrome)">AArch64.PACFailException</a>(error_code);</line>
<line>    elsif mtx then</line>
<line>        assert <a link="impl-aarch64.HaveEnhancedPAC2.0" file="shared_pseudocode.xml" hover="function: boolean HaveEnhancedPAC2()">HaveEnhancedPAC2</a>();</line>
<line>        result = ptr;</line>
<line>        result&lt;54:bottom_PAC_bit&gt; = result&lt;54:bottom_PAC_bit&gt; EOR PAC&lt;54:bottom_PAC_bit&gt;;</line>
<line>        result&lt;63:60&gt; = result&lt;63:60&gt; EOR PAC&lt;63:60&gt;;</line>
<line>        if <a link="impl-aarch64.HaveFPACCombined.0" file="shared_pseudocode.xml" hover="function: boolean HaveFPACCombined()">HaveFPACCombined</a>() || (<a link="impl-aarch64.HaveFPAC.0" file="shared_pseudocode.xml" hover="function: boolean HaveFPAC()">HaveFPAC</a>() &amp;&amp; !is_combined) then</line>
<line>            if ((result&lt;54:bottom_PAC_bit&gt; != <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(result&lt;55&gt;, (55-bottom_PAC_bit))) ||</line>
<line>                (result&lt;63:60&gt; != <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(result&lt;55&gt;, 4))) then</line>
<line>                error_code = (if data then '1' else '0'):key_number;</line>
<line>                <a link="AArch64.PACFailException.1" file="shared_pseudocode.xml" hover="function: AArch64.PACFailException(bits(2) syndrome)">AArch64.PACFailException</a>(error_code);</line>
<line>    else</line>
<line>        if !<a link="impl-aarch64.HaveEnhancedPAC2.0" file="shared_pseudocode.xml" hover="function: boolean HaveEnhancedPAC2()">HaveEnhancedPAC2</a>() then</line>
<line>            if PAC&lt;54:bottom_PAC_bit&gt; == ptr&lt;54:bottom_PAC_bit&gt; &amp;&amp; PAC&lt;63:56&gt; == ptr&lt;63:56&gt; then</line>
<line>                result = original_ptr;</line>
<line>            else</line>
<line>                error_code = key_number:NOT(key_number);</line>
<line>                result = original_ptr&lt;63&gt;:error_code:original_ptr&lt;60:0&gt;;</line>
<line>        else</line>
<line>            result = ptr;</line>
<line>            result&lt;54:bottom_PAC_bit&gt; = result&lt;54:bottom_PAC_bit&gt; EOR PAC&lt;54:bottom_PAC_bit&gt;;</line>
<line>            result&lt;63:56&gt; = result&lt;63:56&gt; EOR PAC&lt;63:56&gt;;</line>
<line>            if <a link="impl-aarch64.HaveFPACCombined.0" file="shared_pseudocode.xml" hover="function: boolean HaveFPACCombined()">HaveFPACCombined</a>() || (<a link="impl-aarch64.HaveFPAC.0" file="shared_pseudocode.xml" hover="function: boolean HaveFPAC()">HaveFPAC</a>() &amp;&amp; !is_combined) then</line>
<line>                if result&lt;63:bottom_PAC_bit&gt; != <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(result&lt;55&gt;, (64-bottom_PAC_bit)) then</line>
<line>                    error_code = (if data then '1' else '0'):key_number;</line>
<line>                    <a link="AArch64.PACFailException.1" file="shared_pseudocode.xml" hover="function: AArch64.PACFailException(bits(2) syndrome)">AArch64.PACFailException</a>(error_code);</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/authda/AuthDA" mylink="aarch64.functions.pac.authda.AuthDA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AuthDA()</line>
<line>// ========</line>
<line>// Returns a 64-bit value containing x, but replacing the pointer authentication code</line>
<line>// field bits with the extension of the address bits. The instruction checks a pointer</line>
<line>// authentication code in the pointer authentication code field bits of x, using the same</line>
<line>// algorithm and key as AddPACDA().</line>
<line></line>
<line link="impl-aarch64.AuthDA.3" hover="function: bits(64) AuthDA(bits(64) x, bits(64) y, boolean is_combined)" conts="AuthDA">bits(64) <anchor link="impl-aarch64.AuthDA.3" hover="function: bits(64) AuthDA(bits(64) x, bits(64) y, boolean is_combined)">AuthDA</anchor>(bits(64) x, bits(64) y, boolean is_combined)</line>
<line>    boolean TrapEL2;</line>
<line>    boolean TrapEL3;</line>
<line>    bits(1)  Enable;</line>
<line>    bits(128) APDAKey_EL1;</line>
<line></line>
<line>    APDAKey_EL1 = APDAKeyHi_EL1&lt;63:0&gt; : APDAKeyLo_EL1&lt;63:0&gt;;</line>
<line>    case PSTATE.EL of</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>            boolean IsEL1Regime = <a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>() == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>            Enable = if IsEL1Regime then SCTLR_EL1.EnDA else SCTLR_EL2.EnDA;</line>
<line>            TrapEL2 = (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.API == '0' &amp;&amp;</line>
<line>                       (HCR_EL2.TGE == '0' || HCR_EL2.E2H == '0'));</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            Enable = SCTLR_EL1.EnDA;</line>
<line>            TrapEL2 = <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.API == '0';</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            Enable = SCTLR_EL2.EnDA;</line>
<line>            TrapEL2 = FALSE;</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            Enable = SCTLR_EL3.EnDA;</line>
<line>            TrapEL2 = FALSE;</line>
<line>            TrapEL3 = FALSE;</line>
<line></line>
<line>    if Enable == '0' then</line>
<line>        return x;</line>
<line>    elsif TrapEL3 &amp;&amp; <a link="impl-shared.EL3SDDUndefPriority.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndefPriority()">EL3SDDUndefPriority</a>() then</line>
<line>        UNDEFINED;</line>
<line>    elsif TrapEL2 then</line>
<line>        <a link="impl-aarch64.TrapPACUse.1" file="shared_pseudocode.xml" hover="function: TrapPACUse(bits(2) target_el)">TrapPACUse</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>    elsif TrapEL3 then</line>
<line>        if <a link="impl-shared.EL3SDDUndef.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndef()">EL3SDDUndef</a>() then</line>
<line>            UNDEFINED;</line>
<line>        else</line>
<line>            <a link="impl-aarch64.TrapPACUse.1" file="shared_pseudocode.xml" hover="function: TrapPACUse(bits(2) target_el)">TrapPACUse</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>    else</line>
<line>        return <a link="impl-aarch64.Auth.6" file="shared_pseudocode.xml" hover="function: bits(64) Auth(bits(64) ptr, bits(64) modifier, bits(128) K, boolean data, bit key_number, boolean is_combined)">Auth</a>(x, y, APDAKey_EL1, TRUE, '0', is_combined);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/authdb/AuthDB" mylink="aarch64.functions.pac.authdb.AuthDB" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AuthDB()</line>
<line>// ========</line>
<line>// Returns a 64-bit value containing x, but replacing the pointer authentication code</line>
<line>// field bits with the extension of the address bits. The instruction checks a</line>
<line>// pointer authentication code in the pointer authentication code field bits of x, using</line>
<line>// the same algorithm and key as AddPACDB().</line>
<line></line>
<line link="impl-aarch64.AuthDB.3" hover="function: bits(64) AuthDB(bits(64) x, bits(64) y, boolean is_combined)" conts="AuthDB">bits(64) <anchor link="impl-aarch64.AuthDB.3" hover="function: bits(64) AuthDB(bits(64) x, bits(64) y, boolean is_combined)">AuthDB</anchor>(bits(64) x, bits(64) y, boolean is_combined)</line>
<line>    boolean TrapEL2;</line>
<line>    boolean TrapEL3;</line>
<line>    bits(1)  Enable;</line>
<line>    bits(128) APDBKey_EL1;</line>
<line></line>
<line>    APDBKey_EL1 = APDBKeyHi_EL1&lt;63:0&gt; : APDBKeyLo_EL1&lt;63:0&gt;;</line>
<line>    case PSTATE.EL of</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>            boolean IsEL1Regime = <a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>() == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>            Enable = if IsEL1Regime then SCTLR_EL1.EnDB else SCTLR_EL2.EnDB;</line>
<line>            TrapEL2 = (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.API == '0' &amp;&amp;</line>
<line>                        (HCR_EL2.TGE == '0' || HCR_EL2.E2H == '0'));</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            Enable = SCTLR_EL1.EnDB;</line>
<line>            TrapEL2 = <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.API == '0';</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            Enable = SCTLR_EL2.EnDB;</line>
<line>            TrapEL2 = FALSE;</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            Enable = SCTLR_EL3.EnDB;</line>
<line>            TrapEL2 = FALSE;</line>
<line>            TrapEL3 = FALSE;</line>
<line></line>
<line>    if Enable == '0' then</line>
<line>        return x;</line>
<line>    elsif TrapEL3 &amp;&amp; <a link="impl-shared.EL3SDDUndefPriority.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndefPriority()">EL3SDDUndefPriority</a>() then</line>
<line>        UNDEFINED;</line>
<line>    elsif TrapEL2 then</line>
<line>        <a link="impl-aarch64.TrapPACUse.1" file="shared_pseudocode.xml" hover="function: TrapPACUse(bits(2) target_el)">TrapPACUse</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>    elsif TrapEL3 then</line>
<line>        if <a link="impl-shared.EL3SDDUndef.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndef()">EL3SDDUndef</a>() then</line>
<line>            UNDEFINED;</line>
<line>        else</line>
<line>            <a link="impl-aarch64.TrapPACUse.1" file="shared_pseudocode.xml" hover="function: TrapPACUse(bits(2) target_el)">TrapPACUse</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>    else</line>
<line>        return <a link="impl-aarch64.Auth.6" file="shared_pseudocode.xml" hover="function: bits(64) Auth(bits(64) ptr, bits(64) modifier, bits(128) K, boolean data, bit key_number, boolean is_combined)">Auth</a>(x, y, APDBKey_EL1, TRUE, '1', is_combined);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/authia/AuthIA" mylink="aarch64.functions.pac.authia.AuthIA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AuthIA()</line>
<line>// ========</line>
<line>// Returns a 64-bit value containing x, but replacing the pointer authentication code</line>
<line>// field bits with the extension of the address bits. The instruction checks a pointer</line>
<line>// authentication code in the pointer authentication code field bits of x, using the same</line>
<line>// algorithm and key as AddPACIA().</line>
<line></line>
<line link="impl-aarch64.AuthIA.3" hover="function: bits(64) AuthIA(bits(64) x, bits(64) y, boolean is_combined)" conts="AuthIA">bits(64) <anchor link="impl-aarch64.AuthIA.3" hover="function: bits(64) AuthIA(bits(64) x, bits(64) y, boolean is_combined)">AuthIA</anchor>(bits(64) x, bits(64) y, boolean is_combined)</line>
<line>    boolean TrapEL2;</line>
<line>    boolean TrapEL3;</line>
<line>    bits(1)  Enable;</line>
<line>    bits(128) APIAKey_EL1;</line>
<line></line>
<line>    APIAKey_EL1 = APIAKeyHi_EL1&lt;63:0&gt; : APIAKeyLo_EL1&lt;63:0&gt;;</line>
<line>    case PSTATE.EL of</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>            boolean IsEL1Regime = <a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>() == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>            Enable = if IsEL1Regime then SCTLR_EL1.EnIA else SCTLR_EL2.EnIA;</line>
<line>            TrapEL2 = (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.API == '0' &amp;&amp;</line>
<line>                       (HCR_EL2.TGE == '0' || HCR_EL2.E2H == '0'));</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            Enable = SCTLR_EL1.EnIA;</line>
<line>            TrapEL2 = <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.API == '0';</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            Enable = SCTLR_EL2.EnIA;</line>
<line>            TrapEL2 = FALSE;</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            Enable = SCTLR_EL3.EnIA;</line>
<line>            TrapEL2 = FALSE;</line>
<line>            TrapEL3 = FALSE;</line>
<line></line>
<line>    if Enable == '0' then</line>
<line>        return x;</line>
<line>    elsif TrapEL3 &amp;&amp; <a link="impl-shared.EL3SDDUndefPriority.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndefPriority()">EL3SDDUndefPriority</a>() then</line>
<line>        UNDEFINED;</line>
<line>    elsif TrapEL2 then</line>
<line>        <a link="impl-aarch64.TrapPACUse.1" file="shared_pseudocode.xml" hover="function: TrapPACUse(bits(2) target_el)">TrapPACUse</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>    elsif TrapEL3 then</line>
<line>        if <a link="impl-shared.EL3SDDUndef.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndef()">EL3SDDUndef</a>() then</line>
<line>            UNDEFINED;</line>
<line>        else</line>
<line>            <a link="impl-aarch64.TrapPACUse.1" file="shared_pseudocode.xml" hover="function: TrapPACUse(bits(2) target_el)">TrapPACUse</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>    else</line>
<line>        return <a link="impl-aarch64.Auth.6" file="shared_pseudocode.xml" hover="function: bits(64) Auth(bits(64) ptr, bits(64) modifier, bits(128) K, boolean data, bit key_number, boolean is_combined)">Auth</a>(x, y, APIAKey_EL1, FALSE, '0', is_combined);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/authib/AuthIB" mylink="aarch64.functions.pac.authib.AuthIB" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AuthIB()</line>
<line>// ========</line>
<line>// Returns a 64-bit value containing x, but replacing the pointer authentication code</line>
<line>// field bits with the extension of the address bits. The instruction checks a pointer</line>
<line>// authentication code in the pointer authentication code field bits of x, using the same</line>
<line>// algorithm and key as AddPACIB().</line>
<line></line>
<line link="impl-aarch64.AuthIB.3" hover="function: bits(64) AuthIB(bits(64) x, bits(64) y, boolean is_combined)" conts="AuthIB">bits(64) <anchor link="impl-aarch64.AuthIB.3" hover="function: bits(64) AuthIB(bits(64) x, bits(64) y, boolean is_combined)">AuthIB</anchor>(bits(64) x, bits(64) y, boolean is_combined)</line>
<line>    boolean TrapEL2;</line>
<line>    boolean TrapEL3;</line>
<line>    bits(1)  Enable;</line>
<line>    bits(128) APIBKey_EL1;</line>
<line></line>
<line>    APIBKey_EL1 = APIBKeyHi_EL1&lt;63:0&gt; : APIBKeyLo_EL1&lt;63:0&gt;;</line>
<line>    case PSTATE.EL of</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>            boolean IsEL1Regime = <a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>() == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>            Enable = if IsEL1Regime then SCTLR_EL1.EnIB else SCTLR_EL2.EnIB;</line>
<line>            TrapEL2 = (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.API == '0' &amp;&amp;</line>
<line>                       (HCR_EL2.TGE == '0' || HCR_EL2.E2H == '0'));</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            Enable = SCTLR_EL1.EnIB;</line>
<line>            TrapEL2 = <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.API == '0';</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            Enable = SCTLR_EL2.EnIB;</line>
<line>            TrapEL2 = FALSE;</line>
<line>            TrapEL3 = <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.API == '0';</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            Enable = SCTLR_EL3.EnIB;</line>
<line>            TrapEL2 = FALSE;</line>
<line>            TrapEL3 = FALSE;</line>
<line></line>
<line>    if Enable == '0' then</line>
<line>        return x;</line>
<line>    elsif TrapEL3 &amp;&amp; <a link="impl-shared.EL3SDDUndefPriority.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndefPriority()">EL3SDDUndefPriority</a>() then</line>
<line>        UNDEFINED;</line>
<line>    elsif TrapEL2 then</line>
<line>        <a link="impl-aarch64.TrapPACUse.1" file="shared_pseudocode.xml" hover="function: TrapPACUse(bits(2) target_el)">TrapPACUse</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>    elsif TrapEL3 then</line>
<line>        if <a link="impl-shared.EL3SDDUndef.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndef()">EL3SDDUndef</a>() then</line>
<line>            UNDEFINED;</line>
<line>        else</line>
<line>            <a link="impl-aarch64.TrapPACUse.1" file="shared_pseudocode.xml" hover="function: TrapPACUse(bits(2) target_el)">TrapPACUse</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>    else</line>
<line>        return <a link="impl-aarch64.Auth.6" file="shared_pseudocode.xml" hover="function: bits(64) Auth(bits(64) ptr, bits(64) modifier, bits(128) K, boolean data, bit key_number, boolean is_combined)">Auth</a>(x, y, APIBKey_EL1, FALSE, '1', is_combined);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/calcbottompacbit/AArch64.PACEffectiveTxSZ" mylink="aarch64.functions.pac.calcbottompacbit.AArch64.PACEffectiveTxSZ" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.PACEffectiveTxSZ()</line>
<line>// ==========================</line>
<line>// Compute the effective value for TxSZ used to determine the placement of the PAC field</line>
<line></line>
<line>bits(6) AArch64.PACEffectiveTxSZ(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, S1TTWParams walkparams)</line>
<line>    constant integer s1maxtxsz = <a link="AArch64.MaxTxSZ.1" file="shared_pseudocode.xml" hover="function: integer AArch64.MaxTxSZ(TGx tgx)">AArch64.MaxTxSZ</a>(walkparams.tgx);</line>
<line>    constant integer s1mintxsz = <a link="AArch64.S1MinTxSZ.4" file="shared_pseudocode.xml" hover="function: integer AArch64.S1MinTxSZ(Regime regime, bit d128, bit ds, TGx tgx)">AArch64.S1MinTxSZ</a>(regime, walkparams.d128,</line>
<line>                                                   walkparams.ds, walkparams.tgx);</line>
<line></line>
<line>    if AArch64.S1TxSZFaults(regime, walkparams) then</line>
<line>        if <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_RESTnSZ" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESTnSZ</a>) == <a link="Constraint_FORCE" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_FORCE</a> then</line>
<line>            if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(walkparams.txsz) &lt; s1mintxsz then</line>
<line>                return s1mintxsz&lt;5:0&gt;;</line>
<line>            if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(walkparams.txsz) &gt; s1maxtxsz then</line>
<line>                return s1maxtxsz&lt;5:0&gt;;</line>
<line>    elsif <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(walkparams.txsz) &lt; s1mintxsz then</line>
<line>        return s1mintxsz&lt;5:0&gt;;</line>
<line>    elsif <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(walkparams.txsz) &gt; s1maxtxsz then</line>
<line>        return s1maxtxsz&lt;5:0&gt;;</line>
<line></line>
<line>    return walkparams.txsz;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/calcbottompacbit/CalculateBottomPACBit" mylink="aarch64.functions.pac.calcbottompacbit.CalculateBottomPACBit" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CalculateBottomPACBit()</line>
<line>// =======================</line>
<line></line>
<line link="impl-aarch64.CalculateBottomPACBit.1" hover="function: integer CalculateBottomPACBit(bit top_bit)" conts="CalculateBottomPACBit">integer <anchor link="impl-aarch64.CalculateBottomPACBit.1" hover="function: integer CalculateBottomPACBit(bit top_bit)">CalculateBottomPACBit</anchor>(bit top_bit)</line>
<line>    <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime;</line>
<line>    S1TTWParams walkparams;</line>
<line>    integer bottom_PAC_bit;</line>
<line></line>
<line>    regime = <a link="impl-shared.TranslationRegime.1" file="shared_pseudocode.xml" hover="function: Regime TranslationRegime(bits(2) el)">TranslationRegime</a>(PSTATE.EL);</line>
<line>    ss = <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>();</line>
<line>    walkparams = AArch64.GetS1TTWParams(regime, ss, <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(top_bit, 64));</line>
<line>    bottom_PAC_bit = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(AArch64.PACEffectiveTxSZ(regime, walkparams));</line>
<line></line>
<line>    return bottom_PAC_bit;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/computepac/ComputePAC" mylink="aarch64.functions.pac.computepac.ComputePAC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ComputePAC()</line>
<line>// ============</line>
<line></line>
<line link="impl-aarch64.ComputePAC.5" hover="function: bits(64) ComputePAC(bits(64) data, bits(64) modifier, bits(64) key0, bits(64) key1, boolean isgeneric)" conts="ComputePAC">bits(64) <anchor link="impl-aarch64.ComputePAC.5" hover="function: bits(64) ComputePAC(bits(64) data, bits(64) modifier, bits(64) key0, bits(64) key1, boolean isgeneric)">ComputePAC</anchor>(bits(64) data, bits(64) modifier, bits(64) key0, bits(64) key1,</line>
<line>                    boolean isgeneric)</line>
<line>    if <a link="impl-aarch64.UsePACIMP.1" file="shared_pseudocode.xml" hover="function: boolean UsePACIMP(boolean isgeneric)">UsePACIMP</a>(isgeneric) then</line>
<line>        return <a link="impl-aarch64.ComputePACIMPDEF.4" file="shared_pseudocode.xml" hover="function: bits(64) ComputePACIMPDEF(bits(64) data, bits(64) modifier, bits(64) key0, bits(64) key1)">ComputePACIMPDEF</a>(data, modifier, key0, key1);</line>
<line>    if <a link="impl-aarch64.UsePACQARMA3.1" file="shared_pseudocode.xml" hover="function: boolean UsePACQARMA3(boolean isgeneric)">UsePACQARMA3</a>(isgeneric) then</line>
<line>        boolean isqarma3 = TRUE;</line>
<line>        return <a link="impl-aarch64.ComputePACQARMA.5" file="shared_pseudocode.xml" hover="function: bits(64) ComputePACQARMA(bits(64) data, bits(64) modifier, bits(64) key0, bits(64) key1, boolean isqarma3)">ComputePACQARMA</a>(data, modifier, key0, key1, isqarma3);</line>
<line>    if <a link="impl-aarch64.UsePACQARMA5.1" file="shared_pseudocode.xml" hover="function: boolean UsePACQARMA5(boolean isgeneric)">UsePACQARMA5</a>(isgeneric) then</line>
<line>        boolean isqarma3 = FALSE;</line>
<line>        return <a link="impl-aarch64.ComputePACQARMA.5" file="shared_pseudocode.xml" hover="function: bits(64) ComputePACQARMA(bits(64) data, bits(64) modifier, bits(64) key0, bits(64) key1, boolean isqarma3)">ComputePACQARMA</a>(data, modifier, key0, key1, isqarma3);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/computepac/ComputePACIMPDEF" mylink="aarch64.functions.pac.computepac.ComputePACIMPDEF" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ComputePACIMPDEF()</line>
<line>// ==================</line>
<line>// Compute IMPLEMENTATION DEFINED cryptographic algorithm to be used for PAC calculation.</line>
<line></line>
<line link="impl-aarch64.ComputePACIMPDEF.4" hover="function: bits(64) ComputePACIMPDEF(bits(64) data, bits(64) modifier, bits(64) key0, bits(64) key1)" conts="ComputePACIMPDEF">bits(64) <anchor link="impl-aarch64.ComputePACIMPDEF.4" hover="function: bits(64) ComputePACIMPDEF(bits(64) data, bits(64) modifier, bits(64) key0, bits(64) key1)">ComputePACIMPDEF</anchor>(bits(64) data, bits(64) modifier, bits(64) key0, bits(64) key1);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/computepac/ComputePACQARMA" mylink="aarch64.functions.pac.computepac.ComputePACQARMA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ComputePACQARMA()</line>
<line>// =================</line>
<line>// Compute QARMA3 or QARMA5 cryptographic algorithm for PAC calculation</line>
<line></line>
<line link="impl-aarch64.ComputePACQARMA.5" hover="function: bits(64) ComputePACQARMA(bits(64) data, bits(64) modifier, bits(64) key0, bits(64) key1, boolean isqarma3)" conts="ComputePACQARMA">bits(64) <anchor link="impl-aarch64.ComputePACQARMA.5" hover="function: bits(64) ComputePACQARMA(bits(64) data, bits(64) modifier, bits(64) key0, bits(64) key1, boolean isqarma3)">ComputePACQARMA</anchor>(bits(64) data, bits(64) modifier, bits(64) key0,</line>
<line>                         bits(64) key1, boolean isqarma3)</line>
<line>    bits(64)  workingval;</line>
<line>    bits(64)  runningmod;</line>
<line>    bits(64)  roundkey;</line>
<line>    bits(64)  modk0;</line>
<line>    constant bits(64) Alpha = 0xC0AC29B7C97C50DD&lt;63:0&gt;;</line>
<line></line>
<line>    integer iterations;</line>
<line>    RC[0] = 0x0000000000000000&lt;63:0&gt;;</line>
<line>    RC[1] = 0x13198A2E03707344&lt;63:0&gt;;</line>
<line>    RC[2] = 0xA4093822299F31D0&lt;63:0&gt;;</line>
<line></line>
<line>    if isqarma3 then</line>
<line>        iterations = 2;</line>
<line>    else // QARMA5</line>
<line>        iterations = 4;</line>
<line>        RC[3] = 0x082EFA98EC4E6C89&lt;63:0&gt;;</line>
<line>        RC[4] = 0x452821E638D01377&lt;63:0&gt;;</line>
<line></line>
<line>    modk0 = key0&lt;0&gt;:key0&lt;63:2&gt;:(key0&lt;63&gt; EOR key0&lt;1&gt;);</line>
<line>    runningmod = modifier;</line>
<line>    workingval = data EOR key0;</line>
<line></line>
<line>    for i = 0 to iterations</line>
<line>        roundkey = key1 EOR runningmod;</line>
<line>        workingval  = workingval EOR roundkey;</line>
<line>        workingval = workingval EOR RC[i];</line>
<line>        if i &gt; 0 then</line>
<line>            workingval = <a link="impl-aarch64.PACCellShuffle.1" file="shared_pseudocode.xml" hover="function: bits(64) PACCellShuffle(bits(64) indata)">PACCellShuffle</a>(workingval);</line>
<line>            workingval = <a link="impl-aarch64.PACMult.1" file="shared_pseudocode.xml" hover="function: bits(64) PACMult(bits(64) Sinput)">PACMult</a>(workingval);</line>
<line>        if isqarma3 then</line>
<line>            workingval = <a link="impl-aarch64.PACSub1.1" file="shared_pseudocode.xml" hover="function: bits(64) PACSub1(bits(64) Tinput)">PACSub1</a>(workingval);</line>
<line>        else</line>
<line>            workingval = <a link="impl-aarch64.PACSub.1" file="shared_pseudocode.xml" hover="function: bits(64) PACSub(bits(64) Tinput)">PACSub</a>(workingval);</line>
<line>        runningmod = <a link="impl-aarch64.TweakShuffle.1" file="shared_pseudocode.xml" hover="function: bits(64) TweakShuffle(bits(64) indata)">TweakShuffle</a>(runningmod&lt;63:0&gt;);</line>
<line>    roundkey = modk0 EOR runningmod;</line>
<line>    workingval = workingval EOR roundkey;</line>
<line>    workingval = <a link="impl-aarch64.PACCellShuffle.1" file="shared_pseudocode.xml" hover="function: bits(64) PACCellShuffle(bits(64) indata)">PACCellShuffle</a>(workingval);</line>
<line>    workingval = <a link="impl-aarch64.PACMult.1" file="shared_pseudocode.xml" hover="function: bits(64) PACMult(bits(64) Sinput)">PACMult</a>(workingval);</line>
<line>    if isqarma3 then</line>
<line>        workingval = <a link="impl-aarch64.PACSub1.1" file="shared_pseudocode.xml" hover="function: bits(64) PACSub1(bits(64) Tinput)">PACSub1</a>(workingval);</line>
<line>    else</line>
<line>        workingval = <a link="impl-aarch64.PACSub.1" file="shared_pseudocode.xml" hover="function: bits(64) PACSub(bits(64) Tinput)">PACSub</a>(workingval);</line>
<line>    workingval = <a link="impl-aarch64.PACCellShuffle.1" file="shared_pseudocode.xml" hover="function: bits(64) PACCellShuffle(bits(64) indata)">PACCellShuffle</a>(workingval);</line>
<line>    workingval = <a link="impl-aarch64.PACMult.1" file="shared_pseudocode.xml" hover="function: bits(64) PACMult(bits(64) Sinput)">PACMult</a>(workingval);</line>
<line>    workingval = key1 EOR workingval;</line>
<line>    workingval = <a link="impl-aarch64.PACCellInvShuffle.1" file="shared_pseudocode.xml" hover="function: bits(64) PACCellInvShuffle(bits(64) indata)">PACCellInvShuffle</a>(workingval);</line>
<line>    if isqarma3 then</line>
<line>        workingval = <a link="impl-aarch64.PACSub1.1" file="shared_pseudocode.xml" hover="function: bits(64) PACSub1(bits(64) Tinput)">PACSub1</a>(workingval);</line>
<line>    else</line>
<line>        workingval = <a link="impl-aarch64.PACInvSub.1" file="shared_pseudocode.xml" hover="function: bits(64) PACInvSub(bits(64) Tinput)">PACInvSub</a>(workingval);</line>
<line>    workingval = <a link="impl-aarch64.PACMult.1" file="shared_pseudocode.xml" hover="function: bits(64) PACMult(bits(64) Sinput)">PACMult</a>(workingval);</line>
<line>    workingval = <a link="impl-aarch64.PACCellInvShuffle.1" file="shared_pseudocode.xml" hover="function: bits(64) PACCellInvShuffle(bits(64) indata)">PACCellInvShuffle</a>(workingval);</line>
<line>    workingval = workingval EOR key0;</line>
<line>    workingval = workingval EOR runningmod;</line>
<line>    for i = 0 to iterations</line>
<line>        if isqarma3 then</line>
<line>            workingval = <a link="impl-aarch64.PACSub1.1" file="shared_pseudocode.xml" hover="function: bits(64) PACSub1(bits(64) Tinput)">PACSub1</a>(workingval);</line>
<line>        else</line>
<line>            workingval = <a link="impl-aarch64.PACInvSub.1" file="shared_pseudocode.xml" hover="function: bits(64) PACInvSub(bits(64) Tinput)">PACInvSub</a>(workingval);</line>
<line>        if i &lt; iterations then</line>
<line>            workingval = <a link="impl-aarch64.PACMult.1" file="shared_pseudocode.xml" hover="function: bits(64) PACMult(bits(64) Sinput)">PACMult</a>(workingval);</line>
<line>            workingval = <a link="impl-aarch64.PACCellInvShuffle.1" file="shared_pseudocode.xml" hover="function: bits(64) PACCellInvShuffle(bits(64) indata)">PACCellInvShuffle</a>(workingval);</line>
<line>        runningmod = <a link="impl-aarch64.TweakInvShuffle.1" file="shared_pseudocode.xml" hover="function: bits(64) TweakInvShuffle(bits(64) indata)">TweakInvShuffle</a>(runningmod&lt;63:0&gt;);</line>
<line>        roundkey = key1 EOR runningmod;</line>
<line>        workingval = workingval EOR RC[iterations-i];</line>
<line>        workingval = workingval EOR roundkey;</line>
<line>        workingval = workingval EOR Alpha;</line>
<line>    workingval = workingval EOR modk0;</line>
<line></line>
<line>    return workingval;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/computepac/PACCellInvShuffle" mylink="aarch64.functions.pac.computepac.PACCellInvShuffle" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PACCellInvShuffle()</line>
<line>// ===================</line>
<line></line>
<line link="impl-aarch64.PACCellInvShuffle.1" hover="function: bits(64) PACCellInvShuffle(bits(64) indata)" conts="PACCellInvShuffle">bits(64) <anchor link="impl-aarch64.PACCellInvShuffle.1" hover="function: bits(64) PACCellInvShuffle(bits(64) indata)">PACCellInvShuffle</anchor>(bits(64) indata)</line>
<line>    bits(64) outdata;</line>
<line>    outdata&lt;3:0&gt; = indata&lt;15:12&gt;;</line>
<line>    outdata&lt;7:4&gt; = indata&lt;27:24&gt;;</line>
<line>    outdata&lt;11:8&gt; = indata&lt;51:48&gt;;</line>
<line>    outdata&lt;15:12&gt; = indata&lt;39:36&gt;;</line>
<line>    outdata&lt;19:16&gt; = indata&lt;59:56&gt;;</line>
<line>    outdata&lt;23:20&gt; = indata&lt;47:44&gt;;</line>
<line>    outdata&lt;27:24&gt; = indata&lt;7:4&gt;;</line>
<line>    outdata&lt;31:28&gt; = indata&lt;19:16&gt;;</line>
<line>    outdata&lt;35:32&gt; = indata&lt;35:32&gt;;</line>
<line>    outdata&lt;39:36&gt; = indata&lt;55:52&gt;;</line>
<line>    outdata&lt;43:40&gt; = indata&lt;31:28&gt;;</line>
<line>    outdata&lt;47:44&gt; = indata&lt;11:8&gt;;</line>
<line>    outdata&lt;51:48&gt; = indata&lt;23:20&gt;;</line>
<line>    outdata&lt;55:52&gt; = indata&lt;3:0&gt;;</line>
<line>    outdata&lt;59:56&gt; = indata&lt;43:40&gt;;</line>
<line>    outdata&lt;63:60&gt; = indata&lt;63:60&gt;;</line>
<line>    return outdata;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/computepac/PACCellShuffle" mylink="aarch64.functions.pac.computepac.PACCellShuffle" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PACCellShuffle()</line>
<line>// ================</line>
<line></line>
<line link="impl-aarch64.PACCellShuffle.1" hover="function: bits(64) PACCellShuffle(bits(64) indata)" conts="PACCellShuffle">bits(64) <anchor link="impl-aarch64.PACCellShuffle.1" hover="function: bits(64) PACCellShuffle(bits(64) indata)">PACCellShuffle</anchor>(bits(64) indata)</line>
<line>    bits(64) outdata;</line>
<line>    outdata&lt;3:0&gt; = indata&lt;55:52&gt;;</line>
<line>    outdata&lt;7:4&gt; = indata&lt;27:24&gt;;</line>
<line>    outdata&lt;11:8&gt; = indata&lt;47:44&gt;;</line>
<line>    outdata&lt;15:12&gt; = indata&lt;3:0&gt;;</line>
<line>    outdata&lt;19:16&gt; = indata&lt;31:28&gt;;</line>
<line>    outdata&lt;23:20&gt; = indata&lt;51:48&gt;;</line>
<line>    outdata&lt;27:24&gt; = indata&lt;7:4&gt;;</line>
<line>    outdata&lt;31:28&gt; = indata&lt;43:40&gt;;</line>
<line>    outdata&lt;35:32&gt; = indata&lt;35:32&gt;;</line>
<line>    outdata&lt;39:36&gt; = indata&lt;15:12&gt;;</line>
<line>    outdata&lt;43:40&gt; = indata&lt;59:56&gt;;</line>
<line>    outdata&lt;47:44&gt; = indata&lt;23:20&gt;;</line>
<line>    outdata&lt;51:48&gt; = indata&lt;11:8&gt;;</line>
<line>    outdata&lt;55:52&gt; = indata&lt;39:36&gt;;</line>
<line>    outdata&lt;59:56&gt; = indata&lt;19:16&gt;;</line>
<line>    outdata&lt;63:60&gt; = indata&lt;63:60&gt;;</line>
<line>    return outdata;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/computepac/PACInvSub" mylink="aarch64.functions.pac.computepac.PACInvSub" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PACInvSub()</line>
<line>// ===========</line>
<line></line>
<line link="impl-aarch64.PACInvSub.1" hover="function: bits(64) PACInvSub(bits(64) Tinput)" conts="PACInvSub">bits(64) <anchor link="impl-aarch64.PACInvSub.1" hover="function: bits(64) PACInvSub(bits(64) Tinput)">PACInvSub</anchor>(bits(64) Tinput)</line>
<line>    // This is a 4-bit substitution from the PRINCE-family cipher</line>
<line>    bits(64) Toutput;</line>
<line>    for i = 0 to 15</line>
<line>        case Tinput&lt;4*i+3:4*i&gt; of</line>
<line>            when '0000'  Toutput&lt;4*i+3:4*i&gt; = '0101';</line>
<line>            when '0001'  Toutput&lt;4*i+3:4*i&gt; = '1110';</line>
<line>            when '0010'  Toutput&lt;4*i+3:4*i&gt; = '1101';</line>
<line>            when '0011'  Toutput&lt;4*i+3:4*i&gt; = '1000';</line>
<line>            when '0100'  Toutput&lt;4*i+3:4*i&gt; = '1010';</line>
<line>            when '0101'  Toutput&lt;4*i+3:4*i&gt; = '1011';</line>
<line>            when '0110'  Toutput&lt;4*i+3:4*i&gt; = '0001';</line>
<line>            when '0111'  Toutput&lt;4*i+3:4*i&gt; = '1001';</line>
<line>            when '1000'  Toutput&lt;4*i+3:4*i&gt; = '0010';</line>
<line>            when '1001'  Toutput&lt;4*i+3:4*i&gt; = '0110';</line>
<line>            when '1010'  Toutput&lt;4*i+3:4*i&gt; = '1111';</line>
<line>            when '1011'  Toutput&lt;4*i+3:4*i&gt; = '0000';</line>
<line>            when '1100'  Toutput&lt;4*i+3:4*i&gt; = '0100';</line>
<line>            when '1101'  Toutput&lt;4*i+3:4*i&gt; = '1100';</line>
<line>            when '1110'  Toutput&lt;4*i+3:4*i&gt; = '0111';</line>
<line>            when '1111'  Toutput&lt;4*i+3:4*i&gt; = '0011';</line>
<line>    return Toutput;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/computepac/PACMult" mylink="aarch64.functions.pac.computepac.PACMult" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PACMult()</line>
<line>// =========</line>
<line></line>
<line link="impl-aarch64.PACMult.1" hover="function: bits(64) PACMult(bits(64) Sinput)" conts="PACMult">bits(64) <anchor link="impl-aarch64.PACMult.1" hover="function: bits(64) PACMult(bits(64) Sinput)">PACMult</anchor>(bits(64) Sinput)</line>
<line>    bits(4)  t0;</line>
<line>    bits(4)  t1;</line>
<line>    bits(4)  t2;</line>
<line>    bits(4)  t3;</line>
<line>    bits(64) Soutput;</line>
<line></line>
<line>    for i = 0 to 3</line>
<line>        t0&lt;3:0&gt; = <a link="impl-aarch64.RotCell.2" file="shared_pseudocode.xml" hover="function: bits(4) RotCell(bits(4) incell, integer amount)">RotCell</a>(Sinput&lt;4*(i+8)+3:4*(i+8)&gt;, 1) EOR <a link="impl-aarch64.RotCell.2" file="shared_pseudocode.xml" hover="function: bits(4) RotCell(bits(4) incell, integer amount)">RotCell</a>(Sinput&lt;4*(i+4)+3:4*(i+4)&gt;, 2);</line>
<line>        t0&lt;3:0&gt; = t0&lt;3:0&gt; EOR <a link="impl-aarch64.RotCell.2" file="shared_pseudocode.xml" hover="function: bits(4) RotCell(bits(4) incell, integer amount)">RotCell</a>(Sinput&lt;4*(i)+3:4*(i)&gt;, 1);</line>
<line>        t1&lt;3:0&gt; = <a link="impl-aarch64.RotCell.2" file="shared_pseudocode.xml" hover="function: bits(4) RotCell(bits(4) incell, integer amount)">RotCell</a>(Sinput&lt;4*(i+12)+3:4*(i+12)&gt;, 1) EOR <a link="impl-aarch64.RotCell.2" file="shared_pseudocode.xml" hover="function: bits(4) RotCell(bits(4) incell, integer amount)">RotCell</a>(Sinput&lt;4*(i+4)+3:4*(i+4)&gt;, 1);</line>
<line>        t1&lt;3:0&gt; = t1&lt;3:0&gt; EOR <a link="impl-aarch64.RotCell.2" file="shared_pseudocode.xml" hover="function: bits(4) RotCell(bits(4) incell, integer amount)">RotCell</a>(Sinput&lt;4*(i)+3:4*(i)&gt;, 2);</line>
<line>        t2&lt;3:0&gt; = <a link="impl-aarch64.RotCell.2" file="shared_pseudocode.xml" hover="function: bits(4) RotCell(bits(4) incell, integer amount)">RotCell</a>(Sinput&lt;4*(i+12)+3:4*(i+12)&gt;, 2) EOR <a link="impl-aarch64.RotCell.2" file="shared_pseudocode.xml" hover="function: bits(4) RotCell(bits(4) incell, integer amount)">RotCell</a>(Sinput&lt;4*(i+8)+3:4*(i+8)&gt;, 1);</line>
<line>        t2&lt;3:0&gt; = t2&lt;3:0&gt; EOR <a link="impl-aarch64.RotCell.2" file="shared_pseudocode.xml" hover="function: bits(4) RotCell(bits(4) incell, integer amount)">RotCell</a>(Sinput&lt;4*(i)+3:4*(i)&gt;, 1);</line>
<line>        t3&lt;3:0&gt; = <a link="impl-aarch64.RotCell.2" file="shared_pseudocode.xml" hover="function: bits(4) RotCell(bits(4) incell, integer amount)">RotCell</a>(Sinput&lt;4*(i+12)+3:4*(i+12)&gt;, 1) EOR <a link="impl-aarch64.RotCell.2" file="shared_pseudocode.xml" hover="function: bits(4) RotCell(bits(4) incell, integer amount)">RotCell</a>(Sinput&lt;4*(i+8)+3:4*(i+8)&gt;, 2);</line>
<line>        t3&lt;3:0&gt; = t3&lt;3:0&gt; EOR <a link="impl-aarch64.RotCell.2" file="shared_pseudocode.xml" hover="function: bits(4) RotCell(bits(4) incell, integer amount)">RotCell</a>(Sinput&lt;4*(i+4)+3:4*(i+4)&gt;, 1);</line>
<line>        Soutput&lt;4*i+3:4*i&gt; = t3&lt;3:0&gt;;</line>
<line>        Soutput&lt;4*(i+4)+3:4*(i+4)&gt; = t2&lt;3:0&gt;;</line>
<line>        Soutput&lt;4*(i+8)+3:4*(i+8)&gt; = t1&lt;3:0&gt;;</line>
<line>        Soutput&lt;4*(i+12)+3:4*(i+12)&gt; = t0&lt;3:0&gt;;</line>
<line>    return Soutput;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/computepac/PACSub" mylink="aarch64.functions.pac.computepac.PACSub" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PACSub()</line>
<line>// ========</line>
<line></line>
<line link="impl-aarch64.PACSub.1" hover="function: bits(64) PACSub(bits(64) Tinput)" conts="PACSub">bits(64) <anchor link="impl-aarch64.PACSub.1" hover="function: bits(64) PACSub(bits(64) Tinput)">PACSub</anchor>(bits(64) Tinput)</line>
<line>    // This is a 4-bit substitution from the PRINCE-family cipher</line>
<line>    bits(64) Toutput;</line>
<line>    for i = 0 to 15</line>
<line>        case Tinput&lt;4*i+3:4*i&gt; of</line>
<line>            when '0000'  Toutput&lt;4*i+3:4*i&gt; = '1011';</line>
<line>            when '0001'  Toutput&lt;4*i+3:4*i&gt; = '0110';</line>
<line>            when '0010'  Toutput&lt;4*i+3:4*i&gt; = '1000';</line>
<line>            when '0011'  Toutput&lt;4*i+3:4*i&gt; = '1111';</line>
<line>            when '0100'  Toutput&lt;4*i+3:4*i&gt; = '1100';</line>
<line>            when '0101'  Toutput&lt;4*i+3:4*i&gt; = '0000';</line>
<line>            when '0110'  Toutput&lt;4*i+3:4*i&gt; = '1001';</line>
<line>            when '0111'  Toutput&lt;4*i+3:4*i&gt; = '1110';</line>
<line>            when '1000'  Toutput&lt;4*i+3:4*i&gt; = '0011';</line>
<line>            when '1001'  Toutput&lt;4*i+3:4*i&gt; = '0111';</line>
<line>            when '1010'  Toutput&lt;4*i+3:4*i&gt; = '0100';</line>
<line>            when '1011'  Toutput&lt;4*i+3:4*i&gt; = '0101';</line>
<line>            when '1100'  Toutput&lt;4*i+3:4*i&gt; = '1101';</line>
<line>            when '1101'  Toutput&lt;4*i+3:4*i&gt; = '0010';</line>
<line>            when '1110'  Toutput&lt;4*i+3:4*i&gt; = '0001';</line>
<line>            when '1111'  Toutput&lt;4*i+3:4*i&gt; = '1010';</line>
<line>    return Toutput;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/computepac/PacSub1" mylink="aarch64.functions.pac.computepac.PacSub1" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PacSub1()</line>
<line>// =========</line>
<line></line>
<line link="impl-aarch64.PACSub1.1" hover="function: bits(64) PACSub1(bits(64) Tinput)" conts="PACSub1">bits(64) <anchor link="impl-aarch64.PACSub1.1" hover="function: bits(64) PACSub1(bits(64) Tinput)">PACSub1</anchor>(bits(64) Tinput)</line>
<line>    // This is a 4-bit substitution from Qarma sigma1</line>
<line>    bits(64) Toutput;</line>
<line>    for i = 0 to 15</line>
<line>        case Tinput&lt;4*i+3:4*i&gt; of</line>
<line>            when '0000' Toutput&lt;4*i+3:4*i&gt; = '1010';</line>
<line>            when '0001' Toutput&lt;4*i+3:4*i&gt; = '1101';</line>
<line>            when '0010' Toutput&lt;4*i+3:4*i&gt; = '1110';</line>
<line>            when '0011' Toutput&lt;4*i+3:4*i&gt; = '0110';</line>
<line>            when '0100' Toutput&lt;4*i+3:4*i&gt; = '1111';</line>
<line>            when '0101' Toutput&lt;4*i+3:4*i&gt; = '0111';</line>
<line>            when '0110' Toutput&lt;4*i+3:4*i&gt; = '0011';</line>
<line>            when '0111' Toutput&lt;4*i+3:4*i&gt; = '0101';</line>
<line>            when '1000' Toutput&lt;4*i+3:4*i&gt; = '1001';</line>
<line>            when '1001' Toutput&lt;4*i+3:4*i&gt; = '1000';</line>
<line>            when '1010' Toutput&lt;4*i+3:4*i&gt; = '0000';</line>
<line>            when '1011' Toutput&lt;4*i+3:4*i&gt; = '1100';</line>
<line>            when '1100' Toutput&lt;4*i+3:4*i&gt; = '1011';</line>
<line>            when '1101' Toutput&lt;4*i+3:4*i&gt; = '0001';</line>
<line>            when '1110' Toutput&lt;4*i+3:4*i&gt; = '0010';</line>
<line>            when '1111' Toutput&lt;4*i+3:4*i&gt; = '0100';</line>
<line>    return Toutput;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/computepac/RC" mylink="aarch64.functions.pac.computepac.RC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// RC[]</line>
<line>// ====</line>
<line></line>
<line>array bits(64) RC[0..4];</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/computepac/RotCell" mylink="aarch64.functions.pac.computepac.RotCell" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// RotCell()</line>
<line>// =========</line>
<line></line>
<line link="impl-aarch64.RotCell.2" hover="function: bits(4) RotCell(bits(4) incell, integer amount)" conts="RotCell">bits(4) <anchor link="impl-aarch64.RotCell.2" hover="function: bits(4) RotCell(bits(4) incell, integer amount)">RotCell</anchor>(bits(4) incell, integer amount)</line>
<line>    bits(8) tmp;</line>
<line>    bits(4) outcell;</line>
<line></line>
<line>    // assert amount&gt;3 || amount&lt;1;</line>
<line>    tmp&lt;7:0&gt; = incell&lt;3:0&gt;:incell&lt;3:0&gt;;</line>
<line>    outcell = tmp&lt;7-amount:4-amount&gt;;</line>
<line>    return outcell;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/computepac/TweakCellInvRot" mylink="aarch64.functions.pac.computepac.TweakCellInvRot" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TweakCellInvRot()</line>
<line>// =================</line>
<line></line>
<line link="impl-aarch64.TweakCellInvRot.1" hover="function: bits(4) TweakCellInvRot(bits(4) incell)" conts="TweakCellInvRot">bits(4) <anchor link="impl-aarch64.TweakCellInvRot.1" hover="function: bits(4) TweakCellInvRot(bits(4) incell)">TweakCellInvRot</anchor>(bits(4) incell)</line>
<line>    bits(4) outcell;</line>
<line>    outcell&lt;3&gt; = incell&lt;2&gt;;</line>
<line>    outcell&lt;2&gt; = incell&lt;1&gt;;</line>
<line>    outcell&lt;1&gt; = incell&lt;0&gt;;</line>
<line>    outcell&lt;0&gt; = incell&lt;0&gt; EOR incell&lt;3&gt;;</line>
<line>    return outcell;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/computepac/TweakCellRot" mylink="aarch64.functions.pac.computepac.TweakCellRot" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TweakCellRot()</line>
<line>// ==============</line>
<line></line>
<line link="impl-aarch64.TweakCellRot.1" hover="function: bits(4) TweakCellRot(bits(4) incell)" conts="TweakCellRot">bits(4) <anchor link="impl-aarch64.TweakCellRot.1" hover="function: bits(4) TweakCellRot(bits(4) incell)">TweakCellRot</anchor>(bits(4) incell)</line>
<line>    bits(4) outcell;</line>
<line>    outcell&lt;3&gt; = incell&lt;0&gt; EOR incell&lt;1&gt;;</line>
<line>    outcell&lt;2&gt; = incell&lt;3&gt;;</line>
<line>    outcell&lt;1&gt; = incell&lt;2&gt;;</line>
<line>    outcell&lt;0&gt; = incell&lt;1&gt;;</line>
<line>    return outcell;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/computepac/TweakInvShuffle" mylink="aarch64.functions.pac.computepac.TweakInvShuffle" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TweakInvShuffle()</line>
<line>// =================</line>
<line></line>
<line link="impl-aarch64.TweakInvShuffle.1" hover="function: bits(64) TweakInvShuffle(bits(64) indata)" conts="TweakInvShuffle">bits(64) <anchor link="impl-aarch64.TweakInvShuffle.1" hover="function: bits(64) TweakInvShuffle(bits(64) indata)">TweakInvShuffle</anchor>(bits(64) indata)</line>
<line>    bits(64) outdata;</line>
<line>    outdata&lt;3:0&gt; = <a link="impl-aarch64.TweakCellInvRot.1" file="shared_pseudocode.xml" hover="function: bits(4) TweakCellInvRot(bits(4) incell)">TweakCellInvRot</a>(indata&lt;51:48&gt;);</line>
<line>    outdata&lt;7:4&gt; = indata&lt;55:52&gt;;</line>
<line>    outdata&lt;11:8&gt; = indata&lt;23:20&gt;;</line>
<line>    outdata&lt;15:12&gt; = indata&lt;27:24&gt;;</line>
<line>    outdata&lt;19:16&gt; = indata&lt;3:0&gt;;</line>
<line>    outdata&lt;23:20&gt; = indata&lt;7:4&gt;;</line>
<line>    outdata&lt;27:24&gt; = <a link="impl-aarch64.TweakCellInvRot.1" file="shared_pseudocode.xml" hover="function: bits(4) TweakCellInvRot(bits(4) incell)">TweakCellInvRot</a>(indata&lt;11:8&gt;);</line>
<line>    outdata&lt;31:28&gt; = indata&lt;15:12&gt;;</line>
<line>    outdata&lt;35:32&gt; = <a link="impl-aarch64.TweakCellInvRot.1" file="shared_pseudocode.xml" hover="function: bits(4) TweakCellInvRot(bits(4) incell)">TweakCellInvRot</a>(indata&lt;31:28&gt;);</line>
<line>    outdata&lt;39:36&gt; = <a link="impl-aarch64.TweakCellInvRot.1" file="shared_pseudocode.xml" hover="function: bits(4) TweakCellInvRot(bits(4) incell)">TweakCellInvRot</a>(indata&lt;63:60&gt;);</line>
<line>    outdata&lt;43:40&gt; = <a link="impl-aarch64.TweakCellInvRot.1" file="shared_pseudocode.xml" hover="function: bits(4) TweakCellInvRot(bits(4) incell)">TweakCellInvRot</a>(indata&lt;59:56&gt;);</line>
<line>    outdata&lt;47:44&gt; = <a link="impl-aarch64.TweakCellInvRot.1" file="shared_pseudocode.xml" hover="function: bits(4) TweakCellInvRot(bits(4) incell)">TweakCellInvRot</a>(indata&lt;19:16&gt;);</line>
<line>    outdata&lt;51:48&gt; = indata&lt;35:32&gt;;</line>
<line>    outdata&lt;55:52&gt; = indata&lt;39:36&gt;;</line>
<line>    outdata&lt;59:56&gt; = indata&lt;43:40&gt;;</line>
<line>    outdata&lt;63:60&gt; = <a link="impl-aarch64.TweakCellInvRot.1" file="shared_pseudocode.xml" hover="function: bits(4) TweakCellInvRot(bits(4) incell)">TweakCellInvRot</a>(indata&lt;47:44&gt;);</line>
<line>    return outdata;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/computepac/TweakShuffle" mylink="aarch64.functions.pac.computepac.TweakShuffle" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TweakShuffle()</line>
<line>// ==============</line>
<line></line>
<line link="impl-aarch64.TweakShuffle.1" hover="function: bits(64) TweakShuffle(bits(64) indata)" conts="TweakShuffle">bits(64) <anchor link="impl-aarch64.TweakShuffle.1" hover="function: bits(64) TweakShuffle(bits(64) indata)">TweakShuffle</anchor>(bits(64) indata)</line>
<line>    bits(64) outdata;</line>
<line>    outdata&lt;3:0&gt; = indata&lt;19:16&gt;;</line>
<line>    outdata&lt;7:4&gt; = indata&lt;23:20&gt;;</line>
<line>    outdata&lt;11:8&gt; = <a link="impl-aarch64.TweakCellRot.1" file="shared_pseudocode.xml" hover="function: bits(4) TweakCellRot(bits(4) incell)">TweakCellRot</a>(indata&lt;27:24&gt;);</line>
<line>    outdata&lt;15:12&gt; = indata&lt;31:28&gt;;</line>
<line>    outdata&lt;19:16&gt; = <a link="impl-aarch64.TweakCellRot.1" file="shared_pseudocode.xml" hover="function: bits(4) TweakCellRot(bits(4) incell)">TweakCellRot</a>(indata&lt;47:44&gt;);</line>
<line>    outdata&lt;23:20&gt; = indata&lt;11:8&gt;;</line>
<line>    outdata&lt;27:24&gt; = indata&lt;15:12&gt;;</line>
<line>    outdata&lt;31:28&gt; = <a link="impl-aarch64.TweakCellRot.1" file="shared_pseudocode.xml" hover="function: bits(4) TweakCellRot(bits(4) incell)">TweakCellRot</a>(indata&lt;35:32&gt;);</line>
<line>    outdata&lt;35:32&gt; = indata&lt;51:48&gt;;</line>
<line>    outdata&lt;39:36&gt; = indata&lt;55:52&gt;;</line>
<line>    outdata&lt;43:40&gt; = indata&lt;59:56&gt;;</line>
<line>    outdata&lt;47:44&gt; = <a link="impl-aarch64.TweakCellRot.1" file="shared_pseudocode.xml" hover="function: bits(4) TweakCellRot(bits(4) incell)">TweakCellRot</a>(indata&lt;63:60&gt;);</line>
<line>    outdata&lt;51:48&gt; = <a link="impl-aarch64.TweakCellRot.1" file="shared_pseudocode.xml" hover="function: bits(4) TweakCellRot(bits(4) incell)">TweakCellRot</a>(indata&lt;3:0&gt;);</line>
<line>    outdata&lt;55:52&gt; = indata&lt;7:4&gt;;</line>
<line>    outdata&lt;59:56&gt; = <a link="impl-aarch64.TweakCellRot.1" file="shared_pseudocode.xml" hover="function: bits(4) TweakCellRot(bits(4) incell)">TweakCellRot</a>(indata&lt;43:40&gt;);</line>
<line>    outdata&lt;63:60&gt; = <a link="impl-aarch64.TweakCellRot.1" file="shared_pseudocode.xml" hover="function: bits(4) TweakCellRot(bits(4) incell)">TweakCellRot</a>(indata&lt;39:36&gt;);</line>
<line>    return outdata;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/computepac/UsePACIMP" mylink="aarch64.functions.pac.computepac.UsePACIMP" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// UsePACIMP()</line>
<line>// ===========</line>
<line>// Checks whether IMPLEMENTATION DEFINED cryptographic algorithm to be used for PAC</line>
<line>// calculation.</line>
<line></line>
<line link="impl-aarch64.UsePACIMP.1" hover="function: boolean UsePACIMP(boolean isgeneric)" conts="UsePACIMP">boolean <anchor link="impl-aarch64.UsePACIMP.1" hover="function: boolean UsePACIMP(boolean isgeneric)">UsePACIMP</anchor>(boolean isgeneric)</line>
<line>    return if isgeneric then <a link="impl-aarch64.HavePACIMPGeneric.0" file="shared_pseudocode.xml" hover="function: boolean HavePACIMPGeneric()">HavePACIMPGeneric</a>() else <a link="impl-aarch64.HavePACIMPAuth.0" file="shared_pseudocode.xml" hover="function: boolean HavePACIMPAuth()">HavePACIMPAuth</a>();</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/computepac/UsePACQARMA3" mylink="aarch64.functions.pac.computepac.UsePACQARMA3" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// UsePACQARMA3()</line>
<line>// ==============</line>
<line>// Checks whether QARMA3 cryptographic algorithm to be used for PAC calculation.</line>
<line></line>
<line link="impl-aarch64.UsePACQARMA3.1" hover="function: boolean UsePACQARMA3(boolean isgeneric)" conts="UsePACQARMA3">boolean <anchor link="impl-aarch64.UsePACQARMA3.1" hover="function: boolean UsePACQARMA3(boolean isgeneric)">UsePACQARMA3</anchor>(boolean isgeneric)</line>
<line>    return if isgeneric then <a link="impl-aarch64.HavePACQARMA3Generic.0" file="shared_pseudocode.xml" hover="function: boolean HavePACQARMA3Generic()">HavePACQARMA3Generic</a>() else <a link="impl-aarch64.HavePACQARMA3Auth.0" file="shared_pseudocode.xml" hover="function: boolean HavePACQARMA3Auth()">HavePACQARMA3Auth</a>();</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/computepac/UsePACQARMA5" mylink="aarch64.functions.pac.computepac.UsePACQARMA5" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// UsePACQARMA5()</line>
<line>// ==============</line>
<line>// Checks whether QARMA5 cryptographic algorithm to be used for PAC calculation.</line>
<line></line>
<line link="impl-aarch64.UsePACQARMA5.1" hover="function: boolean UsePACQARMA5(boolean isgeneric)" conts="UsePACQARMA5">boolean <anchor link="impl-aarch64.UsePACQARMA5.1" hover="function: boolean UsePACQARMA5(boolean isgeneric)">UsePACQARMA5</anchor>(boolean isgeneric)</line>
<line>    return if isgeneric then <a link="impl-aarch64.HavePACQARMA5Generic.0" file="shared_pseudocode.xml" hover="function: boolean HavePACQARMA5Generic()">HavePACQARMA5Generic</a>() else <a link="impl-aarch64.HavePACQARMA5Auth.0" file="shared_pseudocode.xml" hover="function: boolean HavePACQARMA5Auth()">HavePACQARMA5Auth</a>();</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/pac/ConstPACField" mylink="aarch64.functions.pac.pac.ConstPACField" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ConstPACField()</line>
<line>// ===============</line>
<line>// Returns TRUE if bit&lt;55&gt; can be used to determine the size of the PAC field, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.ConstPACField.0" hover="function: boolean ConstPACField()" conts="ConstPACField">boolean <anchor link="impl-aarch64.ConstPACField.0" hover="function: boolean ConstPACField()">ConstPACField</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_CONSTPACFIELD);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/pac/HaveEnhancedPAC" mylink="aarch64.functions.pac.pac.HaveEnhancedPAC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveEnhancedPAC()</line>
<line>// =================</line>
<line>// Returns TRUE if support for EnhancedPAC is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveEnhancedPAC.0" hover="function: boolean HaveEnhancedPAC()" conts="HaveEnhancedPAC">boolean <anchor link="impl-aarch64.HaveEnhancedPAC.0" hover="function: boolean HaveEnhancedPAC()">HaveEnhancedPAC</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_EPAC);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/pac/HaveEnhancedPAC2" mylink="aarch64.functions.pac.pac.HaveEnhancedPAC2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveEnhancedPAC2()</line>
<line>// ==================</line>
<line>// Returns TRUE if support for EnhancedPAC2 is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveEnhancedPAC2.0" hover="function: boolean HaveEnhancedPAC2()" conts="HaveEnhancedPAC2">boolean <anchor link="impl-aarch64.HaveEnhancedPAC2.0" hover="function: boolean HaveEnhancedPAC2()">HaveEnhancedPAC2</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_PAuth2);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/pac/HaveFPAC" mylink="aarch64.functions.pac.pac.HaveFPAC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFPAC()</line>
<line>// ==========</line>
<line>// Returns TRUE if support for FPAC is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveFPAC.0" hover="function: boolean HaveFPAC()" conts="HaveFPAC">boolean <anchor link="impl-aarch64.HaveFPAC.0" hover="function: boolean HaveFPAC()">HaveFPAC</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_FPAC);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/pac/HaveFPACCombined" mylink="aarch64.functions.pac.pac.HaveFPACCombined" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFPACCombined()</line>
<line>// ==================</line>
<line>// Returns TRUE if support for FPACCombined is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveFPACCombined.0" hover="function: boolean HaveFPACCombined()" conts="HaveFPACCombined">boolean <anchor link="impl-aarch64.HaveFPACCombined.0" hover="function: boolean HaveFPACCombined()">HaveFPACCombined</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_FPACCOMBINE);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/pac/HavePACExt" mylink="aarch64.functions.pac.pac.HavePACExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HavePACExt()</line>
<line>// ============</line>
<line>// Returns TRUE if support for the PAC extension is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HavePACExt.0" hover="function: boolean HavePACExt()" conts="HavePACExt">boolean <anchor link="impl-aarch64.HavePACExt.0" hover="function: boolean HavePACExt()">HavePACExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_PAuth);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/pac/HavePACIMPAuth" mylink="aarch64.functions.pac.pac.HavePACIMPAuth" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HavePACIMPAuth()</line>
<line>// ================</line>
<line>// Returns TRUE if support for PAC IMP Auth is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HavePACIMPAuth.0" hover="function: boolean HavePACIMPAuth()" conts="HavePACIMPAuth">boolean <anchor link="impl-aarch64.HavePACIMPAuth.0" hover="function: boolean HavePACIMPAuth()">HavePACIMPAuth</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_PACIMP);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/pac/HavePACIMPGeneric" mylink="aarch64.functions.pac.pac.HavePACIMPGeneric" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HavePACIMPGeneric()</line>
<line>// ===================</line>
<line>// Returns TRUE if support for PAC IMP Generic is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HavePACIMPGeneric.0" hover="function: boolean HavePACIMPGeneric()" conts="HavePACIMPGeneric">boolean <anchor link="impl-aarch64.HavePACIMPGeneric.0" hover="function: boolean HavePACIMPGeneric()">HavePACIMPGeneric</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_PACIMP);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/pac/HavePACQARMA3Auth" mylink="aarch64.functions.pac.pac.HavePACQARMA3Auth" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HavePACQARMA3Auth()</line>
<line>// ===================</line>
<line>// Returns TRUE if support for PAC QARMA3 Auth is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HavePACQARMA3Auth.0" hover="function: boolean HavePACQARMA3Auth()" conts="HavePACQARMA3Auth">boolean <anchor link="impl-aarch64.HavePACQARMA3Auth.0" hover="function: boolean HavePACQARMA3Auth()">HavePACQARMA3Auth</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_PACQARMA3);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/pac/HavePACQARMA3Generic" mylink="aarch64.functions.pac.pac.HavePACQARMA3Generic" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HavePACQARMA3Generic()</line>
<line>// ======================</line>
<line>// Returns TRUE if support for PAC QARMA3 Generic is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HavePACQARMA3Generic.0" hover="function: boolean HavePACQARMA3Generic()" conts="HavePACQARMA3Generic">boolean <anchor link="impl-aarch64.HavePACQARMA3Generic.0" hover="function: boolean HavePACQARMA3Generic()">HavePACQARMA3Generic</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_PACQARMA3);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/pac/HavePACQARMA5Auth" mylink="aarch64.functions.pac.pac.HavePACQARMA5Auth" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HavePACQARMA5Auth()</line>
<line>// ===================</line>
<line>// Returns TRUE if support for PAC QARMA5 Auth is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HavePACQARMA5Auth.0" hover="function: boolean HavePACQARMA5Auth()" conts="HavePACQARMA5Auth">boolean <anchor link="impl-aarch64.HavePACQARMA5Auth.0" hover="function: boolean HavePACQARMA5Auth()">HavePACQARMA5Auth</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_PACQARMA5);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/pac/HavePACQARMA5Generic" mylink="aarch64.functions.pac.pac.HavePACQARMA5Generic" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HavePACQARMA5Generic()</line>
<line>// ======================</line>
<line>// Returns TRUE if support for PAC QARMA5 Generic is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HavePACQARMA5Generic.0" hover="function: boolean HavePACQARMA5Generic()" conts="HavePACQARMA5Generic">boolean <anchor link="impl-aarch64.HavePACQARMA5Generic.0" hover="function: boolean HavePACQARMA5Generic()">HavePACQARMA5Generic</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_PACQARMA5);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/pac/PtrHasUpperAndLowerAddRanges" mylink="aarch64.functions.pac.pac.PtrHasUpperAndLowerAddRanges" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PtrHasUpperAndLowerAddRanges()</line>
<line>// ==============================</line>
<line>// Returns TRUE if the pointer has upper and lower address ranges, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.PtrHasUpperAndLowerAddRanges.0" hover="function: boolean PtrHasUpperAndLowerAddRanges()" conts="PtrHasUpperAndLowerAddRanges">boolean <anchor link="impl-aarch64.PtrHasUpperAndLowerAddRanges.0" hover="function: boolean PtrHasUpperAndLowerAddRanges()">PtrHasUpperAndLowerAddRanges</anchor>()</line>
<line>    regime = <a link="impl-shared.TranslationRegime.1" file="shared_pseudocode.xml" hover="function: Regime TranslationRegime(bits(2) el)">TranslationRegime</a>(PSTATE.EL);</line>
<line>    return <a link="impl-shared.HasUnprivileged.1" file="shared_pseudocode.xml" hover="function: boolean HasUnprivileged(Regime regime)">HasUnprivileged</a>(regime);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/strip/Strip" mylink="aarch64.functions.pac.strip.Strip" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Strip()</line>
<line>// =======</line>
<line>// Strip() returns a 64-bit value containing A, but replacing the pointer authentication</line>
<line>// code field bits with the extension of the address bits. This can apply to either</line>
<line>// instructions or data, where, as the use of tagged pointers is distinct, it might be</line>
<line>// handled differently.</line>
<line></line>
<line link="impl-aarch64.Strip.2" hover="function: bits(64) Strip(bits(64) A, boolean data)" conts="Strip">bits(64) <anchor link="impl-aarch64.Strip.2" hover="function: bits(64) Strip(bits(64) A, boolean data)">Strip</anchor>(bits(64) A, boolean data)</line>
<line>    bits(64) original_ptr;</line>
<line>    bits(64) extfield;</line>
<line>    boolean tbi = <a link="impl-shared.EffectiveTBI.3" file="shared_pseudocode.xml" hover="function: bit EffectiveTBI(bits(64) address, boolean IsInstr, bits(2) el)">EffectiveTBI</a>(A, !data, PSTATE.EL) == '1';</line>
<line>    boolean mtx = <a link="impl-shared.EffectiveMTX.3" file="shared_pseudocode.xml" hover="function: bit EffectiveMTX(bits(64) address, boolean is_instr, bits(2) el)">EffectiveMTX</a>(A, !data, PSTATE.EL) == '1';</line>
<line>    integer bottom_PAC_bit = <a link="impl-aarch64.CalculateBottomPACBit.1" file="shared_pseudocode.xml" hover="function: integer CalculateBottomPACBit(bit top_bit)">CalculateBottomPACBit</a>(A&lt;55&gt;);</line>
<line>    extfield = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(A&lt;55&gt;, 64);</line>
<line></line>
<line>    // If the VA is 56 or 55 bits and Top Byte is Ignored,</line>
<line>    // there are no unused bits left for the PAC</line>
<line>    if tbi &amp;&amp; bottom_PAC_bit &gt;= 55 then</line>
<line>        return A;</line>
<line></line>
<line>    if tbi then</line>
<line>        original_ptr = (A&lt;63:56&gt; :</line>
<line>                        extfield&lt;(56-bottom_PAC_bit)-1:0&gt; : A&lt;bottom_PAC_bit-1:0&gt;);</line>
<line>    elsif mtx then</line>
<line>        original_ptr = (extfield&lt;63:60&gt; : A&lt;59:56&gt; :</line>
<line>                        extfield&lt;(56-bottom_PAC_bit)-1:0&gt; : A&lt;bottom_PAC_bit-1:0&gt;);</line>
<line>    else</line>
<line>        original_ptr =  extfield&lt;(64-bottom_PAC_bit)-1:0&gt; : A&lt;bottom_PAC_bit-1:0&gt;;</line>
<line></line>
<line>    return original_ptr;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/pac/trappacuse/TrapPACUse" mylink="aarch64.functions.pac.trappacuse.TrapPACUse" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TrapPACUse()</line>
<line>// ============</line>
<line>// Used for the trapping of the pointer authentication functions by higher exception</line>
<line>// levels.</line>
<line></line>
<line link="impl-aarch64.TrapPACUse.1" hover="function: TrapPACUse(bits(2) target_el)" conts="TrapPACUse"><anchor link="impl-aarch64.TrapPACUse.1" hover="function: TrapPACUse(bits(2) target_el)">TrapPACUse</anchor>(bits(2) target_el)</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(target_el) &amp;&amp; target_el !=  <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(target_el) &gt;= <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL);</line>
<line></line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    <a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> exception;</line>
<line>    vect_offset = 0;</line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_PACTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_PACTrap</a>);</line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(target_el, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/ras/AArch64.ESBOperation" mylink="aarch64.functions.ras.AArch64.ESBOperation" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ESBOperation()</line>
<line>// ======================</line>
<line>// Perform the AArch64 ESB operation, either for ESB executed in AArch64 state, or for</line>
<line>// ESB in AArch32 state when SError interrupts are routed to an Exception level using</line>
<line>// AArch64</line>
<line></line>
<line link="AArch64.ESBOperation.0" hover="function: AArch64.ESBOperation()" conts="AArch64.ESBOperation"><anchor link="AArch64.ESBOperation.0" hover="function: AArch64.ESBOperation()">AArch64.ESBOperation</anchor>()</line>
<line>    bits(2) target_el;</line>
<line>    boolean masked;</line>
<line></line>
<line>    (masked, target_el) = <a link="AArch64.PhysicalSErrorTarget.0" file="shared_pseudocode.xml" hover="function: (boolean, bits(2)) AArch64.PhysicalSErrorTarget()">AArch64.PhysicalSErrorTarget</a>();</line>
<line></line>
<line>    intdis = <a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() || <a link="impl-shared.ExternalDebugInterruptsDisabled.1" file="shared_pseudocode.xml" hover="function: boolean ExternalDebugInterruptsDisabled(bits(2) target)">ExternalDebugInterruptsDisabled</a>(target_el);</line>
<line>    masked = masked || intdis;</line>
<line></line>
<line>    // Check for a masked Physical SError pending that can be synchronized</line>
<line>    // by an Error synchronization event.</line>
<line>    if masked &amp;&amp; <a link="impl-shared.IsSynchronizablePhysicalSErrorPending.0" file="shared_pseudocode.xml" hover="function: boolean IsSynchronizablePhysicalSErrorPending()">IsSynchronizablePhysicalSErrorPending</a>() then</line>
<line>        // This function might be called for an interworking case, and INTdis is masking</line>
<line>        // the SError interrupt.</line>
<line>        if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>()) then</line>
<line>            bits(32) syndrome = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32);</line>
<line>            syndrome&lt;31&gt; = '1'; // A</line>
<line>            syndrome&lt;15:0&gt; = <a link="AArch32.PhysicalSErrorSyndrome.0" file="shared_pseudocode.xml" hover="function: bits(16) AArch32.PhysicalSErrorSyndrome()">AArch32.PhysicalSErrorSyndrome</a>();</line>
<line>            DISR = syndrome;</line>
<line>        else</line>
<line>            implicit_esb = FALSE;</line>
<line>            bits(64) syndrome = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>            syndrome&lt;31&gt; = '1'; // A</line>
<line>            syndrome&lt;24:0&gt; = <a link="AArch64.PhysicalSErrorSyndrome.1" file="shared_pseudocode.xml" hover="function: bits(25) AArch64.PhysicalSErrorSyndrome(boolean implicit_esb)">AArch64.PhysicalSErrorSyndrome</a>(implicit_esb);</line>
<line>            DISR_EL1 = syndrome;</line>
<line>        <a link="impl-shared.ClearPendingPhysicalSError.0" file="shared_pseudocode.xml" hover="function: ClearPendingPhysicalSError()">ClearPendingPhysicalSError</a>();               // Set ISR_EL1.A to 0</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/ras/AArch64.EncodeAsyncErrorSyndrome" mylink="aarch64.functions.ras.AArch64.EncodeAsyncErrorSyndrome" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.EncodeAsyncErrorSyndrome()</line>
<line>// ==================================</line>
<line>// Return the encoding for corresponding ErrorState.</line>
<line></line>
<line link="AArch64.EncodeAsyncErrorSyndrome.1" hover="function: bits(3) AArch64.EncodeAsyncErrorSyndrome(ErrorState errorstate)" conts="AArch64.EncodeAsyncErrorSyndrome">bits(3) <anchor link="AArch64.EncodeAsyncErrorSyndrome.1" hover="function: bits(3) AArch64.EncodeAsyncErrorSyndrome(ErrorState errorstate)">AArch64.EncodeAsyncErrorSyndrome</anchor>(<a link="ErrorState" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState</a> errorstate)</line>
<line>    case errorstate of</line>
<line>        when <a link="ErrorState_UC" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UC</a>  return '000';</line>
<line>        when <a link="ErrorState_UEU" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UEU</a> return '001';</line>
<line>        when <a link="ErrorState_UEO" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UEO</a> return '010';</line>
<line>        when <a link="ErrorState_UER" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UER</a> return '011';</line>
<line>        when <a link="ErrorState_CE" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_CE</a>  return '110';</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/ras/AArch64.EncodeSyncErrorSyndrome" mylink="aarch64.functions.ras.AArch64.EncodeSyncErrorSyndrome" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.EncodeSyncErrorSyndrome()</line>
<line>// =================================</line>
<line>// Return the encoding for corresponding ErrorState.</line>
<line></line>
<line link="AArch64.EncodeSyncErrorSyndrome.1" hover="function: bits(2) AArch64.EncodeSyncErrorSyndrome(ErrorState errorstate)" conts="AArch64.EncodeSyncErrorSyndrome">bits(2) <anchor link="AArch64.EncodeSyncErrorSyndrome.1" hover="function: bits(2) AArch64.EncodeSyncErrorSyndrome(ErrorState errorstate)">AArch64.EncodeSyncErrorSyndrome</anchor>(<a link="ErrorState" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState</a> errorstate)</line>
<line>    case errorstate of</line>
<line>        when <a link="ErrorState_UC" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UC</a>  return '10';</line>
<line>        when <a link="ErrorState_UEO" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UEO</a> return '11';</line>
<line>        when <a link="ErrorState_UER" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UER</a> return '00';</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/ras/AArch64.PhysicalSErrorSyndrome" mylink="aarch64.functions.ras.AArch64.PhysicalSErrorSyndrome" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.PhysicalSErrorSyndrome()</line>
<line>// ================================</line>
<line>// Generate SError syndrome.</line>
<line></line>
<line link="AArch64.PhysicalSErrorSyndrome.1" hover="function: bits(25) AArch64.PhysicalSErrorSyndrome(boolean implicit_esb)" conts="AArch64.PhysicalSErrorSyndrome">bits(25) <anchor link="AArch64.PhysicalSErrorSyndrome.1" hover="function: bits(25) AArch64.PhysicalSErrorSyndrome(boolean implicit_esb)">AArch64.PhysicalSErrorSyndrome</anchor>(boolean implicit_esb)</line>
<line>    bits(25) syndrome = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(25);</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = <a link="impl-shared.GetPendingPhysicalSError.0" file="shared_pseudocode.xml" hover="function: FaultRecord GetPendingPhysicalSError()">GetPendingPhysicalSError</a>();</line>
<line>    <a link="ErrorState" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState</a> errorstate = <a link="AArch64.PEErrorState.1" file="shared_pseudocode.xml" hover="function: ErrorState AArch64.PEErrorState(FaultRecord fault)">AArch64.PEErrorState</a>(fault);</line>
<line>    if errorstate == <a link="ErrorState_Uncategorized" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_Uncategorized</a> then</line>
<line>        syndrome = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(25);</line>
<line>    elsif errorstate == <a link="ErrorState_IMPDEF" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_IMPDEF</a> then</line>
<line>        syndrome&lt;24&gt; = '1';                                             // IDS</line>
<line>        syndrome&lt;23:0&gt; = bits(24) IMPLEMENTATION_DEFINED "IMPDEF <a link="ErrorState" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState</a>";</line>
<line>    else</line>
<line>        syndrome&lt;24&gt; = '0';                                             // IDS</line>
<line>        syndrome&lt;13&gt; = (if implicit_esb then '1' else '0');             // IESB</line>
<line>        syndrome&lt;12:10&gt; = <a link="AArch64.EncodeAsyncErrorSyndrome.1" file="shared_pseudocode.xml" hover="function: bits(3) AArch64.EncodeAsyncErrorSyndrome(ErrorState errorstate)">AArch64.EncodeAsyncErrorSyndrome</a>(errorstate); // AET</line>
<line>        syndrome&lt;9&gt; = fault.extflag;                                    // EA</line>
<line>        syndrome&lt;5:0&gt; = '010001';                                       // DFSC</line>
<line>    return syndrome;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/ras/AArch64.vESBOperation" mylink="aarch64.functions.ras.AArch64.vESBOperation" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.vESBOperation()</line>
<line>// =======================</line>
<line>// Perform the AArch64 ESB operation for virtual SError interrupts, either for ESB</line>
<line>// executed in AArch64 state, or for ESB in AArch32 state with EL2 using AArch64 state</line>
<line></line>
<line link="AArch64.vESBOperation.0" hover="function: AArch64.vESBOperation()" conts="AArch64.vESBOperation"><anchor link="AArch64.vESBOperation.0" hover="function: AArch64.vESBOperation()">AArch64.vESBOperation</anchor>()</line>
<line>    assert PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>();</line>
<line></line>
<line>    // If physical SError interrupts are routed to EL2, and TGE is not set, then a virtual</line>
<line>    // SError interrupt might be pending</line>
<line>    vSEI_enabled = HCR_EL2.TGE == '0' &amp;&amp; HCR_EL2.AMO == '1';</line>
<line>    vSEI_pending = vSEI_enabled &amp;&amp; HCR_EL2.VSE == '1';</line>
<line>    vintdis      = <a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() || <a link="impl-shared.ExternalDebugInterruptsDisabled.1" file="shared_pseudocode.xml" hover="function: boolean ExternalDebugInterruptsDisabled(bits(2) target)">ExternalDebugInterruptsDisabled</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line>    vmasked      = vintdis || PSTATE.A == '1';</line>
<line></line>
<line>    // Check for a masked virtual SError pending</line>
<line>    if vSEI_pending &amp;&amp; vmasked then</line>
<line>        // This function might be called for the interworking case, and INTdis is masking</line>
<line>        // the virtual SError interrupt.</line>
<line>        if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>            bits(32) target = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32);</line>
<line>            target&lt;31&gt; = '1';              // A</line>
<line>            target&lt;15:14&gt; = VDFSR&lt;15:14&gt;;  // AET</line>
<line>            target&lt;12&gt;    = VDFSR&lt;12&gt;;     // ExT</line>
<line>            target&lt;9&gt;     = TTBCR.EAE;     // LPAE</line>
<line>            if TTBCR.EAE == '1' then       // Long-descriptor format</line>
<line>                target&lt;5:0&gt;    = '010001'; // STATUS</line>
<line>            else                           // Short-descriptor format</line>
<line>                target&lt;10,3:0&gt; = '10110';  // FS</line>
<line>            VDISR = target;</line>
<line>        else</line>
<line>            bits(64) target = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>            target&lt;31&gt; = '1';              // A</line>
<line>            target&lt;24:0&gt; = VSESR_EL2&lt;24:0&gt;;</line>
<line>            VDISR_EL2 = target;</line>
<line>        HCR_EL2.VSE = '0';                       // Clear pending virtual SError</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/rcw/ProtectionEnabled" mylink="aarch64.functions.rcw.ProtectionEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ProtectionEnabled()</line>
<line>// ===================</line>
<line>// Returns TRUE if the ProtectedBit is</line>
<line>// enabled in the current Exception level.</line>
<line></line>
<line link="impl-aarch64.ProtectionEnabled.1" hover="function: boolean ProtectionEnabled(bits(2) el)" conts="ProtectionEnabled">boolean <anchor link="impl-aarch64.ProtectionEnabled.1" hover="function: boolean ProtectionEnabled(bits(2) el)">ProtectionEnabled</anchor>(bits(2) el)</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(el);</line>
<line>    regime = <a link="impl-shared.S1TranslationRegime.1" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime(bits(2) el)">S1TranslationRegime</a>(el);</line>
<line>    assert(!<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(regime));</line>
<line>    if (!<a link="impl-aarch64.IsD128Enabled.1" file="shared_pseudocode.xml" hover="function: boolean IsD128Enabled(bits(2) el)">IsD128Enabled</a>(el)) then</line>
<line>        case regime of</line>
<line>            when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>                return <a link="impl-aarch64.IsTCR2EL1Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL1Enabled()">IsTCR2EL1Enabled</a>() &amp;&amp; TCR2_EL1.PnCH == '1';</line>
<line>            when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>                return <a link="impl-aarch64.IsTCR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL2Enabled()">IsTCR2EL2Enabled</a>() &amp;&amp; TCR2_EL2.PnCH == '1';</line>
<line>            when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>                return TCR_EL3.PnCH == '1';</line>
<line>    else</line>
<line>        return TRUE;</line>
<line>    return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/rcw/RCW128_PROTECTED_BIT" mylink="aarch64.functions.rcw.RCW128_PROTECTED_BIT" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="RCW128_PROTECTED_BIT" hover="constant integer RCW128_PROTECTED_BIT = 114" conts="RCW128_PROTECTED_BIT">constant integer <anchor link="RCW128_PROTECTED_BIT" hover="constant integer RCW128_PROTECTED_BIT = 114">RCW128_PROTECTED_BIT</anchor> = 114;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/rcw/RCW64_PROTECTED_BIT" mylink="aarch64.functions.rcw.RCW64_PROTECTED_BIT" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="RCW64_PROTECTED_BIT" hover="constant integer RCW64_PROTECTED_BIT = 52" conts="RCW64_PROTECTED_BIT">constant integer <anchor link="RCW64_PROTECTED_BIT" hover="constant integer RCW64_PROTECTED_BIT = 52">RCW64_PROTECTED_BIT</anchor> = 52;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/rcw/RCWCheck" mylink="aarch64.functions.rcw.RCWCheck" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// RCWCheck()</line>
<line>// ==========</line>
<line>// Returns nzcv based on : if the new value for RCW/RCWS instructions satisfy RCW and/or RCWS checks</line>
<line>// Z is set to 1 if RCW checks fail</line>
<line>// C is set to 0 if RCWS checks fail</line>
<line></line>
<line link="impl-aarch64.RCWCheck.3" hover="function: bits(4) RCWCheck(bits(N) old, bits(N) new, boolean soft)" conts="RCWCheck">bits(4) <anchor link="impl-aarch64.RCWCheck.3" hover="function: bits(4) RCWCheck(bits(N) old, bits(N) new, boolean soft)">RCWCheck</anchor>(bits(N) old, bits(N) new, boolean soft)</line>
<line>    assert N IN {64,128};</line>
<line>    integer protectedbit = if N == 128 then <a link="RCW128_PROTECTED_BIT" file="shared_pseudocode.xml" hover="constant integer RCW128_PROTECTED_BIT = 114">RCW128_PROTECTED_BIT</a> else <a link="RCW64_PROTECTED_BIT" file="shared_pseudocode.xml" hover="constant integer RCW64_PROTECTED_BIT = 52">RCW64_PROTECTED_BIT</a>;</line>
<line>    boolean rcw_fail = FALSE;</line>
<line>    boolean rcws_fail = FALSE;</line>
<line>    boolean rcw_state_fail = FALSE;</line>
<line>    boolean rcws_state_fail = FALSE;</line>
<line>    boolean rcw_mask_fail = FALSE;</line>
<line>    boolean rcws_mask_fail = FALSE;</line>
<line></line>
<line>    //Effective RCWMask calculation</line>
<line>    bits(N) rcwmask = RCWMASK_EL1&lt;N-1:0&gt;;</line>
<line>    if N == 64 then</line>
<line>        rcwmask&lt;49:18&gt; = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(rcwmask&lt;17&gt;,32);</line>
<line>    else</line>
<line>        rcwmask&lt;55:17&gt; = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(rcwmask&lt;16&gt;,39);</line>
<line>        rcwmask&lt;126:125,120:119,108:101,90:56,1&gt; = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(48);</line>
<line></line>
<line>    //Effective RCWSMask calculation</line>
<line>    bits(N) rcwsoftmask = RCWSMASK_EL1&lt;N-1:0&gt;;</line>
<line>    if N == 64 then</line>
<line>        rcwsoftmask&lt;49:18&gt; = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(rcwsoftmask&lt;17&gt;,32);</line>
<line>        if(<a link="impl-aarch64.ProtectionEnabled.1" file="shared_pseudocode.xml" hover="function: boolean ProtectionEnabled(bits(2) el)">ProtectionEnabled</a>(PSTATE.EL)) then</line>
<line>            rcwsoftmask&lt;52&gt; = '0';</line>
<line>    else</line>
<line>        rcwsoftmask&lt;55:17&gt; = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(rcwsoftmask&lt;16&gt;,39);</line>
<line>        rcwsoftmask&lt;126:125,120:119,108:101,90:56,1&gt; = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(48);</line>
<line>        rcwsoftmask&lt;114&gt; = '0';</line>
<line></line>
<line>    //RCW Checks</line>
<line>    //State Check</line>
<line>    if (<a link="impl-aarch64.ProtectionEnabled.1" file="shared_pseudocode.xml" hover="function: boolean ProtectionEnabled(bits(2) el)">ProtectionEnabled</a>(PSTATE.EL)) then</line>
<line>        if old&lt;protectedbit&gt; == '1' then</line>
<line>            rcw_state_fail = new&lt;protectedbit,0&gt; != old&lt;protectedbit,0&gt;;</line>
<line>        elsif old&lt;protectedbit&gt; == '0' then</line>
<line>            rcw_state_fail = new&lt;protectedbit&gt; != old&lt;protectedbit&gt;;</line>
<line></line>
<line>    //Mask Check</line>
<line>    if (<a link="impl-aarch64.ProtectionEnabled.1" file="shared_pseudocode.xml" hover="function: boolean ProtectionEnabled(bits(2) el)">ProtectionEnabled</a>(PSTATE.EL)) then</line>
<line>        if old&lt;protectedbit,0&gt; == '11' then</line>
<line>            rcw_mask_fail = !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>((new EOR old) AND NOT(rcwmask));</line>
<line></line>
<line>    //RCWS Checks</line>
<line>    if soft then</line>
<line>        //State Check</line>
<line>        if old&lt;0&gt; == '1' then</line>
<line>            rcws_state_fail = new&lt;0&gt; != old&lt;0&gt;;</line>
<line>        elsif (!<a link="impl-aarch64.ProtectionEnabled.1" file="shared_pseudocode.xml" hover="function: boolean ProtectionEnabled(bits(2) el)">ProtectionEnabled</a>(PSTATE.EL) ||</line>
<line>              (<a link="impl-aarch64.ProtectionEnabled.1" file="shared_pseudocode.xml" hover="function: boolean ProtectionEnabled(bits(2) el)">ProtectionEnabled</a>(PSTATE.EL) &amp;&amp; old&lt;protectedbit&gt; == '0')) then</line>
<line>            rcws_state_fail = new&lt;0&gt; != old&lt;0&gt; ;</line>
<line>        //Mask Check</line>
<line>        if old&lt;0&gt; == '1' then</line>
<line>            rcws_mask_fail = !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>((new EOR old) AND NOT(rcwsoftmask));</line>
<line></line>
<line>    rcw_fail = rcw_state_fail  || rcw_mask_fail ;</line>
<line>    rcws_fail = rcws_state_fail || rcws_mask_fail;</line>
<line></line>
<line>    bit n = '0';</line>
<line>    bit z = if rcw_fail then '1' else '0';</line>
<line>    bit c = if rcws_fail then '0' else '1';</line>
<line>    bit v = '0';</line>
<line>    return &lt;n, z, c, v&gt;;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/AArch64.MaybeZeroRegisterUppers" mylink="aarch64.functions.registers.AArch64.MaybeZeroRegisterUppers" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.MaybeZeroRegisterUppers()</line>
<line>// =================================</line>
<line>// On taking an exception to  AArch64 from AArch32, it is CONSTRAINED UNPREDICTABLE whether the top</line>
<line>// 32 bits of registers visible at any lower Exception level using AArch32 are set to zero.</line>
<line></line>
<line link="AArch64.MaybeZeroRegisterUppers.0" hover="function: AArch64.MaybeZeroRegisterUppers()" conts="AArch64.MaybeZeroRegisterUppers"><anchor link="AArch64.MaybeZeroRegisterUppers.0" hover="function: AArch64.MaybeZeroRegisterUppers()">AArch64.MaybeZeroRegisterUppers</anchor>()</line>
<line>    assert <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>();         // Always called from AArch32 state before entering AArch64 state</line>
<line></line>
<line>    integer first;</line>
<line>    integer last;</line>
<line>    boolean include_R15;</line>
<line>    if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>        first = 0;  last = 14;  include_R15 = FALSE;</line>
<line>    elsif PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>        first = 0;  last = 30;  include_R15 = FALSE;</line>
<line>    else</line>
<line>        first = 0;  last = 30;  include_R15 = TRUE;</line>
<line></line>
<line>    for n = first to last</line>
<line>        if (n != 15 || include_R15) &amp;&amp; <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_ZEROUPPER" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_ZEROUPPER</a>) then</line>
<line>            _R[n]&lt;63:32&gt; = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32);</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/AArch64.ResetGeneralRegisters" mylink="aarch64.functions.registers.AArch64.ResetGeneralRegisters" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ResetGeneralRegisters()</line>
<line>// ===============================</line>
<line></line>
<line link="AArch64.ResetGeneralRegisters.0" hover="function: AArch64.ResetGeneralRegisters()" conts="AArch64.ResetGeneralRegisters"><anchor link="AArch64.ResetGeneralRegisters.0" hover="function: AArch64.ResetGeneralRegisters()">AArch64.ResetGeneralRegisters</anchor>()</line>
<line></line>
<line>    for i = 0 to 30</line>
<line>        <a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[i, 64] = bits(64) UNKNOWN;</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/AArch64.ResetSIMDFPRegisters" mylink="aarch64.functions.registers.AArch64.ResetSIMDFPRegisters" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ResetSIMDFPRegisters()</line>
<line>// ==============================</line>
<line></line>
<line link="AArch64.ResetSIMDFPRegisters.0" hover="function: AArch64.ResetSIMDFPRegisters()" conts="AArch64.ResetSIMDFPRegisters"><anchor link="AArch64.ResetSIMDFPRegisters.0" hover="function: AArch64.ResetSIMDFPRegisters()">AArch64.ResetSIMDFPRegisters</anchor>()</line>
<line></line>
<line>    for i = 0 to 31</line>
<line>        <a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[i, 128] = bits(128) UNKNOWN;</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/AArch64.ResetSpecialRegisters" mylink="aarch64.functions.registers.AArch64.ResetSpecialRegisters" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ResetSpecialRegisters()</line>
<line>// ===============================</line>
<line></line>
<line link="AArch64.ResetSpecialRegisters.0" hover="function: AArch64.ResetSpecialRegisters()" conts="AArch64.ResetSpecialRegisters"><anchor link="AArch64.ResetSpecialRegisters.0" hover="function: AArch64.ResetSpecialRegisters()">AArch64.ResetSpecialRegisters</anchor>()</line>
<line></line>
<line>    // AArch64 special registers</line>
<line>    SP_EL0 = bits(64) UNKNOWN;</line>
<line>    SP_EL1 = bits(64) UNKNOWN;</line>
<line>    SPSR_EL1 = bits(64) UNKNOWN;</line>
<line>    ELR_EL1  = bits(64) UNKNOWN;</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>        SP_EL2 = bits(64) UNKNOWN;</line>
<line>        SPSR_EL2 = bits(64) UNKNOWN;</line>
<line>        ELR_EL2  = bits(64) UNKNOWN;</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        SP_EL3 = bits(64) UNKNOWN;</line>
<line>        SPSR_EL3 = bits(64) UNKNOWN;</line>
<line>        ELR_EL3  = bits(64) UNKNOWN;</line>
<line></line>
<line>    // AArch32 special registers that are not architecturally mapped to AArch64 registers</line>
<line>    if <a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>        SPSR_fiq&lt;31:0&gt; = bits(32) UNKNOWN;</line>
<line>        SPSR_irq&lt;31:0&gt; = bits(32) UNKNOWN;</line>
<line>        SPSR_abt&lt;31:0&gt; = bits(32) UNKNOWN;</line>
<line>        SPSR_und&lt;31:0&gt; = bits(32) UNKNOWN;</line>
<line></line>
<line>    // External debug special registers</line>
<line>    DLR_EL0 = bits(64) UNKNOWN;</line>
<line>    DSPSR_EL0 = bits(64) UNKNOWN;</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/AArch64.ResetSystemRegisters" mylink="aarch64.functions.registers.AArch64.ResetSystemRegisters" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ResetSystemRegisters()</line>
<line>// ==============================</line>
<line></line>
<line link="AArch64.ResetSystemRegisters.1" hover="function: AArch64.ResetSystemRegisters(boolean cold_reset)" conts="AArch64.ResetSystemRegisters"><anchor link="AArch64.ResetSystemRegisters.1" hover="function: AArch64.ResetSystemRegisters(boolean cold_reset)">AArch64.ResetSystemRegisters</anchor>(boolean cold_reset);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/PC" mylink="aarch64.functions.registers.PC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PC - non-assignment form</line>
<line>// ========================</line>
<line>// Read program counter.</line>
<line></line>
<line link="impl-aarch64.PC.read.0" hover="accessor: bits(64) PC[]" conts="PC">bits(64) <anchor link="impl-aarch64.PC.read.0" hover="accessor: bits(64) PC[]">PC</anchor>[]</line>
<line>    return _PC;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/SP" mylink="aarch64.functions.registers.SP" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SP[] - assignment form</line>
<line>// ======================</line>
<line>// Write to stack pointer from a 64-bit value.</line>
<line></line>
<line link="impl-aarch64.SP.write.0" hover="accessor: SP[] = bits(64) value" conts="SP"><anchor link="impl-aarch64.SP.write.0" hover="accessor: SP[] = bits(64) value">SP</anchor>[] = bits(64) value</line>
<line>    if PSTATE.SP == '0' then</line>
<line>        SP_EL0 = value;</line>
<line>    else</line>
<line>        case PSTATE.EL of</line>
<line>            when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>  SP_EL0 = value;</line>
<line>            when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>  SP_EL1 = value;</line>
<line>            when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>  SP_EL2 = value;</line>
<line>            when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>  SP_EL3 = value;</line>
<line>    return;</line>
<line></line>
<line>// SP[] - non-assignment form</line>
<line>// ==========================</line>
<line>// Read stack pointer with slice of 64 bits.</line>
<line></line>
<line link="impl-aarch64.SP.read.0" hover="accessor: bits(64) SP[]" conts="SP">bits(64) <anchor link="impl-aarch64.SP.read.0" hover="accessor: bits(64) SP[]">SP</anchor>[]</line>
<line>    if PSTATE.SP == '0' then</line>
<line>        return SP_EL0;</line>
<line>    else</line>
<line>        case PSTATE.EL of</line>
<line>            when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>  return SP_EL0;</line>
<line>            when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>  return SP_EL1;</line>
<line>            when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>  return SP_EL2;</line>
<line>            when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>  return SP_EL3;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/SPMCFGR_EL1" mylink="aarch64.functions.registers.SPMCFGR_EL1" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPMCFGR_EL1[] - non-assignment form</line>
<line>// =====================================</line>
<line>// Read the current configuration of System Performance monitor for</line>
<line>// System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMCFGR_EL1.read.1" hover="accessor: bits(64) SPMCFGR_EL1[integer s]" conts="SPMCFGR_EL1">bits(64) <anchor link="impl-aarch64.SPMCFGR_EL1.read.1" hover="accessor: bits(64) SPMCFGR_EL1[integer s]">SPMCFGR_EL1</anchor>[integer s];</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/SPMCGCR_EL1" mylink="aarch64.functions.registers.SPMCGCR_EL1" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPMCGCR_EL1[] - non-assignment form</line>
<line>// =====================================</line>
<line>// Read the counter group configuration of System Performance monitor</line>
<line>// 's'.</line>
<line></line>
<line link="impl-aarch64.SPMCGCR_EL1.read.1" hover="accessor: bits(64) SPMCGCR_EL1[integer s]" conts="SPMCGCR_EL1">bits(64) <anchor link="impl-aarch64.SPMCGCR_EL1.read.1" hover="accessor: bits(64) SPMCGCR_EL1[integer s]">SPMCGCR_EL1</anchor>[integer s];</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/SPMCNTENCLR_EL0" mylink="aarch64.functions.registers.SPMCNTENCLR_EL0" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPMCNTENCLR_EL0[] - non-assignment form</line>
<line>// =======================================</line>
<line>// Read the current mapping of disabled event counters for an 's'.</line>
<line></line>
<line link="impl-aarch64.SPMCNTENCLR_EL0.read.1" hover="accessor: bits(64) SPMCNTENCLR_EL0[integer s]" conts="SPMCNTENCLR_EL0">bits(64) <anchor link="impl-aarch64.SPMCNTENCLR_EL0.read.1" hover="accessor: bits(64) SPMCNTENCLR_EL0[integer s]">SPMCNTENCLR_EL0</anchor>[integer s];</line>
<line></line>
<line>// SPMCNTENCLR_EL0[] - assignment form</line>
<line>// ===================================</line>
<line>// Disable event counters for System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMCNTENCLR_EL0.write.1" hover="accessor: SPMCNTENCLR_EL0[integer s] = bits(64) value" conts="SPMCNTENCLR_EL0"><anchor link="impl-aarch64.SPMCNTENCLR_EL0.write.1" hover="accessor: SPMCNTENCLR_EL0[integer s] = bits(64) value">SPMCNTENCLR_EL0</anchor>[integer s] = bits(64) value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/SPMCNTENSET_EL0" mylink="aarch64.functions.registers.SPMCNTENSET_EL0" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPMCNTENSET_EL0[] - non-assignment form</line>
<line>// =======================================</line>
<line>// Read the current mapping for enabled event counters of System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMCNTENSET_EL0.read.1" hover="accessor: bits(64) SPMCNTENSET_EL0[integer s]" conts="SPMCNTENSET_EL0">bits(64) <anchor link="impl-aarch64.SPMCNTENSET_EL0.read.1" hover="accessor: bits(64) SPMCNTENSET_EL0[integer s]">SPMCNTENSET_EL0</anchor>[integer s];</line>
<line></line>
<line>// SPMCNTENSET_EL0[] - assignment form</line>
<line>// ===================================</line>
<line>// Enable event counters of System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMCNTENSET_EL0.write.1" hover="accessor: SPMCNTENSET_EL0[integer s] = bits(64) value" conts="SPMCNTENSET_EL0"><anchor link="impl-aarch64.SPMCNTENSET_EL0.write.1" hover="accessor: SPMCNTENSET_EL0[integer s] = bits(64) value">SPMCNTENSET_EL0</anchor>[integer s] = bits(64) value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/SPMCR_EL0" mylink="aarch64.functions.registers.SPMCR_EL0" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPMCR_EL0[] - non-assignment form</line>
<line>// ==================================</line>
<line>// Read the control register for System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMCR_EL0.read.1" hover="accessor: bits(64) SPMCR_EL0[integer s]" conts="SPMCR_EL0">bits(64) <anchor link="impl-aarch64.SPMCR_EL0.read.1" hover="accessor: bits(64) SPMCR_EL0[integer s]">SPMCR_EL0</anchor>[integer s];</line>
<line></line>
<line>// SPMCR_EL0[] - assignment form</line>
<line>// =============================</line>
<line>// Write to the control register for System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMCR_EL0.write.1" hover="accessor: SPMCR_EL0[integer s] = bits(64) value" conts="SPMCR_EL0"><anchor link="impl-aarch64.SPMCR_EL0.write.1" hover="accessor: SPMCR_EL0[integer s] = bits(64) value">SPMCR_EL0</anchor>[integer s] = bits(64) value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/SPMDEVAFF_EL1" mylink="aarch64.functions.registers.SPMDEVAFF_EL1" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPMDEVAFF_EL1[] - non-assignment form</line>
<line>// =====================================</line>
<line>// Read the discovery information for System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMDEVAFF_EL1.read.1" hover="accessor: bits(64) SPMDEVAFF_EL1[integer s]" conts="SPMDEVAFF_EL1">bits(64) <anchor link="impl-aarch64.SPMDEVAFF_EL1.read.1" hover="accessor: bits(64) SPMDEVAFF_EL1[integer s]">SPMDEVAFF_EL1</anchor>[integer s];</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/SPMDEVARCH_EL1" mylink="aarch64.functions.registers.SPMDEVARCH_EL1" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPMDEVARCH_EL1[] - non-assignment form</line>
<line>// ======================================</line>
<line>// Read the discovery information for System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMDEVARCH_EL1.read.1" hover="accessor: bits(64) SPMDEVARCH_EL1[integer s]" conts="SPMDEVARCH_EL1">bits(64) <anchor link="impl-aarch64.SPMDEVARCH_EL1.read.1" hover="accessor: bits(64) SPMDEVARCH_EL1[integer s]">SPMDEVARCH_EL1</anchor>[integer s];</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/SPMEVCNTR_EL0" mylink="aarch64.functions.registers.SPMEVCNTR_EL0" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPMEVCNTR_EL0[] - non-assignment form</line>
<line>// =====================================</line>
<line>// Read a System PMU Event Counter register for counter 'n' of a given</line>
<line>// System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMEVCNTR_EL0.read.2" hover="accessor: bits(64) SPMEVCNTR_EL0[integer s, integer n]" conts="SPMEVCNTR_EL0">bits(64) <anchor link="impl-aarch64.SPMEVCNTR_EL0.read.2" hover="accessor: bits(64) SPMEVCNTR_EL0[integer s, integer n]">SPMEVCNTR_EL0</anchor>[integer s, integer n];</line>
<line></line>
<line>// SPMEVCNTR_EL0[] - assignment form</line>
<line>// =================================</line>
<line>// Write to a System PMU Event Counter register for counter 'n' of a given</line>
<line>// System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMEVCNTR_EL0.write.2" hover="accessor: SPMEVCNTR_EL0[integer s, integer n] = bits(64) value" conts="SPMEVCNTR_EL0"><anchor link="impl-aarch64.SPMEVCNTR_EL0.write.2" hover="accessor: SPMEVCNTR_EL0[integer s, integer n] = bits(64) value">SPMEVCNTR_EL0</anchor>[integer s, integer n] = bits(64) value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/SPMEVFILT2R_EL0" mylink="aarch64.functions.registers.SPMEVFILT2R_EL0" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPMEVFILT2R_EL0[] - non-assignment form</line>
<line>// =======================================</line>
<line>// Read the additional event selection controls for</line>
<line>// counter 'n' of a given System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMEVFILT2R_EL0.read.2" hover="accessor: bits(64) SPMEVFILT2R_EL0[integer s, integer n]" conts="SPMEVFILT2R_EL0">bits(64) <anchor link="impl-aarch64.SPMEVFILT2R_EL0.read.2" hover="accessor: bits(64) SPMEVFILT2R_EL0[integer s, integer n]">SPMEVFILT2R_EL0</anchor>[integer s, integer n];</line>
<line></line>
<line>// SPMEVFILT2R_EL0[] - assignment form</line>
<line>// ===================================</line>
<line>// Configure the additional event selection controls for</line>
<line>// counter 'n' of a given System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMEVFILT2R_EL0.write.2" hover="accessor: SPMEVFILT2R_EL0[integer s, integer n] = bits(64) value" conts="SPMEVFILT2R_EL0"><anchor link="impl-aarch64.SPMEVFILT2R_EL0.write.2" hover="accessor: SPMEVFILT2R_EL0[integer s, integer n] = bits(64) value">SPMEVFILT2R_EL0</anchor>[integer s, integer n] = bits(64) value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/SPMEVFILTR_EL0" mylink="aarch64.functions.registers.SPMEVFILTR_EL0" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPMEVFILTR_EL0[] - non-assignment form</line>
<line>// ======================================</line>
<line>// Read the additional event selection controls for</line>
<line>// counter 'n' of a given System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMEVFILTR_EL0.read.2" hover="accessor: bits(64) SPMEVFILTR_EL0[integer s, integer n]" conts="SPMEVFILTR_EL0">bits(64) <anchor link="impl-aarch64.SPMEVFILTR_EL0.read.2" hover="accessor: bits(64) SPMEVFILTR_EL0[integer s, integer n]">SPMEVFILTR_EL0</anchor>[integer s, integer n];</line>
<line></line>
<line>// SPMEVFILTR_EL0[] - assignment form</line>
<line>// ==================================</line>
<line>// Configure the additional event selection controls for</line>
<line>// counter 'n' of a given System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMEVFILTR_EL0.write.2" hover="accessor: SPMEVFILTR_EL0[integer s, integer n] = bits(64) value" conts="SPMEVFILTR_EL0"><anchor link="impl-aarch64.SPMEVFILTR_EL0.write.2" hover="accessor: SPMEVFILTR_EL0[integer s, integer n] = bits(64) value">SPMEVFILTR_EL0</anchor>[integer s, integer n] = bits(64) value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/SPMEVTYPER_EL0" mylink="aarch64.functions.registers.SPMEVTYPER_EL0" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPMEVTYPER_EL0[] - non-assignment form</line>
<line>// ======================================</line>
<line>// Read the current mapping of event with event counter SPMEVCNTR_EL0</line>
<line>// for counter 'n' of a given System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMEVTYPER_EL0.read.2" hover="accessor: bits(64) SPMEVTYPER_EL0[integer s, integer n]" conts="SPMEVTYPER_EL0">bits(64) <anchor link="impl-aarch64.SPMEVTYPER_EL0.read.2" hover="accessor: bits(64) SPMEVTYPER_EL0[integer s, integer n]">SPMEVTYPER_EL0</anchor>[integer s, integer n];</line>
<line></line>
<line>// SPMEVTYPER_EL0[] - assignment form</line>
<line>// ==================================</line>
<line>// Configure which event increments the event counter SPMEVCNTR_EL0, for</line>
<line>// counter 'n' of a given System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMEVTYPER_EL0.write.2" hover="accessor: SPMEVTYPER_EL0[integer s, integer n] = bits(64) value" conts="SPMEVTYPER_EL0"><anchor link="impl-aarch64.SPMEVTYPER_EL0.write.2" hover="accessor: SPMEVTYPER_EL0[integer s, integer n] = bits(64) value">SPMEVTYPER_EL0</anchor>[integer s, integer n] = bits(64) value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/SPMIIDR_EL1" mylink="aarch64.functions.registers.SPMIIDR_EL1" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPMIIDR_EL1[] - non-assignment form</line>
<line>// ===================================</line>
<line>// Read the discovery information for System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMIIDR_EL1.read.1" hover="accessor: bits(64) SPMIIDR_EL1[integer s]" conts="SPMIIDR_EL1">bits(64) <anchor link="impl-aarch64.SPMIIDR_EL1.read.1" hover="accessor: bits(64) SPMIIDR_EL1[integer s]">SPMIIDR_EL1</anchor>[integer s];</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/SPMINTENCLR_EL1" mylink="aarch64.functions.registers.SPMINTENCLR_EL1" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPMINTENCLR_EL1[] - non-assignment form</line>
<line>// =======================================</line>
<line>// Read the masking information for interrupt requests on overflows of</line>
<line>// implemented counters of System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMINTENCLR_EL1.read.1" hover="accessor: bits(64) SPMINTENCLR_EL1[integer s]" conts="SPMINTENCLR_EL1">bits(64) <anchor link="impl-aarch64.SPMINTENCLR_EL1.read.1" hover="accessor: bits(64) SPMINTENCLR_EL1[integer s]">SPMINTENCLR_EL1</anchor>[integer s];</line>
<line></line>
<line>// SPMINTENCLR_EL1[] - assignment form</line>
<line>// ===================================</line>
<line>// Disable the generation of interrupt requests on overflows of</line>
<line>// implemented counters of System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMINTENCLR_EL1.write.1" hover="accessor: SPMINTENCLR_EL1[integer s] = bits(64) value" conts="SPMINTENCLR_EL1"><anchor link="impl-aarch64.SPMINTENCLR_EL1.write.1" hover="accessor: SPMINTENCLR_EL1[integer s] = bits(64) value">SPMINTENCLR_EL1</anchor>[integer s] = bits(64) value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/SPMINTENSET_EL1" mylink="aarch64.functions.registers.SPMINTENSET_EL1" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPMINTENSET_EL1[] - non-assignment form</line>
<line>// =======================================</line>
<line>// Read the masking information for interrupt requests on overflows of</line>
<line>// implemented counters of System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMINTENSET_EL1.read.1" hover="accessor: bits(64) SPMINTENSET_EL1[integer s]" conts="SPMINTENSET_EL1">bits(64) <anchor link="impl-aarch64.SPMINTENSET_EL1.read.1" hover="accessor: bits(64) SPMINTENSET_EL1[integer s]">SPMINTENSET_EL1</anchor>[integer s];</line>
<line></line>
<line>// SPMINTENSET_EL1[] - assignment form</line>
<line>// ===================================</line>
<line>// Disable the generation of interrupt requests on overflows of</line>
<line>// implemented counters for System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMINTENSET_EL1.write.1" hover="accessor: SPMINTENSET_EL1[integer s] = bits(64) value" conts="SPMINTENSET_EL1"><anchor link="impl-aarch64.SPMINTENSET_EL1.write.1" hover="accessor: SPMINTENSET_EL1[integer s] = bits(64) value">SPMINTENSET_EL1</anchor>[integer s] = bits(64) value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/SPMOVSCLR_EL0" mylink="aarch64.functions.registers.SPMOVSCLR_EL0" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPMOVSCLR_EL0[] - non-assignment form</line>
<line>// =====================================</line>
<line>// Read the overflow bit clear status of implemented counters for System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMOVSCLR_EL0.read.1" hover="accessor: bits(64) SPMOVSCLR_EL0[integer s]" conts="SPMOVSCLR_EL0">bits(64) <anchor link="impl-aarch64.SPMOVSCLR_EL0.read.1" hover="accessor: bits(64) SPMOVSCLR_EL0[integer s]">SPMOVSCLR_EL0</anchor>[integer s];</line>
<line></line>
<line>// SPMOVSCLR_EL0[] - assignment form</line>
<line>// =================================</line>
<line>// Clear the overflow bit clear status of implemented counters for</line>
<line>// System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMOVSCLR_EL0.write.1" hover="accessor: SPMOVSCLR_EL0[integer s] = bits(64) value" conts="SPMOVSCLR_EL0"><anchor link="impl-aarch64.SPMOVSCLR_EL0.write.1" hover="accessor: SPMOVSCLR_EL0[integer s] = bits(64) value">SPMOVSCLR_EL0</anchor>[integer s] = bits(64) value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/SPMOVSSET_EL0" mylink="aarch64.functions.registers.SPMOVSSET_EL0" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPMOVSSET_EL0[] - non-assignment form</line>
<line>// =====================================</line>
<line>// Read state of the overflow bit for the implemented event counters</line>
<line>// of System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMOVSSET_EL0.read.1" hover="accessor: bits(64) SPMOVSSET_EL0[integer s]" conts="SPMOVSSET_EL0">bits(64) <anchor link="impl-aarch64.SPMOVSSET_EL0.read.1" hover="accessor: bits(64) SPMOVSSET_EL0[integer s]">SPMOVSSET_EL0</anchor>[integer s];</line>
<line></line>
<line>// SPMOVSSET_EL0[] - assignment form</line>
<line>// =================================</line>
<line>// Sets the state of the overflow bit for the implemented event counters</line>
<line>// of System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMOVSSET_EL0.write.1" hover="accessor: SPMOVSSET_EL0[integer s] = bits(64) value" conts="SPMOVSSET_EL0"><anchor link="impl-aarch64.SPMOVSSET_EL0.write.1" hover="accessor: SPMOVSSET_EL0[integer s] = bits(64) value">SPMOVSSET_EL0</anchor>[integer s] = bits(64) value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/SPMROOTCR_EL3" mylink="aarch64.functions.registers.SPMROOTCR_EL3" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPMROOTCR_EL3[] - non-assignment form</line>
<line>// =====================================</line>
<line>// Read the observability of Root and Realm events by System Performance</line>
<line>// Monitor for System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMROOTCR_EL3.read.1" hover="accessor: bits(64) SPMROOTCR_EL3[integer s]" conts="SPMROOTCR_EL3">bits(64) <anchor link="impl-aarch64.SPMROOTCR_EL3.read.1" hover="accessor: bits(64) SPMROOTCR_EL3[integer s]">SPMROOTCR_EL3</anchor>[integer s];</line>
<line></line>
<line>// SPMROOTCR_EL3[] - assignment form</line>
<line>// =================================</line>
<line>// Configure the observability of Root and Realm events by System</line>
<line>// Performance Monitor for System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMROOTCR_EL3.write.1" hover="accessor: SPMROOTCR_EL3[integer s] = bits(64) value" conts="SPMROOTCR_EL3"><anchor link="impl-aarch64.SPMROOTCR_EL3.write.1" hover="accessor: SPMROOTCR_EL3[integer s] = bits(64) value">SPMROOTCR_EL3</anchor>[integer s] = bits(64) value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/SPMSCR_EL1" mylink="aarch64.functions.registers.SPMSCR_EL1" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPMSCR_EL1[] - non-assignment form</line>
<line>// ===================================</line>
<line>// Read the observability of Secure events by System Performance Monitor</line>
<line>// for System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMSCR_EL1.read.1" hover="accessor: bits(64) SPMSCR_EL1[integer s]" conts="SPMSCR_EL1">bits(64) <anchor link="impl-aarch64.SPMSCR_EL1.read.1" hover="accessor: bits(64) SPMSCR_EL1[integer s]">SPMSCR_EL1</anchor>[integer s];</line>
<line></line>
<line>// SPMSCR_EL1[] - assignment form</line>
<line>// ==============================</line>
<line>// Configure the observability of secure events by System Performance</line>
<line>// Monitor for System PMU 's'.</line>
<line></line>
<line link="impl-aarch64.SPMSCR_EL1.write.1" hover="accessor: SPMSCR_EL1[integer s] = bits(64) value" conts="SPMSCR_EL1"><anchor link="impl-aarch64.SPMSCR_EL1.write.1" hover="accessor: SPMSCR_EL1[integer s] = bits(64) value">SPMSCR_EL1</anchor>[integer s] = bits(64) value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/V" mylink="aarch64.functions.registers.V" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// V[] - assignment form</line>
<line>// =====================</line>
<line>// Write to SIMD&amp;FP register with implicit extension from</line>
<line>// 8, 16, 32, 64 or 128 bits.</line>
<line></line>
<line link="impl-aarch64.V.write.2" hover="accessor: V[integer n, integer width] = bits(width) value" conts="V"><anchor link="impl-aarch64.V.write.2" hover="accessor: V[integer n, integer width] = bits(width) value">V</anchor>[integer n, integer width] = bits(width) value</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt;= 31;</line>
<line>    assert width IN {8,16,32,64,128};</line>
<line>    integer vlen = if <a link="impl-aarch64.IsSVEEnabled.1" file="shared_pseudocode.xml" hover="function: boolean IsSVEEnabled(bits(2) el)">IsSVEEnabled</a>(PSTATE.EL) then <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a> else 128;</line>
<line>    if <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_SVEZEROUPPER" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_SVEZEROUPPER</a>) then</line>
<line>        _Z[n] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(value, <a link="MAX_VL" file="shared_pseudocode.xml" hover="constant integer MAX_VL = 2048">MAX_VL</a>);</line>
<line>    else</line>
<line>        _Z[n]&lt;vlen-1:0&gt; = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(value, vlen);</line>
<line></line>
<line>// V[] - non-assignment form</line>
<line>// =========================</line>
<line>// Read from SIMD&amp;FP register with implicit slice of 8, 16</line>
<line>// 32, 64 or 128 bits.</line>
<line></line>
<line link="impl-aarch64.V.read.2" hover="accessor: bits(width) V[integer n, integer width]" conts="V">bits(width) <anchor link="impl-aarch64.V.read.2" hover="accessor: bits(width) V[integer n, integer width]">V</anchor>[integer n, integer width]</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt;= 31;</line>
<line>    assert width IN {8,16,32,64,128};</line>
<line>    return _Z[n]&lt;width-1:0&gt;;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/Vpart" mylink="aarch64.functions.registers.Vpart" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Vpart[] - non-assignment form</line>
<line>// =============================</line>
<line>// Reads a 128-bit SIMD&amp;FP register in up to two parts:</line>
<line>//  part 0 returns the bottom 8, 16, 32 or 64 bits of a value held in the register;</line>
<line>//  part 1 returns the top half of the bottom 64 bits or the top half of the 128-bit</line>
<line>//  value held in the register.</line>
<line></line>
<line link="impl-aarch64.Vpart.read.3" hover="accessor: bits(width) Vpart[integer n, integer part, integer width]" conts="Vpart">bits(width) <anchor link="impl-aarch64.Vpart.read.3" hover="accessor: bits(width) Vpart[integer n, integer part, integer width]">Vpart</anchor>[integer n, integer part, integer width]</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt;= 31;</line>
<line>    assert part IN {0, 1};</line>
<line>    if part == 0 then</line>
<line>        assert width &lt; 128;</line>
<line>        return <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, width];</line>
<line>    else</line>
<line>        assert width IN {32,64};</line>
<line>        bits(128) vreg = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, 128];</line>
<line>        return vreg&lt;(width * 2)-1:width&gt;;</line>
<line></line>
<line>// Vpart[] - assignment form</line>
<line>// =========================</line>
<line>// Writes a 128-bit SIMD&amp;FP register in up to two parts:</line>
<line>//  part 0 zero extends a 8, 16, 32, or 64-bit value to fill the whole register;</line>
<line>//  part 1 inserts a 64-bit value into the top half of the register.</line>
<line></line>
<line link="impl-aarch64.Vpart.write.3" hover="accessor: Vpart[integer n, integer part, integer width] = bits(width) value" conts="Vpart"><anchor link="impl-aarch64.Vpart.write.3" hover="accessor: Vpart[integer n, integer part, integer width] = bits(width) value">Vpart</anchor>[integer n, integer part, integer width] = bits(width) value</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt;= 31;</line>
<line>    assert part IN {0, 1};</line>
<line>    if part == 0 then</line>
<line>        assert width &lt; 128;</line>
<line>        <a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[n, width] = value;</line>
<line>    else</line>
<line>        assert width == 64;</line>
<line>        bits(64) vreg = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, 64];</line>
<line>        <a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[n, 128] = value&lt;63:0&gt; : vreg;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/registers/X" mylink="aarch64.functions.registers.X" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// X[] - assignment form</line>
<line>// =====================</line>
<line>// Write to general-purpose register from either a 32-bit or a 64-bit value,</line>
<line>// where the size of the value is passed as an argument.</line>
<line></line>
<line link="impl-aarch64.X.write.2" hover="accessor: X[integer n, integer width] = bits(width) value" conts="X"><anchor link="impl-aarch64.X.write.2" hover="accessor: X[integer n, integer width] = bits(width) value">X</anchor>[integer n, integer width] = bits(width) value</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt;= 31;</line>
<line>    assert width IN {32,64};</line>
<line>    if n != 31 then</line>
<line>        _R[n] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(value, 64);</line>
<line>    return;</line>
<line></line>
<line>// X[] - non-assignment form</line>
<line>// =========================</line>
<line>// Read from general-purpose register with an explicit slice of 8, 16, 32 or 64 bits.</line>
<line></line>
<line link="impl-aarch64.X.read.2" hover="accessor: bits(width) X[integer n, integer width]" conts="X">bits(width) <anchor link="impl-aarch64.X.read.2" hover="accessor: bits(width) X[integer n, integer width]">X</anchor>[integer n, integer width]</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt;= 31;</line>
<line>    assert width IN {8,16,32,64};</line>
<line>    if n != 31 then</line>
<line>        return _R[n]&lt;width-1:0&gt;;</line>
<line>    else</line>
<line>        return <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(width);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sme/CounterToPredicate" mylink="aarch64.functions.sme.CounterToPredicate" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CounterToPredicate()</line>
<line>// ====================</line>
<line></line>
<line link="impl-aarch64.CounterToPredicate.2" hover="function: bits(width) CounterToPredicate(bits(16) pred, integer width)" conts="CounterToPredicate">bits(width) <anchor link="impl-aarch64.CounterToPredicate.2" hover="function: bits(width) CounterToPredicate(bits(16) pred, integer width)">CounterToPredicate</anchor>(bits(16) pred, integer width)</line>
<line>    integer count;</line>
<line>    integer esize;</line>
<line>    integer elements;</line>
<line>    constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;</line>
<line>    constant integer PL = VL DIV 8;</line>
<line>    integer maxbit = <a link="impl-shared.HighestSetBit.1" file="shared_pseudocode.xml" hover="function: integer HighestSetBit(bits(N) x)">HighestSetBit</a>(<a link="impl-aarch64.CeilPow2.1" file="shared_pseudocode.xml" hover="function: integer CeilPow2(integer x)">CeilPow2</a>(PL * 4)&lt;15:0&gt;);</line>
<line>    assert maxbit &lt;= 14;</line>
<line>    bits(PL*4) result;</line>
<line>    boolean invert = pred&lt;15&gt; == '1';</line>
<line></line>
<line>    assert width == PL || width == PL*2 || width == PL*3 || width == PL*4;</line>
<line></line>
<line>    if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(pred&lt;3:0&gt;) then</line>
<line>        return <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(width);</line>
<line></line>
<line>    case pred&lt;3:0&gt; of</line>
<line>        when 'xxx1'</line>
<line>            count = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(pred&lt;maxbit:1&gt;);</line>
<line>            esize = 8;</line>
<line>        when 'xx10'</line>
<line>            count = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(pred&lt;maxbit:2&gt;);</line>
<line>            esize = 16;</line>
<line>        when 'x100'</line>
<line>            count = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(pred&lt;maxbit:3&gt;);</line>
<line>            esize = 32;</line>
<line>        when '1000'</line>
<line>            count = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(pred&lt;maxbit:4&gt;);</line>
<line>            esize = 64;</line>
<line></line>
<line>    elements = (VL * 4) DIV esize;</line>
<line>    result = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(PL*4);</line>
<line>    constant integer psize = esize DIV 8;</line>
<line>    for e = 0 to elements-1</line>
<line>        bit pbit = if e &lt; count then '1' else '0';</line>
<line>        if invert then</line>
<line>            pbit = NOT(pbit);</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, psize] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(pbit, psize);</line>
<line></line>
<line>    return result&lt;width-1:0&gt;;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sme/EncodePredCount" mylink="aarch64.functions.sme.EncodePredCount" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EncodePredCount()</line>
<line>// =================</line>
<line></line>
<line link="impl-aarch64.EncodePredCount.5" hover="function: bits(width) EncodePredCount(integer esize, integer elements, integer count_in, boolean invert_in, integer width)" conts="EncodePredCount">bits(width) <anchor link="impl-aarch64.EncodePredCount.5" hover="function: bits(width) EncodePredCount(integer esize, integer elements, integer count_in, boolean invert_in, integer width)">EncodePredCount</anchor>(integer esize, integer elements,</line>
<line>                            integer count_in, boolean invert_in, integer width)</line>
<line>    integer count = count_in;</line>
<line>    boolean invert = invert_in;</line>
<line>    constant integer PL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a> DIV 8;</line>
<line>    assert width == PL;</line>
<line>    assert esize IN {8, 16, 32, 64};</line>
<line>    assert count &gt;=0 &amp;&amp; count &lt;= elements;</line>
<line>    bits(16) pred;</line>
<line></line>
<line>    if count == 0 then</line>
<line>        return <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(width);</line>
<line></line>
<line>    if invert then</line>
<line>        count = elements - count;</line>
<line>    elsif count == elements then</line>
<line>        count = 0;</line>
<line>        invert = TRUE;</line>
<line></line>
<line>    bit inv = (if invert then '1' else '0');</line>
<line>    case esize of</line>
<line>        when 8  pred = inv : count&lt;13:0&gt; :    '1';</line>
<line>        when 16 pred = inv : count&lt;12:0&gt; :   '10';</line>
<line>        when 32 pred = inv : count&lt;11:0&gt; :  '100';</line>
<line>        when 64 pred = inv : count&lt;10:0&gt; : '1000';</line>
<line></line>
<line>    return <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(pred, width);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sme/HaveSME" mylink="aarch64.functions.sme.HaveSME" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSME()</line>
<line>// =========</line>
<line>// Returns TRUE if the SME extension is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveSME.0" hover="function: boolean HaveSME()" conts="HaveSME">boolean <anchor link="impl-aarch64.HaveSME.0" hover="function: boolean HaveSME()">HaveSME</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SME);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sme/HaveSME2" mylink="aarch64.functions.sme.HaveSME2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSME2()</line>
<line>// ==========</line>
<line>// Returns TRUE if the SME2 extension is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveSME2.0" hover="function: boolean HaveSME2()" conts="HaveSME2">boolean <anchor link="impl-aarch64.HaveSME2.0" hover="function: boolean HaveSME2()">HaveSME2</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SME2);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sme/HaveSME2p1" mylink="aarch64.functions.sme.HaveSME2p1" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSME2p1()</line>
<line>// ============</line>
<line>// Returns TRUE if the SME2.1 extension is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveSME2p1.0" hover="function: boolean HaveSME2p1()" conts="HaveSME2p1">boolean <anchor link="impl-aarch64.HaveSME2p1.0" hover="function: boolean HaveSME2p1()">HaveSME2p1</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SME2p1);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sme/HaveSMEB16B16" mylink="aarch64.functions.sme.HaveSMEB16B16" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSMEB16B16()</line>
<line>// ===============</line>
<line>// Returns TRUE if the SME2.1 non-widening BFloat16 instructions are implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveSMEB16B16.0" hover="function: boolean HaveSMEB16B16()" conts="HaveSMEB16B16">boolean <anchor link="impl-aarch64.HaveSMEB16B16.0" hover="function: boolean HaveSMEB16B16()">HaveSMEB16B16</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_B16B16);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sme/HaveSMEF16F16" mylink="aarch64.functions.sme.HaveSMEF16F16" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSMEF16F16()</line>
<line>// ===============</line>
<line>// Returns TRUE if the SME2.1 half-precision instructions are implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveSMEF16F16.0" hover="function: boolean HaveSMEF16F16()" conts="HaveSMEF16F16">boolean <anchor link="impl-aarch64.HaveSMEF16F16.0" hover="function: boolean HaveSMEF16F16()">HaveSMEF16F16</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SME_F16F16);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sme/HaveSMEF64F64" mylink="aarch64.functions.sme.HaveSMEF64F64" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSMEF64F64()</line>
<line>// ===============</line>
<line>// Returns TRUE if the SMEF64F64 extension is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveSMEF64F64.0" hover="function: boolean HaveSMEF64F64()" conts="HaveSMEF64F64">boolean <anchor link="impl-aarch64.HaveSMEF64F64.0" hover="function: boolean HaveSMEF64F64()">HaveSMEF64F64</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SME_F64F64);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sme/HaveSMEI16I64" mylink="aarch64.functions.sme.HaveSMEI16I64" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSMEI16I64()</line>
<line>// ===============</line>
<line>// Returns TRUE if the SMEI16I64 extension is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveSMEI16I64.0" hover="function: boolean HaveSMEI16I64()" conts="HaveSMEI16I64">boolean <anchor link="impl-aarch64.HaveSMEI16I64.0" hover="function: boolean HaveSMEI16I64()">HaveSMEI16I64</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SME_I16I64);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sme/Lookup" mylink="aarch64.functions.sme.Lookup" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>bits(512) _ZT0;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sme/PredCountTest" mylink="aarch64.functions.sme.PredCountTest" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PredCountTest()</line>
<line>// ===============</line>
<line></line>
<line link="impl-aarch64.PredCountTest.3" hover="function: bits(4) PredCountTest(integer elements, integer count, boolean invert)" conts="PredCountTest">bits(4) <anchor link="impl-aarch64.PredCountTest.3" hover="function: bits(4) PredCountTest(integer elements, integer count, boolean invert)">PredCountTest</anchor>(integer elements, integer count, boolean invert)</line>
<line>    bit n, z, c, v;</line>
<line>    z = (if count == 0 then '1' else '0');              // none active</line>
<line>    if !invert then</line>
<line>        n = (if count != 0 then '1' else '0');          // first active</line>
<line>        c = (if count == elements then '0' else '1');   // NOT last active</line>
<line>    else</line>
<line>        n = (if count == elements then '1' else '0');   // first active</line>
<line>        c = (if count != 0 then '0' else '1');          // NOT last active</line>
<line>    v = '0';</line>
<line></line>
<line>    return n:z:c:v;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sme/System" mylink="aarch64.functions.sme.System" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// System Registers</line>
<line>// ================</line>
<line></line>
<line>array bits(<a link="MAX_VL" file="shared_pseudocode.xml" hover="constant integer MAX_VL = 2048">MAX_VL</a>) _ZA[0..255];</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sme/ZAhslice" mylink="aarch64.functions.sme.ZAhslice" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ZAhslice[] - non-assignment form</line>
<line>// ================================</line>
<line></line>
<line link="impl-aarch64.ZAhslice.read.4" hover="accessor: bits(width) ZAhslice[integer tile, integer esize, integer slice, integer width]" conts="ZAhslice">bits(width) <anchor link="impl-aarch64.ZAhslice.read.4" hover="accessor: bits(width) ZAhslice[integer tile, integer esize, integer slice, integer width]">ZAhslice</anchor>[integer tile, integer esize, integer slice, integer width]</line>
<line>    assert esize IN {8, 16, 32, 64, 128};</line>
<line>    integer tiles = esize DIV 8;</line>
<line>    assert tile &gt;= 0 &amp;&amp; tile &lt; tiles;</line>
<line>    integer slices = <a link="impl-aarch64.CurrentSVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentSVL">CurrentSVL</a> DIV esize;</line>
<line>    assert slice &gt;= 0 &amp;&amp; slice &lt; slices;</line>
<line></line>
<line>    return <a link="impl-aarch64.ZAvector.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) ZAvector[integer index, integer width]">ZAvector</a>[tile + slice * tiles, width];</line>
<line></line>
<line>// ZAhslice[] - assignment form</line>
<line>// ============================</line>
<line></line>
<line link="impl-aarch64.ZAhslice.write.4" hover="accessor: ZAhslice[integer tile, integer esize, integer slice, integer width] = bits(width) value" conts="ZAhslice"><anchor link="impl-aarch64.ZAhslice.write.4" hover="accessor: ZAhslice[integer tile, integer esize, integer slice, integer width] = bits(width) value">ZAhslice</anchor>[integer tile, integer esize, integer slice, integer width] = bits(width) value</line>
<line>    assert esize IN {8, 16, 32, 64, 128};</line>
<line>    integer tiles = esize DIV 8;</line>
<line>    assert tile &gt;= 0 &amp;&amp; tile &lt; tiles;</line>
<line>    integer slices = <a link="impl-aarch64.CurrentSVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentSVL">CurrentSVL</a> DIV esize;</line>
<line>    assert slice &gt;= 0 &amp;&amp; slice &lt; slices;</line>
<line></line>
<line>    <a link="impl-aarch64.ZAvector.write.2" file="shared_pseudocode.xml" hover="accessor: ZAvector[integer index, integer width] = bits(width) value">ZAvector</a>[tile + slice * tiles, width] = value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sme/ZAslice" mylink="aarch64.functions.sme.ZAslice" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ZAslice[] - non-assignment form</line>
<line>// ===============================</line>
<line></line>
<line link="impl-aarch64.ZAslice.read.5" hover="accessor: bits(width) ZAslice[integer tile, integer esize, boolean vertical, integer slice, integer width]" conts="ZAslice">bits(width) <anchor link="impl-aarch64.ZAslice.read.5" hover="accessor: bits(width) ZAslice[integer tile, integer esize, boolean vertical, integer slice, integer width]">ZAslice</anchor>[integer tile, integer esize, boolean vertical, integer slice, integer width]</line>
<line>    bits(width) result;</line>
<line></line>
<line>    if vertical then</line>
<line>        result = <a link="impl-aarch64.ZAvslice.read.4" file="shared_pseudocode.xml" hover="accessor: bits(width) ZAvslice[integer tile, integer esize, integer slice, integer width]">ZAvslice</a>[tile, esize, slice, width];</line>
<line>    else</line>
<line>        result = <a link="impl-aarch64.ZAhslice.read.4" file="shared_pseudocode.xml" hover="accessor: bits(width) ZAhslice[integer tile, integer esize, integer slice, integer width]">ZAhslice</a>[tile, esize, slice, width];</line>
<line></line>
<line>    return result;</line>
<line></line>
<line>// ZAslice[] - assignment form</line>
<line>// ===========================</line>
<line></line>
<line link="impl-aarch64.ZAslice.write.5" hover="accessor: ZAslice[integer tile, integer esize, boolean vertical, integer slice, integer width] = bits(width) value" conts="ZAslice"><anchor link="impl-aarch64.ZAslice.write.5" hover="accessor: ZAslice[integer tile, integer esize, boolean vertical, integer slice, integer width] = bits(width) value">ZAslice</anchor>[integer tile, integer esize, boolean vertical,</line>
<line>        integer slice, integer width] = bits(width) value</line>
<line>    if vertical then</line>
<line>        <a link="impl-aarch64.ZAvslice.write.4" file="shared_pseudocode.xml" hover="accessor: ZAvslice[integer tile, integer esize, integer slice, integer width] = bits(width) value">ZAvslice</a>[tile, esize, slice, width] = value;</line>
<line>    else</line>
<line>        <a link="impl-aarch64.ZAhslice.write.4" file="shared_pseudocode.xml" hover="accessor: ZAhslice[integer tile, integer esize, integer slice, integer width] = bits(width) value">ZAhslice</a>[tile, esize, slice, width] = value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sme/ZAtile" mylink="aarch64.functions.sme.ZAtile" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ZAtile[] - non-assignment form</line>
<line>// ==============================</line>
<line></line>
<line link="impl-aarch64.ZAtile.read.3" hover="accessor: bits(width) ZAtile[integer tile, integer esize, integer width]" conts="ZAtile">bits(width) <anchor link="impl-aarch64.ZAtile.read.3" hover="accessor: bits(width) ZAtile[integer tile, integer esize, integer width]">ZAtile</anchor>[integer tile, integer esize, integer width]</line>
<line>    constant integer SVL = <a link="impl-aarch64.CurrentSVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentSVL">CurrentSVL</a>;</line>
<line>    integer slices = SVL DIV esize;</line>
<line>    assert width == SVL * slices;</line>
<line>    bits(width) result;</line>
<line></line>
<line>    for slice = 0 to slices-1</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, slice, SVL] = <a link="impl-aarch64.ZAhslice.read.4" file="shared_pseudocode.xml" hover="accessor: bits(width) ZAhslice[integer tile, integer esize, integer slice, integer width]">ZAhslice</a>[tile, esize, slice, SVL];</line>
<line></line>
<line>    return result;</line>
<line></line>
<line>// ZAtile[] - assignment form</line>
<line>// ==========================</line>
<line></line>
<line link="impl-aarch64.ZAtile.write.3" hover="accessor: ZAtile[integer tile, integer esize, integer width] = bits(width) value" conts="ZAtile"><anchor link="impl-aarch64.ZAtile.write.3" hover="accessor: ZAtile[integer tile, integer esize, integer width] = bits(width) value">ZAtile</anchor>[integer tile, integer esize, integer width] = bits(width) value</line>
<line>    constant integer SVL = <a link="impl-aarch64.CurrentSVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentSVL">CurrentSVL</a>;</line>
<line>    integer slices = SVL DIV esize;</line>
<line>    assert width == SVL * slices;</line>
<line></line>
<line>    for slice = 0 to slices-1</line>
<line>        <a link="impl-aarch64.ZAhslice.write.4" file="shared_pseudocode.xml" hover="accessor: ZAhslice[integer tile, integer esize, integer slice, integer width] = bits(width) value">ZAhslice</a>[tile, esize, slice, SVL] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[value, slice, SVL];</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sme/ZAvector" mylink="aarch64.functions.sme.ZAvector" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ZAvector[] - non-assignment form</line>
<line>// ================================</line>
<line></line>
<line link="impl-aarch64.ZAvector.read.2" hover="accessor: bits(width) ZAvector[integer index, integer width]" conts="ZAvector">bits(width) <anchor link="impl-aarch64.ZAvector.read.2" hover="accessor: bits(width) ZAvector[integer index, integer width]">ZAvector</anchor>[integer index, integer width]</line>
<line>    assert width == <a link="impl-aarch64.CurrentSVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentSVL">CurrentSVL</a>;</line>
<line>    assert index &gt;= 0 &amp;&amp; index &lt; (width DIV 8);</line>
<line></line>
<line>    return _ZA[index]&lt;width-1:0&gt;;</line>
<line></line>
<line>// ZAvector[] - assignment form</line>
<line>// ============================</line>
<line></line>
<line link="impl-aarch64.ZAvector.write.2" hover="accessor: ZAvector[integer index, integer width] = bits(width) value" conts="ZAvector"><anchor link="impl-aarch64.ZAvector.write.2" hover="accessor: ZAvector[integer index, integer width] = bits(width) value">ZAvector</anchor>[integer index, integer width] = bits(width) value</line>
<line>    assert width == <a link="impl-aarch64.CurrentSVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentSVL">CurrentSVL</a>;</line>
<line>    assert index &gt;= 0 &amp;&amp; index &lt; (width DIV 8);</line>
<line></line>
<line>    if <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_SMEZEROUPPER" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_SMEZEROUPPER</a>) then</line>
<line>        _ZA[index] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(value, <a link="MAX_VL" file="shared_pseudocode.xml" hover="constant integer MAX_VL = 2048">MAX_VL</a>);</line>
<line>    else</line>
<line>        _ZA[index]&lt;width-1:0&gt; = value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sme/ZAvslice" mylink="aarch64.functions.sme.ZAvslice" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ZAvslice[] - non-assignment form</line>
<line>// ================================</line>
<line></line>
<line link="impl-aarch64.ZAvslice.read.4" hover="accessor: bits(width) ZAvslice[integer tile, integer esize, integer slice, integer width]" conts="ZAvslice">bits(width) <anchor link="impl-aarch64.ZAvslice.read.4" hover="accessor: bits(width) ZAvslice[integer tile, integer esize, integer slice, integer width]">ZAvslice</anchor>[integer tile, integer esize, integer slice, integer width]</line>
<line>    integer slices = <a link="impl-aarch64.CurrentSVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentSVL">CurrentSVL</a> DIV esize;</line>
<line>    bits(width) result;</line>
<line></line>
<line>    for s = 0 to slices-1</line>
<line>        bits(width) hslice = <a link="impl-aarch64.ZAhslice.read.4" file="shared_pseudocode.xml" hover="accessor: bits(width) ZAhslice[integer tile, integer esize, integer slice, integer width]">ZAhslice</a>[tile, esize, s, width];</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, s, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[hslice, slice, esize];</line>
<line></line>
<line>    return result;</line>
<line></line>
<line>// ZAvslice[] - assignment form</line>
<line>// ============================</line>
<line></line>
<line link="impl-aarch64.ZAvslice.write.4" hover="accessor: ZAvslice[integer tile, integer esize, integer slice, integer width] = bits(width) value" conts="ZAvslice"><anchor link="impl-aarch64.ZAvslice.write.4" hover="accessor: ZAvslice[integer tile, integer esize, integer slice, integer width] = bits(width) value">ZAvslice</anchor>[integer tile, integer esize, integer slice, integer width] = bits(width) value</line>
<line>    integer slices = <a link="impl-aarch64.CurrentSVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentSVL">CurrentSVL</a> DIV esize;</line>
<line></line>
<line>    for s = 0 to slices-1</line>
<line>        bits(width) hslice = <a link="impl-aarch64.ZAhslice.read.4" file="shared_pseudocode.xml" hover="accessor: bits(width) ZAhslice[integer tile, integer esize, integer slice, integer width]">ZAhslice</a>[tile, esize, s, width];</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[hslice, slice, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[value, s, esize];</line>
<line>        <a link="impl-aarch64.ZAhslice.write.4" file="shared_pseudocode.xml" hover="accessor: ZAhslice[integer tile, integer esize, integer slice, integer width] = bits(width) value">ZAhslice</a>[tile, esize, s, width] = hslice;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sme/ZT0" mylink="aarch64.functions.sme.ZT0" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ZT0[] - non-assignment form</line>
<line>// ===========================</line>
<line></line>
<line link="impl-aarch64.ZT0.read.1" hover="accessor: bits(width) ZT0[integer width]" conts="ZT0">bits(width) <anchor link="impl-aarch64.ZT0.read.1" hover="accessor: bits(width) ZT0[integer width]">ZT0</anchor>[integer width]</line>
<line>    assert width == 512;</line>
<line>    return _ZT0&lt;width-1:0&gt;;</line>
<line></line>
<line>// ZT0[] - assignment form</line>
<line>// =======================</line>
<line></line>
<line link="impl-aarch64.ZT0.write.1" hover="accessor: ZT0[integer width] = bits(width) value" conts="ZT0"><anchor link="impl-aarch64.ZT0.write.1" hover="accessor: ZT0[integer width] = bits(width) value">ZT0</anchor>[integer width] = bits(width) value</line>
<line>    assert width == 512;</line>
<line>    _ZT0&lt;width-1:0&gt; = value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/AArch32.IsFPEnabled" mylink="aarch64.functions.sve.AArch32.IsFPEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.IsFPEnabled()</line>
<line>// =====================</line>
<line>// Returns TRUE if access to the SIMD&amp;FP instructions or System registers are</line>
<line>// enabled at the target exception level in AArch32 state and FALSE otherwise.</line>
<line></line>
<line link="AArch32.IsFPEnabled.1" hover="function: boolean AArch32.IsFPEnabled(bits(2) el)" conts="AArch32.IsFPEnabled">boolean <anchor link="AArch32.IsFPEnabled.1" hover="function: boolean AArch32.IsFPEnabled(bits(2) el)">AArch32.IsFPEnabled</anchor>(bits(2) el)</line>
<line>    if el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>        return <a link="AArch64.IsFPEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.IsFPEnabled(bits(2) el)">AArch64.IsFPEnabled</a>(el);</line>
<line></line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() == <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> then</line>
<line>        // Check if access disabled in NSACR</line>
<line>        if NSACR.cp10 == '0' then return FALSE;</line>
<line></line>
<line>    if el IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} then</line>
<line>        // Check if access disabled in CPACR</line>
<line>        boolean disabled;</line>
<line>        case CPACR.cp10 of</line>
<line>            when '00' disabled = TRUE;</line>
<line>            when '01' disabled = el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;</line>
<line>            when '10' disabled = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_RESCPACR" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESCPACR</a>);</line>
<line>            when '11' disabled = FALSE;</line>
<line>        if disabled then return FALSE;</line>
<line></line>
<line>    if el IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        if !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>            return <a link="AArch64.IsFPEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.IsFPEnabled(bits(2) el)">AArch64.IsFPEnabled</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>        if HCPTR.TCP10 == '1' then return FALSE;</line>
<line></line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        // Check if access disabled in CPTR_EL3</line>
<line>        if CPTR_EL3.TFP == '1' then return FALSE;</line>
<line></line>
<line>    return TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/AArch64.IsFPEnabled" mylink="aarch64.functions.sve.AArch64.IsFPEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.IsFPEnabled()</line>
<line>// =====================</line>
<line>// Returns TRUE if access to the SIMD&amp;FP instructions or System registers are</line>
<line>// enabled at the target exception level in AArch64 state and FALSE otherwise.</line>
<line></line>
<line link="AArch64.IsFPEnabled.1" hover="function: boolean AArch64.IsFPEnabled(bits(2) el)" conts="AArch64.IsFPEnabled">boolean <anchor link="AArch64.IsFPEnabled.1" hover="function: boolean AArch64.IsFPEnabled(bits(2) el)">AArch64.IsFPEnabled</anchor>(bits(2) el)</line>
<line>    // Check if access disabled in CPACR_EL1</line>
<line>    if el IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>        // Check SIMD&amp;FP at EL0/EL1</line>
<line>        boolean disabled;</line>
<line>        case CPACR_EL1.FPEN of</line>
<line>            when 'x0' disabled = TRUE;</line>
<line>            when '01' disabled = el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;</line>
<line>            when '11' disabled = FALSE;</line>
<line>        if disabled then return FALSE;</line>
<line></line>
<line>    // Check if access disabled in CPTR_EL2</line>
<line>    if el IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        if <a link="impl-shared.HaveVirtHostExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</a>() &amp;&amp; HCR_EL2.E2H == '1' then</line>
<line>            boolean disabled;</line>
<line>            case CPTR_EL2.FPEN of</line>
<line>                when 'x0' disabled = TRUE;</line>
<line>                when '01' disabled = el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; HCR_EL2.TGE == '1';</line>
<line>                when '11' disabled = FALSE;</line>
<line>            if disabled then return FALSE;</line>
<line>        else</line>
<line>            if CPTR_EL2.TFP == '1' then return FALSE;</line>
<line></line>
<line>    // Check if access disabled in CPTR_EL3</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        if CPTR_EL3.TFP == '1' then return FALSE;</line>
<line></line>
<line>    return TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/ActivePredicateElement" mylink="aarch64.functions.sve.ActivePredicateElement" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ActivePredicateElement()</line>
<line>// ========================</line>
<line>// Returns TRUE if the predicate bit is 1 and FALSE otherwise</line>
<line></line>
<line link="impl-aarch64.ActivePredicateElement.3" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)" conts="ActivePredicateElement">boolean <anchor link="impl-aarch64.ActivePredicateElement.3" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</anchor>(bits(N) pred, integer e, integer esize)</line>
<line>    assert esize IN {8, 16, 32, 64, 128};</line>
<line>    integer n = e * (esize DIV 8);</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt; N;</line>
<line>    return pred&lt;n&gt; == '1';</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/AnyActiveElement" mylink="aarch64.functions.sve.AnyActiveElement" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AnyActiveElement()</line>
<line>// ==================</line>
<line>// Return TRUE if there is at least one active element in mask. Otherwise,</line>
<line>// return FALSE.</line>
<line></line>
<line link="impl-aarch64.AnyActiveElement.2" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)" conts="AnyActiveElement">boolean <anchor link="impl-aarch64.AnyActiveElement.2" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</anchor>(bits(N) mask, integer esize)</line>
<line>    return <a link="impl-aarch64.LastActiveElement.2" file="shared_pseudocode.xml" hover="function: integer LastActiveElement(bits(N) mask, integer esize)">LastActiveElement</a>(mask, esize) &gt;= 0;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/BitDeposit" mylink="aarch64.functions.sve.BitDeposit" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BitDeposit()</line>
<line>// ============</line>
<line>// Deposit the least significant bits from DATA into result positions</line>
<line>// selected by non-zero bits in MASK, setting other result bits to zero.</line>
<line></line>
<line link="impl-aarch64.BitDeposit.2" hover="function: bits(N) BitDeposit (bits(N) data, bits(N) mask)" conts="BitDeposit">bits(N) <anchor link="impl-aarch64.BitDeposit.2" hover="function: bits(N) BitDeposit (bits(N) data, bits(N) mask)">BitDeposit</anchor> (bits(N) data, bits(N) mask)</line>
<line>    bits(N) res = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(N);</line>
<line>    integer db = 0;</line>
<line>    for rb = 0 to N-1</line>
<line>        if mask&lt;rb&gt; == '1' then</line>
<line>            res&lt;rb&gt; = data&lt;db&gt;;</line>
<line>            db = db + 1;</line>
<line>    return res;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/BitExtract" mylink="aarch64.functions.sve.BitExtract" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BitExtract()</line>
<line>// ============</line>
<line>// Extract and pack DATA bits selected by the non-zero bits in MASK into</line>
<line>// the least significant result bits, setting other result bits to zero.</line>
<line></line>
<line link="impl-aarch64.BitExtract.2" hover="function: bits(N) BitExtract (bits(N) data, bits(N) mask)" conts="BitExtract">bits(N) <anchor link="impl-aarch64.BitExtract.2" hover="function: bits(N) BitExtract (bits(N) data, bits(N) mask)">BitExtract</anchor> (bits(N) data, bits(N) mask)</line>
<line>    bits(N) res = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(N);</line>
<line>    integer rb = 0;</line>
<line>    for db = 0 to N-1</line>
<line>        if mask&lt;db&gt; == '1' then</line>
<line>            res&lt;rb&gt; = data&lt;db&gt;;</line>
<line>            rb = rb + 1;</line>
<line>    return res;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/BitGroup" mylink="aarch64.functions.sve.BitGroup" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BitGroup()</line>
<line>// ==========</line>
<line>// Extract and pack DATA bits selected by the non-zero bits in MASK into</line>
<line>// the least significant result bits, and pack unselected bits into the</line>
<line>// most significant result bits.</line>
<line></line>
<line link="impl-aarch64.BitGroup.2" hover="function: bits(N) BitGroup (bits(N) data, bits(N) mask)" conts="BitGroup">bits(N) <anchor link="impl-aarch64.BitGroup.2" hover="function: bits(N) BitGroup (bits(N) data, bits(N) mask)">BitGroup</anchor> (bits(N) data, bits(N) mask)</line>
<line>    bits(N) res;</line>
<line>    integer rb = 0;</line>
<line></line>
<line>    // compress masked bits to right</line>
<line>    for db = 0 to N-1</line>
<line>        if mask&lt;db&gt; == '1' then</line>
<line>            res&lt;rb&gt; = data&lt;db&gt;;</line>
<line>            rb = rb + 1;</line>
<line>    // compress unmasked bits to left</line>
<line>    for db = 0 to N-1</line>
<line>        if mask&lt;db&gt; == '0' then</line>
<line>            res&lt;rb&gt; = data&lt;db&gt;;</line>
<line>            rb = rb + 1;</line>
<line>    return res;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/CeilPow2" mylink="aarch64.functions.sve.CeilPow2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CeilPow2()</line>
<line>// ==========</line>
<line>// For a positive integer X, return the smallest power of 2 &gt;= X</line>
<line></line>
<line link="impl-aarch64.CeilPow2.1" hover="function: integer CeilPow2(integer x)" conts="CeilPow2">integer <anchor link="impl-aarch64.CeilPow2.1" hover="function: integer CeilPow2(integer x)">CeilPow2</anchor>(integer x)</line>
<line>    if x == 0 then return 0;</line>
<line>    if x == 1 then return 2;</line>
<line>    return <a link="impl-aarch64.FloorPow2.1" file="shared_pseudocode.xml" hover="function: integer FloorPow2(integer x)">FloorPow2</a>(x - 1) * 2;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/CheckNonStreamingSVEEnabled" mylink="aarch64.functions.sve.CheckNonStreamingSVEEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckNonStreamingSVEEnabled()</line>
<line>// =============================</line>
<line>// Checks for traps on SVE instructions that are not legal in streaming mode.</line>
<line></line>
<line link="impl-aarch64.CheckNonStreamingSVEEnabled.0" hover="function: CheckNonStreamingSVEEnabled()" conts="CheckNonStreamingSVEEnabled"><anchor link="impl-aarch64.CheckNonStreamingSVEEnabled.0" hover="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</anchor>()</line>
<line>    <a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();</line>
<line></line>
<line>    if <a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() &amp;&amp; PSTATE.SM == '1' &amp;&amp; !<a link="impl-aarch64.IsFullA64Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsFullA64Enabled()">IsFullA64Enabled</a>() then</line>
<line>        <a link="impl-aarch64.SMEAccessTrap.2" file="shared_pseudocode.xml" hover="function: SMEAccessTrap(SMEExceptionType etype, bits(2) target_el_in)">SMEAccessTrap</a>(<a link="SMEExceptionType_Streaming" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_Streaming</a>, PSTATE.EL);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/CheckOriginalSVEEnabled" mylink="aarch64.functions.sve.CheckOriginalSVEEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckOriginalSVEEnabled()</line>
<line>// =========================</line>
<line>// Checks for traps on SVE instructions and instructions that access SVE System</line>
<line>// registers.</line>
<line></line>
<line link="impl-aarch64.CheckOriginalSVEEnabled.0" hover="function: CheckOriginalSVEEnabled()" conts="CheckOriginalSVEEnabled"><anchor link="impl-aarch64.CheckOriginalSVEEnabled.0" hover="function: CheckOriginalSVEEnabled()">CheckOriginalSVEEnabled</anchor>()</line>
<line>    assert <a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>();</line>
<line>    boolean disabled;</line>
<line></line>
<line>    if (<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; (CPTR_EL3.EZ == '0' || CPTR_EL3.TFP == '1') &amp;&amp;</line>
<line>        <a link="impl-shared.EL3SDDUndefPriority.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndefPriority()">EL3SDDUndefPriority</a>()) then</line>
<line>        UNDEFINED;</line>
<line></line>
<line>    // Check if access disabled in CPACR_EL1</line>
<line>    if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>        // Check SVE at EL0/EL1</line>
<line>        case CPACR_EL1.ZEN of</line>
<line>            when 'x0' disabled = TRUE;</line>
<line>            when '01' disabled = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;</line>
<line>            when '11' disabled = FALSE;</line>
<line>        if disabled then <a link="impl-aarch64.SVEAccessTrap.1" file="shared_pseudocode.xml" hover="function: SVEAccessTrap(bits(2) target_el)">SVEAccessTrap</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line></line>
<line>        // Check SIMD&amp;FP at EL0/EL1</line>
<line>        case CPACR_EL1.FPEN of</line>
<line>            when 'x0' disabled = TRUE;</line>
<line>            when '01' disabled = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;</line>
<line>            when '11' disabled = FALSE;</line>
<line>        if disabled then <a link="AArch64.AdvSIMDFPAccessTrap.1" file="shared_pseudocode.xml" hover="function: AArch64.AdvSIMDFPAccessTrap(bits(2) target_el)">AArch64.AdvSIMDFPAccessTrap</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line></line>
<line>    // Check if access disabled in CPTR_EL2</line>
<line>    if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        if <a link="impl-shared.HaveVirtHostExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</a>() &amp;&amp; HCR_EL2.E2H == '1' then</line>
<line>            // Check SVE at EL2</line>
<line>            case CPTR_EL2.ZEN of</line>
<line>                when 'x0' disabled = TRUE;</line>
<line>                when '01' disabled = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; HCR_EL2.TGE == '1';</line>
<line>                when '11' disabled = FALSE;</line>
<line>            if disabled then <a link="impl-aarch64.SVEAccessTrap.1" file="shared_pseudocode.xml" hover="function: SVEAccessTrap(bits(2) target_el)">SVEAccessTrap</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line></line>
<line>            // Check SIMD&amp;FP at EL2</line>
<line>            case CPTR_EL2.FPEN of</line>
<line>                when 'x0' disabled = TRUE;</line>
<line>                when '01' disabled = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; HCR_EL2.TGE == '1';</line>
<line>                when '11' disabled = FALSE;</line>
<line>            if disabled then <a link="AArch64.AdvSIMDFPAccessTrap.1" file="shared_pseudocode.xml" hover="function: AArch64.AdvSIMDFPAccessTrap(bits(2) target_el)">AArch64.AdvSIMDFPAccessTrap</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>        else</line>
<line>            if CPTR_EL2.TZ == '1' then <a link="impl-aarch64.SVEAccessTrap.1" file="shared_pseudocode.xml" hover="function: SVEAccessTrap(bits(2) target_el)">SVEAccessTrap</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>            if CPTR_EL2.TFP == '1' then <a link="AArch64.AdvSIMDFPAccessTrap.1" file="shared_pseudocode.xml" hover="function: AArch64.AdvSIMDFPAccessTrap(bits(2) target_el)">AArch64.AdvSIMDFPAccessTrap</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line></line>
<line>    // Check if access disabled in CPTR_EL3</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        if CPTR_EL3.EZ == '0' then</line>
<line>            if <a link="impl-shared.EL3SDDUndef.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndef()">EL3SDDUndef</a>() then</line>
<line>                UNDEFINED;</line>
<line>            else</line>
<line>                <a link="impl-aarch64.SVEAccessTrap.1" file="shared_pseudocode.xml" hover="function: SVEAccessTrap(bits(2) target_el)">SVEAccessTrap</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line></line>
<line>        if CPTR_EL3.TFP == '1' then</line>
<line>            if <a link="impl-shared.EL3SDDUndef.0" file="shared_pseudocode.xml" hover="function: boolean EL3SDDUndef()">EL3SDDUndef</a>() then</line>
<line>                UNDEFINED;</line>
<line>            else</line>
<line>                <a link="AArch64.AdvSIMDFPAccessTrap.1" file="shared_pseudocode.xml" hover="function: AArch64.AdvSIMDFPAccessTrap(bits(2) target_el)">AArch64.AdvSIMDFPAccessTrap</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/CheckSMEAccess" mylink="aarch64.functions.sve.CheckSMEAccess" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckSMEAccess()</line>
<line>// ================</line>
<line>// Check that access to SME System registers is enabled.</line>
<line></line>
<line link="impl-aarch64.CheckSMEAccess.0" hover="function: CheckSMEAccess()" conts="CheckSMEAccess"><anchor link="impl-aarch64.CheckSMEAccess.0" hover="function: CheckSMEAccess()">CheckSMEAccess</anchor>()</line>
<line>    boolean disabled;</line>
<line>    // Check if access disabled in CPACR_EL1</line>
<line>    if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>        // Check SME at EL0/EL1</line>
<line>        case CPACR_EL1.SMEN of</line>
<line>            when 'x0' disabled = TRUE;</line>
<line>            when '01' disabled = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;</line>
<line>            when '11' disabled = FALSE;</line>
<line>        if disabled then <a link="impl-aarch64.SMEAccessTrap.2" file="shared_pseudocode.xml" hover="function: SMEAccessTrap(SMEExceptionType etype, bits(2) target_el_in)">SMEAccessTrap</a>(<a link="SMEExceptionType_AccessTrap" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_AccessTrap</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line></line>
<line>    if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        if <a link="impl-shared.HaveVirtHostExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</a>() &amp;&amp; HCR_EL2.E2H == '1' then</line>
<line>            // Check SME at EL2</line>
<line>            case CPTR_EL2.SMEN of</line>
<line>                when 'x0' disabled = TRUE;</line>
<line>                when '01' disabled = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; HCR_EL2.TGE == '1';</line>
<line>                when '11' disabled = FALSE;</line>
<line>            if disabled then <a link="impl-aarch64.SMEAccessTrap.2" file="shared_pseudocode.xml" hover="function: SMEAccessTrap(SMEExceptionType etype, bits(2) target_el_in)">SMEAccessTrap</a>(<a link="SMEExceptionType_AccessTrap" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_AccessTrap</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>        else</line>
<line>            if CPTR_EL2.TSM == '1' then <a link="impl-aarch64.SMEAccessTrap.2" file="shared_pseudocode.xml" hover="function: SMEAccessTrap(SMEExceptionType etype, bits(2) target_el_in)">SMEAccessTrap</a>(<a link="SMEExceptionType_AccessTrap" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_AccessTrap</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line></line>
<line>    // Check if access disabled in CPTR_EL3</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        if CPTR_EL3.ESM == '0' then <a link="impl-aarch64.SMEAccessTrap.2" file="shared_pseudocode.xml" hover="function: SMEAccessTrap(SMEExceptionType etype, bits(2) target_el_in)">SMEAccessTrap</a>(<a link="SMEExceptionType_AccessTrap" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_AccessTrap</a>, <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/CheckSMEAndZAEnabled" mylink="aarch64.functions.sve.CheckSMEAndZAEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckSMEAndZAEnabled()</line>
<line>// ======================</line>
<line></line>
<line link="impl-aarch64.CheckSMEAndZAEnabled.0" hover="function: CheckSMEAndZAEnabled()" conts="CheckSMEAndZAEnabled"><anchor link="impl-aarch64.CheckSMEAndZAEnabled.0" hover="function: CheckSMEAndZAEnabled()">CheckSMEAndZAEnabled</anchor>()</line>
<line>    <a link="impl-aarch64.CheckSMEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSMEEnabled()">CheckSMEEnabled</a>();</line>
<line></line>
<line>    if PSTATE.ZA == '0' then</line>
<line>        <a link="impl-aarch64.SMEAccessTrap.2" file="shared_pseudocode.xml" hover="function: SMEAccessTrap(SMEExceptionType etype, bits(2) target_el_in)">SMEAccessTrap</a>(<a link="SMEExceptionType_InactiveZA" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_InactiveZA</a>, PSTATE.EL);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/CheckSMEEnabled" mylink="aarch64.functions.sve.CheckSMEEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckSMEEnabled()</line>
<line>// =================</line>
<line></line>
<line link="impl-aarch64.CheckSMEEnabled.0" hover="function: CheckSMEEnabled()" conts="CheckSMEEnabled"><anchor link="impl-aarch64.CheckSMEEnabled.0" hover="function: CheckSMEEnabled()">CheckSMEEnabled</anchor>()</line>
<line>    boolean disabled;</line>
<line>    // Check if access disabled in CPACR_EL1</line>
<line>    if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>        // Check SME at EL0/EL1</line>
<line>        case CPACR_EL1.SMEN of</line>
<line>            when 'x0' disabled = TRUE;</line>
<line>            when '01' disabled = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;</line>
<line>            when '11' disabled = FALSE;</line>
<line>        if disabled then <a link="impl-aarch64.SMEAccessTrap.2" file="shared_pseudocode.xml" hover="function: SMEAccessTrap(SMEExceptionType etype, bits(2) target_el_in)">SMEAccessTrap</a>(<a link="SMEExceptionType_AccessTrap" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_AccessTrap</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line></line>
<line>        // Check SIMD&amp;FP at EL0/EL1</line>
<line>        case CPACR_EL1.FPEN of</line>
<line>            when 'x0' disabled = TRUE;</line>
<line>            when '01' disabled = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;</line>
<line>            when '11' disabled = FALSE;</line>
<line>        if disabled then <a link="AArch64.AdvSIMDFPAccessTrap.1" file="shared_pseudocode.xml" hover="function: AArch64.AdvSIMDFPAccessTrap(bits(2) target_el)">AArch64.AdvSIMDFPAccessTrap</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line></line>
<line>    if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        if <a link="impl-shared.HaveVirtHostExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</a>() &amp;&amp; HCR_EL2.E2H == '1' then</line>
<line>            // Check SME at EL2</line>
<line>            case CPTR_EL2.SMEN of</line>
<line>                when 'x0' disabled = TRUE;</line>
<line>                when '01' disabled = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; HCR_EL2.TGE == '1';</line>
<line>                when '11' disabled = FALSE;</line>
<line>            if disabled then <a link="impl-aarch64.SMEAccessTrap.2" file="shared_pseudocode.xml" hover="function: SMEAccessTrap(SMEExceptionType etype, bits(2) target_el_in)">SMEAccessTrap</a>(<a link="SMEExceptionType_AccessTrap" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_AccessTrap</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line></line>
<line>            // Check SIMD&amp;FP at EL2</line>
<line>            case CPTR_EL2.FPEN of</line>
<line>                when 'x0' disabled = TRUE;</line>
<line>                when '01' disabled = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; HCR_EL2.TGE == '1';</line>
<line>                when '11' disabled = FALSE;</line>
<line>            if disabled then <a link="AArch64.AdvSIMDFPAccessTrap.1" file="shared_pseudocode.xml" hover="function: AArch64.AdvSIMDFPAccessTrap(bits(2) target_el)">AArch64.AdvSIMDFPAccessTrap</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>        else</line>
<line>            if CPTR_EL2.TSM == '1' then <a link="impl-aarch64.SMEAccessTrap.2" file="shared_pseudocode.xml" hover="function: SMEAccessTrap(SMEExceptionType etype, bits(2) target_el_in)">SMEAccessTrap</a>(<a link="SMEExceptionType_AccessTrap" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_AccessTrap</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>            if CPTR_EL2.TFP == '1' then <a link="AArch64.AdvSIMDFPAccessTrap.1" file="shared_pseudocode.xml" hover="function: AArch64.AdvSIMDFPAccessTrap(bits(2) target_el)">AArch64.AdvSIMDFPAccessTrap</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line></line>
<line>    // Check if access disabled in CPTR_EL3</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        if CPTR_EL3.ESM == '0' then <a link="impl-aarch64.SMEAccessTrap.2" file="shared_pseudocode.xml" hover="function: SMEAccessTrap(SMEExceptionType etype, bits(2) target_el_in)">SMEAccessTrap</a>(<a link="SMEExceptionType_AccessTrap" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_AccessTrap</a>, <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>        if CPTR_EL3.TFP == '1' then <a link="AArch64.AdvSIMDFPAccessTrap.1" file="shared_pseudocode.xml" hover="function: AArch64.AdvSIMDFPAccessTrap(bits(2) target_el)">AArch64.AdvSIMDFPAccessTrap</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/CheckSMEZT0Enabled" mylink="aarch64.functions.sve.CheckSMEZT0Enabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckSMEZT0Enabled()</line>
<line>// ====================</line>
<line>// Checks for ZT0 enabled.</line>
<line></line>
<line link="impl-aarch64.CheckSMEZT0Enabled.0" hover="function: CheckSMEZT0Enabled()" conts="CheckSMEZT0Enabled"><anchor link="impl-aarch64.CheckSMEZT0Enabled.0" hover="function: CheckSMEZT0Enabled()">CheckSMEZT0Enabled</anchor>()</line>
<line>    // Check if ZA and ZT0 are inactive in PSTATE</line>
<line>    if PSTATE.ZA == '0' then</line>
<line>        <a link="impl-aarch64.SMEAccessTrap.2" file="shared_pseudocode.xml" hover="function: SMEAccessTrap(SMEExceptionType etype, bits(2) target_el_in)">SMEAccessTrap</a>(<a link="SMEExceptionType_InactiveZA" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_InactiveZA</a>, PSTATE.EL);</line>
<line></line>
<line>    // Check if EL0/EL1 accesses to ZT0 are disabled in SMCR_EL1</line>
<line>    if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>        if SMCR_EL1.EZT0 == '0' then</line>
<line>            <a link="impl-aarch64.SMEAccessTrap.2" file="shared_pseudocode.xml" hover="function: SMEAccessTrap(SMEExceptionType etype, bits(2) target_el_in)">SMEAccessTrap</a>(<a link="SMEExceptionType_InaccessibleZT0" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_InaccessibleZT0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line></line>
<line>    // Check if EL0/EL1/EL2 accesses to ZT0 are disabled in SMCR_EL2</line>
<line>    if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        if SMCR_EL2.EZT0 == '0' then</line>
<line>            <a link="impl-aarch64.SMEAccessTrap.2" file="shared_pseudocode.xml" hover="function: SMEAccessTrap(SMEExceptionType etype, bits(2) target_el_in)">SMEAccessTrap</a>(<a link="SMEExceptionType_InaccessibleZT0" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_InaccessibleZT0</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line></line>
<line>    // Check if all accesses to ZT0 are disabled in SMCR_EL3</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        if SMCR_EL3.EZT0 == '0' then</line>
<line>            <a link="impl-aarch64.SMEAccessTrap.2" file="shared_pseudocode.xml" hover="function: SMEAccessTrap(SMEExceptionType etype, bits(2) target_el_in)">SMEAccessTrap</a>(<a link="SMEExceptionType_InaccessibleZT0" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_InaccessibleZT0</a>, <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/CheckSVEEnabled" mylink="aarch64.functions.sve.CheckSVEEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckSVEEnabled()</line>
<line>// =================</line>
<line>// Checks for traps on SVE instructions and instructions that</line>
<line>// access SVE System registers.</line>
<line></line>
<line link="impl-aarch64.CheckSVEEnabled.0" hover="function: CheckSVEEnabled()" conts="CheckSVEEnabled"><anchor link="impl-aarch64.CheckSVEEnabled.0" hover="function: CheckSVEEnabled()">CheckSVEEnabled</anchor>()</line>
<line>    if <a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() &amp;&amp; PSTATE.SM == '1' then</line>
<line>        <a link="impl-aarch64.CheckSMEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSMEEnabled()">CheckSMEEnabled</a>();</line>
<line>    elsif <a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() &amp;&amp; !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() then</line>
<line>        <a link="impl-aarch64.CheckStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEEnabled()">CheckStreamingSVEEnabled</a>();</line>
<line>    else</line>
<line>        <a link="impl-aarch64.CheckOriginalSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckOriginalSVEEnabled()">CheckOriginalSVEEnabled</a>();</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/CheckStreamingSVEAndZAEnabled" mylink="aarch64.functions.sve.CheckStreamingSVEAndZAEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckStreamingSVEAndZAEnabled()</line>
<line>// ===============================</line>
<line></line>
<line link="impl-aarch64.CheckStreamingSVEAndZAEnabled.0" hover="function: CheckStreamingSVEAndZAEnabled()" conts="CheckStreamingSVEAndZAEnabled"><anchor link="impl-aarch64.CheckStreamingSVEAndZAEnabled.0" hover="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</anchor>()</line>
<line>    <a link="impl-aarch64.CheckStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEEnabled()">CheckStreamingSVEEnabled</a>();</line>
<line></line>
<line>    if PSTATE.ZA == '0' then</line>
<line>        <a link="impl-aarch64.SMEAccessTrap.2" file="shared_pseudocode.xml" hover="function: SMEAccessTrap(SMEExceptionType etype, bits(2) target_el_in)">SMEAccessTrap</a>(<a link="SMEExceptionType_InactiveZA" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_InactiveZA</a>, PSTATE.EL);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/CheckStreamingSVEEnabled" mylink="aarch64.functions.sve.CheckStreamingSVEEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckStreamingSVEEnabled()</line>
<line>// ==========================</line>
<line></line>
<line link="impl-aarch64.CheckStreamingSVEEnabled.0" hover="function: CheckStreamingSVEEnabled()" conts="CheckStreamingSVEEnabled"><anchor link="impl-aarch64.CheckStreamingSVEEnabled.0" hover="function: CheckStreamingSVEEnabled()">CheckStreamingSVEEnabled</anchor>()</line>
<line>    <a link="impl-aarch64.CheckSMEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSMEEnabled()">CheckSMEEnabled</a>();</line>
<line></line>
<line>    if PSTATE.SM == '0' then</line>
<line>        <a link="impl-aarch64.SMEAccessTrap.2" file="shared_pseudocode.xml" hover="function: SMEAccessTrap(SMEExceptionType etype, bits(2) target_el_in)">SMEAccessTrap</a>(<a link="SMEExceptionType_NotStreaming" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_NotStreaming</a>, PSTATE.EL);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/CurrentNSVL" mylink="aarch64.functions.sve.CurrentNSVL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CurrentNSVL - non-assignment form</line>
<line>// =================================</line>
<line>// Non-Streaming VL</line>
<line></line>
<line link="impl-aarch64.CurrentNSVL.read.none" hover="accessor: integer CurrentNSVL" conts="CurrentNSVL">integer <anchor link="impl-aarch64.CurrentNSVL.read.none" hover="accessor: integer CurrentNSVL">CurrentNSVL</anchor></line>
<line>    integer vl;</line>
<line></line>
<line>    if PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> || (PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>()) then</line>
<line>        vl = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(ZCR_EL1.LEN);</line>
<line></line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || (PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>()) then</line>
<line>        vl = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(ZCR_EL2.LEN);</line>
<line>    elsif PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        vl = <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(vl, <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(ZCR_EL2.LEN));</line>
<line></line>
<line>    if PSTATE.EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then</line>
<line>        vl = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(ZCR_EL3.LEN);</line>
<line>    elsif <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        vl = <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(vl, <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(ZCR_EL3.LEN));</line>
<line></line>
<line>    vl = (vl + 1) * 128;</line>
<line>    vl = <a link="impl-aarch64.ImplementedSVEVectorLength.1" file="shared_pseudocode.xml" hover="function: integer ImplementedSVEVectorLength(integer nbits_in)">ImplementedSVEVectorLength</a>(vl);</line>
<line></line>
<line>    return vl;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/CurrentSVL" mylink="aarch64.functions.sve.CurrentSVL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CurrentSVL - non-assignment form</line>
<line>// ================================</line>
<line>// Streaming SVL</line>
<line></line>
<line link="impl-aarch64.CurrentSVL.read.none" hover="accessor: integer CurrentSVL" conts="CurrentSVL">integer <anchor link="impl-aarch64.CurrentSVL.read.none" hover="accessor: integer CurrentSVL">CurrentSVL</anchor></line>
<line>    integer vl;</line>
<line></line>
<line>    if PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> || (PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>()) then</line>
<line>        vl = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(SMCR_EL1.LEN);</line>
<line></line>
<line>    if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || (PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>()) then</line>
<line>        vl = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(SMCR_EL2.LEN);</line>
<line>    elsif PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        vl = <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(vl, <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(SMCR_EL2.LEN));</line>
<line></line>
<line>    if PSTATE.EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then</line>
<line>        vl = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(SMCR_EL3.LEN);</line>
<line>    elsif <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        vl = <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(vl, <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(SMCR_EL3.LEN));</line>
<line></line>
<line>    vl = (vl + 1) * 128;</line>
<line>    vl = <a link="impl-aarch64.ImplementedSMEVectorLength.1" file="shared_pseudocode.xml" hover="function: integer ImplementedSMEVectorLength(integer nbits_in)">ImplementedSMEVectorLength</a>(vl);</line>
<line></line>
<line>    return vl;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/CurrentVL" mylink="aarch64.functions.sve.CurrentVL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CurrentVL - non-assignment form</line>
<line>// ===============================</line>
<line></line>
<line link="impl-aarch64.CurrentVL.read.none" hover="accessor: integer CurrentVL" conts="CurrentVL">integer <anchor link="impl-aarch64.CurrentVL.read.none" hover="accessor: integer CurrentVL">CurrentVL</anchor></line>
<line>    return if <a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() &amp;&amp; PSTATE.SM == '1' then <a link="impl-aarch64.CurrentSVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentSVL">CurrentSVL</a> else <a link="impl-aarch64.CurrentNSVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentNSVL">CurrentNSVL</a>;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/DecodePredCount" mylink="aarch64.functions.sve.DecodePredCount" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DecodePredCount()</line>
<line>// =================</line>
<line></line>
<line link="impl-aarch64.DecodePredCount.2" hover="function: integer DecodePredCount(bits(5) pattern, integer esize)" conts="DecodePredCount">integer <anchor link="impl-aarch64.DecodePredCount.2" hover="function: integer DecodePredCount(bits(5) pattern, integer esize)">DecodePredCount</anchor>(bits(5) pattern, integer esize)</line>
<line>    integer elements = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a> DIV esize;</line>
<line>    integer numElem;</line>
<line>    case pattern of</line>
<line>        when '00000' numElem = <a link="impl-aarch64.FloorPow2.1" file="shared_pseudocode.xml" hover="function: integer FloorPow2(integer x)">FloorPow2</a>(elements);</line>
<line>        when '00001' numElem = if elements &gt;= 1 then 1 else 0;</line>
<line>        when '00010' numElem = if elements &gt;= 2 then 2 else 0;</line>
<line>        when '00011' numElem = if elements &gt;= 3 then 3 else 0;</line>
<line>        when '00100' numElem = if elements &gt;= 4 then 4 else 0;</line>
<line>        when '00101' numElem = if elements &gt;= 5 then 5 else 0;</line>
<line>        when '00110' numElem = if elements &gt;= 6 then 6 else 0;</line>
<line>        when '00111' numElem = if elements &gt;= 7 then 7 else 0;</line>
<line>        when '01000' numElem = if elements &gt;= 8 then 8 else 0;</line>
<line>        when '01001' numElem = if elements &gt;= 16 then 16 else 0;</line>
<line>        when '01010' numElem = if elements &gt;= 32 then 32 else 0;</line>
<line>        when '01011' numElem = if elements &gt;= 64 then 64 else 0;</line>
<line>        when '01100' numElem = if elements &gt;= 128 then 128 else 0;</line>
<line>        when '01101' numElem = if elements &gt;= 256 then 256 else 0;</line>
<line>        when '11101' numElem = elements - (elements MOD 4);</line>
<line>        when '11110' numElem = elements - (elements MOD 3);</line>
<line>        when '11111' numElem = elements;</line>
<line>        otherwise    numElem = 0;</line>
<line>    return numElem;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/ElemFFR" mylink="aarch64.functions.sve.ElemFFR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ElemFFR[] - non-assignment form</line>
<line>// ===============================</line>
<line></line>
<line link="impl-aarch64.ElemFFR.read.2" hover="accessor: bit ElemFFR[integer e, integer esize]" conts="ElemFFR">bit <anchor link="impl-aarch64.ElemFFR.read.2" hover="accessor: bit ElemFFR[integer e, integer esize]">ElemFFR</anchor>[integer e, integer esize]</line>
<line>    return <a link="impl-aarch64.PredicateElement.3" file="shared_pseudocode.xml" hover="function: bit PredicateElement(bits(N) pred, integer e, integer esize)">PredicateElement</a>(_FFR, e, esize);</line>
<line></line>
<line>// ElemFFR[] - assignment form</line>
<line>// ===========================</line>
<line></line>
<line link="impl-aarch64.ElemFFR.write.2" hover="accessor: ElemFFR[integer e, integer esize] = bit value" conts="ElemFFR"><anchor link="impl-aarch64.ElemFFR.write.2" hover="accessor: ElemFFR[integer e, integer esize] = bit value">ElemFFR</anchor>[integer e, integer esize] = bit value</line>
<line>    integer psize = esize DIV 8;</line>
<line>    integer n = e * psize;</line>
<line>    assert n &gt;= 0 &amp;&amp; (n + psize) &lt;= <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a> DIV 8;</line>
<line>    _FFR&lt;(n+psize)-1:n&gt; = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(value, psize);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/FFR" mylink="aarch64.functions.sve.FFR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FFR[] - non-assignment form</line>
<line>// ===========================</line>
<line></line>
<line link="impl-aarch64.FFR.read.1" hover="accessor: bits(width) FFR[integer width]" conts="FFR">bits(width) <anchor link="impl-aarch64.FFR.read.1" hover="accessor: bits(width) FFR[integer width]">FFR</anchor>[integer width]</line>
<line>    assert width == <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a> DIV 8;</line>
<line>    return _FFR&lt;width-1:0&gt;;</line>
<line></line>
<line>// FFR[] - assignment form</line>
<line>// =======================</line>
<line></line>
<line link="impl-aarch64.FFR.write.1" hover="accessor: FFR[integer width] = bits(width) value" conts="FFR"><anchor link="impl-aarch64.FFR.write.1" hover="accessor: FFR[integer width] = bits(width) value">FFR</anchor>[integer width] = bits(width) value</line>
<line>    assert width == <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a> DIV 8;</line>
<line>    if <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_SVEZEROUPPER" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_SVEZEROUPPER</a>) then</line>
<line>        _FFR = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(value, <a link="MAX_PL" file="shared_pseudocode.xml" hover="constant integer MAX_PL = 256">MAX_PL</a>);</line>
<line>    else</line>
<line>        _FFR&lt;width-1:0&gt; = value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/FPCompareNE" mylink="aarch64.functions.sve.FPCompareNE" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPCompareNE()</line>
<line>// =============</line>
<line></line>
<line link="impl-aarch64.FPCompareNE.3" hover="function: boolean FPCompareNE(bits(N) op1, bits(N) op2, FPCRType fpcr)" conts="FPCompareNE">boolean <anchor link="impl-aarch64.FPCompareNE.3" hover="function: boolean FPCompareNE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareNE</anchor>(bits(N) op1, bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    assert N IN {16,32,64};</line>
<line>    boolean result;</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op1, fpcr);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op2, fpcr);</line>
<line>    op1_nan = type1 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>};</line>
<line>    op2_nan = type2 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>};</line>
<line></line>
<line>    if op1_nan || op2_nan then</line>
<line>        result = TRUE;</line>
<line>        if type1 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> || type2 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> then</line>
<line>            <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>    else // All non-NaN cases can be evaluated on the values produced by FPUnpack()</line>
<line>        result = (value1 != value2);</line>
<line>        <a link="impl-shared.FPProcessDenorms.4" file="shared_pseudocode.xml" hover="function: FPProcessDenorms(FPType type1, FPType type2, integer N, FPCRType fpcr)">FPProcessDenorms</a>(type1, type2, N, fpcr);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/FPCompareUN" mylink="aarch64.functions.sve.FPCompareUN" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPCompareUN()</line>
<line>// =============</line>
<line></line>
<line link="impl-aarch64.FPCompareUN.3" hover="function: boolean FPCompareUN(bits(N) op1, bits(N) op2, FPCRType fpcr)" conts="FPCompareUN">boolean <anchor link="impl-aarch64.FPCompareUN.3" hover="function: boolean FPCompareUN(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareUN</anchor>(bits(N) op1, bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    assert N IN {16,32,64};</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op1, fpcr);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op2, fpcr);</line>
<line></line>
<line>    if type1 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> || type2 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> then</line>
<line>        <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line></line>
<line>    result = type1 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>} || type2 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>};</line>
<line>    if !result then</line>
<line>        <a link="impl-shared.FPProcessDenorms.4" file="shared_pseudocode.xml" hover="function: FPProcessDenorms(FPType type1, FPType type2, integer N, FPCRType fpcr)">FPProcessDenorms</a>(type1, type2, N, fpcr);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/FPConvertSVE" mylink="aarch64.functions.sve.FPConvertSVE" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPConvertSVE()</line>
<line>// ==============</line>
<line></line>
<line link="impl-aarch64.FPConvertSVE.4" hover="function: bits(M) FPConvertSVE(bits(N) op, FPCRType fpcr_in, FPRounding rounding, integer M)" conts="FPConvertSVE">bits(M) <anchor link="impl-aarch64.FPConvertSVE.4" hover="function: bits(M) FPConvertSVE(bits(N) op, FPCRType fpcr_in, FPRounding rounding, integer M)">FPConvertSVE</anchor>(bits(N) op, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in, <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding, integer M)</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    fpcr.AHP = '0';</line>
<line>    return <a link="impl-shared.FPConvert.4" file="shared_pseudocode.xml" hover="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, FPRounding rounding, integer M)">FPConvert</a>(op, fpcr, rounding, M);</line>
<line></line>
<line>// FPConvertSVE()</line>
<line>// ==============</line>
<line></line>
<line link="impl-aarch64.FPConvertSVE.3" hover="function: bits(M) FPConvertSVE(bits(N) op, FPCRType fpcr_in, integer M)" conts="FPConvertSVE">bits(M) <anchor link="impl-aarch64.FPConvertSVE.3" hover="function: bits(M) FPConvertSVE(bits(N) op, FPCRType fpcr_in, integer M)">FPConvertSVE</anchor>(bits(N) op, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in, integer M)</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    fpcr.AHP = '0';</line>
<line>    return <a link="impl-shared.FPConvert.4" file="shared_pseudocode.xml" hover="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, FPRounding rounding, integer M)">FPConvert</a>(op, fpcr, <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(fpcr), M);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/FPExpA" mylink="aarch64.functions.sve.FPExpA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPExpA()</line>
<line>// ========</line>
<line></line>
<line link="impl-aarch64.FPExpA.1" hover="function: bits(N) FPExpA(bits(N) op)" conts="FPExpA">bits(N) <anchor link="impl-aarch64.FPExpA.1" hover="function: bits(N) FPExpA(bits(N) op)">FPExpA</anchor>(bits(N) op)</line>
<line>    assert N IN {16,32,64};</line>
<line>    bits(N) result;</line>
<line>    bits(N) coeff;</line>
<line>    integer idx = if N == 16 then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op&lt;4:0&gt;) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op&lt;5:0&gt;);</line>
<line>    coeff = <a link="impl-aarch64.FPExpCoefficient.read.2" file="shared_pseudocode.xml" hover="accessor: bits(N) FPExpCoefficient[integer index, integer N]">FPExpCoefficient</a>[idx, N];</line>
<line>    if N == 16 then</line>
<line>        result&lt;15:0&gt; = '0':op&lt;9:5&gt;:coeff&lt;9:0&gt;;</line>
<line>    elsif N == 32 then</line>
<line>        result&lt;31:0&gt; = '0':op&lt;13:6&gt;:coeff&lt;22:0&gt;;</line>
<line>    else // N == 64</line>
<line>        result&lt;63:0&gt; = '0':op&lt;16:6&gt;:coeff&lt;51:0&gt;;</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/FPExpCoefficient" mylink="aarch64.functions.sve.FPExpCoefficient" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPExpCoefficient()</line>
<line>// ==================</line>
<line></line>
<line link="impl-aarch64.FPExpCoefficient.read.2" hover="accessor: bits(N) FPExpCoefficient[integer index, integer N]" conts="FPExpCoefficient">bits(N) <anchor link="impl-aarch64.FPExpCoefficient.read.2" hover="accessor: bits(N) FPExpCoefficient[integer index, integer N]">FPExpCoefficient</anchor>[integer index, integer N]</line>
<line>    assert N IN {16,32,64};</line>
<line>    integer result;</line>
<line></line>
<line>    if N == 16 then</line>
<line>        case index of</line>
<line>            when  0 result = 0x0000;</line>
<line>            when  1 result = 0x0016;</line>
<line>            when  2 result = 0x002d;</line>
<line>            when  3 result = 0x0045;</line>
<line>            when  4 result = 0x005d;</line>
<line>            when  5 result = 0x0075;</line>
<line>            when  6 result = 0x008e;</line>
<line>            when  7 result = 0x00a8;</line>
<line>            when  8 result = 0x00c2;</line>
<line>            when  9 result = 0x00dc;</line>
<line>            when 10 result = 0x00f8;</line>
<line>            when 11 result = 0x0114;</line>
<line>            when 12 result = 0x0130;</line>
<line>            when 13 result = 0x014d;</line>
<line>            when 14 result = 0x016b;</line>
<line>            when 15 result = 0x0189;</line>
<line>            when 16 result = 0x01a8;</line>
<line>            when 17 result = 0x01c8;</line>
<line>            when 18 result = 0x01e8;</line>
<line>            when 19 result = 0x0209;</line>
<line>            when 20 result = 0x022b;</line>
<line>            when 21 result = 0x024e;</line>
<line>            when 22 result = 0x0271;</line>
<line>            when 23 result = 0x0295;</line>
<line>            when 24 result = 0x02ba;</line>
<line>            when 25 result = 0x02e0;</line>
<line>            when 26 result = 0x0306;</line>
<line>            when 27 result = 0x032e;</line>
<line>            when 28 result = 0x0356;</line>
<line>            when 29 result = 0x037f;</line>
<line>            when 30 result = 0x03a9;</line>
<line>            when 31 result = 0x03d4;</line>
<line></line>
<line>    elsif N == 32 then</line>
<line>        case index of</line>
<line>            when  0 result = 0x000000;</line>
<line>            when  1 result = 0x0164d2;</line>
<line>            when  2 result = 0x02cd87;</line>
<line>            when  3 result = 0x043a29;</line>
<line>            when  4 result = 0x05aac3;</line>
<line>            when  5 result = 0x071f62;</line>
<line>            when  6 result = 0x08980f;</line>
<line>            when  7 result = 0x0a14d5;</line>
<line>            when  8 result = 0x0b95c2;</line>
<line>            when  9 result = 0x0d1adf;</line>
<line>            when 10 result = 0x0ea43a;</line>
<line>            when 11 result = 0x1031dc;</line>
<line>            when 12 result = 0x11c3d3;</line>
<line>            when 13 result = 0x135a2b;</line>
<line>            when 14 result = 0x14f4f0;</line>
<line>            when 15 result = 0x16942d;</line>
<line>            when 16 result = 0x1837f0;</line>
<line>            when 17 result = 0x19e046;</line>
<line>            when 18 result = 0x1b8d3a;</line>
<line>            when 19 result = 0x1d3eda;</line>
<line>            when 20 result = 0x1ef532;</line>
<line>            when 21 result = 0x20b051;</line>
<line>            when 22 result = 0x227043;</line>
<line>            when 23 result = 0x243516;</line>
<line>            when 24 result = 0x25fed7;</line>
<line>            when 25 result = 0x27cd94;</line>
<line>            when 26 result = 0x29a15b;</line>
<line>            when 27 result = 0x2b7a3a;</line>
<line>            when 28 result = 0x2d583f;</line>
<line>            when 29 result = 0x2f3b79;</line>
<line>            when 30 result = 0x3123f6;</line>
<line>            when 31 result = 0x3311c4;</line>
<line>            when 32 result = 0x3504f3;</line>
<line>            when 33 result = 0x36fd92;</line>
<line>            when 34 result = 0x38fbaf;</line>
<line>            when 35 result = 0x3aff5b;</line>
<line>            when 36 result = 0x3d08a4;</line>
<line>            when 37 result = 0x3f179a;</line>
<line>            when 38 result = 0x412c4d;</line>
<line>            when 39 result = 0x4346cd;</line>
<line>            when 40 result = 0x45672a;</line>
<line>            when 41 result = 0x478d75;</line>
<line>            when 42 result = 0x49b9be;</line>
<line>            when 43 result = 0x4bec15;</line>
<line>            when 44 result = 0x4e248c;</line>
<line>            when 45 result = 0x506334;</line>
<line>            when 46 result = 0x52a81e;</line>
<line>            when 47 result = 0x54f35b;</line>
<line>            when 48 result = 0x5744fd;</line>
<line>            when 49 result = 0x599d16;</line>
<line>            when 50 result = 0x5bfbb8;</line>
<line>            when 51 result = 0x5e60f5;</line>
<line>            when 52 result = 0x60ccdf;</line>
<line>            when 53 result = 0x633f89;</line>
<line>            when 54 result = 0x65b907;</line>
<line>            when 55 result = 0x68396a;</line>
<line>            when 56 result = 0x6ac0c7;</line>
<line>            when 57 result = 0x6d4f30;</line>
<line>            when 58 result = 0x6fe4ba;</line>
<line>            when 59 result = 0x728177;</line>
<line>            when 60 result = 0x75257d;</line>
<line>            when 61 result = 0x77d0df;</line>
<line>            when 62 result = 0x7a83b3;</line>
<line>            when 63 result = 0x7d3e0c;</line>
<line></line>
<line>    else // N == 64</line>
<line>        case index of</line>
<line>            when  0 result = 0x0000000000000;</line>
<line>            when  1 result = 0x02C9A3E778061;</line>
<line>            when  2 result = 0x059B0D3158574;</line>
<line>            when  3 result = 0x0874518759BC8;</line>
<line>            when  4 result = 0x0B5586CF9890F;</line>
<line>            when  5 result = 0x0E3EC32D3D1A2;</line>
<line>            when  6 result = 0x11301D0125B51;</line>
<line>            when  7 result = 0x1429AAEA92DE0;</line>
<line>            when  8 result = 0x172B83C7D517B;</line>
<line>            when  9 result = 0x1A35BEB6FCB75;</line>
<line>            when 10 result = 0x1D4873168B9AA;</line>
<line>            when 11 result = 0x2063B88628CD6;</line>
<line>            when 12 result = 0x2387A6E756238;</line>
<line>            when 13 result = 0x26B4565E27CDD;</line>
<line>            when 14 result = 0x29E9DF51FDEE1;</line>
<line>            when 15 result = 0x2D285A6E4030B;</line>
<line>            when 16 result = 0x306FE0A31B715;</line>
<line>            when 17 result = 0x33C08B26416FF;</line>
<line>            when 18 result = 0x371A7373AA9CB;</line>
<line>            when 19 result = 0x3A7DB34E59FF7;</line>
<line>            when 20 result = 0x3DEA64C123422;</line>
<line>            when 21 result = 0x4160A21F72E2A;</line>
<line>            when 22 result = 0x44E086061892D;</line>
<line>            when 23 result = 0x486A2B5C13CD0;</line>
<line>            when 24 result = 0x4BFDAD5362A27;</line>
<line>            when 25 result = 0x4F9B2769D2CA7;</line>
<line>            when 26 result = 0x5342B569D4F82;</line>
<line>            when 27 result = 0x56F4736B527DA;</line>
<line>            when 28 result = 0x5AB07DD485429;</line>
<line>            when 29 result = 0x5E76F15AD2148;</line>
<line>            when 30 result = 0x6247EB03A5585;</line>
<line>            when 31 result = 0x6623882552225;</line>
<line>            when 32 result = 0x6A09E667F3BCD;</line>
<line>            when 33 result = 0x6DFB23C651A2F;</line>
<line>            when 34 result = 0x71F75E8EC5F74;</line>
<line>            when 35 result = 0x75FEB564267C9;</line>
<line>            when 36 result = 0x7A11473EB0187;</line>
<line>            when 37 result = 0x7E2F336CF4E62;</line>
<line>            when 38 result = 0x82589994CCE13;</line>
<line>            when 39 result = 0x868D99B4492ED;</line>
<line>            when 40 result = 0x8ACE5422AA0DB;</line>
<line>            when 41 result = 0x8F1AE99157736;</line>
<line>            when 42 result = 0x93737B0CDC5E5;</line>
<line>            when 43 result = 0x97D829FDE4E50;</line>
<line>            when 44 result = 0x9C49182A3F090;</line>
<line>            when 45 result = 0xA0C667B5DE565;</line>
<line>            when 46 result = 0xA5503B23E255D;</line>
<line>            when 47 result = 0xA9E6B5579FDBF;</line>
<line>            when 48 result = 0xAE89F995AD3AD;</line>
<line>            when 49 result = 0xB33A2B84F15FB;</line>
<line>            when 50 result = 0xB7F76F2FB5E47;</line>
<line>            when 51 result = 0xBCC1E904BC1D2;</line>
<line>            when 52 result = 0xC199BDD85529C;</line>
<line>            when 53 result = 0xC67F12E57D14B;</line>
<line>            when 54 result = 0xCB720DCEF9069;</line>
<line>            when 55 result = 0xD072D4A07897C;</line>
<line>            when 56 result = 0xD5818DCFBA487;</line>
<line>            when 57 result = 0xDA9E603DB3285;</line>
<line>            when 58 result = 0xDFC97337B9B5F;</line>
<line>            when 59 result = 0xE502EE78B3FF6;</line>
<line>            when 60 result = 0xEA4AFA2A490DA;</line>
<line>            when 61 result = 0xEFA1BEE615A27;</line>
<line>            when 62 result = 0xF50765B6E4540;</line>
<line>            when 63 result = 0xFA7C1819E90D8;</line>
<line></line>
<line>    return result&lt;N-1:0&gt;;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/FPLogB" mylink="aarch64.functions.sve.FPLogB" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPLogB()</line>
<line>// ========</line>
<line></line>
<line link="impl-aarch64.FPLogB.2" hover="function: bits(N) FPLogB(bits(N) op, FPCRType fpcr)" conts="FPLogB">bits(N) <anchor link="impl-aarch64.FPLogB.2" hover="function: bits(N) FPLogB(bits(N) op, FPCRType fpcr)">FPLogB</anchor>(bits(N) op, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    assert N IN {16,32,64};</line>
<line>    integer result;</line>
<line>    (fptype,sign,value) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op, fpcr);</line>
<line></line>
<line>    if fptype == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> || fptype == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> || fptype == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> then</line>
<line>        <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>        result = -(2^(N-1));            // MinInt, 100..00</line>
<line>    elsif fptype == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a> then</line>
<line>        result = 2^(N-1) - 1;           // MaxInt, 011..11</line>
<line>    else</line>
<line>        // FPUnpack has already scaled a subnormal input</line>
<line>        value = <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(value);</line>
<line>        result = 0;</line>
<line>        while value &lt; 1.0 do</line>
<line>            value = value * 2.0;</line>
<line>            result = result - 1;</line>
<line>        while value &gt;= 2.0 do</line>
<line>            value = value / 2.0;</line>
<line>            result = result + 1;</line>
<line></line>
<line>        <a link="impl-shared.FPProcessDenorm.3" file="shared_pseudocode.xml" hover="function: FPProcessDenorm(FPType fptype, integer N, FPCRType fpcr)">FPProcessDenorm</a>(fptype, N, fpcr);</line>
<line></line>
<line>    return result&lt;N-1:0&gt;;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/FPMinNormal" mylink="aarch64.functions.sve.FPMinNormal" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPMinNormal()</line>
<line>// =============</line>
<line></line>
<line link="impl-aarch64.FPMinNormal.2" hover="function: bits(N) FPMinNormal(bit sign, integer N)" conts="FPMinNormal">bits(N) <anchor link="impl-aarch64.FPMinNormal.2" hover="function: bits(N) FPMinNormal(bit sign, integer N)">FPMinNormal</anchor>(bit sign, integer N)</line>
<line>    assert N IN {16,32,64};</line>
<line>    constant integer E = (if N == 16 then 5 elsif N == 32 then 8 else 11);</line>
<line>    constant integer F = N - (E + 1);</line>
<line>    exp = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(E-1):'1';</line>
<line>    frac = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(F);</line>
<line>    return sign : exp : frac;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/FPOne" mylink="aarch64.functions.sve.FPOne" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPOne()</line>
<line>// =======</line>
<line></line>
<line link="impl-aarch64.FPOne.2" hover="function: bits(N) FPOne(bit sign, integer N)" conts="FPOne">bits(N) <anchor link="impl-aarch64.FPOne.2" hover="function: bits(N) FPOne(bit sign, integer N)">FPOne</anchor>(bit sign, integer N)</line>
<line>    assert N IN {16,32,64};</line>
<line>    constant integer E = (if N == 16 then 5 elsif N == 32 then 8 else 11);</line>
<line>    constant integer F = N - (E + 1);</line>
<line>    exp = '0':<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(E-1);</line>
<line>    frac = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(F);</line>
<line>    return sign : exp : frac;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/FPPointFive" mylink="aarch64.functions.sve.FPPointFive" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPPointFive()</line>
<line>// =============</line>
<line></line>
<line link="impl-aarch64.FPPointFive.2" hover="function: bits(N) FPPointFive(bit sign, integer N)" conts="FPPointFive">bits(N) <anchor link="impl-aarch64.FPPointFive.2" hover="function: bits(N) FPPointFive(bit sign, integer N)">FPPointFive</anchor>(bit sign, integer N)</line>
<line>    assert N IN {16,32,64};</line>
<line>    constant integer E = (if N == 16 then 5 elsif N == 32 then 8 else 11);</line>
<line>    constant integer F = N - (E + 1);</line>
<line>    exp = '0':<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(E-2):'0';</line>
<line>    frac = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(F);</line>
<line>    return sign : exp : frac;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/FPScale" mylink="aarch64.functions.sve.FPScale" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPScale()</line>
<line>// =========</line>
<line></line>
<line link="impl-aarch64.FPScale.3" hover="function: bits(N) FPScale(bits (N) op, integer scale, FPCRType fpcr)" conts="FPScale">bits(N) <anchor link="impl-aarch64.FPScale.3" hover="function: bits(N) FPScale(bits (N) op, integer scale, FPCRType fpcr)">FPScale</anchor>(bits (N) op, integer scale, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    assert N IN {16,32,64};</line>
<line>    bits(N) result;</line>
<line>    (fptype,sign,value) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op, fpcr);</line>
<line></line>
<line>    if fptype == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> || fptype == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        result = <a link="impl-shared.FPProcessNaN.3" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr)">FPProcessNaN</a>(fptype, op, fpcr);</line>
<line>    elsif fptype == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> then</line>
<line>        result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign, N);</line>
<line>    elsif fptype == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a> then</line>
<line>        result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>(sign, N);</line>
<line>    else</line>
<line>        result = <a link="impl-shared.FPRound.3" file="shared_pseudocode.xml" hover="function: bits(N) FPRound(real op, FPCRType fpcr, integer N)">FPRound</a>(value * (2.0^scale), fpcr, N);</line>
<line>        <a link="impl-shared.FPProcessDenorm.3" file="shared_pseudocode.xml" hover="function: FPProcessDenorm(FPType fptype, integer N, FPCRType fpcr)">FPProcessDenorm</a>(fptype, N, fpcr);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/FPTrigMAdd" mylink="aarch64.functions.sve.FPTrigMAdd" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPTrigMAdd()</line>
<line>// ============</line>
<line></line>
<line link="impl-aarch64.FPTrigMAdd.4" hover="function: bits(N) FPTrigMAdd(integer x_in, bits(N) op1, bits(N) op2_in, FPCRType fpcr)" conts="FPTrigMAdd">bits(N) <anchor link="impl-aarch64.FPTrigMAdd.4" hover="function: bits(N) FPTrigMAdd(integer x_in, bits(N) op1, bits(N) op2_in, FPCRType fpcr)">FPTrigMAdd</anchor>(integer x_in, bits(N) op1, bits(N) op2_in, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    assert N IN {16,32,64};</line>
<line>    bits(N) coeff;</line>
<line>    bits(N) op2 = op2_in;</line>
<line>    integer x = x_in;</line>
<line>    assert x &gt;= 0;</line>
<line>    assert x &lt; 8;</line>
<line></line>
<line>    if op2&lt;N-1&gt; == '1' then</line>
<line>        x = x + 8;</line>
<line></line>
<line>    coeff    = <a link="impl-aarch64.FPTrigMAddCoefficient.read.2" file="shared_pseudocode.xml" hover="accessor: bits(N) FPTrigMAddCoefficient[integer index, integer N]">FPTrigMAddCoefficient</a>[x, N];</line>
<line>    op2      = <a link="impl-shared.FPAbs.1" file="shared_pseudocode.xml" hover="function: bits(N) FPAbs(bits(N) op)">FPAbs</a>(op2);</line>
<line>    result   = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(coeff, op1, op2, fpcr);</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/FPTrigMAddCoefficient" mylink="aarch64.functions.sve.FPTrigMAddCoefficient" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPTrigMAddCoefficient()</line>
<line>// =======================</line>
<line></line>
<line link="impl-aarch64.FPTrigMAddCoefficient.read.2" hover="accessor: bits(N) FPTrigMAddCoefficient[integer index, integer N]" conts="FPTrigMAddCoefficient">bits(N) <anchor link="impl-aarch64.FPTrigMAddCoefficient.read.2" hover="accessor: bits(N) FPTrigMAddCoefficient[integer index, integer N]">FPTrigMAddCoefficient</anchor>[integer index, integer N]</line>
<line>    assert N IN {16,32,64};</line>
<line>    integer result;</line>
<line></line>
<line>    if N == 16 then</line>
<line>        case index of</line>
<line>            when  0 result = 0x3c00;</line>
<line>            when  1 result = 0xb155;</line>
<line>            when  2 result = 0x2030;</line>
<line>            when  3 result = 0x0000;</line>
<line>            when  4 result = 0x0000;</line>
<line>            when  5 result = 0x0000;</line>
<line>            when  6 result = 0x0000;</line>
<line>            when  7 result = 0x0000;</line>
<line>            when  8 result = 0x3c00;</line>
<line>            when  9 result = 0xb800;</line>
<line>            when 10 result = 0x293a;</line>
<line>            when 11 result = 0x0000;</line>
<line>            when 12 result = 0x0000;</line>
<line>            when 13 result = 0x0000;</line>
<line>            when 14 result = 0x0000;</line>
<line>            when 15 result = 0x0000;</line>
<line>    elsif N == 32 then</line>
<line>        case index of</line>
<line>            when  0 result = 0x3f800000;</line>
<line>            when  1 result = 0xbe2aaaab;</line>
<line>            when  2 result = 0x3c088886;</line>
<line>            when  3 result = 0xb95008b9;</line>
<line>            when  4 result = 0x36369d6d;</line>
<line>            when  5 result = 0x00000000;</line>
<line>            when  6 result = 0x00000000;</line>
<line>            when  7 result = 0x00000000;</line>
<line>            when  8 result = 0x3f800000;</line>
<line>            when  9 result = 0xbf000000;</line>
<line>            when 10 result = 0x3d2aaaa6;</line>
<line>            when 11 result = 0xbab60705;</line>
<line>            when 12 result = 0x37cd37cc;</line>
<line>            when 13 result = 0x00000000;</line>
<line>            when 14 result = 0x00000000;</line>
<line>            when 15 result = 0x00000000;</line>
<line>    else // N == 64</line>
<line>        case index of</line>
<line>            when  0 result = 0x3ff0000000000000;</line>
<line>            when  1 result = 0xbfc5555555555543;</line>
<line>            when  2 result = 0x3f8111111110f30c;</line>
<line>            when  3 result = 0xbf2a01a019b92fc6;</line>
<line>            when  4 result = 0x3ec71de351f3d22b;</line>
<line>            when  5 result = 0xbe5ae5e2b60f7b91;</line>
<line>            when  6 result = 0x3de5d8408868552f;</line>
<line>            when  7 result = 0x0000000000000000;</line>
<line>            when  8 result = 0x3ff0000000000000;</line>
<line>            when  9 result = 0xbfe0000000000000;</line>
<line>            when 10 result = 0x3fa5555555555536;</line>
<line>            when 11 result = 0xbf56c16c16c13a0b;</line>
<line>            when 12 result = 0x3efa01a019b1e8d8;</line>
<line>            when 13 result = 0xbe927e4f7282f468;</line>
<line>            when 14 result = 0x3e21ee96d2641b13;</line>
<line>            when 15 result = 0xbda8f76380fbb401;</line>
<line></line>
<line>    return result&lt;N-1:0&gt;;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/FPTrigSMul" mylink="aarch64.functions.sve.FPTrigSMul" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPTrigSMul()</line>
<line>// ============</line>
<line></line>
<line link="impl-aarch64.FPTrigSMul.3" hover="function: bits(N) FPTrigSMul(bits(N) op1, bits(N) op2, FPCRType fpcr)" conts="FPTrigSMul">bits(N) <anchor link="impl-aarch64.FPTrigSMul.3" hover="function: bits(N) FPTrigSMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPTrigSMul</anchor>(bits(N) op1, bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    assert N IN {16,32,64};</line>
<line>    result = <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(op1, op1, fpcr);</line>
<line>    fpexc = FALSE;</line>
<line>    (fptype, sign, value) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(result, fpcr, fpexc);</line>
<line></line>
<line>    if !(fptype IN {<a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>, <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>}) then</line>
<line>        result&lt;N-1&gt; = op2&lt;0&gt;;</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/FPTrigSSel" mylink="aarch64.functions.sve.FPTrigSSel" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPTrigSSel()</line>
<line>// ============</line>
<line></line>
<line link="impl-aarch64.FPTrigSSel.2" hover="function: bits(N) FPTrigSSel(bits(N) op1, bits(N) op2)" conts="FPTrigSSel">bits(N) <anchor link="impl-aarch64.FPTrigSSel.2" hover="function: bits(N) FPTrigSSel(bits(N) op1, bits(N) op2)">FPTrigSSel</anchor>(bits(N) op1, bits(N) op2)</line>
<line>    assert N IN {16,32,64};</line>
<line>    bits(N) result;</line>
<line></line>
<line>    if op2&lt;0&gt; == '1' then</line>
<line>        result = <a link="impl-aarch64.FPOne.2" file="shared_pseudocode.xml" hover="function: bits(N) FPOne(bit sign, integer N)">FPOne</a>(op2&lt;1&gt;, N);</line>
<line>    elsif op2&lt;1&gt; == '1' then</line>
<line>        result = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(op1);</line>
<line>    else</line>
<line>        result = op1;</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/FirstActive" mylink="aarch64.functions.sve.FirstActive" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FirstActive()</line>
<line>// =============</line>
<line></line>
<line link="impl-aarch64.FirstActive.3" hover="function: bit FirstActive(bits(N) mask, bits(N) x, integer esize)" conts="FirstActive">bit <anchor link="impl-aarch64.FirstActive.3" hover="function: bit FirstActive(bits(N) mask, bits(N) x, integer esize)">FirstActive</anchor>(bits(N) mask, bits(N) x, integer esize)</line>
<line>    integer elements = N DIV (esize DIV 8);</line>
<line>    for e = 0 to elements-1</line>
<line>        if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then</line>
<line>            return <a link="impl-aarch64.PredicateElement.3" file="shared_pseudocode.xml" hover="function: bit PredicateElement(bits(N) pred, integer e, integer esize)">PredicateElement</a>(x, e, esize);</line>
<line>    return '0';</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/FloorPow2" mylink="aarch64.functions.sve.FloorPow2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FloorPow2()</line>
<line>// ===========</line>
<line>// For a positive integer X, return the largest power of 2 &lt;= X</line>
<line></line>
<line link="impl-aarch64.FloorPow2.1" hover="function: integer FloorPow2(integer x)" conts="FloorPow2">integer <anchor link="impl-aarch64.FloorPow2.1" hover="function: integer FloorPow2(integer x)">FloorPow2</anchor>(integer x)</line>
<line>    assert x &gt;= 0;</line>
<line>    integer n = 1;</line>
<line>    if x == 0 then return 0;</line>
<line>    while x &gt;= 2^n do</line>
<line>        n = n + 1;</line>
<line>    return 2^(n - 1);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/HaveSMEFullA64" mylink="aarch64.functions.sve.HaveSMEFullA64" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSMEFullA64()</line>
<line>// ================</line>
<line>// Returns TRUE if the SME FA64 extension is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveSMEFullA64.0" hover="function: boolean HaveSMEFullA64()" conts="HaveSMEFullA64">boolean <anchor link="impl-aarch64.HaveSMEFullA64.0" hover="function: boolean HaveSMEFullA64()">HaveSMEFullA64</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SME_FA64);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/HaveSVE" mylink="aarch64.functions.sve.HaveSVE" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSVE()</line>
<line>// =========</line>
<line></line>
<line link="impl-aarch64.HaveSVE.0" hover="function: boolean HaveSVE()" conts="HaveSVE">boolean <anchor link="impl-aarch64.HaveSVE.0" hover="function: boolean HaveSVE()">HaveSVE</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SVE);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/HaveSVE2" mylink="aarch64.functions.sve.HaveSVE2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSVE2()</line>
<line>// ==========</line>
<line>// Returns TRUE if the SVE2 extension is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveSVE2.0" hover="function: boolean HaveSVE2()" conts="HaveSVE2">boolean <anchor link="impl-aarch64.HaveSVE2.0" hover="function: boolean HaveSVE2()">HaveSVE2</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SVE2);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/HaveSVE2AES" mylink="aarch64.functions.sve.HaveSVE2AES" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSVE2AES()</line>
<line>// =============</line>
<line>// Returns TRUE if the SVE2 AES extension is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveSVE2AES.0" hover="function: boolean HaveSVE2AES()" conts="HaveSVE2AES">boolean <anchor link="impl-aarch64.HaveSVE2AES.0" hover="function: boolean HaveSVE2AES()">HaveSVE2AES</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SVE_AES);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/HaveSVE2BitPerm" mylink="aarch64.functions.sve.HaveSVE2BitPerm" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSVE2BitPerm()</line>
<line>// =================</line>
<line>// Returns TRUE if the SVE2 Bit Permissions extension is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveSVE2BitPerm.0" hover="function: boolean HaveSVE2BitPerm()" conts="HaveSVE2BitPerm">boolean <anchor link="impl-aarch64.HaveSVE2BitPerm.0" hover="function: boolean HaveSVE2BitPerm()">HaveSVE2BitPerm</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SVE_BitPerm);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/HaveSVE2PMULL128" mylink="aarch64.functions.sve.HaveSVE2PMULL128" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSVE2PMULL128()</line>
<line>// ==================</line>
<line>// Returns TRUE if the SVE2 128 bit PMULL extension is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveSVE2PMULL128.0" hover="function: boolean HaveSVE2PMULL128()" conts="HaveSVE2PMULL128">boolean <anchor link="impl-aarch64.HaveSVE2PMULL128.0" hover="function: boolean HaveSVE2PMULL128()">HaveSVE2PMULL128</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SVE_PMULL128);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/HaveSVE2SHA256" mylink="aarch64.functions.sve.HaveSVE2SHA256" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSVE2SHA256()</line>
<line>// ================</line>
<line>// Returns TRUE if the SVE2 SHA256 extension is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveSVE2SHA256.0" hover="function: boolean HaveSVE2SHA256()" conts="HaveSVE2SHA256">boolean <anchor link="impl-aarch64.HaveSVE2SHA256.0" hover="function: boolean HaveSVE2SHA256()">HaveSVE2SHA256</anchor>()</line>
<line>    return <a link="impl-aarch64.HaveSVE2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2()">HaveSVE2</a>() &amp;&amp; boolean IMPLEMENTATION_DEFINED "Have SVE2 SHA256 extension";</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/HaveSVE2SHA3" mylink="aarch64.functions.sve.HaveSVE2SHA3" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSVE2SHA3()</line>
<line>// ==============</line>
<line>// Returns TRUE if the SVE2 SHA3 extension is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveSVE2SHA3.0" hover="function: boolean HaveSVE2SHA3()" conts="HaveSVE2SHA3">boolean <anchor link="impl-aarch64.HaveSVE2SHA3.0" hover="function: boolean HaveSVE2SHA3()">HaveSVE2SHA3</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SVE_SHA3);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/HaveSVE2SHA512" mylink="aarch64.functions.sve.HaveSVE2SHA512" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSVE2SHA512()</line>
<line>// ================</line>
<line>// Returns TRUE if the SVE2 SHA512 extension is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveSVE2SHA512.0" hover="function: boolean HaveSVE2SHA512()" conts="HaveSVE2SHA512">boolean <anchor link="impl-aarch64.HaveSVE2SHA512.0" hover="function: boolean HaveSVE2SHA512()">HaveSVE2SHA512</anchor>()</line>
<line>    return <a link="impl-aarch64.HaveSVE2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2()">HaveSVE2</a>() &amp;&amp; boolean IMPLEMENTATION_DEFINED "Have SVE2 SHA512 extension";</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/HaveSVE2SM3" mylink="aarch64.functions.sve.HaveSVE2SM3" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSVE2SM3()</line>
<line>// =============</line>
<line>// Returns TRUE if the SVE2 SM3 extension is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveSVE2SM3.0" hover="function: boolean HaveSVE2SM3()" conts="HaveSVE2SM3">boolean <anchor link="impl-aarch64.HaveSVE2SM3.0" hover="function: boolean HaveSVE2SM3()">HaveSVE2SM3</anchor>()</line>
<line>    return <a link="impl-aarch64.HaveSVE2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2()">HaveSVE2</a>() &amp;&amp; boolean IMPLEMENTATION_DEFINED "Have SVE2 SM3 extension";</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/HaveSVE2SM4" mylink="aarch64.functions.sve.HaveSVE2SM4" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSVE2SM4()</line>
<line>// =============</line>
<line>// Returns TRUE if the SVE2 SM4 extension is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveSVE2SM4.0" hover="function: boolean HaveSVE2SM4()" conts="HaveSVE2SM4">boolean <anchor link="impl-aarch64.HaveSVE2SM4.0" hover="function: boolean HaveSVE2SM4()">HaveSVE2SM4</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SVE_SM4);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/HaveSVE2p1" mylink="aarch64.functions.sve.HaveSVE2p1" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSVE2p1()</line>
<line>// ============</line>
<line>// Returns TRUE if the SVE2.1 extension is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveSVE2p1.0" hover="function: boolean HaveSVE2p1()" conts="HaveSVE2p1">boolean <anchor link="impl-aarch64.HaveSVE2p1.0" hover="function: boolean HaveSVE2p1()">HaveSVE2p1</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SVE2p1);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/HaveSVEB16B16" mylink="aarch64.functions.sve.HaveSVEB16B16" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSVEB16B16()</line>
<line>// ===============</line>
<line>// Returns TRUE if the SVE2.1 non-widening BFloat16 instructions are implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveSVEB16B16.0" hover="function: boolean HaveSVEB16B16()" conts="HaveSVEB16B16">boolean <anchor link="impl-aarch64.HaveSVEB16B16.0" hover="function: boolean HaveSVEB16B16()">HaveSVEB16B16</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_B16B16);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/HaveSVEFP32MatMulExt" mylink="aarch64.functions.sve.HaveSVEFP32MatMulExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSVEFP32MatMulExt()</line>
<line>// ======================</line>
<line>// Returns TRUE if single-precision floating-point matrix multiply instruction support implemented</line>
<line>// and FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveSVEFP32MatMulExt.0" hover="function: boolean HaveSVEFP32MatMulExt()" conts="HaveSVEFP32MatMulExt">boolean <anchor link="impl-aarch64.HaveSVEFP32MatMulExt.0" hover="function: boolean HaveSVEFP32MatMulExt()">HaveSVEFP32MatMulExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_F32MM);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/HaveSVEFP64MatMulExt" mylink="aarch64.functions.sve.HaveSVEFP64MatMulExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSVEFP64MatMulExt()</line>
<line>// ======================</line>
<line>// Returns TRUE if double-precision floating-point matrix multiply instruction support implemented</line>
<line>// and FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HaveSVEFP64MatMulExt.0" hover="function: boolean HaveSVEFP64MatMulExt()" conts="HaveSVEFP64MatMulExt">boolean <anchor link="impl-aarch64.HaveSVEFP64MatMulExt.0" hover="function: boolean HaveSVEFP64MatMulExt()">HaveSVEFP64MatMulExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_F64MM);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/ImplementedSMEVectorLength" mylink="aarch64.functions.sve.ImplementedSMEVectorLength" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ImplementedSMEVectorLength()</line>
<line>// ============================</line>
<line>// Reduce SVE/SME vector length to a supported value (power of two)</line>
<line></line>
<line link="impl-aarch64.ImplementedSMEVectorLength.1" hover="function: integer ImplementedSMEVectorLength(integer nbits_in)" conts="ImplementedSMEVectorLength">integer <anchor link="impl-aarch64.ImplementedSMEVectorLength.1" hover="function: integer ImplementedSMEVectorLength(integer nbits_in)">ImplementedSMEVectorLength</anchor>(integer nbits_in)</line>
<line>    integer maxbits = <a link="impl-aarch64.MaxImplementedSVL.0" file="shared_pseudocode.xml" hover="function: integer MaxImplementedSVL()">MaxImplementedSVL</a>();</line>
<line>    assert 128 &lt;= maxbits &amp;&amp; maxbits &lt;= 2048 &amp;&amp; <a link="impl-aarch64.IsPow2.1" file="shared_pseudocode.xml" hover="function: boolean IsPow2(integer x)">IsPow2</a>(maxbits);</line>
<line>    integer nbits = <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(nbits_in, maxbits);</line>
<line>    assert 128 &lt;= nbits &amp;&amp; nbits &lt;= 2048 &amp;&amp; <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(nbits, 128) == nbits;</line>
<line></line>
<line>    // Search for a supported power-of-two VL less than or equal to nbits</line>
<line>    while nbits &gt; 128 do</line>
<line>        if <a link="impl-aarch64.IsPow2.1" file="shared_pseudocode.xml" hover="function: boolean IsPow2(integer x)">IsPow2</a>(nbits) &amp;&amp; <a link="impl-aarch64.SupportedPowerTwoSVL.1" file="shared_pseudocode.xml" hover="function: boolean SupportedPowerTwoSVL(integer nbits)">SupportedPowerTwoSVL</a>(nbits) then return nbits;</line>
<line>        nbits = nbits - 128;</line>
<line></line>
<line>    // Return the smallest supported power-of-two VL</line>
<line>    nbits = 128;</line>
<line>    while nbits &lt; maxbits do</line>
<line>        if <a link="impl-aarch64.SupportedPowerTwoSVL.1" file="shared_pseudocode.xml" hover="function: boolean SupportedPowerTwoSVL(integer nbits)">SupportedPowerTwoSVL</a>(nbits) then return nbits;</line>
<line>        nbits = nbits * 2;</line>
<line></line>
<line>    // The only option is maxbits</line>
<line>    return maxbits;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/ImplementedSVEVectorLength" mylink="aarch64.functions.sve.ImplementedSVEVectorLength" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ImplementedSVEVectorLength()</line>
<line>// ============================</line>
<line>// Reduce SVE vector length to a supported value (power of two)</line>
<line></line>
<line link="impl-aarch64.ImplementedSVEVectorLength.1" hover="function: integer ImplementedSVEVectorLength(integer nbits_in)" conts="ImplementedSVEVectorLength">integer <anchor link="impl-aarch64.ImplementedSVEVectorLength.1" hover="function: integer ImplementedSVEVectorLength(integer nbits_in)">ImplementedSVEVectorLength</anchor>(integer nbits_in)</line>
<line>    integer maxbits = <a link="impl-aarch64.MaxImplementedVL.0" file="shared_pseudocode.xml" hover="function: integer MaxImplementedVL()">MaxImplementedVL</a>();</line>
<line>    assert 128 &lt;= maxbits &amp;&amp; maxbits &lt;= 2048 &amp;&amp; <a link="impl-aarch64.IsPow2.1" file="shared_pseudocode.xml" hover="function: boolean IsPow2(integer x)">IsPow2</a>(maxbits);</line>
<line>    integer nbits = <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(nbits_in, maxbits);</line>
<line>    assert 128 &lt;= nbits &amp;&amp; nbits &lt;= 2048 &amp;&amp; <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(nbits, 128) == nbits;</line>
<line></line>
<line>    while nbits &gt; 128 do</line>
<line>        if <a link="impl-aarch64.IsPow2.1" file="shared_pseudocode.xml" hover="function: boolean IsPow2(integer x)">IsPow2</a>(nbits) then return nbits;</line>
<line>        nbits = nbits - 128;</line>
<line>    return nbits;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/InStreamingMode" mylink="aarch64.functions.sve.InStreamingMode" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// InStreamingMode()</line>
<line>// =================</line>
<line></line>
<line link="impl-aarch64.InStreamingMode.0" hover="function: boolean InStreamingMode()" conts="InStreamingMode">boolean <anchor link="impl-aarch64.InStreamingMode.0" hover="function: boolean InStreamingMode()">InStreamingMode</anchor>()</line>
<line>    return <a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() &amp;&amp; PSTATE.SM == '1';</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/IsEven" mylink="aarch64.functions.sve.IsEven" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsEven()</line>
<line>// ========</line>
<line></line>
<line link="impl-aarch64.IsEven.1" hover="function: boolean IsEven(integer val)" conts="IsEven">boolean <anchor link="impl-aarch64.IsEven.1" hover="function: boolean IsEven(integer val)">IsEven</anchor>(integer val)</line>
<line>    return val MOD 2 == 0;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/IsFPEnabled" mylink="aarch64.functions.sve.IsFPEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsFPEnabled()</line>
<line>// =============</line>
<line>// Returns TRUE if accesses to the Advanced SIMD and floating-point</line>
<line>// registers are enabled at the target exception level in the current</line>
<line>// execution state and FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.IsFPEnabled.1" hover="function: boolean IsFPEnabled(bits(2) el)" conts="IsFPEnabled">boolean <anchor link="impl-aarch64.IsFPEnabled.1" hover="function: boolean IsFPEnabled(bits(2) el)">IsFPEnabled</anchor>(bits(2) el)</line>
<line>    if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(el) then</line>
<line>        return <a link="AArch32.IsFPEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch32.IsFPEnabled(bits(2) el)">AArch32.IsFPEnabled</a>(el);</line>
<line>    else</line>
<line>        return <a link="AArch64.IsFPEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.IsFPEnabled(bits(2) el)">AArch64.IsFPEnabled</a>(el);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/IsFullA64Enabled" mylink="aarch64.functions.sve.IsFullA64Enabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsFullA64Enabled()</line>
<line>// ==================</line>
<line>// Returns TRUE is full A64 is enabled in Streaming mode and FALSE othersise.</line>
<line></line>
<line link="impl-aarch64.IsFullA64Enabled.0" hover="function: boolean IsFullA64Enabled()" conts="IsFullA64Enabled">boolean <anchor link="impl-aarch64.IsFullA64Enabled.0" hover="function: boolean IsFullA64Enabled()">IsFullA64Enabled</anchor>()</line>
<line>    if !<a link="impl-aarch64.HaveSMEFullA64.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEFullA64()">HaveSMEFullA64</a>() then return FALSE;</line>
<line></line>
<line>    // Check if full SVE disabled in SMCR_EL1</line>
<line>    if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>        // Check full SVE at EL0/EL1</line>
<line>        if SMCR_EL1.FA64 == '0' then return FALSE;</line>
<line></line>
<line>    // Check if full SVE disabled in SMCR_EL2</line>
<line>    if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        if SMCR_EL2.FA64 == '0' then return FALSE;</line>
<line></line>
<line>    // Check if full SVE disabled in SMCR_EL3</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        if SMCR_EL3.FA64 == '0' then return FALSE;</line>
<line></line>
<line>    return TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/IsOdd" mylink="aarch64.functions.sve.IsOdd" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsOdd()</line>
<line>// =======</line>
<line></line>
<line link="impl-aarch64.IsOdd.1" hover="function: boolean IsOdd(integer val)" conts="IsOdd">boolean <anchor link="impl-aarch64.IsOdd.1" hover="function: boolean IsOdd(integer val)">IsOdd</anchor>(integer val)</line>
<line>    return val MOD 2 == 1;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/IsOriginalSVEEnabled" mylink="aarch64.functions.sve.IsOriginalSVEEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsOriginalSVEEnabled()</line>
<line>// ======================</line>
<line>// Returns TRUE if access to SVE functionality is enabled at the target</line>
<line>// exception level and FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.IsOriginalSVEEnabled.1" hover="function: boolean IsOriginalSVEEnabled(bits(2) el)" conts="IsOriginalSVEEnabled">boolean <anchor link="impl-aarch64.IsOriginalSVEEnabled.1" hover="function: boolean IsOriginalSVEEnabled(bits(2) el)">IsOriginalSVEEnabled</anchor>(bits(2) el)</line>
<line>    boolean disabled;</line>
<line>    if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(el) then</line>
<line>        return FALSE;</line>
<line></line>
<line>    // Check if access disabled in CPACR_EL1</line>
<line>    if el IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>        // Check SVE at EL0/EL1</line>
<line>        case CPACR_EL1.ZEN of</line>
<line>            when 'x0' disabled = TRUE;</line>
<line>            when '01' disabled = el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;</line>
<line>            when '11' disabled = FALSE;</line>
<line>        if disabled then return FALSE;</line>
<line></line>
<line>    // Check if access disabled in CPTR_EL2</line>
<line>    if el IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        if <a link="impl-shared.HaveVirtHostExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</a>() &amp;&amp; HCR_EL2.E2H == '1' then</line>
<line>            case CPTR_EL2.ZEN of</line>
<line>                when 'x0' disabled = TRUE;</line>
<line>                when '01' disabled = el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; HCR_EL2.TGE == '1';</line>
<line>                when '11' disabled = FALSE;</line>
<line>            if disabled then return FALSE;</line>
<line>        else</line>
<line>            if CPTR_EL2.TZ == '1' then return FALSE;</line>
<line></line>
<line>    // Check if access disabled in CPTR_EL3</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        if CPTR_EL3.EZ == '0' then return FALSE;</line>
<line></line>
<line>    return TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/IsPow2" mylink="aarch64.functions.sve.IsPow2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsPow2()</line>
<line>// ========</line>
<line>// Return TRUE if positive integer X is a power of 2. Otherwise,</line>
<line>// return FALSE.</line>
<line></line>
<line link="impl-aarch64.IsPow2.1" hover="function: boolean IsPow2(integer x)" conts="IsPow2">boolean <anchor link="impl-aarch64.IsPow2.1" hover="function: boolean IsPow2(integer x)">IsPow2</anchor>(integer x)</line>
<line>    if x &lt;= 0 then return FALSE;</line>
<line>    return <a link="impl-aarch64.FloorPow2.1" file="shared_pseudocode.xml" hover="function: integer FloorPow2(integer x)">FloorPow2</a>(x) == <a link="impl-aarch64.CeilPow2.1" file="shared_pseudocode.xml" hover="function: integer CeilPow2(integer x)">CeilPow2</a>(x);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/IsSMEEnabled" mylink="aarch64.functions.sve.IsSMEEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsSMEEnabled()</line>
<line>// ==============</line>
<line>// Returns TRUE if access to SME functionality is enabled at the target</line>
<line>// exception level and FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.IsSMEEnabled.1" hover="function: boolean IsSMEEnabled(bits(2) el)" conts="IsSMEEnabled">boolean <anchor link="impl-aarch64.IsSMEEnabled.1" hover="function: boolean IsSMEEnabled(bits(2) el)">IsSMEEnabled</anchor>(bits(2) el)</line>
<line>    boolean disabled;</line>
<line>    if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(el) then</line>
<line>        return FALSE;</line>
<line></line>
<line>    // Check if access disabled in CPACR_EL1</line>
<line>    if el IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>        // Check SME at EL0/EL1</line>
<line>        case CPACR_EL1.SMEN of</line>
<line>            when 'x0' disabled = TRUE;</line>
<line>            when '01' disabled = el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;</line>
<line>            when '11' disabled = FALSE;</line>
<line>        if disabled then return FALSE;</line>
<line></line>
<line>    // Check if access disabled in CPTR_EL2</line>
<line>    if el IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        if <a link="impl-shared.HaveVirtHostExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</a>() &amp;&amp; HCR_EL2.E2H == '1' then</line>
<line>            case CPTR_EL2.SMEN of</line>
<line>                when 'x0' disabled = TRUE;</line>
<line>                when '01' disabled = el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; HCR_EL2.TGE == '1';</line>
<line>                when '11' disabled = FALSE;</line>
<line>            if disabled then return FALSE;</line>
<line>        else</line>
<line>            if CPTR_EL2.TSM == '1' then return FALSE;</line>
<line></line>
<line>    // Check if access disabled in CPTR_EL3</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        if CPTR_EL3.ESM == '0' then return FALSE;</line>
<line></line>
<line>    return TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/IsSVEEnabled" mylink="aarch64.functions.sve.IsSVEEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsSVEEnabled()</line>
<line>// ==============</line>
<line>// Returns TRUE if access to SVE registers is enabled at the target exception</line>
<line>// level and FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.IsSVEEnabled.1" hover="function: boolean IsSVEEnabled(bits(2) el)" conts="IsSVEEnabled">boolean <anchor link="impl-aarch64.IsSVEEnabled.1" hover="function: boolean IsSVEEnabled(bits(2) el)">IsSVEEnabled</anchor>(bits(2) el)</line>
<line>    if <a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() &amp;&amp; PSTATE.SM == '1' then</line>
<line>        return <a link="impl-aarch64.IsSMEEnabled.1" file="shared_pseudocode.xml" hover="function: boolean IsSMEEnabled(bits(2) el)">IsSMEEnabled</a>(el);</line>
<line>    elsif <a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() then</line>
<line>        return <a link="impl-aarch64.IsOriginalSVEEnabled.1" file="shared_pseudocode.xml" hover="function: boolean IsOriginalSVEEnabled(bits(2) el)">IsOriginalSVEEnabled</a>(el);</line>
<line>    else</line>
<line>        return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/LastActive" mylink="aarch64.functions.sve.LastActive" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// LastActive()</line>
<line>// ============</line>
<line></line>
<line link="impl-aarch64.LastActive.3" hover="function: bit LastActive(bits(N) mask, bits(N) x, integer esize)" conts="LastActive">bit <anchor link="impl-aarch64.LastActive.3" hover="function: bit LastActive(bits(N) mask, bits(N) x, integer esize)">LastActive</anchor>(bits(N) mask, bits(N) x, integer esize)</line>
<line>    integer elements = N DIV (esize DIV 8);</line>
<line>    for e = elements-1 downto 0</line>
<line>        if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then</line>
<line>            return <a link="impl-aarch64.PredicateElement.3" file="shared_pseudocode.xml" hover="function: bit PredicateElement(bits(N) pred, integer e, integer esize)">PredicateElement</a>(x, e, esize);</line>
<line>    return '0';</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/LastActiveElement" mylink="aarch64.functions.sve.LastActiveElement" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// LastActiveElement()</line>
<line>// ===================</line>
<line></line>
<line link="impl-aarch64.LastActiveElement.2" hover="function: integer LastActiveElement(bits(N) mask, integer esize)" conts="LastActiveElement">integer <anchor link="impl-aarch64.LastActiveElement.2" hover="function: integer LastActiveElement(bits(N) mask, integer esize)">LastActiveElement</anchor>(bits(N) mask, integer esize)</line>
<line>    integer elements = N DIV (esize DIV 8);</line>
<line>    for e = elements-1 downto 0</line>
<line>        if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then return e;</line>
<line>    return -1;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/MaxImplementedSVL" mylink="aarch64.functions.sve.MaxImplementedSVL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MaxImplementedSVL()</line>
<line>// ===================</line>
<line></line>
<line link="impl-aarch64.MaxImplementedSVL.0" hover="function: integer MaxImplementedSVL()" conts="MaxImplementedSVL">integer <anchor link="impl-aarch64.MaxImplementedSVL.0" hover="function: integer MaxImplementedSVL()">MaxImplementedSVL</anchor>()</line>
<line>    return integer IMPLEMENTATION_DEFINED "Max implemented SVL";</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/MaxImplementedVL" mylink="aarch64.functions.sve.MaxImplementedVL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MaxImplementedVL()</line>
<line>// ==================</line>
<line></line>
<line link="impl-aarch64.MaxImplementedVL.0" hover="function: integer MaxImplementedVL()" conts="MaxImplementedVL">integer <anchor link="impl-aarch64.MaxImplementedVL.0" hover="function: integer MaxImplementedVL()">MaxImplementedVL</anchor>()</line>
<line>    return integer IMPLEMENTATION_DEFINED "Max implemented VL";</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/MaybeZeroSVEUppers" mylink="aarch64.functions.sve.MaybeZeroSVEUppers" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MaybeZeroSVEUppers()</line>
<line>// ====================</line>
<line></line>
<line link="impl-aarch64.MaybeZeroSVEUppers.1" hover="function: MaybeZeroSVEUppers(bits(2) target_el)" conts="MaybeZeroSVEUppers"><anchor link="impl-aarch64.MaybeZeroSVEUppers.1" hover="function: MaybeZeroSVEUppers(bits(2) target_el)">MaybeZeroSVEUppers</anchor>(bits(2) target_el)</line>
<line>    boolean lower_enabled;</line>
<line></line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(target_el) &lt;= <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL) || !<a link="impl-aarch64.IsSVEEnabled.1" file="shared_pseudocode.xml" hover="function: boolean IsSVEEnabled(bits(2) el)">IsSVEEnabled</a>(target_el) then</line>
<line>        return;</line>
<line></line>
<line>    if target_el == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then</line>
<line>        if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>            lower_enabled = <a link="impl-aarch64.IsFPEnabled.1" file="shared_pseudocode.xml" hover="function: boolean IsFPEnabled(bits(2) el)">IsFPEnabled</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>        else</line>
<line>            lower_enabled = <a link="impl-aarch64.IsFPEnabled.1" file="shared_pseudocode.xml" hover="function: boolean IsFPEnabled(bits(2) el)">IsFPEnabled</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line>    elsif target_el == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>        assert !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>        if HCR_EL2.TGE == '0' then</line>
<line>            lower_enabled = <a link="impl-aarch64.IsFPEnabled.1" file="shared_pseudocode.xml" hover="function: boolean IsFPEnabled(bits(2) el)">IsFPEnabled</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line>        else</line>
<line>            lower_enabled = <a link="impl-aarch64.IsFPEnabled.1" file="shared_pseudocode.xml" hover="function: boolean IsFPEnabled(bits(2) el)">IsFPEnabled</a>(<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>);</line>
<line>    else</line>
<line>        assert target_el == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line>        lower_enabled = <a link="impl-aarch64.IsFPEnabled.1" file="shared_pseudocode.xml" hover="function: boolean IsFPEnabled(bits(2) el)">IsFPEnabled</a>(<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>);</line>
<line></line>
<line>    if lower_enabled then</line>
<line>        constant integer VL = if <a link="impl-aarch64.IsSVEEnabled.1" file="shared_pseudocode.xml" hover="function: boolean IsSVEEnabled(bits(2) el)">IsSVEEnabled</a>(PSTATE.EL) then <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a> else 128;</line>
<line>        constant integer PL = VL DIV 8;</line>
<line>        for n = 0 to 31</line>
<line>            if <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_SVEZEROUPPER" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_SVEZEROUPPER</a>) then</line>
<line>                _Z[n] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(_Z[n]&lt;VL-1:0&gt;, <a link="MAX_VL" file="shared_pseudocode.xml" hover="constant integer MAX_VL = 2048">MAX_VL</a>);</line>
<line>        for n = 0 to 15</line>
<line>            if <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_SVEZEROUPPER" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_SVEZEROUPPER</a>) then</line>
<line>                _P[n] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(_P[n]&lt;PL-1:0&gt;, <a link="MAX_PL" file="shared_pseudocode.xml" hover="constant integer MAX_PL = 256">MAX_PL</a>);</line>
<line>        if <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_SVEZEROUPPER" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_SVEZEROUPPER</a>) then</line>
<line>            _FFR = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(_FFR&lt;PL-1:0&gt;, <a link="MAX_PL" file="shared_pseudocode.xml" hover="constant integer MAX_PL = 256">MAX_PL</a>);</line>
<line>        if <a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() &amp;&amp; PSTATE.ZA == '1' then</line>
<line>            constant integer SVL = <a link="impl-aarch64.CurrentSVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentSVL">CurrentSVL</a>;</line>
<line>            constant integer accessiblevecs = SVL DIV 8;</line>
<line>            constant integer allvecs = <a link="impl-aarch64.MaxImplementedSVL.0" file="shared_pseudocode.xml" hover="function: integer MaxImplementedSVL()">MaxImplementedSVL</a>() DIV 8;</line>
<line></line>
<line>            for n = 0 to accessiblevecs - 1</line>
<line>                if <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_SMEZEROUPPER" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_SMEZEROUPPER</a>) then</line>
<line>                    _ZA[n] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(_ZA[n]&lt;SVL-1:0&gt;, <a link="MAX_VL" file="shared_pseudocode.xml" hover="constant integer MAX_VL = 2048">MAX_VL</a>);</line>
<line>            for n = accessiblevecs to allvecs - 1</line>
<line>                if <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_SMEZEROUPPER" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_SMEZEROUPPER</a>) then</line>
<line>                    _ZA[n] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(<a link="MAX_VL" file="shared_pseudocode.xml" hover="constant integer MAX_VL = 2048">MAX_VL</a>);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/MemNF" mylink="aarch64.functions.sve.MemNF" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemNF[] - non-assignment form</line>
<line>// =============================</line>
<line></line>
<line link="impl-aarch64.MemNF.read.3" hover="accessor: (bits(8*size), boolean) MemNF[bits(64) address, integer size, AccessDescriptor accdesc]" conts="MemNF">(bits(8*size), boolean) <anchor link="impl-aarch64.MemNF.read.3" hover="accessor: (bits(8*size), boolean) MemNF[bits(64) address, integer size, AccessDescriptor accdesc]">MemNF</anchor>[bits(64) address, integer size, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc]</line>
<line>    assert size IN {1, 2, 4, 8, 16};</line>
<line>    bits(8*size) value;</line>
<line>    boolean bad;</line>
<line></line>
<line>    boolean aligned = <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, size);</line>
<line></line>
<line>    if !aligned &amp;&amp; <a link="impl-shared.AlignmentEnforced.0" file="shared_pseudocode.xml" hover="function: boolean AlignmentEnforced()">AlignmentEnforced</a>() then</line>
<line>        return (bits(8*size) UNKNOWN, TRUE);</line>
<line></line>
<line>    boolean atomic = aligned || size == 1;</line>
<line></line>
<line>    if !atomic then</line>
<line>        (value&lt;7:0&gt;, bad) = <a link="impl-aarch64.MemSingleNF.read.4" file="shared_pseudocode.xml" hover="accessor: (bits(8*size), boolean) MemSingleNF[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned]">MemSingleNF</a>[address, 1, accdesc, aligned];</line>
<line></line>
<line>        if bad then</line>
<line>            return (bits(8*size) UNKNOWN, TRUE);</line>
<line></line>
<line>        // For subsequent bytes it is CONSTRAINED UNPREDICTABLE whether an unaligned Device memory</line>
<line>        // access will generate an Alignment Fault, as to get this far means the first byte did</line>
<line>        // not, so we must be changing to a new translation page.</line>
<line>        if !aligned then</line>
<line>            c = <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_DEVPAGE2" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_DEVPAGE2</a>);</line>
<line>            assert c IN {<a link="Constraint_FAULT" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_FAULT</a>, <a link="Constraint_NONE" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NONE</a>};</line>
<line>            if c == <a link="Constraint_NONE" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NONE</a> then aligned = TRUE;</line>
<line></line>
<line>        for i = 1 to size-1</line>
<line>            (value&lt;8*i+7:8*i&gt;, bad) = <a link="impl-aarch64.MemSingleNF.read.4" file="shared_pseudocode.xml" hover="accessor: (bits(8*size), boolean) MemSingleNF[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned]">MemSingleNF</a>[address+i, 1, accdesc, aligned];</line>
<line></line>
<line>            if bad then</line>
<line>                return (bits(8*size) UNKNOWN, TRUE);</line>
<line>    else</line>
<line>        (value, bad) = <a link="impl-aarch64.MemSingleNF.read.4" file="shared_pseudocode.xml" hover="accessor: (bits(8*size), boolean) MemSingleNF[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned]">MemSingleNF</a>[address, size, accdesc, aligned];</line>
<line>        if bad then</line>
<line>            return (bits(8*size) UNKNOWN, TRUE);</line>
<line></line>
<line>    if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(accdesc.acctype) then</line>
<line>        value = <a link="impl-shared.BigEndianReverse.1" file="shared_pseudocode.xml" hover="function: bits(width) BigEndianReverse (bits(width) value)">BigEndianReverse</a>(value);</line>
<line></line>
<line>    return (value, FALSE);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/MemSingleNF" mylink="aarch64.functions.sve.MemSingleNF" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemSingleNF[] - non-assignment form</line>
<line>// ===================================</line>
<line></line>
<line link="impl-aarch64.MemSingleNF.read.4" hover="accessor: (bits(8*size), boolean) MemSingleNF[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned]" conts="MemSingleNF">(bits(8*size), boolean) <anchor link="impl-aarch64.MemSingleNF.read.4" hover="accessor: (bits(8*size), boolean) MemSingleNF[bits(64) address, integer size, AccessDescriptor accdesc_in, boolean aligned]">MemSingleNF</anchor>[bits(64) address, integer size, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc_in,</line>
<line>                                    boolean aligned]</line>
<line>    assert accdesc_in.acctype == <a link="AccessType_SVE" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_SVE</a>;</line>
<line>    assert accdesc_in.nonfault || (accdesc_in.firstfault &amp;&amp; !accdesc_in.first);</line>
<line></line>
<line>    bits(8*size) value;</line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc;</line>
<line>    <a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> memstatus;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = accdesc_in;</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = <a link="impl-shared.NoFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord NoFault(AccessDescriptor accdesc)">NoFault</a>(accdesc);</line>
<line></line>
<line>    // Implementation may suppress NF load for any reason</line>
<line>    if <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_NONFAULT" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_NONFAULT</a>) then</line>
<line>        return (bits(8*size) UNKNOWN, TRUE);</line>
<line></line>
<line>    // If the instruction encoding permits tag checking, confer with system register configuration</line>
<line>    // which may override this.</line>
<line>    if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; accdesc.tagchecked then</line>
<line>        accdesc.tagchecked = <a link="AArch64.AccessIsTagChecked.2" file="shared_pseudocode.xml" hover="function: boolean AArch64.AccessIsTagChecked(bits(64) vaddr, AccessDescriptor accdesc)">AArch64.AccessIsTagChecked</a>(address, accdesc);</line>
<line></line>
<line>    // MMU or MPU</line>
<line>    memaddrdesc = <a link="AArch64.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch64.TranslateAddress(bits(64) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch64.TranslateAddress</a>(address, accdesc, aligned, size);</line>
<line></line>
<line>    // Non-fault load from Device memory must not be performed externally</line>
<line>    if memaddrdesc.memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> then</line>
<line>        return (bits(8*size) UNKNOWN, TRUE);</line>
<line></line>
<line>    // Check for aborts or debug exceptions</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>        return (bits(8*size) UNKNOWN, TRUE);</line>
<line></line>
<line>    if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; accdesc.tagchecked then</line>
<line>        bits(4) ptag = <a link="AArch64.PhysicalTag.1" file="shared_pseudocode.xml" hover="function: bits(4) AArch64.PhysicalTag(bits(64) vaddr)">AArch64.PhysicalTag</a>(address);</line>
<line>        if !<a link="AArch64.CheckTag.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.CheckTag(AddressDescriptor memaddrdesc, AccessDescriptor accdesc, bits(4) ptag)">AArch64.CheckTag</a>(memaddrdesc, accdesc, ptag) then</line>
<line>            return (bits(8*size) UNKNOWN, TRUE);</line>
<line></line>
<line>    (memstatus, value) = <a link="impl-shared.PhysMemRead.3" file="shared_pseudocode.xml" hover="function: (PhysMemRetStatus, bits(8*size)) PhysMemRead(AddressDescriptor desc, integer size, AccessDescriptor accdesc)">PhysMemRead</a>(memaddrdesc, size, accdesc);</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>        boolean iswrite = FALSE;</line>
<line>        if <a link="impl-shared.IsExternalAbortTakenSynchronously.5" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbortTakenSynchronously(PhysMemRetStatus memstatus, boolean iswrite, AddressDescriptor desc, integer size, AccessDescriptor accdesc)">IsExternalAbortTakenSynchronously</a>(memstatus, iswrite, memaddrdesc, size, accdesc) then</line>
<line>            return (bits(8*size) UNKNOWN, TRUE);</line>
<line>        fault.merrorstate = memstatus.merrorstate;</line>
<line>        fault.extflag    = memstatus.extflag;</line>
<line>        fault.statuscode = memstatus.statuscode;</line>
<line>        <a link="impl-shared.PendSErrorInterrupt.1" file="shared_pseudocode.xml" hover="function: PendSErrorInterrupt(FaultRecord fault)">PendSErrorInterrupt</a>(fault);</line>
<line></line>
<line>    return (value, FALSE);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/NoneActive" mylink="aarch64.functions.sve.NoneActive" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// NoneActive()</line>
<line>// ============</line>
<line></line>
<line link="impl-aarch64.NoneActive.3" hover="function: bit NoneActive(bits(N) mask, bits(N) x, integer esize)" conts="NoneActive">bit <anchor link="impl-aarch64.NoneActive.3" hover="function: bit NoneActive(bits(N) mask, bits(N) x, integer esize)">NoneActive</anchor>(bits(N) mask, bits(N) x, integer esize)</line>
<line>    integer elements = N DIV (esize DIV 8);</line>
<line>    for e = 0 to elements-1</line>
<line>        if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) &amp;&amp; <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(x, e, esize) then</line>
<line>            return '0';</line>
<line>    return '1';</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/P" mylink="aarch64.functions.sve.P" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// P[] - non-assignment form</line>
<line>// =========================</line>
<line></line>
<line link="impl-aarch64.P.read.2" hover="accessor: bits(width) P[integer n, integer width]" conts="P">bits(width) <anchor link="impl-aarch64.P.read.2" hover="accessor: bits(width) P[integer n, integer width]">P</anchor>[integer n, integer width]</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt;= 31;</line>
<line>    assert width == <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a> DIV 8;</line>
<line>    return _P[n]&lt;width-1:0&gt;;</line>
<line></line>
<line>// P[] - assignment form</line>
<line>// =====================</line>
<line></line>
<line link="impl-aarch64.P.write.2" hover="accessor: P[integer n, integer width] = bits(width) value" conts="P"><anchor link="impl-aarch64.P.write.2" hover="accessor: P[integer n, integer width] = bits(width) value">P</anchor>[integer n, integer width] = bits(width) value</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt;= 31;</line>
<line>    assert width == <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a> DIV 8;</line>
<line>    if <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_SVEZEROUPPER" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_SVEZEROUPPER</a>) then</line>
<line>        _P[n] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(value, <a link="MAX_PL" file="shared_pseudocode.xml" hover="constant integer MAX_PL = 256">MAX_PL</a>);</line>
<line>    else</line>
<line>        _P[n]&lt;width-1:0&gt; = value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/PredTest" mylink="aarch64.functions.sve.PredTest" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PredTest()</line>
<line>// ==========</line>
<line></line>
<line link="impl-aarch64.PredTest.3" hover="function: bits(4) PredTest(bits(N) mask, bits(N) result, integer esize)" conts="PredTest">bits(4) <anchor link="impl-aarch64.PredTest.3" hover="function: bits(4) PredTest(bits(N) mask, bits(N) result, integer esize)">PredTest</anchor>(bits(N) mask, bits(N) result, integer esize)</line>
<line>    bit n = <a link="impl-aarch64.FirstActive.3" file="shared_pseudocode.xml" hover="function: bit FirstActive(bits(N) mask, bits(N) x, integer esize)">FirstActive</a>(mask, result, esize);</line>
<line>    bit z = <a link="impl-aarch64.NoneActive.3" file="shared_pseudocode.xml" hover="function: bit NoneActive(bits(N) mask, bits(N) x, integer esize)">NoneActive</a>(mask, result, esize);</line>
<line>    bit c = NOT <a link="impl-aarch64.LastActive.3" file="shared_pseudocode.xml" hover="function: bit LastActive(bits(N) mask, bits(N) x, integer esize)">LastActive</a>(mask, result, esize);</line>
<line>    bit v = '0';</line>
<line>    return n:z:c:v;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/PredicateElement" mylink="aarch64.functions.sve.PredicateElement" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PredicateElement()</line>
<line>// ==================</line>
<line>// Returns the predicate bit</line>
<line></line>
<line link="impl-aarch64.PredicateElement.3" hover="function: bit PredicateElement(bits(N) pred, integer e, integer esize)" conts="PredicateElement">bit <anchor link="impl-aarch64.PredicateElement.3" hover="function: bit PredicateElement(bits(N) pred, integer e, integer esize)">PredicateElement</anchor>(bits(N) pred, integer e, integer esize)</line>
<line>    assert esize IN {8, 16, 32, 64, 128};</line>
<line>    integer n = e * (esize DIV 8);</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt; N;</line>
<line>    return pred&lt;n&gt;;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/ReducePredicated" mylink="aarch64.functions.sve.ReducePredicated" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ReducePredicated()</line>
<line>// ==================</line>
<line></line>
<line link="impl-aarch64.ReducePredicated.4" hover="function: bits(esize) ReducePredicated(ReduceOp op, bits(N) input, bits(M) mask, bits(esize) identity)" conts="ReducePredicated">bits(esize) <anchor link="impl-aarch64.ReducePredicated.4" hover="function: bits(esize) ReducePredicated(ReduceOp op, bits(N) input, bits(M) mask, bits(esize) identity)">ReducePredicated</anchor>(<a link="ReduceOp" file="shared_pseudocode.xml" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}">ReduceOp</a> op, bits(N) input, bits(M) mask, bits(esize) identity)</line>
<line>    assert(N == M * 8);</line>
<line>    integer p2bits = <a link="impl-aarch64.CeilPow2.1" file="shared_pseudocode.xml" hover="function: integer CeilPow2(integer x)">CeilPow2</a>(N);</line>
<line>    bits(p2bits) operand;</line>
<line>    integer elements = p2bits DIV esize;</line>
<line></line>
<line>    for e = 0 to elements-1</line>
<line>        if e * esize &lt; N &amp;&amp; <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[operand, e, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[input, e, esize];</line>
<line>        else</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[operand, e, esize] = identity;</line>
<line></line>
<line>    return <a link="impl-aarch64.Reduce.3" file="shared_pseudocode.xml" hover="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize)">Reduce</a>(op, operand, esize);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/ResetSMEState" mylink="aarch64.functions.sve.ResetSMEState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ResetSMEState()</line>
<line>// ===============</line>
<line></line>
<line link="impl-aarch64.ResetSMEState.0" hover="function: ResetSMEState()" conts="ResetSMEState"><anchor link="impl-aarch64.ResetSMEState.0" hover="function: ResetSMEState()">ResetSMEState</anchor>()</line>
<line>    integer vectors = <a link="MAX_VL" file="shared_pseudocode.xml" hover="constant integer MAX_VL = 2048">MAX_VL</a> DIV 8;</line>
<line>    for n = 0 to vectors - 1</line>
<line>        _ZA[n] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(<a link="MAX_VL" file="shared_pseudocode.xml" hover="constant integer MAX_VL = 2048">MAX_VL</a>);</line>
<line>    _ZT0 = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(<a link="ZT0_LEN" file="shared_pseudocode.xml" hover="constant integer ZT0_LEN = 512">ZT0_LEN</a>);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/ResetSVEState" mylink="aarch64.functions.sve.ResetSVEState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ResetSVEState()</line>
<line>// ===============</line>
<line></line>
<line link="impl-aarch64.ResetSVEState.0" hover="function: ResetSVEState()" conts="ResetSVEState"><anchor link="impl-aarch64.ResetSVEState.0" hover="function: ResetSVEState()">ResetSVEState</anchor>()</line>
<line>    for n = 0 to 31</line>
<line>        _Z[n] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(<a link="MAX_VL" file="shared_pseudocode.xml" hover="constant integer MAX_VL = 2048">MAX_VL</a>);</line>
<line>    for n = 0 to 15</line>
<line>        _P[n] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(<a link="MAX_PL" file="shared_pseudocode.xml" hover="constant integer MAX_PL = 256">MAX_PL</a>);</line>
<line>    _FFR = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(<a link="MAX_PL" file="shared_pseudocode.xml" hover="constant integer MAX_PL = 256">MAX_PL</a>);</line>
<line>    FPSR = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(0x0800009f&lt;31:0&gt;, 64);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/Reverse" mylink="aarch64.functions.sve.Reverse" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Reverse()</line>
<line>// =========</line>
<line>// Reverse subwords of M bits in an N-bit word</line>
<line></line>
<line link="impl-aarch64.Reverse.2" hover="function: bits(N) Reverse(bits(N) word, integer M)" conts="Reverse">bits(N) <anchor link="impl-aarch64.Reverse.2" hover="function: bits(N) Reverse(bits(N) word, integer M)">Reverse</anchor>(bits(N) word, integer M)</line>
<line>    bits(N) result;</line>
<line>    integer sw = N DIV M;</line>
<line>    assert N == sw * M;</line>
<line>    for s = 0 to sw-1</line>
<line>        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, (sw - 1) - s, M] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[word, s, M];</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/SMEAccessTrap" mylink="aarch64.functions.sve.SMEAccessTrap" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SMEAccessTrap()</line>
<line>// ===============</line>
<line>// Trapped access to SME registers due to CPACR_EL1, CPTR_EL2, or CPTR_EL3.</line>
<line></line>
<line link="impl-aarch64.SMEAccessTrap.2" hover="function: SMEAccessTrap(SMEExceptionType etype, bits(2) target_el_in)" conts="SMEAccessTrap"><anchor link="impl-aarch64.SMEAccessTrap.2" hover="function: SMEAccessTrap(SMEExceptionType etype, bits(2) target_el_in)">SMEAccessTrap</anchor>(<a link="SMEExceptionType" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType</a> etype, bits(2) target_el_in)</line>
<line>    bits(2) target_el = target_el_in;</line>
<line>    assert <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(target_el) &gt;= <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL);</line>
<line>    if target_el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        target_el = <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>    boolean route_to_el2;</line>
<line>    route_to_el2 = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; target_el == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1';</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_SMEAccessTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SMEAccessTrap</a>);</line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x0;</line>
<line></line>
<line>    case etype of</line>
<line>        when <a link="SMEExceptionType_AccessTrap" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_AccessTrap</a></line>
<line>            exception.syndrome&lt;2:0&gt; = '000';</line>
<line>        when <a link="SMEExceptionType_Streaming" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_Streaming</a></line>
<line>            exception.syndrome&lt;2:0&gt; = '001';</line>
<line>        when <a link="SMEExceptionType_NotStreaming" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_NotStreaming</a></line>
<line>            exception.syndrome&lt;2:0&gt; = '010';</line>
<line>        when <a link="SMEExceptionType_InactiveZA" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_InactiveZA</a></line>
<line>            exception.syndrome&lt;2:0&gt; = '011';</line>
<line>        when <a link="SMEExceptionType_InaccessibleZT0" file="shared_pseudocode.xml" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_InaccessibleZT0</a></line>
<line>            exception.syndrome&lt;2:0&gt; = '100';</line>
<line></line>
<line>    if route_to_el2 then</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, exception, preferred_exception_return, vect_offset);</line>
<line>    else</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(target_el, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/SMEExceptionType" mylink="aarch64.functions.sve.SMEExceptionType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SMEExceptionType</line>
<line>// ================</line>
<line link="SMEExceptionType" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }" conts="SMEExceptionType">enumeration <anchor link="SMEExceptionType" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType</anchor> {</line>
<line link="SMEExceptionType_AccessTrap" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }" conts="SMEExceptionType_AccessTrap">    <anchor link="SMEExceptionType_AccessTrap" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_AccessTrap</anchor>,        // SME functionality trapped or disabled</line>
<line link="SMEExceptionType_Streaming" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }" conts="SMEExceptionType_Streaming">    <anchor link="SMEExceptionType_Streaming" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_Streaming</anchor>,         // Illegal instruction in Streaming SVE mode</line>
<line link="SMEExceptionType_NotStreaming" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }" conts="SMEExceptionType_NotStreaming">    <anchor link="SMEExceptionType_NotStreaming" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_NotStreaming</anchor>,      // Illegal instruction not in Streaming SVE mode</line>
<line link="SMEExceptionType_InactiveZA" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }" conts="SMEExceptionType_InactiveZA">    <anchor link="SMEExceptionType_InactiveZA" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_InactiveZA</anchor>,        // Illegal instruction when ZA is inactive</line>
<line link="SMEExceptionType_InaccessibleZT0" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }" conts="SMEExceptionType_InaccessibleZT0">    <anchor link="SMEExceptionType_InaccessibleZT0" hover="enumeration SMEExceptionType { SMEExceptionType_AccessTrap, SMEExceptionType_Streaming, SMEExceptionType_NotStreaming, SMEExceptionType_InactiveZA, SMEExceptionType_InaccessibleZT0, }">SMEExceptionType_InaccessibleZT0</anchor>,   // Access to ZT0 is disabled</line>
<line>};</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/SVEAccessTrap" mylink="aarch64.functions.sve.SVEAccessTrap" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SVEAccessTrap()</line>
<line>// ===============</line>
<line>// Trapped access to SVE registers due to CPACR_EL1, CPTR_EL2, or CPTR_EL3.</line>
<line></line>
<line link="impl-aarch64.SVEAccessTrap.1" hover="function: SVEAccessTrap(bits(2) target_el)" conts="SVEAccessTrap"><anchor link="impl-aarch64.SVEAccessTrap.1" hover="function: SVEAccessTrap(bits(2) target_el)">SVEAccessTrap</anchor>(bits(2) target_el)</line>
<line>    assert <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(target_el) &gt;= <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL) &amp;&amp; target_el != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(target_el);</line>
<line>    route_to_el2 = target_el == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1';</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_SVEAccessTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SVEAccessTrap</a>);</line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x0;</line>
<line></line>
<line>    if route_to_el2 then</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, exception, preferred_exception_return, vect_offset);</line>
<line>    else</line>
<line>        <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(target_el, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/SVECmp" mylink="aarch64.functions.sve.SVECmp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SVECmp</line>
<line>// ======</line>
<line></line>
<line link="SVECmp" hover="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }" conts="SVECmp">enumeration <anchor link="SVECmp" hover="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</anchor> { <anchor link="Cmp_EQ" hover="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_EQ</anchor>, <anchor link="Cmp_NE" hover="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_NE</anchor>, <anchor link="Cmp_GE" hover="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GE</anchor>, <anchor link="Cmp_GT" hover="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GT</anchor>, <anchor link="Cmp_LT" hover="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_LT</anchor>, <anchor link="Cmp_LE" hover="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_LE</anchor>, <anchor link="Cmp_UN" hover="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_UN</anchor> };</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/SVEMoveMaskPreferred" mylink="aarch64.functions.sve.SVEMoveMaskPreferred" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SVEMoveMaskPreferred()</line>
<line>// ======================</line>
<line>// Return FALSE if a bitmask immediate encoding would generate an immediate</line>
<line>// value that could also be represented by a single DUP instruction.</line>
<line>// Used as a condition for the preferred MOV&lt;-DUPM alias.</line>
<line></line>
<line link="impl-aarch64.SVEMoveMaskPreferred.1" hover="function: boolean SVEMoveMaskPreferred(bits(13) imm13)" conts="SVEMoveMaskPreferred">boolean <anchor link="impl-aarch64.SVEMoveMaskPreferred.1" hover="function: boolean SVEMoveMaskPreferred(bits(13) imm13)">SVEMoveMaskPreferred</anchor>(bits(13) imm13)</line>
<line>    bits(64) imm;</line>
<line>    (imm, -) = <a link="impl-aarch64.DecodeBitMasks.5" file="shared_pseudocode.xml" hover="function: (bits(M), bits(M)) DecodeBitMasks(bit immN, bits(6) imms, bits(6) immr, boolean immediate, integer M)">DecodeBitMasks</a>(imm13&lt;12&gt;, imm13&lt;5:0&gt;, imm13&lt;11:6&gt;, TRUE, 64);</line>
<line></line>
<line>    // Check for 8 bit immediates</line>
<line>    if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(imm&lt;7:0&gt;) then</line>
<line>        // Check for 'ffffffffffffffxy' or '00000000000000xy'</line>
<line>        if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(imm&lt;63:7&gt;) || <a link="impl-shared.IsOnes.1" file="shared_pseudocode.xml" hover="function: boolean IsOnes(bits(N) x)">IsOnes</a>(imm&lt;63:7&gt;) then</line>
<line>            return FALSE;</line>
<line></line>
<line>        // Check for 'ffffffxyffffffxy' or '000000xy000000xy'</line>
<line>        if imm&lt;63:32&gt; == imm&lt;31:0&gt; &amp;&amp; (<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(imm&lt;31:7&gt;) || <a link="impl-shared.IsOnes.1" file="shared_pseudocode.xml" hover="function: boolean IsOnes(bits(N) x)">IsOnes</a>(imm&lt;31:7&gt;)) then</line>
<line>            return FALSE;</line>
<line></line>
<line>        // Check for 'ffxyffxyffxyffxy' or '00xy00xy00xy00xy'</line>
<line>        if (imm&lt;63:32&gt; == imm&lt;31:0&gt; &amp;&amp; imm&lt;31:16&gt; == imm&lt;15:0&gt; &amp;&amp;</line>
<line>              (<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(imm&lt;15:7&gt;) || <a link="impl-shared.IsOnes.1" file="shared_pseudocode.xml" hover="function: boolean IsOnes(bits(N) x)">IsOnes</a>(imm&lt;15:7&gt;))) then</line>
<line>            return FALSE;</line>
<line></line>
<line>        // Check for 'xyxyxyxyxyxyxyxy'</line>
<line>        if imm&lt;63:32&gt; == imm&lt;31:0&gt; &amp;&amp; imm&lt;31:16&gt; == imm&lt;15:0&gt; &amp;&amp; (imm&lt;15:8&gt; == imm&lt;7:0&gt;) then</line>
<line>            return FALSE;</line>
<line></line>
<line>    // Check for 16 bit immediates</line>
<line>    else</line>
<line>        // Check for 'ffffffffffffxy00' or '000000000000xy00'</line>
<line>        if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(imm&lt;63:15&gt;) || <a link="impl-shared.IsOnes.1" file="shared_pseudocode.xml" hover="function: boolean IsOnes(bits(N) x)">IsOnes</a>(imm&lt;63:15&gt;) then</line>
<line>            return FALSE;</line>
<line></line>
<line>        // Check for 'ffffxy00ffffxy00' or '0000xy000000xy00'</line>
<line>        if imm&lt;63:32&gt; == imm&lt;31:0&gt; &amp;&amp; (<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(imm&lt;31:7&gt;) || <a link="impl-shared.IsOnes.1" file="shared_pseudocode.xml" hover="function: boolean IsOnes(bits(N) x)">IsOnes</a>(imm&lt;31:7&gt;)) then</line>
<line>            return FALSE;</line>
<line></line>
<line>        // Check for 'xy00xy00xy00xy00'</line>
<line>        if imm&lt;63:32&gt; == imm&lt;31:0&gt; &amp;&amp; imm&lt;31:16&gt; == imm&lt;15:0&gt; then</line>
<line>            return FALSE;</line>
<line></line>
<line>    return TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/SetPSTATE_SM" mylink="aarch64.functions.sve.SetPSTATE_SM" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SetPSTATE_SM()</line>
<line>// ==============</line>
<line></line>
<line link="impl-aarch64.SetPSTATE_SM.1" hover="function: SetPSTATE_SM(bit value)" conts="SetPSTATE_SM"><anchor link="impl-aarch64.SetPSTATE_SM.1" hover="function: SetPSTATE_SM(bit value)">SetPSTATE_SM</anchor>(bit value)</line>
<line>    if PSTATE.SM != value then</line>
<line>        <a link="impl-aarch64.ResetSVEState.0" file="shared_pseudocode.xml" hover="function: ResetSVEState()">ResetSVEState</a>();</line>
<line>        PSTATE.SM = value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/SetPSTATE_SVCR" mylink="aarch64.functions.sve.SetPSTATE_SVCR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SetPSTATE_SVCR</line>
<line>// ==============</line>
<line></line>
<line link="impl-aarch64.SetPSTATE_SVCR.1" hover="function: SetPSTATE_SVCR(bits(32) svcr)" conts="SetPSTATE_SVCR"><anchor link="impl-aarch64.SetPSTATE_SVCR.1" hover="function: SetPSTATE_SVCR(bits(32) svcr)">SetPSTATE_SVCR</anchor>(bits(32) svcr)</line>
<line>    <a link="impl-aarch64.SetPSTATE_SM.1" file="shared_pseudocode.xml" hover="function: SetPSTATE_SM(bit value)">SetPSTATE_SM</a>(svcr&lt;0&gt;);</line>
<line>    <a link="impl-aarch64.SetPSTATE_ZA.1" file="shared_pseudocode.xml" hover="function: SetPSTATE_ZA(bit value)">SetPSTATE_ZA</a>(svcr&lt;1&gt;);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/SetPSTATE_ZA" mylink="aarch64.functions.sve.SetPSTATE_ZA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SetPSTATE_ZA()</line>
<line>// ==============</line>
<line></line>
<line link="impl-aarch64.SetPSTATE_ZA.1" hover="function: SetPSTATE_ZA(bit value)" conts="SetPSTATE_ZA"><anchor link="impl-aarch64.SetPSTATE_ZA.1" hover="function: SetPSTATE_ZA(bit value)">SetPSTATE_ZA</anchor>(bit value)</line>
<line>    if PSTATE.ZA != value then</line>
<line>        <a link="impl-aarch64.ResetSMEState.0" file="shared_pseudocode.xml" hover="function: ResetSMEState()">ResetSMEState</a>();</line>
<line>        PSTATE.ZA = value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/ShiftSat" mylink="aarch64.functions.sve.ShiftSat" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ShiftSat()</line>
<line>// ==========</line>
<line></line>
<line link="impl-aarch64.ShiftSat.2" hover="function: integer ShiftSat(integer shift, integer esize)" conts="ShiftSat">integer <anchor link="impl-aarch64.ShiftSat.2" hover="function: integer ShiftSat(integer shift, integer esize)">ShiftSat</anchor>(integer shift, integer esize)</line>
<line>    if shift &gt; esize+1 then return esize+1;</line>
<line>    elsif shift &lt; -(esize+1) then return -(esize+1);</line>
<line>    return shift;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/SupportedPowerTwoSVL" mylink="aarch64.functions.sve.SupportedPowerTwoSVL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SupportedPowerTwoSVL()</line>
<line>// ======================</line>
<line>// Return an IMPLEMENTATION DEFINED specific value</line>
<line>// returns TRUE if SVL is supported and is a power of two, FALSE otherwise</line>
<line></line>
<line link="impl-aarch64.SupportedPowerTwoSVL.1" hover="function: boolean SupportedPowerTwoSVL(integer nbits)" conts="SupportedPowerTwoSVL">boolean <anchor link="impl-aarch64.SupportedPowerTwoSVL.1" hover="function: boolean SupportedPowerTwoSVL(integer nbits)">SupportedPowerTwoSVL</anchor>(integer nbits);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/System" mylink="aarch64.functions.sve.System" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="MAX_VL" hover="constant integer MAX_VL = 2048" conts="MAX_VL">constant integer <anchor link="MAX_VL" hover="constant integer MAX_VL = 2048">MAX_VL</anchor> = 2048;</line>
<line link="MAX_PL" hover="constant integer MAX_PL = 256" conts="MAX_PL">constant integer <anchor link="MAX_PL" hover="constant integer MAX_PL = 256">MAX_PL</anchor> = 256;</line>
<line link="ZT0_LEN" hover="constant integer ZT0_LEN = 512" conts="ZT0_LEN">constant integer <anchor link="ZT0_LEN" hover="constant integer ZT0_LEN = 512">ZT0_LEN</anchor> =  512;</line>
<line>bits(<a link="MAX_PL" file="shared_pseudocode.xml" hover="constant integer MAX_PL = 256">MAX_PL</a>) _FFR;</line>
<line></line>
<line>array bits(<a link="MAX_VL" file="shared_pseudocode.xml" hover="constant integer MAX_VL = 2048">MAX_VL</a>) _Z[0..31];</line>
<line></line>
<line>array bits(<a link="MAX_PL" file="shared_pseudocode.xml" hover="constant integer MAX_PL = 256">MAX_PL</a>) _P[0..15];</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sve/Z" mylink="aarch64.functions.sve.Z" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Z[] - non-assignment form</line>
<line>// =========================</line>
<line></line>
<line link="impl-aarch64.Z.read.2" hover="accessor: bits(width) Z[integer n, integer width]" conts="Z">bits(width) <anchor link="impl-aarch64.Z.read.2" hover="accessor: bits(width) Z[integer n, integer width]">Z</anchor>[integer n, integer width]</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt;= 31;</line>
<line>    assert width == <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;</line>
<line>    return _Z[n]&lt;width-1:0&gt;;</line>
<line></line>
<line>// Z[] - assignment form</line>
<line>// =====================</line>
<line></line>
<line link="impl-aarch64.Z.write.2" hover="accessor: Z[integer n, integer width] = bits(width) value" conts="Z"><anchor link="impl-aarch64.Z.write.2" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</anchor>[integer n, integer width] = bits(width) value</line>
<line>    assert n &gt;= 0 &amp;&amp; n &lt;= 31;</line>
<line>    assert width == <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;</line>
<line>    if <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_SVEZEROUPPER" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_SVEZEROUPPER</a>) then</line>
<line>        _Z[n] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(value, <a link="MAX_VL" file="shared_pseudocode.xml" hover="constant integer MAX_VL = 2048">MAX_VL</a>);</line>
<line>    else</line>
<line>        _Z[n]&lt;width-1:0&gt; = value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sysregisters/CNTKCTL" mylink="aarch64.functions.sysregisters.CNTKCTL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CNTKCTL[] - non-assignment form</line>
<line>// ===============================</line>
<line></line>
<line link="impl-aarch64.CNTKCTL.read.0" hover="accessor: CNTKCTLType CNTKCTL[]" conts="CNTKCTL">CNTKCTLType <anchor link="impl-aarch64.CNTKCTL.read.0" hover="accessor: CNTKCTLType CNTKCTL[]">CNTKCTL</anchor>[]</line>
<line>    bits(64) r;</line>
<line>    if <a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>        r = CNTHCTL_EL2;</line>
<line>        return r;</line>
<line>    r = CNTKCTL_EL1;</line>
<line>    return r;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sysregisters/CNTKCTLType" mylink="aarch64.functions.sysregisters.CNTKCTLType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="CNTKCTLType" hover="type CNTKCTLType" conts="CNTKCTLType">type <anchor link="CNTKCTLType" hover="type CNTKCTLType">CNTKCTLType</anchor>;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sysregisters/CPACR" mylink="aarch64.functions.sysregisters.CPACR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CPACR[] - non-assignment form</line>
<line>// =============================</line>
<line></line>
<line link="impl-aarch64.CPACR.read.0" hover="accessor: CPACRType CPACR[]" conts="CPACR">CPACRType <anchor link="impl-aarch64.CPACR.read.0" hover="accessor: CPACRType CPACR[]">CPACR</anchor>[]</line>
<line>    bits(64) r;</line>
<line>    if <a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>        r = CPTR_EL2;</line>
<line>        return r;</line>
<line>    r = CPACR_EL1;</line>
<line>    return r;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sysregisters/CPACRType" mylink="aarch64.functions.sysregisters.CPACRType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="CPACRType" hover="type CPACRType" conts="CPACRType">type <anchor link="CPACRType" hover="type CPACRType">CPACRType</anchor>;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sysregisters/ELR" mylink="aarch64.functions.sysregisters.ELR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ELR[] - non-assignment form</line>
<line>// ===========================</line>
<line></line>
<line link="impl-aarch64.ELR.read.1" hover="accessor: bits(64) ELR[bits(2) el]" conts="ELR">bits(64) <anchor link="impl-aarch64.ELR.read.1" hover="accessor: bits(64) ELR[bits(2) el]">ELR</anchor>[bits(2) el]</line>
<line>    bits(64) r;</line>
<line>    case el of</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>  r = ELR_EL1;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>  r = ELR_EL2;</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>  r = ELR_EL3;</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>    return r;</line>
<line></line>
<line>// ELR[] - non-assignment form</line>
<line>// ===========================</line>
<line></line>
<line link="impl-aarch64.ELR.read.0" hover="accessor: bits(64) ELR[]" conts="ELR">bits(64) <anchor link="impl-aarch64.ELR.read.0" hover="accessor: bits(64) ELR[]">ELR</anchor>[]</line>
<line>    assert PSTATE.EL != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;</line>
<line>    return <a link="impl-aarch64.ELR.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) ELR[bits(2) el]">ELR</a>[PSTATE.EL];</line>
<line></line>
<line>// ELR[] - assignment form</line>
<line>// =======================</line>
<line></line>
<line link="impl-aarch64.ELR.write.1" hover="accessor: ELR[bits(2) el] = bits(64) value" conts="ELR"><anchor link="impl-aarch64.ELR.write.1" hover="accessor: ELR[bits(2) el] = bits(64) value">ELR</anchor>[bits(2) el] = bits(64) value</line>
<line>    bits(64) r = value;</line>
<line>    case el of</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>  ELR_EL1 = r;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>  ELR_EL2 = r;</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>  ELR_EL3 = r;</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>    return;</line>
<line></line>
<line>// ELR[] - assignment form</line>
<line>// =======================</line>
<line></line>
<line link="impl-aarch64.ELR.write.0" hover="accessor: ELR[] = bits(64) value" conts="ELR"><anchor link="impl-aarch64.ELR.write.0" hover="accessor: ELR[] = bits(64) value">ELR</anchor>[] = bits(64) value</line>
<line>    assert PSTATE.EL != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;</line>
<line>    <a link="impl-aarch64.ELR.write.1" file="shared_pseudocode.xml" hover="accessor: ELR[bits(2) el] = bits(64) value">ELR</a>[PSTATE.EL] = value;</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sysregisters/ESR" mylink="aarch64.functions.sysregisters.ESR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ESR[] - non-assignment form</line>
<line>// ===========================</line>
<line></line>
<line link="impl-aarch64.ESR.read.1" hover="accessor: ESRType ESR[bits(2) regime]" conts="ESR">ESRType <anchor link="impl-aarch64.ESR.read.1" hover="accessor: ESRType ESR[bits(2) regime]">ESR</anchor>[bits(2) regime]</line>
<line>    bits(64) r;</line>
<line>    case regime of</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>  r = ESR_EL1;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>  r = ESR_EL2;</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>  r = ESR_EL3;</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>    return r;</line>
<line></line>
<line>// ESR[] - non-assignment form</line>
<line>// ===========================</line>
<line></line>
<line link="impl-aarch64.ESR.read.0" hover="accessor: ESRType ESR[]" conts="ESR">ESRType <anchor link="impl-aarch64.ESR.read.0" hover="accessor: ESRType ESR[]">ESR</anchor>[]</line>
<line>    return <a link="impl-aarch64.ESR.read.1" file="shared_pseudocode.xml" hover="accessor: ESRType ESR[bits(2) regime]">ESR</a>[<a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>()];</line>
<line></line>
<line>// ESR[] - assignment form</line>
<line>// =======================</line>
<line></line>
<line link="impl-aarch64.ESR.write.1" hover="accessor: ESR[bits(2) regime] = ESRType value" conts="ESR"><anchor link="impl-aarch64.ESR.write.1" hover="accessor: ESR[bits(2) regime] = ESRType value">ESR</anchor>[bits(2) regime] = <a link="ESRType" file="shared_pseudocode.xml" hover="type ESRType">ESRType</a> value</line>
<line>    bits(64) r = value;</line>
<line>    case regime of</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>  ESR_EL1 = r;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>  ESR_EL2 = r;</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>  ESR_EL3 = r;</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>    return;</line>
<line></line>
<line>// ESR[] - assignment form</line>
<line>// =======================</line>
<line></line>
<line link="impl-aarch64.ESR.write.0" hover="accessor: ESR[] = ESRType value" conts="ESR"><anchor link="impl-aarch64.ESR.write.0" hover="accessor: ESR[] = ESRType value">ESR</anchor>[] = <a link="ESRType" file="shared_pseudocode.xml" hover="type ESRType">ESRType</a> value</line>
<line>    <a link="impl-aarch64.ESR.write.1" file="shared_pseudocode.xml" hover="accessor: ESR[bits(2) regime] = ESRType value">ESR</a>[<a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>()] = value;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sysregisters/ESRType" mylink="aarch64.functions.sysregisters.ESRType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="ESRType" hover="type ESRType" conts="ESRType">type <anchor link="ESRType" hover="type ESRType">ESRType</anchor>;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sysregisters/FAR" mylink="aarch64.functions.sysregisters.FAR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FAR[] - non-assignment form</line>
<line>// ===========================</line>
<line></line>
<line link="impl-aarch64.FAR.read.1" hover="accessor: bits(64) FAR[bits(2) regime]" conts="FAR">bits(64) <anchor link="impl-aarch64.FAR.read.1" hover="accessor: bits(64) FAR[bits(2) regime]">FAR</anchor>[bits(2) regime]</line>
<line>    bits(64) r;</line>
<line>    case regime of</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>  r = FAR_EL1;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>  r = FAR_EL2;</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>  r = FAR_EL3;</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>    return r;</line>
<line></line>
<line>// FAR[] - non-assignment form</line>
<line>// ===========================</line>
<line></line>
<line link="impl-aarch64.FAR.read.0" hover="accessor: bits(64) FAR[]" conts="FAR">bits(64) <anchor link="impl-aarch64.FAR.read.0" hover="accessor: bits(64) FAR[]">FAR</anchor>[]</line>
<line>    return <a link="impl-aarch64.FAR.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) FAR[bits(2) regime]">FAR</a>[<a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>()];</line>
<line></line>
<line>// FAR[] - assignment form</line>
<line>// =======================</line>
<line></line>
<line link="impl-aarch64.FAR.write.1" hover="accessor: FAR[bits(2) regime] = bits(64) value" conts="FAR"><anchor link="impl-aarch64.FAR.write.1" hover="accessor: FAR[bits(2) regime] = bits(64) value">FAR</anchor>[bits(2) regime] = bits(64) value</line>
<line>    bits(64) r = value;</line>
<line>    case regime of</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>  FAR_EL1 = r;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>  FAR_EL2 = r;</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>  FAR_EL3 = r;</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>    return;</line>
<line></line>
<line>// FAR[] - assignment form</line>
<line>// =======================</line>
<line></line>
<line link="impl-aarch64.FAR.write.0" hover="accessor: FAR[] = bits(64) value" conts="FAR"><anchor link="impl-aarch64.FAR.write.0" hover="accessor: FAR[] = bits(64) value">FAR</anchor>[] = bits(64) value</line>
<line>    <a link="impl-aarch64.FAR.write.1" file="shared_pseudocode.xml" hover="accessor: FAR[bits(2) regime] = bits(64) value">FAR</a>[<a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>()] = value;</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sysregisters/SCTLR" mylink="aarch64.functions.sysregisters.SCTLR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SCTLR[] - non-assignment form</line>
<line>// =============================</line>
<line></line>
<line link="impl-aarch64.SCTLR.read.1" hover="accessor: SCTLRType SCTLR[bits(2) regime]" conts="SCTLR">SCTLRType <anchor link="impl-aarch64.SCTLR.read.1" hover="accessor: SCTLRType SCTLR[bits(2) regime]">SCTLR</anchor>[bits(2) regime]</line>
<line>    bits(64) r;</line>
<line>    case regime of</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>  r = SCTLR_EL1;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>  r = SCTLR_EL2;</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>  r = SCTLR_EL3;</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>    return r;</line>
<line></line>
<line>// SCTLR[] - non-assignment form</line>
<line>// =============================</line>
<line></line>
<line link="impl-aarch64.SCTLR.read.0" hover="accessor: SCTLRType SCTLR[]" conts="SCTLR">SCTLRType <anchor link="impl-aarch64.SCTLR.read.0" hover="accessor: SCTLRType SCTLR[]">SCTLR</anchor>[]</line>
<line>    return <a link="impl-aarch64.SCTLR.read.1" file="shared_pseudocode.xml" hover="accessor: SCTLRType SCTLR[bits(2) regime]">SCTLR</a>[<a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>()];</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sysregisters/SCTLRType" mylink="aarch64.functions.sysregisters.SCTLRType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="SCTLRType" hover="type SCTLRType" conts="SCTLRType">type <anchor link="SCTLRType" hover="type SCTLRType">SCTLRType</anchor>;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/sysregisters/VBAR" mylink="aarch64.functions.sysregisters.VBAR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// VBAR[] - non-assignment form</line>
<line>// ============================</line>
<line></line>
<line link="impl-aarch64.VBAR.read.1" hover="accessor: bits(64) VBAR[bits(2) regime]" conts="VBAR">bits(64) <anchor link="impl-aarch64.VBAR.read.1" hover="accessor: bits(64) VBAR[bits(2) regime]">VBAR</anchor>[bits(2) regime]</line>
<line>    bits(64) r;</line>
<line>    case regime of</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>  r = VBAR_EL1;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>  r = VBAR_EL2;</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>  r = VBAR_EL3;</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>    return r;</line>
<line></line>
<line>// VBAR[] - non-assignment form</line>
<line>// ============================</line>
<line></line>
<line link="impl-aarch64.VBAR.read.0" hover="accessor: bits(64) VBAR[]" conts="VBAR">bits(64) <anchor link="impl-aarch64.VBAR.read.0" hover="accessor: bits(64) VBAR[]">VBAR</anchor>[]</line>
<line>    return <a link="impl-aarch64.VBAR.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) VBAR[bits(2) regime]">VBAR</a>[<a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>()];</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/AArch64.AllocationTagAccessIsEnabled" mylink="aarch64.functions.system.AArch64.AllocationTagAccessIsEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.AllocationTagAccessIsEnabled()</line>
<line>// ======================================</line>
<line>// Check whether access to Allocation Tags is enabled.</line>
<line></line>
<line link="AArch64.AllocationTagAccessIsEnabled.1" hover="function: boolean AArch64.AllocationTagAccessIsEnabled(bits(2) el)" conts="AArch64.AllocationTagAccessIsEnabled">boolean <anchor link="AArch64.AllocationTagAccessIsEnabled.1" hover="function: boolean AArch64.AllocationTagAccessIsEnabled(bits(2) el)">AArch64.AllocationTagAccessIsEnabled</anchor>(bits(2) el)</line>
<line>    if SCR_EL3.ATA == '0' &amp;&amp; el IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>} then</line>
<line>        return FALSE;</line>
<line>    if HCR_EL2.ATA == '0' &amp;&amp; el IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.&lt;E2H,TGE&gt; != '11' then</line>
<line>        return FALSE;</line>
<line></line>
<line>    <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime = <a link="impl-shared.TranslationRegime.1" file="shared_pseudocode.xml" hover="function: Regime TranslationRegime(bits(2) el)">TranslationRegime</a>(el);</line>
<line>    case regime of</line>
<line>        when <a link="Regime_EL3" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL3</a>  return SCTLR_EL3.ATA == '1';</line>
<line>        when <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>  return SCTLR_EL2.ATA == '1';</line>
<line>        when <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a> return if el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then SCTLR_EL2.ATA0 == '1' else SCTLR_EL2.ATA == '1';</line>
<line>        when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> return if el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then SCTLR_EL1.ATA0 == '1' else SCTLR_EL1.ATA == '1';</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/AArch64.CheckSystemAccess" mylink="aarch64.functions.system.AArch64.CheckSystemAccess" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.CheckSystemAccess()</line>
<line>// ===========================</line>
<line></line>
<line link="AArch64.CheckSystemAccess.7" hover="function: AArch64.CheckSystemAccess(bits(2) op0, bits(3) op1, bits(4) crn, bits(4) crm, bits(3) op2, bits(5) rt, bit read)" conts="AArch64.CheckSystemAccess"><anchor link="AArch64.CheckSystemAccess.7" hover="function: AArch64.CheckSystemAccess(bits(2) op0, bits(3) op1, bits(4) crn, bits(4) crm, bits(3) op2, bits(5) rt, bit read)">AArch64.CheckSystemAccess</anchor>(bits(2) op0, bits(3) op1, bits(4) crn,</line>
<line>                          bits(4) crm, bits(3) op2, bits(5) rt, bit read)</line>
<line>    if <a link="impl-shared.HaveBTIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveBTIExt()">HaveBTIExt</a>() then</line>
<line>        <a link="impl-shared.BranchTargetCheck.0" file="shared_pseudocode.xml" hover="function: BranchTargetCheck()">BranchTargetCheck</a>();</line>
<line></line>
<line>    if (<a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0 &amp;&amp;</line>
<line>          !<a link="impl-aarch64.CheckTransactionalSystemAccess.6" file="shared_pseudocode.xml" hover="function: boolean CheckTransactionalSystemAccess(bits(2) op0, bits(3) op1, bits(4) crn, bits(4) crm, bits(3) op2, bit read)">CheckTransactionalSystemAccess</a>(op0, op1, crn, crm, op2, read)) then</line>
<line>        <a link="impl-aarch64.FailTransaction.2" file="shared_pseudocode.xml" hover="function: FailTransaction(TMFailure cause, boolean retry)">FailTransaction</a>(<a link="TMFailure_ERR" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_ERR</a>, FALSE);</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/AArch64.ChooseNonExcludedTag" mylink="aarch64.functions.system.AArch64.ChooseNonExcludedTag" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ChooseNonExcludedTag()</line>
<line>// ==============================</line>
<line>// Return a tag derived from the start and the offset values, excluding</line>
<line>// any tags in the given mask.</line>
<line></line>
<line link="AArch64.ChooseNonExcludedTag.3" hover="function: bits(4) AArch64.ChooseNonExcludedTag(bits(4) tag_in, bits(4) offset_in, bits(16) exclude)" conts="AArch64.ChooseNonExcludedTag">bits(4) <anchor link="AArch64.ChooseNonExcludedTag.3" hover="function: bits(4) AArch64.ChooseNonExcludedTag(bits(4) tag_in, bits(4) offset_in, bits(16) exclude)">AArch64.ChooseNonExcludedTag</anchor>(bits(4) tag_in, bits(4) offset_in, bits(16) exclude)</line>
<line>    bits(4) tag = tag_in;</line>
<line>    bits(4) offset = offset_in;</line>
<line></line>
<line>    if <a link="impl-shared.IsOnes.1" file="shared_pseudocode.xml" hover="function: boolean IsOnes(bits(N) x)">IsOnes</a>(exclude) then</line>
<line>        return '0000';</line>
<line></line>
<line>    if offset == '0000' then</line>
<line>        while exclude&lt;<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(tag)&gt; == '1' do</line>
<line>            tag = tag + '0001';</line>
<line></line>
<line>    while offset != '0000' do</line>
<line>        offset = offset - '0001';</line>
<line>        tag = tag + '0001';</line>
<line>        while exclude&lt;<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(tag)&gt; == '1' do</line>
<line>            tag = tag + '0001';</line>
<line></line>
<line>    return tag;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/AArch64.ExecutingBROrBLROrRetInstr" mylink="aarch64.functions.system.AArch64.ExecutingBROrBLROrRetInstr" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ExecutingBROrBLROrRetInstr()</line>
<line>// ====================================</line>
<line>// Returns TRUE if current instruction is a BR, BLR, RET, B[L]RA[B][Z], or RETA[B].</line>
<line></line>
<line link="AArch64.ExecutingBROrBLROrRetInstr.0" hover="function: boolean AArch64.ExecutingBROrBLROrRetInstr()" conts="AArch64.ExecutingBROrBLROrRetInstr">boolean <anchor link="AArch64.ExecutingBROrBLROrRetInstr.0" hover="function: boolean AArch64.ExecutingBROrBLROrRetInstr()">AArch64.ExecutingBROrBLROrRetInstr</anchor>()</line>
<line>    if !<a link="impl-shared.HaveBTIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveBTIExt()">HaveBTIExt</a>() then return FALSE;</line>
<line></line>
<line>    instr = <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>();</line>
<line>    if instr&lt;31:25&gt; == '1101011' &amp;&amp; instr&lt;20:16&gt; == '11111' then</line>
<line>        opc = instr&lt;24:21&gt;;</line>
<line>        return opc != '0101';</line>
<line>    else</line>
<line>        return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/AArch64.ExecutingBTIInstr" mylink="aarch64.functions.system.AArch64.ExecutingBTIInstr" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ExecutingBTIInstr()</line>
<line>// ===========================</line>
<line>// Returns TRUE if current instruction is a BTI.</line>
<line></line>
<line link="AArch64.ExecutingBTIInstr.0" hover="function: boolean AArch64.ExecutingBTIInstr()" conts="AArch64.ExecutingBTIInstr">boolean <anchor link="AArch64.ExecutingBTIInstr.0" hover="function: boolean AArch64.ExecutingBTIInstr()">AArch64.ExecutingBTIInstr</anchor>()</line>
<line>    if !<a link="impl-shared.HaveBTIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveBTIExt()">HaveBTIExt</a>() then return FALSE;</line>
<line></line>
<line>    instr = <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>();</line>
<line>    if instr&lt;31:22&gt; == '1101010100' &amp;&amp; instr&lt;21:12&gt; == '0000110010' &amp;&amp; instr&lt;4:0&gt; == '11111' then</line>
<line>        CRm  = instr&lt;11:8&gt;;</line>
<line>        op2  = instr&lt;7:5&gt;;</line>
<line>        return (CRm == '0100' &amp;&amp; op2&lt;0&gt; == '0');</line>
<line>    else</line>
<line>        return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/AArch64.ExecutingERETInstr" mylink="aarch64.functions.system.AArch64.ExecutingERETInstr" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ExecutingERETInstr()</line>
<line>// ============================</line>
<line>// Returns TRUE if current instruction is ERET.</line>
<line></line>
<line link="AArch64.ExecutingERETInstr.0" hover="function: boolean AArch64.ExecutingERETInstr()" conts="AArch64.ExecutingERETInstr">boolean <anchor link="AArch64.ExecutingERETInstr.0" hover="function: boolean AArch64.ExecutingERETInstr()">AArch64.ExecutingERETInstr</anchor>()</line>
<line>    instr = <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>();</line>
<line>    return instr&lt;31:12&gt; == '11010110100111110000';</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/AArch64.ImpDefSysInstr" mylink="aarch64.functions.system.AArch64.ImpDefSysInstr" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ImpDefSysInstr()</line>
<line>// ========================</line>
<line>// Execute an implementation-defined system instruction with write (source operand).</line>
<line></line>
<line link="AArch64.ImpDefSysInstr.6" hover="function: AArch64.ImpDefSysInstr(integer el, bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2, integer t)" conts="AArch64.ImpDefSysInstr"><anchor link="AArch64.ImpDefSysInstr.6" hover="function: AArch64.ImpDefSysInstr(integer el, bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2, integer t)">AArch64.ImpDefSysInstr</anchor>(integer el, bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2, integer t);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/AArch64.ImpDefSysInstr128" mylink="aarch64.functions.system.AArch64.ImpDefSysInstr128" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ImpDefSysInstr128()</line>
<line>// ===========================</line>
<line>// Execute an implementation-defined system instruction with write (128-bit source operand).</line>
<line></line>
<line link="AArch64.ImpDefSysInstr128.7" hover="function: AArch64.ImpDefSysInstr128(integer el, bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2, integer t, integer t2)" conts="AArch64.ImpDefSysInstr128"><anchor link="AArch64.ImpDefSysInstr128.7" hover="function: AArch64.ImpDefSysInstr128(integer el, bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2, integer t, integer t2)">AArch64.ImpDefSysInstr128</anchor>(integer el, bits(3) op1, bits(4) CRn,</line>
<line>                          bits(4) CRm, bits(3) op2,</line>
<line>                          integer t, integer t2);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/AArch64.ImpDefSysInstrWithResult" mylink="aarch64.functions.system.AArch64.ImpDefSysInstrWithResult" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ImpDefSysInstrWithResult()</line>
<line>// ==================================</line>
<line>// Execute an implementation-defined system instruction with read (result operand).</line>
<line></line>
<line link="AArch64.ImpDefSysInstrWithResult.5" hover="function: AArch64.ImpDefSysInstrWithResult(integer el, bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2)" conts="AArch64.ImpDefSysInstrWithResult"><anchor link="AArch64.ImpDefSysInstrWithResult.5" hover="function: AArch64.ImpDefSysInstrWithResult(integer el, bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2)">AArch64.ImpDefSysInstrWithResult</anchor>(integer el, bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/AArch64.ImpDefSysRegRead" mylink="aarch64.functions.system.AArch64.ImpDefSysRegRead" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ImpDefSysRegRead()</line>
<line>// ==========================</line>
<line>// Read from an implementation-defined System register and write the contents of the register</line>
<line>// to X[t].</line>
<line></line>
<line link="AArch64.ImpDefSysRegRead.6" hover="function: AArch64.ImpDefSysRegRead(bits(2) op0, bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2, integer t)" conts="AArch64.ImpDefSysRegRead"><anchor link="AArch64.ImpDefSysRegRead.6" hover="function: AArch64.ImpDefSysRegRead(bits(2) op0, bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2, integer t)">AArch64.ImpDefSysRegRead</anchor>(bits(2) op0, bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2,</line>
<line>                         integer t);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/AArch64.ImpDefSysRegRead128" mylink="aarch64.functions.system.AArch64.ImpDefSysRegRead128" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ImpDefSysRegRead128()</line>
<line>// =============================</line>
<line>// Read from an 128-bit implementation-defined System register</line>
<line>// and write the contents of the register to X[t], X[t+1].</line>
<line></line>
<line link="AArch64.ImpDefSysRegRead128.7" hover="function: AArch64.ImpDefSysRegRead128(bits(2) op0, bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2, integer t, integer t2)" conts="AArch64.ImpDefSysRegRead128"><anchor link="AArch64.ImpDefSysRegRead128.7" hover="function: AArch64.ImpDefSysRegRead128(bits(2) op0, bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2, integer t, integer t2)">AArch64.ImpDefSysRegRead128</anchor>(bits(2) op0, bits(3) op1, bits(4) CRn,</line>
<line>                            bits(4) CRm, bits(3) op2,</line>
<line>                            integer t, integer t2);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/AArch64.ImpDefSysRegWrite" mylink="aarch64.functions.system.AArch64.ImpDefSysRegWrite" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ImpDefSysRegWrite()</line>
<line>// ===========================</line>
<line>// Write to an implementation-defined System register.</line>
<line></line>
<line link="AArch64.ImpDefSysRegWrite.6" hover="function: AArch64.ImpDefSysRegWrite(bits(2) op0, bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2, integer t)" conts="AArch64.ImpDefSysRegWrite"><anchor link="AArch64.ImpDefSysRegWrite.6" hover="function: AArch64.ImpDefSysRegWrite(bits(2) op0, bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2, integer t)">AArch64.ImpDefSysRegWrite</anchor>(bits(2) op0, bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2,</line>
<line>                          integer t);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/AArch64.ImpDefSysRegWrite128" mylink="aarch64.functions.system.AArch64.ImpDefSysRegWrite128" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ImpDefSysRegWrite128()</line>
<line>// ==============================</line>
<line>// Write the contents of X[t], X[t+1] to an 128-bit implementation-defined System register.</line>
<line></line>
<line link="AArch64.ImpDefSysRegWrite128.7" hover="function: AArch64.ImpDefSysRegWrite128(bits(2) op0, bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2, integer t, integer t2)" conts="AArch64.ImpDefSysRegWrite128"><anchor link="AArch64.ImpDefSysRegWrite128.7" hover="function: AArch64.ImpDefSysRegWrite128(bits(2) op0, bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2, integer t, integer t2)">AArch64.ImpDefSysRegWrite128</anchor>(bits(2) op0, bits(3) op1, bits(4) CRn,</line>
<line>                             bits(4) CRm, bits(3) op2,</line>
<line>                             integer t, integer t2);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/AArch64.NextRandomTagBit" mylink="aarch64.functions.system.AArch64.NextRandomTagBit" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.NextRandomTagBit()</line>
<line>// ==========================</line>
<line>// Generate a random bit suitable for generating a random Allocation Tag.</line>
<line></line>
<line link="AArch64.NextRandomTagBit.0" hover="function: bit AArch64.NextRandomTagBit()" conts="AArch64.NextRandomTagBit">bit <anchor link="AArch64.NextRandomTagBit.0" hover="function: bit AArch64.NextRandomTagBit()">AArch64.NextRandomTagBit</anchor>()</line>
<line>    assert GCR_EL1.RRND == '0';</line>
<line>    bits(16) lfsr = RGSR_EL1.SEED&lt;15:0&gt;;</line>
<line>    bit top = lfsr&lt;5&gt; EOR lfsr&lt;3&gt; EOR lfsr&lt;2&gt; EOR lfsr&lt;0&gt;;</line>
<line>    RGSR_EL1.SEED&lt;15:0&gt; = top:lfsr&lt;15:1&gt;;</line>
<line>    return top;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/AArch64.RandomTag" mylink="aarch64.functions.system.AArch64.RandomTag" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.RandomTag()</line>
<line>// ===================</line>
<line>// Generate a random Allocation Tag.</line>
<line></line>
<line link="AArch64.RandomTag.0" hover="function: bits(4) AArch64.RandomTag()" conts="AArch64.RandomTag">bits(4) <anchor link="AArch64.RandomTag.0" hover="function: bits(4) AArch64.RandomTag()">AArch64.RandomTag</anchor>()</line>
<line>    bits(4) tag;</line>
<line>    for i = 0 to 3</line>
<line>        tag&lt;i&gt; = <a link="AArch64.NextRandomTagBit.0" file="shared_pseudocode.xml" hover="function: bit AArch64.NextRandomTagBit()">AArch64.NextRandomTagBit</a>();</line>
<line>    return tag;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/AArch64.SysInstr" mylink="aarch64.functions.system.AArch64.SysInstr" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.SysInstr()</line>
<line>// ==================</line>
<line>// Execute a system instruction with write (source operand).</line>
<line></line>
<line link="AArch64.SysInstr.6" hover="function: AArch64.SysInstr(integer op0, integer op1, integer crn, integer crm, integer op2, integer t)" conts="AArch64.SysInstr"><anchor link="AArch64.SysInstr.6" hover="function: AArch64.SysInstr(integer op0, integer op1, integer crn, integer crm, integer op2, integer t)">AArch64.SysInstr</anchor>(integer op0, integer op1, integer crn, integer crm, integer op2, integer t);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/AArch64.SysInstrWithResult" mylink="aarch64.functions.system.AArch64.SysInstrWithResult" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.SysInstrWithResult()</line>
<line>// ============================</line>
<line>// Execute a system instruction with read (result operand).</line>
<line>// Writes the result of the instruction to X[t].</line>
<line></line>
<line link="AArch64.SysInstrWithResult.6" hover="function: AArch64.SysInstrWithResult(integer op0, integer op1, integer crn, integer crm, integer op2, integer t)" conts="AArch64.SysInstrWithResult"><anchor link="AArch64.SysInstrWithResult.6" hover="function: AArch64.SysInstrWithResult(integer op0, integer op1, integer crn, integer crm, integer op2, integer t)">AArch64.SysInstrWithResult</anchor>(integer op0, integer op1, integer crn, integer crm, integer op2,</line>
<line>                           integer t);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/AArch64.SysRegRead" mylink="aarch64.functions.system.AArch64.SysRegRead" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.SysRegRead()</line>
<line>// ====================</line>
<line>// Read from a System register and write the contents of the register to X[t].</line>
<line></line>
<line link="AArch64.SysRegRead.6" hover="function: AArch64.SysRegRead(integer op0, integer op1, integer crn, integer crm, integer op2, integer t)" conts="AArch64.SysRegRead"><anchor link="AArch64.SysRegRead.6" hover="function: AArch64.SysRegRead(integer op0, integer op1, integer crn, integer crm, integer op2, integer t)">AArch64.SysRegRead</anchor>(integer op0, integer op1, integer crn, integer crm, integer op2, integer t);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/AArch64.SysRegWrite" mylink="aarch64.functions.system.AArch64.SysRegWrite" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.SysRegWrite()</line>
<line>// =====================</line>
<line>// Write to a System register.</line>
<line></line>
<line link="AArch64.SysRegWrite.6" hover="function: AArch64.SysRegWrite(integer op0, integer op1, integer crn, integer crm, integer op2, integer t)" conts="AArch64.SysRegWrite"><anchor link="AArch64.SysRegWrite.6" hover="function: AArch64.SysRegWrite(integer op0, integer op1, integer crn, integer crm, integer op2, integer t)">AArch64.SysRegWrite</anchor>(integer op0, integer op1, integer crn, integer crm, integer op2, integer t);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/BTypeCompatible" mylink="aarch64.functions.system.BTypeCompatible" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>boolean BTypeCompatible;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/BTypeCompatible_BTI" mylink="aarch64.functions.system.BTypeCompatible_BTI" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BTypeCompatible_BTI</line>
<line>// ===================</line>
<line>// This function determines whether a given hint encoding is compatible with the current value of</line>
<line>// PSTATE.BTYPE. A value of TRUE here indicates a valid Branch Target Identification instruction.</line>
<line></line>
<line link="impl-aarch64.BTypeCompatible_BTI.1" hover="function: boolean BTypeCompatible_BTI(bits(2) hintcode)" conts="BTypeCompatible_BTI">boolean <anchor link="impl-aarch64.BTypeCompatible_BTI.1" hover="function: boolean BTypeCompatible_BTI(bits(2) hintcode)">BTypeCompatible_BTI</anchor>(bits(2) hintcode)</line>
<line>    case hintcode of</line>
<line>        when '00'</line>
<line>            return FALSE;</line>
<line>        when '01'</line>
<line>            return PSTATE.BTYPE != '11';</line>
<line>        when '10'</line>
<line>            return PSTATE.BTYPE != '10';</line>
<line>        when '11'</line>
<line>            return TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/BTypeCompatible_PACIXSP" mylink="aarch64.functions.system.BTypeCompatible_PACIXSP" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BTypeCompatible_PACIXSP()</line>
<line>// =========================</line>
<line>// Returns TRUE if PACIASP, PACIBSP instruction is implicit compatible with PSTATE.BTYPE,</line>
<line>// FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.BTypeCompatible_PACIXSP.0" hover="function: boolean BTypeCompatible_PACIXSP()" conts="BTypeCompatible_PACIXSP">boolean <anchor link="impl-aarch64.BTypeCompatible_PACIXSP.0" hover="function: boolean BTypeCompatible_PACIXSP()">BTypeCompatible_PACIXSP</anchor>()</line>
<line>    if PSTATE.BTYPE IN {'01', '10'} then</line>
<line>        return TRUE;</line>
<line>    elsif PSTATE.BTYPE == '11' then</line>
<line>        index = if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then 35 else 36;</line>
<line>        return <a link="impl-aarch64.SCTLR.read.0" file="shared_pseudocode.xml" hover="accessor: SCTLRType SCTLR[]">SCTLR</a>[]&lt;index&gt; == '0';</line>
<line>    else</line>
<line>        return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/BTypeNext" mylink="aarch64.functions.system.BTypeNext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>bits(2) BTypeNext;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/ChooseRandomNonExcludedTag" mylink="aarch64.functions.system.ChooseRandomNonExcludedTag" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ChooseRandomNonExcludedTag()</line>
<line>// ============================</line>
<line>// The ChooseRandomNonExcludedTag function is used when GCR_EL1.RRND == '1' to generate random</line>
<line>// Allocation Tags.</line>
<line>//</line>
<line>// The resulting Allocation Tag is selected from the set [0,15], excluding any Allocation Tag where</line>
<line>// exclude[tag_value] == 1. If 'exclude' is all Ones, the returned Allocation Tag is '0000'.</line>
<line>//</line>
<line>// This function is permitted to generate a non-deterministic selection from the set of non-excluded</line>
<line>// Allocation Tags. A reasonable implementation is described by the Pseudocode used when</line>
<line>// GCR_EL1.RRND is 0, but with a non-deterministic implementation of NextRandomTagBit().</line>
<line>// Implementations may choose to behave the same as GCR_EL1.RRND=0.</line>
<line>//</line>
<line>// This function can read RGSR_EL1 and/or write RGSR_EL1 to an IMPLEMENTATION DEFINED value.</line>
<line>// If it is not capable of writing RGSR_EL1.SEED[15:0] to zero from a previous non-zero</line>
<line>// RGSR_EL1.SEED value, it is IMPLEMENTATION DEFINED whether the randomness is significantly</line>
<line>// impacted if RGSR_EL1.SEED[15:0] is set to zero.</line>
<line></line>
<line link="impl-aarch64.ChooseRandomNonExcludedTag.1" hover="function: bits(4) ChooseRandomNonExcludedTag(bits(16) exclude_in)" conts="ChooseRandomNonExcludedTag">bits(4) <anchor link="impl-aarch64.ChooseRandomNonExcludedTag.1" hover="function: bits(4) ChooseRandomNonExcludedTag(bits(16) exclude_in)">ChooseRandomNonExcludedTag</anchor>(bits(16) exclude_in);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/InGuardedPage" mylink="aarch64.functions.system.InGuardedPage" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>boolean InGuardedPage;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/IsHCRXEL2Enabled" mylink="aarch64.functions.system.IsHCRXEL2Enabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsHCRXEL2Enabled()</line>
<line>// ==================</line>
<line>// Returns TRUE if access to HCRX_EL2 register is enabled, and FALSE otherwise.</line>
<line>// Indirect read of HCRX_EL2 returns 0 when access is not enabled.</line>
<line></line>
<line link="impl-aarch64.IsHCRXEL2Enabled.0" hover="function: boolean IsHCRXEL2Enabled()" conts="IsHCRXEL2Enabled">boolean <anchor link="impl-aarch64.IsHCRXEL2Enabled.0" hover="function: boolean IsHCRXEL2Enabled()">IsHCRXEL2Enabled</anchor>()</line>
<line>    if !<a link="impl-shared.HaveFeatHCX.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatHCX()">HaveFeatHCX</a>() then return FALSE;</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.HXEn == '0' then</line>
<line>        return FALSE;</line>
<line></line>
<line>    return <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>();</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/IsSCTLR2EL1Enabled" mylink="aarch64.functions.system.IsSCTLR2EL1Enabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsSCTLR2EL1Enabled()</line>
<line>// ====================</line>
<line>// Returns TRUE if access to SCTLR2_EL1 register is enabled, and FALSE otherwise.</line>
<line>// Indirect read of SCTLR2_EL1 returns 0 when access is not enabled.</line>
<line></line>
<line link="impl-aarch64.IsSCTLR2EL1Enabled.0" hover="function: boolean IsSCTLR2EL1Enabled()" conts="IsSCTLR2EL1Enabled">boolean <anchor link="impl-aarch64.IsSCTLR2EL1Enabled.0" hover="function: boolean IsSCTLR2EL1Enabled()">IsSCTLR2EL1Enabled</anchor>()</line>
<line>    if !<a link="impl-shared.HaveFeatSCTLR2.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatSCTLR2()">HaveFeatSCTLR2</a>() then return FALSE;</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.SCTLR2En == '0' then</line>
<line>        return FALSE;</line>
<line>    elsif (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; (!<a link="impl-aarch64.IsHCRXEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsHCRXEL2Enabled()">IsHCRXEL2Enabled</a>() || HCRX_EL2.SCTLR2En == '0')) then</line>
<line>        return FALSE;</line>
<line>    else</line>
<line>        return TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/IsSCTLR2EL2Enabled" mylink="aarch64.functions.system.IsSCTLR2EL2Enabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsSCTLR2EL2Enabled()</line>
<line>// ====================</line>
<line>// Returns TRUE if access to SCTLR2_EL2 register is enabled, and FALSE otherwise.</line>
<line>// Indirect read of SCTLR2_EL2 returns 0 when access is not enabled.</line>
<line></line>
<line link="impl-aarch64.IsSCTLR2EL2Enabled.0" hover="function: boolean IsSCTLR2EL2Enabled()" conts="IsSCTLR2EL2Enabled">boolean <anchor link="impl-aarch64.IsSCTLR2EL2Enabled.0" hover="function: boolean IsSCTLR2EL2Enabled()">IsSCTLR2EL2Enabled</anchor>()</line>
<line>    if !<a link="impl-shared.HaveFeatSCTLR2.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatSCTLR2()">HaveFeatSCTLR2</a>() then return FALSE;</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.SCTLR2En == '0' then</line>
<line>        return FALSE;</line>
<line></line>
<line>    return <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>();</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/IsTCR2EL1Enabled" mylink="aarch64.functions.system.IsTCR2EL1Enabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsTCR2EL1Enabled()</line>
<line>// ==================</line>
<line>// Returns TRUE if access to TCR2_EL1 register is enabled, and FALSE otherwise.</line>
<line>// Indirect read of TCR2_EL1 returns 0 when access is not enabled.</line>
<line></line>
<line link="impl-aarch64.IsTCR2EL1Enabled.0" hover="function: boolean IsTCR2EL1Enabled()" conts="IsTCR2EL1Enabled">boolean <anchor link="impl-aarch64.IsTCR2EL1Enabled.0" hover="function: boolean IsTCR2EL1Enabled()">IsTCR2EL1Enabled</anchor>()</line>
<line>    if !<a link="impl-shared.HaveFeatTCR2.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatTCR2()">HaveFeatTCR2</a>() then return FALSE;</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.TCR2En == '0' then</line>
<line>        return FALSE;</line>
<line>    elsif (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; (!<a link="impl-aarch64.IsHCRXEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsHCRXEL2Enabled()">IsHCRXEL2Enabled</a>() || HCRX_EL2.TCR2En == '0')) then</line>
<line>        return FALSE;</line>
<line>    else</line>
<line>        return TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/IsTCR2EL2Enabled" mylink="aarch64.functions.system.IsTCR2EL2Enabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsTCR2EL2Enabled()</line>
<line>// ==================</line>
<line>// Returns TRUE if access to TCR2_EL2 register is enabled, and FALSE otherwise.</line>
<line>// Indirect read of TCR2_EL2 returns 0 when access is not enabled.</line>
<line></line>
<line link="impl-aarch64.IsTCR2EL2Enabled.0" hover="function: boolean IsTCR2EL2Enabled()" conts="IsTCR2EL2Enabled">boolean <anchor link="impl-aarch64.IsTCR2EL2Enabled.0" hover="function: boolean IsTCR2EL2Enabled()">IsTCR2EL2Enabled</anchor>()</line>
<line>    if !<a link="impl-shared.HaveFeatTCR2.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatTCR2()">HaveFeatTCR2</a>() then return FALSE;</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.TCR2En == '0' then</line>
<line>        return FALSE;</line>
<line></line>
<line>    return <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>();</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/SetBTypeCompatible" mylink="aarch64.functions.system.SetBTypeCompatible" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SetBTypeCompatible()</line>
<line>// ====================</line>
<line>// Sets the value of BTypeCompatible global variable used by BTI</line>
<line></line>
<line link="impl-aarch64.SetBTypeCompatible.1" hover="function: SetBTypeCompatible(boolean x)" conts="SetBTypeCompatible"><anchor link="impl-aarch64.SetBTypeCompatible.1" hover="function: SetBTypeCompatible(boolean x)">SetBTypeCompatible</anchor>(boolean x)</line>
<line>    BTypeCompatible = x;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/SetBTypeNext" mylink="aarch64.functions.system.SetBTypeNext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SetBTypeNext()</line>
<line>// ==============</line>
<line>// Set the value of BTypeNext global variable used by BTI</line>
<line></line>
<line link="impl-aarch64.SetBTypeNext.1" hover="function: SetBTypeNext(bits(2) x)" conts="SetBTypeNext"><anchor link="impl-aarch64.SetBTypeNext.1" hover="function: SetBTypeNext(bits(2) x)">SetBTypeNext</anchor>(bits(2) x)</line>
<line>    BTypeNext = x;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system/SetInGuardedPage" mylink="aarch64.functions.system.SetInGuardedPage" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SetInGuardedPage()</line>
<line>// ==================</line>
<line>// Global state updated to denote if memory access is from a guarded page.</line>
<line></line>
<line link="impl-aarch64.SetInGuardedPage.1" hover="function: SetInGuardedPage(boolean guardedpage)" conts="SetInGuardedPage"><anchor link="impl-aarch64.SetInGuardedPage.1" hover="function: SetInGuardedPage(boolean guardedpage)">SetInGuardedPage</anchor>(boolean guardedpage)</line>
<line>    InGuardedPage = guardedpage;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system128/AArch64.SysInstr128" mylink="aarch64.functions.system128.AArch64.SysInstr128" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.SysInstr128()</line>
<line>// =====================</line>
<line>// Execute a system instruction with write (2 64-bit source operands).</line>
<line></line>
<line link="AArch64.SysInstr128.7" hover="function: AArch64.SysInstr128(integer op0, integer op1, integer crn, integer crm, integer op2, integer t, integer t2)" conts="AArch64.SysInstr128"><anchor link="AArch64.SysInstr128.7" hover="function: AArch64.SysInstr128(integer op0, integer op1, integer crn, integer crm, integer op2, integer t, integer t2)">AArch64.SysInstr128</anchor>(integer op0, integer op1, integer crn, integer crm,</line>
<line>                    integer op2, integer t, integer t2);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system128/AArch64.SysRegRead128" mylink="aarch64.functions.system128.AArch64.SysRegRead128" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.SysRegRead128()</line>
<line>// =======================</line>
<line>// Read from a 128-bit System register and write the contents of the register to X[t] and X[t2].</line>
<line></line>
<line link="AArch64.SysRegRead128.7" hover="function: AArch64.SysRegRead128(integer op0, integer op1, integer crn, integer crm, integer op2, integer t, integer t2)" conts="AArch64.SysRegRead128"><anchor link="AArch64.SysRegRead128.7" hover="function: AArch64.SysRegRead128(integer op0, integer op1, integer crn, integer crm, integer op2, integer t, integer t2)">AArch64.SysRegRead128</anchor>(integer op0, integer op1, integer crn, integer crm,</line>
<line>                      integer op2, integer t, integer t2);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/system128/AArch64.SysRegWrite128" mylink="aarch64.functions.system128.AArch64.SysRegWrite128" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.SysRegWrite128()</line>
<line>// ========================</line>
<line>// Read the contents of X[t] and X[t2] and write the contents to a 128-bit System register.</line>
<line></line>
<line link="AArch64.SysRegWrite128.7" hover="function: AArch64.SysRegWrite128(integer op0, integer op1, integer crn, integer crm, integer op2, integer t, integer t2)" conts="AArch64.SysRegWrite128"><anchor link="AArch64.SysRegWrite128.7" hover="function: AArch64.SysRegWrite128(integer op0, integer op1, integer crn, integer crm, integer op2, integer t, integer t2)">AArch64.SysRegWrite128</anchor>(integer op0, integer op1, integer crn, integer crm,</line>
<line>                       integer op2, integer t, integer t2);</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/tme/CheckTransactionalSystemAccess" mylink="aarch64.functions.tme.CheckTransactionalSystemAccess" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckTransactionalSystemAccess()</line>
<line>// ================================</line>
<line>// Returns TRUE if an AArch64 MSR, MRS, or SYS instruction is permitted in</line>
<line>// Transactional state, based on the opcode's encoding, and FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.CheckTransactionalSystemAccess.6" hover="function: boolean CheckTransactionalSystemAccess(bits(2) op0, bits(3) op1, bits(4) crn, bits(4) crm, bits(3) op2, bit read)" conts="CheckTransactionalSystemAccess">boolean <anchor link="impl-aarch64.CheckTransactionalSystemAccess.6" hover="function: boolean CheckTransactionalSystemAccess(bits(2) op0, bits(3) op1, bits(4) crn, bits(4) crm, bits(3) op2, bit read)">CheckTransactionalSystemAccess</anchor>(bits(2) op0, bits(3) op1, bits(4) crn, bits(4) crm,</line>
<line>                                       bits(3) op2, bit read)</line>
<line>    case read:op0:op1:crn:crm:op2 of</line>
<line>        when '0 00 011 0100 xxxx 11x' return TRUE;      // MSR (imm): DAIFSet, DAIFClr</line>
<line>        when '0 01 011 0111 0100 001' return TRUE;      // DC ZVA</line>
<line>        when '0 11 011 0100 0010 00x' return TRUE;      // MSR: NZCV, DAIF</line>
<line>        when '0 11 011 0100 0100 00x' return TRUE;      // MSR: FPCR, FPSR</line>
<line>        when '0 11 000 0100 0110 000' return TRUE;      // MSR: ICC_PMR_EL1</line>
<line>        when '0 11 011 1001 1100 100' return TRUE;      // MRS: PMSWINC_EL0</line>
<line>        when '1 11 xxx 0xxx xxxx xxx' return TRUE;      // MRS: op1=3, CRn=0..7</line>
<line>        when '1 11 xxx 100x xxxx xxx' return TRUE;      // MRS: op1=3, CRn=8..9</line>
<line>        when '1 11 xxx 1010 xxxx xxx' return TRUE;      // MRS: op1=3, CRn=10</line>
<line>        when '1 11 000 1100 1x00 010' return TRUE;      // MRS: op1=3, CRn=12 - ICC_HPPIRx_EL1</line>
<line>        when '1 11 000 1100 1011 011' return TRUE;      // MRS: op1=3, CRn=12 - ICC_RPR_EL1</line>
<line>        when '1 11 xxx 1101 xxxx xxx' return TRUE;      // MRS: op1=3, CRn=13</line>
<line>        when '1 11 xxx 1110 xxxx xxx' return TRUE;      // MRS: op1=3, CRn=14</line>
<line>        when '0 01 011 0111 0011 111' return TRUE;      // CPP RCTX</line>
<line>        when '0 01 011 0111 0011 10x' return TRUE;      // CFP RCTX, DVP RCTX</line>
<line>        when '1 11 011 0010 0101 001' return PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;     // MRS: GCSPR_EL0, at EL0</line>
<line>        // MRS: GCSPR_EL1 at EL1 OR at EL2 when E2H is '1'</line>
<line>        when '1 11 000 0010 0101 001'</line>
<line>            return (PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> || (PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> &amp;&amp; HCR_EL2.E2H == '1'));</line>
<line>        // MRS: GCSPR_EL2, at EL2 when E2H is '0'</line>
<line>        when '1 11 100 0010 0101 001' return PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> &amp;&amp; HCR_EL2.E2H == '0';</line>
<line>        when '1 11 110 0010 0101 001' return PSTATE.EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;     // MRS: GCSPR_EL3, at EL3</line>
<line>        when '0 01 011 0111 0111 000' return TRUE;     // GCSPUSHM</line>
<line>        when '1 01 011 0111 0111 001' return TRUE;     // GCSPOPM</line>
<line>        when '0 01 011 0111 0111 010' return TRUE;     // GCSSS1</line>
<line>        when '1 01 011 0111 0111 011' return TRUE;     // GCSSS2</line>
<line>        when '0 01 000 0111 0111 110' return TRUE;     // GCSPOPX</line>
<line>        when 'x 11 xxx 1x11 xxxx xxx'                   // MRS: op1=3, CRn=11,15</line>
<line>            return boolean IMPLEMENTATION_DEFINED;</line>
<line>        otherwise return FALSE;                         // all other SYS, SYSL, MRS, MSR</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/tme/CommitTransactionalWrites" mylink="aarch64.functions.tme.CommitTransactionalWrites" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CommitTransactionalWrites()</line>
<line>// ===========================</line>
<line>// Makes all transactional writes to memory observable by other PEs and reset</line>
<line>// the transactional read and write sets.</line>
<line></line>
<line link="impl-aarch64.CommitTransactionalWrites.0" hover="function: CommitTransactionalWrites()" conts="CommitTransactionalWrites"><anchor link="impl-aarch64.CommitTransactionalWrites.0" hover="function: CommitTransactionalWrites()">CommitTransactionalWrites</anchor>();</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/tme/DiscardTransactionalWrites" mylink="aarch64.functions.tme.DiscardTransactionalWrites" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DiscardTransactionalWrites()</line>
<line>// ============================</line>
<line>// Discards all transactional writes to memory and reset the transactional</line>
<line>// read and write sets.</line>
<line></line>
<line link="impl-aarch64.DiscardTransactionalWrites.0" hover="function: DiscardTransactionalWrites()" conts="DiscardTransactionalWrites"><anchor link="impl-aarch64.DiscardTransactionalWrites.0" hover="function: DiscardTransactionalWrites()">DiscardTransactionalWrites</anchor>();</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/tme/FailTransaction" mylink="aarch64.functions.tme.FailTransaction" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FailTransaction()</line>
<line>// =================</line>
<line></line>
<line link="impl-aarch64.FailTransaction.2" hover="function: FailTransaction(TMFailure cause, boolean retry)" conts="FailTransaction"><anchor link="impl-aarch64.FailTransaction.2" hover="function: FailTransaction(TMFailure cause, boolean retry)">FailTransaction</anchor>(<a link="TMFailure" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure</a> cause, boolean retry)</line>
<line>    <a link="impl-aarch64.FailTransaction.4" file="shared_pseudocode.xml" hover="function: FailTransaction(TMFailure cause, boolean retry, boolean interrupt, bits(15) reason)">FailTransaction</a>(cause, retry, FALSE, <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(15));</line>
<line>    return;</line>
<line></line>
<line>// FailTransaction()</line>
<line>// =================</line>
<line>// Exits Transactional state and discards transactional updates to registers</line>
<line>// and memory.</line>
<line></line>
<line link="impl-aarch64.FailTransaction.4" hover="function: FailTransaction(TMFailure cause, boolean retry, boolean interrupt, bits(15) reason)" conts="FailTransaction"><anchor link="impl-aarch64.FailTransaction.4" hover="function: FailTransaction(TMFailure cause, boolean retry, boolean interrupt, bits(15) reason)">FailTransaction</anchor>(<a link="TMFailure" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure</a> cause, boolean retry, boolean interrupt, bits(15) reason)</line>
<line>    assert !retry || !interrupt;</line>
<line></line>
<line>    if <a link="impl-shared.HaveBRBExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveBRBExt()">HaveBRBExt</a>() &amp;&amp; <a link="impl-aarch64.BranchRecordAllowed.1" file="shared_pseudocode.xml" hover="function: boolean BranchRecordAllowed(bits(2) el)">BranchRecordAllowed</a>(PSTATE.EL) then BRBFCR_EL1.LASTFAILED = '1';</line>
<line></line>
<line>    <a link="impl-aarch64.DiscardTransactionalWrites.0" file="shared_pseudocode.xml" hover="function: DiscardTransactionalWrites()">DiscardTransactionalWrites</a>();</line>
<line>    // For trivial implementation no transaction checkpoint was taken</line>
<line>    if cause != <a link="TMFailure_TRIVIAL" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_TRIVIAL</a> then</line>
<line>        <a link="impl-aarch64.RestoreTransactionCheckpoint.0" file="shared_pseudocode.xml" hover="function: RestoreTransactionCheckpoint()">RestoreTransactionCheckpoint</a>();</line>
<line>    <a link="impl-shared.ClearExclusiveLocal.1" file="shared_pseudocode.xml" hover="function: ClearExclusiveLocal(integer processorid)">ClearExclusiveLocal</a>(<a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>());</line>
<line></line>
<line>    bits(64) result = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line></line>
<line>    result&lt;23&gt; = if interrupt then '1' else '0';</line>
<line>    result&lt;15&gt; = if retry &amp;&amp; !interrupt then '1' else '0';</line>
<line>    case cause of</line>
<line>        when <a link="TMFailure_TRIVIAL" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_TRIVIAL</a> result&lt;24&gt; = '1';</line>
<line>        when <a link="TMFailure_DBG" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_DBG</a>     result&lt;22&gt; = '1';</line>
<line>        when <a link="TMFailure_NEST" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_NEST</a>    result&lt;21&gt; = '1';</line>
<line>        when <a link="TMFailure_SIZE" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_SIZE</a>    result&lt;20&gt; = '1';</line>
<line>        when <a link="TMFailure_ERR" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_ERR</a>     result&lt;19&gt; = '1';</line>
<line>        when <a link="TMFailure_IMP" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_IMP</a>     result&lt;18&gt; = '1';</line>
<line>        when <a link="TMFailure_MEM" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_MEM</a>     result&lt;17&gt; = '1';</line>
<line>        when <a link="TMFailure_CNCL" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_CNCL</a>    result&lt;16&gt; = '1'; result&lt;14:0&gt; = reason;</line>
<line></line>
<line>    TSTATE.depth = 0;</line>
<line>    <a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[TSTATE.Rt, 64] = result;</line>
<line>    boolean branch_conditional = FALSE;</line>
<line>    <a link="impl-shared.BranchTo.3" file="shared_pseudocode.xml" hover="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(TSTATE.nPC, <a link="BranchType_TMFAIL" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_TMFAIL</a>, branch_conditional);</line>
<line>    <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/tme/IsTMEEnabled" mylink="aarch64.functions.tme.IsTMEEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsTMEEnabled()</line>
<line>// ==============</line>
<line>// Returns TRUE if access to TME instruction is enabled, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.IsTMEEnabled.0" hover="function: boolean IsTMEEnabled()" conts="IsTMEEnabled">boolean <anchor link="impl-aarch64.IsTMEEnabled.0" hover="function: boolean IsTMEEnabled()">IsTMEEnabled</anchor>()</line>
<line>    if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>} &amp;&amp; <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        if SCR_EL3.TME == '0' then</line>
<line>            return FALSE;</line>
<line>    if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        if HCR_EL2.TME == '0' then</line>
<line>            return FALSE;</line>
<line>    return TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/tme/MemHasTransactionalAccess" mylink="aarch64.functions.tme.MemHasTransactionalAccess" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemHasTransactionalAccess()</line>
<line>// ===========================</line>
<line>// Function checks if transactional accesses are not supported for an address</line>
<line>// range or memory type.</line>
<line></line>
<line link="impl-aarch64.MemHasTransactionalAccess.1" hover="function: boolean MemHasTransactionalAccess(MemoryAttributes memattrs)" conts="MemHasTransactionalAccess">boolean <anchor link="impl-aarch64.MemHasTransactionalAccess.1" hover="function: boolean MemHasTransactionalAccess(MemoryAttributes memattrs)">MemHasTransactionalAccess</anchor>(<a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs)</line>
<line>    if ((memattrs.shareability == <a link="Shareability_ISH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_ISH</a> ||</line>
<line>            memattrs.shareability == <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a>) &amp;&amp;</line>
<line>            memattrs.memtype == <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a> &amp;&amp;</line>
<line>            memattrs.inner.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a> &amp;&amp;</line>
<line>            memattrs.inner.hints == <a link="MemHint_RWA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RWA = '11'">MemHint_RWA</a> &amp;&amp;</line>
<line>            memattrs.inner.transient == FALSE &amp;&amp;</line>
<line>            memattrs.outer.hints == <a link="MemHint_RWA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RWA = '11'">MemHint_RWA</a> &amp;&amp;</line>
<line>            memattrs.outer.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a> &amp;&amp;</line>
<line>            memattrs.outer.transient == FALSE) then</line>
<line>        return TRUE;</line>
<line>    else</line>
<line>        return boolean IMPLEMENTATION_DEFINED "Memory Region does not support Transactional access";</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/tme/RestoreTransactionCheckpoint" mylink="aarch64.functions.tme.RestoreTransactionCheckpoint" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// RestoreTransactionCheckpoint()</line>
<line>// ==============================</line>
<line>// Restores part of the PE registers from the transaction checkpoint.</line>
<line></line>
<line link="impl-aarch64.RestoreTransactionCheckpoint.0" hover="function: RestoreTransactionCheckpoint()" conts="RestoreTransactionCheckpoint"><anchor link="impl-aarch64.RestoreTransactionCheckpoint.0" hover="function: RestoreTransactionCheckpoint()">RestoreTransactionCheckpoint</anchor>()</line>
<line>    <a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[]             = TSTATE.SP;</line>
<line>    ICC_PMR_EL1      = TSTATE.ICC_PMR_EL1;</line>
<line>    PSTATE.&lt;N,Z,C,V&gt; = TSTATE.nzcv;</line>
<line>    PSTATE.&lt;D,A,I,F&gt; = TSTATE.&lt;D,A,I,F&gt;;</line>
<line></line>
<line>    for n = 0 to 30</line>
<line>        <a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[n, 64] = TSTATE.X[n];</line>
<line></line>
<line>    if <a link="impl-aarch64.IsFPEnabled.1" file="shared_pseudocode.xml" hover="function: boolean IsFPEnabled(bits(2) el)">IsFPEnabled</a>(PSTATE.EL) then</line>
<line>        if <a link="impl-aarch64.IsSVEEnabled.1" file="shared_pseudocode.xml" hover="function: boolean IsSVEEnabled(bits(2) el)">IsSVEEnabled</a>(PSTATE.EL) then</line>
<line>            constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;</line>
<line>            constant integer PL = VL DIV 8;</line>
<line>            for n = 0 to 31</line>
<line>                <a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[n, VL] = TSTATE.Z[n]&lt;VL-1:0&gt;;</line>
<line>            for n = 0 to 15</line>
<line>                <a link="impl-aarch64.P.write.2" file="shared_pseudocode.xml" hover="accessor: P[integer n, integer width] = bits(width) value">P</a>[n, PL] = TSTATE.P[n]&lt;PL-1:0&gt;;</line>
<line>            <a link="impl-aarch64.FFR.write.1" file="shared_pseudocode.xml" hover="accessor: FFR[integer width] = bits(width) value">FFR</a>[PL] = TSTATE.FFR&lt;PL-1:0&gt;;</line>
<line>        else</line>
<line>            for n = 0 to 31</line>
<line>                <a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[n, 128] = TSTATE.Z[n]&lt;127:0&gt;;</line>
<line>        FPCR = TSTATE.FPCR;</line>
<line>        FPSR = TSTATE.FPSR;</line>
<line></line>
<line>    case PSTATE.EL of</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> GCSPR_EL0 = TSTATE.GCSPR_ELx;</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> GCSPR_EL1 = TSTATE.GCSPR_ELx;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> GCSPR_EL2 = TSTATE.GCSPR_ELx;</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> GCSPR_EL3 = TSTATE.GCSPR_ELx;</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/tme/StartTrackingTransactionalReadsWrites" mylink="aarch64.functions.tme.StartTrackingTransactionalReadsWrites" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// StartTrackingTransactionalReadsWrites()</line>
<line>// =======================================</line>
<line>// Starts tracking transactional reads and writes to memory.</line>
<line></line>
<line link="impl-aarch64.StartTrackingTransactionalReadsWrites.0" hover="function: StartTrackingTransactionalReadsWrites()" conts="StartTrackingTransactionalReadsWrites"><anchor link="impl-aarch64.StartTrackingTransactionalReadsWrites.0" hover="function: StartTrackingTransactionalReadsWrites()">StartTrackingTransactionalReadsWrites</anchor>();</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/tme/TMFailure" mylink="aarch64.functions.tme.TMFailure" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TMFailure</line>
<line>// =========</line>
<line>// Transactional failure causes</line>
<line></line>
<line link="TMFailure" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }" conts="TMFailure">enumeration <anchor link="TMFailure" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure</anchor> {</line>
<line link="TMFailure_CNCL" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }" conts="TMFailure_CNCL">    <anchor link="TMFailure_CNCL" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_CNCL</anchor>,    // Executed a TCANCEL instruction</line>
<line link="TMFailure_DBG" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }" conts="TMFailure_DBG">    <anchor link="TMFailure_DBG" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_DBG</anchor>,     // A debug event was generated</line>
<line link="TMFailure_ERR" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }" conts="TMFailure_ERR">    <anchor link="TMFailure_ERR" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_ERR</anchor>,     // A non-permissible operation was attempted</line>
<line link="TMFailure_NEST" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }" conts="TMFailure_NEST">    <anchor link="TMFailure_NEST" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_NEST</anchor>,    // The maximum transactional nesting level was exceeded</line>
<line link="TMFailure_SIZE" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }" conts="TMFailure_SIZE">    <anchor link="TMFailure_SIZE" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_SIZE</anchor>,    // The transactional read or write set limit was exceeded</line>
<line link="TMFailure_MEM" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }" conts="TMFailure_MEM">    <anchor link="TMFailure_MEM" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_MEM</anchor>,     // A transactional conflict occurred</line>
<line link="TMFailure_TRIVIAL" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }" conts="TMFailure_TRIVIAL">    <anchor link="TMFailure_TRIVIAL" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_TRIVIAL</anchor>, // Only a TRIVIAL version of TM is available</line>
<line link="TMFailure_IMP" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }" conts="TMFailure_IMP">    <anchor link="TMFailure_IMP" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_IMP</anchor>      // Any other failure cause</line>
<line>};</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/tme/TMState" mylink="aarch64.functions.tme.TMState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TMState</line>
<line>// =======</line>
<line>// Transactional execution state bits.</line>
<line>// There is no significance to the field order.</line>
<line></line>
<line>type TMState is (</line>
<line>    integer       depth,              // Transaction nesting depth</line>
<line>    integer       Rt,                 // TSTART destination register</line>
<line>    bits(64)      nPC,                // Fallback instruction address</line>
<line>    array[0..30] of bits(64)     X,   // General purpose registers</line>
<line>    array[0..31] of bits(<a link="MAX_VL" file="shared_pseudocode.xml" hover="constant integer MAX_VL = 2048">MAX_VL</a>) Z,   // Vector registers</line>
<line>    array[0..15] of bits(<a link="MAX_PL" file="shared_pseudocode.xml" hover="constant integer MAX_PL = 256">MAX_PL</a>) P,   // Predicate registers</line>
<line>    bits(<a link="MAX_PL" file="shared_pseudocode.xml" hover="constant integer MAX_PL = 256">MAX_PL</a>)  FFR,                // First Fault Register</line>
<line>    bits(64)      SP,                 // Stack Pointer at current EL</line>
<line>    bits(64)      FPCR,               // Floating-point Control Register</line>
<line>    bits(64)      FPSR,               // Floating-point Status Register</line>
<line>    bits(64)      ICC_PMR_EL1,        // Interrupt Controller Interrupt Priority Mask Register</line>
<line>    bits(64)      GCSPR_ELx,          // GCS pointer for current EL</line>
<line>    bits(4)       nzcv,               // Condition flags</line>
<line>    bits(1)       D,                  // Debug mask bit</line>
<line>    bits(1)       A,                  // SError interrupt mask bit</line>
<line>    bits(1)       I,                  // IRQ mask bit</line>
<line>    bits(1)       F                   // FIQ mask bit</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/tme/TSTATE" mylink="aarch64.functions.tme.TSTATE" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>TMState TSTATE;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/tme/TakeTransactionCheckpoint" mylink="aarch64.functions.tme.TakeTransactionCheckpoint" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TakeTransactionCheckpoint()</line>
<line>// ===========================</line>
<line>// Captures part of the PE registers into the transaction checkpoint.</line>
<line></line>
<line link="impl-aarch64.TakeTransactionCheckpoint.0" hover="function: TakeTransactionCheckpoint()" conts="TakeTransactionCheckpoint"><anchor link="impl-aarch64.TakeTransactionCheckpoint.0" hover="function: TakeTransactionCheckpoint()">TakeTransactionCheckpoint</anchor>()</line>
<line>    TSTATE.SP             = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];</line>
<line>    TSTATE.ICC_PMR_EL1    = ICC_PMR_EL1;</line>
<line>    TSTATE.nzcv           = PSTATE.&lt;N,Z,C,V&gt;;</line>
<line>    TSTATE.&lt;D,A,I,F&gt;      = PSTATE.&lt;D,A,I,F&gt;;</line>
<line></line>
<line>    for n = 0 to 30</line>
<line>        TSTATE.X[n] = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];</line>
<line></line>
<line>    if <a link="impl-aarch64.IsFPEnabled.1" file="shared_pseudocode.xml" hover="function: boolean IsFPEnabled(bits(2) el)">IsFPEnabled</a>(PSTATE.EL) then</line>
<line>        if <a link="impl-aarch64.IsSVEEnabled.1" file="shared_pseudocode.xml" hover="function: boolean IsSVEEnabled(bits(2) el)">IsSVEEnabled</a>(PSTATE.EL) then</line>
<line>            constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;</line>
<line>            constant integer PL = VL DIV 8;</line>
<line>            for n = 0 to 31</line>
<line>                TSTATE.Z[n]&lt;VL-1:0&gt; = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];</line>
<line>            for n = 0 to 15</line>
<line>                TSTATE.P[n]&lt;PL-1:0&gt; = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[n, PL];</line>
<line>            TSTATE.FFR&lt;PL-1:0&gt; = <a link="impl-aarch64.FFR.read.1" file="shared_pseudocode.xml" hover="accessor: bits(width) FFR[integer width]">FFR</a>[PL];</line>
<line>        else</line>
<line>            for n = 0 to 31</line>
<line>                TSTATE.Z[n]&lt;127:0&gt; = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, 128];</line>
<line>        TSTATE.FPCR = FPCR;</line>
<line>        TSTATE.FPSR = FPSR;</line>
<line></line>
<line>    case PSTATE.EL of</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> TSTATE.GCSPR_ELx = GCSPR_EL0;</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> TSTATE.GCSPR_ELx = GCSPR_EL1;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> TSTATE.GCSPR_ELx = GCSPR_EL2;</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> TSTATE.GCSPR_ELx = GCSPR_EL3;</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/functions/tme/TransactionStartTrap" mylink="aarch64.functions.tme.TransactionStartTrap" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TransactionStartTrap()</line>
<line>// ======================</line>
<line>// Traps the execution of TSTART instruction.</line>
<line></line>
<line link="impl-aarch64.TransactionStartTrap.1" hover="function: TransactionStartTrap(integer dreg)" conts="TransactionStartTrap"><anchor link="impl-aarch64.TransactionStartTrap.1" hover="function: TransactionStartTrap(integer dreg)">TransactionStartTrap</anchor>(integer dreg)</line>
<line>    bits(2) targetEL;</line>
<line>    bits(64) preferred_exception_return = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    vect_offset = 0x0;</line>
<line></line>
<line>    exception = <a link="impl-shared.ExceptionSyndrome.1" file="shared_pseudocode.xml" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</a>(<a link="Exception_TSTARTAccessTrap" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_TSTARTAccessTrap</a>);</line>
<line>    exception.syndrome&lt;9:5&gt; = dreg&lt;4:0&gt;;</line>
<line></line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>        targetEL = PSTATE.EL;</line>
<line>    elsif <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1' then</line>
<line>        targetEL = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>    else</line>
<line>        targetEL = <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>    <a link="AArch64.TakeException.4" file="shared_pseudocode.xml" hover="function: AArch64.TakeException(bits(2) target_el, ExceptionRecord exception_in, bits(64) preferred_exception_return, integer vect_offset_in)">AArch64.TakeException</a>(targetEL, exception, preferred_exception_return, vect_offset);</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/branch/eret/AArch64.ExceptionReturn" mylink="aarch64.instrs.branch.eret.AArch64.ExceptionReturn" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ExceptionReturn()</line>
<line>// =========================</line>
<line></line>
<line link="AArch64.ExceptionReturn.2" hover="function: AArch64.ExceptionReturn(bits(64) new_pc_in, bits(64) spsr)" conts="AArch64.ExceptionReturn"><anchor link="AArch64.ExceptionReturn.2" hover="function: AArch64.ExceptionReturn(bits(64) new_pc_in, bits(64) spsr)">AArch64.ExceptionReturn</anchor>(bits(64) new_pc_in, bits(64) spsr)</line>
<line>    bits(64) new_pc = new_pc_in;</line>
<line>    if <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0 then</line>
<line>        <a link="impl-aarch64.FailTransaction.2" file="shared_pseudocode.xml" hover="function: FailTransaction(TMFailure cause, boolean retry)">FailTransaction</a>(<a link="TMFailure_ERR" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_ERR</a>, FALSE);</line>
<line></line>
<line>    if <a link="impl-shared.HaveIESB.0" file="shared_pseudocode.xml" hover="function: boolean HaveIESB()">HaveIESB</a>() then</line>
<line>        sync_errors = <a link="impl-aarch64.SCTLR.read.0" file="shared_pseudocode.xml" hover="accessor: SCTLRType SCTLR[]">SCTLR</a>[].IESB == '1';</line>
<line>        if <a link="impl-shared.HaveDoubleFaultExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDoubleFaultExt()">HaveDoubleFaultExt</a>() then</line>
<line>            sync_errors = sync_errors || (SCR_EL3.&lt;EA,NMEA&gt; == '11' &amp;&amp; PSTATE.EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>        if sync_errors then</line>
<line>            <a link="impl-shared.SynchronizeErrors.0" file="shared_pseudocode.xml" hover="function: SynchronizeErrors()">SynchronizeErrors</a>();</line>
<line>            iesb_req = TRUE;</line>
<line>            <a link="impl-shared.TakeUnmaskedPhysicalSErrorInterrupts.1" file="shared_pseudocode.xml" hover="function: TakeUnmaskedPhysicalSErrorInterrupts(boolean iesb_req)">TakeUnmaskedPhysicalSErrorInterrupts</a>(iesb_req);</line>
<line>    <a link="impl-shared.SynchronizeContext.0" file="shared_pseudocode.xml" hover="function: SynchronizeContext()">SynchronizeContext</a>();</line>
<line></line>
<line>    // Attempts to change to an illegal state will invoke the Illegal Execution state mechanism</line>
<line>    bits(2) source_el = PSTATE.EL;</line>
<line>    boolean illegal_psr_state = <a link="impl-shared.IllegalExceptionReturn.1" file="shared_pseudocode.xml" hover="function: boolean IllegalExceptionReturn(bits(N) spsr)">IllegalExceptionReturn</a>(spsr);</line>
<line>    <a link="impl-shared.SetPSTATEFromPSR.2" file="shared_pseudocode.xml" hover="function: SetPSTATEFromPSR(bits(N) spsr_in, boolean illegal_psr_state)">SetPSTATEFromPSR</a>(spsr, illegal_psr_state);</line>
<line>    <a link="impl-shared.ClearExclusiveLocal.1" file="shared_pseudocode.xml" hover="function: ClearExclusiveLocal(integer processorid)">ClearExclusiveLocal</a>(<a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>());</line>
<line>    <a link="impl-shared.SendEventLocal.0" file="shared_pseudocode.xml" hover="function: SendEventLocal()">SendEventLocal</a>();</line>
<line></line>
<line>    if illegal_psr_state &amp;&amp; spsr&lt;4&gt; == '1' then</line>
<line>        // If the exception return is illegal, PC[63:32,1:0] are UNKNOWN</line>
<line>        new_pc&lt;63:32&gt; = bits(32) UNKNOWN;</line>
<line>        new_pc&lt;1:0&gt; = bits(2) UNKNOWN;</line>
<line>    elsif <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then                // Return to AArch32</line>
<line>        // ELR_ELx[1:0] or ELR_ELx[0] are treated as being 0, depending on the</line>
<line>        // target instruction set state</line>
<line>        if PSTATE.T == '1' then</line>
<line>            new_pc&lt;0&gt; = '0';                 // T32</line>
<line>        else</line>
<line>            new_pc&lt;1:0&gt; = '00';              // A32</line>
<line>    else                                     // Return to AArch64</line>
<line>        // ELR_ELx[63:56] might include a tag</line>
<line>        new_pc = <a link="AArch64.BranchAddr.2" file="shared_pseudocode.xml" hover="function: bits(64) AArch64.BranchAddr(bits(64) vaddress, bits(2) el)">AArch64.BranchAddr</a>(new_pc, PSTATE.EL);</line>
<line></line>
<line>    if <a link="impl-shared.HaveBRBExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveBRBExt()">HaveBRBExt</a>() then</line>
<line>        <a link="impl-aarch64.BRBEExceptionReturn.2" file="shared_pseudocode.xml" hover="function: BRBEExceptionReturn(bits(64) target_address_in, bits(2) source_el)">BRBEExceptionReturn</a>(new_pc, source_el);</line>
<line></line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        if <a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() &amp;&amp; PSTATE.SM == '1' then <a link="impl-aarch64.ResetSVEState.0" file="shared_pseudocode.xml" hover="function: ResetSVEState()">ResetSVEState</a>();</line>
<line></line>
<line>        // 32 most significant bits are ignored.</line>
<line>        boolean branch_conditional = FALSE;</line>
<line>        <a link="impl-shared.BranchTo.3" file="shared_pseudocode.xml" hover="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(new_pc&lt;31:0&gt;, <a link="BranchType_ERET" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_ERET</a>, branch_conditional);</line>
<line>    else</line>
<line>        <a link="impl-shared.BranchToAddr.2" file="shared_pseudocode.xml" hover="function: BranchToAddr(bits(N) target, BranchType branch_type)">BranchToAddr</a>(new_pc, <a link="BranchType_ERET" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_ERET</a>);</line>
<line></line>
<line>    <a link="impl-shared.CheckExceptionCatch.1" file="shared_pseudocode.xml" hover="function: CheckExceptionCatch(boolean exception_entry)">CheckExceptionCatch</a>(FALSE);              // Check for debug event on exception return</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/countop/CountOp" mylink="aarch64.instrs.countop.CountOp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CountOp</line>
<line>// =======</line>
<line>// Bit counting instruction types.</line>
<line></line>
<line link="CountOp" hover="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}" conts="CountOp">enumeration <anchor link="CountOp" hover="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}">CountOp</anchor>     {<anchor link="CountOp_CLZ" hover="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}">CountOp_CLZ</anchor>, <anchor link="CountOp_CLS" hover="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}">CountOp_CLS</anchor>, <anchor link="CountOp_CNT" hover="enumeration CountOp     {CountOp_CLZ, CountOp_CLS, CountOp_CNT}">CountOp_CNT</anchor>};</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/extendreg/DecodeRegExtend" mylink="aarch64.instrs.extendreg.DecodeRegExtend" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DecodeRegExtend()</line>
<line>// =================</line>
<line>// Decode a register extension option</line>
<line></line>
<line link="impl-aarch64.DecodeRegExtend.1" hover="function: ExtendType DecodeRegExtend(bits(3) op)" conts="DecodeRegExtend">ExtendType <anchor link="impl-aarch64.DecodeRegExtend.1" hover="function: ExtendType DecodeRegExtend(bits(3) op)">DecodeRegExtend</anchor>(bits(3) op)</line>
<line>    case op of</line>
<line>        when '000' return <a link="ExtendType_UXTB" file="shared_pseudocode.xml" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_UXTB</a>;</line>
<line>        when '001' return <a link="ExtendType_UXTH" file="shared_pseudocode.xml" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_UXTH</a>;</line>
<line>        when '010' return <a link="ExtendType_UXTW" file="shared_pseudocode.xml" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_UXTW</a>;</line>
<line>        when '011' return <a link="ExtendType_UXTX" file="shared_pseudocode.xml" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_UXTX</a>;</line>
<line>        when '100' return <a link="ExtendType_SXTB" file="shared_pseudocode.xml" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_SXTB</a>;</line>
<line>        when '101' return <a link="ExtendType_SXTH" file="shared_pseudocode.xml" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_SXTH</a>;</line>
<line>        when '110' return <a link="ExtendType_SXTW" file="shared_pseudocode.xml" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_SXTW</a>;</line>
<line>        when '111' return <a link="ExtendType_SXTX" file="shared_pseudocode.xml" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_SXTX</a>;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/extendreg/ExtendReg" mylink="aarch64.instrs.extendreg.ExtendReg" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExtendReg()</line>
<line>// ===========</line>
<line>// Perform a register extension and shift</line>
<line></line>
<line link="impl-aarch64.ExtendReg.4" hover="function: bits(N) ExtendReg(integer reg, ExtendType exttype, integer shift, integer N)" conts="ExtendReg">bits(N) <anchor link="impl-aarch64.ExtendReg.4" hover="function: bits(N) ExtendReg(integer reg, ExtendType exttype, integer shift, integer N)">ExtendReg</anchor>(integer reg, <a link="ExtendType" file="shared_pseudocode.xml" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType</a> exttype, integer shift, integer N)</line>
<line>    assert shift &gt;= 0 &amp;&amp; shift &lt;= 4;</line>
<line>    bits(N) val = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[reg, N];</line>
<line>    boolean unsigned;</line>
<line>    integer len;</line>
<line></line>
<line>    case exttype of</line>
<line>        when <a link="ExtendType_SXTB" file="shared_pseudocode.xml" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_SXTB</a> unsigned = FALSE; len = 8;</line>
<line>        when <a link="ExtendType_SXTH" file="shared_pseudocode.xml" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_SXTH</a> unsigned = FALSE; len = 16;</line>
<line>        when <a link="ExtendType_SXTW" file="shared_pseudocode.xml" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_SXTW</a> unsigned = FALSE; len = 32;</line>
<line>        when <a link="ExtendType_SXTX" file="shared_pseudocode.xml" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_SXTX</a> unsigned = FALSE; len = 64;</line>
<line>        when <a link="ExtendType_UXTB" file="shared_pseudocode.xml" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_UXTB</a> unsigned = TRUE;  len = 8;</line>
<line>        when <a link="ExtendType_UXTH" file="shared_pseudocode.xml" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_UXTH</a> unsigned = TRUE;  len = 16;</line>
<line>        when <a link="ExtendType_UXTW" file="shared_pseudocode.xml" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_UXTW</a> unsigned = TRUE;  len = 32;</line>
<line>        when <a link="ExtendType_UXTX" file="shared_pseudocode.xml" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_UXTX</a> unsigned = TRUE;  len = 64;</line>
<line></line>
<line>    // Note the extended width of the intermediate value and</line>
<line>    // that sign extension occurs from bit &lt;len+shift-1&gt;, not</line>
<line>    // from bit &lt;len-1&gt;. This is equivalent to the instruction</line>
<line>    //   [SU]BFIZ Rtmp, Rreg, #shift, #len</line>
<line>    // It may also be seen as a sign/zero extend followed by a shift:</line>
<line>    //   LSL(Extend(val&lt;len-1:0&gt;, N, unsigned), shift);</line>
<line></line>
<line>    len = <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(len, N - shift);</line>
<line>    return <a link="impl-shared.Extend.3" file="shared_pseudocode.xml" hover="function: bits(N) Extend(bits(M) x, integer N, boolean unsigned)">Extend</a>(val&lt;len-1:0&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(shift), N, unsigned);</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/extendreg/ExtendType" mylink="aarch64.instrs.extendreg.ExtendType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExtendType</line>
<line>// ==========</line>
<line>// AArch64 register extend and shift.</line>
<line></line>
<line link="ExtendType" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}" conts="ExtendType">enumeration <anchor link="ExtendType" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType</anchor>  {<anchor link="ExtendType_SXTB" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_SXTB</anchor>, <anchor link="ExtendType_SXTH" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_SXTH</anchor>, <anchor link="ExtendType_SXTW" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_SXTW</anchor>, <anchor link="ExtendType_SXTX" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_SXTX</anchor>,</line>
<line link="ExtendType_UXTB" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}" conts="ExtendType_UXTB">                         <anchor link="ExtendType_UXTB" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_UXTB</anchor>, <anchor link="ExtendType_UXTH" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_UXTH</anchor>, <anchor link="ExtendType_UXTW" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_UXTW</anchor>, <anchor link="ExtendType_UXTX" hover="enumeration ExtendType  {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType_UXTX</anchor>};</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/float/arithmetic/max-min/fpmaxminop/FPMaxMinOp" mylink="aarch64.instrs.float.arithmetic.max-min.fpmaxminop.FPMaxMinOp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPMaxMinOp</line>
<line>// ==========</line>
<line>// Floating-point min/max instruction types.</line>
<line></line>
<line link="FPMaxMinOp" hover="enumeration FPMaxMinOp  {FPMaxMinOp_MAX, FPMaxMinOp_MIN, FPMaxMinOp_MAXNUM, FPMaxMinOp_MINNUM}" conts="FPMaxMinOp">enumeration <anchor link="FPMaxMinOp" hover="enumeration FPMaxMinOp  {FPMaxMinOp_MAX, FPMaxMinOp_MIN, FPMaxMinOp_MAXNUM, FPMaxMinOp_MINNUM}">FPMaxMinOp</anchor>  {<anchor link="FPMaxMinOp_MAX" hover="enumeration FPMaxMinOp  {FPMaxMinOp_MAX, FPMaxMinOp_MIN, FPMaxMinOp_MAXNUM, FPMaxMinOp_MINNUM}">FPMaxMinOp_MAX</anchor>, <anchor link="FPMaxMinOp_MIN" hover="enumeration FPMaxMinOp  {FPMaxMinOp_MAX, FPMaxMinOp_MIN, FPMaxMinOp_MAXNUM, FPMaxMinOp_MINNUM}">FPMaxMinOp_MIN</anchor>,</line>
<line link="FPMaxMinOp_MAXNUM" hover="enumeration FPMaxMinOp  {FPMaxMinOp_MAX, FPMaxMinOp_MIN, FPMaxMinOp_MAXNUM, FPMaxMinOp_MINNUM}" conts="FPMaxMinOp_MAXNUM">                         <anchor link="FPMaxMinOp_MAXNUM" hover="enumeration FPMaxMinOp  {FPMaxMinOp_MAX, FPMaxMinOp_MIN, FPMaxMinOp_MAXNUM, FPMaxMinOp_MINNUM}">FPMaxMinOp_MAXNUM</anchor>, <anchor link="FPMaxMinOp_MINNUM" hover="enumeration FPMaxMinOp  {FPMaxMinOp_MAX, FPMaxMinOp_MIN, FPMaxMinOp_MAXNUM, FPMaxMinOp_MINNUM}">FPMaxMinOp_MINNUM</anchor>};</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/float/arithmetic/unary/fpunaryop/FPUnaryOp" mylink="aarch64.instrs.float.arithmetic.unary.fpunaryop.FPUnaryOp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPUnaryOp</line>
<line>// =========</line>
<line>// Floating-point unary instruction types.</line>
<line></line>
<line link="FPUnaryOp" hover="enumeration FPUnaryOp   {FPUnaryOp_ABS, FPUnaryOp_MOV, FPUnaryOp_NEG, FPUnaryOp_SQRT}" conts="FPUnaryOp">enumeration <anchor link="FPUnaryOp" hover="enumeration FPUnaryOp   {FPUnaryOp_ABS, FPUnaryOp_MOV, FPUnaryOp_NEG, FPUnaryOp_SQRT}">FPUnaryOp</anchor>   {<anchor link="FPUnaryOp_ABS" hover="enumeration FPUnaryOp   {FPUnaryOp_ABS, FPUnaryOp_MOV, FPUnaryOp_NEG, FPUnaryOp_SQRT}">FPUnaryOp_ABS</anchor>, <anchor link="FPUnaryOp_MOV" hover="enumeration FPUnaryOp   {FPUnaryOp_ABS, FPUnaryOp_MOV, FPUnaryOp_NEG, FPUnaryOp_SQRT}">FPUnaryOp_MOV</anchor>,</line>
<line link="FPUnaryOp_NEG" hover="enumeration FPUnaryOp   {FPUnaryOp_ABS, FPUnaryOp_MOV, FPUnaryOp_NEG, FPUnaryOp_SQRT}" conts="FPUnaryOp_NEG">                         <anchor link="FPUnaryOp_NEG" hover="enumeration FPUnaryOp   {FPUnaryOp_ABS, FPUnaryOp_MOV, FPUnaryOp_NEG, FPUnaryOp_SQRT}">FPUnaryOp_NEG</anchor>, <anchor link="FPUnaryOp_SQRT" hover="enumeration FPUnaryOp   {FPUnaryOp_ABS, FPUnaryOp_MOV, FPUnaryOp_NEG, FPUnaryOp_SQRT}">FPUnaryOp_SQRT</anchor>};</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/float/convert/fpconvop/FPConvOp" mylink="aarch64.instrs.float.convert.fpconvop.FPConvOp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPConvOp</line>
<line>// ========</line>
<line>// Floating-point convert/move instruction types.</line>
<line></line>
<line link="FPConvOp" hover="enumeration FPConvOp    {FPConvOp_CVT_FtoI, FPConvOp_CVT_ItoF, FPConvOp_MOV_FtoI, FPConvOp_MOV_ItoF , FPConvOp_CVT_FtoI_JS }" conts="FPConvOp">enumeration <anchor link="FPConvOp" hover="enumeration FPConvOp    {FPConvOp_CVT_FtoI, FPConvOp_CVT_ItoF, FPConvOp_MOV_FtoI, FPConvOp_MOV_ItoF , FPConvOp_CVT_FtoI_JS }">FPConvOp</anchor>    {<anchor link="FPConvOp_CVT_FtoI" hover="enumeration FPConvOp    {FPConvOp_CVT_FtoI, FPConvOp_CVT_ItoF, FPConvOp_MOV_FtoI, FPConvOp_MOV_ItoF , FPConvOp_CVT_FtoI_JS }">FPConvOp_CVT_FtoI</anchor>, <anchor link="FPConvOp_CVT_ItoF" hover="enumeration FPConvOp    {FPConvOp_CVT_FtoI, FPConvOp_CVT_ItoF, FPConvOp_MOV_FtoI, FPConvOp_MOV_ItoF , FPConvOp_CVT_FtoI_JS }">FPConvOp_CVT_ItoF</anchor>,</line>
<line link="FPConvOp_MOV_FtoI" hover="enumeration FPConvOp    {FPConvOp_CVT_FtoI, FPConvOp_CVT_ItoF, FPConvOp_MOV_FtoI, FPConvOp_MOV_ItoF , FPConvOp_CVT_FtoI_JS }" conts="FPConvOp_MOV_FtoI">                         <anchor link="FPConvOp_MOV_FtoI" hover="enumeration FPConvOp    {FPConvOp_CVT_FtoI, FPConvOp_CVT_ItoF, FPConvOp_MOV_FtoI, FPConvOp_MOV_ItoF , FPConvOp_CVT_FtoI_JS }">FPConvOp_MOV_FtoI</anchor>, <anchor link="FPConvOp_MOV_ItoF" hover="enumeration FPConvOp    {FPConvOp_CVT_FtoI, FPConvOp_CVT_ItoF, FPConvOp_MOV_FtoI, FPConvOp_MOV_ItoF , FPConvOp_CVT_FtoI_JS }">FPConvOp_MOV_ItoF</anchor></line>
<line link="FPConvOp_CVT_FtoI_JS" hover="enumeration FPConvOp    {FPConvOp_CVT_FtoI, FPConvOp_CVT_ItoF, FPConvOp_MOV_FtoI, FPConvOp_MOV_ItoF , FPConvOp_CVT_FtoI_JS }" conts="FPConvOp_CVT_FtoI_JS">                         , <anchor link="FPConvOp_CVT_FtoI_JS" hover="enumeration FPConvOp    {FPConvOp_CVT_FtoI, FPConvOp_CVT_ItoF, FPConvOp_MOV_FtoI, FPConvOp_MOV_ItoF , FPConvOp_CVT_FtoI_JS }">FPConvOp_CVT_FtoI_JS</anchor></line>
<line>};</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/integer/bitfield/bfxpreferred/BFXPreferred" mylink="aarch64.instrs.integer.bitfield.bfxpreferred.BFXPreferred" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BFXPreferred()</line>
<line>// ==============</line>
<line>//</line>
<line>// Return TRUE if UBFX or SBFX is the preferred disassembly of a</line>
<line>// UBFM or SBFM bitfield instruction. Must exclude more specific</line>
<line>// aliases UBFIZ, SBFIZ, UXT[BH], SXT[BHW], LSL, LSR and ASR.</line>
<line></line>
<line link="impl-aarch64.BFXPreferred.4" hover="function: boolean BFXPreferred(bit sf, bit uns, bits(6) imms, bits(6) immr)" conts="BFXPreferred">boolean <anchor link="impl-aarch64.BFXPreferred.4" hover="function: boolean BFXPreferred(bit sf, bit uns, bits(6) imms, bits(6) immr)">BFXPreferred</anchor>(bit sf, bit uns, bits(6) imms, bits(6) immr)</line>
<line></line>
<line>    // must not match UBFIZ/SBFIX alias</line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imms) &lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(immr) then</line>
<line>        return FALSE;</line>
<line></line>
<line>    // must not match LSR/ASR/LSL alias (imms == 31 or 63)</line>
<line>    if imms == sf:'11111' then</line>
<line>        return FALSE;</line>
<line></line>
<line>    // must not match UXTx/SXTx alias</line>
<line>    if immr == '000000' then</line>
<line>        // must not match 32-bit UXT[BH] or SXT[BH]</line>
<line>        if sf == '0' &amp;&amp; imms IN {'000111', '001111'} then</line>
<line>            return FALSE;</line>
<line>        // must not match 64-bit SXT[BHW]</line>
<line>        if sf:uns == '10' &amp;&amp; imms IN {'000111', '001111', '011111'} then</line>
<line>            return FALSE;</line>
<line></line>
<line>    // must be UBFX/SBFX alias</line>
<line>    return TRUE;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/integer/bitmasks/AltDecodeBitMasks" mylink="aarch64.instrs.integer.bitmasks.AltDecodeBitMasks" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AltDecodeBitMasks()</line>
<line>// ===================</line>
<line>// Alternative but logically equivalent implementation of DecodeBitMasks() that</line>
<line>// uses simpler primitives to compute tmask and wmask.</line>
<line></line>
<line link="impl-aarch64.AltDecodeBitMasks.5" hover="function: (bits(M), bits(M)) AltDecodeBitMasks(bit immN, bits(6) imms, bits(6) immr, boolean immediate, integer M)" conts="AltDecodeBitMasks">(bits(M), bits(M)) <anchor link="impl-aarch64.AltDecodeBitMasks.5" hover="function: (bits(M), bits(M)) AltDecodeBitMasks(bit immN, bits(6) imms, bits(6) immr, boolean immediate, integer M)">AltDecodeBitMasks</anchor>(bit immN, bits(6) imms, bits(6) immr,</line>
<line>                                     boolean immediate, integer M)</line>
<line>    bits(64) tmask, wmask;</line>
<line>    bits(6) tmask_and, wmask_and;</line>
<line>    bits(6) tmask_or, wmask_or;</line>
<line>    bits(6) levels;</line>
<line></line>
<line>    // Compute log2 of element size</line>
<line>    // 2^len must be in range [2, M]</line>
<line>    len = <a link="impl-shared.HighestSetBit.1" file="shared_pseudocode.xml" hover="function: integer HighestSetBit(bits(N) x)">HighestSetBit</a>(immN:NOT(imms));</line>
<line>    if len &lt; 1 then UNDEFINED;</line>
<line>    assert M &gt;= (1 &lt;&lt; len);</line>
<line></line>
<line>    // Determine s, r and s - r parameters</line>
<line>    levels = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(len), 6);</line>
<line></line>
<line>    // For logical immediates an all-ones value of s is reserved</line>
<line>    // since it would generate a useless all-ones result (many times)</line>
<line>    if immediate &amp;&amp; (imms AND levels) == levels then</line>
<line>        UNDEFINED;</line>
<line></line>
<line>    s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imms AND levels);</line>
<line>    r = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(immr AND levels);</line>
<line>    diff = s - r;    // 6-bit subtract with borrow</line>
<line></line>
<line>    // Compute "top mask"</line>
<line>    tmask_and = diff&lt;5:0&gt; OR NOT(levels);</line>
<line>    tmask_or  = diff&lt;5:0&gt; AND levels;</line>
<line></line>
<line>    tmask = <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(64);</line>
<line>    tmask = ((tmask</line>
<line>              AND <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(tmask_and&lt;0&gt;, 1) : <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(1), 32))</line>
<line>               OR  <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(1) : <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(tmask_or&lt;0&gt;, 1), 32));</line>
<line>    // optimization of first step:</line>
<line>    // tmask = Replicate(tmask_and&lt;0&gt; : '1', 32);</line>
<line>    tmask = ((tmask</line>
<line>              AND <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(tmask_and&lt;1&gt;, 2) : <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(2), 16))</line>
<line>               OR  <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(2) : <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(tmask_or&lt;1&gt;, 2), 16));</line>
<line>    tmask = ((tmask</line>
<line>              AND <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(tmask_and&lt;2&gt;, 4) : <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(4), 8))</line>
<line>               OR  <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(4) : <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(tmask_or&lt;2&gt;, 4), 8));</line>
<line>    tmask = ((tmask</line>
<line>              AND <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(tmask_and&lt;3&gt;, 8) : <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(8), 4))</line>
<line>               OR  <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8) : <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(tmask_or&lt;3&gt;, 8), 4));</line>
<line>    tmask = ((tmask</line>
<line>              AND <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(tmask_and&lt;4&gt;, 16) : <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(16), 2))</line>
<line>               OR  <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(tmask_or&lt;4&gt;, 16), 2));</line>
<line>    tmask = ((tmask</line>
<line>              AND <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(tmask_and&lt;5&gt;, 32) : <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(32), 1))</line>
<line>               OR  <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32) : <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(tmask_or&lt;5&gt;, 32), 1));</line>
<line></line>
<line>    // Compute "wraparound mask"</line>
<line>    wmask_and = immr OR NOT(levels);</line>
<line>    wmask_or  = immr AND levels;</line>
<line></line>
<line>    wmask = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>    wmask = ((wmask</line>
<line>              AND <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(1) : <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(wmask_and&lt;0&gt;, 1), 32))</line>
<line>               OR  <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(wmask_or&lt;0&gt;, 1) : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(1), 32));</line>
<line>    // optimization of first step:</line>
<line>    // wmask = Replicate(wmask_or&lt;0&gt; : '0', 32);</line>
<line>    wmask = ((wmask</line>
<line>              AND <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(2) : <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(wmask_and&lt;1&gt;, 2), 16))</line>
<line>               OR  <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(wmask_or&lt;1&gt;, 2) : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(2), 16));</line>
<line>    wmask = ((wmask</line>
<line>              AND <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(4) : <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(wmask_and&lt;2&gt;, 4), 8))</line>
<line>               OR  <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(wmask_or&lt;2&gt;, 4) : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(4), 8));</line>
<line>    wmask = ((wmask</line>
<line>              AND <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(8) : <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(wmask_and&lt;3&gt;, 8), 4))</line>
<line>               OR  <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(wmask_or&lt;3&gt;, 8) : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8), 4));</line>
<line>    wmask = ((wmask</line>
<line>              AND <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(16) : <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(wmask_and&lt;4&gt;, 16), 2))</line>
<line>               OR  <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(wmask_or&lt;4&gt;, 16) : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16), 2));</line>
<line>    wmask = ((wmask</line>
<line>              AND <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(32) : <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(wmask_and&lt;5&gt;, 32), 1))</line>
<line>               OR  <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(wmask_or&lt;5&gt;, 32) : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32), 1));</line>
<line></line>
<line>    if diff&lt;6&gt; != '0' then // borrow from s - r</line>
<line>        wmask = wmask AND tmask;</line>
<line>    else</line>
<line>        wmask = wmask OR tmask;</line>
<line></line>
<line>    return (wmask&lt;M-1:0&gt;, tmask&lt;M-1:0&gt;);</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/integer/bitmasks/DecodeBitMasks" mylink="aarch64.instrs.integer.bitmasks.DecodeBitMasks" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DecodeBitMasks()</line>
<line>// ================</line>
<line>// Decode AArch64 bitfield and logical immediate masks which use a similar encoding structure</line>
<line></line>
<line link="impl-aarch64.DecodeBitMasks.5" hover="function: (bits(M), bits(M)) DecodeBitMasks(bit immN, bits(6) imms, bits(6) immr, boolean immediate, integer M)" conts="DecodeBitMasks">(bits(M), bits(M)) <anchor link="impl-aarch64.DecodeBitMasks.5" hover="function: (bits(M), bits(M)) DecodeBitMasks(bit immN, bits(6) imms, bits(6) immr, boolean immediate, integer M)">DecodeBitMasks</anchor>(bit immN, bits(6) imms, bits(6) immr,</line>
<line>                                  boolean immediate, integer M)</line>
<line>    bits(M) tmask, wmask;</line>
<line>    bits(6) levels;</line>
<line></line>
<line>    // Compute log2 of element size</line>
<line>    // 2^len must be in range [2, M]</line>
<line>    len = <a link="impl-shared.HighestSetBit.1" file="shared_pseudocode.xml" hover="function: integer HighestSetBit(bits(N) x)">HighestSetBit</a>(immN:NOT(imms));</line>
<line>    if len &lt; 1 then UNDEFINED;</line>
<line>    assert M &gt;= (1 &lt;&lt; len);</line>
<line></line>
<line>    // Determine s, r and s - r parameters</line>
<line>    levels = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(len), 6);</line>
<line></line>
<line>    // For logical immediates an all-ones value of s is reserved</line>
<line>    // since it would generate a useless all-ones result (many times)</line>
<line>    if immediate &amp;&amp; (imms AND levels) == levels then</line>
<line>        UNDEFINED;</line>
<line></line>
<line>    s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imms AND levels);</line>
<line>    r = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(immr AND levels);</line>
<line>    diff = s - r;    // 6-bit subtract with borrow</line>
<line></line>
<line>    esize = 1 &lt;&lt; len;</line>
<line>    d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(diff&lt;len-1:0&gt;);</line>
<line>    welem = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(s + 1), esize);</line>
<line>    telem = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(d + 1), esize);</line>
<line>    wmask = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(welem, r), M DIV esize);</line>
<line>    tmask = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(telem, M DIV esize);</line>
<line>    return (wmask, tmask);</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/integer/ins-ext/insert/movewide/movewideop/MoveWideOp" mylink="aarch64.instrs.integer.ins-ext.insert.movewide.movewideop.MoveWideOp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MoveWideOp</line>
<line>// ==========</line>
<line>// Move wide 16-bit immediate instruction types.</line>
<line></line>
<line link="MoveWideOp" hover="enumeration MoveWideOp  {MoveWideOp_N, MoveWideOp_Z, MoveWideOp_K}" conts="MoveWideOp">enumeration <anchor link="MoveWideOp" hover="enumeration MoveWideOp  {MoveWideOp_N, MoveWideOp_Z, MoveWideOp_K}">MoveWideOp</anchor>  {<anchor link="MoveWideOp_N" hover="enumeration MoveWideOp  {MoveWideOp_N, MoveWideOp_Z, MoveWideOp_K}">MoveWideOp_N</anchor>, <anchor link="MoveWideOp_Z" hover="enumeration MoveWideOp  {MoveWideOp_N, MoveWideOp_Z, MoveWideOp_K}">MoveWideOp_Z</anchor>, <anchor link="MoveWideOp_K" hover="enumeration MoveWideOp  {MoveWideOp_N, MoveWideOp_Z, MoveWideOp_K}">MoveWideOp_K</anchor>};</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/integer/logical/movwpreferred/MoveWidePreferred" mylink="aarch64.instrs.integer.logical.movwpreferred.MoveWidePreferred" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MoveWidePreferred()</line>
<line>// ===================</line>
<line>//</line>
<line>// Return TRUE if a bitmask immediate encoding would generate an immediate</line>
<line>// value that could also be represented by a single MOVZ or MOVN instruction.</line>
<line>// Used as a condition for the preferred MOV&lt;-ORR alias.</line>
<line></line>
<line link="impl-aarch64.MoveWidePreferred.4" hover="function: boolean MoveWidePreferred(bit sf, bit immN, bits(6) imms, bits(6) immr)" conts="MoveWidePreferred">boolean <anchor link="impl-aarch64.MoveWidePreferred.4" hover="function: boolean MoveWidePreferred(bit sf, bit immN, bits(6) imms, bits(6) immr)">MoveWidePreferred</anchor>(bit sf, bit immN, bits(6) imms, bits(6) immr)</line>
<line>    integer s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imms);</line>
<line>    integer r = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(immr);</line>
<line>    integer width = if sf == '1' then 64 else 32;</line>
<line></line>
<line>    // element size must equal total immediate size</line>
<line>    if sf == '1' &amp;&amp; !((immN:imms) IN {'1xxxxxx'}) then</line>
<line>        return FALSE;</line>
<line>    if sf == '0' &amp;&amp; !((immN:imms) IN {'00xxxxx'}) then</line>
<line>        return FALSE;</line>
<line></line>
<line>    // for MOVZ must contain no more than 16 ones</line>
<line>    if s &lt; 16 then</line>
<line>        // ones must not span halfword boundary when rotated</line>
<line>        return (-r MOD 16) &lt;= (15 - s);</line>
<line></line>
<line>    // for MOVN must contain no more than 16 zeros</line>
<line>    if s &gt;= width - 15 then</line>
<line>        // zeros must not span halfword boundary when rotated</line>
<line>        return (r MOD 16) &lt;= (s - (width - 15));</line>
<line></line>
<line>    return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/integer/shiftreg/DecodeShift" mylink="aarch64.instrs.integer.shiftreg.DecodeShift" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DecodeShift()</line>
<line>// =============</line>
<line>// Decode shift encodings</line>
<line></line>
<line link="impl-aarch64.DecodeShift.1" hover="function: ShiftType DecodeShift(bits(2) op)" conts="DecodeShift">ShiftType <anchor link="impl-aarch64.DecodeShift.1" hover="function: ShiftType DecodeShift(bits(2) op)">DecodeShift</anchor>(bits(2) op)</line>
<line>    case op of</line>
<line>        when '00'  return <a link="ShiftType_LSL" file="shared_pseudocode.xml" hover="enumeration ShiftType   {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}">ShiftType_LSL</a>;</line>
<line>        when '01'  return <a link="ShiftType_LSR" file="shared_pseudocode.xml" hover="enumeration ShiftType   {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}">ShiftType_LSR</a>;</line>
<line>        when '10'  return <a link="ShiftType_ASR" file="shared_pseudocode.xml" hover="enumeration ShiftType   {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}">ShiftType_ASR</a>;</line>
<line>        when '11'  return <a link="ShiftType_ROR" file="shared_pseudocode.xml" hover="enumeration ShiftType   {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}">ShiftType_ROR</a>;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/integer/shiftreg/ShiftReg" mylink="aarch64.instrs.integer.shiftreg.ShiftReg" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ShiftReg()</line>
<line>// ==========</line>
<line>// Perform shift of a register operand</line>
<line></line>
<line link="impl-aarch64.ShiftReg.4" hover="function: bits(N) ShiftReg(integer reg, ShiftType shiftype, integer amount, integer N)" conts="ShiftReg">bits(N) <anchor link="impl-aarch64.ShiftReg.4" hover="function: bits(N) ShiftReg(integer reg, ShiftType shiftype, integer amount, integer N)">ShiftReg</anchor>(integer reg, <a link="ShiftType" file="shared_pseudocode.xml" hover="enumeration ShiftType   {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}">ShiftType</a> shiftype, integer amount, integer N)</line>
<line>    bits(N) result = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[reg, N];</line>
<line>    case shiftype of</line>
<line>        when <a link="ShiftType_LSL" file="shared_pseudocode.xml" hover="enumeration ShiftType   {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}">ShiftType_LSL</a> result = <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(result, amount);</line>
<line>        when <a link="ShiftType_LSR" file="shared_pseudocode.xml" hover="enumeration ShiftType   {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}">ShiftType_LSR</a> result = <a link="impl-shared.LSR.2" file="shared_pseudocode.xml" hover="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(result, amount);</line>
<line>        when <a link="ShiftType_ASR" file="shared_pseudocode.xml" hover="enumeration ShiftType   {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}">ShiftType_ASR</a> result = <a link="impl-shared.ASR.2" file="shared_pseudocode.xml" hover="function: bits(N) ASR(bits(N) x, integer shift)">ASR</a>(result, amount);</line>
<line>        when <a link="ShiftType_ROR" file="shared_pseudocode.xml" hover="enumeration ShiftType   {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}">ShiftType_ROR</a> result = <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(result, amount);</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/integer/shiftreg/ShiftType" mylink="aarch64.instrs.integer.shiftreg.ShiftType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ShiftType</line>
<line>// =========</line>
<line>// AArch64 register shifts.</line>
<line></line>
<line link="ShiftType" hover="enumeration ShiftType   {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}" conts="ShiftType">enumeration <anchor link="ShiftType" hover="enumeration ShiftType   {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}">ShiftType</anchor>   {<anchor link="ShiftType_LSL" hover="enumeration ShiftType   {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}">ShiftType_LSL</anchor>, <anchor link="ShiftType_LSR" hover="enumeration ShiftType   {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}">ShiftType_LSR</anchor>, <anchor link="ShiftType_ASR" hover="enumeration ShiftType   {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}">ShiftType_ASR</anchor>, <anchor link="ShiftType_ROR" hover="enumeration ShiftType   {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}">ShiftType_ROR</anchor>};</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/logicalop/LogicalOp" mylink="aarch64.instrs.logicalop.LogicalOp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// LogicalOp</line>
<line>// =========</line>
<line>// Logical instruction types.</line>
<line></line>
<line link="LogicalOp" hover="enumeration LogicalOp   {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}" conts="LogicalOp">enumeration <anchor link="LogicalOp" hover="enumeration LogicalOp   {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp</anchor>   {<anchor link="LogicalOp_AND" hover="enumeration LogicalOp   {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</anchor>, <anchor link="LogicalOp_EOR" hover="enumeration LogicalOp   {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_EOR</anchor>, <anchor link="LogicalOp_ORR" hover="enumeration LogicalOp   {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_ORR</anchor>};</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/memory/prefetch/Prefetch" mylink="aarch64.instrs.memory.prefetch.Prefetch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Prefetch()</line>
<line>// ==========</line>
<line></line>
<line>// Decode and execute the prefetch hint on ADDRESS specified by PRFOP</line>
<line></line>
<line link="impl-aarch64.Prefetch.2" hover="function: Prefetch(bits(64) address, bits(5) prfop)" conts="Prefetch"><anchor link="impl-aarch64.Prefetch.2" hover="function: Prefetch(bits(64) address, bits(5) prfop)">Prefetch</anchor>(bits(64) address, bits(5) prfop)</line>
<line>    <a link="PrefetchHint" file="shared_pseudocode.xml" hover="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">PrefetchHint</a> hint;</line>
<line>    integer target;</line>
<line>    boolean stream;</line>
<line></line>
<line>    case prfop&lt;4:3&gt; of</line>
<line>        when '00' hint = <a link="Prefetch_READ" file="shared_pseudocode.xml" hover="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">Prefetch_READ</a>;         // PLD: prefetch for load</line>
<line>        when '01' hint = <a link="Prefetch_EXEC" file="shared_pseudocode.xml" hover="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">Prefetch_EXEC</a>;         // PLI: preload instructions</line>
<line>        when '10' hint = <a link="Prefetch_WRITE" file="shared_pseudocode.xml" hover="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">Prefetch_WRITE</a>;        // PST: prepare for store</line>
<line>        when '11' return;                       // unallocated hint</line>
<line>    target = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(prfop&lt;2:1&gt;);                  // target cache level</line>
<line>    stream = (prfop&lt;0&gt; != '0');                 // streaming (non-temporal)</line>
<line>    <a link="impl-shared.Hint_Prefetch.4" file="shared_pseudocode.xml" hover="function: Hint_Prefetch(bits(64) address, PrefetchHint hint, integer target, boolean stream)">Hint_Prefetch</a>(address, hint, target, stream);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/barriers/barrierop/MemBarrierOp" mylink="aarch64.instrs.system.barriers.barrierop.MemBarrierOp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemBarrierOp</line>
<line>// ============</line>
<line>// Memory barrier instruction types.</line>
<line></line>
<line link="MemBarrierOp" hover="enumeration MemBarrierOp   {  MemBarrierOp_DSB , MemBarrierOp_DMB , MemBarrierOp_ISB , MemBarrierOp_SSBB , MemBarrierOp_PSSBB , MemBarrierOp_SB }" conts="MemBarrierOp">enumeration <anchor link="MemBarrierOp" hover="enumeration MemBarrierOp   {  MemBarrierOp_DSB , MemBarrierOp_DMB , MemBarrierOp_ISB , MemBarrierOp_SSBB , MemBarrierOp_PSSBB , MemBarrierOp_SB }">MemBarrierOp</anchor>   {  <anchor link="MemBarrierOp_DSB" hover="enumeration MemBarrierOp   {  MemBarrierOp_DSB , MemBarrierOp_DMB , MemBarrierOp_ISB , MemBarrierOp_SSBB , MemBarrierOp_PSSBB , MemBarrierOp_SB }">MemBarrierOp_DSB</anchor>         // Data Synchronization Barrier</line>
<line link="MemBarrierOp_DMB" hover="enumeration MemBarrierOp   {  MemBarrierOp_DSB , MemBarrierOp_DMB , MemBarrierOp_ISB , MemBarrierOp_SSBB , MemBarrierOp_PSSBB , MemBarrierOp_SB }" conts="MemBarrierOp_DMB">                            , <anchor link="MemBarrierOp_DMB" hover="enumeration MemBarrierOp   {  MemBarrierOp_DSB , MemBarrierOp_DMB , MemBarrierOp_ISB , MemBarrierOp_SSBB , MemBarrierOp_PSSBB , MemBarrierOp_SB }">MemBarrierOp_DMB</anchor>         // Data Memory Barrier</line>
<line link="MemBarrierOp_ISB" hover="enumeration MemBarrierOp   {  MemBarrierOp_DSB , MemBarrierOp_DMB , MemBarrierOp_ISB , MemBarrierOp_SSBB , MemBarrierOp_PSSBB , MemBarrierOp_SB }" conts="MemBarrierOp_ISB">                            , <anchor link="MemBarrierOp_ISB" hover="enumeration MemBarrierOp   {  MemBarrierOp_DSB , MemBarrierOp_DMB , MemBarrierOp_ISB , MemBarrierOp_SSBB , MemBarrierOp_PSSBB , MemBarrierOp_SB }">MemBarrierOp_ISB</anchor>         // Instruction Synchronization Barrier</line>
<line link="MemBarrierOp_SSBB" hover="enumeration MemBarrierOp   {  MemBarrierOp_DSB , MemBarrierOp_DMB , MemBarrierOp_ISB , MemBarrierOp_SSBB , MemBarrierOp_PSSBB , MemBarrierOp_SB }" conts="MemBarrierOp_SSBB">                            , <anchor link="MemBarrierOp_SSBB" hover="enumeration MemBarrierOp   {  MemBarrierOp_DSB , MemBarrierOp_DMB , MemBarrierOp_ISB , MemBarrierOp_SSBB , MemBarrierOp_PSSBB , MemBarrierOp_SB }">MemBarrierOp_SSBB</anchor>        // Speculative Synchronization Barrier to VA</line>
<line link="MemBarrierOp_PSSBB" hover="enumeration MemBarrierOp   {  MemBarrierOp_DSB , MemBarrierOp_DMB , MemBarrierOp_ISB , MemBarrierOp_SSBB , MemBarrierOp_PSSBB , MemBarrierOp_SB }" conts="MemBarrierOp_PSSBB">                            , <anchor link="MemBarrierOp_PSSBB" hover="enumeration MemBarrierOp   {  MemBarrierOp_DSB , MemBarrierOp_DMB , MemBarrierOp_ISB , MemBarrierOp_SSBB , MemBarrierOp_PSSBB , MemBarrierOp_SB }">MemBarrierOp_PSSBB</anchor>       // Speculative Synchronization Barrier to PA</line>
<line link="MemBarrierOp_SB" hover="enumeration MemBarrierOp   {  MemBarrierOp_DSB , MemBarrierOp_DMB , MemBarrierOp_ISB , MemBarrierOp_SSBB , MemBarrierOp_PSSBB , MemBarrierOp_SB }" conts="MemBarrierOp_SB">                            , <anchor link="MemBarrierOp_SB" hover="enumeration MemBarrierOp   {  MemBarrierOp_DSB , MemBarrierOp_DMB , MemBarrierOp_ISB , MemBarrierOp_SSBB , MemBarrierOp_PSSBB , MemBarrierOp_SB }">MemBarrierOp_SB</anchor>          // Speculation Barrier</line>
<line>                           };</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/hints/syshintop/SystemHintOp" mylink="aarch64.instrs.system.hints.syshintop.SystemHintOp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SystemHintOp</line>
<line>// ============</line>
<line>// System Hint instruction types.</line>
<line></line>
<line link="SystemHintOp" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }" conts="SystemHintOp">enumeration <anchor link="SystemHintOp" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp</anchor> {</line>
<line link="SystemHintOp_NOP" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }" conts="SystemHintOp_NOP">    <anchor link="SystemHintOp_NOP" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_NOP</anchor>,</line>
<line link="SystemHintOp_YIELD" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }" conts="SystemHintOp_YIELD">    <anchor link="SystemHintOp_YIELD" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_YIELD</anchor>,</line>
<line link="SystemHintOp_WFE" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }" conts="SystemHintOp_WFE">    <anchor link="SystemHintOp_WFE" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_WFE</anchor>,</line>
<line link="SystemHintOp_WFI" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }" conts="SystemHintOp_WFI">    <anchor link="SystemHintOp_WFI" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_WFI</anchor>,</line>
<line link="SystemHintOp_SEV" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }" conts="SystemHintOp_SEV">    <anchor link="SystemHintOp_SEV" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_SEV</anchor>,</line>
<line link="SystemHintOp_SEVL" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }" conts="SystemHintOp_SEVL">    <anchor link="SystemHintOp_SEVL" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_SEVL</anchor>,</line>
<line link="SystemHintOp_DGH" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }" conts="SystemHintOp_DGH">    <anchor link="SystemHintOp_DGH" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_DGH</anchor>,</line>
<line link="SystemHintOp_ESB" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }" conts="SystemHintOp_ESB">    <anchor link="SystemHintOp_ESB" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_ESB</anchor>,</line>
<line link="SystemHintOp_PSB" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }" conts="SystemHintOp_PSB">    <anchor link="SystemHintOp_PSB" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_PSB</anchor>,</line>
<line link="SystemHintOp_TSB" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }" conts="SystemHintOp_TSB">    <anchor link="SystemHintOp_TSB" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_TSB</anchor>,</line>
<line link="SystemHintOp_BTI" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }" conts="SystemHintOp_BTI">    <anchor link="SystemHintOp_BTI" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_BTI</anchor>,</line>
<line link="SystemHintOp_WFET" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }" conts="SystemHintOp_WFET">    <anchor link="SystemHintOp_WFET" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_WFET</anchor>,</line>
<line link="SystemHintOp_WFIT" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }" conts="SystemHintOp_WFIT">    <anchor link="SystemHintOp_WFIT" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_WFIT</anchor>,</line>
<line link="SystemHintOp_CLRBHB" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }" conts="SystemHintOp_CLRBHB">    <anchor link="SystemHintOp_CLRBHB" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_CLRBHB</anchor>,</line>
<line link="SystemHintOp_GCSB" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }" conts="SystemHintOp_GCSB">    <anchor link="SystemHintOp_GCSB" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_GCSB</anchor>,</line>
<line link="SystemHintOp_CHKFEAT" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }" conts="SystemHintOp_CHKFEAT">    <anchor link="SystemHintOp_CHKFEAT" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_CHKFEAT</anchor>,</line>
<line link="SystemHintOp_CSDB" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }" conts="SystemHintOp_CSDB">    <anchor link="SystemHintOp_CSDB" hover="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_CSDB</anchor></line>
<line>};</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/register/cpsr/pstatefield/PSTATEField" mylink="aarch64.instrs.system.register.cpsr.pstatefield.PSTATEField" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PSTATEField</line>
<line>// ===========</line>
<line>// MSR (immediate) instruction destinations.</line>
<line></line>
<line link="PSTATEField" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }" conts="PSTATEField">enumeration <anchor link="PSTATEField" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }">PSTATEField</anchor> {<anchor link="PSTATEField_DAIFSet" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }">PSTATEField_DAIFSet</anchor>, <anchor link="PSTATEField_DAIFClr" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }">PSTATEField_DAIFClr</anchor>,</line>
<line link="PSTATEField_PAN" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }" conts="PSTATEField_PAN">                         <anchor link="PSTATEField_PAN" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }">PSTATEField_PAN</anchor>, // Armv8.1</line>
<line link="PSTATEField_UAO" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }" conts="PSTATEField_UAO">                         <anchor link="PSTATEField_UAO" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }">PSTATEField_UAO</anchor>, // Armv8.2</line>
<line link="PSTATEField_DIT" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }" conts="PSTATEField_DIT">                         <anchor link="PSTATEField_DIT" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }">PSTATEField_DIT</anchor>, // Armv8.4</line>
<line link="PSTATEField_SSBS" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }" conts="PSTATEField_SSBS">                         <anchor link="PSTATEField_SSBS" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }">PSTATEField_SSBS</anchor>,</line>
<line link="PSTATEField_TCO" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }" conts="PSTATEField_TCO">                         <anchor link="PSTATEField_TCO" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }">PSTATEField_TCO</anchor>, // Armv8.5</line>
<line link="PSTATEField_SVCRSM" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }" conts="PSTATEField_SVCRSM">                         <anchor link="PSTATEField_SVCRSM" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }">PSTATEField_SVCRSM</anchor>,</line>
<line link="PSTATEField_SVCRZA" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }" conts="PSTATEField_SVCRZA">                         <anchor link="PSTATEField_SVCRZA" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }">PSTATEField_SVCRZA</anchor>,</line>
<line link="PSTATEField_SVCRSMZA" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }" conts="PSTATEField_SVCRSMZA">                         <anchor link="PSTATEField_SVCRSMZA" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }">PSTATEField_SVCRSMZA</anchor>,</line>
<line link="PSTATEField_ALLINT" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }" conts="PSTATEField_ALLINT">                         <anchor link="PSTATEField_ALLINT" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }">PSTATEField_ALLINT</anchor>,</line>
<line link="PSTATEField_PM" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }" conts="PSTATEField_PM">                         <anchor link="PSTATEField_PM" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }">PSTATEField_PM</anchor>,</line>
<line link="PSTATEField_SP" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }" conts="PSTATEField_SP">                         <anchor link="PSTATEField_SP" hover="enumeration PSTATEField {PSTATEField_DAIFSet, PSTATEField_DAIFClr, PSTATEField_PAN, PSTATEField_UAO, PSTATEField_DIT, PSTATEField_SSBS, PSTATEField_TCO, PSTATEField_SVCRSM, PSTATEField_SVCRZA, PSTATEField_SVCRSMZA, PSTATEField_ALLINT, PSTATEField_PM, PSTATEField_SP }">PSTATEField_SP</anchor></line>
<line>                         };</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/at/AArch64.AT" mylink="aarch64.instrs.system.sysops.at.AArch64.AT" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.AT()</line>
<line>// ============</line>
<line>// Perform address translation as per AT instructions.</line>
<line></line>
<line link="AArch64.AT.4" hover="function: AArch64.AT(bits(64) address, TranslationStage stage_in, bits(2) el_in, ATAccess ataccess)" conts="AArch64.AT"><anchor link="AArch64.AT.4" hover="function: AArch64.AT(bits(64) address, TranslationStage stage_in, bits(2) el_in, ATAccess ataccess)">AArch64.AT</anchor>(bits(64) address, <a link="TranslationStage" file="shared_pseudocode.xml" hover="enumeration TranslationStage { TranslationStage_1, TranslationStage_12 }">TranslationStage</a> stage_in, bits(2) el_in, <a link="ATAccess" file="shared_pseudocode.xml" hover="enumeration ATAccess { ATAccess_Read, ATAccess_Write, ATAccess_ReadPAN, ATAccess_WritePAN }">ATAccess</a> ataccess)</line>
<line>    <a link="TranslationStage" file="shared_pseudocode.xml" hover="enumeration TranslationStage { TranslationStage_1, TranslationStage_12 }">TranslationStage</a> stage = stage_in;</line>
<line>    bits(2) el = el_in;</line>
<line>    bits(2) effective_nse_ns = <a link="impl-shared.EffectiveSCR_EL3_NSE.0" file="shared_pseudocode.xml" hover="function: bit EffectiveSCR_EL3_NSE()">EffectiveSCR_EL3_NSE</a>() : <a link="impl-shared.EffectiveSCR_EL3_NS.0" file="shared_pseudocode.xml" hover="function: bit EffectiveSCR_EL3_NS()">EffectiveSCR_EL3_NS</a>();</line>
<line>    if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() &amp;&amp; PSTATE.EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> &amp;&amp; effective_nse_ns == '10' &amp;&amp; el != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then</line>
<line>        UNDEFINED;</line>
<line>    // For stage 1 translation, when HCR_EL2.{E2H, TGE} is {1,1} and requested EL is EL1,</line>
<line>    // the EL2&amp;0 translation regime is used.</line>
<line>    if HCR_EL2.&lt;E2H, TGE&gt; == '11' &amp;&amp; el == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; stage == <a link="TranslationStage_1" file="shared_pseudocode.xml" hover="enumeration TranslationStage { TranslationStage_1, TranslationStage_12 }">TranslationStage_1</a> then</line>
<line>        el = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; stage == <a link="TranslationStage_12" file="shared_pseudocode.xml" hover="enumeration TranslationStage { TranslationStage_1, TranslationStage_12 }">TranslationStage_12</a> &amp;&amp; !<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        stage = <a link="TranslationStage_1" file="shared_pseudocode.xml" hover="enumeration TranslationStage { TranslationStage_1, TranslationStage_12 }">TranslationStage_1</a>;</line>
<line></line>
<line>    boolean write = ataccess IN {<a link="ATAccess_WritePAN" file="shared_pseudocode.xml" hover="enumeration ATAccess { ATAccess_Read, ATAccess_Write, ATAccess_ReadPAN, ATAccess_WritePAN }">ATAccess_WritePAN</a>, <a link="ATAccess_Write" file="shared_pseudocode.xml" hover="enumeration ATAccess { ATAccess_Read, ATAccess_Write, ATAccess_ReadPAN, ATAccess_WritePAN }">ATAccess_Write</a>};</line>
<line>    <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss = <a link="impl-shared.SecurityStateAtEL.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)">SecurityStateAtEL</a>(el);</line>
<line>    boolean pan = ataccess IN {<a link="ATAccess_ReadPAN" file="shared_pseudocode.xml" hover="enumeration ATAccess { ATAccess_Read, ATAccess_Write, ATAccess_ReadPAN, ATAccess_WritePAN }">ATAccess_ReadPAN</a>, <a link="ATAccess_WritePAN" file="shared_pseudocode.xml" hover="enumeration ATAccess { ATAccess_Read, ATAccess_Write, ATAccess_ReadPAN, ATAccess_WritePAN }">ATAccess_WritePAN</a>};</line>
<line>    accdesc = <a link="impl-shared.CreateAccDescAT.4" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescAT(SecurityState ss, bits(2) el, boolean write, boolean pan)">CreateAccDescAT</a>(ss, el, write, pan);</line>
<line>    aligned = TRUE;</line>
<line></line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = <a link="impl-shared.NoFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord NoFault(AccessDescriptor accdesc)">NoFault</a>(accdesc);</line>
<line>    <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime;</line>
<line>    if stage == <a link="TranslationStage_12" file="shared_pseudocode.xml" hover="enumeration TranslationStage { TranslationStage_1, TranslationStage_12 }">TranslationStage_12</a> then</line>
<line>        regime = <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a>;</line>
<line>    else</line>
<line>        regime = <a link="impl-shared.TranslationRegime.1" file="shared_pseudocode.xml" hover="function: Regime TranslationRegime(bits(2) el)">TranslationRegime</a>(el);</line>
<line></line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> addrdesc;</line>
<line>    if (el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>)) || (el != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(el)) then</line>
<line>        if regime == <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a> || TTBCR.EAE == '1' then</line>
<line>            (fault, addrdesc) = <a link="AArch32.S1TranslateLD.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, AddressDescriptor) AArch32.S1TranslateLD(FaultRecord fault_in, Regime regime, bits(32) va, boolean aligned, AccessDescriptor accdesc)">AArch32.S1TranslateLD</a>(fault, regime, address&lt;31:0&gt;, aligned,</line>
<line>                                                      accdesc);</line>
<line>        else</line>
<line>            (fault, addrdesc, -) = <a link="AArch32.S1TranslateSD.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, AddressDescriptor, SDFType) AArch32.S1TranslateSD(FaultRecord fault_in, Regime regime, bits(32) va, boolean aligned, AccessDescriptor accdesc)">AArch32.S1TranslateSD</a>(fault, regime, address&lt;31:0&gt;, aligned,</line>
<line>                                                         accdesc);</line>
<line>    else</line>
<line>        (fault, addrdesc) = <a link="AArch64.S1Translate.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, AddressDescriptor) AArch64.S1Translate(FaultRecord fault_in, Regime regime, bits(64) va, boolean aligned, AccessDescriptor accdesc)">AArch64.S1Translate</a>(fault, regime, address, aligned, accdesc);</line>
<line></line>
<line>    if stage == <a link="TranslationStage_12" file="shared_pseudocode.xml" hover="enumeration TranslationStage { TranslationStage_1, TranslationStage_12 }">TranslationStage_12</a> &amp;&amp; fault.statuscode == <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>        boolean s1aarch64;</line>
<line>        if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) &amp;&amp; regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>            addrdesc.vaddress = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(address, 64);</line>
<line>            (fault, addrdesc) = <a link="AArch32.S2Translate.4" file="shared_pseudocode.xml" hover="function: (FaultRecord, AddressDescriptor) AArch32.S2Translate(FaultRecord fault_in, AddressDescriptor ipa, boolean aligned, AccessDescriptor accdesc)">AArch32.S2Translate</a>(fault, addrdesc, aligned, accdesc);</line>
<line>        elsif regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>            s1aarch64 = TRUE;</line>
<line>            (fault, addrdesc) = <a link="AArch64.S2Translate.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, AddressDescriptor) AArch64.S2Translate(FaultRecord fault_in, AddressDescriptor ipa, boolean s1aarch64, boolean aligned, AccessDescriptor accdesc)">AArch64.S2Translate</a>(fault, addrdesc, s1aarch64, aligned, accdesc);</line>
<line></line>
<line>    is_ATS1Ex = stage != <a link="TranslationStage_12" file="shared_pseudocode.xml" hover="enumeration TranslationStage { TranslationStage_1, TranslationStage_12 }">TranslationStage_12</a>;</line>
<line>    if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>        addrdesc = <a link="impl-shared.CreateFaultyAddressDescriptor.2" file="shared_pseudocode.xml" hover="function: AddressDescriptor CreateFaultyAddressDescriptor(bits(64) va, FaultRecord fault)">CreateFaultyAddressDescriptor</a>(address, fault);</line>
<line>        // Take an exception on:</line>
<line>        // * A Synchronous External abort occurs on translation table walk</line>
<line>        // * A stage 2 fault occurs on a stage 1 walk</line>
<line>        // * A GPC Exception (FEAT_RME)</line>
<line>        // * A GPF from ATS1E{1,0}* when executed from EL1 and HCR_EL2.GPF == '1' (FEAT_RME)</line>
<line>        if (<a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault) ||</line>
<line>                (PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; fault.s2fs1walk) ||</line>
<line>                (<a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() &amp;&amp; fault.gpcf.gpf != <a link="GPCF_None" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_None</a> &amp;&amp; (</line>
<line>                    <a link="impl-shared.ReportAsGPCException.1" file="shared_pseudocode.xml" hover="function: boolean ReportAsGPCException(FaultRecord fault)">ReportAsGPCException</a>(fault) ||</line>
<line>                    (HCR_EL2.GPF == '1' &amp;&amp; PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; el IN {<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>} &amp;&amp; is_ATS1Ex)</line>
<line>                ))) then</line>
<line>            PAR_EL1 = bits(128) UNKNOWN;</line>
<line>            <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(address, addrdesc.fault);</line>
<line></line>
<line>    <a link="AArch64.EncodePAR.3" file="shared_pseudocode.xml" hover="function: AArch64.EncodePAR(Regime regime, boolean is_ATS1Ex, AddressDescriptor addrdesc)">AArch64.EncodePAR</a>(regime, is_ATS1Ex, addrdesc);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/at/AArch64.EncodePAR" mylink="aarch64.instrs.system.sysops.at.AArch64.EncodePAR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.EncodePAR()</line>
<line>// ===================</line>
<line>// Encode PAR register with result of translation.</line>
<line></line>
<line link="AArch64.EncodePAR.3" hover="function: AArch64.EncodePAR(Regime regime, boolean is_ATS1Ex, AddressDescriptor addrdesc)" conts="AArch64.EncodePAR"><anchor link="AArch64.EncodePAR.3" hover="function: AArch64.EncodePAR(Regime regime, boolean is_ATS1Ex, AddressDescriptor addrdesc)">AArch64.EncodePAR</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, boolean is_ATS1Ex, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> addrdesc)</line>
<line>    PAR_EL1 = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(128);</line>
<line>    paspace = addrdesc.paddress.paspace;</line>
<line></line>
<line>    if !<a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(addrdesc) then</line>
<line>        PAR_EL1.F = '0';</line>
<line>        if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then</line>
<line>            if regime == <a link="Regime_EL3" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL3</a> then</line>
<line>                case paspace of</line>
<line>                    when <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a>     PAR_EL1.&lt;NSE,NS&gt; = '00';</line>
<line>                    when <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>  PAR_EL1.&lt;NSE,NS&gt; = '01';</line>
<line>                    when <a link="PAS_Root" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Root</a>       PAR_EL1.&lt;NSE,NS&gt; = '10';</line>
<line>                    when <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a>      PAR_EL1.&lt;NSE,NS&gt; = '11';</line>
<line></line>
<line>            elsif <a link="impl-shared.SecurityStateForRegime.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateForRegime(Regime regime)">SecurityStateForRegime</a>(regime) == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>  then</line>
<line>                PAR_EL1.NSE = bit UNKNOWN;</line>
<line>                PAR_EL1.NS = if paspace == <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a> then '0' else '1';</line>
<line></line>
<line>            elsif <a link="impl-shared.SecurityStateForRegime.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateForRegime(Regime regime)">SecurityStateForRegime</a>(regime) == <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a> then</line>
<line>                if regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; is_ATS1Ex then</line>
<line>                    PAR_EL1.NSE = bit UNKNOWN;</line>
<line>                    PAR_EL1.NS  = bit UNKNOWN;</line>
<line>                else</line>
<line>                    PAR_EL1.NSE = bit UNKNOWN;</line>
<line>                    PAR_EL1.NS  = if paspace == <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a> then '0' else '1';</line>
<line></line>
<line>            else</line>
<line>                PAR_EL1.NSE = bit UNKNOWN;</line>
<line>                PAR_EL1.NS  = bit UNKNOWN;</line>
<line>        else</line>
<line>            PAR_EL1&lt;11&gt; = '1'; // RES1</line>
<line>            if <a link="impl-shared.SecurityStateForRegime.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateForRegime(Regime regime)">SecurityStateForRegime</a>(regime) == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>                PAR_EL1.NS = if paspace == <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a> then '0' else '1';</line>
<line>            else</line>
<line>                PAR_EL1.NS = bit UNKNOWN;</line>
<line>        PAR_EL1.SH   = <a link="impl-shared.ReportedPARShareability.1" file="shared_pseudocode.xml" hover="function: bits(2) ReportedPARShareability(bits(2) sh)">ReportedPARShareability</a>(<a link="impl-shared.PAREncodeShareability.1" file="shared_pseudocode.xml" hover="function: bits(2) PAREncodeShareability(MemoryAttributes memattrs)">PAREncodeShareability</a>(addrdesc.memattrs));</line>
<line>        if <a link="AArch64.IsVMSAv9_128.2" file="shared_pseudocode.xml" hover="function: boolean AArch64.IsVMSAv9_128(Regime regime, boolean is_ATS1Ex)">AArch64.IsVMSAv9_128</a>(regime, is_ATS1Ex) then</line>
<line>            PAR_EL1.D128 = '1';</line>
<line>            PAR_EL1&lt;119:76&gt; = addrdesc.paddress.address&lt;55:12&gt;;</line>
<line>        else</line>
<line>            PAR_EL1.D128 = '0';</line>
<line>            PAR_EL1&lt;55:12&gt; = addrdesc.paddress.address&lt;55:12&gt;;</line>
<line>        PAR_EL1.ATTR = <a link="impl-shared.ReportedPARAttrs.1" file="shared_pseudocode.xml" hover="function: bits(8) ReportedPARAttrs(bits(8) parattrs)">ReportedPARAttrs</a>(<a link="impl-shared.EncodePARAttrs.1" file="shared_pseudocode.xml" hover="function: bits(8) EncodePARAttrs(MemoryAttributes memattrs)">EncodePARAttrs</a>(addrdesc.memattrs));</line>
<line>        PAR_EL1&lt;10&gt; = bit IMPLEMENTATION_DEFINED "Non-Faulting PAR";</line>
<line>    else</line>
<line>        PAR_EL1.F   = '1';</line>
<line>        PAR_EL1.DirtyBit    = if addrdesc.fault.dirtybit then '1' else '0';</line>
<line>        PAR_EL1.Overlay     = if addrdesc.fault.overlay then '1' else '0';</line>
<line>        PAR_EL1.TopLevel    = if addrdesc.fault.toplevel then '1' else '0';</line>
<line>        PAR_EL1.AssuredOnly = if addrdesc.fault.assuredonly then '1' else '0';</line>
<line>        PAR_EL1.FST = <a link="AArch64.PARFaultStatus.1" file="shared_pseudocode.xml" hover="function: bits(6) AArch64.PARFaultStatus(FaultRecord fault)">AArch64.PARFaultStatus</a>(addrdesc.fault);</line>
<line>        PAR_EL1.PTW = if addrdesc.fault.s2fs1walk then '1' else '0';</line>
<line>        PAR_EL1.S   = if addrdesc.fault.secondstage then '1' else '0';</line>
<line>        PAR_EL1&lt;11&gt; = '1'; // RES1</line>
<line>        PAR_EL1&lt;63:48&gt; = bits(16) IMPLEMENTATION_DEFINED "Faulting PAR";</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/at/AArch64.IsVMSAv9_128" mylink="aarch64.instrs.system.sysops.at.AArch64.IsVMSAv9_128" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.IsVMSAv9_128()</line>
<line>// ======================</line>
<line>// Check if the Translation Regime uses VMSAv9-128.</line>
<line></line>
<line link="AArch64.IsVMSAv9_128.2" hover="function: boolean AArch64.IsVMSAv9_128(Regime regime, boolean is_ATS1Ex)" conts="AArch64.IsVMSAv9_128">boolean <anchor link="AArch64.IsVMSAv9_128.2" hover="function: boolean AArch64.IsVMSAv9_128(Regime regime, boolean is_ATS1Ex)">AArch64.IsVMSAv9_128</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, boolean is_ATS1Ex)</line>
<line>    boolean is_VMSAv9_128;</line>
<line>    // Regime_EL2 does not support VMSAv9-128</line>
<line>    if regime == <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a> || !<a link="impl-shared.Have128BitDescriptorExt.0" file="shared_pseudocode.xml" hover="function: boolean Have128BitDescriptorExt()">Have128BitDescriptorExt</a>() then</line>
<line>        is_VMSAv9_128 = FALSE;</line>
<line>    else</line>
<line>        is_VMSAv9_128 = FALSE;</line>
<line>        case regime of</line>
<line>            when <a link="Regime_EL3" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL3</a></line>
<line>                is_VMSAv9_128 = TCR_EL3.D128 == '1';</line>
<line>            when <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a></line>
<line>                is_VMSAv9_128 = TCR2_EL2.D128 == '1';</line>
<line>            when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a></line>
<line>                if (is_ATS1Ex || (HCR_EL2.&lt;VM,DC&gt; == '00')) then</line>
<line>                    is_VMSAv9_128 = TCR2_EL1.D128 == '1';</line>
<line>                else</line>
<line>                    is_VMSAv9_128 = VTCR_EL2.D128 == '1';</line>
<line></line>
<line>    return is_VMSAv9_128;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/at/AArch64.PARFaultStatus" mylink="aarch64.instrs.system.sysops.at.AArch64.PARFaultStatus" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.PARFaultStatus()</line>
<line>// ========================</line>
<line>// Fault status field decoding of 64-bit PAR.</line>
<line></line>
<line link="AArch64.PARFaultStatus.1" hover="function: bits(6) AArch64.PARFaultStatus(FaultRecord fault)" conts="AArch64.PARFaultStatus">bits(6) <anchor link="AArch64.PARFaultStatus.1" hover="function: bits(6) AArch64.PARFaultStatus(FaultRecord fault)">AArch64.PARFaultStatus</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    bits(6) fst;</line>
<line></line>
<line>    if fault.statuscode == <a link="Fault_Domain" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Domain</a> then</line>
<line>        // Report Domain fault</line>
<line>        assert fault.level IN {1,2};</line>
<line>        fst&lt;1:0&gt; = if fault.level == 1 then '01' else '10';</line>
<line>        fst&lt;5:2&gt; = '1111';</line>
<line>    else</line>
<line>        fst = <a link="impl-shared.EncodeLDFSC.2" file="shared_pseudocode.xml" hover="function: bits(6) EncodeLDFSC(Fault statuscode, integer level)">EncodeLDFSC</a>(fault.statuscode, fault.level);</line>
<line>    return fst;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/at/GetPAR_EL1_D128" mylink="aarch64.instrs.system.sysops.at.GetPAR_EL1_D128" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GetPAR_EL1_D128()</line>
<line>// =================</line>
<line>// Query the PAR_EL1.D128 field</line>
<line></line>
<line link="impl-aarch64.GetPAR_EL1_D128.0" hover="function: bit GetPAR_EL1_D128()" conts="GetPAR_EL1_D128">bit <anchor link="impl-aarch64.GetPAR_EL1_D128.0" hover="function: bit GetPAR_EL1_D128()">GetPAR_EL1_D128</anchor>()</line>
<line>    bit D128;</line>
<line></line>
<line>    D128 = PAR_EL1.D128;</line>
<line>    return D128;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/at/GetPAR_EL1_F" mylink="aarch64.instrs.system.sysops.at.GetPAR_EL1_F" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GetPAR_EL1_F()</line>
<line>// ==============</line>
<line>// Query the PAR_EL1.F field.</line>
<line></line>
<line link="impl-aarch64.GetPAR_EL1_F.0" hover="function: bit GetPAR_EL1_F()" conts="GetPAR_EL1_F">bit <anchor link="impl-aarch64.GetPAR_EL1_F.0" hover="function: bit GetPAR_EL1_F()">GetPAR_EL1_F</anchor>()</line>
<line>    bit F;</line>
<line></line>
<line>    F = PAR_EL1.F;</line>
<line>    return F;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/dc/AArch64.DC" mylink="aarch64.instrs.system.sysops.dc.AArch64.DC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.DC()</line>
<line>// ============</line>
<line>// Perform Data Cache Operation.</line>
<line></line>
<line link="AArch64.DC.4" hover="function: AArch64.DC(bits(64) regval, CacheType cachetype, CacheOp cacheop, CacheOpScope opscope_in)" conts="AArch64.DC"><anchor link="AArch64.DC.4" hover="function: AArch64.DC(bits(64) regval, CacheType cachetype, CacheOp cacheop, CacheOpScope opscope_in)">AArch64.DC</anchor>(bits(64) regval, <a link="CacheType" file="shared_pseudocode.xml" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }">CacheType</a> cachetype, <a link="CacheOp" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp</a> cacheop, <a link="CacheOpScope" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope</a> opscope_in)</line>
<line>    <a link="CacheOpScope" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope</a> opscope = opscope_in;</line>
<line>    <a link="CacheRecord" file="shared_pseudocode.xml" hover="type CacheRecord is ( AccessType acctype, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, bits(64) regval, FullAddress paddress, bits(64) vaddress, integer set, integer way, integer level, Shareability shareability, boolean translated, boolean is_vmid_valid, bits(16) vmid, boolean is_asid_valid, bits(16) asid, SecurityState security, CachePASpace cpas )">CacheRecord</a> cache;</line>
<line></line>
<line>    cache.acctype   = <a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>;</line>
<line>    cache.cachetype = cachetype;</line>
<line>    cache.cacheop   = cacheop;</line>
<line>    cache.opscope   = opscope;</line>
<line></line>
<line>    if opscope == <a link="CacheOpScope_SetWay" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_SetWay</a> then</line>
<line>        ss = <a link="impl-shared.SecurityStateAtEL.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)">SecurityStateAtEL</a>(PSTATE.EL);</line>
<line>        cache.cpas = <a link="impl-shared.CPASAtSecurityState.1" file="shared_pseudocode.xml" hover="function: CachePASpace CPASAtSecurityState(SecurityState ss)">CPASAtSecurityState</a>(ss);</line>
<line>        cache.shareability = <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a>;</line>
<line>        (cache.set, cache.way, cache.level) = <a link="impl-shared.DecodeSW.2" file="shared_pseudocode.xml" hover="function: (integer, integer, integer) DecodeSW(bits(64) regval, CacheType cachetype)">DecodeSW</a>(regval, cachetype);</line>
<line>        if (cacheop == <a link="CacheOp_Invalidate" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_Invalidate</a> &amp;&amp; PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>          (HCR_EL2.SWIO == '1' || HCR_EL2.&lt;DC,VM&gt; != '00')) then</line>
<line>            cache.cacheop = <a link="CacheOp_CleanInvalidate" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_CleanInvalidate</a>;</line>
<line></line>
<line>        <a link="impl-shared.CACHE_OP.1" file="shared_pseudocode.xml" hover="function: CACHE_OP(CacheRecord cache)">CACHE_OP</a>(cache);</line>
<line>        return;</line>
<line></line>
<line>    if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>        if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} then</line>
<line>            cache.is_vmid_valid = TRUE;</line>
<line>            cache.vmid          = <a link="impl-aarch64.VMID.read.0" file="shared_pseudocode.xml" hover="accessor: bits(16) VMID[]">VMID</a>[];</line>
<line>        else</line>
<line>            cache.is_vmid_valid = FALSE;</line>
<line>    else</line>
<line>        cache.is_vmid_valid = FALSE;</line>
<line></line>
<line>    if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        cache.is_asid_valid = TRUE;</line>
<line>        cache.asid          = <a link="impl-shared.ASID.read.0" file="shared_pseudocode.xml" hover="accessor: bits(16) ASID[]">ASID</a>[];</line>
<line>    else</line>
<line>        cache.is_asid_valid = FALSE;</line>
<line></line>
<line>    if (opscope == <a link="CacheOpScope_PoDP" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_PoDP</a> &amp;&amp;</line>
<line>          boolean IMPLEMENTATION_DEFINED "Memory system does not supports PoDP") then</line>
<line>        opscope = <a link="CacheOpScope_PoP" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_PoP</a>;</line>
<line>    if (opscope == <a link="CacheOpScope_PoP" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_PoP</a> &amp;&amp;</line>
<line>          boolean IMPLEMENTATION_DEFINED "Memory system does not supports PoP") then</line>
<line>        opscope = <a link="CacheOpScope_PoC" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_PoC</a>;</line>
<line>    vaddress = regval;</line>
<line></line>
<line>    size = 0;        // by default no watchpoint address</line>
<line>    if cacheop == <a link="CacheOp_Invalidate" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_Invalidate</a> then</line>
<line>        size = integer IMPLEMENTATION_DEFINED "Data Cache Invalidate Watchpoint Size";</line>
<line>        assert size &gt;= 4*(2^(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(CTR_EL0.DminLine))) &amp;&amp; size &lt;= 2048;</line>
<line>        assert <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size&lt;32:0&gt; AND (size-1)&lt;32:0&gt;) == 0; // size is power of 2</line>
<line>        vaddress = <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(regval, size);</line>
<line></line>
<line>    if <a link="impl-shared.DCInstNeedsTranslation.1" file="shared_pseudocode.xml" hover="function: boolean DCInstNeedsTranslation(CacheOpScope opscope)">DCInstNeedsTranslation</a>(opscope) then</line>
<line>        cache.vaddress  = vaddress;</line>
<line>        boolean aligned = TRUE;</line>
<line>        <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescDC.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescDC(CacheRecord cache)">CreateAccDescDC</a>(cache);</line>
<line>        <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc = <a link="AArch64.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch64.TranslateAddress(bits(64) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch64.TranslateAddress</a>(vaddress, accdesc, aligned, size);</line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>            <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(regval, memaddrdesc.fault);</line>
<line></line>
<line>        cache.translated = TRUE;</line>
<line>        cache.paddress   = memaddrdesc.paddress;</line>
<line>        cache.cpas       = <a link="impl-shared.CPASAtPAS.1" file="shared_pseudocode.xml" hover="function: CachePASpace CPASAtPAS(PASpace pas)">CPASAtPAS</a>(memaddrdesc.paddress.paspace);</line>
<line>        if opscope IN {<a link="CacheOpScope_PoC" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_PoC</a>, <a link="CacheOpScope_PoP" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_PoP</a>, <a link="CacheOpScope_PoDP" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_PoDP</a>} then</line>
<line>            cache.shareability = memaddrdesc.memattrs.shareability;</line>
<line>        else</line>
<line>            cache.shareability = <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a>;</line>
<line>    elsif opscope == <a link="CacheOpScope_PoE" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_PoE</a> then</line>
<line>        cache.vaddress         = bits(64) UNKNOWN;</line>
<line>        cache.translated       = TRUE;</line>
<line>        cache.shareability     = <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a>;</line>
<line>        cache.paddress.address = regval&lt;55:0&gt;;</line>
<line>        cache.paddress.paspace = <a link="impl-shared.DecodePASpace.2" file="shared_pseudocode.xml" hover="function: PASpace DecodePASpace (bit nse, bit ns)">DecodePASpace</a>(regval&lt;62&gt;, regval&lt;63&gt;);</line>
<line>        cache.cpas             = <a link="impl-shared.CPASAtPAS.1" file="shared_pseudocode.xml" hover="function: CachePASpace CPASAtPAS(PASpace pas)">CPASAtPAS</a>(cache.paddress.paspace);</line>
<line></line>
<line>        // If a Reserved encoding is selected, the instruction is permitted to be treated as a NOP.</line>
<line>        if cache.paddress.paspace != <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a> then</line>
<line>            <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
<line></line>
<line>        if boolean IMPLEMENTATION_DEFINED "Apply granule protection check on DC to PoE" then</line>
<line>            <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc;</line>
<line>            <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescDC.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescDC(CacheRecord cache)">CreateAccDescDC</a>(cache);</line>
<line>            memaddrdesc.paddress     = cache.paddress;</line>
<line>            memaddrdesc.fault.gpcf   = <a link="impl-shared.GranuleProtectionCheck.2" file="shared_pseudocode.xml" hover="function: GPCFRecord GranuleProtectionCheck(AddressDescriptor addrdesc, AccessDescriptor accdesc)">GranuleProtectionCheck</a>(memaddrdesc, accdesc);</line>
<line></line>
<line>            if memaddrdesc.fault.gpcf.gpf != <a link="GPCF_None" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_None</a> then</line>
<line>                memaddrdesc.fault.statuscode = <a link="Fault_GPCFOnOutput" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_GPCFOnOutput</a>;</line>
<line>                memaddrdesc.fault.paddress   = memaddrdesc.paddress;</line>
<line>                <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(bits(64) UNKNOWN, memaddrdesc.fault);</line>
<line>    else</line>
<line>        cache.vaddress     = vaddress;</line>
<line>        cache.translated   = FALSE;</line>
<line>        cache.shareability = <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> UNKNOWN;</line>
<line>        cache.paddress     = <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> UNKNOWN;</line>
<line></line>
<line>    if (cacheop == <a link="CacheOp_Invalidate" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_Invalidate</a> &amp;&amp; PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>            HCR_EL2.&lt;DC,VM&gt; != '00') then</line>
<line>        cache.cacheop = <a link="CacheOp_CleanInvalidate" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_CleanInvalidate</a>;</line>
<line></line>
<line>    <a link="impl-shared.CACHE_OP.1" file="shared_pseudocode.xml" hover="function: CACHE_OP(CacheRecord cache)">CACHE_OP</a>(cache);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/dc/AArch64.MemZero" mylink="aarch64.instrs.system.sysops.dc.AArch64.MemZero" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.MemZero()</line>
<line>// =================</line>
<line></line>
<line link="AArch64.MemZero.2" hover="function: AArch64.MemZero(bits(64) regval, CacheType cachetype)" conts="AArch64.MemZero"><anchor link="AArch64.MemZero.2" hover="function: AArch64.MemZero(bits(64) regval, CacheType cachetype)">AArch64.MemZero</anchor>(bits(64) regval, <a link="CacheType" file="shared_pseudocode.xml" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }">CacheType</a> cachetype)</line>
<line>    integer size = 4*(2^(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(DCZID_EL0.BS)));</line>
<line>    assert size &lt;= <a link="MAX_ZERO_BLOCK_SIZE" file="shared_pseudocode.xml" hover="constant integer MAX_ZERO_BLOCK_SIZE = 2048">MAX_ZERO_BLOCK_SIZE</a>;</line>
<line>    if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() then</line>
<line>        assert size &gt;= <a link="TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer TAG_GRANULE = 1 &lt;&lt; LOG2_TAG_GRANULE">TAG_GRANULE</a>;</line>
<line></line>
<line>    bits(64) vaddress = <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(regval, size);</line>
<line></line>
<line>    boolean tagaccess = cachetype IN {<a link="CacheType_Tag" file="shared_pseudocode.xml" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }">CacheType_Tag</a>, <a link="CacheType_Data_Tag" file="shared_pseudocode.xml" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }">CacheType_Data_Tag</a>};</line>
<line>    boolean tagchecked = cachetype == <a link="CacheType_Data" file="shared_pseudocode.xml" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }">CacheType_Data</a>;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescDCZero.2" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescDCZero(boolean tagaccess, boolean tagchecked)">CreateAccDescDCZero</a>(tagaccess, tagchecked);</line>
<line></line>
<line>    if cachetype IN {<a link="CacheType_Tag" file="shared_pseudocode.xml" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }">CacheType_Tag</a>, <a link="CacheType_Data_Tag" file="shared_pseudocode.xml" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }">CacheType_Data_Tag</a>} then</line>
<line>        <a link="AArch64.TagMemZero.4" file="shared_pseudocode.xml" hover="function: AArch64.TagMemZero(bits(64) regval, bits(64) vaddress, AccessDescriptor accdesc_in, integer size)">AArch64.TagMemZero</a>(regval, vaddress, accdesc, size);</line>
<line></line>
<line>    if cachetype IN {<a link="CacheType_Data" file="shared_pseudocode.xml" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }">CacheType_Data</a>, <a link="CacheType_Data_Tag" file="shared_pseudocode.xml" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }">CacheType_Data_Tag</a>} then</line>
<line>        <a link="AArch64.DataMemZero.4" file="shared_pseudocode.xml" hover="function: AArch64.DataMemZero(bits(64) regval, bits(64) vaddress, AccessDescriptor accdesc_in, integer size)">AArch64.DataMemZero</a>(regval, vaddress, accdesc, size);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/dc/MemZero" mylink="aarch64.instrs.system.sysops.dc.MemZero" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="MAX_ZERO_BLOCK_SIZE" hover="constant integer MAX_ZERO_BLOCK_SIZE = 2048" conts="MAX_ZERO_BLOCK_SIZE">constant integer <anchor link="MAX_ZERO_BLOCK_SIZE" hover="constant integer MAX_ZERO_BLOCK_SIZE = 2048">MAX_ZERO_BLOCK_SIZE</anchor> = 2048;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/ic/AArch64.IC" mylink="aarch64.instrs.system.sysops.ic.AArch64.IC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.IC()</line>
<line>// ============</line>
<line>// Perform Instruction Cache Operation.</line>
<line></line>
<line link="AArch64.IC.1" hover="function: AArch64.IC(CacheOpScope opscope)" conts="AArch64.IC"><anchor link="AArch64.IC.1" hover="function: AArch64.IC(CacheOpScope opscope)">AArch64.IC</anchor>(<a link="CacheOpScope" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope</a> opscope)</line>
<line>    regval = bits(64) UNKNOWN;</line>
<line>    <a link="AArch64.IC.2" file="shared_pseudocode.xml" hover="function: AArch64.IC(bits(64) regval, CacheOpScope opscope)">AArch64.IC</a>(regval, opscope);</line>
<line></line>
<line>// AArch64.IC()</line>
<line>// ============</line>
<line>// Perform Instruction Cache Operation.</line>
<line></line>
<line link="AArch64.IC.2" hover="function: AArch64.IC(bits(64) regval, CacheOpScope opscope)" conts="AArch64.IC"><anchor link="AArch64.IC.2" hover="function: AArch64.IC(bits(64) regval, CacheOpScope opscope)">AArch64.IC</anchor>(bits(64) regval, <a link="CacheOpScope" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope</a> opscope)</line>
<line>    <a link="CacheRecord" file="shared_pseudocode.xml" hover="type CacheRecord is ( AccessType acctype, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, bits(64) regval, FullAddress paddress, bits(64) vaddress, integer set, integer way, integer level, Shareability shareability, boolean translated, boolean is_vmid_valid, bits(16) vmid, boolean is_asid_valid, bits(16) asid, SecurityState security, CachePASpace cpas )">CacheRecord</a> cache;</line>
<line></line>
<line>    cache.acctype   = <a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a>;</line>
<line>    cache.cachetype = <a link="CacheType_Instruction" file="shared_pseudocode.xml" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }">CacheType_Instruction</a>;</line>
<line>    cache.cacheop   = <a link="CacheOp_Invalidate" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_Invalidate</a>;</line>
<line>    cache.opscope   = opscope;</line>
<line></line>
<line>    if opscope IN {<a link="CacheOpScope_ALLU" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_ALLU</a>, <a link="CacheOpScope_ALLUIS" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_ALLUIS</a>} then</line>
<line>        ss = <a link="impl-shared.SecurityStateAtEL.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)">SecurityStateAtEL</a>(PSTATE.EL);</line>
<line>        cache.cpas = <a link="impl-shared.CPASAtSecurityState.1" file="shared_pseudocode.xml" hover="function: CachePASpace CPASAtSecurityState(SecurityState ss)">CPASAtSecurityState</a>(ss);</line>
<line>        if (opscope == <a link="CacheOpScope_ALLUIS" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_ALLUIS</a> || (opscope == <a link="CacheOpScope_ALLU" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_ALLU</a> &amp;&amp; PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.FB == '1')) then</line>
<line>            cache.shareability = <a link="Shareability_ISH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_ISH</a>;</line>
<line>        else</line>
<line>            cache.shareability = <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a>;</line>
<line>        cache.regval = regval;</line>
<line>        <a link="impl-shared.CACHE_OP.1" file="shared_pseudocode.xml" hover="function: CACHE_OP(CacheRecord cache)">CACHE_OP</a>(cache);</line>
<line>    else</line>
<line>        assert opscope == <a link="CacheOpScope_PoU" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_PoU</a>;</line>
<line></line>
<line>        if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>            if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} then</line>
<line>                cache.is_vmid_valid = TRUE;</line>
<line>                cache.vmid          = <a link="impl-aarch64.VMID.read.0" file="shared_pseudocode.xml" hover="accessor: bits(16) VMID[]">VMID</a>[];</line>
<line>            else</line>
<line>                cache.is_vmid_valid = FALSE;</line>
<line>        else</line>
<line>            cache.is_vmid_valid = FALSE;</line>
<line></line>
<line>        if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>            cache.is_asid_valid = TRUE;</line>
<line>            cache.asid          = <a link="impl-shared.ASID.read.0" file="shared_pseudocode.xml" hover="accessor: bits(16) ASID[]">ASID</a>[];</line>
<line>        else</line>
<line>            cache.is_asid_valid = FALSE;</line>
<line></line>
<line>        bits(64) vaddress = regval;</line>
<line>        boolean need_translate = <a link="impl-shared.ICInstNeedsTranslation.1" file="shared_pseudocode.xml" hover="function: boolean ICInstNeedsTranslation(CacheOpScope opscope)">ICInstNeedsTranslation</a>(opscope);</line>
<line></line>
<line>        cache.vaddress     = regval;</line>
<line>        cache.shareability = <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a>;</line>
<line>        cache.translated   = need_translate;</line>
<line></line>
<line>        if !need_translate then</line>
<line>            cache.paddress = <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> UNKNOWN;</line>
<line>            <a link="impl-shared.CACHE_OP.1" file="shared_pseudocode.xml" hover="function: CACHE_OP(CacheRecord cache)">CACHE_OP</a>(cache);</line>
<line>            return;</line>
<line></line>
<line>        <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescIC.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescIC(CacheRecord cache)">CreateAccDescIC</a>(cache);</line>
<line>        boolean aligned = TRUE;</line>
<line>        integer size = 0;</line>
<line>        <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc = <a link="AArch64.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch64.TranslateAddress(bits(64) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch64.TranslateAddress</a>(vaddress, accdesc, aligned, size);</line>
<line></line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memaddrdesc) then</line>
<line>            <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(regval, memaddrdesc.fault);</line>
<line></line>
<line>        cache.cpas     = <a link="impl-shared.CPASAtPAS.1" file="shared_pseudocode.xml" hover="function: CachePASpace CPASAtPAS(PASpace pas)">CPASAtPAS</a>(memaddrdesc.paddress.paspace);</line>
<line>        cache.paddress = memaddrdesc.paddress;</line>
<line>        <a link="impl-shared.CACHE_OP.1" file="shared_pseudocode.xml" hover="function: CACHE_OP(CacheRecord cache)">CACHE_OP</a>(cache);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/predictionrestrict/AArch64.RestrictPrediction" mylink="aarch64.instrs.system.sysops.predictionrestrict.AArch64.RestrictPrediction" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.RestrictPrediction()</line>
<line>// ============================</line>
<line>// Clear all predictions in the context.</line>
<line></line>
<line link="AArch64.RestrictPrediction.2" hover="function: AArch64.RestrictPrediction(bits(64) val, RestrictType restriction)" conts="AArch64.RestrictPrediction"><anchor link="AArch64.RestrictPrediction.2" hover="function: AArch64.RestrictPrediction(bits(64) val, RestrictType restriction)">AArch64.RestrictPrediction</anchor>(bits(64) val, <a link="RestrictType" file="shared_pseudocode.xml" hover="enumeration RestrictType { RestrictType_DataValue, RestrictType_ControlFlow, RestrictType_CachePrefetch, RestrictType_Other }">RestrictType</a> restriction)</line>
<line></line>
<line>    <a link="ExecutionCntxt" file="shared_pseudocode.xml" hover="type ExecutionCntxt is ( boolean is_vmid_valid, boolean all_vmid, bits(16) vmid, boolean is_asid_valid, boolean all_asid, bits(16) asid, bits(2) target_el, SecurityState security, RestrictType restriction )">ExecutionCntxt</a> c;</line>
<line>    target_el    = val&lt;25:24&gt;;</line>
<line></line>
<line>    // If the target EL is not implemented or the instruction is executed at an</line>
<line>    // EL lower than the specified level, the instruction is treated as a NOP.</line>
<line>    if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(target_el) || <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(target_el) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL) then <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
<line></line>
<line>    bit ns  = val&lt;26&gt;;</line>
<line>    bit nse = val&lt;27&gt;;</line>
<line>    ss = <a link="impl-shared.TargetSecurityState.2" file="shared_pseudocode.xml" hover="function: SecurityState TargetSecurityState(bit NS, bit NSE)">TargetSecurityState</a>(ns, nse);</line>
<line></line>
<line>    // If the combination of Security state and Exception level is not implemented,</line>
<line>    // the instruction is treated as a NOP.</line>
<line>    if ss == <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a> &amp;&amp; target_el != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
<line>    if !<a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() &amp;&amp; target_el == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> &amp;&amp; ss != <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
<line></line>
<line>    c.security  = ss;</line>
<line>    c.target_el = target_el;</line>
<line></line>
<line>    if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        if (PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>()) || PSTATE.EL == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> then</line>
<line>            c.is_vmid_valid = TRUE;</line>
<line>            c.all_vmid      = FALSE;</line>
<line>            c.vmid          = <a link="impl-aarch64.VMID.read.0" file="shared_pseudocode.xml" hover="accessor: bits(16) VMID[]">VMID</a>[];</line>
<line></line>
<line>        elsif (target_el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.ELIsInHost.1" file="shared_pseudocode.xml" hover="function: boolean ELIsInHost(bits(2) el)">ELIsInHost</a>(target_el)) || target_el == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> then</line>
<line>            c.is_vmid_valid = TRUE;</line>
<line>            c.all_vmid      = val&lt;48&gt; == '1';</line>
<line>            c.vmid          = val&lt;47:32&gt;;       // Only valid if  val&lt;48&gt; == '0';</line>
<line></line>
<line>        else</line>
<line>            c.is_vmid_valid = FALSE;</line>
<line>    else</line>
<line>        c.is_vmid_valid = FALSE;</line>
<line></line>
<line>    if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        c.is_asid_valid = TRUE;</line>
<line>        c.all_asid      = FALSE;</line>
<line>        c.asid          = <a link="impl-shared.ASID.read.0" file="shared_pseudocode.xml" hover="accessor: bits(16) ASID[]">ASID</a>[];</line>
<line></line>
<line>    elsif target_el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        c.is_asid_valid = TRUE;</line>
<line>        c.all_asid      = val&lt;16&gt; == '1';</line>
<line>        c.asid          = val&lt;15:0&gt;;            // Only valid if  val&lt;16&gt; == '0';</line>
<line></line>
<line>    else</line>
<line>        c.is_asid_valid = FALSE;</line>
<line></line>
<line>    c.restriction = restriction;</line>
<line>    <a link="impl-shared.RESTRICT_PREDICTIONS.1" file="shared_pseudocode.xml" hover="function: RESTRICT_PREDICTIONS(ExecutionCntxt c)">RESTRICT_PREDICTIONS</a>(c);</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/sysop/SysOp" mylink="aarch64.instrs.system.sysops.sysop.SysOp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SysOp()</line>
<line>// =======</line>
<line></line>
<line link="impl-aarch64.SysOp.4" hover="function: SystemOp SysOp(bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2)" conts="SysOp">SystemOp <anchor link="impl-aarch64.SysOp.4" hover="function: SystemOp SysOp(bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2)">SysOp</anchor>(bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2)</line>
<line>    case op1:CRn:CRm:op2 of</line>
<line>        when '000 0111 1000 000' return <a link="Sys_AT" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_AT</a>;    // S1E1R</line>
<line>        when '000 0111 1000 001' return <a link="Sys_AT" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_AT</a>;    // S1E1W</line>
<line>        when '000 0111 1000 010' return <a link="Sys_AT" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_AT</a>;    // S1E0R</line>
<line>        when '000 0111 1000 011' return <a link="Sys_AT" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_AT</a>;    // S1E0W</line>
<line>        when '000 0111 1001 000' return <a link="Sys_AT" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_AT</a>;    // S1E1RP</line>
<line>        when '000 0111 1001 001' return <a link="Sys_AT" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_AT</a>;    // S1E1WP</line>
<line>        when '100 0111 1000 000' return <a link="Sys_AT" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_AT</a>;    // S1E2R</line>
<line>        when '100 0111 1000 001' return <a link="Sys_AT" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_AT</a>;    // S1E2W</line>
<line>        when '100 0111 1000 100' return <a link="Sys_AT" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_AT</a>;    // S12E1R</line>
<line>        when '100 0111 1000 101' return <a link="Sys_AT" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_AT</a>;    // S12E1W</line>
<line>        when '100 0111 1000 110' return <a link="Sys_AT" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_AT</a>;    // S12E0R</line>
<line>        when '100 0111 1000 111' return <a link="Sys_AT" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_AT</a>;    // S12E0W</line>
<line>        when '110 0111 1000 000' return <a link="Sys_AT" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_AT</a>;    // S1E3R</line>
<line>        when '110 0111 1000 001' return <a link="Sys_AT" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_AT</a>;    // S1E3W</line>
<line>        when '001 0111 0010 100' return <a link="Sys_BRB" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_BRB</a>;   // IALL</line>
<line>        when '001 0111 0010 101' return <a link="Sys_BRB" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_BRB</a>;   // INJ</line>
<line>        when '000 0111 0110 001' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // IVAC</line>
<line>        when '000 0111 0110 010' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // ISW</line>
<line>        when '000 0111 0110 011' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // IGVAC</line>
<line>        when '000 0111 0110 100' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // IGSW</line>
<line>        when '000 0111 0110 101' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // IGDVAC</line>
<line>        when '000 0111 0110 110' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // IGDSW</line>
<line>        when '000 0111 1010 010' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CSW</line>
<line>        when '000 0111 1010 100' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CGSW</line>
<line>        when '000 0111 1010 110' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CGDSW</line>
<line>        when '000 0111 1110 010' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CISW</line>
<line>        when '000 0111 1110 100' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CIGSW</line>
<line>        when '000 0111 1110 110' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CIGDSW</line>
<line>        when '011 0111 0100 001' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // ZVA</line>
<line>        when '011 0111 0100 011' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // GVA</line>
<line>        when '011 0111 0100 100' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // GZVA</line>
<line>        when '011 0111 1010 001' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CVAC</line>
<line>        when '011 0111 1010 011' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CGVAC</line>
<line>        when '011 0111 1010 101' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CGDVAC</line>
<line>        when '011 0111 1011 001' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CVAU</line>
<line>        when '011 0111 1100 001' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CVAP</line>
<line>        when '011 0111 1100 011' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CGVAP</line>
<line>        when '011 0111 1100 101' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CGDVAP</line>
<line>        when '011 0111 1101 001' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CVADP</line>
<line>        when '011 0111 1101 011' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CGVADP</line>
<line>        when '011 0111 1101 101' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CGDVADP</line>
<line>        when '011 0111 1110 001' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CIVAC</line>
<line>        when '011 0111 1110 011' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CIGVAC</line>
<line>        when '011 0111 1110 101' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CIGDVAC</line>
<line>        when '100 0111 1110 000' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CIPAE</line>
<line>        when '100 0111 1110 111' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CIGDPAE</line>
<line>        when '110 0111 1110 001' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CIPAPA</line>
<line>        when '110 0111 1110 101' return <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a>;    // CIGDPAPA</line>
<line>        when '000 0111 0001 000' return <a link="Sys_IC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_IC</a>;    // IALLUIS</line>
<line>        when '000 0111 0101 000' return <a link="Sys_IC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_IC</a>;    // IALLU</line>
<line>        when '011 0111 0101 001' return <a link="Sys_IC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_IC</a>;    // IVAU</line>
<line>        when '000 1000 0001 000' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VMALLE1OS</line>
<line>        when '000 1000 0001 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAE1OS</line>
<line>        when '000 1000 0001 010' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ASIDE1OS</line>
<line>        when '000 1000 0001 011' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAAE1OS</line>
<line>        when '000 1000 0001 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VALE1OS</line>
<line>        when '000 1000 0001 111' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAALE1OS</line>
<line>        when '000 1000 0010 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAE1IS</line>
<line>        when '000 1000 0010 011' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAAE1IS</line>
<line>        when '000 1000 0010 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVALE1IS</line>
<line>        when '000 1000 0010 111' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAALE1IS</line>
<line>        when '000 1000 0011 000' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VMALLE1IS</line>
<line>        when '000 1000 0011 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAE1IS</line>
<line>        when '000 1000 0011 010' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ASIDE1IS</line>
<line>        when '000 1000 0011 011' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAAE1IS</line>
<line>        when '000 1000 0011 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VALE1IS</line>
<line>        when '000 1000 0011 111' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAALE1IS</line>
<line>        when '000 1000 0101 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAE1OS</line>
<line>        when '000 1000 0101 011' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAAE1OS</line>
<line>        when '000 1000 0101 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVALE1OS</line>
<line>        when '000 1000 0101 111' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAALE1OS</line>
<line>        when '000 1000 0110 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAE1</line>
<line>        when '000 1000 0110 011' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAAE1</line>
<line>        when '000 1000 0110 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVALE1</line>
<line>        when '000 1000 0110 111' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAALE1</line>
<line>        when '000 1000 0111 000' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VMALLE1</line>
<line>        when '000 1000 0111 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAE1</line>
<line>        when '000 1000 0111 010' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ASIDE1</line>
<line>        when '000 1000 0111 011' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAAE1</line>
<line>        when '000 1000 0111 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VALE1</line>
<line>        when '000 1000 0111 111' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAALE1</line>
<line>        when '000 1001 0001 000' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VMALLE1OSNXS</line>
<line>        when '000 1001 0001 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAE1OSNXS</line>
<line>        when '000 1001 0001 010' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ASIDE1OSNXS</line>
<line>        when '000 1001 0001 011' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAAE1OSNXS</line>
<line>        when '000 1001 0001 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VALE1OSNXS</line>
<line>        when '000 1001 0001 111' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAALE1OSNXS</line>
<line>        when '000 1001 0010 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAE1ISNXS</line>
<line>        when '000 1001 0010 011' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAAE1ISNXS</line>
<line>        when '000 1001 0010 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVALE1ISNXS</line>
<line>        when '000 1001 0010 111' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAALE1ISNXS</line>
<line>        when '000 1001 0011 000' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VMALLE1ISNXS</line>
<line>        when '000 1001 0011 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAE1ISNXS</line>
<line>        when '000 1001 0011 010' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ASIDE1ISNXS</line>
<line>        when '000 1001 0011 011' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAAE1ISNXS</line>
<line>        when '000 1001 0011 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VALE1ISNXS</line>
<line>        when '000 1001 0011 111' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAALE1ISNXS</line>
<line>        when '000 1001 0101 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAE1OSNXS</line>
<line>        when '000 1001 0101 011' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAAE1OSNXS</line>
<line>        when '000 1001 0101 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVALE1OSNXS</line>
<line>        when '000 1001 0101 111' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAALE1OSNXS</line>
<line>        when '000 1001 0110 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAE1NXS</line>
<line>        when '000 1001 0110 011' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAAE1NXS</line>
<line>        when '000 1001 0110 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVALE1NXS</line>
<line>        when '000 1001 0110 111' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAALE1NXS</line>
<line>        when '000 1001 0111 000' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VMALLE1NXS</line>
<line>        when '000 1001 0111 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAE1NXS</line>
<line>        when '000 1001 0111 010' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ASIDE1NXS</line>
<line>        when '000 1001 0111 011' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAAE1NXS</line>
<line>        when '000 1001 0111 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VALE1NXS</line>
<line>        when '000 1001 0111 111' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAALE1NXS</line>
<line>        when '100 1000 0000 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // IPAS2E1IS</line>
<line>        when '100 1000 0000 010' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RIPAS2E1IS</line>
<line>        when '100 1000 0000 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // IPAS2LE1IS</line>
<line>        when '100 1000 0000 110' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RIPAS2LE1IS</line>
<line>        when '100 1000 0001 000' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ALLE2OS</line>
<line>        when '100 1000 0001 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAE2OS</line>
<line>        when '100 1000 0001 100' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ALLE1OS</line>
<line>        when '100 1000 0001 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VALE2OS</line>
<line>        when '100 1000 0001 110' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VMALLS12E1OS</line>
<line>        when '100 1000 0010 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAE2IS</line>
<line>        when '100 1000 0010 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVALE2IS</line>
<line>        when '100 1000 0011 000' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ALLE2IS</line>
<line>        when '100 1000 0011 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAE2IS</line>
<line>        when '100 1000 0011 100' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ALLE1IS</line>
<line>        when '100 1000 0011 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VALE2IS</line>
<line>        when '100 1000 0011 110' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VMALLS12E1IS</line>
<line>        when '100 1000 0100 000' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // IPAS2E1OS</line>
<line>        when '100 1000 0100 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // IPAS2E1</line>
<line>        when '100 1000 0100 010' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RIPAS2E1</line>
<line>        when '100 1000 0100 011' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RIPAS2E1OS</line>
<line>        when '100 1000 0100 100' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // IPAS2LE1OS</line>
<line>        when '100 1000 0100 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // IPAS2LE1</line>
<line>        when '100 1000 0100 110' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RIPAS2LE1</line>
<line>        when '100 1000 0100 111' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RIPAS2LE1OS</line>
<line>        when '100 1000 0101 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAE2OS</line>
<line>        when '100 1000 0101 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVALE2OS</line>
<line>        when '100 1000 0110 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAE2</line>
<line>        when '100 1000 0110 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVALE2</line>
<line>        when '100 1000 0111 000' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ALLE2</line>
<line>        when '100 1000 0111 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAE2</line>
<line>        when '100 1000 0111 100' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ALLE1</line>
<line>        when '100 1000 0111 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VALE2</line>
<line>        when '100 1000 0111 110' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VMALLS12E1</line>
<line>        when '100 1001 0000 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // IPAS2E1ISNXS</line>
<line>        when '100 1001 0000 010' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RIPAS2E1ISNXS</line>
<line>        when '100 1001 0000 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // IPAS2LE1ISNXS</line>
<line>        when '100 1001 0000 110' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RIPAS2LE1ISNXS</line>
<line>        when '100 1001 0001 000' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ALLE2OSNXS</line>
<line>        when '100 1001 0001 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAE2OSNXS</line>
<line>        when '100 1001 0001 100' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ALLE1OSNXS</line>
<line>        when '100 1001 0001 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VALE2OSNXS</line>
<line>        when '100 1001 0001 110' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VMALLS12E1OSNXS</line>
<line>        when '100 1001 0010 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAE2ISNXS</line>
<line>        when '100 1001 0010 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVALE2ISNXS</line>
<line>        when '100 1001 0011 000' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ALLE2ISNXS</line>
<line>        when '100 1001 0011 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAE2ISNXS</line>
<line>        when '100 1001 0011 100' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ALLE1ISNXS</line>
<line>        when '100 1001 0011 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VALE2ISNXS</line>
<line>        when '100 1001 0011 110' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VMALLS12E1ISNXS</line>
<line>        when '100 1001 0100 000' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // IPAS2E1OSNXS</line>
<line>        when '100 1001 0100 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // IPAS2E1NXS</line>
<line>        when '100 1001 0100 010' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RIPAS2E1NXS</line>
<line>        when '100 1001 0100 011' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RIPAS2E1OSNXS</line>
<line>        when '100 1001 0100 100' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // IPAS2LE1OSNXS</line>
<line>        when '100 1001 0100 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // IPAS2LE1NXS</line>
<line>        when '100 1001 0100 110' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RIPAS2LE1NXS</line>
<line>        when '100 1001 0100 111' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RIPAS2LE1OSNXS</line>
<line>        when '100 1001 0101 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAE2OSNXS</line>
<line>        when '100 1001 0101 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVALE2OSNXS</line>
<line>        when '100 1001 0110 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAE2NXS</line>
<line>        when '100 1001 0110 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVALE2NXS</line>
<line>        when '100 1001 0111 000' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ALLE2NXS</line>
<line>        when '100 1001 0111 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAE2NXS</line>
<line>        when '100 1001 0111 100' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ALLE1NXS</line>
<line>        when '100 1001 0111 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VALE2NXS</line>
<line>        when '100 1001 0111 110' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VMALLS12E1NXS</line>
<line>        when '110 1000 0001 000' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ALLE3OS</line>
<line>        when '110 1000 0001 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAE3OS</line>
<line>        when '110 1000 0001 100' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // PAALLOS</line>
<line>        when '110 1000 0001 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VALE3OS</line>
<line>        when '110 1000 0010 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAE3IS</line>
<line>        when '110 1000 0010 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVALE3IS</line>
<line>        when '110 1000 0011 000' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ALLE3IS</line>
<line>        when '110 1000 0011 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAE3IS</line>
<line>        when '110 1000 0011 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VALE3IS</line>
<line>        when '110 1000 0100 011' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RPAOS</line>
<line>        when '110 1000 0100 111' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RPALOS</line>
<line>        when '110 1000 0101 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAE3OS</line>
<line>        when '110 1000 0101 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVALE3OS</line>
<line>        when '110 1000 0110 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAE3</line>
<line>        when '110 1000 0110 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVALE3</line>
<line>        when '110 1000 0111 000' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ALLE3</line>
<line>        when '110 1000 0111 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAE3</line>
<line>        when '110 1000 0111 100' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // PAALL</line>
<line>        when '110 1000 0111 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VALE3</line>
<line>        when '110 1001 0001 000' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ALLE3OSNXS</line>
<line>        when '110 1001 0001 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAE3OSNXS</line>
<line>        when '110 1001 0001 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VALE3OSNXS</line>
<line>        when '110 1001 0010 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAE3ISNXS</line>
<line>        when '110 1001 0010 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVALE3ISNXS</line>
<line>        when '110 1001 0011 000' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ALLE3ISNXS</line>
<line>        when '110 1001 0011 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAE3ISNXS</line>
<line>        when '110 1001 0011 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VALE3ISNXS</line>
<line>        when '110 1001 0101 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAE3OSNXS</line>
<line>        when '110 1001 0101 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVALE3OSNXS</line>
<line>        when '110 1001 0110 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVAE3NXS</line>
<line>        when '110 1001 0110 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // RVALE3NXS</line>
<line>        when '110 1001 0111 000' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // ALLE3NXS</line>
<line>        when '110 1001 0111 001' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VAE3NXS</line>
<line>        when '110 1001 0111 101' return <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a>;  // VALE3NXS</line>
<line>        otherwise                return <a link="Sys_SYS" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_SYS</a>;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/sysop/SystemOp" mylink="aarch64.instrs.system.sysops.sysop.SystemOp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SystemOp</line>
<line>// ========</line>
<line>// System instruction types.</line>
<line></line>
<line link="SystemOp" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}" conts="SystemOp">enumeration <anchor link="SystemOp" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">SystemOp</anchor> {<anchor link="Sys_AT" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_AT</anchor>, <anchor link="Sys_BRB" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_BRB</anchor>, <anchor link="Sys_DC" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</anchor>, <anchor link="Sys_IC" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_IC</anchor>, <anchor link="Sys_TLBI" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</anchor>, <anchor link="Sys_SYS" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_SYS</anchor>};</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/AArch64.TLBIP_IPAS2" mylink="aarch64.instrs.system.sysops.tlbi.AArch64.TLBIP_IPAS2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TLBIP_IPAS2()</line>
<line>// =====================</line>
<line>// Invalidate by IPA all stage 2 only TLB entries in the indicated shareability</line>
<line>// domain matching the indicated VMID in the indicated regime with the indicated security state.</line>
<line>// Note: stage 1 and stage 2 combined entries are not in the scope of this operation.</line>
<line>// IPA and related parameters of the are derived from Xt.</line>
<line></line>
<line link="AArch64.TLBIP_IPAS2.7" hover="function: AArch64.TLBIP_IPAS2(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr, bits(128) Xt)" conts="AArch64.TLBIP_IPAS2"><anchor link="AArch64.TLBIP_IPAS2.7" hover="function: AArch64.TLBIP_IPAS2(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr, bits(128) Xt)">AArch64.TLBIP_IPAS2</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                    <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBILevel" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel</a> level, <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr, bits(128) Xt)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_IPAS2" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_IPAS2</a>;</line>
<line>    r.from_aarch64 = TRUE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.level        = level;</line>
<line>    r.attr         = attr;</line>
<line>    r.ttl          = Xt&lt;47:44&gt;;</line>
<line>    r.address      = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(Xt&lt;107:64&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12), 64);</line>
<line>    r.d64          = r.ttl IN {'00xx'};</line>
<line>    r.d128         = TRUE;</line>
<line></line>
<line>    case security of</line>
<line>        when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a></line>
<line>            r.ipaspace = <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line>        when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a></line>
<line>            r.ipaspace = if Xt&lt;63&gt; == '1' then <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a> else <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a>;</line>
<line>        when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a></line>
<line>            r.ipaspace = <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a>;</line>
<line>        otherwise</line>
<line>            // Root security state does not have stage 2 translation</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    <a link="impl-aarch64.TLBI.1" file="shared_pseudocode.xml" hover="function: TLBI(TLBIRecord r)">TLBI</a>(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then <a link="impl-aarch64.Broadcast.2" file="shared_pseudocode.xml" hover="function: Broadcast(Shareability shareability, TLBIRecord r)">Broadcast</a>(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/AArch64.TLBIP_RIPAS2" mylink="aarch64.instrs.system.sysops.tlbi.AArch64.TLBIP_RIPAS2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TLBIP_RIPAS2()</line>
<line>// ======================</line>
<line>// Range invalidate by IPA all stage 2 only TLB entries in the indicated</line>
<line>// shareability domain matching the indicated VMID in the indicated regime with the indicated</line>
<line>// security state.</line>
<line>// Note: stage 1 and stage 2 combined entries are not in the scope of this operation.</line>
<line>// The range of IPA and related parameters of the are derived from Xt.</line>
<line></line>
<line link="AArch64.TLBIP_RIPAS2.7" hover="function: AArch64.TLBIP_RIPAS2(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr, bits(128) Xt)" conts="AArch64.TLBIP_RIPAS2"><anchor link="AArch64.TLBIP_RIPAS2.7" hover="function: AArch64.TLBIP_RIPAS2(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr, bits(128) Xt)">AArch64.TLBIP_RIPAS2</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                     <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBILevel" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel</a> level, <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr, bits(128) Xt)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_RIPAS2" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_RIPAS2</a>;</line>
<line>    r.from_aarch64 = TRUE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.level        = level;</line>
<line>    r.attr         = attr;</line>
<line>    r.ttl&lt;1:0&gt;     = Xt&lt;38:37&gt;;</line>
<line>    r.d64          = r.ttl&lt;1:0&gt; == '00';</line>
<line>    r.d128         = TRUE;</line>
<line></line>
<line>    bits(2) tg        = Xt&lt;47:46&gt;;</line>
<line>    integer scale     = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt&lt;45:44&gt;);</line>
<line>    integer num       = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt&lt;43:39&gt;);</line>
<line>    integer baseaddr  = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(Xt&lt;36:0&gt;);</line>
<line></line>
<line>    boolean valid;</line>
<line></line>
<line>    (valid, r.tg, r.address, r.end_address) = <a link="impl-aarch64.TLBIPRange.2" file="shared_pseudocode.xml" hover="function: (boolean, bits(2), bits(64), bits(64)) TLBIPRange(Regime regime, bits(128) Xt)">TLBIPRange</a>(regime, Xt);</line>
<line></line>
<line>    if !valid then return;</line>
<line></line>
<line>    case security of</line>
<line>        when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a></line>
<line>            r.ipaspace = <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line>        when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a></line>
<line>            r.ipaspace = if Xt&lt;63&gt; == '1' then <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a> else <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a>;</line>
<line>        when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a></line>
<line>            r.ipaspace = <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a>;</line>
<line>        otherwise</line>
<line>            // Root security state does not have stage 2 translation</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    <a link="impl-aarch64.TLBI.1" file="shared_pseudocode.xml" hover="function: TLBI(TLBIRecord r)">TLBI</a>(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then <a link="impl-aarch64.Broadcast.2" file="shared_pseudocode.xml" hover="function: Broadcast(Shareability shareability, TLBIRecord r)">Broadcast</a>(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/AArch64.TLBIP_RVA" mylink="aarch64.instrs.system.sysops.tlbi.AArch64.TLBIP_RVA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TLBIP_RVA()</line>
<line>// ===================</line>
<line>// Range invalidate by VA range all stage 1 TLB entries in the indicated</line>
<line>// shareability domain matching the indicated VMID and ASID (where regime</line>
<line>// supports VMID, ASID) in the indicated regime with the indicated security state.</line>
<line>// ASID, and range related parameters are derived from Xt.</line>
<line>// Note: stage 1 and stage 2 combined entries are in the scope of this operation.</line>
<line></line>
<line link="AArch64.TLBIP_RVA.7" hover="function: AArch64.TLBIP_RVA(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr, bits(128)  Xt)" conts="AArch64.TLBIP_RVA"><anchor link="AArch64.TLBIP_RVA.7" hover="function: AArch64.TLBIP_RVA(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr, bits(128)  Xt)">AArch64.TLBIP_RVA</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                  <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBILevel" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel</a> level, <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr, bits(128)  Xt)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_RVA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_RVA</a>;</line>
<line>    r.from_aarch64 = TRUE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.level        = level;</line>
<line>    r.attr         = attr;</line>
<line>    r.asid         = Xt&lt;63:48&gt;;</line>
<line>    r.ttl&lt;1:0&gt;     = Xt&lt;38:37&gt;;</line>
<line>    r.d64          = r.ttl&lt;1:0&gt; == '00';</line>
<line>    r.d128         = TRUE;</line>
<line></line>
<line>    boolean valid;</line>
<line></line>
<line>    (valid, r.tg, r.address, r.end_address) = <a link="impl-aarch64.TLBIPRange.2" file="shared_pseudocode.xml" hover="function: (boolean, bits(2), bits(64), bits(64)) TLBIPRange(Regime regime, bits(128) Xt)">TLBIPRange</a>(regime, Xt);</line>
<line></line>
<line>    if !valid then return;</line>
<line></line>
<line>    <a link="impl-aarch64.TLBI.1" file="shared_pseudocode.xml" hover="function: TLBI(TLBIRecord r)">TLBI</a>(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then <a link="impl-aarch64.Broadcast.2" file="shared_pseudocode.xml" hover="function: Broadcast(Shareability shareability, TLBIRecord r)">Broadcast</a>(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/AArch64.TLBIP_RVAA" mylink="aarch64.instrs.system.sysops.tlbi.AArch64.TLBIP_RVAA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TLBIP_RVAA()</line>
<line>// ====================</line>
<line>// Range invalidate by VA range all stage 1 TLB entries in the indicated</line>
<line>// shareability domain matching the indicated VMID (where regimesupports VMID)</line>
<line>// and all ASID in the indicated regime with the indicated security state.</line>
<line>// VA range related parameters are derived from Xt.</line>
<line>// Note: stage 1 and stage 2 combined entries are in the scope of this operation.</line>
<line></line>
<line link="AArch64.TLBIP_RVAA.7" hover="function: AArch64.TLBIP_RVAA(SecurityState security, Regime  regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr, bits(128) Xt)" conts="AArch64.TLBIP_RVAA"><anchor link="AArch64.TLBIP_RVAA.7" hover="function: AArch64.TLBIP_RVAA(SecurityState security, Regime  regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr, bits(128) Xt)">AArch64.TLBIP_RVAA</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a>  regime, bits(16) vmid,</line>
<line>                   <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBILevel" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel</a> level, <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr, bits(128) Xt)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_RVAA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_RVAA</a>;</line>
<line>    r.from_aarch64 = TRUE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.level        = level;</line>
<line>    r.attr         = attr;</line>
<line>    r.ttl&lt;1:0&gt;     = Xt&lt;38:37&gt;;</line>
<line>    r.d64          = r.ttl&lt;1:0&gt; == '00';</line>
<line>    r.d128         = TRUE;</line>
<line></line>
<line>    bits(2) tg        = Xt&lt;47:46&gt;;</line>
<line>    integer scale     = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt&lt;45:44&gt;);</line>
<line>    integer num       = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt&lt;43:39&gt;);</line>
<line>    integer baseaddr  = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(Xt&lt;36:0&gt;);</line>
<line></line>
<line>    boolean valid;</line>
<line></line>
<line>    (valid, r.tg, r.address, r.end_address) = <a link="impl-aarch64.TLBIPRange.2" file="shared_pseudocode.xml" hover="function: (boolean, bits(2), bits(64), bits(64)) TLBIPRange(Regime regime, bits(128) Xt)">TLBIPRange</a>(regime, Xt);</line>
<line></line>
<line>    if !valid then return;</line>
<line></line>
<line>    <a link="impl-aarch64.TLBI.1" file="shared_pseudocode.xml" hover="function: TLBI(TLBIRecord r)">TLBI</a>(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then <a link="impl-aarch64.Broadcast.2" file="shared_pseudocode.xml" hover="function: Broadcast(Shareability shareability, TLBIRecord r)">Broadcast</a>(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/AArch64.TLBIP_VA" mylink="aarch64.instrs.system.sysops.tlbi.AArch64.TLBIP_VA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TLBIP_VA()</line>
<line>// ==================</line>
<line>// Invalidate by VA all stage 1 TLB entries in the indicated shareability domain</line>
<line>// matching the indicated VMID and ASID (where regime supports VMID, ASID) in the indicated regime</line>
<line>// with the indicated security state.</line>
<line>// ASID, VA and related parameters are derived from Xt.</line>
<line>// Note: stage 1 and stage 2 combined entries are in the scope of this operation.</line>
<line></line>
<line link="AArch64.TLBIP_VA.7" hover="function: AArch64.TLBIP_VA(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level,  TLBIMemAttr attr, bits(128) Xt)" conts="AArch64.TLBIP_VA"><anchor link="AArch64.TLBIP_VA.7" hover="function: AArch64.TLBIP_VA(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level,  TLBIMemAttr attr, bits(128) Xt)">AArch64.TLBIP_VA</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                 <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBILevel" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel</a> level,  <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr, bits(128) Xt)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_VA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_VA</a>;</line>
<line>    r.from_aarch64 = TRUE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.level        = level;</line>
<line>    r.attr         = attr;</line>
<line>    r.asid         = Xt&lt;63:48&gt;;</line>
<line>    r.ttl          = Xt&lt;47:44&gt;;</line>
<line>    r.address      = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(Xt&lt;107:64&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12), 64);</line>
<line>    r.d64          = r.ttl IN {'00xx'};</line>
<line>    r.d128         = TRUE;</line>
<line></line>
<line>    <a link="impl-aarch64.TLBI.1" file="shared_pseudocode.xml" hover="function: TLBI(TLBIRecord r)">TLBI</a>(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then <a link="impl-aarch64.Broadcast.2" file="shared_pseudocode.xml" hover="function: Broadcast(Shareability shareability, TLBIRecord r)">Broadcast</a>(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/AArch64.TLBIP_VAA" mylink="aarch64.instrs.system.sysops.tlbi.AArch64.TLBIP_VAA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TLBIP_VAA()</line>
<line>// ===================</line>
<line>// Invalidate by VA all stage 1 TLB entries in the indicated shareability domain</line>
<line>// matching the indicated VMID (where regime supports VMID) and all ASID in the indicated regime</line>
<line>// with the indicated security state.</line>
<line>// VA and related parameters are derived from Xt.</line>
<line>// Note: stage 1 and stage 2 combined entries are in the scope of this operation.</line>
<line></line>
<line link="AArch64.TLBIP_VAA.7" hover="function: AArch64.TLBIP_VAA(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr,  bits(128) Xt)" conts="AArch64.TLBIP_VAA"><anchor link="AArch64.TLBIP_VAA.7" hover="function: AArch64.TLBIP_VAA(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr,  bits(128) Xt)">AArch64.TLBIP_VAA</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                  <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBILevel" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel</a> level, <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr,  bits(128) Xt)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_VAA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_VAA</a>;</line>
<line>    r.from_aarch64 = TRUE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.level        = level;</line>
<line>    r.attr         = attr;</line>
<line>    r.ttl          = Xt&lt;47:44&gt;;</line>
<line>    r.address      = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(Xt&lt;107:64&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12), 64);</line>
<line>    r.d64          = r.ttl IN {'00xx'};</line>
<line>    r.d128         = TRUE;</line>
<line></line>
<line>    <a link="impl-aarch64.TLBI.1" file="shared_pseudocode.xml" hover="function: TLBI(TLBIRecord r)">TLBI</a>(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then <a link="impl-aarch64.Broadcast.2" file="shared_pseudocode.xml" hover="function: Broadcast(Shareability shareability, TLBIRecord r)">Broadcast</a>(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/AArch64.TLBI_ALL" mylink="aarch64.instrs.system.sysops.tlbi.AArch64.TLBI_ALL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TLBI_ALL()</line>
<line>// ==================</line>
<line>// Invalidate all entries for the indicated translation regime with the</line>
<line>// the indicated security state for all TLBs within the indicated shareability domain.</line>
<line>// Invalidation applies to all applicable stage 1 and stage 2 entries.</line>
<line></line>
<line link="AArch64.TLBI_ALL.4" hover="function: AArch64.TLBI_ALL(SecurityState security, Regime regime, Shareability shareability, TLBIMemAttr attr)" conts="AArch64.TLBI_ALL"><anchor link="AArch64.TLBI_ALL.4" hover="function: AArch64.TLBI_ALL(SecurityState security, Regime regime, Shareability shareability, TLBIMemAttr attr)">AArch64.TLBI_ALL</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_ALL" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_ALL</a>;</line>
<line>    r.from_aarch64 = TRUE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.level        = <a link="TLBILevel_Any" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel_Any</a>;</line>
<line>    r.attr         = attr;</line>
<line></line>
<line>    <a link="impl-aarch64.TLBI.1" file="shared_pseudocode.xml" hover="function: TLBI(TLBIRecord r)">TLBI</a>(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then <a link="impl-aarch64.Broadcast.2" file="shared_pseudocode.xml" hover="function: Broadcast(Shareability shareability, TLBIRecord r)">Broadcast</a>(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/AArch64.TLBI_ASID" mylink="aarch64.instrs.system.sysops.tlbi.AArch64.TLBI_ASID" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TLBI_ASID()</line>
<line>// ===================</line>
<line>// Invalidate all stage 1 entries matching the indicated VMID (where regime supports)</line>
<line>// and ASID in the parameter Xt in the indicated translation regime with the</line>
<line>// indicated security state for all TLBs within the indicated shareability domain.</line>
<line>// Note: stage 1 and stage 2 combined entries are in the scope of this operation.</line>
<line></line>
<line link="AArch64.TLBI_ASID.6" hover="function: AArch64.TLBI_ASID(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBIMemAttr attr, bits(64) Xt)" conts="AArch64.TLBI_ASID"><anchor link="AArch64.TLBI_ASID.6" hover="function: AArch64.TLBI_ASID(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBIMemAttr attr, bits(64) Xt)">AArch64.TLBI_ASID</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                  <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr, bits(64) Xt)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_ASID" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_ASID</a>;</line>
<line>    r.from_aarch64 = TRUE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.level        = <a link="TLBILevel_Any" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel_Any</a>;</line>
<line>    r.attr         = attr;</line>
<line>    r.asid         = Xt&lt;63:48&gt;;</line>
<line></line>
<line>    <a link="impl-aarch64.TLBI.1" file="shared_pseudocode.xml" hover="function: TLBI(TLBIRecord r)">TLBI</a>(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then <a link="impl-aarch64.Broadcast.2" file="shared_pseudocode.xml" hover="function: Broadcast(Shareability shareability, TLBIRecord r)">Broadcast</a>(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/AArch64.TLBI_IPAS2" mylink="aarch64.instrs.system.sysops.tlbi.AArch64.TLBI_IPAS2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TLBI_IPAS2()</line>
<line>// ====================</line>
<line>// Invalidate by IPA all stage 2 only TLB entries in the indicated shareability</line>
<line>// domain matching the indicated VMID in the indicated regime with the indicated security state.</line>
<line>// Note: stage 1 and stage 2 combined entries are not in the scope of this operation.</line>
<line>// IPA and related parameters of the are derived from Xt.</line>
<line></line>
<line link="AArch64.TLBI_IPAS2.7" hover="function: AArch64.TLBI_IPAS2(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr, bits(64) Xt)" conts="AArch64.TLBI_IPAS2"><anchor link="AArch64.TLBI_IPAS2.7" hover="function: AArch64.TLBI_IPAS2(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr, bits(64) Xt)">AArch64.TLBI_IPAS2</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                   <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBILevel" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel</a> level, <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr, bits(64) Xt)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_IPAS2" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_IPAS2</a>;</line>
<line>    r.from_aarch64 = TRUE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.level        = level;</line>
<line>    r.attr         = attr;</line>
<line>    r.ttl          = Xt&lt;47:44&gt;;</line>
<line>    r.address      = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(Xt&lt;39:0&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12), 64);</line>
<line>    r.d64          = TRUE;</line>
<line>    r.d128         = r.ttl IN {'00xx'};</line>
<line></line>
<line>    case security of</line>
<line>        when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a></line>
<line>            r.ipaspace = <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line>        when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a></line>
<line>            r.ipaspace = if Xt&lt;63&gt; == '1' then <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a> else <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a>;</line>
<line>        when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a></line>
<line>            r.ipaspace = <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a>;</line>
<line>        otherwise</line>
<line>            // Root security state does not have stage 2 translation</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    <a link="impl-aarch64.TLBI.1" file="shared_pseudocode.xml" hover="function: TLBI(TLBIRecord r)">TLBI</a>(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then <a link="impl-aarch64.Broadcast.2" file="shared_pseudocode.xml" hover="function: Broadcast(Shareability shareability, TLBIRecord r)">Broadcast</a>(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/AArch64.TLBI_PAALL" mylink="aarch64.instrs.system.sysops.tlbi.AArch64.TLBI_PAALL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TLBI_PAALL()</line>
<line>// ====================</line>
<line>// TLB Invalidate ALL GPT Information.</line>
<line>// Invalidates cached copies of GPT entries from TLBs in the indicated</line>
<line>// Shareabilty domain.</line>
<line>// The invalidation applies to all TLB entries containing GPT information.</line>
<line></line>
<line link="AArch64.TLBI_PAALL.1" hover="function: AArch64.TLBI_PAALL(Shareability shareability)" conts="AArch64.TLBI_PAALL"><anchor link="AArch64.TLBI_PAALL.1" hover="function: AArch64.TLBI_PAALL(Shareability shareability)">AArch64.TLBI_PAALL</anchor>(<a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability)</line>
<line>    assert <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() &amp;&amp; PSTATE.EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line></line>
<line>    // r.security and r.regime do not apply for TLBI by PA operations</line>
<line>    r.op    = <a link="TLBIOp_PAALL" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_PAALL</a>;</line>
<line>    r.level = <a link="TLBILevel_Any" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel_Any</a>;</line>
<line>    r.attr  = <a link="TLBI_AllAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBI_AllAttr</a>;</line>
<line></line>
<line>    <a link="impl-aarch64.TLBI.1" file="shared_pseudocode.xml" hover="function: TLBI(TLBIRecord r)">TLBI</a>(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then <a link="impl-aarch64.Broadcast.2" file="shared_pseudocode.xml" hover="function: Broadcast(Shareability shareability, TLBIRecord r)">Broadcast</a>(shareability, r);</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/AArch64.TLBI_RIPAS2" mylink="aarch64.instrs.system.sysops.tlbi.AArch64.TLBI_RIPAS2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TLBI_RIPAS2()</line>
<line>// =====================</line>
<line>// Range invalidate by IPA all stage 2 only TLB entries in the indicated</line>
<line>// shareability domain matching the indicated VMID in the indicated regime with the indicated</line>
<line>// security state.</line>
<line>// Note: stage 1 and stage 2 combined entries are not in the scope of this operation.</line>
<line>// The range of IPA and related parameters of the are derived from Xt.</line>
<line></line>
<line link="AArch64.TLBI_RIPAS2.7" hover="function: AArch64.TLBI_RIPAS2(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr, bits(64) Xt)" conts="AArch64.TLBI_RIPAS2"><anchor link="AArch64.TLBI_RIPAS2.7" hover="function: AArch64.TLBI_RIPAS2(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr, bits(64) Xt)">AArch64.TLBI_RIPAS2</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                    <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBILevel" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel</a> level, <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr, bits(64) Xt)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_RIPAS2" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_RIPAS2</a>;</line>
<line>    r.from_aarch64 = TRUE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.level        = level;</line>
<line>    r.attr         = attr;</line>
<line>    r.ttl&lt;1:0&gt;     = Xt&lt;38:37&gt;;</line>
<line>    r.d64          = TRUE;</line>
<line>    r.d128         = r.ttl&lt;1:0&gt; == '00';</line>
<line></line>
<line>    bits(2) tg        = Xt&lt;47:46&gt;;</line>
<line>    integer scale     = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt&lt;45:44&gt;);</line>
<line>    integer num       = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt&lt;43:39&gt;);</line>
<line>    integer baseaddr  = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(Xt&lt;36:0&gt;);</line>
<line></line>
<line>    boolean valid;</line>
<line></line>
<line>    (valid, r.tg, r.address, r.end_address) = <a link="impl-aarch64.TLBIRange.2" file="shared_pseudocode.xml" hover="function: (boolean, bits(2), bits(64), bits(64)) TLBIRange(Regime regime, bits(64) Xt)">TLBIRange</a>(regime, Xt);</line>
<line></line>
<line>    if !valid then return;</line>
<line></line>
<line>    case security of</line>
<line>        when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a></line>
<line>            r.ipaspace = <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line>        when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a></line>
<line>            r.ipaspace = if Xt&lt;63&gt; == '1' then <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a> else <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a>;</line>
<line>        when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a></line>
<line>            r.ipaspace = <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a>;</line>
<line>        otherwise</line>
<line>            // Root security state does not have stage 2 translation</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    <a link="impl-aarch64.TLBI.1" file="shared_pseudocode.xml" hover="function: TLBI(TLBIRecord r)">TLBI</a>(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then <a link="impl-aarch64.Broadcast.2" file="shared_pseudocode.xml" hover="function: Broadcast(Shareability shareability, TLBIRecord r)">Broadcast</a>(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/AArch64.TLBI_RPA" mylink="aarch64.instrs.system.sysops.tlbi.AArch64.TLBI_RPA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TLBI_RPA()</line>
<line>// ==================</line>
<line>// TLB Range Invalidate GPT Information by PA.</line>
<line>// Invalidates cached copies of GPT entries from TLBs in the indicated</line>
<line>// Shareabilty domain.</line>
<line>// The invalidation applies to TLB entries containing GPT information relating</line>
<line>// to the indicated physical address range.</line>
<line>// When the indicated level is</line>
<line>//     TLBILevel_Any  : this applies to TLB entries containing GPT information</line>
<line>//                      from all levels of the GPT walk</line>
<line>//     TLBILevel_Last : this applies to TLB entries containing GPT information</line>
<line>//                      from the last level of the GPT walk</line>
<line></line>
<line link="AArch64.TLBI_RPA.3" hover="function: AArch64.TLBI_RPA(TLBILevel level, bits(64) Xt, Shareability shareability)" conts="AArch64.TLBI_RPA"><anchor link="AArch64.TLBI_RPA.3" hover="function: AArch64.TLBI_RPA(TLBILevel level, bits(64) Xt, Shareability shareability)">AArch64.TLBI_RPA</anchor>(<a link="TLBILevel" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel</a> level, bits(64) Xt, <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability)</line>
<line>    assert <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() &amp;&amp; PSTATE.EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    integer range_bits;</line>
<line>    integer p;</line>
<line></line>
<line>    // r.security and r.regime do not apply for TLBI by PA operations</line>
<line>    r.op    = <a link="TLBIOp_RPA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_RPA</a>;</line>
<line>    r.level = level;</line>
<line>    r.attr  = <a link="TLBI_AllAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBI_AllAttr</a>;</line>
<line></line>
<line>    // SIZE field</line>
<line>    case Xt&lt;47:44&gt; of</line>
<line>        when '0000' range_bits = 12; // 4KB</line>
<line>        when '0001' range_bits = 14; // 16KB</line>
<line>        when '0010' range_bits = 16; // 64KB</line>
<line>        when '0011' range_bits = 21; // 2MB</line>
<line>        when '0100' range_bits = 25; // 32MB</line>
<line>        when '0101' range_bits = 29; // 512MB</line>
<line>        when '0110' range_bits = 30; // 1GB</line>
<line>        when '0111' range_bits = 34; // 16GB</line>
<line>        when '1000' range_bits = 36; // 64GB</line>
<line>        when '1001' range_bits = 39; // 512GB</line>
<line>        otherwise   range_bits = 0;  // Reserved encoding</line>
<line></line>
<line>    // If SIZE selects a range smaller than PGS, then PGS is used instead</line>
<line>    case <a link="impl-shared.DecodePGS.1" file="shared_pseudocode.xml" hover="function: PGSe DecodePGS(bits(2) pgs)">DecodePGS</a>(GPCCR_EL3.PGS) of</line>
<line>        when <a link="PGS_4KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_4KB</a>  p = 12;</line>
<line>        when <a link="PGS_16KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_16KB</a> p = 14;</line>
<line>        when <a link="PGS_64KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_64KB</a> p = 16;</line>
<line></line>
<line>    if range_bits &lt; p then</line>
<line>        range_bits = p;</line>
<line></line>
<line>    bits(52) BaseADDR = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(52);</line>
<line>    case GPCCR_EL3.PGS of</line>
<line>        when '00' BaseADDR&lt;51:12&gt; = Xt&lt;39:0&gt;;   // 4KB</line>
<line>        when '10' BaseADDR&lt;51:14&gt; = Xt&lt;39:2&gt;;   // 16KB</line>
<line>        when '01' BaseADDR&lt;51:16&gt; = Xt&lt;39:4&gt;;   // 64KB</line>
<line></line>
<line>    // The calculation here automatically aligns BaseADDR to the size of</line>
<line>    // the region specififed in SIZE. However, the architecture does not</line>
<line>    // require this alignment and if BaseADDR is not aligned to the region</line>
<line>    // specified by SIZE then no entries are required to be invalidated.</line>
<line>    bits(52) start_addr = BaseADDR AND NOT <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(range_bits), 52);</line>
<line>    bits(52) end_addr   = start_addr + <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(range_bits), 52);</line>
<line></line>
<line>    // PASpace is not considered in TLBI by PA operations</line>
<line>    r.address     = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(start_addr, 64);</line>
<line>    r.end_address = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(end_addr, 64);</line>
<line></line>
<line>    <a link="impl-aarch64.TLBI.1" file="shared_pseudocode.xml" hover="function: TLBI(TLBIRecord r)">TLBI</a>(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then <a link="impl-aarch64.Broadcast.2" file="shared_pseudocode.xml" hover="function: Broadcast(Shareability shareability, TLBIRecord r)">Broadcast</a>(shareability, r);</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/AArch64.TLBI_RVA" mylink="aarch64.instrs.system.sysops.tlbi.AArch64.TLBI_RVA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TLBI_RVA()</line>
<line>// ==================</line>
<line>// Range invalidate by VA range all stage 1 TLB entries in the indicated</line>
<line>// shareability domain matching the indicated VMID and ASID (where regime</line>
<line>// supports VMID, ASID) in the indicated regime with the indicated security state.</line>
<line>// ASID, and range related parameters are derived from Xt.</line>
<line>// Note: stage 1 and stage 2 combined entries are in the scope of this operation.</line>
<line></line>
<line link="AArch64.TLBI_RVA.7" hover="function: AArch64.TLBI_RVA(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr, bits(64)  Xt)" conts="AArch64.TLBI_RVA"><anchor link="AArch64.TLBI_RVA.7" hover="function: AArch64.TLBI_RVA(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr, bits(64)  Xt)">AArch64.TLBI_RVA</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                 <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBILevel" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel</a> level, <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr, bits(64)  Xt)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_RVA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_RVA</a>;</line>
<line>    r.from_aarch64 = TRUE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.level        = level;</line>
<line>    r.attr         = attr;</line>
<line>    r.asid         = Xt&lt;63:48&gt;;</line>
<line>    r.ttl&lt;1:0&gt;     = Xt&lt;38:37&gt;;</line>
<line>    r.d64          = TRUE;</line>
<line>    r.d128         = r.ttl&lt;1:0&gt; == '00';</line>
<line></line>
<line>    boolean valid;</line>
<line></line>
<line>    (valid, r.tg, r.address, r.end_address) = <a link="impl-aarch64.TLBIRange.2" file="shared_pseudocode.xml" hover="function: (boolean, bits(2), bits(64), bits(64)) TLBIRange(Regime regime, bits(64) Xt)">TLBIRange</a>(regime, Xt);</line>
<line></line>
<line>    if !valid then return;</line>
<line></line>
<line>    <a link="impl-aarch64.TLBI.1" file="shared_pseudocode.xml" hover="function: TLBI(TLBIRecord r)">TLBI</a>(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then <a link="impl-aarch64.Broadcast.2" file="shared_pseudocode.xml" hover="function: Broadcast(Shareability shareability, TLBIRecord r)">Broadcast</a>(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/AArch64.TLBI_RVAA" mylink="aarch64.instrs.system.sysops.tlbi.AArch64.TLBI_RVAA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TLBI_RVAA()</line>
<line>// ===================</line>
<line>// Range invalidate by VA range all stage 1 TLB entries in the indicated</line>
<line>// shareability domain matching the indicated VMID (where regimesupports VMID)</line>
<line>// and all ASID in the indicated regime with the indicated security state.</line>
<line>// VA range related parameters are derived from Xt.</line>
<line>// Note: stage 1 and stage 2 combined entries are in the scope of this operation.</line>
<line></line>
<line link="AArch64.TLBI_RVAA.7" hover="function: AArch64.TLBI_RVAA(SecurityState security, Regime  regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr, bits(64) Xt)" conts="AArch64.TLBI_RVAA"><anchor link="AArch64.TLBI_RVAA.7" hover="function: AArch64.TLBI_RVAA(SecurityState security, Regime  regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr, bits(64) Xt)">AArch64.TLBI_RVAA</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a>  regime, bits(16) vmid,</line>
<line>                  <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBILevel" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel</a> level, <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr, bits(64) Xt)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_RVAA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_RVAA</a>;</line>
<line>    r.from_aarch64 = TRUE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.level        = level;</line>
<line>    r.attr         = attr;</line>
<line>    r.ttl&lt;1:0&gt;     = Xt&lt;38:37&gt;;</line>
<line>    r.d64          = TRUE;</line>
<line>    r.d128         = r.ttl&lt;1:0&gt; == '00';</line>
<line></line>
<line>    bits(2) tg        = Xt&lt;47:46&gt;;</line>
<line>    integer scale     = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt&lt;45:44&gt;);</line>
<line>    integer num       = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt&lt;43:39&gt;);</line>
<line>    integer baseaddr  = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(Xt&lt;36:0&gt;);</line>
<line></line>
<line>    boolean valid;</line>
<line></line>
<line>    (valid, r.tg, r.address, r.end_address) = <a link="impl-aarch64.TLBIRange.2" file="shared_pseudocode.xml" hover="function: (boolean, bits(2), bits(64), bits(64)) TLBIRange(Regime regime, bits(64) Xt)">TLBIRange</a>(regime, Xt);</line>
<line></line>
<line>    if !valid then return;</line>
<line></line>
<line>    <a link="impl-aarch64.TLBI.1" file="shared_pseudocode.xml" hover="function: TLBI(TLBIRecord r)">TLBI</a>(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then <a link="impl-aarch64.Broadcast.2" file="shared_pseudocode.xml" hover="function: Broadcast(Shareability shareability, TLBIRecord r)">Broadcast</a>(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/AArch64.TLBI_VA" mylink="aarch64.instrs.system.sysops.tlbi.AArch64.TLBI_VA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TLBI_VA()</line>
<line>// =================</line>
<line>// Invalidate by VA all stage 1 TLB entries in the indicated shareability domain</line>
<line>// matching the indicated VMID and ASID (where regime supports VMID, ASID) in the indicated regime</line>
<line>// with the indicated security state.</line>
<line>// ASID, VA and related parameters are derived from Xt.</line>
<line>// Note: stage 1 and stage 2 combined entries are in the scope of this operation.</line>
<line></line>
<line link="AArch64.TLBI_VA.7" hover="function: AArch64.TLBI_VA(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level,  TLBIMemAttr attr, bits(64) Xt)" conts="AArch64.TLBI_VA"><anchor link="AArch64.TLBI_VA.7" hover="function: AArch64.TLBI_VA(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level,  TLBIMemAttr attr, bits(64) Xt)">AArch64.TLBI_VA</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBILevel" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel</a> level,  <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr, bits(64) Xt)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_VA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_VA</a>;</line>
<line>    r.from_aarch64 = TRUE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.level        = level;</line>
<line>    r.attr         = attr;</line>
<line>    r.asid         = Xt&lt;63:48&gt;;</line>
<line>    r.ttl          = Xt&lt;47:44&gt;;</line>
<line>    r.address      = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(Xt&lt;43:0&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12), 64);</line>
<line>    r.d64          = TRUE;</line>
<line>    r.d128         = r.ttl IN {'00xx'};</line>
<line></line>
<line>    <a link="impl-aarch64.TLBI.1" file="shared_pseudocode.xml" hover="function: TLBI(TLBIRecord r)">TLBI</a>(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then <a link="impl-aarch64.Broadcast.2" file="shared_pseudocode.xml" hover="function: Broadcast(Shareability shareability, TLBIRecord r)">Broadcast</a>(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/AArch64.TLBI_VAA" mylink="aarch64.instrs.system.sysops.tlbi.AArch64.TLBI_VAA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TLBI_VAA()</line>
<line>// ==================</line>
<line>// Invalidate by VA all stage 1 TLB entries in the indicated shareability domain</line>
<line>// matching the indicated VMID (where regime supports VMID) and all ASID in the indicated regime</line>
<line>// with the indicated security state.</line>
<line>// VA and related parameters are derived from Xt.</line>
<line>// Note: stage 1 and stage 2 combined entries are in the scope of this operation.</line>
<line></line>
<line link="AArch64.TLBI_VAA.7" hover="function: AArch64.TLBI_VAA(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr,  bits(64) Xt)" conts="AArch64.TLBI_VAA"><anchor link="AArch64.TLBI_VAA.7" hover="function: AArch64.TLBI_VAA(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBILevel level, TLBIMemAttr attr,  bits(64) Xt)">AArch64.TLBI_VAA</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                 <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBILevel" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel</a> level, <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr,  bits(64) Xt)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_VAA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_VAA</a>;</line>
<line>    r.from_aarch64 = TRUE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.level        = level;</line>
<line>    r.attr         = attr;</line>
<line>    r.ttl          = Xt&lt;47:44&gt;;</line>
<line>    r.address      = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(Xt&lt;43:0&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12), 64);</line>
<line>    r.d64          = TRUE;</line>
<line>    r.d128         = r.ttl IN {'00xx'};</line>
<line></line>
<line>    <a link="impl-aarch64.TLBI.1" file="shared_pseudocode.xml" hover="function: TLBI(TLBIRecord r)">TLBI</a>(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then <a link="impl-aarch64.Broadcast.2" file="shared_pseudocode.xml" hover="function: Broadcast(Shareability shareability, TLBIRecord r)">Broadcast</a>(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/AArch64.TLBI_VMALL" mylink="aarch64.instrs.system.sysops.tlbi.AArch64.TLBI_VMALL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TLBI_VMALL()</line>
<line>// ====================</line>
<line>// Invalidate all stage 1 entries for the indicated translation regime with the</line>
<line>// the indicated security state for all TLBs within the indicated shareability</line>
<line>// domain that match the indicated VMID (where applicable).</line>
<line>// Note: stage 1 and stage 2 combined entries are in the scope of this operation.</line>
<line>// Note: stage 2 only entries are not in the scope of this operation.</line>
<line></line>
<line link="AArch64.TLBI_VMALL.5" hover="function: AArch64.TLBI_VMALL(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBIMemAttr attr)" conts="AArch64.TLBI_VMALL"><anchor link="AArch64.TLBI_VMALL.5" hover="function: AArch64.TLBI_VMALL(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBIMemAttr attr)">AArch64.TLBI_VMALL</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                   <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_VMALL" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_VMALL</a>;</line>
<line>    r.from_aarch64 = TRUE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.level        = <a link="TLBILevel_Any" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel_Any</a>;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.attr         = attr;</line>
<line></line>
<line>    <a link="impl-aarch64.TLBI.1" file="shared_pseudocode.xml" hover="function: TLBI(TLBIRecord r)">TLBI</a>(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then <a link="impl-aarch64.Broadcast.2" file="shared_pseudocode.xml" hover="function: Broadcast(Shareability shareability, TLBIRecord r)">Broadcast</a>(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/AArch64.TLBI_VMALLS12" mylink="aarch64.instrs.system.sysops.tlbi.AArch64.TLBI_VMALLS12" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TLBI_VMALLS12()</line>
<line>// =======================</line>
<line>// Invalidate all stage 1 and stage 2 entries for the indicated translation</line>
<line>// regime with the indicated security state for all TLBs within the indicated</line>
<line>// shareability domain that match the indicated VMID.</line>
<line></line>
<line link="AArch64.TLBI_VMALLS12.5" hover="function: AArch64.TLBI_VMALLS12(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBIMemAttr attr)" conts="AArch64.TLBI_VMALLS12"><anchor link="AArch64.TLBI_VMALLS12.5" hover="function: AArch64.TLBI_VMALLS12(SecurityState security, Regime regime, bits(16) vmid, Shareability shareability, TLBIMemAttr attr)">AArch64.TLBI_VMALLS12</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(16) vmid,</line>
<line>                      <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a> attr)</line>
<line>    assert PSTATE.EL IN {<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>};</line>
<line></line>
<line>    <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r;</line>
<line>    r.op           = <a link="TLBIOp_VMALLS12" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_VMALLS12</a>;</line>
<line>    r.from_aarch64 = TRUE;</line>
<line>    r.security     = security;</line>
<line>    r.regime       = regime;</line>
<line>    r.level        = <a link="TLBILevel_Any" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel_Any</a>;</line>
<line>    r.vmid         = vmid;</line>
<line>    r.attr         = attr;</line>
<line></line>
<line>    <a link="impl-aarch64.TLBI.1" file="shared_pseudocode.xml" hover="function: TLBI(TLBIRecord r)">TLBI</a>(r);</line>
<line>    if shareability != <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> then <a link="impl-aarch64.Broadcast.2" file="shared_pseudocode.xml" hover="function: Broadcast(Shareability shareability, TLBIRecord r)">Broadcast</a>(shareability, r);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/ASID_NONE" mylink="aarch64.instrs.system.sysops.tlbi.ASID_NONE" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="ASID_NONE" hover="constant bits(16) ASID_NONE = Zeros(16)" conts="ASID_NONE">constant bits(16) <anchor link="ASID_NONE" hover="constant bits(16) ASID_NONE = Zeros(16)">ASID_NONE</anchor> = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/Broadcast" mylink="aarch64.instrs.system.sysops.tlbi.Broadcast" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Broadcast()</line>
<line>// ===========</line>
<line>// IMPLEMENTATION DEFINED function to broadcast TLBI operation within the indicated shareability</line>
<line>// domain.</line>
<line></line>
<line link="impl-aarch64.Broadcast.2" hover="function: Broadcast(Shareability shareability, TLBIRecord r)" conts="Broadcast"><anchor link="impl-aarch64.Broadcast.2" hover="function: Broadcast(Shareability shareability, TLBIRecord r)">Broadcast</anchor>(<a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, <a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r)</line>
<line>    IMPLEMENTATION_DEFINED;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/DecodeTLBITG" mylink="aarch64.instrs.system.sysops.tlbi.DecodeTLBITG" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DecodeTLBITG()</line>
<line>// ==============</line>
<line>// Decode translation granule size in TLBI range instructions</line>
<line></line>
<line link="impl-aarch64.DecodeTLBITG.1" hover="function: TGx DecodeTLBITG(bits(2) tg)" conts="DecodeTLBITG">TGx <anchor link="impl-aarch64.DecodeTLBITG.1" hover="function: TGx DecodeTLBITG(bits(2) tg)">DecodeTLBITG</anchor>(bits(2) tg)</line>
<line>    case tg of</line>
<line>        when '01'   return <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>;</line>
<line>        when '10'   return <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a>;</line>
<line>        when '11'   return <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a>;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/GPTTLBIMatch" mylink="aarch64.instrs.system.sysops.tlbi.GPTTLBIMatch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GPTTLBIMatch()</line>
<line>// ==============</line>
<line>// Determine whether the GPT TLB entry lies within the scope of invalidation</line>
<line></line>
<line link="impl-aarch64.GPTTLBIMatch.2" hover="function: boolean GPTTLBIMatch(TLBIRecord tlbi, GPTEntry entry)" conts="GPTTLBIMatch">boolean <anchor link="impl-aarch64.GPTTLBIMatch.2" hover="function: boolean GPTTLBIMatch(TLBIRecord tlbi, GPTEntry entry)">GPTTLBIMatch</anchor>(<a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> tlbi, <a link="GPTEntry" file="shared_pseudocode.xml" hover="type GPTEntry is ( bits(4) gpi, integer size, integer contig_size, integer level, bits(56) pa )">GPTEntry</a> entry)</line>
<line>    assert tlbi.op IN {<a link="TLBIOp_RPA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_RPA</a>, <a link="TLBIOp_PAALL" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_PAALL</a>};</line>
<line></line>
<line>    boolean match;</line>
<line>    bits(64) entry_size_mask    = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(entry.size), 64);</line>
<line>    bits(64) entry_end_address   = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(entry.pa&lt;55:0&gt; OR entry_size_mask&lt;55:0&gt;, 64);</line>
<line>    bits(64) entry_start_address = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(entry.pa&lt;55:0&gt; AND NOT entry_size_mask&lt;55:0&gt;, 64);</line>
<line></line>
<line>    case tlbi.op of</line>
<line>        when <a link="TLBIOp_RPA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_RPA</a></line>
<line>            match = (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(tlbi.address&lt;55:0&gt;) &lt;= <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(entry_end_address&lt;55:0&gt;) &amp;&amp;</line>
<line>                     <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(tlbi.end_address&lt;55:0&gt;) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(entry_start_address&lt;55:0&gt;) &amp;&amp;</line>
<line>                     (tlbi.level == <a link="TLBILevel_Any" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel_Any</a> || entry.level == 1));</line>
<line>        when <a link="TLBIOp_PAALL" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_PAALL</a></line>
<line>            match = TRUE;</line>
<line></line>
<line>    return match;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/HasLargeAddress" mylink="aarch64.instrs.system.sysops.tlbi.HasLargeAddress" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HasLargeAddress()</line>
<line>// =================</line>
<line>// Returns TRUE if the regime is configured for 52 bit addresses, FALSE otherwise.</line>
<line></line>
<line link="impl-aarch64.HasLargeAddress.1" hover="function: boolean HasLargeAddress(Regime regime)" conts="HasLargeAddress">boolean <anchor link="impl-aarch64.HasLargeAddress.1" hover="function: boolean HasLargeAddress(Regime regime)">HasLargeAddress</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime)</line>
<line>    if !<a link="impl-shared.Have52BitIPAAndPASpaceExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitIPAAndPASpaceExt()">Have52BitIPAAndPASpaceExt</a>() then</line>
<line>        return FALSE;</line>
<line>    case regime of</line>
<line>        when <a link="Regime_EL3" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL3</a></line>
<line>            return TCR_EL3&lt;32&gt; == '1';</line>
<line>        when <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a></line>
<line>            return TCR_EL2&lt;32&gt; == '1';</line>
<line>        when <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a></line>
<line>            return TCR_EL2&lt;59&gt; == '1';</line>
<line>        when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a></line>
<line>            return TCR_EL1&lt;59&gt; == '1';</line>
<line>        otherwise</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/ResTLBIRTTL" mylink="aarch64.instrs.system.sysops.tlbi.ResTLBIRTTL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ResTLBIRTTL()</line>
<line>// =============</line>
<line>// Determine whether the TTL field in TLBI instructions that do apply</line>
<line>// to a range of addresses contains a reserved value</line>
<line></line>
<line link="impl-aarch64.ResTLBIRTTL.2" hover="function: boolean ResTLBIRTTL(bits(2) tg, bits(2) ttl)" conts="ResTLBIRTTL">boolean <anchor link="impl-aarch64.ResTLBIRTTL.2" hover="function: boolean ResTLBIRTTL(bits(2) tg, bits(2) ttl)">ResTLBIRTTL</anchor>(bits(2) tg, bits(2) ttl)</line>
<line>    case ttl of</line>
<line>        when '00' return TRUE;</line>
<line>        when '01' return <a link="impl-aarch64.DecodeTLBITG.1" file="shared_pseudocode.xml" hover="function: TGx DecodeTLBITG(bits(2) tg)">DecodeTLBITG</a>(tg) == <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a> &amp;&amp; !<a link="impl-shared.Have52BitIPAAndPASpaceExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitIPAAndPASpaceExt()">Have52BitIPAAndPASpaceExt</a>();</line>
<line>        otherwise return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/ResTLBITTL" mylink="aarch64.instrs.system.sysops.tlbi.ResTLBITTL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ResTLBITTL()</line>
<line>// ============</line>
<line>// Determine whether the TTL field in TLBI instructions that do not apply</line>
<line>// to a range of addresses contains a reserved value</line>
<line></line>
<line link="impl-aarch64.ResTLBITTL.1" hover="function: boolean ResTLBITTL(bits(4) ttl)" conts="ResTLBITTL">boolean <anchor link="impl-aarch64.ResTLBITTL.1" hover="function: boolean ResTLBITTL(bits(4) ttl)">ResTLBITTL</anchor>(bits(4) ttl)</line>
<line>    case ttl of</line>
<line>        when '00xx' return TRUE;</line>
<line>        when '0100' return !<a link="impl-shared.Have52BitIPAAndPASpaceExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitIPAAndPASpaceExt()">Have52BitIPAAndPASpaceExt</a>();</line>
<line>        when '1000' return TRUE;</line>
<line>        when '1001' return !<a link="impl-shared.Have52BitIPAAndPASpaceExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitIPAAndPASpaceExt()">Have52BitIPAAndPASpaceExt</a>();</line>
<line>        when '1100' return TRUE;</line>
<line>        otherwise   return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/TLBI" mylink="aarch64.instrs.system.sysops.tlbi.TLBI" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TLBI()</line>
<line>// ======</line>
<line>// Invalidates TLB entries for which TLBIMatch() returns TRUE.</line>
<line></line>
<line link="impl-aarch64.TLBI.1" hover="function: TLBI(TLBIRecord r)" conts="TLBI"><anchor link="impl-aarch64.TLBI.1" hover="function: TLBI(TLBIRecord r)">TLBI</anchor>(<a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> r)</line>
<line>    IMPLEMENTATION_DEFINED;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/TLBILevel" mylink="aarch64.instrs.system.sysops.tlbi.TLBILevel" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TLBILevel</line>
<line>// =========</line>
<line></line>
<line link="TLBILevel" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }" conts="TLBILevel">enumeration <anchor link="TLBILevel" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel</anchor> {</line>
<line link="TLBILevel_Any" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }" conts="TLBILevel_Any">    <anchor link="TLBILevel_Any" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel_Any</anchor>,        // this applies to TLB entries at all levels</line>
<line link="TLBILevel_Last" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }" conts="TLBILevel_Last">    <anchor link="TLBILevel_Last" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel_Last</anchor>        // this applies to TLB entries at last level only</line>
<line>};</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/TLBIMatch" mylink="aarch64.instrs.system.sysops.tlbi.TLBIMatch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TLBIMatch()</line>
<line>// ===========</line>
<line>// Determine whether the TLB entry lies within the scope of invalidation</line>
<line></line>
<line link="impl-aarch64.TLBIMatch.2" hover="function: boolean TLBIMatch(TLBIRecord tlbi, TLBRecord entry)" conts="TLBIMatch">boolean <anchor link="impl-aarch64.TLBIMatch.2" hover="function: boolean TLBIMatch(TLBIRecord tlbi, TLBRecord entry)">TLBIMatch</anchor>(<a link="TLBIRecord" file="shared_pseudocode.xml" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</a> tlbi, <a link="TLBRecord" file="shared_pseudocode.xml" hover="type TLBRecord is ( TLBContext context, TTWState walkstate, integer blocksize, integer contigsize, bits(128) s1descriptor, bits(128) s2descriptor )">TLBRecord</a> entry)</line>
<line>    boolean match;</line>
<line>    bits(64) entry_block_mask    = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(entry.blocksize), 64);</line>
<line>    bits(64) entry_end_address   = entry.context.ia OR entry_block_mask;</line>
<line>    bits(64) entry_start_address = entry.context.ia AND NOT entry_block_mask;</line>
<line>    case tlbi.op of</line>
<line>        when <a link="TLBIOp_DALL" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_DALL</a>, <a link="TLBIOp_IALL" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_IALL</a></line>
<line>            match = (tlbi.security == entry.context.ss &amp;&amp;</line>
<line>                     tlbi.regime   == entry.context.regime);</line>
<line>        when <a link="TLBIOp_DASID" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_DASID</a>, <a link="TLBIOp_IASID" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_IASID</a></line>
<line>            match = (entry.context.includes_s1 &amp;&amp;</line>
<line>                     tlbi.security == entry.context.ss &amp;&amp;</line>
<line>                     tlbi.regime   == entry.context.regime &amp;&amp;</line>
<line>                     (!<a link="impl-shared.UseVMID.1" file="shared_pseudocode.xml" hover="function: boolean UseVMID(TLBContext access)">UseVMID</a>(entry.context) || tlbi.vmid == entry.context.vmid) &amp;&amp;</line>
<line>                     (<a link="impl-shared.UseASID.1" file="shared_pseudocode.xml" hover="function: boolean UseASID(TLBContext access)">UseASID</a>(entry.context) &amp;&amp; entry.context.nG == '1' &amp;&amp;</line>
<line>                        tlbi.asid  == entry.context.asid));</line>
<line>        when <a link="TLBIOp_DVA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_DVA</a>, <a link="TLBIOp_IVA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_IVA</a></line>
<line>            match = (entry.context.includes_s1 &amp;&amp;</line>
<line>                     tlbi.security == entry.context.ss &amp;&amp;</line>
<line>                     tlbi.regime   == entry.context.regime &amp;&amp;</line>
<line>                     (!<a link="impl-shared.UseVMID.1" file="shared_pseudocode.xml" hover="function: boolean UseVMID(TLBContext access)">UseVMID</a>(entry.context) || tlbi.vmid == entry.context.vmid) &amp;&amp;</line>
<line>                     (!<a link="impl-shared.UseASID.1" file="shared_pseudocode.xml" hover="function: boolean UseASID(TLBContext access)">UseASID</a>(entry.context) || tlbi.asid == entry.context.asid ||</line>
<line>                        entry.context.nG == '0') &amp;&amp;</line>
<line>                     tlbi.address&lt;55:entry.blocksize&gt; == entry.context.ia&lt;55:entry.blocksize&gt; &amp;&amp;</line>
<line>                     (tlbi.level == <a link="TLBILevel_Any" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel_Any</a> || !entry.walkstate.istable));</line>
<line>        when <a link="TLBIOp_ALL" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_ALL</a></line>
<line>            relax_regime = (tlbi.from_aarch64 &amp;&amp;</line>
<line>                            tlbi.regime IN {<a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a>, <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>} &amp;&amp;</line>
<line>                            entry.context.regime IN {<a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a>, <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>});</line>
<line>            match = (tlbi.security == entry.context.ss &amp;&amp;</line>
<line>                     (tlbi.regime  == entry.context.regime || relax_regime));</line>
<line>        when <a link="TLBIOp_ASID" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_ASID</a></line>
<line>            match = (entry.context.includes_s1 &amp;&amp;</line>
<line>                     tlbi.security == entry.context.ss &amp;&amp;</line>
<line>                     tlbi.regime   == entry.context.regime &amp;&amp;</line>
<line>                     (!<a link="impl-shared.UseVMID.1" file="shared_pseudocode.xml" hover="function: boolean UseVMID(TLBContext access)">UseVMID</a>(entry.context) || tlbi.vmid == entry.context.vmid) &amp;&amp;</line>
<line>                     (<a link="impl-shared.UseASID.1" file="shared_pseudocode.xml" hover="function: boolean UseASID(TLBContext access)">UseASID</a>(entry.context) &amp;&amp; entry.context.nG == '1' &amp;&amp;</line>
<line>                        tlbi.asid  == entry.context.asid));</line>
<line>        when <a link="TLBIOp_IPAS2" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_IPAS2</a>, <a link="TLBIPOp_IPAS2" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIPOp_IPAS2</a></line>
<line>            match = (!entry.context.includes_s1 &amp;&amp; entry.context.includes_s2 &amp;&amp;</line>
<line>                     tlbi.security == entry.context.ss &amp;&amp;</line>
<line>                     tlbi.regime   == entry.context.regime &amp;&amp;</line>
<line>                     (!<a link="impl-shared.UseVMID.1" file="shared_pseudocode.xml" hover="function: boolean UseVMID(TLBContext access)">UseVMID</a>(entry.context) || tlbi.vmid == entry.context.vmid) &amp;&amp;</line>
<line>                     tlbi.ipaspace == entry.context.ipaspace &amp;&amp;</line>
<line>                     tlbi.address&lt;55:entry.blocksize&gt; == entry.context.ia&lt;55:entry.blocksize&gt; &amp;&amp;</line>
<line>                     (!tlbi.from_aarch64 || <a link="impl-aarch64.ResTLBITTL.1" file="shared_pseudocode.xml" hover="function: boolean ResTLBITTL(bits(4) ttl)">ResTLBITTL</a>(tlbi.ttl) || (</line>
<line>                         <a link="impl-aarch64.DecodeTLBITG.1" file="shared_pseudocode.xml" hover="function: TGx DecodeTLBITG(bits(2) tg)">DecodeTLBITG</a>(tlbi.ttl&lt;3:2&gt;) == entry.context.tg &amp;&amp;</line>
<line>                         <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(tlbi.ttl&lt;1:0&gt;) == entry.walkstate.level)</line>
<line>                     ) &amp;&amp;</line>
<line>                     ((tlbi.d128  &amp;&amp; entry.context.isd128) ||</line>
<line>                      (tlbi.d64  &amp;&amp; !entry.context.isd128) ||</line>
<line>                      (tlbi.d64 &amp;&amp; tlbi.d128)) &amp;&amp;</line>
<line>                     (tlbi.level == <a link="TLBILevel_Any" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel_Any</a> || !entry.walkstate.istable));</line>
<line>        when <a link="TLBIOp_VAA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_VAA</a>, <a link="TLBIPOp_VAA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIPOp_VAA</a></line>
<line>            match = (entry.context.includes_s1 &amp;&amp;</line>
<line>                     tlbi.security == entry.context.ss &amp;&amp;</line>
<line>                     tlbi.regime   == entry.context.regime &amp;&amp;</line>
<line>                     (!<a link="impl-shared.UseVMID.1" file="shared_pseudocode.xml" hover="function: boolean UseVMID(TLBContext access)">UseVMID</a>(entry.context) || tlbi.vmid == entry.context.vmid) &amp;&amp;</line>
<line>                     tlbi.address&lt;55:entry.blocksize&gt; == entry.context.ia&lt;55:entry.blocksize&gt; &amp;&amp;</line>
<line>                     (!tlbi.from_aarch64 || <a link="impl-aarch64.ResTLBITTL.1" file="shared_pseudocode.xml" hover="function: boolean ResTLBITTL(bits(4) ttl)">ResTLBITTL</a>(tlbi.ttl) || (</line>
<line>                         <a link="impl-aarch64.DecodeTLBITG.1" file="shared_pseudocode.xml" hover="function: TGx DecodeTLBITG(bits(2) tg)">DecodeTLBITG</a>(tlbi.ttl&lt;3:2&gt;) == entry.context.tg &amp;&amp;</line>
<line>                         <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(tlbi.ttl&lt;1:0&gt;) == entry.walkstate.level)</line>
<line>                     ) &amp;&amp;</line>
<line>                     ((tlbi.d128  &amp;&amp; entry.context.isd128) ||</line>
<line>                      (tlbi.d64  &amp;&amp; !entry.context.isd128) ||</line>
<line>                      (tlbi.d64 &amp;&amp; tlbi.d128)) &amp;&amp;</line>
<line>                     (tlbi.level == <a link="TLBILevel_Any" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel_Any</a> || !entry.walkstate.istable));</line>
<line>        when <a link="TLBIOp_VA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_VA</a>, <a link="TLBIPOp_VA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIPOp_VA</a></line>
<line>            match = (entry.context.includes_s1 &amp;&amp;</line>
<line>                     tlbi.security == entry.context.ss &amp;&amp;</line>
<line>                     tlbi.regime   == entry.context.regime &amp;&amp;</line>
<line>                     (!<a link="impl-shared.UseVMID.1" file="shared_pseudocode.xml" hover="function: boolean UseVMID(TLBContext access)">UseVMID</a>(entry.context) || tlbi.vmid == entry.context.vmid) &amp;&amp;</line>
<line>                     (!<a link="impl-shared.UseASID.1" file="shared_pseudocode.xml" hover="function: boolean UseASID(TLBContext access)">UseASID</a>(entry.context) || tlbi.asid == entry.context.asid ||</line>
<line>                        entry.context.nG == '0') &amp;&amp;</line>
<line>                     tlbi.address&lt;55:entry.blocksize&gt; == entry.context.ia&lt;55:entry.blocksize&gt; &amp;&amp;</line>
<line>                     (!tlbi.from_aarch64 || <a link="impl-aarch64.ResTLBITTL.1" file="shared_pseudocode.xml" hover="function: boolean ResTLBITTL(bits(4) ttl)">ResTLBITTL</a>(tlbi.ttl) || (</line>
<line>                         <a link="impl-aarch64.DecodeTLBITG.1" file="shared_pseudocode.xml" hover="function: TGx DecodeTLBITG(bits(2) tg)">DecodeTLBITG</a>(tlbi.ttl&lt;3:2&gt;) == entry.context.tg &amp;&amp;</line>
<line>                         <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(tlbi.ttl&lt;1:0&gt;) == entry.walkstate.level)</line>
<line>                     ) &amp;&amp;</line>
<line>                     ((tlbi.d128  &amp;&amp; entry.context.isd128) ||</line>
<line>                      (tlbi.d64  &amp;&amp; !entry.context.isd128) ||</line>
<line>                      (tlbi.d64 &amp;&amp; tlbi.d128)) &amp;&amp;</line>
<line>                     (tlbi.level == <a link="TLBILevel_Any" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel_Any</a> || !entry.walkstate.istable));</line>
<line>        when <a link="TLBIOp_VMALL" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_VMALL</a></line>
<line>            match = (entry.context.includes_s1 &amp;&amp;</line>
<line>                     tlbi.security == entry.context.ss &amp;&amp;</line>
<line>                     tlbi.regime   == entry.context.regime &amp;&amp;</line>
<line>                     (!<a link="impl-shared.UseVMID.1" file="shared_pseudocode.xml" hover="function: boolean UseVMID(TLBContext access)">UseVMID</a>(entry.context) || tlbi.vmid == entry.context.vmid));</line>
<line>        when <a link="TLBIOp_VMALLS12" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_VMALLS12</a></line>
<line>            match = (tlbi.security == entry.context.ss &amp;&amp;</line>
<line>                     tlbi.regime   == entry.context.regime &amp;&amp;</line>
<line>                     (!<a link="impl-shared.UseVMID.1" file="shared_pseudocode.xml" hover="function: boolean UseVMID(TLBContext access)">UseVMID</a>(entry.context) || tlbi.vmid == entry.context.vmid));</line>
<line>        when <a link="TLBIOp_RIPAS2" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_RIPAS2</a>, <a link="TLBIPOp_RIPAS2" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIPOp_RIPAS2</a></line>
<line>            match = (!entry.context.includes_s1 &amp;&amp; entry.context.includes_s2 &amp;&amp;</line>
<line>                     tlbi.security == entry.context.ss &amp;&amp;</line>
<line>                     tlbi.regime   == entry.context.regime &amp;&amp;</line>
<line>                     (!<a link="impl-shared.UseVMID.1" file="shared_pseudocode.xml" hover="function: boolean UseVMID(TLBContext access)">UseVMID</a>(entry.context) || tlbi.vmid == entry.context.vmid) &amp;&amp;</line>
<line>                     tlbi.ipaspace == entry.context.ipaspace &amp;&amp;</line>
<line>                     (tlbi.tg != '00' &amp;&amp; <a link="impl-aarch64.DecodeTLBITG.1" file="shared_pseudocode.xml" hover="function: TGx DecodeTLBITG(bits(2) tg)">DecodeTLBITG</a>(tlbi.tg) == entry.context.tg) &amp;&amp;</line>
<line>                     (!tlbi.from_aarch64 || <a link="impl-aarch64.ResTLBIRTTL.2" file="shared_pseudocode.xml" hover="function: boolean ResTLBIRTTL(bits(2) tg, bits(2) ttl)">ResTLBIRTTL</a>(tlbi.tg, tlbi.ttl&lt;1:0&gt;) ||</line>
<line>                        <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(tlbi.ttl&lt;1:0&gt;) == entry.walkstate.level) &amp;&amp;</line>
<line>                     ((tlbi.d128  &amp;&amp; entry.context.isd128) ||</line>
<line>                      (tlbi.d64  &amp;&amp; !entry.context.isd128) ||</line>
<line>                      (tlbi.d64 &amp;&amp; tlbi.d128)) &amp;&amp;</line>
<line>                     <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(tlbi.address&lt;55:0&gt;) &lt;= <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(entry_end_address&lt;55:0&gt;) &amp;&amp;</line>
<line>                     <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(tlbi.end_address&lt;55:0&gt;) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(entry_start_address&lt;55:0&gt;));</line>
<line>        when <a link="TLBIOp_RVAA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_RVAA</a>, <a link="TLBIPOp_RVAA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIPOp_RVAA</a></line>
<line>            match = (entry.context.includes_s1 &amp;&amp;</line>
<line>                     tlbi.security == entry.context.ss &amp;&amp;</line>
<line>                     tlbi.regime   == entry.context.regime &amp;&amp;</line>
<line>                     (!<a link="impl-shared.UseVMID.1" file="shared_pseudocode.xml" hover="function: boolean UseVMID(TLBContext access)">UseVMID</a>(entry.context) || tlbi.vmid == entry.context.vmid) &amp;&amp;</line>
<line>                     (tlbi.tg != '00' &amp;&amp; <a link="impl-aarch64.DecodeTLBITG.1" file="shared_pseudocode.xml" hover="function: TGx DecodeTLBITG(bits(2) tg)">DecodeTLBITG</a>(tlbi.tg) == entry.context.tg) &amp;&amp;</line>
<line>                     (!tlbi.from_aarch64 || <a link="impl-aarch64.ResTLBIRTTL.2" file="shared_pseudocode.xml" hover="function: boolean ResTLBIRTTL(bits(2) tg, bits(2) ttl)">ResTLBIRTTL</a>(tlbi.tg, tlbi.ttl&lt;1:0&gt;) ||</line>
<line>                        <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(tlbi.ttl&lt;1:0&gt;) == entry.walkstate.level) &amp;&amp;</line>
<line>                     ((tlbi.d128  &amp;&amp; entry.context.isd128) ||</line>
<line>                      (tlbi.d64  &amp;&amp; !entry.context.isd128) ||</line>
<line>                      (tlbi.d64 &amp;&amp; tlbi.d128)) &amp;&amp;</line>
<line>                     <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(tlbi.address&lt;55:0&gt;) &lt;= <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(entry_end_address&lt;55:0&gt;) &amp;&amp;</line>
<line>                     <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(tlbi.end_address&lt;55:0&gt;) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(entry_start_address&lt;55:0&gt;));</line>
<line>        when <a link="TLBIOp_RVA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_RVA</a>, <a link="TLBIPOp_RVA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIPOp_RVA</a></line>
<line>            match = (entry.context.includes_s1 &amp;&amp;</line>
<line>                     tlbi.security == entry.context.ss &amp;&amp;</line>
<line>                     tlbi.regime   == entry.context.regime &amp;&amp;</line>
<line>                     (!<a link="impl-shared.UseVMID.1" file="shared_pseudocode.xml" hover="function: boolean UseVMID(TLBContext access)">UseVMID</a>(entry.context) || tlbi.vmid == entry.context.vmid) &amp;&amp;</line>
<line>                     (!<a link="impl-shared.UseASID.1" file="shared_pseudocode.xml" hover="function: boolean UseASID(TLBContext access)">UseASID</a>(entry.context) || tlbi.asid == entry.context.asid ||</line>
<line>                        entry.context.nG == '0') &amp;&amp;</line>
<line>                     (tlbi.tg != '00' &amp;&amp; <a link="impl-aarch64.DecodeTLBITG.1" file="shared_pseudocode.xml" hover="function: TGx DecodeTLBITG(bits(2) tg)">DecodeTLBITG</a>(tlbi.tg) == entry.context.tg) &amp;&amp;</line>
<line>                     (!tlbi.from_aarch64 || <a link="impl-aarch64.ResTLBIRTTL.2" file="shared_pseudocode.xml" hover="function: boolean ResTLBIRTTL(bits(2) tg, bits(2) ttl)">ResTLBIRTTL</a>(tlbi.tg, tlbi.ttl&lt;1:0&gt;) ||</line>
<line>                        <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(tlbi.ttl&lt;1:0&gt;) == entry.walkstate.level) &amp;&amp;</line>
<line>                     ((tlbi.d128  &amp;&amp; entry.context.isd128) ||</line>
<line>                      (tlbi.d64  &amp;&amp; !entry.context.isd128) ||</line>
<line>                      (tlbi.d64 &amp;&amp; tlbi.d128)) &amp;&amp;</line>
<line>                     <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(tlbi.address&lt;55:0&gt;) &lt;= <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(entry_end_address&lt;55:0&gt;) &amp;&amp;</line>
<line>                     <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(tlbi.end_address&lt;55:0&gt;) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(entry_start_address&lt;55:0&gt;));</line>
<line>        when <a link="TLBIOp_RPA" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_RPA</a></line>
<line>            entry_end_address&lt;55:0&gt; = (entry.walkstate.baseaddress.address&lt;55:0&gt; OR</line>
<line>                                               entry_block_mask&lt;55:0&gt;);</line>
<line>            entry_start_address&lt;55:0&gt; = (entry.walkstate.baseaddress.address&lt;55:0&gt; AND</line>
<line>                                                 NOT entry_block_mask&lt;55:0&gt;);</line>
<line>            match = (entry.context.includes_gpt &amp;&amp;</line>
<line>                     <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(tlbi.address&lt;55:0&gt;) &lt;= <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(entry_end_address&lt;55:0&gt;) &amp;&amp;</line>
<line>                     <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(tlbi.end_address&lt;55:0&gt;) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(entry_start_address&lt;55:0&gt;));</line>
<line>        when <a link="TLBIOp_PAALL" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_PAALL</a></line>
<line>            match = entry.context.includes_gpt;</line>
<line></line>
<line>    if tlbi.attr == <a link="TLBI_ExcludeXS" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBI_ExcludeXS</a> &amp;&amp; entry.context.xs == '1' then</line>
<line>        match = FALSE;</line>
<line></line>
<line>    return match;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/TLBIMemAttr" mylink="aarch64.instrs.system.sysops.tlbi.TLBIMemAttr" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TLBIMemAttr</line>
<line>// ===========</line>
<line>// Defines the attributes of the memory operations that must be completed in</line>
<line>// order to deem the TLBI operation as completed.</line>
<line></line>
<line link="TLBIMemAttr" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }" conts="TLBIMemAttr">enumeration <anchor link="TLBIMemAttr" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</anchor> {</line>
<line link="TLBI_AllAttr" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }" conts="TLBI_AllAttr">    <anchor link="TLBI_AllAttr" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBI_AllAttr</anchor>,         // All TLB entries within the scope of the invalidation</line>
<line link="TLBI_ExcludeXS" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }" conts="TLBI_ExcludeXS">    <anchor link="TLBI_ExcludeXS" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBI_ExcludeXS</anchor>        // Only TLB entries with XS=0 within the scope of the invalidation</line>
<line>};</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/TLBIOp" mylink="aarch64.instrs.system.sysops.tlbi.TLBIOp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TLBIOp</line>
<line>// ======</line>
<line></line>
<line link="TLBIOp" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIOp">enumeration <anchor link="TLBIOp" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp</anchor> {</line>
<line link="TLBIOp_DALL" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIOp_DALL">    <anchor link="TLBIOp_DALL" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_DALL</anchor>,          // AArch32 Data TLBI operations - deprecated</line>
<line link="TLBIOp_DASID" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIOp_DASID">    <anchor link="TLBIOp_DASID" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_DASID</anchor>,</line>
<line link="TLBIOp_DVA" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIOp_DVA">    <anchor link="TLBIOp_DVA" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_DVA</anchor>,</line>
<line link="TLBIOp_IALL" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIOp_IALL">    <anchor link="TLBIOp_IALL" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_IALL</anchor>,          // AArch32 Instruction TLBI operations - deprecated</line>
<line link="TLBIOp_IASID" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIOp_IASID">    <anchor link="TLBIOp_IASID" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_IASID</anchor>,</line>
<line link="TLBIOp_IVA" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIOp_IVA">    <anchor link="TLBIOp_IVA" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_IVA</anchor>,</line>
<line link="TLBIOp_ALL" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIOp_ALL">    <anchor link="TLBIOp_ALL" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_ALL</anchor>,</line>
<line link="TLBIOp_ASID" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIOp_ASID">    <anchor link="TLBIOp_ASID" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_ASID</anchor>,</line>
<line link="TLBIOp_IPAS2" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIOp_IPAS2">    <anchor link="TLBIOp_IPAS2" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_IPAS2</anchor>,</line>
<line link="TLBIPOp_IPAS2" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIPOp_IPAS2">    <anchor link="TLBIPOp_IPAS2" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIPOp_IPAS2</anchor>,</line>
<line link="TLBIOp_VAA" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIOp_VAA">    <anchor link="TLBIOp_VAA" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_VAA</anchor>,</line>
<line link="TLBIOp_VA" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIOp_VA">    <anchor link="TLBIOp_VA" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_VA</anchor>,</line>
<line link="TLBIPOp_VAA" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIPOp_VAA">    <anchor link="TLBIPOp_VAA" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIPOp_VAA</anchor>,</line>
<line link="TLBIPOp_VA" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIPOp_VA">    <anchor link="TLBIPOp_VA" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIPOp_VA</anchor>,</line>
<line link="TLBIOp_VMALL" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIOp_VMALL">    <anchor link="TLBIOp_VMALL" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_VMALL</anchor>,</line>
<line link="TLBIOp_VMALLS12" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIOp_VMALLS12">    <anchor link="TLBIOp_VMALLS12" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_VMALLS12</anchor>,</line>
<line link="TLBIOp_RIPAS2" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIOp_RIPAS2">    <anchor link="TLBIOp_RIPAS2" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_RIPAS2</anchor>,</line>
<line link="TLBIPOp_RIPAS2" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIPOp_RIPAS2">    <anchor link="TLBIPOp_RIPAS2" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIPOp_RIPAS2</anchor>,</line>
<line link="TLBIOp_RVAA" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIOp_RVAA">    <anchor link="TLBIOp_RVAA" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_RVAA</anchor>,</line>
<line link="TLBIOp_RVA" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIOp_RVA">    <anchor link="TLBIOp_RVA" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_RVA</anchor>,</line>
<line link="TLBIPOp_RVAA" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIPOp_RVAA">    <anchor link="TLBIPOp_RVAA" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIPOp_RVAA</anchor>,</line>
<line link="TLBIPOp_RVA" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIPOp_RVA">    <anchor link="TLBIPOp_RVA" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIPOp_RVA</anchor>,</line>
<line link="TLBIOp_RPA" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIOp_RPA">    <anchor link="TLBIOp_RPA" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_RPA</anchor>,</line>
<line link="TLBIOp_PAALL" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }" conts="TLBIOp_PAALL">    <anchor link="TLBIOp_PAALL" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp_PAALL</anchor>,</line>
<line>};</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/TLBIPRange" mylink="aarch64.instrs.system.sysops.tlbi.TLBIPRange" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TLBIPRange()</line>
<line>// ============</line>
<line>// Extract the input address range information from encoded Xt.</line>
<line></line>
<line link="impl-aarch64.TLBIPRange.2" hover="function: (boolean, bits(2), bits(64), bits(64)) TLBIPRange(Regime regime, bits(128) Xt)" conts="TLBIPRange">(boolean, bits(2), bits(64), bits(64)) <anchor link="impl-aarch64.TLBIPRange.2" hover="function: (boolean, bits(2), bits(64), bits(64)) TLBIPRange(Regime regime, bits(128) Xt)">TLBIPRange</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(128) Xt)</line>
<line>    boolean  valid = TRUE;</line>
<line>    bits(64) start = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>    bits(64) end   = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line></line>
<line>    bits(2) tg        = Xt&lt;47:46&gt;;</line>
<line>    integer scale     = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt&lt;45:44&gt;);</line>
<line>    integer num       = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt&lt;43:39&gt;);</line>
<line>    integer tg_bits;</line>
<line></line>
<line>    if tg == '00' then</line>
<line>        return (FALSE, tg, start, end);</line>
<line></line>
<line>    case tg of</line>
<line>        when '01' // 4KB</line>
<line>            tg_bits = 12;</line>
<line>            start&lt;55:12&gt; = Xt&lt;107:64&gt;;</line>
<line>            start&lt;63:56&gt; = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(Xt&lt;107&gt;, 8);</line>
<line>        when '10' // 16KB</line>
<line>            tg_bits = 14;</line>
<line>            start&lt;55:14&gt; = Xt&lt;107:66&gt;;</line>
<line>            start&lt;63:56&gt; = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(Xt&lt;107&gt;, 8);</line>
<line>        when '11' // 64KB</line>
<line>            tg_bits = 16;</line>
<line>            start&lt;55:16&gt; = Xt&lt;107:68&gt;;</line>
<line>            start&lt;63:56&gt; = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(Xt&lt;107&gt;, 8);</line>
<line>        otherwise</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    integer range = (num+1) &lt;&lt; (5*scale + 1 + tg_bits);</line>
<line>    end   = start + range&lt;63:0&gt;;</line>
<line></line>
<line>    if end&lt;55&gt; != start&lt;55&gt; then</line>
<line>        // overflow, saturate it</line>
<line>        end = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(start&lt;55&gt;, 64-55) : <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(55);</line>
<line></line>
<line>    return (valid, tg, start, end);</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/TLBIRange" mylink="aarch64.instrs.system.sysops.tlbi.TLBIRange" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TLBIRange()</line>
<line>// ===========</line>
<line>// Extract the input address range information from encoded Xt.</line>
<line></line>
<line link="impl-aarch64.TLBIRange.2" hover="function: (boolean, bits(2), bits(64), bits(64)) TLBIRange(Regime regime, bits(64) Xt)" conts="TLBIRange">(boolean, bits(2), bits(64), bits(64)) <anchor link="impl-aarch64.TLBIRange.2" hover="function: (boolean, bits(2), bits(64), bits(64)) TLBIRange(Regime regime, bits(64) Xt)">TLBIRange</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(64) Xt)</line>
<line>    boolean  valid = TRUE;</line>
<line>    bits(64) start = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>    bits(64) end   = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line></line>
<line>    bits(2) tg        = Xt&lt;47:46&gt;;</line>
<line>    integer scale     = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt&lt;45:44&gt;);</line>
<line>    integer num       = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt&lt;43:39&gt;);</line>
<line>    integer tg_bits;</line>
<line></line>
<line>    if tg == '00' then</line>
<line>        return (FALSE, tg, start, end);</line>
<line></line>
<line>    case tg of</line>
<line>        when '01' // 4KB</line>
<line>            tg_bits = 12;</line>
<line>            if <a link="impl-aarch64.HasLargeAddress.1" file="shared_pseudocode.xml" hover="function: boolean HasLargeAddress(Regime regime)">HasLargeAddress</a>(regime) then</line>
<line>                start&lt;52:16&gt; = Xt&lt;36:0&gt;;</line>
<line>                start&lt;63:53&gt; = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(Xt&lt;36&gt;, 11);</line>
<line>            else</line>
<line>                start&lt;48:12&gt; = Xt&lt;36:0&gt;;</line>
<line>                start&lt;63:49&gt; = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(Xt&lt;36&gt;, 15);</line>
<line>        when '10' // 16KB</line>
<line>            tg_bits = 14;</line>
<line>            if <a link="impl-aarch64.HasLargeAddress.1" file="shared_pseudocode.xml" hover="function: boolean HasLargeAddress(Regime regime)">HasLargeAddress</a>(regime) then</line>
<line>                start&lt;52:16&gt; = Xt&lt;36:0&gt;;</line>
<line>                start&lt;63:53&gt; = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(Xt&lt;36&gt;, 11);</line>
<line>            else</line>
<line>                start&lt;50:14&gt; = Xt&lt;36:0&gt;;</line>
<line>                start&lt;63:51&gt; = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(Xt&lt;36&gt;, 13);</line>
<line>        when '11' // 64KB</line>
<line>            tg_bits = 16;</line>
<line>            start&lt;52:16&gt; = Xt&lt;36:0&gt;;</line>
<line>            start&lt;63:53&gt; = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(Xt&lt;36&gt;, 11);</line>
<line>        otherwise</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    integer range = (num+1) &lt;&lt; (5*scale + 1 + tg_bits);</line>
<line>    end   = start + range&lt;63:0&gt;;</line>
<line></line>
<line>    if end&lt;52&gt; != start&lt;52&gt; then</line>
<line>        // overflow, saturate it</line>
<line>        end = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(start&lt;52&gt;, 64-52) : <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(52);</line>
<line></line>
<line>    return (valid, tg, start, end);</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/TLBIRecord" mylink="aarch64.instrs.system.sysops.tlbi.TLBIRecord" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TLBIRecord</line>
<line>// ==========</line>
<line>// Details related to a TLBI operation.</line>
<line></line>
<line link="TLBIRecord" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )" conts="TLBIRecord">type <anchor link="TLBIRecord" hover="type TLBIRecord is ( TLBIOp op, boolean from_aarch64, SecurityState security, Regime regime, bits(16) vmid, bits(16) asid, TLBILevel level, TLBIMemAttr attr, PASpace ipaspace, bits(64) address, bits(64) end_address, boolean d64, boolean d128, bits(4) ttl, bits(2) tg )">TLBIRecord</anchor> is (</line>
<line>    <a link="TLBIOp" file="shared_pseudocode.xml" hover="enumeration TLBIOp { TLBIOp_DALL, TLBIOp_DASID, TLBIOp_DVA, TLBIOp_IALL, TLBIOp_IASID, TLBIOp_IVA, TLBIOp_ALL, TLBIOp_ASID, TLBIOp_IPAS2, TLBIPOp_IPAS2, TLBIOp_VAA, TLBIOp_VA, TLBIPOp_VAA, TLBIPOp_VA, TLBIOp_VMALL, TLBIOp_VMALLS12, TLBIOp_RIPAS2, TLBIPOp_RIPAS2, TLBIOp_RVAA, TLBIOp_RVA, TLBIPOp_RVAA, TLBIPOp_RVA, TLBIOp_RPA, TLBIOp_PAALL, }">TLBIOp</a>          op,</line>
<line>    boolean         from_aarch64, // originated as an AArch64 operation</line>
<line>    <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a>   security,</line>
<line>    <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a>          regime,</line>
<line>    bits(16)        vmid,</line>
<line>    bits(16)        asid,</line>
<line>    <a link="TLBILevel" file="shared_pseudocode.xml" hover="enumeration TLBILevel { TLBILevel_Any, TLBILevel_Last }">TLBILevel</a>       level,</line>
<line>    <a link="TLBIMemAttr" file="shared_pseudocode.xml" hover="enumeration TLBIMemAttr { TLBI_AllAttr, TLBI_ExcludeXS }">TLBIMemAttr</a>     attr,</line>
<line>    <a link="PASpace" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PASpace</a>         ipaspace,     // For operations that take IPA as input address</line>
<line>    bits(64)        address,      // input address, for range operations, start address</line>
<line>    bits(64)        end_address,  // for range operations, end address</line>
<line>    boolean         d64,          // For operations that evict VMSAv8-64 based TLB entries</line>
<line>    boolean         d128,         // For operations that evict VMSAv9-128 based TLB entries</line>
<line>    bits(4)         ttl,          // translation table walk level holding the leaf entry</line>
<line>                                  // for the address being invalidated</line>
<line>                                  // For Non-Range Invalidations:</line>
<line>                                  //   When the ttl is</line>
<line>                                  //     '00xx'    : this applies to all TLB entries</line>
<line>                                  //     Otherwise : TLBIP instructions invalidates D128 TLB</line>
<line>                                  //                 entries only</line>
<line>                                  //                 TLBI instructions invalidates D64 TLB</line>
<line>                                  //                 entries only</line>
<line>                                  // For Range Invalidations:</line>
<line>                                  //   When the ttl is</line>
<line>                                  //     '00'      : this applies to all TLB entries</line>
<line>                                  //     Otherwise : TLBIP instructions invalidates D128 TLB</line>
<line>                                  //                 entries only</line>
<line>                                  //                 TLBI instructions invalidates D64 TLB</line>
<line>                                  //                 entries only</line>
<line>    bits(2)         tg            // for range operations, translation granule</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/VMID" mylink="aarch64.instrs.system.sysops.tlbi.VMID" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// VMID[]</line>
<line>// ======</line>
<line>// Effective VMID.</line>
<line></line>
<line link="impl-aarch64.VMID.read.0" hover="accessor: bits(16) VMID[]" conts="VMID">bits(16) <anchor link="impl-aarch64.VMID.read.0" hover="accessor: bits(16) VMID[]">VMID</anchor>[]</line>
<line>    if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        if !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>            if <a link="impl-shared.Have16bitVMID.0" file="shared_pseudocode.xml" hover="function: boolean Have16bitVMID()">Have16bitVMID</a>() &amp;&amp; VTCR_EL2.VS == '1' then</line>
<line>                return VTTBR_EL2.VMID;</line>
<line>            else</line>
<line>                return <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(VTTBR_EL2.VMID&lt;7:0&gt;, 16);</line>
<line>        else</line>
<line>            return <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(VTTBR.VMID, 16);</line>
<line>    elsif <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; <a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>() then</line>
<line>        return <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>    else</line>
<line>        return <a link="VMID_NONE" file="shared_pseudocode.xml" hover="constant bits(16) VMID_NONE = Zeros(16)">VMID_NONE</a>;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops/tlbi/VMID_NONE" mylink="aarch64.instrs.system.sysops.tlbi.VMID_NONE" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="VMID_NONE" hover="constant bits(16) VMID_NONE = Zeros(16)" conts="VMID_NONE">constant bits(16) <anchor link="VMID_NONE" hover="constant bits(16) VMID_NONE = Zeros(16)">VMID_NONE</anchor> = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops_128/sysop_128/SysOp128" mylink="aarch64.instrs.system.sysops_128.sysop_128.SysOp128" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SysOp128()</line>
<line>// ==========</line>
<line></line>
<line link="impl-aarch64.SysOp128.4" hover="function: SystemOp SysOp128(bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2)" conts="SysOp128">SystemOp <anchor link="impl-aarch64.SysOp128.4" hover="function: SystemOp SysOp128(bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2)">SysOp128</anchor>(bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2)</line>
<line>    case op1:CRn:CRm:op2 of</line>
<line>        when '000 1000 0001 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAE1OS</line>
<line>        when '000 1000 0001 011' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAAE1OS</line>
<line>        when '000 1000 0001 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VALE1OS</line>
<line>        when '000 1000 0001 111' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAALE1OS</line>
<line>        when '000 1000 0011 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAE1IS</line>
<line>        when '000 1000 0011 011' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAAE1IS</line>
<line>        when '000 1000 0011 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VALE1IS</line>
<line>        when '000 1000 0011 111' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAALE1IS</line>
<line>        when '000 1000 0111 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAE1</line>
<line>        when '000 1000 0111 011' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAAE1</line>
<line>        when '000 1000 0111 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VALE1</line>
<line>        when '000 1000 0111 111' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAALE1</line>
<line>        when '000 1001 0001 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAE1OSNXS</line>
<line>        when '000 1001 0001 011' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAAE1OSNXS</line>
<line>        when '000 1001 0001 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VALE1OSNXS</line>
<line>        when '000 1001 0001 111' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAALE1OSNXS</line>
<line>        when '000 1001 0011 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAE1ISNXS</line>
<line>        when '000 1001 0011 011' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAAE1ISNXS</line>
<line>        when '000 1001 0011 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VALE1ISNXS</line>
<line>        when '000 1001 0011 111' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAALE1ISNXS</line>
<line>        when '000 1001 0111 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAE1NXS</line>
<line>        when '000 1001 0111 011' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAAE1NXS</line>
<line>        when '000 1001 0111 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VALE1NXS</line>
<line>        when '000 1001 0111 111' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAALE1NXS</line>
<line>        when '100 1000 0001 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAE2OS</line>
<line>        when '100 1000 0001 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VALE2OS</line>
<line>        when '100 1000 0011 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAE2IS</line>
<line>        when '100 1000 0011 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VALE2IS</line>
<line>        when '100 1000 0111 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAE2</line>
<line>        when '100 1000 0111 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VALE2</line>
<line>        when '100 1001 0001 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAE2OSNXS</line>
<line>        when '100 1001 0001 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VALE2OSNXS</line>
<line>        when '100 1001 0011 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAE2ISNXS</line>
<line>        when '100 1001 0011 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VALE2ISNXS</line>
<line>        when '100 1001 0111 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAE2NXS</line>
<line>        when '100 1001 0111 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VALE2NXS</line>
<line>        when '110 1000 0001 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAE3OS</line>
<line>        when '110 1000 0001 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VALE3OS</line>
<line>        when '110 1000 0011 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAE3IS</line>
<line>        when '110 1000 0011 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VALE3IS</line>
<line>        when '110 1000 0111 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAE3</line>
<line>        when '110 1000 0111 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VALE3</line>
<line>        when '110 1001 0001 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAE3OSNXS</line>
<line>        when '110 1001 0001 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VALE3OSNXS</line>
<line>        when '110 1001 0011 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAE3ISNXS</line>
<line>        when '110 1001 0011 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VALE3ISNXS</line>
<line>        when '110 1001 0111 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VAE3NXS</line>
<line>        when '110 1001 0111 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // VALE3NXS</line>
<line>        when '100 1000 0000 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // IPAS2E1IS</line>
<line>        when '100 1000 0000 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // IPAS2LE1IS</line>
<line>        when '100 1000 0100 000' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // IPAS2E1OS</line>
<line>        when '100 1000 0100 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // IPAS2E1</line>
<line>        when '100 1000 0100 100' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // IPAS2LE1OS</line>
<line>        when '100 1000 0100 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // IPAS2LE1</line>
<line>        when '100 1001 0000 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // IPAS2E1ISNXS</line>
<line>        when '100 1001 0000 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // IPAS2LE1ISNXS</line>
<line>        when '100 1001 0100 000' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // IPAS2E1OSNXS</line>
<line>        when '100 1001 0100 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // IPAS2E1NXS</line>
<line>        when '100 1001 0100 100' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // IPAS2LE1OSNXS</line>
<line>        when '100 1001 0100 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // IPAS2LE1NXS</line>
<line>        when '000 1000 0010 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAE1IS</line>
<line>        when '000 1000 0010 011' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAAE1IS</line>
<line>        when '000 1000 0010 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVALE1IS</line>
<line>        when '000 1000 0010 111' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAALE1IS</line>
<line>        when '000 1000 0101 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAE1OS</line>
<line>        when '000 1000 0101 011' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAAE1OS</line>
<line>        when '000 1000 0101 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVALE1OS</line>
<line>        when '000 1000 0101 111' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAALE1OS</line>
<line>        when '000 1000 0110 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAE1</line>
<line>        when '000 1000 0110 011' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAAE1</line>
<line>        when '000 1000 0110 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVALE1</line>
<line>        when '000 1000 0110 111' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAALE1</line>
<line>        when '000 1001 0010 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAE1ISNXS</line>
<line>        when '000 1001 0010 011' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAAE1ISNXS</line>
<line>        when '000 1001 0010 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVALE1ISNXS</line>
<line>        when '000 1001 0010 111' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAALE1ISNXS</line>
<line>        when '000 1001 0101 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAE1OSNXS</line>
<line>        when '000 1001 0101 011' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAAE1OSNXS</line>
<line>        when '000 1001 0101 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVALE1OSNXS</line>
<line>        when '000 1001 0101 111' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAALE1OSNXS</line>
<line>        when '000 1001 0110 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAE1NXS</line>
<line>        when '000 1001 0110 011' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAAE1NXS</line>
<line>        when '000 1001 0110 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVALE1NXS</line>
<line>        when '000 1001 0110 111' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAALE1NXS</line>
<line>        when '100 1000 0010 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAE2IS</line>
<line>        when '100 1000 0010 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVALE2IS</line>
<line>        when '100 1000 0101 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAE2OS</line>
<line>        when '100 1000 0101 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVALE2OS</line>
<line>        when '100 1000 0110 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAE2</line>
<line>        when '100 1000 0110 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVALE2</line>
<line>        when '100 1001 0010 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAE2ISNXS</line>
<line>        when '100 1001 0010 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVALE2ISNXS</line>
<line>        when '100 1001 0101 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAE2OSNXS</line>
<line>        when '100 1001 0101 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVALE2OSNXS</line>
<line>        when '100 1001 0110 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAE2NXS</line>
<line>        when '100 1001 0110 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVALE2NXS</line>
<line>        when '110 1000 0010 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAE3IS</line>
<line>        when '110 1000 0010 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVALE3IS</line>
<line>        when '110 1000 0101 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAE3OS</line>
<line>        when '110 1000 0101 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVALE3OS</line>
<line>        when '110 1000 0110 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAE3</line>
<line>        when '110 1000 0110 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVALE3</line>
<line>        when '110 1001 0010 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAE3ISNXS</line>
<line>        when '110 1001 0010 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVALE3ISNXS</line>
<line>        when '110 1001 0101 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAE3OSNXS</line>
<line>        when '110 1001 0101 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVALE3OSNXS</line>
<line>        when '110 1001 0110 001' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVAE3NXS</line>
<line>        when '110 1001 0110 101' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RVALE3NXS</line>
<line>        when '100 1000 0000 010' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RIPAS2E1IS</line>
<line>        when '100 1000 0000 110' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RIPAS2LE1IS</line>
<line>        when '100 1000 0100 010' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RIPAS2E1</line>
<line>        when '100 1000 0100 011' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RIPAS2E1OS</line>
<line>        when '100 1000 0100 110' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RIPAS2LE1</line>
<line>        when '100 1000 0100 111' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RIPAS2LE1OS</line>
<line>        when '100 1001 0000 010' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RIPAS2E1ISNXS</line>
<line>        when '100 1001 0000 110' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RIPAS2LE1ISNXS</line>
<line>        when '100 1001 0100 010' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RIPAS2E1NXS</line>
<line>        when '100 1001 0100 011' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RIPAS2E1OSNXS</line>
<line>        when '100 1001 0100 110' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RIPAS2LE1NXS</line>
<line>        when '100 1001 0100 111' return <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a>;  // RIPAS2LE1OSNXS</line>
<line>        otherwise                return <a link="Sys_SYSP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_SYSP</a>;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/system/sysops_128/sysop_128/SystemOp128" mylink="aarch64.instrs.system.sysops_128.sysop_128.SystemOp128" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SystemOp128()</line>
<line>// =============</line>
<line>// System instruction types.</line>
<line></line>
<line link="SystemOp128" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}" conts="SystemOp128">enumeration <anchor link="SystemOp128" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">SystemOp128</anchor> {<anchor link="Sys_TLBIP" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</anchor>, <anchor link="Sys_SYSP" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_SYSP</anchor>};</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/vector/arithmetic/binary/uniform/logical/bsl-eor/vbitop/VBitOp" mylink="aarch64.instrs.vector.arithmetic.binary.uniform.logical.bsl-eor.vbitop.VBitOp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// VBitOp</line>
<line>// ======</line>
<line>// Vector bit select instruction types.</line>
<line></line>
<line link="VBitOp" hover="enumeration VBitOp      {VBitOp_VBIF, VBitOp_VBIT, VBitOp_VBSL, VBitOp_VEOR}" conts="VBitOp">enumeration <anchor link="VBitOp" hover="enumeration VBitOp      {VBitOp_VBIF, VBitOp_VBIT, VBitOp_VBSL, VBitOp_VEOR}">VBitOp</anchor>      {<anchor link="VBitOp_VBIF" hover="enumeration VBitOp      {VBitOp_VBIF, VBitOp_VBIT, VBitOp_VBSL, VBitOp_VEOR}">VBitOp_VBIF</anchor>, <anchor link="VBitOp_VBIT" hover="enumeration VBitOp      {VBitOp_VBIF, VBitOp_VBIT, VBitOp_VBSL, VBitOp_VEOR}">VBitOp_VBIT</anchor>, <anchor link="VBitOp_VBSL" hover="enumeration VBitOp      {VBitOp_VBIF, VBitOp_VBIT, VBitOp_VBSL, VBitOp_VEOR}">VBitOp_VBSL</anchor>, <anchor link="VBitOp_VEOR" hover="enumeration VBitOp      {VBitOp_VBIF, VBitOp_VBIT, VBitOp_VBSL, VBitOp_VEOR}">VBitOp_VEOR</anchor>};</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/vector/arithmetic/unary/cmp/compareop/CompareOp" mylink="aarch64.instrs.vector.arithmetic.unary.cmp.compareop.CompareOp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CompareOp</line>
<line>// =========</line>
<line>// Vector compare instruction types.</line>
<line></line>
<line link="CompareOp" hover="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}" conts="CompareOp">enumeration <anchor link="CompareOp" hover="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp</anchor>   {<anchor link="CompareOp_GT" hover="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_GT</anchor>, <anchor link="CompareOp_GE" hover="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_GE</anchor>, <anchor link="CompareOp_EQ" hover="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_EQ</anchor>,</line>
<line link="CompareOp_LE" hover="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}" conts="CompareOp_LE">                         <anchor link="CompareOp_LE" hover="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_LE</anchor>, <anchor link="CompareOp_LT" hover="enumeration CompareOp   {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_LT</anchor>};</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/vector/logical/immediateop/ImmediateOp" mylink="aarch64.instrs.vector.logical.immediateop.ImmediateOp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ImmediateOp</line>
<line>// ===========</line>
<line>// Vector logical immediate instruction types.</line>
<line></line>
<line link="ImmediateOp" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}" conts="ImmediateOp">enumeration <anchor link="ImmediateOp" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp</anchor> {<anchor link="ImmediateOp_MOVI" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp_MOVI</anchor>, <anchor link="ImmediateOp_MVNI" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp_MVNI</anchor>,</line>
<line link="ImmediateOp_ORR" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}" conts="ImmediateOp_ORR">                         <anchor link="ImmediateOp_ORR" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp_ORR</anchor>, <anchor link="ImmediateOp_BIC" hover="enumeration ImmediateOp {ImmediateOp_MOVI, ImmediateOp_MVNI, ImmediateOp_ORR, ImmediateOp_BIC}">ImmediateOp_BIC</anchor>};</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/vector/reduce/reduceop/Reduce" mylink="aarch64.instrs.vector.reduce.reduceop.Reduce" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Reduce()</line>
<line>// ========</line>
<line></line>
<line link="impl-aarch64.Reduce.3" hover="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize)" conts="Reduce">bits(esize) <anchor link="impl-aarch64.Reduce.3" hover="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize)">Reduce</anchor>(<a link="ReduceOp" file="shared_pseudocode.xml" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}">ReduceOp</a> op, bits(N) input, integer esize)</line>
<line>    boolean altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; FPCR.AH == '1';</line>
<line>    return <a link="impl-aarch64.Reduce.4" file="shared_pseudocode.xml" hover="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize, boolean altfp)">Reduce</a>(op, input, esize, altfp);</line>
<line></line>
<line>// Reduce()</line>
<line>// ========</line>
<line>// Perform the operation 'op' on pairs of elements from the input vector,</line>
<line>// reducing the vector to a scalar result. The 'altfp' argument controls</line>
<line>// alternative floating-point behavior.</line>
<line></line>
<line link="impl-aarch64.Reduce.4" hover="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize, boolean altfp)" conts="Reduce">bits(esize) <anchor link="impl-aarch64.Reduce.4" hover="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize, boolean altfp)">Reduce</anchor>(<a link="ReduceOp" file="shared_pseudocode.xml" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}">ReduceOp</a> op, bits(N) input, integer esize, boolean altfp)</line>
<line>    integer half;</line>
<line>    bits(esize) hi;</line>
<line>    bits(esize) lo;</line>
<line>    bits(esize) result;</line>
<line></line>
<line>    if N == esize then</line>
<line>        return input&lt;esize-1:0&gt;;</line>
<line></line>
<line>    half = N DIV 2;</line>
<line>    hi = <a link="impl-aarch64.Reduce.4" file="shared_pseudocode.xml" hover="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize, boolean altfp)">Reduce</a>(op, input&lt;N-1:half&gt;, esize, altfp);</line>
<line>    lo = <a link="impl-aarch64.Reduce.4" file="shared_pseudocode.xml" hover="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize, boolean altfp)">Reduce</a>(op, input&lt;half-1:0&gt;, esize, altfp);</line>
<line></line>
<line>    case op of</line>
<line>        when <a link="ReduceOp_FMINNUM" file="shared_pseudocode.xml" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_FMINNUM</a></line>
<line>            result = <a link="impl-shared.FPMinNum.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMinNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)">FPMinNum</a>(lo, hi, FPCR[]);</line>
<line>        when <a link="ReduceOp_FMAXNUM" file="shared_pseudocode.xml" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_FMAXNUM</a></line>
<line>            result = <a link="impl-shared.FPMaxNum.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMaxNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)">FPMaxNum</a>(lo, hi, FPCR[]);</line>
<line>        when <a link="ReduceOp_FMIN" file="shared_pseudocode.xml" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_FMIN</a></line>
<line>            result = <a link="impl-shared.FPMin.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr_in, boolean altfp)">FPMin</a>(lo, hi, FPCR[], altfp);</line>
<line>        when <a link="ReduceOp_FMAX" file="shared_pseudocode.xml" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_FMAX</a></line>
<line>            result = <a link="impl-shared.FPMax.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr_in, boolean altfp)">FPMax</a>(lo, hi, FPCR[], altfp);</line>
<line>        when <a link="ReduceOp_FADD" file="shared_pseudocode.xml" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_FADD</a></line>
<line>            result = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(lo, hi, FPCR[]);</line>
<line>        when <a link="ReduceOp_ADD" file="shared_pseudocode.xml" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_ADD</a></line>
<line>            result = lo + hi;</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch64/instrs/vector/reduce/reduceop/ReduceOp" mylink="aarch64.instrs.vector.reduce.reduceop.ReduceOp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ReduceOp</line>
<line>// ========</line>
<line>// Vector reduce instruction types.</line>
<line></line>
<line link="ReduceOp" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}" conts="ReduceOp">enumeration <anchor link="ReduceOp" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}">ReduceOp</anchor> {<anchor link="ReduceOp_FMINNUM" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_FMINNUM</anchor>, <anchor link="ReduceOp_FMAXNUM" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_FMAXNUM</anchor>,</line>
<line link="ReduceOp_FMIN" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}" conts="ReduceOp_FMIN">                      <anchor link="ReduceOp_FMIN" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_FMIN</anchor>, <anchor link="ReduceOp_FMAX" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_FMAX</anchor>,</line>
<line link="ReduceOp_FADD" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}" conts="ReduceOp_FADD">                      <anchor link="ReduceOp_FADD" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_FADD</anchor>, <anchor link="ReduceOp_ADD" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_ADD</anchor>};</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/attrs/AArch64.MAIRAttr" mylink="aarch64.translation.attrs.AArch64.MAIRAttr" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.MAIRAttr()</line>
<line>// ==================</line>
<line>// Retrieve the memory attribute encoding indexed in the given MAIR</line>
<line></line>
<line>bits(8) AArch64.MAIRAttr(integer index, MAIRType mair2, MAIRType mair)</line>
<line>    bit_index = 8 * index;</line>
<line>    assert (index &lt; 8 || (<a link="impl-shared.HaveAIEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAIEExt()">HaveAIEExt</a>() &amp;&amp; (index &lt; 16)));</line>
<line>    if (index &gt; 7) then</line>
<line>        bit_index = bit_index - 64;                      // Read from LSB at MAIR2</line>
<line>        return mair2&lt;bit_index+7:bit_index&gt;;</line>
<line>    else</line>
<line>        return mair&lt;bit_index+7:bit_index&gt;;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/debug/AArch64.CheckBreakpoint" mylink="aarch64.translation.debug.AArch64.CheckBreakpoint" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.CheckBreakpoint()</line>
<line>// =========================</line>
<line>// Called before executing the instruction of length "size" bytes at "vaddress" in an AArch64</line>
<line>// translation regime, when either debug exceptions are enabled, or halting debug is enabled</line>
<line>// and halting is allowed.</line>
<line></line>
<line link="AArch64.CheckBreakpoint.4" hover="function: FaultRecord AArch64.CheckBreakpoint(FaultRecord fault_in, bits(64) vaddress, AccessDescriptor accdesc, integer size)" conts="AArch64.CheckBreakpoint">FaultRecord <anchor link="AArch64.CheckBreakpoint.4" hover="function: FaultRecord AArch64.CheckBreakpoint(FaultRecord fault_in, bits(64) vaddress, AccessDescriptor accdesc, integer size)">AArch64.CheckBreakpoint</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault_in, bits(64) vaddress,</line>
<line>                                    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, integer size)</line>
<line>    assert !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>());</line>
<line>    assert (<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; size IN {2,4}) || size == 4;</line>
<line></line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = fault_in;</line>
<line></line>
<line>    for i = 0 to <a link="impl-shared.NumBreakpointsImplemented.0" file="shared_pseudocode.xml" hover="function: integer NumBreakpointsImplemented()">NumBreakpointsImplemented</a>() - 1</line>
<line>        if <a link="AArch64.BreakpointMatch.4" file="shared_pseudocode.xml" hover="function: boolean AArch64.BreakpointMatch(integer n, bits(64) vaddress, AccessDescriptor accdesc, integer size)">AArch64.BreakpointMatch</a>(i, vaddress, accdesc, size) then</line>
<line>            fault.statuscode = <a link="Fault_Debug" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Debug</a>;</line>
<line></line>
<line>    if fault.statuscode == <a link="Fault_Debug" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Debug</a> &amp;&amp; <a link="impl-shared.HaltOnBreakpointOrWatchpoint.0" file="shared_pseudocode.xml" hover="function: boolean HaltOnBreakpointOrWatchpoint()">HaltOnBreakpointOrWatchpoint</a>() then</line>
<line>        reason = <a link="DebugHalt_Breakpoint" file="shared_pseudocode.xml" hover="constant bits(6) DebugHalt_Breakpoint = '000111'">DebugHalt_Breakpoint</a>;</line>
<line>        <a link="impl-shared.Halt.1" file="shared_pseudocode.xml" hover="function: Halt(bits(6) reason)">Halt</a>(reason);</line>
<line></line>
<line>    return fault;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/debug/AArch64.CheckDebug" mylink="aarch64.translation.debug.AArch64.CheckDebug" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.CheckDebug()</line>
<line>// ====================</line>
<line>// Called on each access to check for a debug exception or entry to Debug state.</line>
<line></line>
<line link="AArch64.CheckDebug.3" hover="function: FaultRecord AArch64.CheckDebug(bits(64) vaddress, AccessDescriptor accdesc, integer size)" conts="AArch64.CheckDebug">FaultRecord <anchor link="AArch64.CheckDebug.3" hover="function: FaultRecord AArch64.CheckDebug(bits(64) vaddress, AccessDescriptor accdesc, integer size)">AArch64.CheckDebug</anchor>(bits(64) vaddress, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, integer size)</line>
<line></line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = <a link="impl-shared.NoFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord NoFault(AccessDescriptor accdesc)">NoFault</a>(accdesc);</line>
<line>    boolean generate_exception;</line>
<line></line>
<line>    boolean d_side = (<a link="impl-shared.IsDataAccess.1" file="shared_pseudocode.xml" hover="function: boolean IsDataAccess(AccessType acctype)">IsDataAccess</a>(accdesc.acctype) || accdesc.acctype == <a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>);</line>
<line>    boolean i_side = (accdesc.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a>);</line>
<line>    if accdesc.acctype == <a link="AccessType_NV2" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_NV2</a> then</line>
<line>        mask = '0';</line>
<line>        ss = <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>();</line>
<line>        generate_exception = (<a link="AArch64.GenerateDebugExceptionsFrom.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.GenerateDebugExceptionsFrom(bits(2) from_el, SecurityState from_state, bit mask)">AArch64.GenerateDebugExceptionsFrom</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, ss, mask) &amp;&amp;</line>
<line>                              MDSCR_EL1.MDE == '1');</line>
<line>    else</line>
<line>        generate_exception = <a link="AArch64.GenerateDebugExceptions.0" file="shared_pseudocode.xml" hover="function: boolean AArch64.GenerateDebugExceptions()">AArch64.GenerateDebugExceptions</a>() &amp;&amp; MDSCR_EL1.MDE == '1';</line>
<line>    halt = <a link="impl-shared.HaltOnBreakpointOrWatchpoint.0" file="shared_pseudocode.xml" hover="function: boolean HaltOnBreakpointOrWatchpoint()">HaltOnBreakpointOrWatchpoint</a>();</line>
<line></line>
<line>    if generate_exception || halt then</line>
<line>        if d_side then</line>
<line>            fault = <a link="AArch64.CheckWatchpoint.4" file="shared_pseudocode.xml" hover="function: FaultRecord AArch64.CheckWatchpoint(FaultRecord fault_in, bits(64) vaddress, AccessDescriptor accdesc, integer size)">AArch64.CheckWatchpoint</a>(fault, vaddress, accdesc, size);</line>
<line>        elsif i_side then</line>
<line>            fault = <a link="AArch64.CheckBreakpoint.4" file="shared_pseudocode.xml" hover="function: FaultRecord AArch64.CheckBreakpoint(FaultRecord fault_in, bits(64) vaddress, AccessDescriptor accdesc, integer size)">AArch64.CheckBreakpoint</a>(fault, vaddress, accdesc, size);</line>
<line></line>
<line>    return fault;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/debug/AArch64.CheckWatchpoint" mylink="aarch64.translation.debug.AArch64.CheckWatchpoint" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.CheckWatchpoint()</line>
<line>// =========================</line>
<line>// Called before accessing the memory location of "size" bytes at "address",</line>
<line>// when either debug exceptions are enabled for the access, or halting debug</line>
<line>// is enabled and halting is allowed.</line>
<line></line>
<line link="AArch64.CheckWatchpoint.4" hover="function: FaultRecord AArch64.CheckWatchpoint(FaultRecord fault_in, bits(64) vaddress, AccessDescriptor accdesc, integer size)" conts="AArch64.CheckWatchpoint">FaultRecord <anchor link="AArch64.CheckWatchpoint.4" hover="function: FaultRecord AArch64.CheckWatchpoint(FaultRecord fault_in, bits(64) vaddress, AccessDescriptor accdesc, integer size)">AArch64.CheckWatchpoint</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault_in, bits(64) vaddress,</line>
<line>                                    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, integer size)</line>
<line>    assert !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="impl-shared.S1TranslationRegime.0" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</a>());</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = fault_in;</line>
<line></line>
<line>    if accdesc.acctype == <a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a> then</line>
<line>        if accdesc.cacheop != <a link="CacheOp_Invalidate" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_Invalidate</a> then</line>
<line>            return fault;</line>
<line>    elsif !<a link="impl-shared.IsDataAccess.1" file="shared_pseudocode.xml" hover="function: boolean IsDataAccess(AccessType acctype)">IsDataAccess</a>(accdesc.acctype) then</line>
<line>        return fault;</line>
<line></line>
<line>    for i = 0 to <a link="impl-shared.NumWatchpointsImplemented.0" file="shared_pseudocode.xml" hover="function: integer NumWatchpointsImplemented()">NumWatchpointsImplemented</a>() - 1</line>
<line>        if <a link="AArch64.WatchpointMatch.4" file="shared_pseudocode.xml" hover="function: boolean AArch64.WatchpointMatch(integer n, bits(64) vaddress, integer size, AccessDescriptor accdesc)">AArch64.WatchpointMatch</a>(i, vaddress, size, accdesc) then</line>
<line>            fault.statuscode = <a link="Fault_Debug" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Debug</a>;</line>
<line>            if DBGWCR_EL1[i].LSC&lt;0&gt; == '1' &amp;&amp; accdesc.read then</line>
<line>                fault.write = FALSE;</line>
<line>            elsif DBGWCR_EL1[i].LSC&lt;1&gt; == '1' &amp;&amp; accdesc.write then</line>
<line>                fault.write = TRUE;</line>
<line></line>
<line>    if (fault.statuscode == <a link="Fault_Debug" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Debug</a> &amp;&amp; <a link="impl-shared.HaltOnBreakpointOrWatchpoint.0" file="shared_pseudocode.xml" hover="function: boolean HaltOnBreakpointOrWatchpoint()">HaltOnBreakpointOrWatchpoint</a>() &amp;&amp;</line>
<line>            !accdesc.nonfault &amp;&amp; !(accdesc.firstfault &amp;&amp; !accdesc.first)) then</line>
<line>        reason = <a link="DebugHalt_Watchpoint" file="shared_pseudocode.xml" hover="constant bits(6) DebugHalt_Watchpoint = '101011'">DebugHalt_Watchpoint</a>;</line>
<line>        EDWAR = vaddress;</line>
<line>        <a link="impl-shared.Halt.1" file="shared_pseudocode.xml" hover="function: Halt(bits(6) reason)">Halt</a>(reason);</line>
<line></line>
<line>    return fault;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_addrcalc/AArch64.IASize" mylink="aarch64.translation.vmsa_addrcalc.AArch64.IASize" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.IASize()</line>
<line>// ================</line>
<line>// Retrieve the number of bits containing the input address</line>
<line></line>
<line link="AArch64.IASize.1" hover="function: integer AArch64.IASize(bits(6) txsz)" conts="AArch64.IASize">integer <anchor link="AArch64.IASize.1" hover="function: integer AArch64.IASize(bits(6) txsz)">AArch64.IASize</anchor>(bits(6) txsz)</line>
<line>    return 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(txsz);</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_addrcalc/AArch64.LeafBase" mylink="aarch64.translation.vmsa_addrcalc.AArch64.LeafBase" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.LeafBase()</line>
<line>// ==================</line>
<line>// Extract the address embedded in a block and page descriptor pointing to the</line>
<line>// base of a memory block</line>
<line></line>
<line link="AArch64.LeafBase.5" hover="function: bits(56) AArch64.LeafBase(bits(N) descriptor, bit d128, bit ds, TGx tgx, integer level)" conts="AArch64.LeafBase">bits(56) <anchor link="AArch64.LeafBase.5" hover="function: bits(56) AArch64.LeafBase(bits(N) descriptor, bit d128, bit ds, TGx tgx, integer level)">AArch64.LeafBase</anchor>(bits(N) descriptor, bit d128, bit ds,</line>
<line>                               <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tgx, integer level)</line>
<line>    bits(56) leafbase = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(56);</line>
<line></line>
<line>    granulebits  = <a link="impl-shared.TGxGranuleBits.1" file="shared_pseudocode.xml" hover="function: integer TGxGranuleBits(TGx tgx)">TGxGranuleBits</a>(tgx);</line>
<line>    descsizelog2 = if d128 == '1' then 4 else 3;</line>
<line>    stride      = granulebits - descsizelog2;</line>
<line>    leafsize    = granulebits + stride * (<a link="FINAL_LEVEL" file="shared_pseudocode.xml" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</a> - level);</line>
<line></line>
<line>    leafbase&lt;47:0&gt; = descriptor&lt;47:leafsize&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(leafsize);</line>
<line></line>
<line>    if <a link="impl-shared.Have56BitPAExt.0" file="shared_pseudocode.xml" hover="function: boolean Have56BitPAExt()">Have56BitPAExt</a>() &amp;&amp; d128 == '1' then</line>
<line>        leafbase&lt;55:48&gt; = descriptor&lt;55:48&gt;;</line>
<line>        return leafbase;</line>
<line>    if <a link="impl-shared.Have52BitPAExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitPAExt()">Have52BitPAExt</a>() &amp;&amp; tgx == <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a> then</line>
<line>        leafbase&lt;51:48&gt; = descriptor&lt;15:12&gt;;</line>
<line>    elsif ds == '1' then</line>
<line>        leafbase&lt;51:48&gt; = descriptor&lt;9:8&gt;:descriptor&lt;49:48&gt;;</line>
<line></line>
<line>    return leafbase;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_addrcalc/AArch64.NextTableBase" mylink="aarch64.translation.vmsa_addrcalc.AArch64.NextTableBase" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.NextTableBase()</line>
<line>// =======================</line>
<line>// Extract the address embedded in a table descriptor pointing to the base of</line>
<line>// the next level table of descriptors</line>
<line></line>
<line link="AArch64.NextTableBase.4" hover="function: bits(56) AArch64.NextTableBase(bits(N) descriptor, bit d128, bit ds, TGx tgx)" conts="AArch64.NextTableBase">bits(56) <anchor link="AArch64.NextTableBase.4" hover="function: bits(56) AArch64.NextTableBase(bits(N) descriptor, bit d128, bit ds, TGx tgx)">AArch64.NextTableBase</anchor>(bits(N) descriptor, bit d128, bit ds, <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tgx)</line>
<line>    bits(56) tablebase = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(56);</line>
<line></line>
<line>    case tgx of</line>
<line>        when <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>  tablebase&lt;47:12&gt; = descriptor&lt;47:12&gt;;</line>
<line>        when <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a> tablebase&lt;47:14&gt; = descriptor&lt;47:14&gt;;</line>
<line>        when <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a> tablebase&lt;47:16&gt; = descriptor&lt;47:16&gt;;</line>
<line></line>
<line>    if <a link="impl-shared.Have56BitPAExt.0" file="shared_pseudocode.xml" hover="function: boolean Have56BitPAExt()">Have56BitPAExt</a>() &amp;&amp; d128 == '1' then</line>
<line>        tablebase&lt;55:48&gt; = descriptor&lt;55:48&gt;;</line>
<line>        return tablebase;</line>
<line>    if <a link="impl-shared.Have52BitPAExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitPAExt()">Have52BitPAExt</a>() &amp;&amp; tgx == <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a> then</line>
<line>        tablebase&lt;51:48&gt; = descriptor&lt;15:12&gt;;</line>
<line>        return tablebase;</line>
<line>    if ds == '1' then</line>
<line>        tablebase&lt;51:48&gt; = descriptor&lt;9:8&gt;:descriptor&lt;49:48&gt;;</line>
<line>        return tablebase;</line>
<line>    return tablebase;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_addrcalc/AArch64.PhysicalAddressSize" mylink="aarch64.translation.vmsa_addrcalc.AArch64.PhysicalAddressSize" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.PhysicalAddressSize()</line>
<line>// =============================</line>
<line>// Retrieve the number of bits bounding the physical address</line>
<line></line>
<line link="AArch64.PhysicalAddressSize.3" hover="function: integer AArch64.PhysicalAddressSize(bit d128, bits(3) encoded_ps, TGx tgx)" conts="AArch64.PhysicalAddressSize">integer <anchor link="AArch64.PhysicalAddressSize.3" hover="function: integer AArch64.PhysicalAddressSize(bit d128, bits(3) encoded_ps, TGx tgx)">AArch64.PhysicalAddressSize</anchor>(bit d128, bits(3) encoded_ps, <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tgx)</line>
<line>    integer ps;</line>
<line>    integer max_ps;</line>
<line></line>
<line>    case encoded_ps of</line>
<line>        when '000'  ps = 32;</line>
<line>        when '001'  ps = 36;</line>
<line>        when '010'  ps = 40;</line>
<line>        when '011'  ps = 42;</line>
<line>        when '100'  ps = 44;</line>
<line>        when '101'  ps = 48;</line>
<line>        when '110'  ps = 52;</line>
<line>        when '111'  ps = 56;</line>
<line>    if !<a link="impl-shared.Have56BitPAExt.0" file="shared_pseudocode.xml" hover="function: boolean Have56BitPAExt()">Have56BitPAExt</a>() || d128 == '0' then</line>
<line>        if tgx != <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a> &amp;&amp; !<a link="impl-shared.Have52BitIPAAndPASpaceExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitIPAAndPASpaceExt()">Have52BitIPAAndPASpaceExt</a>() then</line>
<line>            max_ps = <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(48, <a link="AArch64.PAMax.0" file="shared_pseudocode.xml" hover="function: integer AArch64.PAMax()">AArch64.PAMax</a>());</line>
<line>        elsif !<a link="impl-shared.Have52BitPAExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitPAExt()">Have52BitPAExt</a>() then</line>
<line>            max_ps = <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(48, <a link="AArch64.PAMax.0" file="shared_pseudocode.xml" hover="function: integer AArch64.PAMax()">AArch64.PAMax</a>());</line>
<line>        else</line>
<line>            max_ps = <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(52, <a link="AArch64.PAMax.0" file="shared_pseudocode.xml" hover="function: integer AArch64.PAMax()">AArch64.PAMax</a>());</line>
<line>    else</line>
<line>        max_ps = <a link="AArch64.PAMax.0" file="shared_pseudocode.xml" hover="function: integer AArch64.PAMax()">AArch64.PAMax</a>();</line>
<line></line>
<line>    return <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(ps, max_ps);</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_addrcalc/AArch64.S1SLTTEntryAddress" mylink="aarch64.translation.vmsa_addrcalc.AArch64.S1SLTTEntryAddress" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1SLTTEntryAddress()</line>
<line>// ============================</line>
<line>// Compute the first stage 1 translation table descriptor address within the</line>
<line>// table pointed to by the base at the start level</line>
<line></line>
<line><a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> AArch64.S1SLTTEntryAddress(integer level, S1TTWParams walkparams,</line>
<line>                                       bits(64) ia, <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> tablebase)</line>
<line>    // Input Address size</line>
<line>    iasize       = <a link="AArch64.IASize.1" file="shared_pseudocode.xml" hover="function: integer AArch64.IASize(bits(6) txsz)">AArch64.IASize</a>(walkparams.txsz);</line>
<line>    granulebits  = <a link="impl-shared.TGxGranuleBits.1" file="shared_pseudocode.xml" hover="function: integer TGxGranuleBits(TGx tgx)">TGxGranuleBits</a>(walkparams.tgx);</line>
<line>    descsizelog2 = if walkparams.d128 == '1' then 4 else 3;</line>
<line>    stride       = granulebits - descsizelog2;</line>
<line>    levels       = <a link="FINAL_LEVEL" file="shared_pseudocode.xml" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</a> - level;</line>
<line></line>
<line>    bits(56) index;</line>
<line>    lsb   = levels*stride + granulebits;</line>
<line>    msb   = iasize - 1;</line>
<line>    index = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(ia&lt;msb:lsb&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(descsizelog2), 56);</line>
<line></line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> descaddress;</line>
<line>    descaddress.address = tablebase.address OR index;</line>
<line>    descaddress.paspace = tablebase.paspace;</line>
<line></line>
<line>    return descaddress;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_addrcalc/AArch64.S1StartLevel" mylink="aarch64.translation.vmsa_addrcalc.AArch64.S1StartLevel" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1StartLevel()</line>
<line>// ======================</line>
<line>// Compute the initial lookup level when performing a stage 1 translation</line>
<line>// table walk</line>
<line></line>
<line>integer AArch64.S1StartLevel(S1TTWParams walkparams)</line>
<line>    // Input Address size</line>
<line>    iasize       = <a link="AArch64.IASize.1" file="shared_pseudocode.xml" hover="function: integer AArch64.IASize(bits(6) txsz)">AArch64.IASize</a>(walkparams.txsz);</line>
<line>    granulebits  = <a link="impl-shared.TGxGranuleBits.1" file="shared_pseudocode.xml" hover="function: integer TGxGranuleBits(TGx tgx)">TGxGranuleBits</a>(walkparams.tgx);</line>
<line>    descsizelog2 = if walkparams.d128 == '1' then 4 else 3;</line>
<line>    stride       = granulebits - descsizelog2;</line>
<line>    s1startlevel = <a link="FINAL_LEVEL" file="shared_pseudocode.xml" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</a> - (((iasize-1) - granulebits) DIV stride);</line>
<line>    if walkparams.d128 == '1' then</line>
<line>        s1startlevel = s1startlevel + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(walkparams.skl);</line>
<line>    return s1startlevel;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_addrcalc/AArch64.S2SLTTEntryAddress" mylink="aarch64.translation.vmsa_addrcalc.AArch64.S2SLTTEntryAddress" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S2SLTTEntryAddress()</line>
<line>// ============================</line>
<line>// Compute the first stage 2 translation table descriptor address within the</line>
<line>// table pointed to by the base at the start level</line>
<line></line>
<line><a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> AArch64.S2SLTTEntryAddress(S2TTWParams walkparams, bits(56) ipa,</line>
<line>                                       <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> tablebase)</line>
<line>    startlevel   = AArch64.S2StartLevel(walkparams);</line>
<line>    iasize       = <a link="AArch64.IASize.1" file="shared_pseudocode.xml" hover="function: integer AArch64.IASize(bits(6) txsz)">AArch64.IASize</a>(walkparams.txsz);</line>
<line>    granulebits  = <a link="impl-shared.TGxGranuleBits.1" file="shared_pseudocode.xml" hover="function: integer TGxGranuleBits(TGx tgx)">TGxGranuleBits</a>(walkparams.tgx);</line>
<line>    descsizelog2 = if walkparams.d128 == '1' then 4 else 3;</line>
<line>    stride       = granulebits - descsizelog2;</line>
<line>    levels       = <a link="FINAL_LEVEL" file="shared_pseudocode.xml" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</a> - startlevel;</line>
<line></line>
<line>    bits(56) index;</line>
<line>    integer lsb;</line>
<line>    integer msb;</line>
<line>    lsb   = levels*stride + granulebits;</line>
<line>    msb   = iasize - 1;</line>
<line>    index = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(ipa&lt;msb:lsb&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(descsizelog2), 56);</line>
<line></line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> descaddress;</line>
<line>    descaddress.address = tablebase.address OR index;</line>
<line>    descaddress.paspace = tablebase.paspace;</line>
<line></line>
<line>    return descaddress;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_addrcalc/AArch64.S2StartLevel" mylink="aarch64.translation.vmsa_addrcalc.AArch64.S2StartLevel" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S2StartLevel()</line>
<line>// ======================</line>
<line>// Determine the initial lookup level when performing a stage 2 translation</line>
<line>// table walk</line>
<line></line>
<line>integer AArch64.S2StartLevel(S2TTWParams walkparams)</line>
<line>    if walkparams.d128 == '1' then</line>
<line>        iasize       = <a link="AArch64.IASize.1" file="shared_pseudocode.xml" hover="function: integer AArch64.IASize(bits(6) txsz)">AArch64.IASize</a>(walkparams.txsz);</line>
<line>        granulebits  = <a link="impl-shared.TGxGranuleBits.1" file="shared_pseudocode.xml" hover="function: integer TGxGranuleBits(TGx tgx)">TGxGranuleBits</a>(walkparams.tgx);</line>
<line>        descsizelog2 = 4;</line>
<line>        stride       = granulebits - descsizelog2;</line>
<line>        s2startlevel = <a link="FINAL_LEVEL" file="shared_pseudocode.xml" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</a> - (((iasize-1) - granulebits) DIV stride);</line>
<line>        s2startlevel = s2startlevel + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(walkparams.skl);</line>
<line></line>
<line>        return s2startlevel;</line>
<line></line>
<line>    case walkparams.tgx of</line>
<line>        when <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a></line>
<line>            case walkparams.sl2:walkparams.sl0 of</line>
<line>                when '000' return 2;</line>
<line>                when '001' return 1;</line>
<line>                when '010' return 0;</line>
<line>                when '011' return 3;</line>
<line>                when '100' return -1;</line>
<line>        when <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a></line>
<line>            case walkparams.sl0 of</line>
<line>                when '00' return 3;</line>
<line>                when '01' return 2;</line>
<line>                when '10' return 1;</line>
<line>                when '11' return 0;</line>
<line>        when <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a></line>
<line>            case walkparams.sl0 of</line>
<line>                when '00' return 3;</line>
<line>                when '01' return 2;</line>
<line>                when '10' return 1;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_addrcalc/AArch64.TTBaseAddress" mylink="aarch64.translation.vmsa_addrcalc.AArch64.TTBaseAddress" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TTBaseAddress()</line>
<line>// =======================</line>
<line>// Retrieve the PA/IPA pointing to the base of the initial translation table</line>
<line></line>
<line link="AArch64.TTBaseAddress.7" hover="function: bits(56) AArch64.TTBaseAddress(bits(64) ttb, bits(6) txsz, bits(3) ps, bit d128, bit ds, TGx tgx, integer startlevel)" conts="AArch64.TTBaseAddress">bits(56) <anchor link="AArch64.TTBaseAddress.7" hover="function: bits(56) AArch64.TTBaseAddress(bits(64) ttb, bits(6) txsz, bits(3) ps, bit d128, bit ds, TGx tgx, integer startlevel)">AArch64.TTBaseAddress</anchor>(bits(64) ttb, bits(6) txsz, bits(3) ps,</line>
<line>                                   bit d128, bit ds, <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tgx, integer startlevel)</line>
<line>    bits(56) tablebase = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(56);</line>
<line></line>
<line>    // Input Address size</line>
<line>    iasize      = <a link="AArch64.IASize.1" file="shared_pseudocode.xml" hover="function: integer AArch64.IASize(bits(6) txsz)">AArch64.IASize</a>(txsz);</line>
<line>    granulebits = <a link="impl-shared.TGxGranuleBits.1" file="shared_pseudocode.xml" hover="function: integer TGxGranuleBits(TGx tgx)">TGxGranuleBits</a>(tgx);</line>
<line>    descsizelog2 = if d128 == '1' then 4 else 3;</line>
<line>    stride      = granulebits - descsizelog2;</line>
<line>    levels      = <a link="FINAL_LEVEL" file="shared_pseudocode.xml" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</a> - startlevel;</line>
<line></line>
<line>    // Base address is aligned to size of the initial translation table in bytes</line>
<line>    tsize = (iasize - (levels*stride + granulebits)) + descsizelog2;</line>
<line></line>
<line>    if <a link="impl-shared.Have56BitPAExt.0" file="shared_pseudocode.xml" hover="function: boolean Have56BitPAExt()">Have56BitPAExt</a>() &amp;&amp;  d128 == '1' then</line>
<line>        tsize = <a link="impl-shared.Max.2" file="shared_pseudocode.xml" hover="function: integer Max(integer a, integer b)">Max</a>(tsize, 5);</line>
<line>        tablebase&lt;55:5&gt; = ttb&lt;50:0&gt;;</line>
<line>    elsif (<a link="impl-shared.Have52BitPAExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitPAExt()">Have52BitPAExt</a>() &amp;&amp; tgx == <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a> &amp;&amp; ps == '110') || (ds == '1') then</line>
<line>        tsize = <a link="impl-shared.Max.2" file="shared_pseudocode.xml" hover="function: integer Max(integer a, integer b)">Max</a>(tsize, 6);</line>
<line>        tablebase&lt;51:6&gt; = ttb&lt;4:1&gt;:ttb&lt;46:5&gt;;</line>
<line>    else</line>
<line>        tablebase&lt;47:1&gt; = ttb&lt;46:0&gt;;</line>
<line>    tablebase = <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(tablebase, 1 &lt;&lt; tsize);</line>
<line>    return tablebase;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_addrcalc/AArch64.TTEntryAddress" mylink="aarch64.translation.vmsa_addrcalc.AArch64.TTEntryAddress" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TTEntryAddress()</line>
<line>// ========================</line>
<line>// Compute translation table descriptor address within the table pointed to by</line>
<line>// the table base</line>
<line></line>
<line link="AArch64.TTEntryAddress.7" hover="function: FullAddress AArch64.TTEntryAddress(integer level, bit d128, bits(2) skl, TGx tgx, bits(6) txsz, bits(64) ia, FullAddress tablebase)" conts="AArch64.TTEntryAddress">FullAddress <anchor link="AArch64.TTEntryAddress.7" hover="function: FullAddress AArch64.TTEntryAddress(integer level, bit d128, bits(2) skl, TGx tgx, bits(6) txsz, bits(64) ia, FullAddress tablebase)">AArch64.TTEntryAddress</anchor>(integer level, bit d128, bits(2) skl, <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tgx, bits(6) txsz,</line>
<line>                                   bits(64) ia, <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> tablebase)</line>
<line>    // Input Address size</line>
<line>    iasize      = <a link="AArch64.IASize.1" file="shared_pseudocode.xml" hover="function: integer AArch64.IASize(bits(6) txsz)">AArch64.IASize</a>(txsz);</line>
<line>    granulebits = <a link="impl-shared.TGxGranuleBits.1" file="shared_pseudocode.xml" hover="function: integer TGxGranuleBits(TGx tgx)">TGxGranuleBits</a>(tgx);</line>
<line>    descsizelog2 = if d128 == '1' then 4 else 3;</line>
<line>    stride      = granulebits - descsizelog2;</line>
<line>    levels      = <a link="FINAL_LEVEL" file="shared_pseudocode.xml" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</a> - level;</line>
<line></line>
<line>    bits(56) index;</line>
<line>    integer lsb;</line>
<line>    integer msb;</line>
<line></line>
<line>    lsb   = levels*stride + granulebits;</line>
<line>    if d128 == '1' then</line>
<line>        msb   = (lsb + stride*(1 + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(skl))) - 1;</line>
<line>    else</line>
<line>        msb   = (lsb + stride) - 1;</line>
<line>    index = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(ia&lt;msb:lsb&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(descsizelog2), 56);</line>
<line></line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> descaddress;</line>
<line>    descaddress.address = tablebase.address OR index;</line>
<line>    descaddress.paspace = tablebase.paspace;</line>
<line></line>
<line>    return descaddress;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_faults/AArch64.AddrTop" mylink="aarch64.translation.vmsa_faults.AArch64.AddrTop" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.AddrTop()</line>
<line>// =================</line>
<line>// Get the top bit position of the virtual address.</line>
<line>// Bits above are not accounted as part of the translation process.</line>
<line></line>
<line link="AArch64.AddrTop.3" hover="function: integer AArch64.AddrTop(bit tbid, AccessType acctype, bit tbi)" conts="AArch64.AddrTop">integer <anchor link="AArch64.AddrTop.3" hover="function: integer AArch64.AddrTop(bit tbid, AccessType acctype, bit tbi)">AArch64.AddrTop</anchor>(bit tbid, <a link="AccessType" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType</a> acctype, bit tbi)</line>
<line>    if tbid == '1' &amp;&amp; acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> then</line>
<line>        return 63;</line>
<line></line>
<line>    if tbi == '1' then</line>
<line>        return 55;</line>
<line>    else</line>
<line>        return 63;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_faults/AArch64.ContiguousBitFaults" mylink="aarch64.translation.vmsa_faults.AArch64.ContiguousBitFaults" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ContiguousBitFaults()</line>
<line>// =============================</line>
<line>// If contiguous bit is set, returns whether the translation size exceeds the</line>
<line>// input address size and if the implementation generates a fault</line>
<line></line>
<line link="AArch64.ContiguousBitFaults.4" hover="function: boolean AArch64.ContiguousBitFaults(bit d128, bits(6) txsz, TGx tgx, integer level)" conts="AArch64.ContiguousBitFaults">boolean <anchor link="AArch64.ContiguousBitFaults.4" hover="function: boolean AArch64.ContiguousBitFaults(bit d128, bits(6) txsz, TGx tgx, integer level)">AArch64.ContiguousBitFaults</anchor>(bit d128, bits(6) txsz, <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tgx, integer level)</line>
<line>    // Input Address size</line>
<line>    iasize = <a link="AArch64.IASize.1" file="shared_pseudocode.xml" hover="function: integer AArch64.IASize(bits(6) txsz)">AArch64.IASize</a>(txsz);</line>
<line>    // Translation size</line>
<line>    tsize  = <a link="impl-shared.TranslationSize.3" file="shared_pseudocode.xml" hover="function: integer TranslationSize(bit d128, TGx tgx, integer level)">TranslationSize</a>(d128, tgx, level) + <a link="impl-shared.ContiguousSize.3" file="shared_pseudocode.xml" hover="function: integer ContiguousSize(bit d128, TGx tgx, integer level)">ContiguousSize</a>(d128, tgx, level);</line>
<line></line>
<line>    return (tsize &gt; iasize &amp;&amp;</line>
<line>            boolean IMPLEMENTATION_DEFINED "Translation fault on misprogrammed contiguous bit");</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_faults/AArch64.IPAIsOutOfRange" mylink="aarch64.translation.vmsa_faults.AArch64.IPAIsOutOfRange" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.IPAIsOutOfRange()</line>
<line>// =========================</line>
<line>// Check bits not resolved by translation are ZERO</line>
<line></line>
<line>boolean AArch64.IPAIsOutOfRange(bits(56) ipa, S2TTWParams walkparams)</line>
<line>    //Input Address size</line>
<line>    iasize = <a link="AArch64.IASize.1" file="shared_pseudocode.xml" hover="function: integer AArch64.IASize(bits(6) txsz)">AArch64.IASize</a>(walkparams.txsz);</line>
<line></line>
<line>    if iasize &lt; 56 then</line>
<line>        return !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(ipa&lt;55:iasize&gt;);</line>
<line>    else</line>
<line>        return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_faults/AArch64.OAOutOfRange" mylink="aarch64.translation.vmsa_faults.AArch64.OAOutOfRange" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.OAOutOfRange()</line>
<line>// ======================</line>
<line>// Returns whether output address is expressed in the configured size number of bits</line>
<line></line>
<line link="AArch64.OAOutOfRange.5" hover="function: boolean AArch64.OAOutOfRange(TTWState walkstate, bit d128, bits(3) ps, TGx tgx, bits(64) ia)" conts="AArch64.OAOutOfRange">boolean <anchor link="AArch64.OAOutOfRange.5" hover="function: boolean AArch64.OAOutOfRange(TTWState walkstate, bit d128, bits(3) ps, TGx tgx, bits(64) ia)">AArch64.OAOutOfRange</anchor>(<a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> walkstate, bit d128, bits(3) ps,</line>
<line>                             <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tgx, bits(64) ia)</line>
<line>    // Output Address size</line>
<line>    oasize  = <a link="AArch64.PhysicalAddressSize.3" file="shared_pseudocode.xml" hover="function: integer AArch64.PhysicalAddressSize(bit d128, bits(3) encoded_ps, TGx tgx)">AArch64.PhysicalAddressSize</a>(d128, ps, tgx);</line>
<line></line>
<line>    if oasize &lt; 56 then</line>
<line>        if walkstate.istable then</line>
<line>            baseaddress = walkstate.baseaddress.address;</line>
<line>            return !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(baseaddress&lt;55:oasize&gt;);</line>
<line>        else</line>
<line>            // Output address</line>
<line>            oa = <a link="impl-shared.StageOA.4" file="shared_pseudocode.xml" hover="function: FullAddress StageOA(bits(64) ia, bit d128, TGx tgx, TTWState walkstate)">StageOA</a>(ia, d128, tgx, walkstate);</line>
<line>            return !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(oa.address&lt;55:oasize&gt;);</line>
<line>    else</line>
<line>        return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_faults/AArch64.S1CheckPermissions" mylink="aarch64.translation.vmsa_faults.AArch64.S1CheckPermissions" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1CheckPermissions()</line>
<line>// ============================</line>
<line>// Checks whether stage 1 access violates permissions of target memory</line>
<line>// and returns a fault record</line>
<line></line>
<line><a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> AArch64.S1CheckPermissions(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault_in, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> walkstate,</line>
<line>                                       S1TTWParams walkparams, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = fault_in;</line>
<line>    <a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> permissions = walkstate.permissions;</line>
<line>    <a link="S1AccessControls" file="shared_pseudocode.xml" hover="type S1AccessControls is ( bit r, bit w, bit x, bit gcs, boolean overlay, bit or, bit ow, bit ox, bit wxn )">S1AccessControls</a> s1perms;</line>
<line></line>
<line>    s1perms = AArch64.S1ComputePermissions(regime, walkstate, walkparams, accdesc);</line>
<line></line>
<line>    if accdesc.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> then</line>
<line>        if s1perms.overlay &amp;&amp; s1perms.ox == '0' then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>            fault.overlay    = TRUE;</line>
<line>        elsif (walkstate.memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> &amp;&amp;</line>
<line>                <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_INSTRDEVICE" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_INSTRDEVICE</a>) == <a link="Constraint_FAULT" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_FAULT</a>) then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        elsif s1perms.x == '0' then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>    elsif accdesc.acctype == <a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a> then</line>
<line>        if accdesc.cacheop == <a link="CacheOp_Invalidate" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_Invalidate</a> then</line>
<line>            if s1perms.overlay &amp;&amp; s1perms.ow == '0' then</line>
<line>                fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>                fault.overlay    = TRUE;</line>
<line>            elsif s1perms.w == '0' then</line>
<line>                fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        // DC from privileged context which clean cannot generate a Permission fault</line>
<line>        elsif accdesc.el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>            if s1perms.overlay &amp;&amp; s1perms.or == '0' then</line>
<line>                fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>                fault.overlay    = TRUE;</line>
<line>            elsif (walkparams.cmow == '1' &amp;&amp;</line>
<line>                    accdesc.opscope == <a link="CacheOpScope_PoC" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_PoC</a> &amp;&amp;</line>
<line>                    accdesc.cacheop == <a link="CacheOp_CleanInvalidate" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_CleanInvalidate</a> &amp;&amp;</line>
<line>                    s1perms.overlay &amp;&amp; s1perms.ow == '0') then</line>
<line>                fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>                fault.overlay    = TRUE;</line>
<line>            elsif s1perms.r == '0' then</line>
<line>                fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>            elsif (walkparams.cmow == '1' &amp;&amp;</line>
<line>                    accdesc.opscope == <a link="CacheOpScope_PoC" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_PoC</a> &amp;&amp;</line>
<line>                    accdesc.cacheop == <a link="CacheOp_CleanInvalidate" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_CleanInvalidate</a> &amp;&amp;</line>
<line>                    s1perms.w == '0') then</line>
<line>                fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>    elsif accdesc.acctype == <a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a> then</line>
<line>        // IC from privileged context cannot generate Permission fault</line>
<line>        if accdesc.el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>            if (s1perms.overlay &amp;&amp; s1perms.or == '0' &amp;&amp;</line>
<line>                  boolean IMPLEMENTATION_DEFINED "Permission fault on <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> IC_IVAU execution") then</line>
<line>                fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>                fault.overlay    = TRUE;</line>
<line>            elsif walkparams.cmow == '1' &amp;&amp; s1perms.overlay &amp;&amp; s1perms.ow == '0' then</line>
<line>                fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>                fault.overlay    = TRUE;</line>
<line>            elsif (s1perms.r == '0' &amp;&amp;</line>
<line>                  boolean IMPLEMENTATION_DEFINED "Permission fault on <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> IC_IVAU execution") then</line>
<line>                fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>            elsif walkparams.cmow == '1' &amp;&amp; s1perms.w == '0' then</line>
<line>                fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>    elsif <a link="impl-shared.HaveGCS.0" file="shared_pseudocode.xml" hover="function: boolean HaveGCS()">HaveGCS</a>() &amp;&amp; accdesc.acctype == <a link="AccessType_GCS" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GCS</a> then</line>
<line>        if s1perms.gcs == '0' then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        elsif accdesc.write &amp;&amp; walkparams.&lt;ha,hd&gt; != '11' &amp;&amp; permissions.ndirty == '1' then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>            fault.dirtybit   = TRUE;</line>
<line>            fault.write      = TRUE;</line>
<line>    elsif accdesc.read &amp;&amp; s1perms.overlay &amp;&amp; s1perms.or == '0' then</line>
<line>        fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        fault.overlay    = TRUE;</line>
<line>        fault.write      = FALSE;</line>
<line>    elsif accdesc.write &amp;&amp; s1perms.overlay &amp;&amp; s1perms.ow == '0' then</line>
<line>        fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        fault.overlay    = TRUE;</line>
<line>        fault.write      = TRUE;</line>
<line>    elsif accdesc.read &amp;&amp; s1perms.r == '0' then</line>
<line>        fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        fault.write      = FALSE;</line>
<line>    elsif accdesc.write &amp;&amp; s1perms.w == '0' then</line>
<line>        fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        fault.write      = TRUE;</line>
<line>    elsif (accdesc.write &amp;&amp; accdesc.tagaccess &amp;&amp;</line>
<line>            walkstate.memattrs.tags == <a link="MemTag_CanonicallyTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_CanonicallyTagged</a>) then</line>
<line>        fault.statuscode   = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        fault.write        = TRUE;</line>
<line>        fault.s1tagnotdata = TRUE;</line>
<line>    elsif (accdesc.write &amp;&amp; !(walkparams.&lt;ha,hd&gt; == '11') &amp;&amp; walkparams.pie == '1' &amp;&amp;</line>
<line>            permissions.ndirty == '1') then</line>
<line>        fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        fault.dirtybit   = TRUE;</line>
<line>        fault.write      = TRUE;</line>
<line></line>
<line>    return fault;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_faults/AArch64.S1ComputePermissions" mylink="aarch64.translation.vmsa_faults.AArch64.S1ComputePermissions" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1ComputePermissions()</line>
<line>// ==============================</line>
<line>// Computes the overall stage 1 permissions</line>
<line></line>
<line><a link="S1AccessControls" file="shared_pseudocode.xml" hover="type S1AccessControls is ( bit r, bit w, bit x, bit gcs, boolean overlay, bit or, bit ow, bit ox, bit wxn )">S1AccessControls</a> AArch64.S1ComputePermissions(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> walkstate,</line>
<line>                                              S1TTWParams walkparams, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    <a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> permissions = walkstate.permissions;</line>
<line>    <a link="S1AccessControls" file="shared_pseudocode.xml" hover="type S1AccessControls is ( bit r, bit w, bit x, bit gcs, boolean overlay, bit or, bit ow, bit ox, bit wxn )">S1AccessControls</a> s1perms;</line>
<line></line>
<line>    if walkparams.pie == '1' then</line>
<line>        s1perms = AArch64.S1IndirectBasePermissions(regime, walkstate, walkparams, accdesc);</line>
<line>    else</line>
<line>        s1perms = AArch64.S1DirectBasePermissions(regime, walkstate, walkparams, accdesc);</line>
<line></line>
<line>    if accdesc.el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="AArch64.S1E0POEnabled.2" file="shared_pseudocode.xml" hover="function: boolean AArch64.S1E0POEnabled(Regime regime, bit nv1)">AArch64.S1E0POEnabled</a>(regime, walkparams.nv1) then</line>
<line>        s1perms.overlay = FALSE;</line>
<line>    elsif accdesc.el != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="AArch64.S1POEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.S1POEnabled(Regime regime)">AArch64.S1POEnabled</a>(regime) then</line>
<line>        s1perms.overlay = FALSE;</line>
<line></line>
<line>    if s1perms.overlay then</line>
<line>        s1overlay_perms = <a link="AArch64.S1OverlayPermissions.3" file="shared_pseudocode.xml" hover="function: S1AccessControls AArch64.S1OverlayPermissions(Regime regime, TTWState walkstate, AccessDescriptor accdesc)">AArch64.S1OverlayPermissions</a>(regime, walkstate, accdesc);</line>
<line>        s1perms.or = s1overlay_perms.or;</line>
<line>        s1perms.ow = s1overlay_perms.ow;</line>
<line>        s1perms.ox = s1overlay_perms.ox;</line>
<line></line>
<line>    // If wxn is set, overlay execute permissions is set to 0</line>
<line>    if s1perms.overlay &amp;&amp; s1perms.wxn == '1' &amp;&amp; s1perms.ox == '1' then</line>
<line>        s1perms.ow = '0';</line>
<line>    elsif s1perms.wxn == '1' then</line>
<line>        s1perms.x = '0';</line>
<line></line>
<line>    return s1perms;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_faults/AArch64.S1DirectBasePermissions" mylink="aarch64.translation.vmsa_faults.AArch64.S1DirectBasePermissions" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1DirectBasePermissions()</line>
<line>// =================================</line>
<line>// Computes the stage 1 direct base permissions</line>
<line></line>
<line><a link="S1AccessControls" file="shared_pseudocode.xml" hover="type S1AccessControls is ( bit r, bit w, bit x, bit gcs, boolean overlay, bit or, bit ow, bit ox, bit wxn )">S1AccessControls</a> AArch64.S1DirectBasePermissions(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> walkstate,</line>
<line>                                                 S1TTWParams walkparams, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    bit  r,  w,  x;</line>
<line>    bit pr, pw, px;</line>
<line>    bit ur, uw, ux;</line>
<line>    <a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> permissions = walkstate.permissions;</line>
<line>    <a link="S1AccessControls" file="shared_pseudocode.xml" hover="type S1AccessControls is ( bit r, bit w, bit x, bit gcs, boolean overlay, bit or, bit ow, bit ox, bit wxn )">S1AccessControls</a> s1perms;</line>
<line></line>
<line>    if <a link="impl-shared.HasUnprivileged.1" file="shared_pseudocode.xml" hover="function: boolean HasUnprivileged(Regime regime)">HasUnprivileged</a>(regime) then</line>
<line>        // Apply leaf permissions</line>
<line>        case permissions.ap&lt;2:1&gt; of</line>
<line>            when '00' (pr,pw,ur,uw) = ('1','1','0','0'); // Privileged access</line>
<line>            when '01' (pr,pw,ur,uw) = ('1','1','1','1'); // No effect</line>
<line>            when '10' (pr,pw,ur,uw) = ('1','0','0','0'); // Read-only, privileged access</line>
<line>            when '11' (pr,pw,ur,uw) = ('1','0','1','0'); // Read-only</line>
<line></line>
<line>        // Apply hierarchical permissions</line>
<line>        case permissions.ap_table of</line>
<line>            when '00' (pr,pw,ur,uw) = ( pr, pw, ur, uw); // No effect</line>
<line>            when '01' (pr,pw,ur,uw) = ( pr, pw,'0','0'); // Privileged access</line>
<line>            when '10' (pr,pw,ur,uw) = ( pr,'0', ur,'0'); // Read-only</line>
<line>            when '11' (pr,pw,ur,uw) = ( pr,'0','0','0'); // Read-only, privileged access</line>
<line></line>
<line>        // Locations writable by unprivileged cannot be executed by privileged</line>
<line>        px = NOT(permissions.pxn OR permissions.pxn_table OR uw);</line>
<line>        ux = NOT(permissions.uxn OR permissions.uxn_table);</line>
<line></line>
<line>        if <a link="impl-shared.HavePANExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePANExt()">HavePANExt</a>() &amp;&amp; accdesc.pan &amp;&amp; !(regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; walkparams.nv1 == '1') then</line>
<line>            bit pan;</line>
<line>            if (boolean IMPLEMENTATION_DEFINED "SCR_EL3.SIF affects EPAN" &amp;&amp;</line>
<line>                    accdesc.ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> &amp;&amp;</line>
<line>                    walkstate.baseaddress.paspace == <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a> &amp;&amp;</line>
<line>                    walkparams.sif == '1') then</line>
<line>                ux = '0';</line>
<line></line>
<line>            if (boolean IMPLEMENTATION_DEFINED "Realm <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>&amp;0 regime affects EPAN" &amp;&amp;</line>
<line>                    accdesc.ss == <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a> &amp;&amp; regime == <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a> &amp;&amp;</line>
<line>                    walkstate.baseaddress.paspace != <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a>) then</line>
<line>                ux = '0';</line>
<line></line>
<line>            pan = PSTATE.PAN AND (ur OR uw OR (walkparams.epan AND ux));</line>
<line>            pr = pr AND NOT(pan);</line>
<line>            pw = pw AND NOT(pan);</line>
<line></line>
<line>    else</line>
<line>        // Apply leaf permissions</line>
<line>        case permissions.ap&lt;2&gt; of</line>
<line>            when '0' (pr,pw) = ('1','1'); // No effect</line>
<line>            when '1' (pr,pw) = ('1','0'); // Read-only</line>
<line></line>
<line>        // Apply hierarchical permissions</line>
<line>        case permissions.ap_table&lt;1&gt; of</line>
<line>            when '0' (pr,pw) = ( pr, pw); // No effect</line>
<line>            when '1' (pr,pw) = ( pr,'0'); // Read-only</line>
<line></line>
<line>        px = NOT(permissions.xn OR permissions.xn_table);</line>
<line></line>
<line>    (r,w,x) = if accdesc.el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then (ur,uw,ux) else (pr,pw,px);</line>
<line></line>
<line>    // Compute WXN value</line>
<line>    wxn = walkparams.wxn AND w AND x;</line>
<line></line>
<line>    // Prevent execution from Non-secure space by PE in secure state if SIF is set</line>
<line>    if accdesc.ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> &amp;&amp; walkstate.baseaddress.paspace == <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a> then</line>
<line>        x = x AND NOT(walkparams.sif);</line>
<line>    // Prevent execution from non-Root space by Root</line>
<line>    if accdesc.ss == <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a> &amp;&amp; walkstate.baseaddress.paspace != <a link="PAS_Root" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Root</a> then</line>
<line>        x = '0';</line>
<line>    // Prevent execution from non-Realm space by Realm EL2 and Realm EL2&amp;0</line>
<line>    if (accdesc.ss == <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a> &amp;&amp; regime IN {<a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>, <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a>} &amp;&amp;</line>
<line>            walkstate.baseaddress.paspace != <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a>) then</line>
<line>        x = '0';</line>
<line></line>
<line>    s1perms.r   = r;</line>
<line>    s1perms.w   = w;</line>
<line>    s1perms.x   = x;</line>
<line>    s1perms.gcs = '0';</line>
<line>    s1perms.wxn = wxn;</line>
<line>    s1perms.overlay = TRUE;</line>
<line></line>
<line>    return s1perms;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_faults/AArch64.S1HasAlignmentFault" mylink="aarch64.translation.vmsa_faults.AArch64.S1HasAlignmentFault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1HasAlignmentFault()</line>
<line>// =============================</line>
<line>// Returns whether stage 1 output fails alignment requirement on data accesses</line>
<line>// to Device memory</line>
<line></line>
<line link="AArch64.S1HasAlignmentFault.4" hover="function: boolean AArch64.S1HasAlignmentFault(AccessDescriptor accdesc, boolean aligned, bit ntlsmd, MemoryAttributes memattrs)" conts="AArch64.S1HasAlignmentFault">boolean <anchor link="AArch64.S1HasAlignmentFault.4" hover="function: boolean AArch64.S1HasAlignmentFault(AccessDescriptor accdesc, boolean aligned, bit ntlsmd, MemoryAttributes memattrs)">AArch64.S1HasAlignmentFault</anchor>(<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, boolean aligned,</line>
<line>                                    bit ntlsmd, <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs)</line>
<line>    if accdesc.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> then</line>
<line>        return FALSE;</line>
<line>    elsif <a link="impl-shared.HaveMTEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEExt()">HaveMTEExt</a>() &amp;&amp; accdesc.tagaccess &amp;&amp; accdesc.write then</line>
<line>        return (memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> &amp;&amp;</line>
<line>                <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_DEVICETAGSTORE" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_DEVICETAGSTORE</a>) == <a link="Constraint_FAULT" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_FAULT</a>);</line>
<line>    elsif accdesc.a32lsmd &amp;&amp; ntlsmd == '0' then</line>
<line>        return memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> &amp;&amp;  memattrs.device != <a link="DeviceType_GRE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_GRE</a>;</line>
<line>    elsif accdesc.acctype == <a link="AccessType_DCZero" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DCZero</a> then</line>
<line>        return memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a>;</line>
<line>    else</line>
<line>        return memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> &amp;&amp; !aligned;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_faults/AArch64.S1IndirectBasePermissions" mylink="aarch64.translation.vmsa_faults.AArch64.S1IndirectBasePermissions" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1IndirectBasePermissions()</line>
<line>// ===================================</line>
<line>// Computes the stage 1 indirect base permissions</line>
<line></line>
<line><a link="S1AccessControls" file="shared_pseudocode.xml" hover="type S1AccessControls is ( bit r, bit w, bit x, bit gcs, boolean overlay, bit or, bit ow, bit ox, bit wxn )">S1AccessControls</a> AArch64.S1IndirectBasePermissions(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> walkstate,</line>
<line>                                                   S1TTWParams walkparams,</line>
<line>                                                   <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line></line>
<line>    bit  r,  w,  x,  gcs,  wxn,   overlay;</line>
<line>    bit pr, pw, px, pgcs, pwxn, p_overlay;</line>
<line>    bit ur, uw, ux, ugcs, uwxn, u_overlay;</line>
<line>    <a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> permissions = walkstate.permissions;</line>
<line>    <a link="S1AccessControls" file="shared_pseudocode.xml" hover="type S1AccessControls is ( bit r, bit w, bit x, bit gcs, boolean overlay, bit or, bit ow, bit ox, bit wxn )">S1AccessControls</a> s1perms;</line>
<line></line>
<line>    // Apply privileged indirect permissions</line>
<line>    case permissions.ppi of</line>
<line>        when '0000' (pr,pw,px,pgcs) = ('0','0','0','0'); // No access</line>
<line>        when '0001' (pr,pw,px,pgcs) = ('1','0','0','0'); // Privileged read</line>
<line>        when '0010' (pr,pw,px,pgcs) = ('0','0','1','0'); // Privileged execute</line>
<line>        when '0011' (pr,pw,px,pgcs) = ('1','0','1','0'); // Privileged read and execute</line>
<line>        when '0100' (pr,pw,px,pgcs) = ('0','0','0','0'); // Reserved</line>
<line>        when '0101' (pr,pw,px,pgcs) = ('1','1','0','0'); // Privileged read and write</line>
<line>        when '0110' (pr,pw,px,pgcs) = ('1','1','1','0'); // Privileged read, write and execute</line>
<line>        when '0111' (pr,pw,px,pgcs) = ('1','1','1','0'); // Privileged read, write and execute</line>
<line>        when '1000' (pr,pw,px,pgcs) = ('1','0','0','0'); // Privileged read</line>
<line>        when '1001' (pr,pw,px,pgcs) = ('1','0','0','1'); // Privileged read and gcs</line>
<line>        when '1010' (pr,pw,px,pgcs) = ('1','0','1','0'); // Privileged read and execute</line>
<line>        when '1011' (pr,pw,px,pgcs) = ('0','0','0','0'); // Reserved</line>
<line>        when '1100' (pr,pw,px,pgcs) = ('1','1','0','0'); // Privileged read and write</line>
<line>        when '1101' (pr,pw,px,pgcs) = ('0','0','0','0'); // Reserved</line>
<line>        when '1110' (pr,pw,px,pgcs) = ('1','1','1','0'); // Privileged read, write and execute</line>
<line>        when '1111' (pr,pw,px,pgcs) = ('0','0','0','0'); // Reserved</line>
<line></line>
<line>    p_overlay = NOT(permissions.ppi[3]);</line>
<line>    pwxn = if permissions.ppi == '0110' then '1' else '0';</line>
<line></line>
<line>    if <a link="impl-shared.HasUnprivileged.1" file="shared_pseudocode.xml" hover="function: boolean HasUnprivileged(Regime regime)">HasUnprivileged</a>(regime) then</line>
<line>        // Apply unprivileged indirect permissions</line>
<line>        case permissions.upi of</line>
<line>            when '0000' (ur,uw,ux,ugcs) = ('0','0','0','0'); // No access</line>
<line>            when '0001' (ur,uw,ux,ugcs) = ('1','0','0','0'); // Unprivileged read</line>
<line>            when '0010' (ur,uw,ux,ugcs) = ('0','0','1','0'); // Unprivileged execute</line>
<line>            when '0011' (ur,uw,ux,ugcs) = ('1','0','1','0'); // Unprivileged read and execute</line>
<line>            when '0100' (ur,uw,ux,ugcs) = ('0','0','0','0'); // Reserved</line>
<line>            when '0101' (ur,uw,ux,ugcs) = ('1','1','0','0'); // Unprivileged read and write</line>
<line>            when '0110' (ur,uw,ux,ugcs) = ('1','1','1','0'); // Unprivileged read, write and execute</line>
<line>            when '0111' (ur,uw,ux,ugcs) = ('1','1','1','0'); // Unprivileged read, write and execute</line>
<line>            when '1000' (ur,uw,ux,ugcs) = ('1','0','0','0'); // Unprivileged read</line>
<line>            when '1001' (ur,uw,ux,ugcs) = ('1','0','0','1'); // Unprivileged read and gcs</line>
<line>            when '1010' (ur,uw,ux,ugcs) = ('1','0','1','0'); // Unprivileged read and execute</line>
<line>            when '1011' (ur,uw,ux,ugcs) = ('0','0','0','0'); // Reserved</line>
<line>            when '1100' (ur,uw,ux,ugcs) = ('1','1','0','0'); // Unprivileged read and write</line>
<line>            when '1101' (ur,uw,ux,ugcs) = ('0','0','0','0'); // Reserved</line>
<line>            when '1110' (ur,uw,ux,ugcs) = ('1','1','1','0'); // Unprivileged read,write and execute</line>
<line>            when '1111' (ur,uw,ux,ugcs) = ('0','0','0','0'); // Reserved</line>
<line></line>
<line>        u_overlay = NOT(permissions.upi[3]);</line>
<line>        uwxn = if permissions.upi == '0110' then '1' else '0';</line>
<line></line>
<line>        // If the decoded permissions has either px or pgcs along with either uw or ugcs,</line>
<line>        // then all effective Stage 1 Base Permissions are set to 0</line>
<line>        if ((px == '1' || pgcs == '1') &amp;&amp; (uw == '1' || ugcs == '1')) then</line>
<line>            (pr,pw,px,pgcs) = ('0','0','0','0');</line>
<line>            (ur,uw,ux,ugcs) = ('0','0','0','0');</line>
<line></line>
<line>        if <a link="impl-shared.HavePANExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePANExt()">HavePANExt</a>() &amp;&amp; accdesc.pan &amp;&amp; !(regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; walkparams.nv1 == '1') then</line>
<line>            if PSTATE.PAN == '1' &amp;&amp; (permissions.upi != '0000') then</line>
<line>                (pr,pw) = ('0','0');</line>
<line></line>
<line>    if accdesc.el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        (r,w,x,gcs,wxn,overlay) = (ur,uw,ux,ugcs,uwxn,u_overlay);</line>
<line>    else</line>
<line>        (r,w,x,gcs,wxn,overlay) = (pr,pw,px,pgcs,pwxn,p_overlay);</line>
<line></line>
<line>    // Prevent execution from Non-secure space by PE in secure state if SIF is set</line>
<line>    if accdesc.ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> &amp;&amp; walkstate.baseaddress.paspace == <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a> then</line>
<line>        x = x AND NOT(walkparams.sif);</line>
<line>        gcs = '0';</line>
<line>    // Prevent execution from non-Root space by Root</line>
<line>    if accdesc.ss == <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a> &amp;&amp; walkstate.baseaddress.paspace != <a link="PAS_Root" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Root</a> then</line>
<line>        x = '0';</line>
<line>        gcs = '0';</line>
<line>    // Prevent execution from non-Realm space by Realm EL2 and Realm EL2&amp;0</line>
<line>    if (accdesc.ss == <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a> &amp;&amp; regime IN {<a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>, <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a>} &amp;&amp;</line>
<line>        walkstate.baseaddress.paspace != <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a>) then</line>
<line>        x = '0';</line>
<line>        gcs = '0';</line>
<line></line>
<line>    s1perms.r       = r;</line>
<line>    s1perms.w       = w;</line>
<line>    s1perms.x       = x;</line>
<line>    s1perms.gcs     = gcs;</line>
<line>    s1perms.wxn     = wxn;</line>
<line>    s1perms.overlay = overlay == '1';</line>
<line></line>
<line>    return s1perms;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_faults/AArch64.S1OverlayPermissions" mylink="aarch64.translation.vmsa_faults.AArch64.S1OverlayPermissions" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1OverlayPermissions()</line>
<line>// ==============================</line>
<line>// Computes the stage 1 overlay permissions</line>
<line></line>
<line link="AArch64.S1OverlayPermissions.3" hover="function: S1AccessControls AArch64.S1OverlayPermissions(Regime regime, TTWState walkstate, AccessDescriptor accdesc)" conts="AArch64.S1OverlayPermissions">S1AccessControls <anchor link="AArch64.S1OverlayPermissions.3" hover="function: S1AccessControls AArch64.S1OverlayPermissions(Regime regime, TTWState walkstate, AccessDescriptor accdesc)">AArch64.S1OverlayPermissions</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> walkstate,</line>
<line>                                              <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line></line>
<line>    bit  r,  w,  x;</line>
<line>    bit pr, pw, px;</line>
<line>    bit ur, uw, ux;</line>
<line>    <a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> permissions = walkstate.permissions;</line>
<line>    <a link="S1AccessControls" file="shared_pseudocode.xml" hover="type S1AccessControls is ( bit r, bit w, bit x, bit gcs, boolean overlay, bit or, bit ow, bit ox, bit wxn )">S1AccessControls</a> s1overlay_perms;</line>
<line></line>
<line>    S1PORType por = AArch64.S1POR(regime);</line>
<line>    integer bit_index = 4 * <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(permissions.po_index);</line>
<line>    bits(4) ppo = por&lt;bit_index+3:bit_index&gt;;</line>
<line></line>
<line>    // Apply privileged overlay permissions</line>
<line>    case ppo of</line>
<line>        when '0000' (pr,pw,px) = ('0','0','0'); // No access</line>
<line>        when '0001' (pr,pw,px) = ('1','0','0'); // Privileged read</line>
<line>        when '0010' (pr,pw,px) = ('0','0','1'); // Privileged execute</line>
<line>        when '0011' (pr,pw,px) = ('1','0','1'); // Privileged read and execute</line>
<line>        when '0100' (pr,pw,px) = ('0','1','0'); // Privileged write</line>
<line>        when '0101' (pr,pw,px) = ('1','1','0'); // Privileged read and write</line>
<line>        when '0110' (pr,pw,px) = ('0','1','1'); // Privileged write and execute</line>
<line>        when '0111' (pr,pw,px) = ('1','1','1'); // Privileged read, write and execute</line>
<line>        when '1xxx' (pr,pw,px) = ('0','0','0'); // Reserved</line>
<line></line>
<line>    if <a link="impl-shared.HasUnprivileged.1" file="shared_pseudocode.xml" hover="function: boolean HasUnprivileged(Regime regime)">HasUnprivileged</a>(regime) then</line>
<line>        bits(4) upo = POR_EL0&lt;bit_index+3:bit_index&gt;;</line>
<line></line>
<line>        // Apply unprivileged overlay permissions</line>
<line>        case upo of</line>
<line>            when '0000' (ur,uw,ux) = ('0','0','0'); // No access</line>
<line>            when '0001' (ur,uw,ux) = ('1','0','0'); // Unprivileged read</line>
<line>            when '0010' (ur,uw,ux) = ('0','0','1'); // Unprivileged execute</line>
<line>            when '0011' (ur,uw,ux) = ('1','0','1'); // Unprivileged read and execute</line>
<line>            when '0100' (ur,uw,ux) = ('0','1','0'); // Unprivileged write</line>
<line>            when '0101' (ur,uw,ux) = ('1','1','0'); // Unprivileged read and write</line>
<line>            when '0110' (ur,uw,ux) = ('0','1','1'); // Unprivileged write and execute</line>
<line>            when '0111' (ur,uw,ux) = ('1','1','1'); // Unprivileged read, write and execute</line>
<line>            when '1xxx' (ur,uw,ux) = ('0','0','0'); // Reserved</line>
<line></line>
<line>    (r,w,x) = if accdesc.el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then (ur,uw,ux) else (pr,pw,px);</line>
<line></line>
<line>    s1overlay_perms.or = r;</line>
<line>    s1overlay_perms.ow = w;</line>
<line>    s1overlay_perms.ox = x;</line>
<line></line>
<line>    return s1overlay_perms;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_faults/AArch64.S1TxSZFaults" mylink="aarch64.translation.vmsa_faults.AArch64.S1TxSZFaults" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1TxSZFaults()</line>
<line>// ======================</line>
<line>// Detect whether configuration of stage 1 TxSZ field generates a fault</line>
<line></line>
<line>boolean AArch64.S1TxSZFaults(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, S1TTWParams walkparams)</line>
<line>    mintxsz = <a link="AArch64.S1MinTxSZ.4" file="shared_pseudocode.xml" hover="function: integer AArch64.S1MinTxSZ(Regime regime, bit d128, bit ds, TGx tgx)">AArch64.S1MinTxSZ</a>(regime, walkparams.d128, walkparams.ds, walkparams.tgx);</line>
<line>    maxtxsz = <a link="AArch64.MaxTxSZ.1" file="shared_pseudocode.xml" hover="function: integer AArch64.MaxTxSZ(TGx tgx)">AArch64.MaxTxSZ</a>(walkparams.tgx);</line>
<line></line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(walkparams.txsz) &lt; mintxsz then</line>
<line>        return (<a link="impl-shared.Have52BitVAExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitVAExt()">Have52BitVAExt</a>() ||</line>
<line>                boolean IMPLEMENTATION_DEFINED "<a link="Fault" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault</a> on TxSZ value below minimum");</line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(walkparams.txsz) &gt; maxtxsz then</line>
<line>        return boolean IMPLEMENTATION_DEFINED "<a link="Fault" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault</a> on TxSZ value above maximum";</line>
<line></line>
<line>    return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_faults/AArch64.S2CheckPermissions" mylink="aarch64.translation.vmsa_faults.AArch64.S2CheckPermissions" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S2CheckPermissions()</line>
<line>// ============================</line>
<line>// Verifies memory access with available permissions.</line>
<line></line>
<line>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a>, boolean) AArch64.S2CheckPermissions(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault_in, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> walkstate,</line>
<line>                                                  S2TTWParams walkparams, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> ipa,</line>
<line>                                                  <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    <a link="MemType" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType</a> memtype = walkstate.memattrs.memtype;</line>
<line>    <a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> permissions = walkstate.permissions;</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = fault_in;</line>
<line>    <a link="S2AccessControls" file="shared_pseudocode.xml" hover="type S2AccessControls is ( bit r, bit w, bit x, bit r_rcw, bit w_rcw, bit r_mmu, bit w_mmu, bit toplevel0, bit toplevel1, boolean overlay, bit or, bit ow, bit ox, bit or_rcw, bit ow_rcw, bit or_mmu, bit ow_mmu, )">S2AccessControls</a> s2perms = AArch64.S2ComputePermissions(permissions, walkparams, accdesc);</line>
<line></line>
<line>    bit  r,  w;</line>
<line>    bit or, ow;</line>
<line></line>
<line>    if accdesc.acctype == <a link="AccessType_TTW" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_TTW</a> then</line>
<line>        r = s2perms.r_mmu;</line>
<line>        w = s2perms.w_mmu;</line>
<line>        or = s2perms.or_mmu;</line>
<line>        ow = s2perms.ow_mmu;</line>
<line>    elsif accdesc.rcw then</line>
<line>        r = s2perms.r_rcw;</line>
<line>        w = s2perms.w_rcw;</line>
<line>        or = s2perms.or_rcw;</line>
<line>        ow = s2perms.ow_rcw;</line>
<line>    else</line>
<line>        r = s2perms.r;</line>
<line>        w = s2perms.w;</line>
<line>        or = s2perms.or;</line>
<line>        ow = s2perms.ow;</line>
<line></line>
<line>    if accdesc.acctype == <a link="AccessType_TTW" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_TTW</a> then</line>
<line>        if (accdesc.toplevel &amp;&amp; accdesc.varange == <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a> &amp;&amp;</line>
<line>               ((walkparams.tl0 == '1' &amp;&amp; s2perms.toplevel0 == '0') ||</line>
<line>               (walkparams.tl1 == '1' &amp;&amp; s2perms.&lt;toplevel1,toplevel0&gt; == '10'))) then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>            fault.toplevel   = TRUE;</line>
<line>        elsif (accdesc.toplevel &amp;&amp; accdesc.varange == <a link="VARange_UPPER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_UPPER</a> &amp;&amp;</line>
<line>               ((walkparams.tl1 == '1' &amp;&amp; s2perms.toplevel1 == '0') ||</line>
<line>               (walkparams.tl0 == '1' &amp;&amp; s2perms.&lt;toplevel1,toplevel0&gt; == '01'))) then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>            fault.toplevel   = TRUE;</line>
<line>        elsif walkparams.ptw == '1' &amp;&amp; memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        elsif s2perms.overlay &amp;&amp; or == '0' then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>            fault.overlay    = TRUE;</line>
<line>        elsif accdesc.write &amp;&amp; s2perms.overlay &amp;&amp; ow == '0' then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>            fault.overlay    = TRUE;</line>
<line>        // Prevent translation table walks in Non-secure space by Realm state</line>
<line>        elsif accdesc.ss == <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a> &amp;&amp; walkstate.baseaddress.paspace != <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a> then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        elsif r == '0' then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        elsif accdesc.write &amp;&amp; w == '0' then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        elsif (accdesc.write &amp;&amp; !(walkparams.&lt;ha,hd&gt; == '11') &amp;&amp; walkparams.s2pie == '1' &amp;&amp;</line>
<line>                permissions.s2dirty == '0') then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>            fault.dirtybit   = TRUE;</line>
<line>            fault.write      = TRUE;</line>
<line>    // Stage 2 Permission fault due to AssuredOnly check</line>
<line>    elsif ((walkstate.s2assuredonly == '1' &amp;&amp; !ipa.s1assured) ||</line>
<line>           (walkstate.s2assuredonly != '1' &amp;&amp; <a link="impl-shared.HaveGCS.0" file="shared_pseudocode.xml" hover="function: boolean HaveGCS()">HaveGCS</a>() &amp;&amp; VTCR_EL2.GCSH == '1' &amp;&amp;</line>
<line>            accdesc.acctype == <a link="AccessType_GCS" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GCS</a> &amp;&amp; accdesc.el != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>)) then</line>
<line>        fault.statuscode  = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        fault.assuredonly = TRUE;</line>
<line>    elsif accdesc.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> then</line>
<line>        if s2perms.overlay &amp;&amp; s2perms.ox == '0' then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>            fault.overlay    = TRUE;</line>
<line>        elsif (memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> &amp;&amp;</line>
<line>                <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_INSTRDEVICE" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_INSTRDEVICE</a>) == <a link="Constraint_FAULT" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_FAULT</a>) then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line></line>
<line>        // Prevent execution from Non-secure space by Realm state</line>
<line>        elsif accdesc.ss == <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a> &amp;&amp; walkstate.baseaddress.paspace != <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a> then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        elsif s2perms.x == '0' then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line></line>
<line>    elsif accdesc.acctype == <a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a> then</line>
<line>        if accdesc.cacheop == <a link="CacheOp_Invalidate" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_Invalidate</a> then</line>
<line>            if !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) &amp;&amp; s2perms.overlay &amp;&amp; ow == '0' then</line>
<line>                fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>                fault.overlay    = TRUE;</line>
<line>            if !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) &amp;&amp; w == '0' then</line>
<line>                fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        elsif !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) &amp;&amp; accdesc.el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; s2perms.overlay &amp;&amp; or == '0' then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>            fault.overlay    = TRUE;</line>
<line>        elsif (walkparams.cmow == '1' &amp;&amp;</line>
<line>                accdesc.opscope == <a link="CacheOpScope_PoC" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_PoC</a> &amp;&amp;</line>
<line>                accdesc.cacheop == <a link="CacheOp_CleanInvalidate" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_CleanInvalidate</a> &amp;&amp;</line>
<line>                s2perms.overlay &amp;&amp; ow == '0') then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>            fault.overlay    = TRUE;</line>
<line>        elsif !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) &amp;&amp; accdesc.el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; r == '0' then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        elsif (walkparams.cmow == '1' &amp;&amp;</line>
<line>                accdesc.opscope == <a link="CacheOpScope_PoC" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_PoC</a> &amp;&amp;</line>
<line>                accdesc.cacheop == <a link="CacheOp_CleanInvalidate" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_CleanInvalidate</a> &amp;&amp;</line>
<line>                w == '0') then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line></line>
<line>    elsif accdesc.acctype == <a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a> then</line>
<line>        if (!<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) &amp;&amp; accdesc.el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; s2perms.overlay &amp;&amp; or == '0' &amp;&amp;</line>
<line>                boolean IMPLEMENTATION_DEFINED "Permission fault on <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> IC_IVAU execution") then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>            fault.overlay    = TRUE;</line>
<line>        elsif walkparams.cmow == '1' &amp;&amp; s2perms.overlay &amp;&amp; ow == '0' then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>            fault.overlay    = TRUE;</line>
<line>        elsif (!<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) &amp;&amp; accdesc.el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp;  r == '0' &amp;&amp;</line>
<line>                boolean IMPLEMENTATION_DEFINED "Permission fault on <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> IC_IVAU execution") then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        elsif walkparams.cmow == '1' &amp;&amp; w == '0' then</line>
<line>            fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line></line>
<line>    elsif accdesc.read &amp;&amp; s2perms.overlay &amp;&amp; or == '0' then</line>
<line>        fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        fault.overlay    = TRUE;</line>
<line>        fault.write      = FALSE;</line>
<line>    elsif accdesc.write &amp;&amp; s2perms.overlay &amp;&amp; ow == '0' then</line>
<line>        fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        fault.overlay    = TRUE;</line>
<line>        fault.write      = TRUE;</line>
<line>    elsif accdesc.read &amp;&amp; r == '0' then</line>
<line>        fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        fault.write      = FALSE;</line>
<line>    elsif accdesc.write &amp;&amp; w == '0' then</line>
<line>        fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        fault.write      = TRUE;</line>
<line>    elsif ((accdesc.tagaccess || accdesc.tagchecked) &amp;&amp;</line>
<line>            ipa.memattrs.tags == <a link="MemTag_AllocationTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_AllocationTagged</a> &amp;&amp;</line>
<line>            permissions.s2tag_na == '1') then</line>
<line>        fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        fault.tagaccess  = TRUE;</line>
<line>        fault.write      = accdesc.tagaccess &amp;&amp; accdesc.write;</line>
<line>    elsif (accdesc.write &amp;&amp; !(walkparams.&lt;ha,hd&gt; == '11') &amp;&amp; walkparams.s2pie == '1' &amp;&amp;</line>
<line>            permissions.s2dirty == '0') then</line>
<line>        fault.statuscode = <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>;</line>
<line>        fault.dirtybit   = TRUE;</line>
<line>        fault.write      = TRUE;</line>
<line></line>
<line>    // MRO* allows only RCW and MMU writes</line>
<line>    boolean mro;</line>
<line>    if s2perms.overlay then</line>
<line>        mro = (s2perms.&lt;w,w_rcw,w_mmu&gt; AND s2perms.&lt;ow,ow_rcw,ow_mmu&gt;) == '011';</line>
<line>    else</line>
<line>        mro = s2perms.&lt;w,w_rcw,w_mmu&gt; == '011';</line>
<line></line>
<line>    return (fault, mro);</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_faults/AArch64.S2ComputePermissions" mylink="aarch64.translation.vmsa_faults.AArch64.S2ComputePermissions" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S2ComputePermissions()</line>
<line>// ==============================</line>
<line>// Compute the overall stage 2 permissions.</line>
<line></line>
<line><a link="S2AccessControls" file="shared_pseudocode.xml" hover="type S2AccessControls is ( bit r, bit w, bit x, bit r_rcw, bit w_rcw, bit r_mmu, bit w_mmu, bit toplevel0, bit toplevel1, boolean overlay, bit or, bit ow, bit ox, bit or_rcw, bit ow_rcw, bit or_mmu, bit ow_mmu, )">S2AccessControls</a> AArch64.S2ComputePermissions(<a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> permissions, S2TTWParams walkparams,</line>
<line>                                              <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line></line>
<line>    <a link="S2AccessControls" file="shared_pseudocode.xml" hover="type S2AccessControls is ( bit r, bit w, bit x, bit r_rcw, bit w_rcw, bit r_mmu, bit w_mmu, bit toplevel0, bit toplevel1, boolean overlay, bit or, bit ow, bit ox, bit or_rcw, bit ow_rcw, bit or_mmu, bit ow_mmu, )">S2AccessControls</a> s2perms;</line>
<line></line>
<line>    if walkparams.s2pie == '1' then</line>
<line>        s2perms = <a link="AArch64.S2IndirectBasePermissions.2" file="shared_pseudocode.xml" hover="function: S2AccessControls AArch64.S2IndirectBasePermissions(Permissions permissions, AccessDescriptor accdesc)">AArch64.S2IndirectBasePermissions</a>(permissions, accdesc);</line>
<line>        s2perms.overlay = <a link="impl-shared.HaveS2POExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveS2POExt()">HaveS2POExt</a>() &amp;&amp; VTCR_EL2.S2POE == '1';</line>
<line>        if s2perms.overlay then</line>
<line>            s2overlay_perms = <a link="AArch64.S2OverlayPermissions.2" file="shared_pseudocode.xml" hover="function: S2AccessControls AArch64.S2OverlayPermissions(Permissions permissions, AccessDescriptor accdesc)">AArch64.S2OverlayPermissions</a>(permissions, accdesc);</line>
<line>            s2perms.or          = s2overlay_perms.or;</line>
<line>            s2perms.ow          = s2overlay_perms.ow;</line>
<line>            s2perms.ox          = s2overlay_perms.ox;</line>
<line>            s2perms.or_rcw      = s2overlay_perms.or_rcw;</line>
<line>            s2perms.ow_rcw      = s2overlay_perms.ow_rcw;</line>
<line>            s2perms.or_mmu      = s2overlay_perms.or_mmu;</line>
<line>            s2perms.ow_mmu      = s2overlay_perms.ow_mmu;</line>
<line></line>
<line>            s2perms.toplevel0   = s2perms.toplevel0 OR s2overlay_perms.toplevel0;</line>
<line>            s2perms.toplevel1   = s2perms.toplevel1 OR s2overlay_perms.toplevel1;</line>
<line>    else</line>
<line>        s2perms = <a link="AArch64.S2DirectBasePermissions.2" file="shared_pseudocode.xml" hover="function: S2AccessControls AArch64.S2DirectBasePermissions(Permissions permissions, AccessDescriptor accdesc)">AArch64.S2DirectBasePermissions</a>(permissions, accdesc);</line>
<line></line>
<line>    return s2perms;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_faults/AArch64.S2DirectBasePermissions" mylink="aarch64.translation.vmsa_faults.AArch64.S2DirectBasePermissions" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S2DirectBasePermissions()</line>
<line>// =================================</line>
<line>// Computes the stage 2 direct base permissions.</line>
<line></line>
<line link="AArch64.S2DirectBasePermissions.2" hover="function: S2AccessControls AArch64.S2DirectBasePermissions(Permissions permissions, AccessDescriptor accdesc)" conts="AArch64.S2DirectBasePermissions">S2AccessControls <anchor link="AArch64.S2DirectBasePermissions.2" hover="function: S2AccessControls AArch64.S2DirectBasePermissions(Permissions permissions, AccessDescriptor accdesc)">AArch64.S2DirectBasePermissions</anchor>(<a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> permissions,</line>
<line>                                                 <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    <a link="S2AccessControls" file="shared_pseudocode.xml" hover="type S2AccessControls is ( bit r, bit w, bit x, bit r_rcw, bit w_rcw, bit r_mmu, bit w_mmu, bit toplevel0, bit toplevel1, boolean overlay, bit or, bit ow, bit ox, bit or_rcw, bit ow_rcw, bit or_mmu, bit ow_mmu, )">S2AccessControls</a> s2perms;</line>
<line>    r = permissions.s2ap&lt;0&gt;;</line>
<line>    w = permissions.s2ap&lt;1&gt;;</line>
<line>    bit px, ux;</line>
<line>    case (permissions.s2xn:permissions.s2xnx) of</line>
<line>        when '00' (px,ux) = ('1','1');</line>
<line>        when '01' (px,ux) = ('0','1');</line>
<line>        when '10' (px,ux) = ('0','0');</line>
<line>        when '11' (px,ux) = ('1','0');</line>
<line></line>
<line>    x = if accdesc.el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then ux else px;</line>
<line>    s2perms.r = r;</line>
<line>    s2perms.w = w;</line>
<line>    s2perms.x = x;</line>
<line>    s2perms.r_rcw = r;</line>
<line>    s2perms.w_rcw = w;</line>
<line>    s2perms.r_mmu = r;</line>
<line>    s2perms.w_mmu = w;</line>
<line></line>
<line>    return s2perms;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_faults/AArch64.S2HasAlignmentFault" mylink="aarch64.translation.vmsa_faults.AArch64.S2HasAlignmentFault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S2HasAlignmentFault()</line>
<line>// =============================</line>
<line>// Returns whether stage 2 output fails alignment requirement on data accesses</line>
<line>// to Device memory</line>
<line></line>
<line link="AArch64.S2HasAlignmentFault.3" hover="function: boolean AArch64.S2HasAlignmentFault(AccessDescriptor accdesc, boolean aligned, MemoryAttributes memattrs)" conts="AArch64.S2HasAlignmentFault">boolean <anchor link="AArch64.S2HasAlignmentFault.3" hover="function: boolean AArch64.S2HasAlignmentFault(AccessDescriptor accdesc, boolean aligned, MemoryAttributes memattrs)">AArch64.S2HasAlignmentFault</anchor>(<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, boolean aligned,</line>
<line>                                    <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs)</line>
<line>    if accdesc.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> then</line>
<line>        return FALSE;</line>
<line>    elsif <a link="impl-shared.HaveMTEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEExt()">HaveMTEExt</a>() &amp;&amp; accdesc.tagaccess &amp;&amp; accdesc.write then</line>
<line>        return (memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> &amp;&amp;</line>
<line>                <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_DEVICETAGSTORE" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_DEVICETAGSTORE</a>) == <a link="Constraint_FAULT" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_FAULT</a>);</line>
<line>    elsif accdesc.acctype == <a link="AccessType_DCZero" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DCZero</a> then</line>
<line>        return memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a>;</line>
<line>    else</line>
<line>        return memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> &amp;&amp; !aligned;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_faults/AArch64.S2InconsistentSL" mylink="aarch64.translation.vmsa_faults.AArch64.S2InconsistentSL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S2InconsistentSL()</line>
<line>// ==========================</line>
<line>// Detect inconsistent configuration of stage 2 TxSZ and SL fields</line>
<line></line>
<line>boolean AArch64.S2InconsistentSL(S2TTWParams walkparams)</line>
<line>    startlevel   = AArch64.S2StartLevel(walkparams);</line>
<line>    levels       = <a link="FINAL_LEVEL" file="shared_pseudocode.xml" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</a> - startlevel;</line>
<line>    granulebits  = <a link="impl-shared.TGxGranuleBits.1" file="shared_pseudocode.xml" hover="function: integer TGxGranuleBits(TGx tgx)">TGxGranuleBits</a>(walkparams.tgx);</line>
<line>    descsizelog2 = 3;</line>
<line>    stride       = granulebits - descsizelog2;</line>
<line></line>
<line>    // Input address size must at least be large enough to be resolved from the start level</line>
<line>    sl_min_iasize = (</line>
<line>        levels * stride // Bits resolved by table walk, except initial level</line>
<line>        + granulebits   // Bits directly mapped to output address</line>
<line>        + 1);           // At least 1 more bit to be decoded by initial level</line>
<line></line>
<line>    // Can accomodate 1 more stride in the level + concatenation of up to 2^4 tables</line>
<line>    sl_max_iasize = sl_min_iasize + (stride-1) + 4;</line>
<line>    // Configured Input Address size</line>
<line>    iasize        = <a link="AArch64.IASize.1" file="shared_pseudocode.xml" hover="function: integer AArch64.IASize(bits(6) txsz)">AArch64.IASize</a>(walkparams.txsz);</line>
<line></line>
<line>    return iasize &lt; sl_min_iasize || iasize &gt; sl_max_iasize;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_faults/AArch64.S2IndirectBasePermissions" mylink="aarch64.translation.vmsa_faults.AArch64.S2IndirectBasePermissions" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S2IndirectBasePermissions()</line>
<line>// ===================================</line>
<line>// Computes the stage 2 indirect base permissions.</line>
<line></line>
<line link="AArch64.S2IndirectBasePermissions.2" hover="function: S2AccessControls AArch64.S2IndirectBasePermissions(Permissions permissions, AccessDescriptor accdesc)" conts="AArch64.S2IndirectBasePermissions">S2AccessControls <anchor link="AArch64.S2IndirectBasePermissions.2" hover="function: S2AccessControls AArch64.S2IndirectBasePermissions(Permissions permissions, AccessDescriptor accdesc)">AArch64.S2IndirectBasePermissions</anchor>(<a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> permissions,</line>
<line>                                                   <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    bit r, w;</line>
<line>    bit r_rcw, w_rcw;</line>
<line>    bit r_mmu, w_mmu;</line>
<line>    bit px, ux;</line>
<line>    bit toplevel0, toplevel1;</line>
<line>    <a link="S2AccessControls" file="shared_pseudocode.xml" hover="type S2AccessControls is ( bit r, bit w, bit x, bit r_rcw, bit w_rcw, bit r_mmu, bit w_mmu, bit toplevel0, bit toplevel1, boolean overlay, bit or, bit ow, bit ox, bit or_rcw, bit ow_rcw, bit or_mmu, bit ow_mmu, )">S2AccessControls</a> s2perms;</line>
<line></line>
<line>    bits(4) s2pi = permissions.s2pi;</line>
<line>    case s2pi of</line>
<line>        when '0000' (r,w,px,ux,w_rcw,w_mmu) = ('0','0','0','0','0','0');  // No Access</line>
<line>        when '0001' (r,w,px,ux,w_rcw,w_mmu) = ('0','0','0','0','0','0');  // Reserved</line>
<line>        when '0010' (r,w,px,ux,w_rcw,w_mmu) = ('1','0','0','0','1','1');  // MRO</line>
<line>        when '0011' (r,w,px,ux,w_rcw,w_mmu) = ('1','0','0','0','1','1');  // MRO-TL1</line>
<line>        when '0100' (r,w,px,ux,w_rcw,w_mmu) = ('0','1','0','0','0','0');  // Write Only</line>
<line>        when '0101' (r,w,px,ux,w_rcw,w_mmu) = ('0','0','0','0','0','0');  // Reserved</line>
<line>        when '0110' (r,w,px,ux,w_rcw,w_mmu) = ('1','0','0','0','1','1');  // MRO-TL0</line>
<line>        when '0111' (r,w,px,ux,w_rcw,w_mmu) = ('1','0','0','0','1','1');  // MRO-TL01</line>
<line>        when '1000' (r,w,px,ux,w_rcw,w_mmu) = ('1','0','0','0','0','0');  // Read Only</line>
<line>        when '1001' (r,w,px,ux,w_rcw,w_mmu) = ('1','0','0','1','0','0');  // Read, Unpriv Execute</line>
<line>        when '1010' (r,w,px,ux,w_rcw,w_mmu) = ('1','0','1','0','0','0');  // Read, Priv Execute</line>
<line>        when '1011' (r,w,px,ux,w_rcw,w_mmu) = ('1','0','1','1','0','0');  // Read, All Execute</line>
<line>        when '1100' (r,w,px,ux,w_rcw,w_mmu) = ('1','1','0','0','1','1');  // RW</line>
<line>        when '1101' (r,w,px,ux,w_rcw,w_mmu) = ('1','1','0','1','1','1');  // RW, Unpriv Execute</line>
<line>        when '1110' (r,w,px,ux,w_rcw,w_mmu) = ('1','1','1','0','1','1');  // RW, Priv Execute</line>
<line>        when '1111' (r,w,px,ux,w_rcw,w_mmu) = ('1','1','1','1','1','1');  // RW, All Execute</line>
<line></line>
<line>    x = if accdesc.el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then ux else px;</line>
<line></line>
<line>    // RCW and MMU read permissions.</line>
<line>    (r_rcw, r_mmu) = (r, r);</line>
<line></line>
<line>    // Stage 2 Top Level Permission Attributes.</line>
<line>    case s2pi of</line>
<line>        when '0110' (toplevel0,toplevel1) = ('1','0');</line>
<line>        when '0011' (toplevel0,toplevel1) = ('0','1');</line>
<line>        when '0111' (toplevel0,toplevel1) = ('1','1');</line>
<line>        otherwise   (toplevel0,toplevel1) = ('0','0');</line>
<line></line>
<line>    s2perms.r = r;</line>
<line>    s2perms.w = w;</line>
<line>    s2perms.x = x;</line>
<line>    s2perms.r_rcw = r_rcw;</line>
<line>    s2perms.r_mmu = r_mmu;</line>
<line>    s2perms.w_rcw = w_rcw;</line>
<line>    s2perms.w_mmu = w_mmu;</line>
<line>    s2perms.toplevel0 = toplevel0;</line>
<line>    s2perms.toplevel1 = toplevel1;</line>
<line></line>
<line>    return s2perms;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_faults/AArch64.S2InvalidSL" mylink="aarch64.translation.vmsa_faults.AArch64.S2InvalidSL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S2InvalidSL()</line>
<line>// =====================</line>
<line>// Detect invalid configuration of SL field</line>
<line></line>
<line>boolean AArch64.S2InvalidSL(S2TTWParams walkparams)</line>
<line>    case walkparams.tgx of</line>
<line>        when <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a></line>
<line>            case walkparams.sl2:walkparams.sl0 of</line>
<line>                when '1x1' return TRUE;</line>
<line>                when '11x' return TRUE;</line>
<line>                when '010' return <a link="AArch64.PAMax.0" file="shared_pseudocode.xml" hover="function: integer AArch64.PAMax()">AArch64.PAMax</a>() &lt; 44;</line>
<line>                when '011' return !<a link="impl-shared.HaveSmallTranslationTableExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveSmallTranslationTableExt()">HaveSmallTranslationTableExt</a>();</line>
<line>                otherwise  return FALSE;</line>
<line>        when <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a></line>
<line>            case walkparams.sl0 of</line>
<line>                when '11' return walkparams.ds == '0';</line>
<line>                when '10' return <a link="AArch64.PAMax.0" file="shared_pseudocode.xml" hover="function: integer AArch64.PAMax()">AArch64.PAMax</a>() &lt; 42;</line>
<line>                otherwise  return FALSE;</line>
<line>        when <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a></line>
<line>            case walkparams.sl0 of</line>
<line>                when '11'  return TRUE;</line>
<line>                when '10'  return <a link="AArch64.PAMax.0" file="shared_pseudocode.xml" hover="function: integer AArch64.PAMax()">AArch64.PAMax</a>() &lt; 44;</line>
<line>                otherwise  return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_faults/AArch64.S2OverlayPermissions" mylink="aarch64.translation.vmsa_faults.AArch64.S2OverlayPermissions" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S2OverlayPermissions()</line>
<line>// ==============================</line>
<line>// Computes the stage 2 overlay permissions.</line>
<line></line>
<line link="AArch64.S2OverlayPermissions.2" hover="function: S2AccessControls AArch64.S2OverlayPermissions(Permissions permissions, AccessDescriptor accdesc)" conts="AArch64.S2OverlayPermissions">S2AccessControls <anchor link="AArch64.S2OverlayPermissions.2" hover="function: S2AccessControls AArch64.S2OverlayPermissions(Permissions permissions, AccessDescriptor accdesc)">AArch64.S2OverlayPermissions</anchor>(<a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> permissions, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    bit r, w;</line>
<line>    bit r_rcw, w_rcw;</line>
<line>    bit r_mmu, w_mmu;</line>
<line>    bit px, ux;</line>
<line>    bit toplevel0, toplevel1;</line>
<line>    <a link="S2AccessControls" file="shared_pseudocode.xml" hover="type S2AccessControls is ( bit r, bit w, bit x, bit r_rcw, bit w_rcw, bit r_mmu, bit w_mmu, bit toplevel0, bit toplevel1, boolean overlay, bit or, bit ow, bit ox, bit or_rcw, bit ow_rcw, bit or_mmu, bit ow_mmu, )">S2AccessControls</a> s2overlay_perms;</line>
<line></line>
<line>    integer index = 4 * <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(permissions.s2po_index);</line>
<line>    bits(4) s2po = S2POR_EL1[index+3 : index];</line>
<line>    case s2po of</line>
<line>        when '0000' (r,w,px,ux,w_rcw,w_mmu) = ('0','0','0','0','0','0');  // No Access</line>
<line>        when '0001' (r,w,px,ux,w_rcw,w_mmu) = ('0','0','0','0','0','0');  // Reserved</line>
<line>        when '0010' (r,w,px,ux,w_rcw,w_mmu) = ('1','0','0','0','1','1');  // MRO</line>
<line>        when '0011' (r,w,px,ux,w_rcw,w_mmu) = ('1','0','0','0','1','1');  // MRO-TL1</line>
<line>        when '0100' (r,w,px,ux,w_rcw,w_mmu) = ('0','1','0','0','0','0');  // Write Only</line>
<line>        when '0101' (r,w,px,ux,w_rcw,w_mmu) = ('0','0','0','0','0','0');  // Reserved</line>
<line>        when '0110' (r,w,px,ux,w_rcw,w_mmu) = ('1','0','0','0','1','1');  // MRO-TL0</line>
<line>        when '0111' (r,w,px,ux,w_rcw,w_mmu) = ('1','0','0','0','1','1');  // MRO-TL01</line>
<line>        when '1000' (r,w,px,ux,w_rcw,w_mmu) = ('1','0','0','0','0','0');  // Read Only</line>
<line>        when '1001' (r,w,px,ux,w_rcw,w_mmu) = ('1','0','0','1','0','0');  // Read, Unpriv Execute</line>
<line>        when '1010' (r,w,px,ux,w_rcw,w_mmu) = ('1','0','1','0','0','0');  // Read, Priv Execute</line>
<line>        when '1011' (r,w,px,ux,w_rcw,w_mmu) = ('1','0','1','1','0','0');  // Read, All Execute</line>
<line>        when '1100' (r,w,px,ux,w_rcw,w_mmu) = ('1','1','0','0','1','1');  // RW</line>
<line>        when '1101' (r,w,px,ux,w_rcw,w_mmu) = ('1','1','0','1','1','1');  // RW, Unpriv Execute</line>
<line>        when '1110' (r,w,px,ux,w_rcw,w_mmu) = ('1','1','1','0','1','1');  // RW, Priv Execute</line>
<line>        when '1111' (r,w,px,ux,w_rcw,w_mmu) = ('1','1','1','1','1','1');  // RW, All Execute</line>
<line></line>
<line>    x = if accdesc.el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then ux else px;</line>
<line></line>
<line>    // RCW and MMU read permissions.</line>
<line>    (r_rcw, r_mmu) = (r, r);</line>
<line></line>
<line>    // Stage 2 Top Level Permission Attributes.</line>
<line>    case s2po of</line>
<line>        when '0110' (toplevel0,toplevel1) = ('1','0');</line>
<line>        when '0011' (toplevel0,toplevel1) = ('0','1');</line>
<line>        when '0111' (toplevel0,toplevel1) = ('1','1');</line>
<line>        otherwise   (toplevel0,toplevel1) = ('0','0');</line>
<line></line>
<line>    s2overlay_perms.or = r;</line>
<line>    s2overlay_perms.ow = w;</line>
<line>    s2overlay_perms.ox = x;</line>
<line>    s2overlay_perms.or_rcw = r_rcw;</line>
<line>    s2overlay_perms.ow_rcw = w_rcw;</line>
<line>    s2overlay_perms.or_mmu = r_mmu;</line>
<line>    s2overlay_perms.ow_mmu = w_mmu;</line>
<line>    s2overlay_perms.toplevel0 = toplevel0;</line>
<line>    s2overlay_perms.toplevel1 = toplevel1;</line>
<line></line>
<line>    return s2overlay_perms;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_faults/AArch64.S2TxSZFaults" mylink="aarch64.translation.vmsa_faults.AArch64.S2TxSZFaults" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S2TxSZFaults()</line>
<line>// ======================</line>
<line>// Detect whether configuration of stage 2 TxSZ field generates a fault</line>
<line></line>
<line>boolean AArch64.S2TxSZFaults(S2TTWParams walkparams, boolean s1aarch64)</line>
<line>    mintxsz = <a link="AArch64.S2MinTxSZ.4" file="shared_pseudocode.xml" hover="function: integer AArch64.S2MinTxSZ(bit d128, bit ds, TGx tgx, boolean s1aarch64)">AArch64.S2MinTxSZ</a>(walkparams.d128, walkparams.ds, walkparams.tgx, s1aarch64);</line>
<line>    maxtxsz = <a link="AArch64.MaxTxSZ.1" file="shared_pseudocode.xml" hover="function: integer AArch64.MaxTxSZ(TGx tgx)">AArch64.MaxTxSZ</a>(walkparams.tgx);</line>
<line></line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(walkparams.txsz) &lt; mintxsz then</line>
<line>        return (<a link="impl-shared.Have52BitPAExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitPAExt()">Have52BitPAExt</a>() ||</line>
<line>                boolean IMPLEMENTATION_DEFINED "<a link="Fault" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault</a> on TxSZ value below minimum");</line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(walkparams.txsz) &gt; maxtxsz then</line>
<line>        return boolean IMPLEMENTATION_DEFINED "<a link="Fault" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault</a> on TxSZ value above maximum";</line>
<line></line>
<line>    return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_faults/AArch64.VAIsOutOfRange" mylink="aarch64.translation.vmsa_faults.AArch64.VAIsOutOfRange" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.VAIsOutOfRange()</line>
<line>// ========================</line>
<line>// Check bits not resolved by translation are identical and of accepted value</line>
<line></line>
<line>boolean AArch64.VAIsOutOfRange(bits(64) va_in, <a link="AccessType" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType</a> acctype,</line>
<line>                               <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, S1TTWParams walkparams)</line>
<line>    bits(64) va = va_in;</line>
<line></line>
<line>    addrtop = <a link="AArch64.AddrTop.3" file="shared_pseudocode.xml" hover="function: integer AArch64.AddrTop(bit tbid, AccessType acctype, bit tbi)">AArch64.AddrTop</a>(walkparams.tbid, acctype, walkparams.tbi);</line>
<line></line>
<line>    // If the VA has a Logical Address Tag then the bits holding the Logical Address Tag are</line>
<line>    // ignored when checking if the address is out of range.</line>
<line>    if walkparams.mtx == '1' then</line>
<line>        va&lt;59:56&gt; = if <a link="AArch64.GetVARange.1" file="shared_pseudocode.xml" hover="function: VARange AArch64.GetVARange(bits(64) va)">AArch64.GetVARange</a>(va) == <a link="VARange_UPPER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_UPPER</a> then '1111' else '0000';</line>
<line></line>
<line>    // Input Address size</line>
<line>    iasize  = <a link="AArch64.IASize.1" file="shared_pseudocode.xml" hover="function: integer AArch64.IASize(bits(6) txsz)">AArch64.IASize</a>(walkparams.txsz);</line>
<line></line>
<line>    // The min value of TxSZ can be 8, with LVA3 implemented.</line>
<line>    // If TxSZ is set to 8 iasize becomes 64 - 8 = 56</line>
<line>    // If tbi is also set, addrtop becomes 55</line>
<line>    // Then the return statements check va&lt;56:55&gt;</line>
<line>    // The check here is to guard against this corner case.</line>
<line>    if addrtop &lt; iasize then</line>
<line>        return FALSE;</line>
<line></line>
<line>    if <a link="impl-shared.HasUnprivileged.1" file="shared_pseudocode.xml" hover="function: boolean HasUnprivileged(Regime regime)">HasUnprivileged</a>(regime) then</line>
<line>        if <a link="AArch64.GetVARange.1" file="shared_pseudocode.xml" hover="function: VARange AArch64.GetVARange(bits(64) va)">AArch64.GetVARange</a>(va) == <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a> then</line>
<line>            return !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(va&lt;addrtop:iasize&gt;);</line>
<line>        else</line>
<line>            return !<a link="impl-shared.IsOnes.1" file="shared_pseudocode.xml" hover="function: boolean IsOnes(bits(N) x)">IsOnes</a>(va&lt;addrtop:iasize&gt;);</line>
<line>    else</line>
<line>        return !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(va&lt;addrtop:iasize&gt;);</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_memattr/AArch64.S2ApplyFWBMemAttrs" mylink="aarch64.translation.vmsa_memattr.AArch64.S2ApplyFWBMemAttrs" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S2ApplyFWBMemAttrs()</line>
<line>// ============================</line>
<line>// Apply stage 2 forced Write-Back on stage 1 memory attributes.</line>
<line></line>
<line><a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> AArch64.S2ApplyFWBMemAttrs(<a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> s1_memattrs, S2TTWParams walkparams,</line>
<line>                                            bits(N) descriptor)</line>
<line>    <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs;</line>
<line>    s2_attr = descriptor&lt;5:2&gt;;</line>
<line>    s2_sh   = if walkparams.ds == '1' then walkparams.sh else descriptor&lt;9:8&gt;;</line>
<line>    s2_fnxs = descriptor&lt;11&gt;;</line>
<line></line>
<line>    if s2_attr&lt;2&gt; == '0' then          // S2 Device, S1 any</line>
<line>        s2_device = <a link="impl-shared.DecodeDevice.1" file="shared_pseudocode.xml" hover="function: DeviceType DecodeDevice(bits(2) device)">DecodeDevice</a>(s2_attr&lt;1:0&gt;);</line>
<line>        memattrs.memtype = <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a>;</line>
<line>        if s1_memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> then</line>
<line>            memattrs.device = <a link="impl-shared.S2CombineS1Device.2" file="shared_pseudocode.xml" hover="function: DeviceType S2CombineS1Device(DeviceType s1_device, DeviceType s2_device)">S2CombineS1Device</a>(s1_memattrs.device, s2_device);</line>
<line>        else</line>
<line>            memattrs.device = s2_device;</line>
<line></line>
<line>        memattrs.xs = s1_memattrs.xs;</line>
<line></line>
<line>    elsif s2_attr&lt;1:0&gt; == '11' then    // S2 attr = S1 attr</line>
<line>        memattrs = s1_memattrs;</line>
<line></line>
<line>    elsif s2_attr&lt;1:0&gt; == '10' then    // Force writeback</line>
<line>        memattrs.memtype = <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>;</line>
<line>        memattrs.inner.attrs = <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>;</line>
<line>        memattrs.outer.attrs = <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>;</line>
<line></line>
<line>        if (s1_memattrs.memtype == <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a> &amp;&amp;</line>
<line>                s1_memattrs.inner.attrs != <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a>) then</line>
<line>            memattrs.inner.hints     = s1_memattrs.inner.hints;</line>
<line>            memattrs.inner.transient = s1_memattrs.inner.transient;</line>
<line>        else</line>
<line>            memattrs.inner.hints     = <a link="MemHint_RWA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RWA = '11'">MemHint_RWA</a>;</line>
<line>            memattrs.inner.transient = FALSE;</line>
<line></line>
<line>        if (s1_memattrs.memtype == <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a> &amp;&amp;</line>
<line>                s1_memattrs.outer.attrs != <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a>) then</line>
<line>            memattrs.outer.hints     = s1_memattrs.outer.hints;</line>
<line>            memattrs.outer.transient = s1_memattrs.outer.transient;</line>
<line>        else</line>
<line>            memattrs.outer.hints     = <a link="MemHint_RWA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RWA = '11'">MemHint_RWA</a>;</line>
<line>            memattrs.outer.transient = FALSE;</line>
<line></line>
<line>        memattrs.xs = '0';</line>
<line></line>
<line>    else                               // Non-cacheable unless S1 is device</line>
<line>        if s1_memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> then</line>
<line>            memattrs = s1_memattrs;</line>
<line>        else</line>
<line>            <a link="MemAttrHints" file="shared_pseudocode.xml" hover="type MemAttrHints is ( bits(2) attrs, bits(2) hints, boolean transient )">MemAttrHints</a> cacheability_attr;</line>
<line>            cacheability_attr.attrs = <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a>;</line>
<line></line>
<line>            memattrs.memtype = <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>;</line>
<line>            memattrs.inner   = cacheability_attr;</line>
<line>            memattrs.outer   = cacheability_attr;</line>
<line></line>
<line>            memattrs.xs = s1_memattrs.xs;</line>
<line></line>
<line>    s2_shareability = <a link="impl-shared.DecodeShareability.1" file="shared_pseudocode.xml" hover="function: Shareability DecodeShareability(bits(2) sh)">DecodeShareability</a>(s2_sh);</line>
<line>    memattrs.shareability = <a link="impl-shared.S2CombineS1Shareability.2" file="shared_pseudocode.xml" hover="function: Shareability S2CombineS1Shareability(Shareability s1_shareability, Shareability s2_shareability)">S2CombineS1Shareability</a>(s1_memattrs.shareability, s2_shareability);</line>
<line>    memattrs.tags         = <a link="impl-shared.S2MemTagType.2" file="shared_pseudocode.xml" hover="function: MemTagType S2MemTagType(MemoryAttributes s2_memattrs, MemTagType s1_tagtype)">S2MemTagType</a>(memattrs, s1_memattrs.tags);</line>
<line>    memattrs.notagaccess  = (s2_attr&lt;3:1&gt; == '111' &amp;&amp; memattrs.tags == <a link="MemTag_AllocationTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_AllocationTagged</a>);</line>
<line></line>
<line>    if s2_fnxs == '1' then</line>
<line>        memattrs.xs = '0';</line>
<line></line>
<line>    memattrs.shareability = <a link="impl-shared.EffectiveShareability.1" file="shared_pseudocode.xml" hover="function: Shareability EffectiveShareability(MemoryAttributes memattrs)">EffectiveShareability</a>(memattrs);</line>
<line>    return memattrs;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_tlbcontext/AArch64.GetS1TLBContext" mylink="aarch64.translation.vmsa_tlbcontext.AArch64.GetS1TLBContext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.GetS1TLBContext()</line>
<line>// =========================</line>
<line>// Gather translation context for accesses with VA to match against TLB entries</line>
<line></line>
<line link="AArch64.GetS1TLBContext.4" hover="function: TLBContext AArch64.GetS1TLBContext(Regime regime, SecurityState ss, bits(64) va, TGx tg)" conts="AArch64.GetS1TLBContext">TLBContext <anchor link="AArch64.GetS1TLBContext.4" hover="function: TLBContext AArch64.GetS1TLBContext(Regime regime, SecurityState ss, bits(64) va, TGx tg)">AArch64.GetS1TLBContext</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss, bits(64) va, <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tg)</line>
<line>    <a link="TLBContext" file="shared_pseudocode.xml" hover="type TLBContext is ( SecurityState ss, Regime regime, bits(16) vmid, bits(16) asid, bit nG, PASpace ipaspace, boolean includes_s1, boolean includes_s2, boolean includes_gpt, bits(64) ia, TGx tg, bit cnp, integer level, boolean isd128, bit xs )">TLBContext</a> tlbcontext;</line>
<line></line>
<line>    case regime of</line>
<line>        when <a link="Regime_EL3" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL3</a>  tlbcontext = <a link="AArch64.TLBContextEL3.3" file="shared_pseudocode.xml" hover="function: TLBContext AArch64.TLBContextEL3(SecurityState ss, bits(64) va, TGx tg)">AArch64.TLBContextEL3</a>(ss, va, tg);</line>
<line>        when <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>  tlbcontext = <a link="AArch64.TLBContextEL2.3" file="shared_pseudocode.xml" hover="function: TLBContext AArch64.TLBContextEL2(SecurityState ss, bits(64) va, TGx tg)">AArch64.TLBContextEL2</a>(ss, va, tg);</line>
<line>        when <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a> tlbcontext = <a link="AArch64.TLBContextEL20.3" file="shared_pseudocode.xml" hover="function: TLBContext AArch64.TLBContextEL20(SecurityState ss, bits(64) va, TGx tg)">AArch64.TLBContextEL20</a>(ss, va, tg);</line>
<line>        when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> tlbcontext = <a link="AArch64.TLBContextEL10.3" file="shared_pseudocode.xml" hover="function: TLBContext AArch64.TLBContextEL10(SecurityState ss, bits(64) va, TGx tg)">AArch64.TLBContextEL10</a>(ss, va, tg);</line>
<line></line>
<line>    tlbcontext.includes_s1  = TRUE;</line>
<line>    // The following may be amended for EL1&amp;0 Regime if caching of stage 2 is successful</line>
<line>    tlbcontext.includes_s2  = FALSE;</line>
<line>    // The following may be amended if Granule Protection Check passes</line>
<line>    tlbcontext.includes_gpt = FALSE;</line>
<line>    return tlbcontext;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_tlbcontext/AArch64.GetS2TLBContext" mylink="aarch64.translation.vmsa_tlbcontext.AArch64.GetS2TLBContext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.GetS2TLBContext()</line>
<line>// =========================</line>
<line>// Gather translation context for accesses with IPA to match against TLB entries</line>
<line></line>
<line link="AArch64.GetS2TLBContext.3" hover="function: TLBContext AArch64.GetS2TLBContext(SecurityState ss, FullAddress ipa, TGx tg)" conts="AArch64.GetS2TLBContext">TLBContext <anchor link="AArch64.GetS2TLBContext.3" hover="function: TLBContext AArch64.GetS2TLBContext(SecurityState ss, FullAddress ipa, TGx tg)">AArch64.GetS2TLBContext</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss, <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> ipa, <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tg)</line>
<line>    assert <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>();</line>
<line></line>
<line>    <a link="TLBContext" file="shared_pseudocode.xml" hover="type TLBContext is ( SecurityState ss, Regime regime, bits(16) vmid, bits(16) asid, bit nG, PASpace ipaspace, boolean includes_s1, boolean includes_s2, boolean includes_gpt, bits(64) ia, TGx tg, bit cnp, integer level, boolean isd128, bit xs )">TLBContext</a> tlbcontext;</line>
<line></line>
<line>    tlbcontext.ss       = ss;</line>
<line>    tlbcontext.regime   = <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a>;</line>
<line>    tlbcontext.ipaspace = ipa.paspace;</line>
<line>    tlbcontext.vmid     = <a link="impl-aarch64.VMID.read.0" file="shared_pseudocode.xml" hover="accessor: bits(16) VMID[]">VMID</a>[];</line>
<line>    tlbcontext.tg       = tg;</line>
<line>    tlbcontext.ia       = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(ipa.address, 64);</line>
<line>    if <a link="impl-shared.HaveCommonNotPrivateTransExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveCommonNotPrivateTransExt()">HaveCommonNotPrivateTransExt</a>() then</line>
<line>        tlbcontext.cnp = if ipa.paspace == <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a> then VSTTBR_EL2.CnP else VTTBR_EL2.CnP;</line>
<line>    else</line>
<line>        tlbcontext.cnp = '0';</line>
<line></line>
<line>    tlbcontext.includes_s1  = FALSE;</line>
<line>    tlbcontext.includes_s2  = TRUE;</line>
<line>    // This amy be amended if Granule Protection Check passes</line>
<line>    tlbcontext.includes_gpt = FALSE;</line>
<line>    return tlbcontext;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_tlbcontext/AArch64.TLBContextEL10" mylink="aarch64.translation.vmsa_tlbcontext.AArch64.TLBContextEL10" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TLBContextEL10()</line>
<line>// ========================</line>
<line>// Gather translation context for accesses under EL10 regime to match against TLB entries</line>
<line></line>
<line link="AArch64.TLBContextEL10.3" hover="function: TLBContext AArch64.TLBContextEL10(SecurityState ss, bits(64) va, TGx tg)" conts="AArch64.TLBContextEL10">TLBContext <anchor link="AArch64.TLBContextEL10.3" hover="function: TLBContext AArch64.TLBContextEL10(SecurityState ss, bits(64) va, TGx tg)">AArch64.TLBContextEL10</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss, bits(64) va, <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tg)</line>
<line>    <a link="TLBContext" file="shared_pseudocode.xml" hover="type TLBContext is ( SecurityState ss, Regime regime, bits(16) vmid, bits(16) asid, bit nG, PASpace ipaspace, boolean includes_s1, boolean includes_s2, boolean includes_gpt, bits(64) ia, TGx tg, bit cnp, integer level, boolean isd128, bit xs )">TLBContext</a> tlbcontext;</line>
<line></line>
<line>    tlbcontext.ss     = ss;</line>
<line>    tlbcontext.regime = <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a>;</line>
<line>    tlbcontext.vmid   = <a link="impl-aarch64.VMID.read.0" file="shared_pseudocode.xml" hover="accessor: bits(16) VMID[]">VMID</a>[];</line>
<line>    tlbcontext.asid   = if TCR_EL1.A1 == '0' then TTBR0_EL1.ASID else TTBR1_EL1.ASID;</line>
<line>    if TCR_EL1.AS == '0' then</line>
<line>        tlbcontext.asid&lt;15:8&gt; = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8);</line>
<line>    tlbcontext.tg     = tg;</line>
<line>    tlbcontext.ia     = va;</line>
<line></line>
<line>    if <a link="impl-shared.HaveCommonNotPrivateTransExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveCommonNotPrivateTransExt()">HaveCommonNotPrivateTransExt</a>() then</line>
<line>        if <a link="AArch64.GetVARange.1" file="shared_pseudocode.xml" hover="function: VARange AArch64.GetVARange(bits(64) va)">AArch64.GetVARange</a>(va) == <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a> then</line>
<line>            tlbcontext.cnp = TTBR0_EL1.CnP;</line>
<line>        else</line>
<line>            tlbcontext.cnp = TTBR1_EL1.CnP;</line>
<line>    else</line>
<line>        tlbcontext.cnp = '0';</line>
<line></line>
<line>    return tlbcontext;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_tlbcontext/AArch64.TLBContextEL2" mylink="aarch64.translation.vmsa_tlbcontext.AArch64.TLBContextEL2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TLBContextEL2()</line>
<line>// =======================</line>
<line>// Gather translation context for accesses under EL2 regime to match against TLB entries</line>
<line></line>
<line link="AArch64.TLBContextEL2.3" hover="function: TLBContext AArch64.TLBContextEL2(SecurityState ss, bits(64) va, TGx tg)" conts="AArch64.TLBContextEL2">TLBContext <anchor link="AArch64.TLBContextEL2.3" hover="function: TLBContext AArch64.TLBContextEL2(SecurityState ss, bits(64) va, TGx tg)">AArch64.TLBContextEL2</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss, bits(64) va, <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tg)</line>
<line>    <a link="TLBContext" file="shared_pseudocode.xml" hover="type TLBContext is ( SecurityState ss, Regime regime, bits(16) vmid, bits(16) asid, bit nG, PASpace ipaspace, boolean includes_s1, boolean includes_s2, boolean includes_gpt, bits(64) ia, TGx tg, bit cnp, integer level, boolean isd128, bit xs )">TLBContext</a> tlbcontext;</line>
<line></line>
<line>    tlbcontext.ss     = ss;</line>
<line>    tlbcontext.regime = <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>;</line>
<line>    tlbcontext.tg     = tg;</line>
<line>    tlbcontext.ia     = va;</line>
<line>    tlbcontext.cnp    = if <a link="impl-shared.HaveCommonNotPrivateTransExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveCommonNotPrivateTransExt()">HaveCommonNotPrivateTransExt</a>() then TTBR0_EL2.CnP else '0';</line>
<line></line>
<line>    return tlbcontext;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_tlbcontext/AArch64.TLBContextEL20" mylink="aarch64.translation.vmsa_tlbcontext.AArch64.TLBContextEL20" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TLBContextEL20()</line>
<line>// ========================</line>
<line>// Gather translation context for accesses under EL20 regime to match against TLB entries</line>
<line></line>
<line link="AArch64.TLBContextEL20.3" hover="function: TLBContext AArch64.TLBContextEL20(SecurityState ss, bits(64) va, TGx tg)" conts="AArch64.TLBContextEL20">TLBContext <anchor link="AArch64.TLBContextEL20.3" hover="function: TLBContext AArch64.TLBContextEL20(SecurityState ss, bits(64) va, TGx tg)">AArch64.TLBContextEL20</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss, bits(64) va, <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tg)</line>
<line>    <a link="TLBContext" file="shared_pseudocode.xml" hover="type TLBContext is ( SecurityState ss, Regime regime, bits(16) vmid, bits(16) asid, bit nG, PASpace ipaspace, boolean includes_s1, boolean includes_s2, boolean includes_gpt, bits(64) ia, TGx tg, bit cnp, integer level, boolean isd128, bit xs )">TLBContext</a> tlbcontext;</line>
<line></line>
<line>    tlbcontext.ss     = ss;</line>
<line>    tlbcontext.regime = <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a>;</line>
<line>    tlbcontext.asid   = if TCR_EL2.A1 == '0' then TTBR0_EL2.ASID else TTBR1_EL2.ASID;</line>
<line>    if TCR_EL2.AS == '0' then</line>
<line>        tlbcontext.asid&lt;15:8&gt; = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8);</line>
<line>    tlbcontext.tg     = tg;</line>
<line>    tlbcontext.ia     = va;</line>
<line></line>
<line>    if <a link="impl-shared.HaveCommonNotPrivateTransExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveCommonNotPrivateTransExt()">HaveCommonNotPrivateTransExt</a>() then</line>
<line>        if <a link="AArch64.GetVARange.1" file="shared_pseudocode.xml" hover="function: VARange AArch64.GetVARange(bits(64) va)">AArch64.GetVARange</a>(va) == <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a> then</line>
<line>            tlbcontext.cnp = TTBR0_EL2.CnP;</line>
<line>        else</line>
<line>            tlbcontext.cnp = TTBR1_EL2.CnP;</line>
<line>    else</line>
<line>        tlbcontext.cnp = '0';</line>
<line></line>
<line>    return tlbcontext;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_tlbcontext/AArch64.TLBContextEL3" mylink="aarch64.translation.vmsa_tlbcontext.AArch64.TLBContextEL3" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TLBContextEL3()</line>
<line>// =======================</line>
<line>// Gather translation context for accesses under EL3 regime to match against TLB entries</line>
<line></line>
<line link="AArch64.TLBContextEL3.3" hover="function: TLBContext AArch64.TLBContextEL3(SecurityState ss, bits(64) va, TGx tg)" conts="AArch64.TLBContextEL3">TLBContext <anchor link="AArch64.TLBContextEL3.3" hover="function: TLBContext AArch64.TLBContextEL3(SecurityState ss, bits(64) va, TGx tg)">AArch64.TLBContextEL3</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss, bits(64) va, <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tg)</line>
<line>    <a link="TLBContext" file="shared_pseudocode.xml" hover="type TLBContext is ( SecurityState ss, Regime regime, bits(16) vmid, bits(16) asid, bit nG, PASpace ipaspace, boolean includes_s1, boolean includes_s2, boolean includes_gpt, bits(64) ia, TGx tg, bit cnp, integer level, boolean isd128, bit xs )">TLBContext</a> tlbcontext;</line>
<line></line>
<line>    tlbcontext.ss     = ss;</line>
<line>    tlbcontext.regime = <a link="Regime_EL3" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL3</a>;</line>
<line>    tlbcontext.tg     = tg;</line>
<line>    tlbcontext.ia     = va;</line>
<line>    tlbcontext.cnp    = if <a link="impl-shared.HaveCommonNotPrivateTransExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveCommonNotPrivateTransExt()">HaveCommonNotPrivateTransExt</a>() then TTBR0_EL3.CnP else '0';</line>
<line></line>
<line>    return tlbcontext;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_translation/AArch64.FullTranslate" mylink="aarch64.translation.vmsa_translation.AArch64.FullTranslate" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.FullTranslate()</line>
<line>// =======================</line>
<line>// Address translation as specified by VMSA</line>
<line>// Alignment check NOT due to memory type is expected to be done before translation</line>
<line></line>
<line link="AArch64.FullTranslate.3" hover="function: AddressDescriptor AArch64.FullTranslate(bits(64) va, AccessDescriptor accdesc, boolean aligned)" conts="AArch64.FullTranslate">AddressDescriptor <anchor link="AArch64.FullTranslate.3" hover="function: AddressDescriptor AArch64.FullTranslate(bits(64) va, AccessDescriptor accdesc, boolean aligned)">AArch64.FullTranslate</anchor>(bits(64) va, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, boolean aligned)</line>
<line>    <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime = <a link="impl-shared.TranslationRegime.1" file="shared_pseudocode.xml" hover="function: Regime TranslationRegime(bits(2) el)">TranslationRegime</a>(accdesc.el);</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = <a link="impl-shared.NoFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord NoFault(AccessDescriptor accdesc)">NoFault</a>(accdesc);</line>
<line></line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> ipa;</line>
<line>    (fault, ipa) = <a link="AArch64.S1Translate.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, AddressDescriptor) AArch64.S1Translate(FaultRecord fault_in, Regime regime, bits(64) va, boolean aligned, AccessDescriptor accdesc)">AArch64.S1Translate</a>(fault, regime, va, aligned, accdesc);</line>
<line></line>
<line>    if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>        return <a link="impl-shared.CreateFaultyAddressDescriptor.2" file="shared_pseudocode.xml" hover="function: AddressDescriptor CreateFaultyAddressDescriptor(bits(64) va, FaultRecord fault)">CreateFaultyAddressDescriptor</a>(va, fault);</line>
<line></line>
<line>    assert (accdesc.ss == <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>) IMPLIES <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>();</line>
<line>    if regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        s1aarch64 = TRUE;</line>
<line>        <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> pa;</line>
<line>        (fault, pa) = <a link="AArch64.S2Translate.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, AddressDescriptor) AArch64.S2Translate(FaultRecord fault_in, AddressDescriptor ipa, boolean s1aarch64, boolean aligned, AccessDescriptor accdesc)">AArch64.S2Translate</a>(fault, ipa, s1aarch64, aligned, accdesc);</line>
<line></line>
<line>        if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>            return <a link="impl-shared.CreateFaultyAddressDescriptor.2" file="shared_pseudocode.xml" hover="function: AddressDescriptor CreateFaultyAddressDescriptor(bits(64) va, FaultRecord fault)">CreateFaultyAddressDescriptor</a>(va, fault);</line>
<line>        else</line>
<line>            return pa;</line>
<line>    else</line>
<line>        return ipa;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_translation/AArch64.MemSwapTableDesc" mylink="aarch64.translation.vmsa_translation.AArch64.MemSwapTableDesc" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.MemSwapTableDesc()</line>
<line>// ==========================</line>
<line>// Perform HW update of table descriptor as an atomic operation</line>
<line></line>
<line link="AArch64.MemSwapTableDesc.6" hover="function: (FaultRecord, bits(N)) AArch64.MemSwapTableDesc(FaultRecord fault_in, bits(N) prev_desc, bits(N) new_desc, bit ee, AccessDescriptor  descaccess, AddressDescriptor descpaddr)" conts="AArch64.MemSwapTableDesc">(FaultRecord, bits(N)) <anchor link="AArch64.MemSwapTableDesc.6" hover="function: (FaultRecord, bits(N)) AArch64.MemSwapTableDesc(FaultRecord fault_in, bits(N) prev_desc, bits(N) new_desc, bit ee, AccessDescriptor  descaccess, AddressDescriptor descpaddr)">AArch64.MemSwapTableDesc</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault_in, bits(N) prev_desc,</line>
<line>                                                bits(N) new_desc, bit ee,</line>
<line>                                                <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a>  descaccess,</line>
<line>                                                <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> descpaddr)</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = fault_in;</line>
<line>    boolean iswrite;</line>
<line></line>
<line>    if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then</line>
<line>        fault.gpcf = <a link="impl-shared.GranuleProtectionCheck.2" file="shared_pseudocode.xml" hover="function: GPCFRecord GranuleProtectionCheck(AddressDescriptor addrdesc, AccessDescriptor accdesc)">GranuleProtectionCheck</a>(descpaddr, descaccess);</line>
<line>        if fault.gpcf.gpf != <a link="GPCF_None" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_None</a> then</line>
<line>            fault.statuscode = <a link="Fault_GPCFOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_GPCFOnWalk</a>;</line>
<line>            fault.paddress   = descpaddr.paddress;</line>
<line>            fault.gpcfs2walk = fault.secondstage;</line>
<line>            return (fault, bits(N) UNKNOWN);</line>
<line></line>
<line>    // All observers in the shareability domain observe the</line>
<line>    // following memory read and write accesses atomically.</line>
<line>    bits(N) mem_desc;</line>
<line>    <a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> memstatus;</line>
<line>    (memstatus, mem_desc) = <a link="impl-shared.PhysMemRead.3" file="shared_pseudocode.xml" hover="function: (PhysMemRetStatus, bits(8*size)) PhysMemRead(AddressDescriptor desc, integer size, AccessDescriptor accdesc)">PhysMemRead</a>(descpaddr, N DIV 8, descaccess);</line>
<line></line>
<line>    if ee == '1' then</line>
<line>        mem_desc = <a link="impl-shared.BigEndianReverse.1" file="shared_pseudocode.xml" hover="function: bits(width) BigEndianReverse (bits(width) value)">BigEndianReverse</a>(mem_desc);</line>
<line></line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>        iswrite = FALSE;</line>
<line>        fault = <a link="impl-shared.HandleExternalTTWAbort.6" file="shared_pseudocode.xml" hover="function: FaultRecord HandleExternalTTWAbort(PhysMemRetStatus memretstatus, boolean iswrite, AddressDescriptor memaddrdesc, AccessDescriptor accdesc, integer size, FaultRecord input_fault)">HandleExternalTTWAbort</a>(memstatus, iswrite, descpaddr, descaccess, N DIV 8, fault);</line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(fault.statuscode) then</line>
<line>            return (fault, bits(N) UNKNOWN);</line>
<line></line>
<line>    if mem_desc == prev_desc  then</line>
<line>        ordered_new_desc = if ee == '1' then <a link="impl-shared.BigEndianReverse.1" file="shared_pseudocode.xml" hover="function: bits(width) BigEndianReverse (bits(width) value)">BigEndianReverse</a>(new_desc) else new_desc;</line>
<line>        memstatus = <a link="impl-shared.PhysMemWrite.4" file="shared_pseudocode.xml" hover="function: PhysMemRetStatus PhysMemWrite(AddressDescriptor desc, integer size, AccessDescriptor accdesc, bits(8*size) value)">PhysMemWrite</a>(descpaddr, N DIV 8, descaccess, ordered_new_desc);</line>
<line></line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>            iswrite = TRUE;</line>
<line>            fault = <a link="impl-shared.HandleExternalTTWAbort.6" file="shared_pseudocode.xml" hover="function: FaultRecord HandleExternalTTWAbort(PhysMemRetStatus memretstatus, boolean iswrite, AddressDescriptor memaddrdesc, AccessDescriptor accdesc, integer size, FaultRecord input_fault)">HandleExternalTTWAbort</a>(memstatus, iswrite, descpaddr, descaccess, N DIV 8,</line>
<line>                                           fault);</line>
<line></line>
<line>            if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(fault.statuscode) then</line>
<line>                return (fault, bits(N) UNKNOWN);</line>
<line></line>
<line>        // Reflect what is now in memory (in little endian format)</line>
<line>        mem_desc = new_desc;</line>
<line></line>
<line>    return (fault, mem_desc);</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_translation/AArch64.S1DisabledOutput" mylink="aarch64.translation.vmsa_translation.AArch64.S1DisabledOutput" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1DisabledOutput()</line>
<line>// ==========================</line>
<line>// Map the VA to IPA/PA and assign default memory attributes</line>
<line></line>
<line link="AArch64.S1DisabledOutput.5" hover="function: (FaultRecord, AddressDescriptor) AArch64.S1DisabledOutput(FaultRecord fault_in, Regime regime, bits(64) va_in, AccessDescriptor accdesc, boolean aligned)" conts="AArch64.S1DisabledOutput">(FaultRecord, AddressDescriptor) <anchor link="AArch64.S1DisabledOutput.5" hover="function: (FaultRecord, AddressDescriptor) AArch64.S1DisabledOutput(FaultRecord fault_in, Regime regime, bits(64) va_in, AccessDescriptor accdesc, boolean aligned)">AArch64.S1DisabledOutput</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault_in, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime,</line>
<line>                                                          bits(64) va_in, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc,</line>
<line>                                                          boolean aligned)</line>
<line></line>
<line>    bits(64) va = va_in;</line>
<line>    walkparams = AArch64.GetS1TTWParams(regime, accdesc.ss, va);</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = fault_in;</line>
<line></line>
<line>    // No memory page is guarded when stage 1 address translation is disabled</line>
<line>    <a link="impl-aarch64.SetInGuardedPage.1" file="shared_pseudocode.xml" hover="function: SetInGuardedPage(boolean guardedpage)">SetInGuardedPage</a>(FALSE);</line>
<line></line>
<line>    // Output Address</line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> oa;</line>
<line>    oa.address = va&lt;55:0&gt;;</line>
<line>    case accdesc.ss of</line>
<line>        when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>    oa.paspace = <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a>;</line>
<line>        when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> oa.paspace = <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line>        when <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>      oa.paspace = <a link="PAS_Root" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Root</a>;</line>
<line>        when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>     oa.paspace = <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a>;</line>
<line></line>
<line>    <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs;</line>
<line>    if regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; walkparams.dc == '1' then</line>
<line>        <a link="MemAttrHints" file="shared_pseudocode.xml" hover="type MemAttrHints is ( bits(2) attrs, bits(2) hints, boolean transient )">MemAttrHints</a> default_cacheability;</line>
<line>        default_cacheability.attrs     = <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>;</line>
<line>        default_cacheability.hints     = <a link="MemHint_RWA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RWA = '11'">MemHint_RWA</a>;</line>
<line>        default_cacheability.transient = FALSE;</line>
<line></line>
<line>        memattrs.memtype      = <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>;</line>
<line>        memattrs.outer        = default_cacheability;</line>
<line>        memattrs.inner        = default_cacheability;</line>
<line>        memattrs.shareability = <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a>;</line>
<line>        if walkparams.dct == '1' then</line>
<line>            memattrs.tags     = <a link="MemTag_AllocationTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_AllocationTagged</a>;</line>
<line>        elsif walkparams.mtx == '1' then</line>
<line>            memattrs.tags     = <a link="MemTag_CanonicallyTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_CanonicallyTagged</a>;</line>
<line>            if walkparams.tbi == '0' then</line>
<line>                // For the purpose of the checks in this function, the MTE tag bits are ignored.</line>
<line>                va&lt;59:56&gt;     = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(va&lt;55&gt;, 4);</line>
<line>        else</line>
<line>            memattrs.tags     = <a link="MemTag_Untagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_Untagged</a>;</line>
<line>        memattrs.xs           = '0';</line>
<line>    elsif accdesc.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> then</line>
<line>        <a link="MemAttrHints" file="shared_pseudocode.xml" hover="type MemAttrHints is ( bits(2) attrs, bits(2) hints, boolean transient )">MemAttrHints</a> i_cache_attr;</line>
<line>        if <a link="AArch64.S1ICacheEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.S1ICacheEnabled(Regime regime)">AArch64.S1ICacheEnabled</a>(regime) then</line>
<line>            i_cache_attr.attrs     = <a link="MemAttr_WT" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WT = '10'">MemAttr_WT</a>;</line>
<line>            i_cache_attr.hints     = <a link="MemHint_RA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RA = '10'">MemHint_RA</a>;</line>
<line>            i_cache_attr.transient = FALSE;</line>
<line>        else</line>
<line>            i_cache_attr.attrs     = <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a>;</line>
<line></line>
<line>        memattrs.memtype      = <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>;</line>
<line>        memattrs.outer        = i_cache_attr;</line>
<line>        memattrs.inner        = i_cache_attr;</line>
<line>        memattrs.shareability = <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a>;</line>
<line>        if walkparams.mtx == '1' then</line>
<line>            memattrs.tags     = <a link="MemTag_CanonicallyTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_CanonicallyTagged</a>;</line>
<line>        else</line>
<line>            memattrs.tags     = <a link="MemTag_Untagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_Untagged</a>;</line>
<line>        memattrs.xs           = '1';</line>
<line>    else</line>
<line>        memattrs.memtype      = <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a>;</line>
<line>        memattrs.device       = <a link="DeviceType_nGnRnE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGnRnE</a>;</line>
<line>        memattrs.shareability = <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a>;</line>
<line>        if walkparams.mtx == '1' then</line>
<line>            memattrs.tags = <a link="MemTag_CanonicallyTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_CanonicallyTagged</a>;</line>
<line>            if walkparams.tbi == '0' then</line>
<line>                // For the purpose of the checks in this function, the MTE tag bits are ignored.</line>
<line>                if <a link="impl-shared.HasUnprivileged.1" file="shared_pseudocode.xml" hover="function: boolean HasUnprivileged(Regime regime)">HasUnprivileged</a>(regime) then</line>
<line>                    va&lt;59:56&gt; = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(va&lt;55&gt;, 4);</line>
<line>                else</line>
<line>                    va&lt;59:56&gt; = '0000';</line>
<line>        else</line>
<line>            memattrs.tags = <a link="MemTag_Untagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_Untagged</a>;</line>
<line>        memattrs.xs           = '1';</line>
<line>    memattrs.notagaccess = FALSE;</line>
<line></line>
<line>    fault.level = 0;</line>
<line>    addrtop     = <a link="AArch64.AddrTop.3" file="shared_pseudocode.xml" hover="function: integer AArch64.AddrTop(bit tbid, AccessType acctype, bit tbi)">AArch64.AddrTop</a>(walkparams.tbid, accdesc.acctype, walkparams.tbi);</line>
<line></line>
<line>    if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(va&lt;addrtop:<a link="AArch64.PAMax.0" file="shared_pseudocode.xml" hover="function: integer AArch64.PAMax()">AArch64.PAMax</a>()&gt;) then</line>
<line>        fault.statuscode = <a link="Fault_AddressSize" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AddressSize</a>;</line>
<line>    elsif <a link="AArch64.S1HasAlignmentFault.4" file="shared_pseudocode.xml" hover="function: boolean AArch64.S1HasAlignmentFault(AccessDescriptor accdesc, boolean aligned, bit ntlsmd, MemoryAttributes memattrs)">AArch64.S1HasAlignmentFault</a>(accdesc, aligned, walkparams.ntlsmd, memattrs) then</line>
<line>        fault.statuscode = <a link="Fault_Alignment" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Alignment</a>;</line>
<line></line>
<line>    if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN);</line>
<line>    else</line>
<line>        ipa = <a link="impl-shared.CreateAddressDescriptor.3" file="shared_pseudocode.xml" hover="function: AddressDescriptor CreateAddressDescriptor(bits(64) va, FullAddress pa, MemoryAttributes memattrs)">CreateAddressDescriptor</a>(va_in, oa, memattrs);</line>
<line>        ipa.mecid = AArch64.S1DisabledOutputMECID(walkparams, regime, ipa.paddress.paspace);</line>
<line>        return (fault, ipa);</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_translation/AArch64.S1Translate" mylink="aarch64.translation.vmsa_translation.AArch64.S1Translate" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1Translate()</line>
<line>// =====================</line>
<line>// Translate VA to IPA/PA depending on the regime</line>
<line></line>
<line link="AArch64.S1Translate.5" hover="function: (FaultRecord, AddressDescriptor) AArch64.S1Translate(FaultRecord fault_in, Regime regime, bits(64) va, boolean aligned, AccessDescriptor accdesc)" conts="AArch64.S1Translate">(FaultRecord, AddressDescriptor) <anchor link="AArch64.S1Translate.5" hover="function: (FaultRecord, AddressDescriptor) AArch64.S1Translate(FaultRecord fault_in, Regime regime, bits(64) va, boolean aligned, AccessDescriptor accdesc)">AArch64.S1Translate</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault_in, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime,</line>
<line>                                                     bits(64) va, boolean aligned,</line>
<line>                                                     <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = fault_in;</line>
<line>    // Prepare fault fields in case a fault is detected</line>
<line>    fault.secondstage = FALSE;</line>
<line>    fault.s2fs1walk   = FALSE;</line>
<line></line>
<line>    if !<a link="AArch64.S1Enabled.2" file="shared_pseudocode.xml" hover="function: boolean AArch64.S1Enabled(Regime regime, AccessType acctype)">AArch64.S1Enabled</a>(regime, accdesc.acctype) then</line>
<line>        return <a link="AArch64.S1DisabledOutput.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, AddressDescriptor) AArch64.S1DisabledOutput(FaultRecord fault_in, Regime regime, bits(64) va_in, AccessDescriptor accdesc, boolean aligned)">AArch64.S1DisabledOutput</a>(fault, regime, va, accdesc, aligned);</line>
<line></line>
<line>    walkparams = AArch64.GetS1TTWParams(regime, accdesc.ss, va);</line>
<line></line>
<line>    constant integer s1mintxsz = <a link="AArch64.S1MinTxSZ.4" file="shared_pseudocode.xml" hover="function: integer AArch64.S1MinTxSZ(Regime regime, bit d128, bit ds, TGx tgx)">AArch64.S1MinTxSZ</a>(regime, walkparams.d128,</line>
<line>                                                   walkparams.ds, walkparams.tgx);</line>
<line>    constant integer s1maxtxsz = <a link="AArch64.MaxTxSZ.1" file="shared_pseudocode.xml" hover="function: integer AArch64.MaxTxSZ(TGx tgx)">AArch64.MaxTxSZ</a>(walkparams.tgx);</line>
<line>    if AArch64.S1TxSZFaults(regime, walkparams) then</line>
<line>        fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>        fault.level      = 0;</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN);</line>
<line>    elsif <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(walkparams.txsz) &lt; s1mintxsz then</line>
<line>        walkparams.txsz = s1mintxsz&lt;5:0&gt;;</line>
<line>    elsif <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(walkparams.txsz) &gt; s1maxtxsz then</line>
<line>        walkparams.txsz = s1maxtxsz&lt;5:0&gt;;</line>
<line></line>
<line>    if AArch64.VAIsOutOfRange(va, accdesc.acctype, regime, walkparams) then</line>
<line>        fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>        fault.level      = 0;</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN);</line>
<line></line>
<line>    if accdesc.el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; walkparams.e0pd == '1' then</line>
<line>        fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>        fault.level      = 0;</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN);</line>
<line></line>
<line>    if <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; accdesc.el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; walkparams.nfd == '1' &amp;&amp; accdesc.transactional then</line>
<line>        fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>        fault.level      = 0;</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN);</line>
<line></line>
<line>    if <a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() &amp;&amp; accdesc.el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; walkparams.nfd == '1' &amp;&amp; (</line>
<line>            (accdesc.nonfault &amp;&amp; accdesc.contiguous) ||</line>
<line>            (accdesc.firstfault &amp;&amp; !accdesc.first &amp;&amp; !accdesc.contiguous)) then</line>
<line>        fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>        fault.level      = 0;</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN);</line>
<line></line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> descipaddr;</line>
<line>    <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> walkstate;</line>
<line>    bits(128) descriptor;</line>
<line>    bits(128) new_desc;</line>
<line>    bits(128) mem_desc;</line>
<line>    repeat</line>
<line>        if walkparams.d128 == '1' then</line>
<line>            (fault, descipaddr, walkstate, descriptor) = AArch64.S1Walk(fault, walkparams, va,</line>
<line>                                                                        regime, accdesc, 128);</line>
<line>        else</line>
<line>            (fault, descipaddr, walkstate, descriptor&lt;63:0&gt;) = AArch64.S1Walk(fault, walkparams,</line>
<line>                                                                              va, regime, accdesc,</line>
<line>                                                                              64);</line>
<line>            descriptor&lt;127:64&gt; = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>        if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>            return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN);</line>
<line></line>
<line>        if accdesc.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> then</line>
<line>            // Flag the fetched instruction is from a guarded page</line>
<line>            <a link="impl-aarch64.SetInGuardedPage.1" file="shared_pseudocode.xml" hover="function: SetInGuardedPage(boolean guardedpage)">SetInGuardedPage</a>(walkstate.guardedpage == '1');</line>
<line></line>
<line>        if <a link="AArch64.S1HasAlignmentFault.4" file="shared_pseudocode.xml" hover="function: boolean AArch64.S1HasAlignmentFault(AccessDescriptor accdesc, boolean aligned, bit ntlsmd, MemoryAttributes memattrs)">AArch64.S1HasAlignmentFault</a>(accdesc, aligned, walkparams.ntlsmd,</line>
<line>                                       walkstate.memattrs) then</line>
<line>            fault.statuscode = <a link="Fault_Alignment" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Alignment</a>;</line>
<line></line>
<line>        if fault.statuscode == <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>            fault = AArch64.S1CheckPermissions(fault, regime, walkstate, walkparams, accdesc);</line>
<line></line>
<line>        new_desc = descriptor;</line>
<line>        if walkparams.ha == '1' &amp;&amp; <a link="AArch64.SettingAccessFlagPermitted.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.SettingAccessFlagPermitted(FaultRecord fault)">AArch64.SettingAccessFlagPermitted</a>(fault) then</line>
<line>            // Set descriptor AF bit</line>
<line>            new_desc&lt;10&gt; = '1';</line>
<line></line>
<line>        // If HW update of dirty bit is enabled, the walk state permissions</line>
<line>        // will already reflect a configuration permitting writes.</line>
<line>        // The update of the descriptor occurs only if the descriptor bits in</line>
<line>        // memory do not reflect that and the access instigates a write.</line>
<line></line>
<line>        if (<a link="AArch64.SettingDirtyStatePermitted.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.SettingDirtyStatePermitted(FaultRecord fault)">AArch64.SettingDirtyStatePermitted</a>(fault) &amp;&amp;</line>
<line>                walkparams.ha  == '1' &amp;&amp;</line>
<line>                walkparams.hd  == '1' &amp;&amp;</line>
<line>                (walkparams.pie == '1' || descriptor&lt;51&gt; == '1') &amp;&amp;</line>
<line>                accdesc.write &amp;&amp;</line>
<line>                !(accdesc.acctype IN {<a link="AccessType_AT" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_AT</a>, <a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a>, <a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>})) then</line>
<line>            // Clear descriptor AP[2]/nDirty bit permitting stage 1 writes</line>
<line>            new_desc&lt;7&gt; = '0';</line>
<line></line>
<line>        // Either the access flag was clear or AP[2]/nDirty is set</line>
<line>        if new_desc != descriptor then</line>
<line>            <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> descpaddr;</line>
<line>            descaccess = <a link="impl-shared.CreateAccDescTTEUpdate.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescTTEUpdate(AccessDescriptor accdesc_in)">CreateAccDescTTEUpdate</a>(accdesc);</line>
<line>            if regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>                <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> s2fault;</line>
<line>                s1aarch64 = TRUE;</line>
<line>                s2aligned = TRUE;</line>
<line>                (s2fault, descpaddr) = <a link="AArch64.S2Translate.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, AddressDescriptor) AArch64.S2Translate(FaultRecord fault_in, AddressDescriptor ipa, boolean s1aarch64, boolean aligned, AccessDescriptor accdesc)">AArch64.S2Translate</a>(fault, descipaddr, s1aarch64, s2aligned,</line>
<line>                                                           descaccess);</line>
<line></line>
<line>                if s2fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>                    return (s2fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN);</line>
<line></line>
<line>            else</line>
<line>                descpaddr = descipaddr;</line>
<line>            if walkparams.d128 == '1' then</line>
<line>                (fault, mem_desc) = <a link="AArch64.MemSwapTableDesc.6" file="shared_pseudocode.xml" hover="function: (FaultRecord, bits(N)) AArch64.MemSwapTableDesc(FaultRecord fault_in, bits(N) prev_desc, bits(N) new_desc, bit ee, AccessDescriptor  descaccess, AddressDescriptor descpaddr)">AArch64.MemSwapTableDesc</a>(fault, descriptor, new_desc,</line>
<line>                                                             walkparams.ee, descaccess, descpaddr);</line>
<line>            else</line>
<line>                (fault, mem_desc&lt;63:0&gt;) = <a link="AArch64.MemSwapTableDesc.6" file="shared_pseudocode.xml" hover="function: (FaultRecord, bits(N)) AArch64.MemSwapTableDesc(FaultRecord fault_in, bits(N) prev_desc, bits(N) new_desc, bit ee, AccessDescriptor  descaccess, AddressDescriptor descpaddr)">AArch64.MemSwapTableDesc</a>(fault, descriptor&lt;63:0&gt;,</line>
<line>                                                                   new_desc&lt;63:0&gt;, walkparams.ee,</line>
<line>                                                                   descaccess, descpaddr);</line>
<line>                mem_desc&lt;127:64&gt; = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line></line>
<line>    until new_desc == descriptor || mem_desc == new_desc;</line>
<line></line>
<line>    if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN);</line>
<line></line>
<line>    // Output Address</line>
<line>    oa = <a link="impl-shared.StageOA.4" file="shared_pseudocode.xml" hover="function: FullAddress StageOA(bits(64) ia, bit d128, TGx tgx, TTWState walkstate)">StageOA</a>(va, walkparams.d128, walkparams.tgx, walkstate);</line>
<line>    <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs;</line>
<line>    if (accdesc.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> &amp;&amp;</line>
<line>        (walkstate.memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> || !<a link="AArch64.S1ICacheEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.S1ICacheEnabled(Regime regime)">AArch64.S1ICacheEnabled</a>(regime))) then</line>
<line>        // Treat memory attributes as Normal Non-Cacheable</line>
<line>        memattrs = <a link="impl-shared.NormalNCMemAttr.0" file="shared_pseudocode.xml" hover="function: MemoryAttributes NormalNCMemAttr()">NormalNCMemAttr</a>();</line>
<line>        memattrs.xs = walkstate.memattrs.xs;</line>
<line>    elsif (accdesc.acctype != <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> &amp;&amp; !<a link="AArch64.S1DCacheEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.S1DCacheEnabled(Regime regime)">AArch64.S1DCacheEnabled</a>(regime) &amp;&amp;</line>
<line>             walkstate.memattrs.memtype == <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>) then</line>
<line>        // Treat memory attributes as Normal Non-Cacheable</line>
<line>        memattrs = <a link="impl-shared.NormalNCMemAttr.0" file="shared_pseudocode.xml" hover="function: MemoryAttributes NormalNCMemAttr()">NormalNCMemAttr</a>();</line>
<line>        memattrs.xs = walkstate.memattrs.xs;</line>
<line></line>
<line>        // The effect of SCTLR_ELx.C when '0' is Constrained UNPREDICTABLE</line>
<line>        // on the Tagged attribute</line>
<line>        if (<a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() &amp;&amp; walkstate.memattrs.tags == <a link="MemTag_AllocationTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_AllocationTagged</a> &amp;&amp;</line>
<line>            !<a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_S1CTAGGED" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_S1CTAGGED</a>)) then</line>
<line>            memattrs.tags = <a link="MemTag_Untagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_Untagged</a>;</line>
<line>    else</line>
<line>        memattrs = walkstate.memattrs;</line>
<line></line>
<line>    // Shareability value of stage 1 translation subject to stage 2 is IMPLEMENTATION DEFINED</line>
<line>    // to be either effective value or descriptor value</line>
<line>    if (regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.VM == '1' &amp;&amp;</line>
<line>            !(boolean IMPLEMENTATION_DEFINED "Apply effective shareability at stage 1")) then</line>
<line>        memattrs.shareability = walkstate.memattrs.shareability;</line>
<line>    else</line>
<line>        memattrs.shareability = <a link="impl-shared.EffectiveShareability.1" file="shared_pseudocode.xml" hover="function: Shareability EffectiveShareability(MemoryAttributes memattrs)">EffectiveShareability</a>(memattrs);</line>
<line></line>
<line>    if accdesc.ls64 &amp;&amp; memattrs.memtype == <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a> then</line>
<line>        if memattrs.inner.attrs != <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a> || memattrs.outer.attrs != <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a> then</line>
<line>            fault.statuscode = <a link="Fault_Exclusive" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Exclusive</a>;</line>
<line>            return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN);</line>
<line></line>
<line>    ipa = <a link="impl-shared.CreateAddressDescriptor.3" file="shared_pseudocode.xml" hover="function: AddressDescriptor CreateAddressDescriptor(bits(64) va, FullAddress pa, MemoryAttributes memattrs)">CreateAddressDescriptor</a>(va, oa, memattrs);</line>
<line>    ipa.s1assured = walkstate.s1assured;</line>
<line>    varange   = <a link="AArch64.GetVARange.1" file="shared_pseudocode.xml" hover="function: VARange AArch64.GetVARange(bits(64) va)">AArch64.GetVARange</a>(va);</line>
<line>    ipa.mecid = AArch64.S1OutputMECID(walkparams, regime, varange, ipa.paddress.paspace,</line>
<line>                                      descriptor);</line>
<line>    return (fault, ipa);</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_translation/AArch64.S2Translate" mylink="aarch64.translation.vmsa_translation.AArch64.S2Translate" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S2Translate()</line>
<line>// =====================</line>
<line>// Translate stage 1 IPA to PA and combine memory attributes</line>
<line></line>
<line link="AArch64.S2Translate.5" hover="function: (FaultRecord, AddressDescriptor) AArch64.S2Translate(FaultRecord fault_in, AddressDescriptor ipa, boolean s1aarch64, boolean aligned, AccessDescriptor accdesc)" conts="AArch64.S2Translate">(FaultRecord, AddressDescriptor) <anchor link="AArch64.S2Translate.5" hover="function: (FaultRecord, AddressDescriptor) AArch64.S2Translate(FaultRecord fault_in, AddressDescriptor ipa, boolean s1aarch64, boolean aligned, AccessDescriptor accdesc)">AArch64.S2Translate</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault_in, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> ipa,</line>
<line>                                                     boolean s1aarch64, boolean aligned,</line>
<line>                                                     <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line></line>
<line>    walkparams = AArch64.GetS2TTWParams(accdesc.ss, ipa.paddress.paspace, s1aarch64);</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = fault_in;</line>
<line>    boolean s2fs1mro;</line>
<line></line>
<line>    // Prepare fault fields in case a fault is detected</line>
<line>    fault.statuscode  = <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a>; // Ignore any faults from stage 1</line>
<line>    fault.secondstage = TRUE;</line>
<line>    fault.s2fs1walk   = accdesc.acctype == <a link="AccessType_TTW" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_TTW</a>;</line>
<line>    fault.ipaddress   = ipa.paddress;</line>
<line></line>
<line>    if walkparams.vm != '1' then</line>
<line>        // Stage 2 translation is disabled</line>
<line>        return (fault, ipa);</line>
<line></line>
<line>    constant integer s2mintxsz = <a link="AArch64.S2MinTxSZ.4" file="shared_pseudocode.xml" hover="function: integer AArch64.S2MinTxSZ(bit d128, bit ds, TGx tgx, boolean s1aarch64)">AArch64.S2MinTxSZ</a>(walkparams.d128, walkparams.ds,</line>
<line>                                                   walkparams.tgx, s1aarch64);</line>
<line>    constant integer s2maxtxsz = <a link="AArch64.MaxTxSZ.1" file="shared_pseudocode.xml" hover="function: integer AArch64.MaxTxSZ(TGx tgx)">AArch64.MaxTxSZ</a>(walkparams.tgx);</line>
<line>    if AArch64.S2TxSZFaults(walkparams, s1aarch64) then</line>
<line>        fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>        fault.level      = 0;</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN);</line>
<line>    elsif <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(walkparams.txsz) &lt; s2mintxsz then</line>
<line>        walkparams.txsz = s2mintxsz&lt;5:0&gt;;</line>
<line>    elsif <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(walkparams.txsz) &gt; s2maxtxsz then</line>
<line>        walkparams.txsz = s2maxtxsz&lt;5:0&gt;;</line>
<line></line>
<line>    if (walkparams.d128 == '0' &amp;&amp;</line>
<line>        (AArch64.S2InvalidSL(walkparams) || AArch64.S2InconsistentSL(walkparams))) then</line>
<line>        fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>        fault.level      = 0;</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN);</line>
<line></line>
<line>    if AArch64.IPAIsOutOfRange(ipa.paddress.address, walkparams) then</line>
<line>        fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>        fault.level      = 0;</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN);</line>
<line></line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> descpaddr;</line>
<line>    <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> walkstate;</line>
<line>    bits(128) descriptor;</line>
<line>    bits(128) new_desc;</line>
<line>    bits(128) mem_desc;</line>
<line>    repeat</line>
<line>        if walkparams.d128 == '1' then</line>
<line>            (fault, descpaddr, walkstate, descriptor) = AArch64.S2Walk(fault, ipa, walkparams,</line>
<line>                                                                       accdesc, 128);</line>
<line>        else</line>
<line>            (fault, descpaddr, walkstate, descriptor&lt;63:0&gt;) = AArch64.S2Walk(fault, ipa,</line>
<line>                                                                             walkparams, accdesc,</line>
<line>                                                                             64);</line>
<line>            descriptor&lt;127:64&gt; = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>        if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>            return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN);</line>
<line></line>
<line>        if <a link="AArch64.S2HasAlignmentFault.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.S2HasAlignmentFault(AccessDescriptor accdesc, boolean aligned, MemoryAttributes memattrs)">AArch64.S2HasAlignmentFault</a>(accdesc, aligned, walkstate.memattrs) then</line>
<line>            fault.statuscode = <a link="Fault_Alignment" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Alignment</a>;</line>
<line></line>
<line>        if fault.statuscode == <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>            (fault, s2fs1mro) = AArch64.S2CheckPermissions(fault, walkstate, walkparams, ipa,</line>
<line>                                                           accdesc);</line>
<line></line>
<line>        new_desc = descriptor;</line>
<line>        if walkparams.ha == '1' &amp;&amp; <a link="AArch64.SettingAccessFlagPermitted.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.SettingAccessFlagPermitted(FaultRecord fault)">AArch64.SettingAccessFlagPermitted</a>(fault) then</line>
<line>            // Set descriptor AF bit</line>
<line>            new_desc&lt;10&gt; = '1';</line>
<line></line>
<line>        // If HW update of dirty bit is enabled, the walk state permissions</line>
<line>        // will already reflect a configuration permitting writes.</line>
<line>        // The update of the descriptor occurs only if the descriptor bits in</line>
<line>        // memory do not reflect that and the access instigates a write.</line>
<line></line>
<line>        if (<a link="AArch64.SettingDirtyStatePermitted.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.SettingDirtyStatePermitted(FaultRecord fault)">AArch64.SettingDirtyStatePermitted</a>(fault) &amp;&amp;</line>
<line>                walkparams.ha  == '1' &amp;&amp;</line>
<line>                walkparams.hd  == '1' &amp;&amp;</line>
<line>                (walkparams.s2pie == '1' || descriptor&lt;51&gt; == '1') &amp;&amp;</line>
<line>                accdesc.write &amp;&amp;</line>
<line>                !(accdesc.acctype IN {<a link="AccessType_AT" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_AT</a>, <a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a>, <a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>})) then</line>
<line>            // Set descriptor S2AP[1]/Dirty bit permitting stage 2 writes</line>
<line>            new_desc&lt;7&gt; = '1';</line>
<line></line>
<line>        // Either the access flag was clear or S2AP[1]/Dirty is clear</line>
<line>        if new_desc != descriptor then</line>
<line>            <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> descaccess = <a link="impl-shared.CreateAccDescTTEUpdate.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescTTEUpdate(AccessDescriptor accdesc_in)">CreateAccDescTTEUpdate</a>(accdesc);</line>
<line>            if walkparams.d128 == '1' then</line>
<line>                (fault, mem_desc) = <a link="AArch64.MemSwapTableDesc.6" file="shared_pseudocode.xml" hover="function: (FaultRecord, bits(N)) AArch64.MemSwapTableDesc(FaultRecord fault_in, bits(N) prev_desc, bits(N) new_desc, bit ee, AccessDescriptor  descaccess, AddressDescriptor descpaddr)">AArch64.MemSwapTableDesc</a>(fault, descriptor, new_desc,</line>
<line>                                                             walkparams.ee, descaccess,</line>
<line>                                                             descpaddr);</line>
<line>            else</line>
<line>                (fault, mem_desc&lt;63:0&gt;) = <a link="AArch64.MemSwapTableDesc.6" file="shared_pseudocode.xml" hover="function: (FaultRecord, bits(N)) AArch64.MemSwapTableDesc(FaultRecord fault_in, bits(N) prev_desc, bits(N) new_desc, bit ee, AccessDescriptor  descaccess, AddressDescriptor descpaddr)">AArch64.MemSwapTableDesc</a>(fault, descriptor&lt;63:0&gt;,</line>
<line>                                                                   new_desc&lt;63:0&gt;, walkparams.ee,</line>
<line>                                                                   descaccess, descpaddr);</line>
<line>                mem_desc&lt;127:64&gt; = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line></line>
<line>    until new_desc == descriptor || mem_desc == new_desc;</line>
<line></line>
<line>    if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN);</line>
<line></line>
<line>    ipa_64 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(ipa.paddress.address, 64);</line>
<line>    // Output Address</line>
<line>    oa = <a link="impl-shared.StageOA.4" file="shared_pseudocode.xml" hover="function: FullAddress StageOA(bits(64) ia, bit d128, TGx tgx, TTWState walkstate)">StageOA</a>(ipa_64, walkparams.d128, walkparams.tgx, walkstate);</line>
<line>    <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> s2_memattrs;</line>
<line>    if ((accdesc.acctype == <a link="AccessType_TTW" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_TTW</a> &amp;&amp;</line>
<line>            walkstate.memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> &amp;&amp; walkparams.ptw == '0') ||</line>
<line>        (accdesc.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> &amp;&amp;</line>
<line>            (walkstate.memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> || HCR_EL2.ID == '1')) ||</line>
<line>        (accdesc.acctype != <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> &amp;&amp;</line>
<line>             walkstate.memattrs.memtype == <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a> &amp;&amp; HCR_EL2.CD == '1')) then</line>
<line>        // Treat memory attributes as Normal Non-Cacheable</line>
<line>        s2_memattrs = <a link="impl-shared.NormalNCMemAttr.0" file="shared_pseudocode.xml" hover="function: MemoryAttributes NormalNCMemAttr()">NormalNCMemAttr</a>();</line>
<line>        s2_memattrs.xs = walkstate.memattrs.xs;</line>
<line>    else</line>
<line>        s2_memattrs = walkstate.memattrs;</line>
<line></line>
<line>    if accdesc.ls64 &amp;&amp; s2_memattrs.memtype == <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a> then</line>
<line>        if s2_memattrs.inner.attrs != <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a> || s2_memattrs.outer.attrs != <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a> then</line>
<line>            fault.statuscode = <a link="Fault_Exclusive" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Exclusive</a>;</line>
<line>            return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN);</line>
<line></line>
<line>    s2aarch64 = TRUE;</line>
<line>    <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs;</line>
<line>    if walkparams.fwb == '0' then</line>
<line>        memattrs = <a link="impl-shared.S2CombineS1MemAttrs.3" file="shared_pseudocode.xml" hover="function: MemoryAttributes S2CombineS1MemAttrs(MemoryAttributes s1_memattrs, MemoryAttributes s2_memattrs, boolean s2aarch64)">S2CombineS1MemAttrs</a>(ipa.memattrs, s2_memattrs, s2aarch64);</line>
<line>    else</line>
<line>        memattrs = s2_memattrs;</line>
<line></line>
<line>    pa = <a link="impl-shared.CreateAddressDescriptor.3" file="shared_pseudocode.xml" hover="function: AddressDescriptor CreateAddressDescriptor(bits(64) va, FullAddress pa, MemoryAttributes memattrs)">CreateAddressDescriptor</a>(ipa.vaddress, oa, memattrs);</line>
<line>    pa.s2fs1mro = s2fs1mro;</line>
<line>    pa.mecid = AArch64.S2OutputMECID(walkparams, pa.paddress.paspace, descriptor);</line>
<line>    return (fault, pa);</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_translation/AArch64.SettingAccessFlagPermitted" mylink="aarch64.translation.vmsa_translation.AArch64.SettingAccessFlagPermitted" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.SettingAccessFlagPermitted()</line>
<line>// ====================================</line>
<line>// Determine whether the access flag could be set by HW given the fault status</line>
<line></line>
<line link="AArch64.SettingAccessFlagPermitted.1" hover="function: boolean AArch64.SettingAccessFlagPermitted(FaultRecord fault)" conts="AArch64.SettingAccessFlagPermitted">boolean <anchor link="AArch64.SettingAccessFlagPermitted.1" hover="function: boolean AArch64.SettingAccessFlagPermitted(FaultRecord fault)">AArch64.SettingAccessFlagPermitted</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    if fault.statuscode == <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>        return TRUE;</line>
<line>    elsif fault.statuscode IN {<a link="Fault_Alignment" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Alignment</a>, <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>} then</line>
<line>        return <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_AFUPDATE" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_AFUPDATE</a>);</line>
<line>    else</line>
<line>        return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_translation/AArch64.SettingDirtyStatePermitted" mylink="aarch64.translation.vmsa_translation.AArch64.SettingDirtyStatePermitted" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.SettingDirtyStatePermitted()</line>
<line>// ====================================</line>
<line>// Determine whether the dirty state could be set by HW given the fault status</line>
<line></line>
<line link="AArch64.SettingDirtyStatePermitted.1" hover="function: boolean AArch64.SettingDirtyStatePermitted(FaultRecord fault)" conts="AArch64.SettingDirtyStatePermitted">boolean <anchor link="AArch64.SettingDirtyStatePermitted.1" hover="function: boolean AArch64.SettingDirtyStatePermitted(FaultRecord fault)">AArch64.SettingDirtyStatePermitted</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    if fault.statuscode == <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>        return TRUE;</line>
<line>    elsif fault.statuscode == <a link="Fault_Alignment" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Alignment</a> then</line>
<line>        return <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_DBUPDATE" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_DBUPDATE</a>);</line>
<line>    else</line>
<line>        return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_translation/AArch64.TranslateAddress" mylink="aarch64.translation.vmsa_translation.AArch64.TranslateAddress" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.TranslateAddress()</line>
<line>// ==========================</line>
<line>// Main entry point for translating an address</line>
<line></line>
<line link="AArch64.TranslateAddress.4" hover="function: AddressDescriptor AArch64.TranslateAddress(bits(64) va, AccessDescriptor accdesc, boolean aligned, integer size)" conts="AArch64.TranslateAddress">AddressDescriptor <anchor link="AArch64.TranslateAddress.4" hover="function: AddressDescriptor AArch64.TranslateAddress(bits(64) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch64.TranslateAddress</anchor>(bits(64) va, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc,</line>
<line>                                           boolean aligned, integer size)</line>
<line>    if (SPESampleInFlight &amp;&amp; !(accdesc.acctype IN {<a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a>,</line>
<line>                                                   <a link="AccessType_SPE" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_SPE</a>})) then</line>
<line>        <a link="impl-aarch64.SPEStartCounter.1" file="shared_pseudocode.xml" hover="function: SPEStartCounter(integer counter_index)">SPEStartCounter</a>(<a link="SPECounterPosTranslationLatency" file="shared_pseudocode.xml" hover="constant integer SPECounterPosTranslationLatency = 2">SPECounterPosTranslationLatency</a>);</line>
<line></line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> result = <a link="AArch64.FullTranslate.3" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch64.FullTranslate(bits(64) va, AccessDescriptor accdesc, boolean aligned)">AArch64.FullTranslate</a>(va, accdesc, aligned);</line>
<line></line>
<line>    if !<a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(result) &amp;&amp; accdesc.acctype != <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> then</line>
<line>        result.fault = <a link="AArch64.CheckDebug.3" file="shared_pseudocode.xml" hover="function: FaultRecord AArch64.CheckDebug(bits(64) vaddress, AccessDescriptor accdesc, integer size)">AArch64.CheckDebug</a>(va, accdesc, size);</line>
<line></line>
<line>    if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() &amp;&amp; !<a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(result) &amp;&amp; (</line>
<line>            accdesc.acctype != <a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a> ||</line>
<line>            boolean IMPLEMENTATION_DEFINED "GPC <a link="Fault" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault</a> on DC operations") then</line>
<line>        result.fault.gpcf = <a link="impl-shared.GranuleProtectionCheck.2" file="shared_pseudocode.xml" hover="function: GPCFRecord GranuleProtectionCheck(AddressDescriptor addrdesc, AccessDescriptor accdesc)">GranuleProtectionCheck</a>(result, accdesc);</line>
<line></line>
<line>        if result.fault.gpcf.gpf != <a link="GPCF_None" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_None</a> then</line>
<line>            result.fault.statuscode = <a link="Fault_GPCFOnOutput" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_GPCFOnOutput</a>;</line>
<line>            result.fault.paddress   = result.paddress;</line>
<line></line>
<line>    if !<a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(result) &amp;&amp; accdesc.acctype == <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a> then</line>
<line>        result.fault = <a link="AArch64.CheckDebug.3" file="shared_pseudocode.xml" hover="function: FaultRecord AArch64.CheckDebug(bits(64) vaddress, AccessDescriptor accdesc, integer size)">AArch64.CheckDebug</a>(va, accdesc, size);</line>
<line></line>
<line>    if (SPESampleInFlight &amp;&amp; !(accdesc.acctype IN {<a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a>,</line>
<line>                                                   <a link="AccessType_SPE" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_SPE</a>})) then</line>
<line>        <a link="impl-aarch64.SPEStopCounter.1" file="shared_pseudocode.xml" hover="function: SPEStopCounter(integer counter_index)">SPEStopCounter</a>(<a link="SPECounterPosTranslationLatency" file="shared_pseudocode.xml" hover="constant integer SPECounterPosTranslationLatency = 2">SPECounterPosTranslationLatency</a>);</line>
<line></line>
<line>    // Update virtual address for abort functions</line>
<line>    result.vaddress = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(va, 64);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_ttentry/AArch64.BlockDescSupported" mylink="aarch64.translation.vmsa_ttentry.AArch64.BlockDescSupported" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.BlockDescSupported()</line>
<line>// ============================</line>
<line>// Determine whether a block descriptor is valid for the given granule size</line>
<line>// and level</line>
<line></line>
<line link="AArch64.BlockDescSupported.4" hover="function: boolean AArch64.BlockDescSupported(bit d128, bit ds, TGx tgx, integer level)" conts="AArch64.BlockDescSupported">boolean <anchor link="AArch64.BlockDescSupported.4" hover="function: boolean AArch64.BlockDescSupported(bit d128, bit ds, TGx tgx, integer level)">AArch64.BlockDescSupported</anchor>(bit d128, bit ds, <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tgx, integer level)</line>
<line>    case tgx of</line>
<line>        when <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>  return ((level == 0 &amp;&amp; (ds == '1' || d128 == '1')) ||</line>
<line>                               level == 1 ||</line>
<line>                               level == 2);</line>
<line>        when <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a> return ((level == 1 &amp;&amp; (ds == '1' || d128 == '1')) ||</line>
<line>                               level == 2);</line>
<line>        when <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a> return ((level == 1 &amp;&amp; (d128 == '1' || <a link="AArch64.PAMax.0" file="shared_pseudocode.xml" hover="function: integer AArch64.PAMax()">AArch64.PAMax</a>() &gt;= 52)) ||</line>
<line>                               level == 2);</line>
<line>    return FALSE;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_ttentry/AArch64.BlocknTFaults" mylink="aarch64.translation.vmsa_ttentry.AArch64.BlocknTFaults" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.BlocknTFaults()</line>
<line>// =======================</line>
<line>// Identify whether the nT bit in a block descriptor is effectively set</line>
<line>// causing a translation fault</line>
<line></line>
<line link="AArch64.BlocknTFaults.2" hover="function: boolean AArch64.BlocknTFaults(bit d128, bits(N) descriptor)" conts="AArch64.BlocknTFaults">boolean <anchor link="AArch64.BlocknTFaults.2" hover="function: boolean AArch64.BlocknTFaults(bit d128, bits(N) descriptor)">AArch64.BlocknTFaults</anchor>(bit d128, bits(N) descriptor)</line>
<line>    bit nT;</line>
<line>    if !<a link="impl-shared.HaveBlockBBM.0" file="shared_pseudocode.xml" hover="function: boolean HaveBlockBBM()">HaveBlockBBM</a>() then</line>
<line>        return FALSE;</line>
<line>    nT = if d128 == '1' then descriptor&lt;6&gt; else descriptor&lt;16&gt;;</line>
<line>    bbm_level = <a link="AArch64.BlockBBMSupportLevel.0" file="shared_pseudocode.xml" hover="function: integer AArch64.BlockBBMSupportLevel()">AArch64.BlockBBMSupportLevel</a>();</line>
<line>    nT_faults = (boolean IMPLEMENTATION_DEFINED</line>
<line>                 "BBM level 1 or 2 support nT bit causes Translation <a link="Fault" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault</a>");</line>
<line></line>
<line>    return bbm_level IN {1, 2} &amp;&amp; nT == '1' &amp;&amp; nT_faults;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_ttentry/AArch64.ContiguousBit" mylink="aarch64.translation.vmsa_ttentry.AArch64.ContiguousBit" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ContiguousBit()</line>
<line>// =======================</line>
<line>// Get the value of the contiguous bit</line>
<line></line>
<line link="AArch64.ContiguousBit.4" hover="function: bit AArch64.ContiguousBit(TGx tgx, bit d128, integer level, bits(N) descriptor)" conts="AArch64.ContiguousBit">bit <anchor link="AArch64.ContiguousBit.4" hover="function: bit AArch64.ContiguousBit(TGx tgx, bit d128, integer level, bits(N) descriptor)">AArch64.ContiguousBit</anchor>(<a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tgx, bit d128, integer level, bits(N) descriptor)</line>
<line>    if d128 == '1' then</line>
<line>        return descriptor&lt;111&gt;;</line>
<line>    // When using TGx 64KB and FEAT_LPA is implememted,</line>
<line>    // the Contiguous bit is RES0 for Block descriptors at level 1</line>
<line></line>
<line>    if tgx == <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a> &amp;&amp; level == 1 then</line>
<line>        return '0'; // RES0</line>
<line></line>
<line>    // When the effective value of TCR_ELx.DS is '1',</line>
<line>    // the Contiguous bit is RES0 for all the following:</line>
<line>    //      * For TGx 4KB, Block descriptors at level 0</line>
<line>    //      * For TGx 16KB, Block descriptors at level 1</line>
<line></line>
<line>    if tgx == <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a> &amp;&amp; level == 1 then</line>
<line>        return '0'; // RES0</line>
<line></line>
<line>    if tgx == <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>  &amp;&amp; level == 0 then</line>
<line>        return '0'; // RES0</line>
<line></line>
<line>    return descriptor&lt;52&gt;;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_ttentry/AArch64.DecodeDescriptorType" mylink="aarch64.translation.vmsa_ttentry.AArch64.DecodeDescriptorType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.DecodeDescriptorType()</line>
<line>// ==============================</line>
<line>// Determine whether the descriptor is a page, block or table</line>
<line></line>
<line link="AArch64.DecodeDescriptorType.5" hover="function: DescriptorType AArch64.DecodeDescriptorType(bits(N) descriptor, bit d128, bit ds, TGx tgx, integer level)" conts="AArch64.DecodeDescriptorType">DescriptorType <anchor link="AArch64.DecodeDescriptorType.5" hover="function: DescriptorType AArch64.DecodeDescriptorType(bits(N) descriptor, bit d128, bit ds, TGx tgx, integer level)">AArch64.DecodeDescriptorType</anchor>(bits(N) descriptor, bit d128, bit ds,</line>
<line>                                            <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tgx, integer level)</line>
<line>    if descriptor&lt;0&gt; == '0' then</line>
<line>        return <a link="DescriptorType_Invalid" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Invalid</a>;</line>
<line>    elsif d128 == '1' then</line>
<line>        bits(2) skl = descriptor&lt;110:109&gt;;</line>
<line>        if tgx IN {<a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a>, <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a>} &amp;&amp; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(skl) == 3 then</line>
<line>            return <a link="DescriptorType_Invalid" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Invalid</a>;</line>
<line></line>
<line>        integer effective_level = level + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(skl);</line>
<line>        if effective_level &gt; <a link="FINAL_LEVEL" file="shared_pseudocode.xml" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</a> then</line>
<line>            return <a link="DescriptorType_Invalid" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Invalid</a>;</line>
<line>        elsif effective_level == <a link="FINAL_LEVEL" file="shared_pseudocode.xml" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</a> then</line>
<line>            return <a link="DescriptorType_Leaf" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Leaf</a>;</line>
<line>        else</line>
<line>            return <a link="DescriptorType_Table" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Table</a>;</line>
<line>    else</line>
<line>        if descriptor&lt;1&gt; == '1' then</line>
<line>            if level == <a link="FINAL_LEVEL" file="shared_pseudocode.xml" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</a> then</line>
<line>                return <a link="DescriptorType_Leaf" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Leaf</a>;</line>
<line>            else</line>
<line>                return <a link="DescriptorType_Table" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Table</a>;</line>
<line>        elsif descriptor&lt;1&gt; == '0' then</line>
<line>            if <a link="AArch64.BlockDescSupported.4" file="shared_pseudocode.xml" hover="function: boolean AArch64.BlockDescSupported(bit d128, bit ds, TGx tgx, integer level)">AArch64.BlockDescSupported</a>(d128, ds, tgx, level) then</line>
<line>                return <a link="DescriptorType_Leaf" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Leaf</a>;</line>
<line>            else</line>
<line>                return <a link="DescriptorType_Invalid" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Invalid</a>;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_ttentry/AArch64.S1ApplyOutputPerms" mylink="aarch64.translation.vmsa_ttentry.AArch64.S1ApplyOutputPerms" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1ApplyOutputPerms()</line>
<line>// ============================</line>
<line>// Apply output permissions encoded in stage 1 page/block descriptors</line>
<line></line>
<line><a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> AArch64.S1ApplyOutputPerms(<a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> permissions_in, bits(N) descriptor,</line>
<line>                                       <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, S1TTWParams walkparams)</line>
<line>    <a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> permissions = permissions_in;</line>
<line></line>
<line>    bits (4) pi_index;</line>
<line>    if walkparams.pie == '1' then</line>
<line>        if walkparams.d128 == '1' then</line>
<line>            pi_index = descriptor&lt;118:115&gt;;</line>
<line>        else</line>
<line>            pi_index = descriptor&lt;54:53&gt;:descriptor&lt;51&gt;:descriptor&lt;6&gt;;</line>
<line>        bit_index          = 4 * <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(pi_index);</line>
<line>        permissions.ppi    = walkparams.pir&lt;bit_index+3:bit_index&gt;;</line>
<line>        permissions.upi    = walkparams.pire0&lt;bit_index+3:bit_index&gt;;</line>
<line>        permissions.ndirty = descriptor&lt;7&gt;;</line>
<line>    else</line>
<line>        if regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; walkparams.nv1 == '1' then</line>
<line>            permissions.ap&lt;2:1&gt; = descriptor&lt;7&gt;:'0';</line>
<line>            permissions.pxn     = descriptor&lt;54&gt;;</line>
<line>        elsif <a link="impl-shared.HasUnprivileged.1" file="shared_pseudocode.xml" hover="function: boolean HasUnprivileged(Regime regime)">HasUnprivileged</a>(regime) then</line>
<line>            permissions.ap&lt;2:1&gt; = descriptor&lt;7:6&gt;;</line>
<line>            permissions.uxn     = descriptor&lt;54&gt;;</line>
<line>            permissions.pxn     = descriptor&lt;53&gt;;</line>
<line>        else</line>
<line>            permissions.ap&lt;2:1&gt; = descriptor&lt;7&gt;:'1';</line>
<line>            permissions.xn      = descriptor&lt;54&gt;;</line>
<line>        // Descriptors marked with DBM set have the effective value of AP[2] cleared.</line>
<line>        // This implies no Permission faults caused by lack of write permissions are</line>
<line>        // reported, and the Dirty bit can be set.</line>
<line>        if walkparams.ha == '1' &amp;&amp; walkparams.hd == '1' &amp;&amp; descriptor&lt;51&gt; == '1' then</line>
<line>            permissions.ap&lt;2&gt; = '0';</line>
<line></line>
<line>    boolean poe   = <a link="AArch64.S1POEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.S1POEnabled(Regime regime)">AArch64.S1POEnabled</a>(regime);</line>
<line>    boolean e0poe = <a link="impl-shared.HasUnprivileged.1" file="shared_pseudocode.xml" hover="function: boolean HasUnprivileged(Regime regime)">HasUnprivileged</a>(regime) &amp;&amp; <a link="AArch64.S1E0POEnabled.2" file="shared_pseudocode.xml" hover="function: boolean AArch64.S1E0POEnabled(Regime regime, bit nv1)">AArch64.S1E0POEnabled</a>(regime, walkparams.nv1);</line>
<line></line>
<line>    if poe || e0poe then</line>
<line>        if walkparams.d128 == '1' then</line>
<line>            permissions.po_index = descriptor&lt;124:121&gt;;</line>
<line>        else</line>
<line>            permissions.po_index = '0':descriptor&lt;62:60&gt;;</line>
<line></line>
<line>    return permissions;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_ttentry/AArch64.S1ApplyTablePerms" mylink="aarch64.translation.vmsa_ttentry.AArch64.S1ApplyTablePerms" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1ApplyTablePerms()</line>
<line>// ===========================</line>
<line>// Apply hierarchical permissions encoded in stage 1 table descriptors</line>
<line></line>
<line><a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> AArch64.S1ApplyTablePerms(<a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> permissions_in, bits(N) descriptor,</line>
<line>                                      <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, S1TTWParams walkparams)</line>
<line>    <a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> permissions = permissions_in;</line>
<line>    bits(2) ap_table;</line>
<line>    bit pxn_table;</line>
<line>    bit uxn_table;</line>
<line>    bit xn_table;</line>
<line>    if regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; walkparams.nv1 == '1' then</line>
<line>        if walkparams.d128 == '1' then</line>
<line>            ap_table  = descriptor&lt;126&gt;:'0';</line>
<line>            pxn_table = descriptor&lt;124&gt;;</line>
<line>        else</line>
<line>            ap_table  = descriptor&lt;62&gt;:'0';</line>
<line>            pxn_table = descriptor&lt;60&gt;;</line>
<line>        permissions.ap_table  = permissions.ap_table  OR ap_table;</line>
<line>        permissions.pxn_table = permissions.pxn_table OR pxn_table;</line>
<line></line>
<line>    elsif <a link="impl-shared.HasUnprivileged.1" file="shared_pseudocode.xml" hover="function: boolean HasUnprivileged(Regime regime)">HasUnprivileged</a>(regime) then</line>
<line>        if walkparams.d128 == '1' then</line>
<line>            ap_table  = descriptor&lt;126:125&gt;;</line>
<line>            uxn_table = descriptor&lt;124&gt;;</line>
<line>            pxn_table = descriptor&lt;123&gt;;</line>
<line>        else</line>
<line>            ap_table  = descriptor&lt;62:61&gt;;</line>
<line>            uxn_table = descriptor&lt;60&gt;;</line>
<line>            pxn_table = descriptor&lt;59&gt;;</line>
<line>        permissions.ap_table  = permissions.ap_table  OR ap_table;</line>
<line>        permissions.uxn_table = permissions.uxn_table OR uxn_table;</line>
<line>        permissions.pxn_table = permissions.pxn_table OR pxn_table;</line>
<line>    else</line>
<line>        if walkparams.d128 == '1' then</line>
<line>            ap_table = descriptor&lt;126&gt;:'0';</line>
<line>            xn_table = descriptor&lt;124&gt;;</line>
<line>        else</line>
<line>            ap_table = descriptor&lt;62&gt;:'0';</line>
<line>            xn_table = descriptor&lt;60&gt;;</line>
<line>        permissions.ap_table = permissions.ap_table OR ap_table;</line>
<line>        permissions.xn_table = permissions.xn_table OR xn_table;</line>
<line></line>
<line>    return permissions;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_ttentry/AArch64.S2ApplyOutputPerms" mylink="aarch64.translation.vmsa_ttentry.AArch64.S2ApplyOutputPerms" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S2ApplyOutputPerms()</line>
<line>// ============================</line>
<line>// Apply output permissions encoded in stage 2 page/block descriptors</line>
<line></line>
<line><a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> AArch64.S2ApplyOutputPerms(bits(N) descriptor, S2TTWParams walkparams)</line>
<line>    <a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> permissions;</line>
<line>    bits(4) s2pi_index;</line>
<line>    if walkparams.s2pie == '1' then</line>
<line>        if walkparams.d128 == '1' then</line>
<line>            s2pi_index = descriptor&lt;118:115&gt;;</line>
<line>        else</line>
<line>            s2pi_index = descriptor&lt;54:53,51,6&gt;;</line>
<line>        bit_index = 4 * <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(s2pi_index);</line>
<line>        permissions.s2pi = walkparams.s2pir&lt;bit_index+3 : bit_index&gt;;</line>
<line>        permissions.s2dirty = descriptor&lt;7&gt;;</line>
<line>    else</line>
<line>        permissions.s2ap = descriptor&lt;7:6&gt;;</line>
<line>        if walkparams.d128 == '1' then</line>
<line>            permissions.s2xn = descriptor&lt;118&gt;;</line>
<line>        else</line>
<line>            permissions.s2xn = descriptor&lt;54&gt;;</line>
<line></line>
<line>        if <a link="impl-shared.HaveExtendedExecuteNeverExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveExtendedExecuteNeverExt()">HaveExtendedExecuteNeverExt</a>() then</line>
<line>            if walkparams.d128 == '1' then</line>
<line>                permissions.s2xnx = descriptor&lt;117&gt;;</line>
<line>            else</line>
<line>                permissions.s2xnx = descriptor&lt;53&gt;;</line>
<line>        else</line>
<line>            permissions.s2xnx = '0';</line>
<line></line>
<line>        // Descriptors marked with DBM set have the effective value of S2AP[1] set.</line>
<line>        // This implies no Permission faults caused by lack of write permissions are</line>
<line>        // reported, and the Dirty bit can be set.</line>
<line>        bit desc_dbm;</line>
<line>        if walkparams.d128 == '1' then</line>
<line>            desc_dbm = descriptor&lt;115&gt;;</line>
<line>        else</line>
<line>            desc_dbm = descriptor&lt;51&gt;;</line>
<line>        if walkparams.ha == '1' &amp;&amp; walkparams.hd == '1' &amp;&amp; desc_dbm == '1' then</line>
<line>            permissions.s2ap&lt;1&gt; = '1';</line>
<line>    if walkparams.s2pie == '1' &amp;&amp; <a link="impl-shared.HaveS2POExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveS2POExt()">HaveS2POExt</a>() &amp;&amp; VTCR_EL2.S2POE == '1' then</line>
<line>        if walkparams.d128 == '1' then</line>
<line>            permissions.s2po_index = descriptor&lt;124:121&gt;;</line>
<line>        else</line>
<line>            permissions.s2po_index = descriptor&lt;62:59&gt;;</line>
<line>    return permissions;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walk/AArch64.S1InitialTTWState" mylink="aarch64.translation.vmsa_walk.AArch64.S1InitialTTWState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1InitialTTWState()</line>
<line>// ===========================</line>
<line>// Set properties of first access to translation tables in stage 1</line>
<line></line>
<line><a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> AArch64.S1InitialTTWState(S1TTWParams walkparams, bits(64) va, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime,</line>
<line>                                   <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss)</line>
<line>    <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a>    walkstate;</line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> tablebase;</line>
<line>    <a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a> permissions;</line>
<line>    bits(64)    ttb;</line>
<line></line>
<line>    startlevel  = AArch64.S1StartLevel(walkparams);</line>
<line>    ttb         = <a link="AArch64.S1TTB.2" file="shared_pseudocode.xml" hover="function: bits(64) AArch64.S1TTB(Regime regime, bits(64) va)">AArch64.S1TTB</a>(regime, va);</line>
<line>    case ss of</line>
<line>        when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>    tablebase.paspace = <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a>;</line>
<line>        when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> tablebase.paspace = <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line>        when <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>      tablebase.paspace = <a link="PAS_Root" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Root</a>;</line>
<line>        when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>     tablebase.paspace = <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a>;</line>
<line></line>
<line>    tablebase.address = <a link="AArch64.TTBaseAddress.7" file="shared_pseudocode.xml" hover="function: bits(56) AArch64.TTBaseAddress(bits(64) ttb, bits(6) txsz, bits(3) ps, bit d128, bit ds, TGx tgx, integer startlevel)">AArch64.TTBaseAddress</a>(ttb, walkparams.txsz,</line>
<line>                                              walkparams.ps, walkparams.d128,</line>
<line>                                              walkparams.ds,</line>
<line>                                              walkparams.tgx, startlevel);</line>
<line></line>
<line>    permissions.ap_table = '00';</line>
<line>    if <a link="impl-shared.HasUnprivileged.1" file="shared_pseudocode.xml" hover="function: boolean HasUnprivileged(Regime regime)">HasUnprivileged</a>(regime) then</line>
<line>        permissions.uxn_table = '0';</line>
<line>        permissions.pxn_table = '0';</line>
<line>    else</line>
<line>        permissions.xn_table  = '0';</line>
<line></line>
<line>    walkstate.baseaddress = tablebase;</line>
<line>    walkstate.level       = startlevel;</line>
<line>    walkstate.istable     = TRUE;</line>
<line>    // In regimes that support global and non-global translations, translation</line>
<line>    // table entries from lookup levels other than the final level of lookup</line>
<line>    // are treated as being non-global</line>
<line>    walkstate.nG          = if <a link="impl-shared.HasUnprivileged.1" file="shared_pseudocode.xml" hover="function: boolean HasUnprivileged(Regime regime)">HasUnprivileged</a>(regime) then '1' else '0';</line>
<line>    walkstate.memattrs    = <a link="impl-shared.WalkMemAttrs.3" file="shared_pseudocode.xml" hover="function: MemoryAttributes WalkMemAttrs(bits(2) sh, bits(2) irgn, bits(2) orgn)">WalkMemAttrs</a>(walkparams.sh, walkparams.irgn, walkparams.orgn);</line>
<line>    walkstate.permissions = permissions;</line>
<line>    if (walkparams.d128 == '1' || walkparams.pnch == '1') then</line>
<line>        walkstate.s1assured = TRUE;</line>
<line>    else</line>
<line>        walkstate.s1assured = FALSE;</line>
<line>    walkstate.disch = walkparams.disch;</line>
<line></line>
<line>    return walkstate;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walk/AArch64.S1NextWalkStateLeaf" mylink="aarch64.translation.vmsa_walk.AArch64.S1NextWalkStateLeaf" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1NextWalkStateLeaf()</line>
<line>// =============================</line>
<line>// Decode stage 1 page or block descriptor as output to this stage of translation</line>
<line></line>
<line><a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> AArch64.S1NextWalkStateLeaf(<a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> currentstate, boolean s2fs1mro, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime,</line>
<line>                                     <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss, S1TTWParams walkparams, bits(N) descriptor)</line>
<line>    <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a>    nextstate;</line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> baseaddress;</line>
<line>    baseaddress.address = <a link="AArch64.LeafBase.5" file="shared_pseudocode.xml" hover="function: bits(56) AArch64.LeafBase(bits(N) descriptor, bit d128, bit ds, TGx tgx, integer level)">AArch64.LeafBase</a>(descriptor, walkparams.d128,</line>
<line>                                               walkparams.ds,</line>
<line>                                               walkparams.tgx, currentstate.level);</line>
<line></line>
<line>    if currentstate.baseaddress.paspace == <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a> then</line>
<line>        // Determine PA space of the block from NS bit</line>
<line>        bit ns;</line>
<line>        ns = if walkparams.d128 == '1' then descriptor&lt;127&gt; else descriptor&lt;5&gt;;</line>
<line>        baseaddress.paspace = if ns == '0' then <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a> else <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line>    elsif currentstate.baseaddress.paspace == <a link="PAS_Root" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Root</a> then</line>
<line>        // Determine PA space of the block from NSE and NS bits</line>
<line>        bit nse;</line>
<line>        bit ns;</line>
<line>        &lt;nse,ns&gt; = if walkparams.d128 == '1' then descriptor&lt;11,127&gt; else descriptor&lt;11,5&gt;;</line>
<line>        baseaddress.paspace = <a link="impl-shared.DecodePASpace.2" file="shared_pseudocode.xml" hover="function: PASpace DecodePASpace (bit nse, bit ns)">DecodePASpace</a>(nse, ns);</line>
<line></line>
<line>        // If Secure state is not implemented, but RME is,</line>
<line>        // force Secure space accesses to Non-secure space</line>
<line>        if baseaddress.paspace == <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a> &amp;&amp; !<a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>() then</line>
<line>            baseaddress.paspace = <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line></line>
<line>    elsif (currentstate.baseaddress.paspace == <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a> &amp;&amp;</line>
<line>            regime IN {<a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>, <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a>}) then</line>
<line>        // Realm EL2 and EL2&amp;0 regimes have a stage 1 NS bit</line>
<line>        bit ns;</line>
<line>        ns = if walkparams.d128 == '1' then descriptor&lt;127&gt; else descriptor&lt;5&gt;;</line>
<line>        baseaddress.paspace = if ns == '0' then <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a> else <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line>    elsif currentstate.baseaddress.paspace == <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a> then</line>
<line>        // Realm EL1&amp;0 regime does not have a stage 1 NS bit</line>
<line>        baseaddress.paspace = <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a>;</line>
<line>    else</line>
<line>        baseaddress.paspace = <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line></line>
<line>    nextstate.istable     = FALSE;</line>
<line>    nextstate.level       = currentstate.level;</line>
<line>    nextstate.baseaddress = baseaddress;</line>
<line></line>
<line>    bits(4) attrindx;</line>
<line>    if walkparams.aie == '1' then</line>
<line>        if walkparams.d128 == '1' then</line>
<line>            attrindx = descriptor&lt;5:2&gt;;</line>
<line>        else</line>
<line>            attrindx = descriptor&lt;59,4:2&gt;;</line>
<line>    else</line>
<line>        attrindx = '0':descriptor&lt;4:2&gt;;</line>
<line></line>
<line>    bits(2) sh;</line>
<line>    if walkparams.d128 == '1' then</line>
<line>        sh = descriptor&lt;9:8&gt;;</line>
<line>    elsif walkparams.ds == '1' then</line>
<line>        sh = walkparams.sh;</line>
<line>    else</line>
<line>        sh = descriptor&lt;9:8&gt;;</line>
<line>    attr = AArch64.MAIRAttr(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(attrindx), walkparams.mair2, walkparams.mair);</line>
<line>    s1aarch64 = TRUE;</line>
<line></line>
<line>    nextstate.memattrs    = S1DecodeMemAttrs(attr, sh, s1aarch64, walkparams);</line>
<line>    nextstate.permissions = AArch64.S1ApplyOutputPerms(currentstate.permissions,</line>
<line>                                                       descriptor, regime, walkparams);</line>
<line>    bit protected;</line>
<line>    if walkparams.d128 == '1' then</line>
<line>        protected = descriptor&lt;114&gt;;</line>
<line>    else</line>
<line>        protected = if walkparams.pnch == '1' then descriptor&lt;52&gt; else '0';</line>
<line>    if (currentstate.s1assured &amp;&amp; s2fs1mro &amp;&amp; protected == '1') then</line>
<line>        nextstate.s1assured = TRUE;</line>
<line>    else</line>
<line>        nextstate.s1assured = FALSE;</line>
<line></line>
<line>    if walkparams.pnch == '1' || currentstate.disch == '1' then</line>
<line>        nextstate.contiguous = '0';</line>
<line>    else</line>
<line>        nextstate.contiguous = <a link="AArch64.ContiguousBit.4" file="shared_pseudocode.xml" hover="function: bit AArch64.ContiguousBit(TGx tgx, bit d128, integer level, bits(N) descriptor)">AArch64.ContiguousBit</a>(walkparams.tgx, walkparams.d128,</line>
<line>                                                     currentstate.level, descriptor);</line>
<line>    if !<a link="impl-shared.HasUnprivileged.1" file="shared_pseudocode.xml" hover="function: boolean HasUnprivileged(Regime regime)">HasUnprivileged</a>(regime) then</line>
<line>        nextstate.nG = '0';</line>
<line>    elsif ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> &amp;&amp; currentstate.baseaddress.paspace == <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a> then</line>
<line>        // In Secure state, a translation must be treated as non-global,</line>
<line>        // regardless of the value of the nG bit,</line>
<line>        // if NSTable is set to 1 at any level of the translation table walk</line>
<line>        nextstate.nG = '1';</line>
<line>    else</line>
<line>        nextstate.nG = descriptor&lt;11&gt;;</line>
<line></line>
<line>    if walkparams.d128 == '1' then</line>
<line>        nextstate.guardedpage = descriptor&lt;113&gt;;</line>
<line>    else</line>
<line>        nextstate.guardedpage = descriptor&lt;50&gt;;</line>
<line></line>
<line>    return nextstate;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walk/AArch64.S1NextWalkStateTable" mylink="aarch64.translation.vmsa_walk.AArch64.S1NextWalkStateTable" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1NextWalkStateTable()</line>
<line>// ==============================</line>
<line>// Decode stage 1 table descriptor to transition to the next level</line>
<line></line>
<line><a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> AArch64.S1NextWalkStateTable(<a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> currentstate, boolean s2fs1mro, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime,</line>
<line>                                      S1TTWParams walkparams, bits(N) descriptor)</line>
<line>    <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a>    nextstate;</line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> tablebase;</line>
<line></line>
<line>    tablebase.address = <a link="AArch64.NextTableBase.4" file="shared_pseudocode.xml" hover="function: bits(56) AArch64.NextTableBase(bits(N) descriptor, bit d128, bit ds, TGx tgx)">AArch64.NextTableBase</a>(descriptor, walkparams.d128,</line>
<line>                                              walkparams.ds,</line>
<line>                                              walkparams.tgx);</line>
<line>    if currentstate.baseaddress.paspace == <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a> then</line>
<line>        // Determine PA space of the next table from NSTable bit</line>
<line>        bit nstable;</line>
<line>        nstable = if walkparams.d128 == '1' then descriptor&lt;127&gt; else descriptor&lt;63&gt;;</line>
<line>        tablebase.paspace = if nstable == '0' then <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a> else <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line>    else</line>
<line>        // Otherwise bit 63 is RES0 and there is no NSTable bit</line>
<line>        tablebase.paspace = currentstate.baseaddress.paspace;</line>
<line></line>
<line>    nextstate.istable     = TRUE;</line>
<line>    nextstate.nG          = currentstate.nG;</line>
<line>    if walkparams.d128 == '1' then</line>
<line>        skl = descriptor&lt;110:109&gt;;</line>
<line>        nextstate.level   = currentstate.level + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(skl) + 1;</line>
<line>    else</line>
<line>        nextstate.level   = currentstate.level + 1;</line>
<line>    nextstate.baseaddress = tablebase;</line>
<line>    nextstate.memattrs    = currentstate.memattrs;</line>
<line>    if walkparams.hpd == '0' &amp;&amp; walkparams.pie == '0' then</line>
<line>        nextstate.permissions = AArch64.S1ApplyTablePerms(currentstate.permissions, descriptor,</line>
<line>                                                          regime, walkparams);</line>
<line>    else</line>
<line>        nextstate.permissions = currentstate.permissions;</line>
<line>    bit protected;</line>
<line>    if walkparams.d128 == '1' then</line>
<line>        protected = descriptor&lt;114&gt;;</line>
<line>    else</line>
<line>        protected = if walkparams.pnch == '1' then descriptor&lt;52&gt; else '0';</line>
<line>    if (currentstate.s1assured &amp;&amp; s2fs1mro &amp;&amp; protected == '1') then</line>
<line>        nextstate.s1assured = TRUE;</line>
<line>    else</line>
<line>        nextstate.s1assured = FALSE;</line>
<line>    nextstate.disch = if walkparams.d128 == '1' then descriptor&lt;112&gt; else '0';</line>
<line></line>
<line>    return nextstate;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walk/AArch64.S1Walk" mylink="aarch64.translation.vmsa_walk.AArch64.S1Walk" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1Walk()</line>
<line>// ================</line>
<line>// Traverse stage 1 translation tables obtaining the final descriptor</line>
<line>// as well as the address leading to that descriptor</line>
<line></line>
<line>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a>, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a>, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a>, bits(N)) AArch64.S1Walk(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault_in,</line>
<line>                                                                   S1TTWParams walkparams,</line>
<line>                                                                   bits(64) va, <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime,</line>
<line>                                                                   <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc,</line>
<line>                                                                   integer N)</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = fault_in;</line>
<line></line>
<line>    if <a link="impl-shared.HasUnprivileged.1" file="shared_pseudocode.xml" hover="function: boolean HasUnprivileged(Regime regime)">HasUnprivileged</a>(regime) &amp;&amp; <a link="AArch64.S1EPD.2" file="shared_pseudocode.xml" hover="function: bit AArch64.S1EPD(Regime regime, bits(64) va)">AArch64.S1EPD</a>(regime, va) == '1' then</line>
<line>        fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>        fault.level      = 0;</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN,</line>
<line>                bits(N) UNKNOWN);</line>
<line></line>
<line>    walkstate = AArch64.S1InitialTTWState(walkparams, va, regime, accdesc.ss);</line>
<line>    constant integer startlevel = walkstate.level;</line>
<line></line>
<line>    // Detect Address Size Fault by TTB</line>
<line>    if <a link="AArch64.OAOutOfRange.5" file="shared_pseudocode.xml" hover="function: boolean AArch64.OAOutOfRange(TTWState walkstate, bit d128, bits(3) ps, TGx tgx, bits(64) ia)">AArch64.OAOutOfRange</a>(walkstate, walkparams.d128,</line>
<line>                            walkparams.ps, walkparams.tgx, va) then</line>
<line>        fault.statuscode = <a link="Fault_AddressSize" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AddressSize</a>;</line>
<line>        fault.level      = 0;</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN,</line>
<line>                bits(N) UNKNOWN);</line>
<line></line>
<line>    bits(N) descriptor;</line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> walkaddress;</line>
<line>    bits(2) skl = '00';</line>
<line>    walkaddress.vaddress = va;</line>
<line>    walkaddress.mecid = <a link="AArch64.TTWalkMECID.3" file="shared_pseudocode.xml" hover="function: bits(16) AArch64.TTWalkMECID(bit emec, Regime regime, SecurityState ss)">AArch64.TTWalkMECID</a>(walkparams.emec, regime, accdesc.ss);</line>
<line></line>
<line>    if !<a link="AArch64.S1DCacheEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.S1DCacheEnabled(Regime regime)">AArch64.S1DCacheEnabled</a>(regime) then</line>
<line>        walkaddress.memattrs = <a link="impl-shared.NormalNCMemAttr.0" file="shared_pseudocode.xml" hover="function: MemoryAttributes NormalNCMemAttr()">NormalNCMemAttr</a>();</line>
<line>        walkaddress.memattrs.xs = walkstate.memattrs.xs;</line>
<line>    else</line>
<line>        walkaddress.memattrs = walkstate.memattrs;</line>
<line></line>
<line>    // Shareability value of stage 1 translation subject to stage 2 is IMPLEMENTATION DEFINED</line>
<line>    // to be either effective value or descriptor value</line>
<line>    if (regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.VM == '1' &amp;&amp;</line>
<line>            !(boolean IMPLEMENTATION_DEFINED "Apply effective shareability at stage 1")) then</line>
<line>        walkaddress.memattrs.shareability = walkstate.memattrs.shareability;</line>
<line>    else</line>
<line>        walkaddress.memattrs.shareability = <a link="impl-shared.EffectiveShareability.1" file="shared_pseudocode.xml" hover="function: Shareability EffectiveShareability(MemoryAttributes memattrs)">EffectiveShareability</a>(walkaddress.memattrs);</line>
<line></line>
<line>    boolean s2fs1mro = FALSE;</line>
<line></line>
<line>    <a link="DescriptorType" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType</a> desctype;</line>
<line>    repeat</line>
<line>        fault.level = walkstate.level;</line>
<line>        <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> descaddress;</line>
<line>        if walkstate.level == startlevel then</line>
<line>            descaddress = AArch64.S1SLTTEntryAddress(walkstate.level, walkparams, va,</line>
<line>                                                     walkstate.baseaddress);</line>
<line>        else</line>
<line>            skl = if walkparams.d128 == '1' then descriptor&lt;110:109&gt; else '00';</line>
<line>            descaddress = <a link="AArch64.TTEntryAddress.7" file="shared_pseudocode.xml" hover="function: FullAddress AArch64.TTEntryAddress(integer level, bit d128, bits(2) skl, TGx tgx, bits(6) txsz, bits(64) ia, FullAddress tablebase)">AArch64.TTEntryAddress</a>(walkstate.level, walkparams.d128, skl,</line>
<line>                                                 walkparams.tgx, walkparams.txsz, va,</line>
<line>                                                 walkstate.baseaddress);</line>
<line>        walkaddress.paddress = descaddress;</line>
<line></line>
<line>        boolean toplevel = walkstate.level == startlevel;</line>
<line>        <a link="VARange" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange</a> varange  = <a link="AArch64.GetVARange.1" file="shared_pseudocode.xml" hover="function: VARange AArch64.GetVARange(bits(64) va)">AArch64.GetVARange</a>(va);</line>
<line>        <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> walkaccess = <a link="impl-shared.CreateAccDescS1TTW.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescS1TTW(boolean toplevel, VARange varange, AccessDescriptor accdesc_in)">CreateAccDescS1TTW</a>(toplevel, varange, accdesc);</line>
<line>        <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> s2fault;</line>
<line>        <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> s2walkaddress;</line>
<line>        if regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>            s1aarch64 = TRUE;</line>
<line>            aligned   = TRUE;</line>
<line>            (s2fault, s2walkaddress) = <a link="AArch64.S2Translate.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, AddressDescriptor) AArch64.S2Translate(FaultRecord fault_in, AddressDescriptor ipa, boolean s1aarch64, boolean aligned, AccessDescriptor accdesc)">AArch64.S2Translate</a>(fault, walkaddress, s1aarch64, aligned,</line>
<line>                                                           walkaccess);</line>
<line></line>
<line>            if s2fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>                return (s2fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN,</line>
<line>                        bits(N) UNKNOWN);</line>
<line></line>
<line>            s2fs1mro = s2walkaddress.s2fs1mro;</line>
<line>            (fault, descriptor) = <a link="impl-shared.FetchDescriptor.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, bits(N)) FetchDescriptor(bit ee, AddressDescriptor walkaddress, AccessDescriptor walkaccess, FaultRecord fault_in, integer N)">FetchDescriptor</a>(walkparams.ee, s2walkaddress, walkaccess,</line>
<line>                                                  fault, N);</line>
<line>        else</line>
<line>            (fault, descriptor) = <a link="impl-shared.FetchDescriptor.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, bits(N)) FetchDescriptor(bit ee, AddressDescriptor walkaddress, AccessDescriptor walkaccess, FaultRecord fault_in, integer N)">FetchDescriptor</a>(walkparams.ee, walkaddress, walkaccess,</line>
<line>                                                  fault, N);</line>
<line></line>
<line>        if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>            return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN,</line>
<line>                    bits(N) UNKNOWN);</line>
<line></line>
<line>        bits(N) new_descriptor;</line>
<line>        repeat</line>
<line>            new_descriptor = descriptor;</line>
<line>            desctype = <a link="AArch64.DecodeDescriptorType.5" file="shared_pseudocode.xml" hover="function: DescriptorType AArch64.DecodeDescriptorType(bits(N) descriptor, bit d128, bit ds, TGx tgx, integer level)">AArch64.DecodeDescriptorType</a>(descriptor, walkparams.d128, walkparams.ds,</line>
<line>                                                    walkparams.tgx, walkstate.level);</line>
<line>            case desctype of</line>
<line>                when <a link="DescriptorType_Table" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Table</a></line>
<line>                    walkstate = AArch64.S1NextWalkStateTable(walkstate, s2fs1mro,</line>
<line>                                                             regime, walkparams, descriptor);</line>
<line>                    // Detect Address Size Fault by table descriptor</line>
<line></line>
<line>                    if <a link="AArch64.OAOutOfRange.5" file="shared_pseudocode.xml" hover="function: boolean AArch64.OAOutOfRange(TTWState walkstate, bit d128, bits(3) ps, TGx tgx, bits(64) ia)">AArch64.OAOutOfRange</a>(walkstate, walkparams.d128,</line>
<line>                                            walkparams.ps, walkparams.tgx, va) then</line>
<line>                        fault.statuscode = <a link="Fault_AddressSize" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AddressSize</a>;</line>
<line>                        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN,</line>
<line>                                bits(N) UNKNOWN);</line>
<line></line>
<line>                    if walkparams.haft == '1' then</line>
<line>                        new_descriptor&lt;10&gt; = '1';</line>
<line></line>
<line>                    if walkparams.d128 == '1' then</line>
<line>                        skl = descriptor&lt;110:109&gt;;</line>
<line>                        if skl != '00' &amp;&amp; <a link="AArch64.BlocknTFaults.2" file="shared_pseudocode.xml" hover="function: boolean AArch64.BlocknTFaults(bit d128, bits(N) descriptor)">AArch64.BlocknTFaults</a>(walkparams.d128, descriptor) then</line>
<line>                            fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>                            return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN,</line>
<line>                                    bits(N) UNKNOWN);</line>
<line>                when <a link="DescriptorType_Leaf" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Leaf</a></line>
<line>                    walkstate = AArch64.S1NextWalkStateLeaf(walkstate, s2fs1mro,</line>
<line>                                                            regime, accdesc.ss, walkparams,</line>
<line>                                                            descriptor);</line>
<line>                when <a link="DescriptorType_Invalid" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Invalid</a></line>
<line>                    fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>                    return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN,</line>
<line>                            bits(N) UNKNOWN);</line>
<line>                otherwise</line>
<line>                    <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>            if new_descriptor != descriptor then</line>
<line>                <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> descpaddr;</line>
<line>                <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> descaccess = <a link="impl-shared.CreateAccDescTTEUpdate.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescTTEUpdate(AccessDescriptor accdesc_in)">CreateAccDescTTEUpdate</a>(accdesc);</line>
<line>                if regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>                    s1aarch64 = TRUE;</line>
<line>                    aligned   = TRUE;</line>
<line>                    (s2fault, descpaddr) = <a link="AArch64.S2Translate.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, AddressDescriptor) AArch64.S2Translate(FaultRecord fault_in, AddressDescriptor ipa, boolean s1aarch64, boolean aligned, AccessDescriptor accdesc)">AArch64.S2Translate</a>(fault, walkaddress,</line>
<line>                                                               s1aarch64, aligned,</line>
<line>                                                               descaccess);</line>
<line>                else</line>
<line>                    descpaddr = walkaddress;</line>
<line></line>
<line>                (fault, descriptor) = <a link="AArch64.MemSwapTableDesc.6" file="shared_pseudocode.xml" hover="function: (FaultRecord, bits(N)) AArch64.MemSwapTableDesc(FaultRecord fault_in, bits(N) prev_desc, bits(N) new_desc, bit ee, AccessDescriptor  descaccess, AddressDescriptor descpaddr)">AArch64.MemSwapTableDesc</a>(fault, descriptor, new_descriptor,</line>
<line>                                                               walkparams.ee, descaccess,</line>
<line>                                                               descpaddr);</line>
<line>                if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>                    return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN,</line>
<line>                            <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN, bits(N) UNKNOWN);</line>
<line>        until new_descriptor == descriptor;</line>
<line>    until desctype == <a link="DescriptorType_Leaf" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Leaf</a>;</line>
<line></line>
<line>    if (walkstate.contiguous == '1' &amp;&amp;</line>
<line>        <a link="AArch64.ContiguousBitFaults.4" file="shared_pseudocode.xml" hover="function: boolean AArch64.ContiguousBitFaults(bit d128, bits(6) txsz, TGx tgx, integer level)">AArch64.ContiguousBitFaults</a>(walkparams.d128, walkparams.txsz, walkparams.tgx,</line>
<line>                                    walkstate.level)) then</line>
<line>        fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>    elsif (desctype == <a link="DescriptorType_Leaf" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Leaf</a> &amp;&amp; walkstate.level &lt; <a link="FINAL_LEVEL" file="shared_pseudocode.xml" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</a> &amp;&amp;</line>
<line>          <a link="AArch64.BlocknTFaults.2" file="shared_pseudocode.xml" hover="function: boolean AArch64.BlocknTFaults(bit d128, bits(N) descriptor)">AArch64.BlocknTFaults</a>(walkparams.d128, descriptor)) then</line>
<line>        fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>    elsif AArch64.S1AMECFault(walkparams, walkstate.baseaddress.paspace, regime, descriptor) then</line>
<line>        fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>    // Detect Address Size Fault by final output</line>
<line>    elsif <a link="AArch64.OAOutOfRange.5" file="shared_pseudocode.xml" hover="function: boolean AArch64.OAOutOfRange(TTWState walkstate, bit d128, bits(3) ps, TGx tgx, bits(64) ia)">AArch64.OAOutOfRange</a>(walkstate, walkparams.d128,</line>
<line>                               walkparams.ps, walkparams.tgx, va) then</line>
<line>        fault.statuscode = <a link="Fault_AddressSize" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AddressSize</a>;</line>
<line>    // Check descriptor AF bit</line>
<line>    elsif (descriptor&lt;10&gt; == '0' &amp;&amp; walkparams.ha == '0' &amp;&amp;</line>
<line>            !(accdesc.acctype IN {<a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>, <a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a>} &amp;&amp;</line>
<line>            !boolean IMPLEMENTATION_DEFINED "Generate access flag fault on IC/DC operations")) then</line>
<line>        fault.statuscode = <a link="Fault_AccessFlag" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AccessFlag</a>;</line>
<line></line>
<line>    if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN, bits(N) UNKNOWN);</line>
<line></line>
<line>    return (fault, walkaddress, walkstate, descriptor);</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walk/AArch64.S2InitialTTWState" mylink="aarch64.translation.vmsa_walk.AArch64.S2InitialTTWState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S2InitialTTWState()</line>
<line>// ===========================</line>
<line>// Set properties of first access to translation tables in stage 2</line>
<line></line>
<line><a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> AArch64.S2InitialTTWState(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss, S2TTWParams walkparams)</line>
<line>    <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a>    walkstate;</line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> tablebase;</line>
<line>    bits(64)    ttb;</line>
<line></line>
<line>    ttb               = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(VTTBR_EL2.BADDR, 64);</line>
<line>    startlevel        = AArch64.S2StartLevel(walkparams);</line>
<line>    case ss of</line>
<line>        when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> tablebase.paspace = <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line>        when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>     tablebase.paspace = <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a>;</line>
<line>    tablebase.address = <a link="AArch64.TTBaseAddress.7" file="shared_pseudocode.xml" hover="function: bits(56) AArch64.TTBaseAddress(bits(64) ttb, bits(6) txsz, bits(3) ps, bit d128, bit ds, TGx tgx, integer startlevel)">AArch64.TTBaseAddress</a>(ttb, walkparams.txsz,</line>
<line>                                              walkparams.ps, walkparams.d128,</line>
<line>                                              walkparams.ds,</line>
<line>                                              walkparams.tgx, startlevel);</line>
<line></line>
<line>    walkstate.baseaddress = tablebase;</line>
<line>    walkstate.level       = startlevel;</line>
<line>    walkstate.istable     = TRUE;</line>
<line>    walkstate.memattrs    = <a link="impl-shared.WalkMemAttrs.3" file="shared_pseudocode.xml" hover="function: MemoryAttributes WalkMemAttrs(bits(2) sh, bits(2) irgn, bits(2) orgn)">WalkMemAttrs</a>(walkparams.sh, walkparams.irgn, walkparams.orgn);</line>
<line></line>
<line>    return walkstate;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walk/AArch64.S2NextWalkStateLeaf" mylink="aarch64.translation.vmsa_walk.AArch64.S2NextWalkStateLeaf" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S2NextWalkStateLeaf()</line>
<line>// =============================</line>
<line>// Decode stage 2 page or block descriptor as output to this stage of translation</line>
<line></line>
<line><a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> AArch64.S2NextWalkStateLeaf(<a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> currentstate, <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss,</line>
<line>                                     S2TTWParams walkparams, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> ipa,</line>
<line>                                     bits(N) descriptor)</line>
<line>    <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a>    nextstate;</line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> baseaddress;</line>
<line></line>
<line>    if ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>        baseaddress.paspace = AArch64.SS2OutputPASpace(walkparams, ipa.paddress.paspace);</line>
<line>    elsif ss == <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a> then</line>
<line>        bit ns;</line>
<line>        ns = if walkparams.d128 == '1' then descriptor&lt;127&gt; else descriptor&lt;55&gt;;</line>
<line>        baseaddress.paspace = if ns == '1' then <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a> else <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a>;</line>
<line>    else</line>
<line>        baseaddress.paspace = <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line>    baseaddress.address   = <a link="AArch64.LeafBase.5" file="shared_pseudocode.xml" hover="function: bits(56) AArch64.LeafBase(bits(N) descriptor, bit d128, bit ds, TGx tgx, integer level)">AArch64.LeafBase</a>(descriptor, walkparams.d128, walkparams.ds,</line>
<line>                                             walkparams.tgx, currentstate.level);</line>
<line></line>
<line>    nextstate.istable     = FALSE;</line>
<line>    nextstate.level       = currentstate.level;</line>
<line>    nextstate.baseaddress = baseaddress;</line>
<line>    nextstate.permissions = AArch64.S2ApplyOutputPerms(descriptor, walkparams);</line>
<line></line>
<line>    s2_attr = descriptor&lt;5:2&gt;;</line>
<line>    s2_sh   = if walkparams.ds == '1' then walkparams.sh else descriptor&lt;9:8&gt;;</line>
<line>    s2_fnxs = descriptor&lt;11&gt;;</line>
<line>    if walkparams.fwb == '1' then</line>
<line>        nextstate.memattrs = AArch64.S2ApplyFWBMemAttrs(ipa.memattrs, walkparams, descriptor);</line>
<line>        if s2_attr&lt;3:1&gt; == '111' then</line>
<line>            nextstate.permissions.s2tag_na = '1';</line>
<line>        else</line>
<line>            nextstate.permissions.s2tag_na = '0';</line>
<line>    else</line>
<line>        s2aarch64 = TRUE;</line>
<line>        nextstate.memattrs = <a link="impl-shared.S2DecodeMemAttrs.3" file="shared_pseudocode.xml" hover="function: MemoryAttributes S2DecodeMemAttrs(bits(4) attr, bits(2) sh, boolean s2aarch64)">S2DecodeMemAttrs</a>(s2_attr, s2_sh, s2aarch64);</line>
<line>        // FnXS is used later to mask the XS value from stage 1</line>
<line>        nextstate.memattrs.xs = NOT s2_fnxs;</line>
<line>        if s2_attr == '0100' then</line>
<line>            nextstate.permissions.s2tag_na = '1';</line>
<line>        else</line>
<line>            nextstate.permissions.s2tag_na = '0';</line>
<line>    nextstate.contiguous = <a link="AArch64.ContiguousBit.4" file="shared_pseudocode.xml" hover="function: bit AArch64.ContiguousBit(TGx tgx, bit d128, integer level, bits(N) descriptor)">AArch64.ContiguousBit</a>(walkparams.tgx, walkparams.d128,</line>
<line>                                                 currentstate.level, descriptor);</line>
<line>    if walkparams.d128 == '1' then</line>
<line>        nextstate.s2assuredonly = descriptor&lt;114&gt;;</line>
<line>    else</line>
<line>        nextstate.s2assuredonly = if walkparams.assuredonly == '1' then descriptor&lt;58&gt; else '0';</line>
<line></line>
<line>    return nextstate;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walk/AArch64.S2NextWalkStateTable" mylink="aarch64.translation.vmsa_walk.AArch64.S2NextWalkStateTable" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S2NextWalkStateTable()</line>
<line>// ==============================</line>
<line>// Decode stage 2 table descriptor to transition to the next level</line>
<line></line>
<line><a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> AArch64.S2NextWalkStateTable(<a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> currentstate, S2TTWParams walkparams,</line>
<line>                                      bits(N) descriptor)</line>
<line>    <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a>    nextstate;</line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> tablebase;</line>
<line></line>
<line>    tablebase.address = <a link="AArch64.NextTableBase.4" file="shared_pseudocode.xml" hover="function: bits(56) AArch64.NextTableBase(bits(N) descriptor, bit d128, bit ds, TGx tgx)">AArch64.NextTableBase</a>(descriptor, walkparams.d128,</line>
<line>                                              walkparams.ds,</line>
<line>                                              walkparams.tgx);</line>
<line>    tablebase.paspace = currentstate.baseaddress.paspace;</line>
<line></line>
<line>    nextstate.istable     = TRUE;</line>
<line>    if walkparams.d128 == '1' then</line>
<line>        skl = descriptor&lt;110:109&gt;;</line>
<line>        nextstate.level   = currentstate.level + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(skl) + 1;</line>
<line>    else</line>
<line>        nextstate.level   = currentstate.level + 1;</line>
<line>    nextstate.baseaddress = tablebase;</line>
<line>    nextstate.memattrs    = currentstate.memattrs;</line>
<line></line>
<line>    return nextstate;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walk/AArch64.S2Walk" mylink="aarch64.translation.vmsa_walk.AArch64.S2Walk" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S2Walk()</line>
<line>// ================</line>
<line>// Traverse stage 2 translation tables obtaining the final descriptor</line>
<line>// as well as the address leading to that descriptor</line>
<line></line>
<line>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a>, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a>, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a>, bits(N)) AArch64.S2Walk(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault_in,</line>
<line>                                                                   <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> ipa,</line>
<line>                                                                   S2TTWParams walkparams,</line>
<line>                                                                   <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc,</line>
<line>                                                                   integer N)</line>
<line></line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = fault_in;</line>
<line>    ipa_64 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(ipa.paddress.address, 64);</line>
<line></line>
<line>    <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> walkstate;</line>
<line>    if accdesc.ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>        walkstate = AArch64.SS2InitialTTWState(walkparams, ipa.paddress.paspace);</line>
<line>    else</line>
<line>        walkstate = AArch64.S2InitialTTWState(accdesc.ss, walkparams);</line>
<line></line>
<line>    constant integer startlevel = walkstate.level;</line>
<line></line>
<line>    // Detect Address Size Fault by TTB</line>
<line>    if <a link="AArch64.OAOutOfRange.5" file="shared_pseudocode.xml" hover="function: boolean AArch64.OAOutOfRange(TTWState walkstate, bit d128, bits(3) ps, TGx tgx, bits(64) ia)">AArch64.OAOutOfRange</a>(walkstate, walkparams.d128, walkparams.ps, walkparams.tgx,</line>
<line>                            ipa_64) then</line>
<line>        fault.statuscode = <a link="Fault_AddressSize" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AddressSize</a>;</line>
<line>        fault.level      = 0;</line>
<line>        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN, bits(N) UNKNOWN);</line>
<line></line>
<line>    bits(N) descriptor;</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> walkaccess = <a link="impl-shared.CreateAccDescS2TTW.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescS2TTW(AccessDescriptor accdesc_in)">CreateAccDescS2TTW</a>(accdesc);</line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> walkaddress;</line>
<line>    bits(2) skl = '00';</line>
<line></line>
<line>    walkaddress.vaddress = ipa.vaddress;</line>
<line>    walkaddress.mecid = <a link="AArch64.TTWalkMECID.3" file="shared_pseudocode.xml" hover="function: bits(16) AArch64.TTWalkMECID(bit emec, Regime regime, SecurityState ss)">AArch64.TTWalkMECID</a>(walkparams.emec, <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a>, accdesc.ss);</line>
<line></line>
<line>    if HCR_EL2.CD == '1' then</line>
<line>        walkaddress.memattrs = <a link="impl-shared.NormalNCMemAttr.0" file="shared_pseudocode.xml" hover="function: MemoryAttributes NormalNCMemAttr()">NormalNCMemAttr</a>();</line>
<line>        walkaddress.memattrs.xs = walkstate.memattrs.xs;</line>
<line>    else</line>
<line>        walkaddress.memattrs = walkstate.memattrs;</line>
<line></line>
<line>    walkaddress.memattrs.shareability = <a link="impl-shared.EffectiveShareability.1" file="shared_pseudocode.xml" hover="function: Shareability EffectiveShareability(MemoryAttributes memattrs)">EffectiveShareability</a>(walkaddress.memattrs);</line>
<line></line>
<line>    <a link="DescriptorType" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType</a> desctype;</line>
<line>    repeat</line>
<line>        fault.level = walkstate.level;</line>
<line></line>
<line>        <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> descaddress;</line>
<line>        if walkstate.level == startlevel then</line>
<line>            // Initial lookup might index into concatenated tables</line>
<line>            descaddress = AArch64.S2SLTTEntryAddress(walkparams, ipa.paddress.address,</line>
<line>                                                     walkstate.baseaddress);</line>
<line>        else</line>
<line>            skl = if walkparams.d128 == '1' then descriptor&lt;110:109&gt; else '00';</line>
<line>            ipa_64 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(ipa.paddress.address, 64);</line>
<line>            descaddress = <a link="AArch64.TTEntryAddress.7" file="shared_pseudocode.xml" hover="function: FullAddress AArch64.TTEntryAddress(integer level, bit d128, bits(2) skl, TGx tgx, bits(6) txsz, bits(64) ia, FullAddress tablebase)">AArch64.TTEntryAddress</a>(walkstate.level, walkparams.d128, skl,</line>
<line>                                                 walkparams.tgx, walkparams.txsz, ipa_64,</line>
<line>                                                 walkstate.baseaddress);</line>
<line></line>
<line>        walkaddress.paddress = descaddress;</line>
<line>        (fault, descriptor) = <a link="impl-shared.FetchDescriptor.5" file="shared_pseudocode.xml" hover="function: (FaultRecord, bits(N)) FetchDescriptor(bit ee, AddressDescriptor walkaddress, AccessDescriptor walkaccess, FaultRecord fault_in, integer N)">FetchDescriptor</a>(walkparams.ee, walkaddress, walkaccess, fault, N);</line>
<line></line>
<line>        if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>            return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN, bits(N) UNKNOWN);</line>
<line></line>
<line>        bits(N) new_descriptor;</line>
<line>        repeat</line>
<line>            new_descriptor = descriptor;</line>
<line>            desctype = <a link="AArch64.DecodeDescriptorType.5" file="shared_pseudocode.xml" hover="function: DescriptorType AArch64.DecodeDescriptorType(bits(N) descriptor, bit d128, bit ds, TGx tgx, integer level)">AArch64.DecodeDescriptorType</a>(descriptor, walkparams.d128, walkparams.ds,</line>
<line>                                                    walkparams.tgx, walkstate.level);</line>
<line>            case desctype of</line>
<line>                when <a link="DescriptorType_Table" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Table</a></line>
<line>                    walkstate = AArch64.S2NextWalkStateTable(walkstate, walkparams, descriptor);</line>
<line></line>
<line>                    // Detect Address Size Fault by table descriptor</line>
<line>                    if <a link="AArch64.OAOutOfRange.5" file="shared_pseudocode.xml" hover="function: boolean AArch64.OAOutOfRange(TTWState walkstate, bit d128, bits(3) ps, TGx tgx, bits(64) ia)">AArch64.OAOutOfRange</a>(walkstate, walkparams.d128,</line>
<line>                                            walkparams.ps, walkparams.tgx, ipa_64) then</line>
<line>                        fault.statuscode = <a link="Fault_AddressSize" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AddressSize</a>;</line>
<line>                        return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN,</line>
<line>                                <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN, bits(N) UNKNOWN);</line>
<line></line>
<line>                    if walkparams.haft == '1' then</line>
<line>                        new_descriptor&lt;10&gt; = '1';</line>
<line></line>
<line>                    if walkparams.d128 == '1' then</line>
<line>                        skl = descriptor&lt;110:109&gt;;</line>
<line>                        if skl != '00' &amp;&amp; <a link="AArch64.BlocknTFaults.2" file="shared_pseudocode.xml" hover="function: boolean AArch64.BlocknTFaults(bit d128, bits(N) descriptor)">AArch64.BlocknTFaults</a>(walkparams.d128, descriptor) then</line>
<line>                            fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>                            return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN,</line>
<line>                                    bits(N) UNKNOWN);</line>
<line></line>
<line>                when <a link="DescriptorType_Leaf" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Leaf</a></line>
<line>                    walkstate = AArch64.S2NextWalkStateLeaf(walkstate, accdesc.ss, walkparams, ipa,</line>
<line>                                                            descriptor);</line>
<line>                when <a link="DescriptorType_Invalid" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Invalid</a></line>
<line>                    fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>                    return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN, bits(N) UNKNOWN);</line>
<line></line>
<line>                otherwise</line>
<line>                    <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>            if new_descriptor != descriptor then</line>
<line>                <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> descaccess = <a link="impl-shared.CreateAccDescTTEUpdate.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescTTEUpdate(AccessDescriptor accdesc_in)">CreateAccDescTTEUpdate</a>(accdesc);</line>
<line>                (fault, descriptor) = <a link="AArch64.MemSwapTableDesc.6" file="shared_pseudocode.xml" hover="function: (FaultRecord, bits(N)) AArch64.MemSwapTableDesc(FaultRecord fault_in, bits(N) prev_desc, bits(N) new_desc, bit ee, AccessDescriptor  descaccess, AddressDescriptor descpaddr)">AArch64.MemSwapTableDesc</a>(fault, descriptor, new_descriptor,</line>
<line>                                                               walkparams.ee, descaccess,</line>
<line>                                                               walkaddress);</line>
<line>                if fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a> then</line>
<line>                    return (fault, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> UNKNOWN, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> UNKNOWN, bits(N) UNKNOWN);</line>
<line>        until new_descriptor == descriptor;</line>
<line>    until desctype == <a link="DescriptorType_Leaf" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Leaf</a>;</line>
<line></line>
<line>    if (walkstate.contiguous == '1' &amp;&amp;</line>
<line>        <a link="AArch64.ContiguousBitFaults.4" file="shared_pseudocode.xml" hover="function: boolean AArch64.ContiguousBitFaults(bit d128, bits(6) txsz, TGx tgx, integer level)">AArch64.ContiguousBitFaults</a>(walkparams.d128, walkparams.txsz, walkparams.tgx,</line>
<line>                                    walkstate.level)) then</line>
<line>        fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>    elsif (desctype == <a link="DescriptorType_Leaf" file="shared_pseudocode.xml" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Leaf</a> &amp;&amp; walkstate.level &lt; <a link="FINAL_LEVEL" file="shared_pseudocode.xml" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</a> &amp;&amp;</line>
<line>          <a link="AArch64.BlocknTFaults.2" file="shared_pseudocode.xml" hover="function: boolean AArch64.BlocknTFaults(bit d128, bits(N) descriptor)">AArch64.BlocknTFaults</a>(walkparams.d128, descriptor)) then</line>
<line>        fault.statuscode = <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>;</line>
<line>    // Detect Address Size Fault by final output</line>
<line>    elsif <a link="AArch64.OAOutOfRange.5" file="shared_pseudocode.xml" hover="function: boolean AArch64.OAOutOfRange(TTWState walkstate, bit d128, bits(3) ps, TGx tgx, bits(64) ia)">AArch64.OAOutOfRange</a>(walkstate, walkparams.d128, walkparams.ps, walkparams.tgx,</line>
<line>                               ipa_64) then</line>
<line>        fault.statuscode = <a link="Fault_AddressSize" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AddressSize</a>;</line>
<line>    // Check descriptor AF bit</line>
<line>    elsif (descriptor&lt;10&gt; == '0' &amp;&amp; walkparams.ha == '0' &amp;&amp;</line>
<line>            !(accdesc.acctype IN {<a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>, <a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a>} &amp;&amp;</line>
<line>            !boolean IMPLEMENTATION_DEFINED "Generate access flag fault on IC/DC operations")) then</line>
<line>        fault.statuscode = <a link="Fault_AccessFlag" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AccessFlag</a>;</line>
<line></line>
<line>    return (fault, walkaddress, walkstate, descriptor);</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walk/AArch64.SS2InitialTTWState" mylink="aarch64.translation.vmsa_walk.AArch64.SS2InitialTTWState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.SS2InitialTTWState()</line>
<line>// ============================</line>
<line>// Set properties of first access to translation tables in Secure stage 2</line>
<line></line>
<line><a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> AArch64.SS2InitialTTWState(S2TTWParams walkparams, <a link="PASpace" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PASpace</a> ipaspace)</line>
<line>    <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a>    walkstate;</line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> tablebase;</line>
<line>    bits(64)    ttb;</line>
<line></line>
<line>    if ipaspace == <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a> then</line>
<line>        ttb = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(VSTTBR_EL2.BADDR, 64);</line>
<line>    else</line>
<line>        ttb = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(VTTBR_EL2.BADDR, 64);</line>
<line></line>
<line>    if ipaspace == <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a> then</line>
<line>        if walkparams.sw == '0' then</line>
<line>            tablebase.paspace = <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a>;</line>
<line>        else</line>
<line>            tablebase.paspace = <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line>    else</line>
<line>        if walkparams.nsw == '0' then</line>
<line>            tablebase.paspace = <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a>;</line>
<line>        else</line>
<line>            tablebase.paspace = <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line></line>
<line>    startlevel        = AArch64.S2StartLevel(walkparams);</line>
<line>    tablebase.address = <a link="AArch64.TTBaseAddress.7" file="shared_pseudocode.xml" hover="function: bits(56) AArch64.TTBaseAddress(bits(64) ttb, bits(6) txsz, bits(3) ps, bit d128, bit ds, TGx tgx, integer startlevel)">AArch64.TTBaseAddress</a>(ttb, walkparams.txsz,</line>
<line>                                              walkparams.ps, walkparams.d128,</line>
<line>                                              walkparams.ds,</line>
<line>                                              walkparams.tgx, startlevel);</line>
<line></line>
<line>    walkstate.baseaddress = tablebase;</line>
<line>    walkstate.level       = startlevel;</line>
<line>    walkstate.istable     = TRUE;</line>
<line>    walkstate.memattrs    = <a link="impl-shared.WalkMemAttrs.3" file="shared_pseudocode.xml" hover="function: MemoryAttributes WalkMemAttrs(bits(2) sh, bits(2) irgn, bits(2) orgn)">WalkMemAttrs</a>(walkparams.sh, walkparams.irgn, walkparams.orgn);</line>
<line></line>
<line>    return walkstate;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walk/AArch64.SS2OutputPASpace" mylink="aarch64.translation.vmsa_walk.AArch64.SS2OutputPASpace" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.SS2OutputPASpace()</line>
<line>// ==========================</line>
<line>// Assign PA Space to output of Secure stage 2 translation</line>
<line></line>
<line><a link="PASpace" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PASpace</a> AArch64.SS2OutputPASpace(S2TTWParams walkparams, <a link="PASpace" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PASpace</a> ipaspace)</line>
<line>    if ipaspace == <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a> then</line>
<line>        if walkparams.&lt;sw,sa&gt; == '00' then</line>
<line>            return <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a>;</line>
<line>        else</line>
<line>            return <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line>    else</line>
<line>        if walkparams.&lt;sw,sa,nsw,nsa&gt; == '0000' then</line>
<line>            return <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a>;</line>
<line>        else</line>
<line>            return <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.BBMSupportLevel" mylink="aarch64.translation.vmsa_walkparams.AArch64.BBMSupportLevel" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.BBMSupportLevel()</line>
<line>// =========================</line>
<line>// Returns the level of FEAT_BBM supported</line>
<line></line>
<line link="AArch64.BlockBBMSupportLevel.0" hover="function: integer AArch64.BlockBBMSupportLevel()" conts="AArch64.BlockBBMSupportLevel">integer <anchor link="AArch64.BlockBBMSupportLevel.0" hover="function: integer AArch64.BlockBBMSupportLevel()">AArch64.BlockBBMSupportLevel</anchor>()</line>
<line>    if !<a link="impl-shared.HaveBlockBBM.0" file="shared_pseudocode.xml" hover="function: boolean HaveBlockBBM()">HaveBlockBBM</a>() then</line>
<line>        return integer UNKNOWN;</line>
<line>    else</line>
<line>        return integer IMPLEMENTATION_DEFINED "Block BBM support level";</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.GetS1TTWParams" mylink="aarch64.translation.vmsa_walkparams.AArch64.GetS1TTWParams" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.GetS1TTWParams()</line>
<line>// ========================</line>
<line>// Returns stage 1 translation table walk parameters from respective controlling</line>
<line>// System registers.</line>
<line></line>
<line>S1TTWParams AArch64.GetS1TTWParams(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss, bits(64) va)</line>
<line>    S1TTWParams walkparams;</line>
<line></line>
<line>    varange = <a link="AArch64.GetVARange.1" file="shared_pseudocode.xml" hover="function: VARange AArch64.GetVARange(bits(64) va)">AArch64.GetVARange</a>(va);</line>
<line></line>
<line>    case regime of</line>
<line>        when <a link="Regime_EL3" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL3</a>  walkparams = AArch64.S1TTWParamsEL3();</line>
<line>        when <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>  walkparams = AArch64.S1TTWParamsEL2(ss);</line>
<line>        when <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a> walkparams = AArch64.S1TTWParamsEL20(ss, varange);</line>
<line>        when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> walkparams = AArch64.S1TTWParamsEL10(varange);</line>
<line></line>
<line>    return walkparams;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.GetS2TTWParams" mylink="aarch64.translation.vmsa_walkparams.AArch64.GetS2TTWParams" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.GetS2TTWParams()</line>
<line>// ========================</line>
<line>// Gather walk parameters for stage 2 translation</line>
<line></line>
<line>S2TTWParams AArch64.GetS2TTWParams(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss, <a link="PASpace" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PASpace</a> ipaspace, boolean s1aarch64)</line>
<line>    S2TTWParams walkparams;</line>
<line></line>
<line>    if ss == <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> then</line>
<line>        walkparams = AArch64.NSS2TTWParams(s1aarch64);</line>
<line>    elsif <a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>() &amp;&amp; ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>        walkparams = AArch64.SS2TTWParams(ipaspace, s1aarch64);</line>
<line>    elsif ss == <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a> then</line>
<line>        walkparams = AArch64.RLS2TTWParams(s1aarch64);</line>
<line>    else</line>
<line>        <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    return walkparams;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.GetVARange" mylink="aarch64.translation.vmsa_walkparams.AArch64.GetVARange" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.GetVARange()</line>
<line>// ====================</line>
<line>// Determines if the VA that is to be translated lies in LOWER or UPPER address range.</line>
<line></line>
<line link="AArch64.GetVARange.1" hover="function: VARange AArch64.GetVARange(bits(64) va)" conts="AArch64.GetVARange">VARange <anchor link="AArch64.GetVARange.1" hover="function: VARange AArch64.GetVARange(bits(64) va)">AArch64.GetVARange</anchor>(bits(64) va)</line>
<line>    if va&lt;55&gt; == '0' then</line>
<line>        return <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a>;</line>
<line>    else</line>
<line>        return <a link="VARange_UPPER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_UPPER</a>;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.HaveS1TG" mylink="aarch64.translation.vmsa_walkparams.AArch64.HaveS1TG" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.HaveS1TG()</line>
<line>// ==================</line>
<line>// Determine whether the given translation granule is supported for stage 1</line>
<line></line>
<line link="AArch64.HaveS1TG.1" hover="function: boolean AArch64.HaveS1TG(TGx tgx)" conts="AArch64.HaveS1TG">boolean <anchor link="AArch64.HaveS1TG.1" hover="function: boolean AArch64.HaveS1TG(TGx tgx)">AArch64.HaveS1TG</anchor>(<a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tgx)</line>
<line>    case tgx of</line>
<line>        when <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>  return boolean IMPLEMENTATION_DEFINED "Has 4K Translation Granule";</line>
<line>        when <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a> return boolean IMPLEMENTATION_DEFINED "Has 16K Translation Granule";</line>
<line>        when <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a> return boolean IMPLEMENTATION_DEFINED "Has 64K Translation Granule";</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.HaveS2TG" mylink="aarch64.translation.vmsa_walkparams.AArch64.HaveS2TG" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.HaveS2TG()</line>
<line>// ==================</line>
<line>// Determine whether the given translation granule is supported for stage 2</line>
<line></line>
<line link="AArch64.HaveS2TG.1" hover="function: boolean AArch64.HaveS2TG(TGx tgx)" conts="AArch64.HaveS2TG">boolean <anchor link="AArch64.HaveS2TG.1" hover="function: boolean AArch64.HaveS2TG(TGx tgx)">AArch64.HaveS2TG</anchor>(<a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tgx)</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line></line>
<line>    if <a link="impl-shared.HaveGTGExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveGTGExt()">HaveGTGExt</a>() then</line>
<line>        case tgx of</line>
<line>            when <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a></line>
<line>                return boolean IMPLEMENTATION_DEFINED "Has Stage 2 4K Translation Granule";</line>
<line>            when <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a></line>
<line>                return boolean IMPLEMENTATION_DEFINED "Has Stage 2 16K Translation Granule";</line>
<line>            when <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a></line>
<line>                return boolean IMPLEMENTATION_DEFINED "Has Stage 2 64K Translation Granule";</line>
<line>    else</line>
<line>        return <a link="AArch64.HaveS1TG.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.HaveS1TG(TGx tgx)">AArch64.HaveS1TG</a>(tgx);</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.MaxTxSZ" mylink="aarch64.translation.vmsa_walkparams.AArch64.MaxTxSZ" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.MaxTxSZ()</line>
<line>// =================</line>
<line>// Retrieve the maximum value of TxSZ indicating minimum input address size for both</line>
<line>// stages of translation</line>
<line></line>
<line link="AArch64.MaxTxSZ.1" hover="function: integer AArch64.MaxTxSZ(TGx tgx)" conts="AArch64.MaxTxSZ">integer <anchor link="AArch64.MaxTxSZ.1" hover="function: integer AArch64.MaxTxSZ(TGx tgx)">AArch64.MaxTxSZ</anchor>(<a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tgx)</line>
<line>    if <a link="impl-shared.HaveSmallTranslationTableExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveSmallTranslationTableExt()">HaveSmallTranslationTableExt</a>() then</line>
<line>        case tgx of</line>
<line>            when <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>   return 48;</line>
<line>            when <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a>  return 48;</line>
<line>            when <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a>  return 47;</line>
<line></line>
<line>    return 39;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.NSS2TTWParams" mylink="aarch64.translation.vmsa_walkparams.AArch64.NSS2TTWParams" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.NSS2TTWParams()</line>
<line>// =======================</line>
<line>// Gather walk parameters specific for Non-secure stage 2 translation</line>
<line></line>
<line>S2TTWParams AArch64.NSS2TTWParams(boolean s1aarch64)</line>
<line>    S2TTWParams walkparams;</line>
<line></line>
<line>    walkparams.vm   = HCR_EL2.VM OR HCR_EL2.DC;</line>
<line>    walkparams.tgx  = <a link="AArch64.S2DecodeTG0.1" file="shared_pseudocode.xml" hover="function: TGx AArch64.S2DecodeTG0(bits(2) tg0_in)">AArch64.S2DecodeTG0</a>(VTCR_EL2.TG0);</line>
<line>    walkparams.txsz = VTCR_EL2.T0SZ;</line>
<line>    walkparams.ps   = VTCR_EL2.PS;</line>
<line>    walkparams.irgn = VTCR_EL2.IRGN0;</line>
<line>    walkparams.orgn = VTCR_EL2.ORGN0;</line>
<line>    walkparams.sh   = VTCR_EL2.SH0;</line>
<line>    walkparams.ee   = SCTLR_EL2.EE;</line>
<line>    walkparams.d128 = if <a link="impl-shared.Have128BitDescriptorExt.0" file="shared_pseudocode.xml" hover="function: boolean Have128BitDescriptorExt()">Have128BitDescriptorExt</a>() then VTCR_EL2.D128 else '0';</line>
<line>    if walkparams.d128 == '1' then</line>
<line>        walkparams.skl = VTTBR_EL2.SKL;</line>
<line>    else</line>
<line>        walkparams.sl0 = VTCR_EL2.SL0;</line>
<line></line>
<line>    walkparams.ptw = if HCR_EL2.TGE == '0'         then HCR_EL2.PTW else '0';</line>
<line>    walkparams.fwb = if <a link="impl-shared.HaveStage2MemAttrControl.0" file="shared_pseudocode.xml" hover="function: boolean HaveStage2MemAttrControl()">HaveStage2MemAttrControl</a>() then HCR_EL2.FWB else '0';</line>
<line>    walkparams.ha  = if <a link="impl-shared.HaveAccessFlagUpdateExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAccessFlagUpdateExt()">HaveAccessFlagUpdateExt</a>()  then VTCR_EL2.HA else '0';</line>
<line>    walkparams.hd  = if <a link="impl-shared.HaveDirtyBitModifierExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDirtyBitModifierExt()">HaveDirtyBitModifierExt</a>()  then VTCR_EL2.HD else '0';</line>
<line>    if walkparams.tgx IN {<a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>, <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a>} &amp;&amp; <a link="impl-shared.Have52BitIPAAndPASpaceExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitIPAAndPASpaceExt()">Have52BitIPAAndPASpaceExt</a>() then</line>
<line>        walkparams.ds = VTCR_EL2.DS;</line>
<line>    else</line>
<line>        walkparams.ds = '0';</line>
<line>    if walkparams.tgx == <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a> &amp;&amp; <a link="impl-shared.Have52BitIPAAndPASpaceExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitIPAAndPASpaceExt()">Have52BitIPAAndPASpaceExt</a>() then</line>
<line>        walkparams.sl2 = VTCR_EL2.SL2 AND VTCR_EL2.DS;</line>
<line>    else</line>
<line>        walkparams.sl2 = '0';</line>
<line>    walkparams.cmow = if <a link="impl-shared.HaveFeatCMOW.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatCMOW()">HaveFeatCMOW</a>() &amp;&amp; <a link="impl-aarch64.IsHCRXEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsHCRXEL2Enabled()">IsHCRXEL2Enabled</a>() then HCRX_EL2.CMOW else '0';</line>
<line>    if walkparams.d128 == '1' then</line>
<line>        walkparams.s2pie = '1';</line>
<line>    else</line>
<line>        walkparams.s2pie = if <a link="impl-shared.HaveS2PIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveS2PIExt()">HaveS2PIExt</a>() then VTCR_EL2.S2PIE else '0';</line>
<line>    walkparams.s2pir = if <a link="impl-shared.HaveS2PIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveS2PIExt()">HaveS2PIExt</a>() then S2PIR_EL2 else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>    if <a link="impl-shared.HaveTHExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTHExt()">HaveTHExt</a>() &amp;&amp; walkparams.d128 != '1' then</line>
<line>        walkparams.assuredonly = VTCR_EL2.AssuredOnly;</line>
<line>    else</line>
<line>        walkparams.assuredonly = '0';</line>
<line>    walkparams.tl0   = if <a link="impl-shared.HaveTHExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTHExt()">HaveTHExt</a>() then VTCR_EL2.TL0 else '0';</line>
<line>    walkparams.tl1   = if <a link="impl-shared.HaveTHExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTHExt()">HaveTHExt</a>() then VTCR_EL2.TL1 else '0';</line>
<line>    if <a link="impl-shared.HaveAccessFlagUpdateForTableExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAccessFlagUpdateForTableExt()">HaveAccessFlagUpdateForTableExt</a>() &amp;&amp; walkparams.ha == '1' then</line>
<line>        walkparams.haft = VTCR_EL2.HAFT;</line>
<line>    else</line>
<line>        walkparams.haft = '0';</line>
<line></line>
<line>    return walkparams;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.PAMax" mylink="aarch64.translation.vmsa_walkparams.AArch64.PAMax" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.PAMax()</line>
<line>// ===============</line>
<line>// Returns the IMPLEMENTATION DEFINED maximum number of bits capable of representing</line>
<line>// physical address for this processor</line>
<line></line>
<line link="AArch64.PAMax.0" hover="function: integer AArch64.PAMax()" conts="AArch64.PAMax">integer <anchor link="AArch64.PAMax.0" hover="function: integer AArch64.PAMax()">AArch64.PAMax</anchor>()</line>
<line>    return integer IMPLEMENTATION_DEFINED "Maximum Physical Address Size";</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.RLS2TTWParams" mylink="aarch64.translation.vmsa_walkparams.AArch64.RLS2TTWParams" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.RLS2TTWParams()</line>
<line>// =======================</line>
<line>// Gather walk parameters specific for Realm stage 2 translation</line>
<line></line>
<line>S2TTWParams AArch64.RLS2TTWParams(boolean s1aarch64)</line>
<line>    // Realm stage 2 walk parameters are similar to Non-secure</line>
<line>    S2TTWParams walkparams = AArch64.NSS2TTWParams(s1aarch64);</line>
<line>    walkparams.emec = if <a link="impl-shared.HaveFeatMEC.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatMEC()">HaveFeatMEC</a>() &amp;&amp; <a link="impl-aarch64.IsSCTLR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsSCTLR2EL2Enabled()">IsSCTLR2EL2Enabled</a>() then SCTLR2_EL2.EMEC else '0';</line>
<line>    return walkparams;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.S1DCacheEnabled" mylink="aarch64.translation.vmsa_walkparams.AArch64.S1DCacheEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1DCacheEnabled()</line>
<line>// =========================</line>
<line>// Determine cacheability of stage 1 data accesses</line>
<line></line>
<line link="AArch64.S1DCacheEnabled.1" hover="function: boolean AArch64.S1DCacheEnabled(Regime regime)" conts="AArch64.S1DCacheEnabled">boolean <anchor link="AArch64.S1DCacheEnabled.1" hover="function: boolean AArch64.S1DCacheEnabled(Regime regime)">AArch64.S1DCacheEnabled</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime)</line>
<line>    case regime of</line>
<line>        when <a link="Regime_EL3" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL3</a>  return SCTLR_EL3.C == '1';</line>
<line>        when <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>  return SCTLR_EL2.C == '1';</line>
<line>        when <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a> return SCTLR_EL2.C == '1';</line>
<line>        when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> return SCTLR_EL1.C == '1';</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.S1DecodeTG0" mylink="aarch64.translation.vmsa_walkparams.AArch64.S1DecodeTG0" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1DecodeTG0()</line>
<line>// =====================</line>
<line>// Decode stage 1 granule size configuration bits TG0</line>
<line></line>
<line link="AArch64.S1DecodeTG0.1" hover="function: TGx AArch64.S1DecodeTG0(bits(2) tg0_in)" conts="AArch64.S1DecodeTG0">TGx <anchor link="AArch64.S1DecodeTG0.1" hover="function: TGx AArch64.S1DecodeTG0(bits(2) tg0_in)">AArch64.S1DecodeTG0</anchor>(bits(2) tg0_in)</line>
<line>    bits(2) tg0 = tg0_in;</line>
<line>    <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tgx;</line>
<line></line>
<line>    if tg0 == '11' then</line>
<line>        tg0 = bits(2) IMPLEMENTATION_DEFINED "TG0 encoded granule size";</line>
<line></line>
<line>    case tg0 of</line>
<line>        when '00'   tgx = <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>;</line>
<line>        when '01'   tgx = <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a>;</line>
<line>        when '10'   tgx = <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a>;</line>
<line></line>
<line>    if !<a link="AArch64.HaveS1TG.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.HaveS1TG(TGx tgx)">AArch64.HaveS1TG</a>(tgx) then</line>
<line>        case bits(2) IMPLEMENTATION_DEFINED "TG0 encoded granule size" of</line>
<line>            when '00'   tgx = <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>;</line>
<line>            when '01'   tgx = <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a>;</line>
<line>            when '10'   tgx = <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a>;</line>
<line></line>
<line>    return tgx;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.S1DecodeTG1" mylink="aarch64.translation.vmsa_walkparams.AArch64.S1DecodeTG1" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1DecodeTG1()</line>
<line>// =====================</line>
<line>// Decode stage 1 granule size configuration bits TG1</line>
<line></line>
<line link="AArch64.S1DecodeTG1.1" hover="function: TGx AArch64.S1DecodeTG1(bits(2) tg1_in)" conts="AArch64.S1DecodeTG1">TGx <anchor link="AArch64.S1DecodeTG1.1" hover="function: TGx AArch64.S1DecodeTG1(bits(2) tg1_in)">AArch64.S1DecodeTG1</anchor>(bits(2) tg1_in)</line>
<line>    bits(2) tg1 = tg1_in;</line>
<line>    <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tgx;</line>
<line></line>
<line>    if tg1 == '00' then</line>
<line>        tg1 = bits(2) IMPLEMENTATION_DEFINED "TG1 encoded granule size";</line>
<line></line>
<line>    case tg1 of</line>
<line>        when '10'   tgx = <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>;</line>
<line>        when '11'   tgx = <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a>;</line>
<line>        when '01'   tgx = <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a>;</line>
<line></line>
<line>    if !<a link="AArch64.HaveS1TG.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.HaveS1TG(TGx tgx)">AArch64.HaveS1TG</a>(tgx) then</line>
<line>        case bits(2) IMPLEMENTATION_DEFINED "TG1 encoded granule size" of</line>
<line>            when '10'   tgx = <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>;</line>
<line>            when '11'   tgx = <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a>;</line>
<line>            when '01'   tgx = <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a>;</line>
<line></line>
<line>    return tgx;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.S1E0POEnabled" mylink="aarch64.translation.vmsa_walkparams.AArch64.S1E0POEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1E0POEnabled()</line>
<line>// =======================</line>
<line>// Determine whether stage 1 unprivileged permission overlay is enabled</line>
<line></line>
<line link="AArch64.S1E0POEnabled.2" hover="function: boolean AArch64.S1E0POEnabled(Regime regime, bit nv1)" conts="AArch64.S1E0POEnabled">boolean <anchor link="AArch64.S1E0POEnabled.2" hover="function: boolean AArch64.S1E0POEnabled(Regime regime, bit nv1)">AArch64.S1E0POEnabled</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bit nv1)</line>
<line>    assert <a link="impl-shared.HasUnprivileged.1" file="shared_pseudocode.xml" hover="function: boolean HasUnprivileged(Regime regime)">HasUnprivileged</a>(regime);</line>
<line></line>
<line>    if !<a link="impl-shared.HaveS1POExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveS1POExt()">HaveS1POExt</a>() then</line>
<line>        return FALSE;</line>
<line></line>
<line>    case regime of</line>
<line>        when <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a> return <a link="impl-aarch64.IsTCR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL2Enabled()">IsTCR2EL2Enabled</a>() &amp;&amp; TCR2_EL2.E0POE == '1';</line>
<line>        when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> return <a link="impl-aarch64.IsTCR2EL1Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL1Enabled()">IsTCR2EL1Enabled</a>() &amp;&amp; nv1 == '0' &amp;&amp; TCR2_EL1.E0POE == '1';</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.S1EPD" mylink="aarch64.translation.vmsa_walkparams.AArch64.S1EPD" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1EPD()</line>
<line>// ===============</line>
<line>// Determine whether stage 1 translation table walk is allowed for the VA range</line>
<line></line>
<line link="AArch64.S1EPD.2" hover="function: bit AArch64.S1EPD(Regime regime, bits(64) va)" conts="AArch64.S1EPD">bit <anchor link="AArch64.S1EPD.2" hover="function: bit AArch64.S1EPD(Regime regime, bits(64) va)">AArch64.S1EPD</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(64) va)</line>
<line>    assert <a link="impl-shared.HasUnprivileged.1" file="shared_pseudocode.xml" hover="function: boolean HasUnprivileged(Regime regime)">HasUnprivileged</a>(regime);</line>
<line>    varange = <a link="AArch64.GetVARange.1" file="shared_pseudocode.xml" hover="function: VARange AArch64.GetVARange(bits(64) va)">AArch64.GetVARange</a>(va);</line>
<line></line>
<line>    case regime of</line>
<line>        when <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a> return if varange == <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a> then TCR_EL2.EPD0 else TCR_EL2.EPD1;</line>
<line>        when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> return if varange == <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a> then TCR_EL1.EPD0 else TCR_EL1.EPD1;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.S1Enabled" mylink="aarch64.translation.vmsa_walkparams.AArch64.S1Enabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1Enabled()</line>
<line>// ===================</line>
<line>// Determine if stage 1 is enabled for the access type for this translation regime</line>
<line></line>
<line link="AArch64.S1Enabled.2" hover="function: boolean AArch64.S1Enabled(Regime regime, AccessType acctype)" conts="AArch64.S1Enabled">boolean <anchor link="AArch64.S1Enabled.2" hover="function: boolean AArch64.S1Enabled(Regime regime, AccessType acctype)">AArch64.S1Enabled</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, <a link="AccessType" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType</a> acctype)</line>
<line>    case regime of</line>
<line>        when <a link="Regime_EL3" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL3</a>  return SCTLR_EL3.M == '1';</line>
<line>        when <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>  return SCTLR_EL2.M == '1';</line>
<line>        when <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a> return SCTLR_EL2.M == '1';</line>
<line>        when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> return (!<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() || HCR_EL2.&lt;DC,TGE&gt; == '00') &amp;&amp; SCTLR_EL1.M == '1';</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.S1ICacheEnabled" mylink="aarch64.translation.vmsa_walkparams.AArch64.S1ICacheEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1ICacheEnabled()</line>
<line>// =========================</line>
<line>// Determine cacheability of stage 1 instruction fetches</line>
<line></line>
<line link="AArch64.S1ICacheEnabled.1" hover="function: boolean AArch64.S1ICacheEnabled(Regime regime)" conts="AArch64.S1ICacheEnabled">boolean <anchor link="AArch64.S1ICacheEnabled.1" hover="function: boolean AArch64.S1ICacheEnabled(Regime regime)">AArch64.S1ICacheEnabled</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime)</line>
<line>    case regime of</line>
<line>        when <a link="Regime_EL3" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL3</a>  return SCTLR_EL3.I == '1';</line>
<line>        when <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>  return SCTLR_EL2.I == '1';</line>
<line>        when <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a> return SCTLR_EL2.I == '1';</line>
<line>        when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> return SCTLR_EL1.I == '1';</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.S1MinTxSZ" mylink="aarch64.translation.vmsa_walkparams.AArch64.S1MinTxSZ" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1MinTxSZ()</line>
<line>// ===================</line>
<line>// Retrieve the minimum value of TxSZ indicating maximum input address size for stage 1</line>
<line></line>
<line link="AArch64.S1MinTxSZ.4" hover="function: integer AArch64.S1MinTxSZ(Regime regime, bit d128, bit ds, TGx tgx)" conts="AArch64.S1MinTxSZ">integer <anchor link="AArch64.S1MinTxSZ.4" hover="function: integer AArch64.S1MinTxSZ(Regime regime, bit d128, bit ds, TGx tgx)">AArch64.S1MinTxSZ</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bit d128, bit ds, <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tgx)</line>
<line>    if <a link="impl-shared.Have56BitVAExt.0" file="shared_pseudocode.xml" hover="function: boolean Have56BitVAExt()">Have56BitVAExt</a>() &amp;&amp; d128 == '1' then</line>
<line>        if <a link="impl-shared.HasUnprivileged.1" file="shared_pseudocode.xml" hover="function: boolean HasUnprivileged(Regime regime)">HasUnprivileged</a>(regime) then</line>
<line>            return 9;</line>
<line>        else</line>
<line>            return 8;</line>
<line>    if (<a link="impl-shared.Have52BitVAExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitVAExt()">Have52BitVAExt</a>() &amp;&amp; tgx == <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a>) || ds == '1' then</line>
<line>        return 12;</line>
<line></line>
<line>    return 16;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.S1POEnabled" mylink="aarch64.translation.vmsa_walkparams.AArch64.S1POEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1POEnabled()</line>
<line>// =====================</line>
<line>// Determine whether stage 1 privileged permission overlay is enabled</line>
<line></line>
<line link="AArch64.S1POEnabled.1" hover="function: boolean AArch64.S1POEnabled(Regime regime)" conts="AArch64.S1POEnabled">boolean <anchor link="AArch64.S1POEnabled.1" hover="function: boolean AArch64.S1POEnabled(Regime regime)">AArch64.S1POEnabled</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime)</line>
<line>    if !<a link="impl-shared.HaveS1POExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveS1POExt()">HaveS1POExt</a>() then</line>
<line>        return FALSE;</line>
<line></line>
<line>    case regime of</line>
<line>        when <a link="Regime_EL3" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL3</a>  return TCR_EL3.POE == '1';</line>
<line>        when <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>  return <a link="impl-aarch64.IsTCR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL2Enabled()">IsTCR2EL2Enabled</a>() &amp;&amp; TCR2_EL2.POE == '1';</line>
<line>        when <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a> return <a link="impl-aarch64.IsTCR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL2Enabled()">IsTCR2EL2Enabled</a>() &amp;&amp; TCR2_EL2.POE == '1';</line>
<line>        when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> return <a link="impl-aarch64.IsTCR2EL1Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL1Enabled()">IsTCR2EL1Enabled</a>() &amp;&amp; TCR2_EL1.POE == '1';</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.S1POR" mylink="aarch64.translation.vmsa_walkparams.AArch64.S1POR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1POR()</line>
<line>// ===============</line>
<line>// Identify stage 1 permissions overlay register for the acting translation regime</line>
<line></line>
<line>S1PORType AArch64.S1POR(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime)</line>
<line>    case regime of</line>
<line>        when <a link="Regime_EL3" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL3</a>  return POR_EL3;</line>
<line>        when <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>  return POR_EL2;</line>
<line>        when <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a> return POR_EL2;</line>
<line>        when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> return POR_EL1;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.S1TTB" mylink="aarch64.translation.vmsa_walkparams.AArch64.S1TTB" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1TTB()</line>
<line>// ===============</line>
<line>// Identify stage 1 table base register's BADDR for the acting translation regime</line>
<line></line>
<line link="AArch64.S1TTB.2" hover="function: bits(64) AArch64.S1TTB(Regime regime, bits(64) va)" conts="AArch64.S1TTB">bits(64) <anchor link="AArch64.S1TTB.2" hover="function: bits(64) AArch64.S1TTB(Regime regime, bits(64) va)">AArch64.S1TTB</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime, bits(64) va)</line>
<line>    varange = <a link="AArch64.GetVARange.1" file="shared_pseudocode.xml" hover="function: VARange AArch64.GetVARange(bits(64) va)">AArch64.GetVARange</a>(va);</line>
<line></line>
<line>    case regime of</line>
<line>        when <a link="Regime_EL3" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL3</a>  return <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(TTBR0_EL3.BADDR, 64);</line>
<line>        when <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>  return <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(TTBR0_EL2.BADDR, 64);</line>
<line>        when <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a></line>
<line>            if varange == <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a> then</line>
<line>                return <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(TTBR0_EL2.BADDR, 64);</line>
<line>            else</line>
<line>                return <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(TTBR1_EL2.BADDR, 64);</line>
<line>        when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a></line>
<line>            if varange == <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a> then</line>
<line>                return <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(TTBR0_EL1.BADDR, 64);</line>
<line>            else</line>
<line>                return <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(TTBR1_EL1.BADDR, 64);</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.S1TTWParamsEL10" mylink="aarch64.translation.vmsa_walkparams.AArch64.S1TTWParamsEL10" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1TTWParamsEL10()</line>
<line>// =========================</line>
<line>// Gather stage 1 translation table walk parameters for EL1&amp;0 regime</line>
<line>// (with EL2 enabled or disabled)</line>
<line></line>
<line>S1TTWParams AArch64.S1TTWParamsEL10(<a link="VARange" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange</a> varange)</line>
<line>    S1TTWParams walkparams;</line>
<line></line>
<line>    if <a link="impl-shared.Have128BitDescriptorExt.0" file="shared_pseudocode.xml" hover="function: boolean Have128BitDescriptorExt()">Have128BitDescriptorExt</a>() &amp;&amp; <a link="impl-aarch64.IsTCR2EL1Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL1Enabled()">IsTCR2EL1Enabled</a>() then</line>
<line>        walkparams.d128 = TCR2_EL1.D128;</line>
<line>    else</line>
<line>        walkparams.d128 = '0';</line>
<line>    if varange == <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a> then</line>
<line>        walkparams.tgx   = <a link="AArch64.S1DecodeTG0.1" file="shared_pseudocode.xml" hover="function: TGx AArch64.S1DecodeTG0(bits(2) tg0_in)">AArch64.S1DecodeTG0</a>(TCR_EL1.TG0);</line>
<line>        walkparams.txsz  = TCR_EL1.T0SZ;</line>
<line>        walkparams.irgn  = TCR_EL1.IRGN0;</line>
<line>        walkparams.orgn  = TCR_EL1.ORGN0;</line>
<line>        walkparams.sh    = TCR_EL1.SH0;</line>
<line>        walkparams.tbi   = TCR_EL1.TBI0;</line>
<line></line>
<line>        walkparams.nfd   = if <a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() || <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() then TCR_EL1.NFD0  else '0';</line>
<line>        walkparams.tbid  = if <a link="impl-aarch64.HavePACExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePACExt()">HavePACExt</a>()           then TCR_EL1.TBID0 else '0';</line>
<line>        walkparams.e0pd  = if <a link="impl-shared.HaveE0PDExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveE0PDExt()">HaveE0PDExt</a>()          then TCR_EL1.E0PD0 else '0';</line>
<line>        walkparams.hpd   = if <a link="AArch64.HaveHPDExt.0" file="shared_pseudocode.xml" hover="function: boolean AArch64.HaveHPDExt()">AArch64.HaveHPDExt</a>()   then TCR_EL1.HPD0  else '0';</line>
<line>        walkparams.mtx   = if <a link="impl-shared.HaveMTE4Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE4Ext()">HaveMTE4Ext</a>() then TCR_EL1.MTX0 else '0';</line>
<line>        walkparams.skl   = if walkparams.d128 == '1' then TTBR0_EL1.SKL else '00';</line>
<line>        walkparams.disch = if walkparams.d128 == '1' then TCR2_EL1.DisCH0 else '0';</line>
<line>    else</line>
<line>        walkparams.tgx   = <a link="AArch64.S1DecodeTG1.1" file="shared_pseudocode.xml" hover="function: TGx AArch64.S1DecodeTG1(bits(2) tg1_in)">AArch64.S1DecodeTG1</a>(TCR_EL1.TG1);</line>
<line>        walkparams.txsz  = TCR_EL1.T1SZ;</line>
<line>        walkparams.irgn  = TCR_EL1.IRGN1;</line>
<line>        walkparams.orgn  = TCR_EL1.ORGN1;</line>
<line>        walkparams.sh    = TCR_EL1.SH1;</line>
<line>        walkparams.tbi   = TCR_EL1.TBI1;</line>
<line></line>
<line>        walkparams.nfd   = if <a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() || <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() then TCR_EL1.NFD1  else '0';</line>
<line>        walkparams.tbid  = if <a link="impl-aarch64.HavePACExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePACExt()">HavePACExt</a>()           then TCR_EL1.TBID1 else '0';</line>
<line>        walkparams.e0pd  = if <a link="impl-shared.HaveE0PDExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveE0PDExt()">HaveE0PDExt</a>()          then TCR_EL1.E0PD1 else '0';</line>
<line>        walkparams.hpd   = if <a link="AArch64.HaveHPDExt.0" file="shared_pseudocode.xml" hover="function: boolean AArch64.HaveHPDExt()">AArch64.HaveHPDExt</a>()   then TCR_EL1.HPD1  else '0';</line>
<line>        walkparams.mtx   = if <a link="impl-shared.HaveMTE4Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE4Ext()">HaveMTE4Ext</a>()          then TCR_EL1.MTX1 else '0';</line>
<line>        walkparams.skl   = if walkparams.d128 == '1' then TTBR1_EL1.SKL else '00';</line>
<line>        walkparams.disch = if walkparams.d128 == '1' then TCR2_EL1.DisCH1 else '0';</line>
<line></line>
<line>    walkparams.mair = MAIR_EL1;</line>
<line>    if <a link="impl-shared.HaveAIEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAIEExt()">HaveAIEExt</a>() then</line>
<line>        walkparams.mair2 = MAIR2_EL1;</line>
<line>    walkparams.aie  = if <a link="impl-shared.HaveAIEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAIEExt()">HaveAIEExt</a>() &amp;&amp; <a link="impl-aarch64.IsTCR2EL1Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL1Enabled()">IsTCR2EL1Enabled</a>() then TCR2_EL1.AIE else '0';</line>
<line>    walkparams.wxn  = SCTLR_EL1.WXN;</line>
<line>    walkparams.ps   = TCR_EL1.IPS;</line>
<line>    walkparams.ee   = SCTLR_EL1.EE;</line>
<line>    if (<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; (!<a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() || <a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>())) then</line>
<line>        walkparams.sif = SCR_EL3.SIF;</line>
<line>    else</line>
<line>        walkparams.sif = '0';</line>
<line></line>
<line>    if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        walkparams.dc  = HCR_EL2.DC;</line>
<line>        walkparams.dct = if <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() then HCR_EL2.DCT else '0';</line>
<line></line>
<line>    if <a link="impl-shared.HaveTrapLoadStoreMultipleDeviceExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTrapLoadStoreMultipleDeviceExt()">HaveTrapLoadStoreMultipleDeviceExt</a>() then</line>
<line>        walkparams.ntlsmd = SCTLR_EL1.nTLSMD;</line>
<line>    else</line>
<line>        walkparams.ntlsmd = '1';</line>
<line></line>
<line>    if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        if HCR_EL2.&lt;NV,NV1&gt; == '01' then</line>
<line>            case <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_NVNV1" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_NVNV1</a>) of</line>
<line>                when <a link="Constraint_NVNV1_00" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NVNV1_00</a> walkparams.nv1 = '0';</line>
<line>                when <a link="Constraint_NVNV1_01" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NVNV1_01</a> walkparams.nv1 = '1';</line>
<line>                when <a link="Constraint_NVNV1_11" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NVNV1_11</a> walkparams.nv1 = '1';</line>
<line>        else</line>
<line>            walkparams.nv1 = HCR_EL2.NV1;</line>
<line>    else</line>
<line>        walkparams.nv1 = '0';</line>
<line></line>
<line>    walkparams.cmow = if <a link="impl-shared.HaveFeatCMOW.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatCMOW()">HaveFeatCMOW</a>()            then SCTLR_EL1.CMOW else '0';</line>
<line>    walkparams.ha   = if <a link="impl-shared.HaveAccessFlagUpdateExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAccessFlagUpdateExt()">HaveAccessFlagUpdateExt</a>() then TCR_EL1.HA else '0';</line>
<line>    walkparams.hd   = if <a link="impl-shared.HaveDirtyBitModifierExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDirtyBitModifierExt()">HaveDirtyBitModifierExt</a>() then TCR_EL1.HD else '0';</line>
<line>    if walkparams.tgx IN {<a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>, <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a>} &amp;&amp; <a link="impl-shared.Have52BitIPAAndPASpaceExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitIPAAndPASpaceExt()">Have52BitIPAAndPASpaceExt</a>() then</line>
<line>        walkparams.ds = TCR_EL1.DS;</line>
<line>    else</line>
<line>        walkparams.ds = '0';</line>
<line>    if walkparams.d128 == '1' then</line>
<line>        walkparams.pie = '1';</line>
<line>    else</line>
<line>        walkparams.pie = if <a link="impl-shared.HaveS1PIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveS1PIExt()">HaveS1PIExt</a>() &amp;&amp; <a link="impl-aarch64.IsTCR2EL1Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL1Enabled()">IsTCR2EL1Enabled</a>() then TCR2_EL1.PIE else '0';</line>
<line>    if <a link="impl-shared.HaveS1PIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveS1PIExt()">HaveS1PIExt</a>() then</line>
<line>        walkparams.pir = PIR_EL1;</line>
<line>        if walkparams.nv1 != '1'then</line>
<line>            walkparams.pire0 = PIRE0_EL1;</line>
<line>    if <a link="impl-shared.HavePAN3Ext.0" file="shared_pseudocode.xml" hover="function: boolean HavePAN3Ext()">HavePAN3Ext</a>() then</line>
<line>        walkparams.epan = if walkparams.pie == '0' then SCTLR_EL1.EPAN else '1';</line>
<line>    else</line>
<line>        walkparams.epan = '0';</line>
<line>    if <a link="impl-shared.HaveTHExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTHExt()">HaveTHExt</a>() &amp;&amp; walkparams.d128 == '0' &amp;&amp; <a link="impl-aarch64.IsTCR2EL1Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL1Enabled()">IsTCR2EL1Enabled</a>() then</line>
<line>        walkparams.pnch = TCR2_EL1.PnCH;</line>
<line>    else</line>
<line>        walkparams.pnch = '0';</line>
<line>    if <a link="impl-shared.HaveAccessFlagUpdateForTableExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAccessFlagUpdateForTableExt()">HaveAccessFlagUpdateForTableExt</a>() &amp;&amp; walkparams.ha == '1' &amp;&amp; <a link="impl-aarch64.IsTCR2EL1Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL1Enabled()">IsTCR2EL1Enabled</a>() then</line>
<line>        walkparams.haft = TCR2_EL1.HAFT;</line>
<line>    else</line>
<line>        walkparams.haft = '0';</line>
<line>    walkparams.emec = if <a link="impl-shared.HaveFeatMEC.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatMEC()">HaveFeatMEC</a>() &amp;&amp; <a link="impl-aarch64.IsSCTLR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsSCTLR2EL2Enabled()">IsSCTLR2EL2Enabled</a>() then SCTLR2_EL2.EMEC else '0';</line>
<line></line>
<line>    return walkparams;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.S1TTWParamsEL2" mylink="aarch64.translation.vmsa_walkparams.AArch64.S1TTWParamsEL2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1TTWParamsEL2()</line>
<line>// ========================</line>
<line>// Gather stage 1 translation table walk parameters for EL2 regime</line>
<line></line>
<line>S1TTWParams AArch64.S1TTWParamsEL2(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss)</line>
<line>    S1TTWParams walkparams;</line>
<line></line>
<line>    walkparams.tgx  = <a link="AArch64.S1DecodeTG0.1" file="shared_pseudocode.xml" hover="function: TGx AArch64.S1DecodeTG0(bits(2) tg0_in)">AArch64.S1DecodeTG0</a>(TCR_EL2.TG0);</line>
<line>    walkparams.txsz = TCR_EL2.T0SZ;</line>
<line>    walkparams.ps   = TCR_EL2.PS;</line>
<line>    walkparams.irgn = TCR_EL2.IRGN0;</line>
<line>    walkparams.orgn = TCR_EL2.ORGN0;</line>
<line>    walkparams.sh   = TCR_EL2.SH0;</line>
<line>    walkparams.tbi  = TCR_EL2.TBI;</line>
<line>    walkparams.mair = MAIR_EL2;</line>
<line>    if <a link="impl-shared.HaveAIEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAIEExt()">HaveAIEExt</a>() then</line>
<line>        walkparams.mair2 = MAIR2_EL2;</line>
<line>    walkparams.aie  = if <a link="impl-shared.HaveAIEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAIEExt()">HaveAIEExt</a>() &amp;&amp; <a link="impl-aarch64.IsTCR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL2Enabled()">IsTCR2EL2Enabled</a>() then TCR2_EL2.AIE else '0';</line>
<line>    walkparams.wxn  = SCTLR_EL2.WXN;</line>
<line>    walkparams.ee   = SCTLR_EL2.EE;</line>
<line>    if (<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; (!<a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() || <a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>())) then</line>
<line>        walkparams.sif = SCR_EL3.SIF;</line>
<line>    else</line>
<line>        walkparams.sif = '0';</line>
<line></line>
<line>    walkparams.tbid = if <a link="impl-aarch64.HavePACExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePACExt()">HavePACExt</a>()              then TCR_EL2.TBID else '0';</line>
<line>    walkparams.hpd  = if <a link="AArch64.HaveHPDExt.0" file="shared_pseudocode.xml" hover="function: boolean AArch64.HaveHPDExt()">AArch64.HaveHPDExt</a>()      then TCR_EL2.HPD  else '0';</line>
<line>    walkparams.ha   = if <a link="impl-shared.HaveAccessFlagUpdateExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAccessFlagUpdateExt()">HaveAccessFlagUpdateExt</a>() then TCR_EL2.HA   else '0';</line>
<line>    walkparams.hd   = if <a link="impl-shared.HaveDirtyBitModifierExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDirtyBitModifierExt()">HaveDirtyBitModifierExt</a>() then TCR_EL2.HD   else '0';</line>
<line>    if walkparams.tgx IN {<a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>, <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a>} &amp;&amp; <a link="impl-shared.Have52BitIPAAndPASpaceExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitIPAAndPASpaceExt()">Have52BitIPAAndPASpaceExt</a>() then</line>
<line>        walkparams.ds = TCR_EL2.DS;</line>
<line>    else</line>
<line>        walkparams.ds = '0';</line>
<line>    walkparams.pie = if <a link="impl-shared.HaveS1PIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveS1PIExt()">HaveS1PIExt</a>() &amp;&amp; <a link="impl-aarch64.IsTCR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL2Enabled()">IsTCR2EL2Enabled</a>() then TCR2_EL2.PIE else '0';</line>
<line>    if <a link="impl-shared.HaveS1PIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveS1PIExt()">HaveS1PIExt</a>() then</line>
<line>        walkparams.pir = PIR_EL2;</line>
<line>    walkparams.mtx  = if <a link="impl-shared.HaveMTE4Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE4Ext()">HaveMTE4Ext</a>()             then TCR_EL2.MTX else '0';</line>
<line>    walkparams.pnch = if <a link="impl-shared.HaveTHExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTHExt()">HaveTHExt</a>() &amp;&amp; <a link="impl-aarch64.IsTCR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL2Enabled()">IsTCR2EL2Enabled</a>() then TCR2_EL2.PnCH else '0';</line>
<line>    if <a link="impl-shared.HaveAccessFlagUpdateForTableExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAccessFlagUpdateForTableExt()">HaveAccessFlagUpdateForTableExt</a>() &amp;&amp; walkparams.ha == '1' &amp;&amp; <a link="impl-aarch64.IsTCR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL2Enabled()">IsTCR2EL2Enabled</a>() then</line>
<line>        walkparams.haft = TCR2_EL2.HAFT;</line>
<line>    else</line>
<line>        walkparams.haft = '0';</line>
<line>    walkparams.emec = if <a link="impl-shared.HaveFeatMEC.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatMEC()">HaveFeatMEC</a>() &amp;&amp; <a link="impl-aarch64.IsSCTLR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsSCTLR2EL2Enabled()">IsSCTLR2EL2Enabled</a>() then SCTLR2_EL2.EMEC else '0';</line>
<line>    if <a link="impl-shared.HaveFeatMEC.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatMEC()">HaveFeatMEC</a>() &amp;&amp; ss == <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a> &amp;&amp; <a link="impl-aarch64.IsTCR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL2Enabled()">IsTCR2EL2Enabled</a>() then</line>
<line>        walkparams.amec = TCR2_EL2.AMEC0;</line>
<line>    else</line>
<line>        walkparams.amec = '0';</line>
<line></line>
<line>    return walkparams;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.S1TTWParamsEL20" mylink="aarch64.translation.vmsa_walkparams.AArch64.S1TTWParamsEL20" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1TTWParamsEL20()</line>
<line>// =========================</line>
<line>// Gather stage 1 translation table walk parameters for EL2&amp;0 regime</line>
<line></line>
<line>S1TTWParams AArch64.S1TTWParamsEL20(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss, <a link="VARange" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange</a> varange)</line>
<line>    S1TTWParams walkparams;</line>
<line></line>
<line>    if <a link="impl-shared.Have128BitDescriptorExt.0" file="shared_pseudocode.xml" hover="function: boolean Have128BitDescriptorExt()">Have128BitDescriptorExt</a>() &amp;&amp; <a link="impl-aarch64.IsTCR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL2Enabled()">IsTCR2EL2Enabled</a>() then</line>
<line>        walkparams.d128 = TCR2_EL2.D128;</line>
<line>    else</line>
<line>        walkparams.d128 = '0';</line>
<line>    if varange == <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a> then</line>
<line>        walkparams.tgx   = <a link="AArch64.S1DecodeTG0.1" file="shared_pseudocode.xml" hover="function: TGx AArch64.S1DecodeTG0(bits(2) tg0_in)">AArch64.S1DecodeTG0</a>(TCR_EL2.TG0);</line>
<line>        walkparams.txsz  = TCR_EL2.T0SZ;</line>
<line>        walkparams.irgn  = TCR_EL2.IRGN0;</line>
<line>        walkparams.orgn  = TCR_EL2.ORGN0;</line>
<line>        walkparams.sh    = TCR_EL2.SH0;</line>
<line>        walkparams.tbi   = TCR_EL2.TBI0;</line>
<line></line>
<line>        walkparams.nfd   = if <a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() || <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() then TCR_EL2.NFD0  else '0';</line>
<line>        walkparams.tbid  = if <a link="impl-aarch64.HavePACExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePACExt()">HavePACExt</a>()           then TCR_EL2.TBID0 else '0';</line>
<line>        walkparams.e0pd  = if <a link="impl-shared.HaveE0PDExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveE0PDExt()">HaveE0PDExt</a>()          then TCR_EL2.E0PD0 else '0';</line>
<line>        walkparams.hpd   = if <a link="AArch64.HaveHPDExt.0" file="shared_pseudocode.xml" hover="function: boolean AArch64.HaveHPDExt()">AArch64.HaveHPDExt</a>()   then TCR_EL2.HPD0  else '0';</line>
<line>        walkparams.mtx   = if <a link="impl-shared.HaveMTE4Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE4Ext()">HaveMTE4Ext</a>()          then TCR_EL2.MTX0 else '0';</line>
<line>        walkparams.skl   = if walkparams.d128 == '1' then TTBR0_EL2.SKL else '00';</line>
<line>        walkparams.disch = if walkparams.d128 == '1' then TCR2_EL2.DisCH0 else '0';</line>
<line>    else</line>
<line>        walkparams.tgx   = <a link="AArch64.S1DecodeTG1.1" file="shared_pseudocode.xml" hover="function: TGx AArch64.S1DecodeTG1(bits(2) tg1_in)">AArch64.S1DecodeTG1</a>(TCR_EL2.TG1);</line>
<line>        walkparams.txsz  = TCR_EL2.T1SZ;</line>
<line>        walkparams.irgn  = TCR_EL2.IRGN1;</line>
<line>        walkparams.orgn  = TCR_EL2.ORGN1;</line>
<line>        walkparams.sh    = TCR_EL2.SH1;</line>
<line>        walkparams.tbi   = TCR_EL2.TBI1;</line>
<line></line>
<line>        walkparams.nfd   = if <a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() || <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() then TCR_EL2.NFD1  else '0';</line>
<line>        walkparams.tbid  = if <a link="impl-aarch64.HavePACExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePACExt()">HavePACExt</a>()           then TCR_EL2.TBID1 else '0';</line>
<line>        walkparams.e0pd  = if <a link="impl-shared.HaveE0PDExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveE0PDExt()">HaveE0PDExt</a>()          then TCR_EL2.E0PD1 else '0';</line>
<line>        walkparams.hpd   = if <a link="AArch64.HaveHPDExt.0" file="shared_pseudocode.xml" hover="function: boolean AArch64.HaveHPDExt()">AArch64.HaveHPDExt</a>()   then TCR_EL2.HPD1  else '0';</line>
<line>        walkparams.mtx   = if <a link="impl-shared.HaveMTE4Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE4Ext()">HaveMTE4Ext</a>()          then TCR_EL2.MTX1 else '0';</line>
<line>        walkparams.skl   = if walkparams.d128 == '1' then TTBR1_EL2.SKL else '00';</line>
<line>        walkparams.disch = if walkparams.d128 == '1' then TCR2_EL2.DisCH1 else '0';</line>
<line>    walkparams.mair = MAIR_EL2;</line>
<line>    if <a link="impl-shared.HaveAIEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAIEExt()">HaveAIEExt</a>() then</line>
<line>        walkparams.mair2 = MAIR2_EL2;</line>
<line>    walkparams.aie  = if <a link="impl-shared.HaveAIEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAIEExt()">HaveAIEExt</a>() &amp;&amp; <a link="impl-aarch64.IsTCR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL2Enabled()">IsTCR2EL2Enabled</a>() then TCR2_EL2.AIE else '0';</line>
<line>    walkparams.wxn  = SCTLR_EL2.WXN;</line>
<line>    walkparams.ps   = TCR_EL2.IPS;</line>
<line>    walkparams.ee   = SCTLR_EL2.EE;</line>
<line>    if (<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; (!<a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() || <a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>())) then</line>
<line>        walkparams.sif = SCR_EL3.SIF;</line>
<line>    else</line>
<line>        walkparams.sif = '0';</line>
<line></line>
<line>    if <a link="impl-shared.HaveTrapLoadStoreMultipleDeviceExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTrapLoadStoreMultipleDeviceExt()">HaveTrapLoadStoreMultipleDeviceExt</a>() then</line>
<line>        walkparams.ntlsmd = SCTLR_EL2.nTLSMD;</line>
<line>    else</line>
<line>        walkparams.ntlsmd = '1';</line>
<line></line>
<line>    walkparams.cmow = if <a link="impl-shared.HaveFeatCMOW.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatCMOW()">HaveFeatCMOW</a>()            then SCTLR_EL2.CMOW else '0';</line>
<line>    walkparams.ha   = if <a link="impl-shared.HaveAccessFlagUpdateExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAccessFlagUpdateExt()">HaveAccessFlagUpdateExt</a>() then TCR_EL2.HA else '0';</line>
<line>    walkparams.hd   = if <a link="impl-shared.HaveDirtyBitModifierExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDirtyBitModifierExt()">HaveDirtyBitModifierExt</a>() then TCR_EL2.HD else '0';</line>
<line>    if walkparams.tgx IN {<a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>, <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a>} &amp;&amp; <a link="impl-shared.Have52BitIPAAndPASpaceExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitIPAAndPASpaceExt()">Have52BitIPAAndPASpaceExt</a>() then</line>
<line>        walkparams.ds = TCR_EL2.DS;</line>
<line>    else</line>
<line>        walkparams.ds = '0';</line>
<line>    if walkparams.d128 == '1' then</line>
<line>        walkparams.pie = '1';</line>
<line>    else</line>
<line>        walkparams.pie = if <a link="impl-shared.HaveS1PIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveS1PIExt()">HaveS1PIExt</a>() &amp;&amp; <a link="impl-aarch64.IsTCR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL2Enabled()">IsTCR2EL2Enabled</a>() then TCR2_EL2.PIE else '0';</line>
<line>    if <a link="impl-shared.HaveS1PIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveS1PIExt()">HaveS1PIExt</a>() then</line>
<line>        walkparams.pir   = PIR_EL2;</line>
<line>        walkparams.pire0 = PIRE0_EL2;</line>
<line>    if <a link="impl-shared.HavePAN3Ext.0" file="shared_pseudocode.xml" hover="function: boolean HavePAN3Ext()">HavePAN3Ext</a>() then</line>
<line>        walkparams.epan = if walkparams.pie == '0' then SCTLR_EL2.EPAN else '1';</line>
<line>    else</line>
<line>        walkparams.epan = '0';</line>
<line>    if <a link="impl-shared.HaveTHExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTHExt()">HaveTHExt</a>() &amp;&amp; walkparams.d128 == '0' &amp;&amp; <a link="impl-aarch64.IsTCR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL2Enabled()">IsTCR2EL2Enabled</a>() then</line>
<line>        walkparams.pnch = TCR2_EL2.PnCH;</line>
<line>    else</line>
<line>        walkparams.pnch = '0';</line>
<line>    if <a link="impl-shared.HaveAccessFlagUpdateForTableExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAccessFlagUpdateForTableExt()">HaveAccessFlagUpdateForTableExt</a>() &amp;&amp; walkparams.ha == '1' &amp;&amp; <a link="impl-aarch64.IsTCR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL2Enabled()">IsTCR2EL2Enabled</a>() then</line>
<line>        walkparams.haft = TCR2_EL2.HAFT;</line>
<line>    else</line>
<line>        walkparams.haft = '0';</line>
<line>    walkparams.emec = if <a link="impl-shared.HaveFeatMEC.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatMEC()">HaveFeatMEC</a>() &amp;&amp; <a link="impl-aarch64.IsSCTLR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsSCTLR2EL2Enabled()">IsSCTLR2EL2Enabled</a>() then SCTLR2_EL2.EMEC else '0';</line>
<line>    if <a link="impl-shared.HaveFeatMEC.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatMEC()">HaveFeatMEC</a>() &amp;&amp; ss == <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a> &amp;&amp; <a link="impl-aarch64.IsTCR2EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsTCR2EL2Enabled()">IsTCR2EL2Enabled</a>() then</line>
<line>        walkparams.amec = if varange == <a link="VARange_LOWER" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</a> then TCR2_EL2.AMEC0 else TCR2_EL2.AMEC1;</line>
<line>    else</line>
<line>        walkparams.amec = '0';</line>
<line></line>
<line>    return walkparams;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.S1TTWParamsEL3" mylink="aarch64.translation.vmsa_walkparams.AArch64.S1TTWParamsEL3" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S1TTWParamsEL3()</line>
<line>// ========================</line>
<line>// Gather stage 1 translation table walk parameters for EL3 regime</line>
<line></line>
<line>S1TTWParams AArch64.S1TTWParamsEL3()</line>
<line>    S1TTWParams walkparams;</line>
<line></line>
<line>    walkparams.tgx  = <a link="AArch64.S1DecodeTG0.1" file="shared_pseudocode.xml" hover="function: TGx AArch64.S1DecodeTG0(bits(2) tg0_in)">AArch64.S1DecodeTG0</a>(TCR_EL3.TG0);</line>
<line>    walkparams.txsz = TCR_EL3.T0SZ;</line>
<line>    walkparams.ps   = TCR_EL3.PS;</line>
<line>    walkparams.irgn = TCR_EL3.IRGN0;</line>
<line>    walkparams.orgn = TCR_EL3.ORGN0;</line>
<line>    walkparams.sh   = TCR_EL3.SH0;</line>
<line>    walkparams.tbi  = TCR_EL3.TBI;</line>
<line>    walkparams.mair = MAIR_EL3;</line>
<line>    if <a link="impl-shared.HaveAIEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAIEExt()">HaveAIEExt</a>() then</line>
<line>        walkparams.mair2 = MAIR2_EL3;</line>
<line>    walkparams.aie  = if <a link="impl-shared.HaveAIEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAIEExt()">HaveAIEExt</a>() then TCR_EL3.AIE else '0';</line>
<line>    walkparams.wxn  = SCTLR_EL3.WXN;</line>
<line>    walkparams.ee   = SCTLR_EL3.EE;</line>
<line>    walkparams.sif = if !<a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() || <a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>() then SCR_EL3.SIF else '0';</line>
<line></line>
<line>    walkparams.tbid = if <a link="impl-aarch64.HavePACExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePACExt()">HavePACExt</a>()              then TCR_EL3.TBID else '0';</line>
<line>    walkparams.hpd  = if <a link="AArch64.HaveHPDExt.0" file="shared_pseudocode.xml" hover="function: boolean AArch64.HaveHPDExt()">AArch64.HaveHPDExt</a>()      then TCR_EL3.HPD  else '0';</line>
<line>    walkparams.ha   = if <a link="impl-shared.HaveAccessFlagUpdateExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAccessFlagUpdateExt()">HaveAccessFlagUpdateExt</a>() then TCR_EL3.HA   else '0';</line>
<line>    walkparams.hd   = if <a link="impl-shared.HaveDirtyBitModifierExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDirtyBitModifierExt()">HaveDirtyBitModifierExt</a>() then TCR_EL3.HD   else '0';</line>
<line>    if walkparams.tgx IN {<a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>, <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a>} &amp;&amp; <a link="impl-shared.Have52BitIPAAndPASpaceExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitIPAAndPASpaceExt()">Have52BitIPAAndPASpaceExt</a>() then</line>
<line>        walkparams.ds = TCR_EL3.DS;</line>
<line>    else</line>
<line>        walkparams.ds = '0';</line>
<line>    walkparams.d128  = if <a link="impl-shared.Have128BitDescriptorExt.0" file="shared_pseudocode.xml" hover="function: boolean Have128BitDescriptorExt()">Have128BitDescriptorExt</a>() then TCR_EL3.D128 else '0';</line>
<line>    walkparams.skl   = if walkparams.d128 == '1' then TTBR0_EL3.SKL else '00';</line>
<line>    walkparams.disch = if walkparams.d128 == '1' then TCR_EL3.DisCH0 else '0';</line>
<line>    if walkparams.d128 == '1' then</line>
<line>        walkparams.pie = '1';</line>
<line>    else</line>
<line>        walkparams.pie = if <a link="impl-shared.HaveS1PIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveS1PIExt()">HaveS1PIExt</a>() then TCR_EL3.PIE else '0';</line>
<line>    if <a link="impl-shared.HaveS1PIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveS1PIExt()">HaveS1PIExt</a>() then</line>
<line>        walkparams.pir = PIR_EL3;</line>
<line>    walkparams.mtx  = if <a link="impl-shared.HaveMTE4Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE4Ext()">HaveMTE4Ext</a>()             then TCR_EL3.MTX else '0';</line>
<line>    if <a link="impl-shared.HaveTHExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTHExt()">HaveTHExt</a>() &amp;&amp; walkparams.d128 == '0' then</line>
<line>        walkparams.pnch = TCR_EL3.PnCH;</line>
<line>    else</line>
<line>        walkparams.pnch = '0';</line>
<line>    if <a link="impl-shared.HaveAccessFlagUpdateForTableExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAccessFlagUpdateForTableExt()">HaveAccessFlagUpdateForTableExt</a>() &amp;&amp; walkparams.ha == '1' then</line>
<line>        walkparams.haft = TCR_EL3.HAFT;</line>
<line>    else</line>
<line>        walkparams.haft = '0';</line>
<line>    walkparams.emec = if <a link="impl-shared.HaveFeatMEC.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatMEC()">HaveFeatMEC</a>() then SCTLR2_EL3.EMEC else '0';</line>
<line></line>
<line>    return walkparams;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.S2DecodeTG0" mylink="aarch64.translation.vmsa_walkparams.AArch64.S2DecodeTG0" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S2DecodeTG0()</line>
<line>// =====================</line>
<line>// Decode stage 2 granule size configuration bits TG0</line>
<line></line>
<line link="AArch64.S2DecodeTG0.1" hover="function: TGx AArch64.S2DecodeTG0(bits(2) tg0_in)" conts="AArch64.S2DecodeTG0">TGx <anchor link="AArch64.S2DecodeTG0.1" hover="function: TGx AArch64.S2DecodeTG0(bits(2) tg0_in)">AArch64.S2DecodeTG0</anchor>(bits(2) tg0_in)</line>
<line>    bits(2) tg0 = tg0_in;</line>
<line>    <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tgx;</line>
<line></line>
<line>    if tg0 == '11' then</line>
<line>        tg0 = bits(2) IMPLEMENTATION_DEFINED "TG0 encoded granule size";</line>
<line></line>
<line>    case tg0 of</line>
<line>        when '00'   tgx = <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>;</line>
<line>        when '01'   tgx = <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a>;</line>
<line>        when '10'   tgx = <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a>;</line>
<line></line>
<line>    if !<a link="AArch64.HaveS2TG.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.HaveS2TG(TGx tgx)">AArch64.HaveS2TG</a>(tgx) then</line>
<line>        case bits(2) IMPLEMENTATION_DEFINED "TG0 encoded granule size" of</line>
<line>            when '00'   tgx = <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>;</line>
<line>            when '01'   tgx = <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a>;</line>
<line>            when '10'   tgx = <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a>;</line>
<line></line>
<line>    return tgx;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.S2MinTxSZ" mylink="aarch64.translation.vmsa_walkparams.AArch64.S2MinTxSZ" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.S2MinTxSZ()</line>
<line>// ===================</line>
<line>// Retrieve the minimum value of TxSZ indicating maximum input address size for stage 2</line>
<line></line>
<line link="AArch64.S2MinTxSZ.4" hover="function: integer AArch64.S2MinTxSZ(bit d128, bit ds, TGx tgx, boolean s1aarch64)" conts="AArch64.S2MinTxSZ">integer <anchor link="AArch64.S2MinTxSZ.4" hover="function: integer AArch64.S2MinTxSZ(bit d128, bit ds, TGx tgx, boolean s1aarch64)">AArch64.S2MinTxSZ</anchor>(bit d128, bit ds, <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tgx, boolean s1aarch64)</line>
<line>    ips = <a link="AArch64.PAMax.0" file="shared_pseudocode.xml" hover="function: integer AArch64.PAMax()">AArch64.PAMax</a>();</line>
<line></line>
<line>    if d128 == '0' then</line>
<line>        if <a link="impl-shared.Have52BitPAExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitPAExt()">Have52BitPAExt</a>() &amp;&amp; tgx != <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a> &amp;&amp; ds == '0' then</line>
<line>            ips = <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(48, <a link="AArch64.PAMax.0" file="shared_pseudocode.xml" hover="function: integer AArch64.PAMax()">AArch64.PAMax</a>());</line>
<line>        else</line>
<line>            ips = <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(52, <a link="AArch64.PAMax.0" file="shared_pseudocode.xml" hover="function: integer AArch64.PAMax()">AArch64.PAMax</a>());</line>
<line>    min_txsz = 64 - ips;</line>
<line>    if !s1aarch64 then</line>
<line>        // EL1 is AArch32</line>
<line>        min_txsz = <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(min_txsz, 24);</line>
<line></line>
<line>    return min_txsz;</line>
</pstext>
    </ps>
    <ps name="aarch64/translation/vmsa_walkparams/AArch64.SS2TTWParams" mylink="aarch64.translation.vmsa_walkparams.AArch64.SS2TTWParams" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.SS2TTWParams()</line>
<line>// ======================</line>
<line>// Gather walk parameters specific for secure stage 2 translation</line>
<line></line>
<line>S2TTWParams AArch64.SS2TTWParams(<a link="PASpace" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PASpace</a> ipaspace, boolean s1aarch64)</line>
<line>    S2TTWParams walkparams;</line>
<line></line>
<line>    walkparams.d128 = if <a link="impl-shared.Have128BitDescriptorExt.0" file="shared_pseudocode.xml" hover="function: boolean Have128BitDescriptorExt()">Have128BitDescriptorExt</a>() then VTCR_EL2.D128 else '0';</line>
<line>    if ipaspace == <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a> then</line>
<line>        walkparams.tgx  = <a link="AArch64.S2DecodeTG0.1" file="shared_pseudocode.xml" hover="function: TGx AArch64.S2DecodeTG0(bits(2) tg0_in)">AArch64.S2DecodeTG0</a>(VSTCR_EL2.TG0);</line>
<line>        walkparams.txsz = VSTCR_EL2.T0SZ;</line>
<line>        if walkparams.d128 == '1' then</line>
<line>            walkparams.skl = VSTTBR_EL2.SKL;</line>
<line>        else</line>
<line>            walkparams.sl0 = VSTCR_EL2.SL0;</line>
<line>        if walkparams.tgx == <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a> &amp;&amp; <a link="impl-shared.Have52BitIPAAndPASpaceExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitIPAAndPASpaceExt()">Have52BitIPAAndPASpaceExt</a>() then</line>
<line>            walkparams.sl2 = VSTCR_EL2.SL2 AND VTCR_EL2.DS;</line>
<line>        else</line>
<line>            walkparams.sl2 = '0';</line>
<line>    elsif ipaspace == <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a> then</line>
<line>        walkparams.tgx  = <a link="AArch64.S2DecodeTG0.1" file="shared_pseudocode.xml" hover="function: TGx AArch64.S2DecodeTG0(bits(2) tg0_in)">AArch64.S2DecodeTG0</a>(VTCR_EL2.TG0);</line>
<line>        walkparams.txsz = VTCR_EL2.T0SZ;</line>
<line>        if walkparams.d128 == '1' then</line>
<line>            walkparams.skl = VTTBR_EL2.SKL;</line>
<line>        else</line>
<line>            walkparams.sl0 = VTCR_EL2.SL0;</line>
<line>        if walkparams.tgx == <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a> &amp;&amp; <a link="impl-shared.Have52BitIPAAndPASpaceExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitIPAAndPASpaceExt()">Have52BitIPAAndPASpaceExt</a>() then</line>
<line>            walkparams.sl2 = VTCR_EL2.SL2 AND VTCR_EL2.DS;</line>
<line>        else</line>
<line>            walkparams.sl2 = '0';</line>
<line>    else</line>
<line>        <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    walkparams.sw   = VSTCR_EL2.SW;</line>
<line>    walkparams.nsw  = VTCR_EL2.NSW;</line>
<line>    walkparams.sa   = VSTCR_EL2.SA;</line>
<line>    walkparams.nsa  = VTCR_EL2.NSA;</line>
<line>    walkparams.vm   = HCR_EL2.VM OR HCR_EL2.DC;</line>
<line>    walkparams.ps   = VTCR_EL2.PS;</line>
<line>    walkparams.irgn = VTCR_EL2.IRGN0;</line>
<line>    walkparams.orgn = VTCR_EL2.ORGN0;</line>
<line>    walkparams.sh   = VTCR_EL2.SH0;</line>
<line>    walkparams.ee   = SCTLR_EL2.EE;</line>
<line></line>
<line>    walkparams.ptw = if HCR_EL2.TGE == '0'         then HCR_EL2.PTW else '0';</line>
<line>    walkparams.fwb = if <a link="impl-shared.HaveStage2MemAttrControl.0" file="shared_pseudocode.xml" hover="function: boolean HaveStage2MemAttrControl()">HaveStage2MemAttrControl</a>() then HCR_EL2.FWB else '0';</line>
<line>    walkparams.ha  = if <a link="impl-shared.HaveAccessFlagUpdateExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAccessFlagUpdateExt()">HaveAccessFlagUpdateExt</a>()  then VTCR_EL2.HA else '0';</line>
<line>    walkparams.hd  = if <a link="impl-shared.HaveDirtyBitModifierExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDirtyBitModifierExt()">HaveDirtyBitModifierExt</a>()  then VTCR_EL2.HD else '0';</line>
<line>    if walkparams.tgx IN {<a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>, <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a>} &amp;&amp; <a link="impl-shared.Have52BitIPAAndPASpaceExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitIPAAndPASpaceExt()">Have52BitIPAAndPASpaceExt</a>() then</line>
<line>        walkparams.ds = VTCR_EL2.DS;</line>
<line>    else</line>
<line>        walkparams.ds = '0';</line>
<line>    walkparams.cmow = if <a link="impl-shared.HaveFeatCMOW.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatCMOW()">HaveFeatCMOW</a>() &amp;&amp; <a link="impl-aarch64.IsHCRXEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsHCRXEL2Enabled()">IsHCRXEL2Enabled</a>() then HCRX_EL2.CMOW else '0';</line>
<line>    if walkparams.d128 == '1' then</line>
<line>        walkparams.s2pie = '1';</line>
<line>    else</line>
<line>        walkparams.s2pie = if <a link="impl-shared.HaveS2PIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveS2PIExt()">HaveS2PIExt</a>() then VTCR_EL2.S2PIE else '0';</line>
<line>    walkparams.s2pir = if <a link="impl-shared.HaveS2PIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveS2PIExt()">HaveS2PIExt</a>() then S2PIR_EL2 else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>    if <a link="impl-shared.HaveTHExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTHExt()">HaveTHExt</a>() &amp;&amp; walkparams.d128 != '1' then</line>
<line>        walkparams.assuredonly = VTCR_EL2.AssuredOnly;</line>
<line>    else</line>
<line>        walkparams.assuredonly = '0';</line>
<line>    walkparams.tl0   = if <a link="impl-shared.HaveTHExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTHExt()">HaveTHExt</a>() then VTCR_EL2.TL0 else '0';</line>
<line>    walkparams.tl1   = if <a link="impl-shared.HaveTHExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTHExt()">HaveTHExt</a>() then VTCR_EL2.TL1 else '0';</line>
<line>    if <a link="impl-shared.HaveAccessFlagUpdateForTableExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAccessFlagUpdateForTableExt()">HaveAccessFlagUpdateForTableExt</a>() &amp;&amp; walkparams.ha == '1' then</line>
<line>        walkparams.haft = VTCR_EL2.HAFT;</line>
<line>    else</line>
<line>        walkparams.haft = '0';</line>
<line>    walkparams.emec = '0';</line>
<line></line>
<line>    return walkparams;</line>
</pstext>
    </ps>
    <ps name="shared/debug/ClearStickyErrors/ClearStickyErrors" mylink="shared.debug.ClearStickyErrors.ClearStickyErrors" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ClearStickyErrors()</line>
<line>// ===================</line>
<line></line>
<line link="impl-shared.ClearStickyErrors.0" hover="function: ClearStickyErrors()" conts="ClearStickyErrors"><anchor link="impl-shared.ClearStickyErrors.0" hover="function: ClearStickyErrors()">ClearStickyErrors</anchor>()</line>
<line>    EDSCR.TXU = '0';            // Clear TX underrun flag</line>
<line>    EDSCR.RXO = '0';            // Clear RX overrun flag</line>
<line></line>
<line>    if <a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() then            // in Debug state</line>
<line>        EDSCR.ITO = '0';        // Clear ITR overrun flag</line>
<line></line>
<line>    // If halted and the ITR is not empty then it is UNPREDICTABLE whether the EDSCR.ERR is cleared.</line>
<line>    // The UNPREDICTABLE behavior also affects the instructions in flight, but this is not described</line>
<line>    // in the pseudocode.</line>
<line>    if (<a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() &amp;&amp; EDSCR.ITE == '0' &amp;&amp;</line>
<line>          <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_CLEARERRITEZERO" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_CLEARERRITEZERO</a>)) then</line>
<line>        return;</line>
<line>    EDSCR.ERR = '0';            // Clear cumulative error flag</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/debug/DebugTarget/DebugTarget" mylink="shared.debug.DebugTarget.DebugTarget" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DebugTarget()</line>
<line>// =============</line>
<line>// Returns the debug exception target Exception level</line>
<line></line>
<line link="impl-shared.DebugTarget.0" hover="function: bits(2) DebugTarget()" conts="DebugTarget">bits(2) <anchor link="impl-shared.DebugTarget.0" hover="function: bits(2) DebugTarget()">DebugTarget</anchor>()</line>
<line>    ss = <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>();</line>
<line>    return <a link="impl-shared.DebugTargetFrom.1" file="shared_pseudocode.xml" hover="function: bits(2) DebugTargetFrom(SecurityState from_state)">DebugTargetFrom</a>(ss);</line>
</pstext>
    </ps>
    <ps name="shared/debug/DebugTarget/DebugTargetFrom" mylink="shared.debug.DebugTarget.DebugTargetFrom" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DebugTargetFrom()</line>
<line>// =================</line>
<line></line>
<line link="impl-shared.DebugTargetFrom.1" hover="function: bits(2) DebugTargetFrom(SecurityState from_state)" conts="DebugTargetFrom">bits(2) <anchor link="impl-shared.DebugTargetFrom.1" hover="function: bits(2) DebugTargetFrom(SecurityState from_state)">DebugTargetFrom</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> from_state)</line>
<line>    boolean route_to_el2;</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; (from_state != <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> ||</line>
<line>        (<a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>() &amp;&amp; (!<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) || SCR_EL3.EEL2 == '1'))) then</line>
<line>        if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>            route_to_el2 = (HDCR.TDE == '1' || HCR.TGE == '1');</line>
<line>        else</line>
<line>            route_to_el2 = (MDCR_EL2.TDE == '1' || HCR_EL2.TGE == '1');</line>
<line>    else</line>
<line>        route_to_el2 = FALSE;</line>
<line></line>
<line>    bits(2) target;</line>
<line>    if route_to_el2 then</line>
<line>        target = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>    elsif <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; !<a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() &amp;&amp; from_state == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>        target = <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line>    else</line>
<line>        target = <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line></line>
<line>    return target;</line>
</pstext>
    </ps>
    <ps name="shared/debug/DoubleLockStatus/DoubleLockStatus" mylink="shared.debug.DoubleLockStatus.DoubleLockStatus" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DoubleLockStatus()</line>
<line>// ==================</line>
<line>// Returns the state of the OS Double Lock.</line>
<line>//    FALSE if OSDLR_EL1.DLK == 0 or DBGPRCR_EL1.CORENPDRQ == 1 or the PE is in Debug state.</line>
<line>//    TRUE if OSDLR_EL1.DLK == 1 and DBGPRCR_EL1.CORENPDRQ == 0 and the PE is in Non-debug state.</line>
<line></line>
<line link="impl-shared.DoubleLockStatus.0" hover="function: boolean DoubleLockStatus()" conts="DoubleLockStatus">boolean <anchor link="impl-shared.DoubleLockStatus.0" hover="function: boolean DoubleLockStatus()">DoubleLockStatus</anchor>()</line>
<line>    if !<a link="impl-shared.HaveDoubleLock.0" file="shared_pseudocode.xml" hover="function: boolean HaveDoubleLock()">HaveDoubleLock</a>() then</line>
<line>        return FALSE;</line>
<line>    elsif <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>        return DBGOSDLR.DLK == '1' &amp;&amp; DBGPRCR.CORENPDRQ == '0' &amp;&amp; !<a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>();</line>
<line>    else</line>
<line>        return OSDLR_EL1.DLK == '1' &amp;&amp; DBGPRCR_EL1.CORENPDRQ == '0' &amp;&amp; !<a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>();</line>
</pstext>
    </ps>
    <ps name="shared/debug/OSLockStatus/OSLockStatus" mylink="shared.debug.OSLockStatus.OSLockStatus" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// OSLockStatus()</line>
<line>// ==============</line>
<line>// Returns the state of the OS Lock.</line>
<line></line>
<line link="impl-shared.OSLockStatus.0" hover="function: boolean OSLockStatus()" conts="OSLockStatus">boolean <anchor link="impl-shared.OSLockStatus.0" hover="function: boolean OSLockStatus()">OSLockStatus</anchor>()</line>
<line>    return (if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then DBGOSLSR.OSLK else OSLSR_EL1.OSLK) == '1';</line>
</pstext>
    </ps>
    <ps name="shared/debug/SoftwareLockStatus/Component" mylink="shared.debug.SoftwareLockStatus.Component" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Component</line>
<line>// =========</line>
<line>// Component Types.</line>
<line></line>
<line link="Component" hover="enumeration Component { Component_PMU, Component_Debug, Component_CTI }" conts="Component">enumeration <anchor link="Component" hover="enumeration Component { Component_PMU, Component_Debug, Component_CTI }">Component</anchor> {</line>
<line link="Component_PMU" hover="enumeration Component { Component_PMU, Component_Debug, Component_CTI }" conts="Component_PMU">        <anchor link="Component_PMU" hover="enumeration Component { Component_PMU, Component_Debug, Component_CTI }">Component_PMU</anchor>,</line>
<line link="Component_Debug" hover="enumeration Component { Component_PMU, Component_Debug, Component_CTI }" conts="Component_Debug">        <anchor link="Component_Debug" hover="enumeration Component { Component_PMU, Component_Debug, Component_CTI }">Component_Debug</anchor>,</line>
<line link="Component_CTI" hover="enumeration Component { Component_PMU, Component_Debug, Component_CTI }" conts="Component_CTI">        <anchor link="Component_CTI" hover="enumeration Component { Component_PMU, Component_Debug, Component_CTI }">Component_CTI</anchor></line>
<line>};</line>
</pstext>
    </ps>
    <ps name="shared/debug/SoftwareLockStatus/GetAccessComponent" mylink="shared.debug.SoftwareLockStatus.GetAccessComponent" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GetAccessComponent()</line>
<line>// ====================</line>
<line>// Returns the accessed component.</line>
<line></line>
<line link="impl-shared.GetAccessComponent.0" hover="function: Component GetAccessComponent()" conts="GetAccessComponent">Component <anchor link="impl-shared.GetAccessComponent.0" hover="function: Component GetAccessComponent()">GetAccessComponent</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/debug/SoftwareLockStatus/SoftwareLockStatus" mylink="shared.debug.SoftwareLockStatus.SoftwareLockStatus" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SoftwareLockStatus()</line>
<line>// ====================</line>
<line>// Returns the state of the Software Lock.</line>
<line></line>
<line link="impl-shared.SoftwareLockStatus.0" hover="function: boolean SoftwareLockStatus()" conts="SoftwareLockStatus">boolean <anchor link="impl-shared.SoftwareLockStatus.0" hover="function: boolean SoftwareLockStatus()">SoftwareLockStatus</anchor>()</line>
<line>    <a link="Component" file="shared_pseudocode.xml" hover="enumeration Component { Component_PMU, Component_Debug, Component_CTI }">Component</a> component = <a link="impl-shared.GetAccessComponent.0" file="shared_pseudocode.xml" hover="function: Component GetAccessComponent()">GetAccessComponent</a>();</line>
<line>    if !<a link="impl-shared.HaveSoftwareLock.1" file="shared_pseudocode.xml" hover="function: boolean HaveSoftwareLock(Component component)">HaveSoftwareLock</a>(component) then</line>
<line>        return FALSE;</line>
<line>    case component of</line>
<line>        when <a link="Component_Debug" file="shared_pseudocode.xml" hover="enumeration Component { Component_PMU, Component_Debug, Component_CTI }">Component_Debug</a></line>
<line>            return EDLSR.SLK == '1';</line>
<line>        when <a link="Component_PMU" file="shared_pseudocode.xml" hover="enumeration Component { Component_PMU, Component_Debug, Component_CTI }">Component_PMU</a></line>
<line>            return PMLSR.SLK == '1';</line>
<line>        when <a link="Component_CTI" file="shared_pseudocode.xml" hover="enumeration Component { Component_PMU, Component_Debug, Component_CTI }">Component_CTI</a></line>
<line>            return CTILSR.SLK == '1';</line>
<line>        otherwise</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
</pstext>
    </ps>
    <ps name="shared/debug/authentication/AccessState" mylink="shared.debug.authentication.AccessState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AccessState()</line>
<line>// =============</line>
<line>// Returns the Security state of the access.</line>
<line></line>
<line link="impl-shared.AccessState.0" hover="function: SecurityState AccessState()" conts="AccessState">SecurityState <anchor link="impl-shared.AccessState.0" hover="function: SecurityState AccessState()">AccessState</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/debug/authentication/AllowExternalDebugAccess" mylink="shared.debug.authentication.AllowExternalDebugAccess" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AllowExternalDebugAccess()</line>
<line>// ==========================</line>
<line>// Returns TRUE if an external debug interface access to the External debug registers</line>
<line>// is allowed, FALSE otherwise.</line>
<line></line>
<line link="impl-shared.AllowExternalDebugAccess.0" hover="function: boolean AllowExternalDebugAccess()" conts="AllowExternalDebugAccess">boolean <anchor link="impl-shared.AllowExternalDebugAccess.0" hover="function: boolean AllowExternalDebugAccess()">AllowExternalDebugAccess</anchor>()</line>
<line>    // The access may also be subject to OS Lock, power-down, etc.</line>
<line>    return <a link="impl-shared.AllowExternalDebugAccess.1" file="shared_pseudocode.xml" hover="function: boolean AllowExternalDebugAccess(SecurityState access_state)">AllowExternalDebugAccess</a>(<a link="impl-shared.AccessState.0" file="shared_pseudocode.xml" hover="function: SecurityState AccessState()">AccessState</a>());</line>
<line></line>
<line>// AllowExternalDebugAccess()</line>
<line>// ==========================</line>
<line>// Returns TRUE if an external debug interface access to the External debug registers</line>
<line>// is allowed for the given Security state, FALSE otherwise.</line>
<line></line>
<line link="impl-shared.AllowExternalDebugAccess.1" hover="function: boolean AllowExternalDebugAccess(SecurityState access_state)" conts="AllowExternalDebugAccess">boolean <anchor link="impl-shared.AllowExternalDebugAccess.1" hover="function: boolean AllowExternalDebugAccess(SecurityState access_state)">AllowExternalDebugAccess</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> access_state)</line>
<line>    // The access may also be subject to OS Lock, power-down, etc.</line>
<line>    if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then</line>
<line>        case MDCR_EL3.&lt;EDADE,EDAD&gt; of</line>
<line>            when '00' return TRUE;</line>
<line>            when '01' return access_state IN {<a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>, <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>};</line>
<line>            when '10' return access_state IN {<a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>, <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>};</line>
<line>            when '11' return access_state == <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>;</line>
<line></line>
<line>    if <a link="impl-shared.HaveSecureExtDebugView.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureExtDebugView()">HaveSecureExtDebugView</a>() then</line>
<line>        if access_state == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then return TRUE;</line>
<line>    else</line>
<line>        if !<a link="impl-shared.ExternalInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalInvasiveDebugEnabled()">ExternalInvasiveDebugEnabled</a>() then return FALSE;</line>
<line>        if <a link="impl-shared.ExternalSecureInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalSecureInvasiveDebugEnabled()">ExternalSecureInvasiveDebugEnabled</a>() then return TRUE;</line>
<line></line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        EDAD_bit = if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then SDCR.EDAD else MDCR_EL3.EDAD;</line>
<line>        return EDAD_bit == '0';</line>
<line>    else</line>
<line>        return <a link="impl-shared.NonSecureOnlyImplementation.0" file="shared_pseudocode.xml" hover="function: boolean NonSecureOnlyImplementation()">NonSecureOnlyImplementation</a>();</line>
</pstext>
    </ps>
    <ps name="shared/debug/authentication/AllowExternalPMUAccess" mylink="shared.debug.authentication.AllowExternalPMUAccess" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AllowExternalPMUAccess()</line>
<line>// ========================</line>
<line>// Returns TRUE if an external debug interface access to the PMU registers is</line>
<line>// allowed, FALSE otherwise.</line>
<line></line>
<line link="impl-shared.AllowExternalPMUAccess.0" hover="function: boolean AllowExternalPMUAccess()" conts="AllowExternalPMUAccess">boolean <anchor link="impl-shared.AllowExternalPMUAccess.0" hover="function: boolean AllowExternalPMUAccess()">AllowExternalPMUAccess</anchor>()</line>
<line>    // The access may also be subject to OS Lock, power-down, etc.</line>
<line>    return <a link="impl-shared.AllowExternalPMUAccess.1" file="shared_pseudocode.xml" hover="function: boolean AllowExternalPMUAccess(SecurityState access_state)">AllowExternalPMUAccess</a>(<a link="impl-shared.AccessState.0" file="shared_pseudocode.xml" hover="function: SecurityState AccessState()">AccessState</a>());</line>
<line></line>
<line>// AllowExternalPMUAccess()</line>
<line>// ========================</line>
<line>// Returns TRUE if an external debug interface access to the PMU registers is</line>
<line>// allowed for the given Security state, FALSE otherwise.</line>
<line></line>
<line link="impl-shared.AllowExternalPMUAccess.1" hover="function: boolean AllowExternalPMUAccess(SecurityState access_state)" conts="AllowExternalPMUAccess">boolean <anchor link="impl-shared.AllowExternalPMUAccess.1" hover="function: boolean AllowExternalPMUAccess(SecurityState access_state)">AllowExternalPMUAccess</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> access_state)</line>
<line>    // The access may also be subject to OS Lock, power-down, etc.</line>
<line>    if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then</line>
<line>        case MDCR_EL3.&lt;EPMADE,EPMAD&gt; of</line>
<line>            when '00' return TRUE;</line>
<line>            when '01' return access_state IN {<a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>, <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>};</line>
<line>            when '10' return access_state IN {<a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>, <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>};</line>
<line>            when '11' return access_state == <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>;</line>
<line></line>
<line>    if <a link="impl-shared.HaveSecureExtDebugView.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureExtDebugView()">HaveSecureExtDebugView</a>() then</line>
<line>        if access_state == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then return TRUE;</line>
<line>    else</line>
<line>        if !<a link="impl-shared.ExternalInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalInvasiveDebugEnabled()">ExternalInvasiveDebugEnabled</a>() then return FALSE;</line>
<line>        if <a link="impl-shared.ExternalSecureInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalSecureInvasiveDebugEnabled()">ExternalSecureInvasiveDebugEnabled</a>() then return TRUE;</line>
<line></line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        EPMAD_bit = if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then SDCR.EPMAD else MDCR_EL3.EPMAD;</line>
<line>        return EPMAD_bit == '0';</line>
<line>    else</line>
<line>        return <a link="impl-shared.NonSecureOnlyImplementation.0" file="shared_pseudocode.xml" hover="function: boolean NonSecureOnlyImplementation()">NonSecureOnlyImplementation</a>();</line>
</pstext>
    </ps>
    <ps name="shared/debug/authentication/AllowExternalTraceAccess" mylink="shared.debug.authentication.AllowExternalTraceAccess" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AllowExternalTraceAccess()</line>
<line>// ==========================</line>
<line>// Returns TRUE if an external Trace access to the Trace registers is allowed, FALSE otherwise.</line>
<line></line>
<line link="impl-shared.AllowExternalTraceAccess.0" hover="function: boolean AllowExternalTraceAccess()" conts="AllowExternalTraceAccess">boolean <anchor link="impl-shared.AllowExternalTraceAccess.0" hover="function: boolean AllowExternalTraceAccess()">AllowExternalTraceAccess</anchor>()</line>
<line>    if !<a link="impl-shared.HaveTraceBufferExtension.0" file="shared_pseudocode.xml" hover="function: boolean HaveTraceBufferExtension()">HaveTraceBufferExtension</a>() then</line>
<line>        return TRUE;</line>
<line>    else</line>
<line>        return <a link="impl-shared.AllowExternalTraceAccess.1" file="shared_pseudocode.xml" hover="function: boolean AllowExternalTraceAccess(SecurityState access_state)">AllowExternalTraceAccess</a>(<a link="impl-shared.AccessState.0" file="shared_pseudocode.xml" hover="function: SecurityState AccessState()">AccessState</a>());</line>
<line></line>
<line>// AllowExternalTraceAccess()</line>
<line>// ==========================</line>
<line>// Returns TRUE if an external Trace access to the Trace registers is allowed for the</line>
<line>// given Security state, FALSE otherwise.</line>
<line></line>
<line link="impl-shared.AllowExternalTraceAccess.1" hover="function: boolean AllowExternalTraceAccess(SecurityState access_state)" conts="AllowExternalTraceAccess">boolean <anchor link="impl-shared.AllowExternalTraceAccess.1" hover="function: boolean AllowExternalTraceAccess(SecurityState access_state)">AllowExternalTraceAccess</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> access_state)</line>
<line>    // The access may also be subject to OS lock, power-down, etc.</line>
<line>    if !<a link="impl-shared.HaveTraceBufferExtension.0" file="shared_pseudocode.xml" hover="function: boolean HaveTraceBufferExtension()">HaveTraceBufferExtension</a>() then return TRUE;</line>
<line>    assert <a link="impl-shared.HaveSecureExtDebugView.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureExtDebugView()">HaveSecureExtDebugView</a>();</line>
<line>    if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then</line>
<line>        case MDCR_EL3.&lt;ETADE,ETAD&gt; of</line>
<line>            when '00' return TRUE;</line>
<line>            when '01' return access_state IN {<a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>, <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>};</line>
<line>            when '10' return access_state IN {<a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>, <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>};</line>
<line>            when '11' return access_state == <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>;</line>
<line></line>
<line>    if access_state == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then return TRUE;</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        // External Trace access is not supported for EL3 using AArch32</line>
<line>        assert !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>        return MDCR_EL3.ETAD == '0';</line>
<line>    else</line>
<line>        return <a link="impl-shared.NonSecureOnlyImplementation.0" file="shared_pseudocode.xml" hover="function: boolean NonSecureOnlyImplementation()">NonSecureOnlyImplementation</a>();</line>
</pstext>
    </ps>
    <ps name="shared/debug/authentication/Debug_authentication" mylink="shared.debug.authentication.Debug_authentication" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>signal DBGEN;</line>
<line>signal NIDEN;</line>
<line>signal SPIDEN;</line>
<line>signal SPNIDEN;</line>
<line>signal RLPIDEN;</line>
<line>signal RTPIDEN;</line>
</pstext>
    </ps>
    <ps name="shared/debug/authentication/ExternalInvasiveDebugEnabled" mylink="shared.debug.authentication.ExternalInvasiveDebugEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExternalInvasiveDebugEnabled()</line>
<line>// ==============================</line>
<line>// The definition of this function is IMPLEMENTATION DEFINED.</line>
<line>// In the recommended interface, this function returns the state of the DBGEN signal.</line>
<line></line>
<line link="impl-shared.ExternalInvasiveDebugEnabled.0" hover="function: boolean ExternalInvasiveDebugEnabled()" conts="ExternalInvasiveDebugEnabled">boolean <anchor link="impl-shared.ExternalInvasiveDebugEnabled.0" hover="function: boolean ExternalInvasiveDebugEnabled()">ExternalInvasiveDebugEnabled</anchor>()</line>
<line>    return DBGEN == HIGH;</line>
</pstext>
    </ps>
    <ps name="shared/debug/authentication/ExternalNoninvasiveDebugAllowed" mylink="shared.debug.authentication.ExternalNoninvasiveDebugAllowed" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExternalNoninvasiveDebugAllowed()</line>
<line>// =================================</line>
<line>// Returns TRUE if Trace and PC Sample-based Profiling are allowed</line>
<line></line>
<line link="impl-shared.ExternalNoninvasiveDebugAllowed.0" hover="function: boolean ExternalNoninvasiveDebugAllowed()" conts="ExternalNoninvasiveDebugAllowed">boolean <anchor link="impl-shared.ExternalNoninvasiveDebugAllowed.0" hover="function: boolean ExternalNoninvasiveDebugAllowed()">ExternalNoninvasiveDebugAllowed</anchor>()</line>
<line>    return <a link="impl-shared.ExternalNoninvasiveDebugAllowed.1" file="shared_pseudocode.xml" hover="function: boolean ExternalNoninvasiveDebugAllowed(bits(2) el)">ExternalNoninvasiveDebugAllowed</a>(PSTATE.EL);</line>
<line></line>
<line>// ExternalNoninvasiveDebugAllowed()</line>
<line>// =================================</line>
<line></line>
<line link="impl-shared.ExternalNoninvasiveDebugAllowed.1" hover="function: boolean ExternalNoninvasiveDebugAllowed(bits(2) el)" conts="ExternalNoninvasiveDebugAllowed">boolean <anchor link="impl-shared.ExternalNoninvasiveDebugAllowed.1" hover="function: boolean ExternalNoninvasiveDebugAllowed(bits(2) el)">ExternalNoninvasiveDebugAllowed</anchor>(bits(2) el)</line>
<line>    if !<a link="impl-shared.ExternalNoninvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalNoninvasiveDebugEnabled()">ExternalNoninvasiveDebugEnabled</a>() then return FALSE;</line>
<line>    ss = <a link="impl-shared.SecurityStateAtEL.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)">SecurityStateAtEL</a>(el);</line>
<line></line>
<line>    if ((<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) || <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>)) &amp;&amp; el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp;</line>
<line>        ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> &amp;&amp; SDER.SUNIDEN == '1') then</line>
<line>        return TRUE;</line>
<line></line>
<line>    case ss of</line>
<line>        when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> return TRUE;</line>
<line>        when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>    return <a link="impl-shared.ExternalSecureNoninvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalSecureNoninvasiveDebugEnabled()">ExternalSecureNoninvasiveDebugEnabled</a>();</line>
<line>        when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>     return <a link="impl-shared.ExternalRealmNoninvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalRealmNoninvasiveDebugEnabled()">ExternalRealmNoninvasiveDebugEnabled</a>();</line>
<line>        when <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>      return <a link="impl-shared.ExternalRootNoninvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalRootNoninvasiveDebugEnabled()">ExternalRootNoninvasiveDebugEnabled</a>();</line>
</pstext>
    </ps>
    <ps name="shared/debug/authentication/ExternalNoninvasiveDebugEnabled" mylink="shared.debug.authentication.ExternalNoninvasiveDebugEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExternalNoninvasiveDebugEnabled()</line>
<line>// =================================</line>
<line>// This function returns TRUE if the FEAT_Debugv8p4 is implemented.</line>
<line>// Otherwise, this function is IMPLEMENTATION DEFINED, and, in the</line>
<line>// recommended interface, ExternalNoninvasiveDebugEnabled returns</line>
<line>// the state of the (DBGEN OR NIDEN) signal.</line>
<line></line>
<line link="impl-shared.ExternalNoninvasiveDebugEnabled.0" hover="function: boolean ExternalNoninvasiveDebugEnabled()" conts="ExternalNoninvasiveDebugEnabled">boolean <anchor link="impl-shared.ExternalNoninvasiveDebugEnabled.0" hover="function: boolean ExternalNoninvasiveDebugEnabled()">ExternalNoninvasiveDebugEnabled</anchor>()</line>
<line>    return !<a link="impl-shared.HaveNoninvasiveDebugAuth.0" file="shared_pseudocode.xml" hover="function: boolean HaveNoninvasiveDebugAuth()">HaveNoninvasiveDebugAuth</a>() || <a link="impl-shared.ExternalInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalInvasiveDebugEnabled()">ExternalInvasiveDebugEnabled</a>() || NIDEN == HIGH;</line>
</pstext>
    </ps>
    <ps name="shared/debug/authentication/ExternalRealmInvasiveDebugEnabled" mylink="shared.debug.authentication.ExternalRealmInvasiveDebugEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExternalRealmInvasiveDebugEnabled()</line>
<line>// ===================================</line>
<line>// The definition of this function is IMPLEMENTATION DEFINED.</line>
<line>// In the recommended interface, this function returns the state of the</line>
<line>// (DBGEN AND RLPIDEN) signal.</line>
<line></line>
<line link="impl-shared.ExternalRealmInvasiveDebugEnabled.0" hover="function: boolean ExternalRealmInvasiveDebugEnabled()" conts="ExternalRealmInvasiveDebugEnabled">boolean <anchor link="impl-shared.ExternalRealmInvasiveDebugEnabled.0" hover="function: boolean ExternalRealmInvasiveDebugEnabled()">ExternalRealmInvasiveDebugEnabled</anchor>()</line>
<line>    if !<a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then return FALSE;</line>
<line>    return <a link="impl-shared.ExternalInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalInvasiveDebugEnabled()">ExternalInvasiveDebugEnabled</a>() &amp;&amp; RLPIDEN == HIGH;</line>
</pstext>
    </ps>
    <ps name="shared/debug/authentication/ExternalRealmNoninvasiveDebugEnabled" mylink="shared.debug.authentication.ExternalRealmNoninvasiveDebugEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExternalRealmNoninvasiveDebugEnabled()</line>
<line>// ======================================</line>
<line>// The definition of this function is IMPLEMENTATION DEFINED.</line>
<line>// In the recommended interface, this function returns the state of the</line>
<line>// (DBGEN AND RLPIDEN) signal.</line>
<line></line>
<line link="impl-shared.ExternalRealmNoninvasiveDebugEnabled.0" hover="function: boolean ExternalRealmNoninvasiveDebugEnabled()" conts="ExternalRealmNoninvasiveDebugEnabled">boolean <anchor link="impl-shared.ExternalRealmNoninvasiveDebugEnabled.0" hover="function: boolean ExternalRealmNoninvasiveDebugEnabled()">ExternalRealmNoninvasiveDebugEnabled</anchor>()</line>
<line>    if !<a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then return FALSE;</line>
<line>    return <a link="impl-shared.ExternalRealmInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalRealmInvasiveDebugEnabled()">ExternalRealmInvasiveDebugEnabled</a>();</line>
</pstext>
    </ps>
    <ps name="shared/debug/authentication/ExternalRootInvasiveDebugEnabled" mylink="shared.debug.authentication.ExternalRootInvasiveDebugEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExternalRootInvasiveDebugEnabled()</line>
<line>// ==================================</line>
<line>// The definition of this function is IMPLEMENTATION DEFINED.</line>
<line>// In the recommended interface, this function returns the state of the</line>
<line>// (DBGEN AND RLPIDEN AND RTPIDEN AND SPIDEN) signal when FEAT_SEL2 is implemented</line>
<line>// and the (DBGEN AND RLPIDEN AND RTPIDEN) signal when FEAT_SEL2 is not implemented.</line>
<line></line>
<line link="impl-shared.ExternalRootInvasiveDebugEnabled.0" hover="function: boolean ExternalRootInvasiveDebugEnabled()" conts="ExternalRootInvasiveDebugEnabled">boolean <anchor link="impl-shared.ExternalRootInvasiveDebugEnabled.0" hover="function: boolean ExternalRootInvasiveDebugEnabled()">ExternalRootInvasiveDebugEnabled</anchor>()</line>
<line>    if !<a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then return FALSE;</line>
<line>    return (<a link="impl-shared.ExternalInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalInvasiveDebugEnabled()">ExternalInvasiveDebugEnabled</a>() &amp;&amp;</line>
<line>            (!<a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>() || <a link="impl-shared.ExternalSecureInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalSecureInvasiveDebugEnabled()">ExternalSecureInvasiveDebugEnabled</a>()) &amp;&amp;</line>
<line>            <a link="impl-shared.ExternalRealmInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalRealmInvasiveDebugEnabled()">ExternalRealmInvasiveDebugEnabled</a>() &amp;&amp;</line>
<line>            RTPIDEN == HIGH);</line>
</pstext>
    </ps>
    <ps name="shared/debug/authentication/ExternalRootNoninvasiveDebugEnabled" mylink="shared.debug.authentication.ExternalRootNoninvasiveDebugEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExternalRootNoninvasiveDebugEnabled()</line>
<line>// =====================================</line>
<line>// The definition of this function is IMPLEMENTATION DEFINED.</line>
<line>// In the recommended interface, this function returns the state of the</line>
<line>// (DBGEN AND RLPIDEN AND SPIDEN AND RTPIDEN) signal.</line>
<line></line>
<line link="impl-shared.ExternalRootNoninvasiveDebugEnabled.0" hover="function: boolean ExternalRootNoninvasiveDebugEnabled()" conts="ExternalRootNoninvasiveDebugEnabled">boolean <anchor link="impl-shared.ExternalRootNoninvasiveDebugEnabled.0" hover="function: boolean ExternalRootNoninvasiveDebugEnabled()">ExternalRootNoninvasiveDebugEnabled</anchor>()</line>
<line>    if !<a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then return FALSE;</line>
<line>    return <a link="impl-shared.ExternalRootInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalRootInvasiveDebugEnabled()">ExternalRootInvasiveDebugEnabled</a>();</line>
</pstext>
    </ps>
    <ps name="shared/debug/authentication/ExternalSecureInvasiveDebugEnabled" mylink="shared.debug.authentication.ExternalSecureInvasiveDebugEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExternalSecureInvasiveDebugEnabled()</line>
<line>// ====================================</line>
<line>// The definition of this function is IMPLEMENTATION DEFINED.</line>
<line>// In the recommended interface, this function returns the state of the (DBGEN AND SPIDEN) signal.</line>
<line>// CoreSight allows asserting SPIDEN without also asserting DBGEN, but this is not recommended.</line>
<line></line>
<line link="impl-shared.ExternalSecureInvasiveDebugEnabled.0" hover="function: boolean ExternalSecureInvasiveDebugEnabled()" conts="ExternalSecureInvasiveDebugEnabled">boolean <anchor link="impl-shared.ExternalSecureInvasiveDebugEnabled.0" hover="function: boolean ExternalSecureInvasiveDebugEnabled()">ExternalSecureInvasiveDebugEnabled</anchor>()</line>
<line>    if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; !<a link="impl-shared.SecureOnlyImplementation.0" file="shared_pseudocode.xml" hover="function: boolean SecureOnlyImplementation()">SecureOnlyImplementation</a>() then return FALSE;</line>
<line>    return <a link="impl-shared.ExternalInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalInvasiveDebugEnabled()">ExternalInvasiveDebugEnabled</a>() &amp;&amp; SPIDEN == HIGH;</line>
</pstext>
    </ps>
    <ps name="shared/debug/authentication/ExternalSecureNoninvasiveDebugEnabled" mylink="shared.debug.authentication.ExternalSecureNoninvasiveDebugEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExternalSecureNoninvasiveDebugEnabled()</line>
<line>// =======================================</line>
<line>// This function returns the value of ExternalSecureInvasiveDebugEnabled() when FEAT_Debugv8p4</line>
<line>// is implemented. Otherwise, the definition of this function is IMPLEMENTATION DEFINED.</line>
<line>// In the recommended interface, this function returns the state of the (DBGEN OR NIDEN) AND</line>
<line>// (SPIDEN OR SPNIDEN) signal.</line>
<line></line>
<line link="impl-shared.ExternalSecureNoninvasiveDebugEnabled.0" hover="function: boolean ExternalSecureNoninvasiveDebugEnabled()" conts="ExternalSecureNoninvasiveDebugEnabled">boolean <anchor link="impl-shared.ExternalSecureNoninvasiveDebugEnabled.0" hover="function: boolean ExternalSecureNoninvasiveDebugEnabled()">ExternalSecureNoninvasiveDebugEnabled</anchor>()</line>
<line>    if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; !<a link="impl-shared.SecureOnlyImplementation.0" file="shared_pseudocode.xml" hover="function: boolean SecureOnlyImplementation()">SecureOnlyImplementation</a>() then return FALSE;</line>
<line>    if <a link="impl-shared.HaveNoninvasiveDebugAuth.0" file="shared_pseudocode.xml" hover="function: boolean HaveNoninvasiveDebugAuth()">HaveNoninvasiveDebugAuth</a>() then</line>
<line>        return <a link="impl-shared.ExternalNoninvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalNoninvasiveDebugEnabled()">ExternalNoninvasiveDebugEnabled</a>() &amp;&amp; (SPIDEN == HIGH || SPNIDEN == HIGH);</line>
<line>    else</line>
<line>        return <a link="impl-shared.ExternalSecureInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalSecureInvasiveDebugEnabled()">ExternalSecureInvasiveDebugEnabled</a>();</line>
</pstext>
    </ps>
    <ps name="shared/debug/authentication/IsAccessSecure" mylink="shared.debug.authentication.IsAccessSecure" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsAccessSecure()</line>
<line>// ================</line>
<line>// Returns TRUE when an access is Secure</line>
<line></line>
<line link="impl-shared.IsAccessSecure.0" hover="function: boolean IsAccessSecure()" conts="IsAccessSecure">boolean <anchor link="impl-shared.IsAccessSecure.0" hover="function: boolean IsAccessSecure()">IsAccessSecure</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/debug/authentication/IsCorePowered" mylink="shared.debug.authentication.IsCorePowered" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsCorePowered()</line>
<line>// ===============</line>
<line>// Returns TRUE if the Core power domain is powered on, FALSE otherwise.</line>
<line></line>
<line link="impl-shared.IsCorePowered.0" hover="function: boolean IsCorePowered()" conts="IsCorePowered">boolean <anchor link="impl-shared.IsCorePowered.0" hover="function: boolean IsCorePowered()">IsCorePowered</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/debug/breakpoint/CheckValidStateMatch" mylink="shared.debug.breakpoint.CheckValidStateMatch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckValidStateMatch()</line>
<line>// ======================</line>
<line>// Checks for an invalid state match that will generate Constrained</line>
<line>// Unpredictable behavior, otherwise returns Constraint_NONE.</line>
<line></line>
<line link="impl-shared.CheckValidStateMatch.5" hover="function: (Constraint, bits(2), bit, bit, bits(2)) CheckValidStateMatch(bits(2) ssc_in, bit ssce_in, bit hmc_in, bits(2) pxc_in, boolean isbreakpnt)" conts="CheckValidStateMatch">(Constraint, bits(2), bit, bit, bits(2)) <anchor link="impl-shared.CheckValidStateMatch.5" hover="function: (Constraint, bits(2), bit, bit, bits(2)) CheckValidStateMatch(bits(2) ssc_in, bit ssce_in, bit hmc_in, bits(2) pxc_in, boolean isbreakpnt)">CheckValidStateMatch</anchor>(bits(2) ssc_in, bit ssce_in,</line>
<line>                                                              bit hmc_in, bits(2) pxc_in,</line>
<line>                                                              boolean isbreakpnt)</line>
<line>    if !<a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then assert ssce_in == '0';</line>
<line>    boolean reserved = FALSE;</line>
<line>    bits(2) ssc = ssc_in;</line>
<line>    bit ssce    = ssce_in;</line>
<line>    bit hmc     = hmc_in;</line>
<line>    bits(2) pxc = pxc_in;</line>
<line></line>
<line>    // Values that are not allocated in any architecture version</line>
<line>    case hmc:ssce:ssc:pxc of</line>
<line>        when '0 0 11 10' reserved = TRUE;</line>
<line>        when '0 0 1x xx' reserved = !<a link="impl-shared.HaveSecureState.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureState()">HaveSecureState</a>();</line>
<line>        when '1 0 00 x0' reserved = TRUE;</line>
<line>        when '1 0 01 10' reserved = TRUE;</line>
<line>        when '1 0 1x 10' reserved = TRUE;</line>
<line>        when 'x 1 xx xx' reserved = ssc != '01' || (hmc:pxc) IN {'000','110'};</line>
<line>        otherwise        reserved = FALSE;</line>
<line></line>
<line>    // Match 'Usr/Sys/Svc' valid only for AArch32 breakpoints</line>
<line>    if (!isbreakpnt || !<a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>)) &amp;&amp; hmc:pxc == '000' &amp;&amp; ssc != '11' then</line>
<line>        reserved = TRUE;</line>
<line></line>
<line>    // Both EL3 and EL2 are not implemented</line>
<line>    if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; (hmc != '0' || ssc != '00') then</line>
<line>        reserved = TRUE;</line>
<line></line>
<line>    // EL3 is not implemented</line>
<line>    if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; ssc IN {'01','10'} &amp;&amp; hmc:ssc:pxc != '10100' then</line>
<line>        reserved = TRUE;</line>
<line></line>
<line>    // EL3 using AArch64 only</line>
<line>    if (!<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) || !<a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>()) &amp;&amp; hmc:ssc:pxc == '11000' then</line>
<line>        reserved = TRUE;</line>
<line></line>
<line>    // EL2 is not implemented</line>
<line>    if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; hmc:ssc:pxc == '11100' then</line>
<line>        reserved = TRUE;</line>
<line></line>
<line>    // Secure EL2 is not implemented</line>
<line>    if !<a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>() &amp;&amp; (hmc:ssc:pxc)  IN {'01100','10100','x11x1'} then</line>
<line>        reserved = TRUE;</line>
<line></line>
<line>    if reserved then</line>
<line>        // If parameters are set to a reserved type, behaves as either disabled or a defined type</line>
<line>        <a link="Constraint" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint</a> c;</line>
<line>        (c, &lt;hmc,ssc,ssce,pxc&gt;) = <a link="impl-shared.ConstrainUnpredictableBits.2" file="shared_pseudocode.xml" hover="function: (Constraint,bits(width)) ConstrainUnpredictableBits(Unpredictable which, integer width)">ConstrainUnpredictableBits</a>(<a link="Unpredictable_RESBPWPCTRL" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESBPWPCTRL</a>, 6);</line>
<line>        assert c IN {<a link="Constraint_DISABLED" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_DISABLED</a>, <a link="Constraint_UNKNOWN" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNKNOWN</a>};</line>
<line>        if c == <a link="Constraint_DISABLED" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_DISABLED</a> then</line>
<line>            return (c, bits(2) UNKNOWN, bit UNKNOWN, bit UNKNOWN, bits(2) UNKNOWN);</line>
<line>        // Otherwise the value returned by ConstrainUnpredictableBits must be a not-reserved value</line>
<line></line>
<line>    return (<a link="Constraint_NONE" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NONE</a>, ssc, ssce, hmc, pxc);</line>
</pstext>
    </ps>
    <ps name="shared/debug/breakpoint/ContextMatchingBreakpointRange" mylink="shared.debug.breakpoint.ContextMatchingBreakpointRange" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ContextMatchingBreakpointRange()</line>
<line>// ================================</line>
<line>// Returns two numbers indicating the index of the first and last context-aware breakpoint.</line>
<line></line>
<line link="impl-shared.ContextMatchingBreakpointRange.0" hover="function: (integer, integer) ContextMatchingBreakpointRange()" conts="ContextMatchingBreakpointRange">(integer, integer) <anchor link="impl-shared.ContextMatchingBreakpointRange.0" hover="function: (integer, integer) ContextMatchingBreakpointRange()">ContextMatchingBreakpointRange</anchor>()</line>
<line>    integer b = <a link="impl-shared.NumBreakpointsImplemented.0" file="shared_pseudocode.xml" hover="function: integer NumBreakpointsImplemented()">NumBreakpointsImplemented</a>();</line>
<line>    integer c = <a link="impl-shared.NumContextAwareBreakpointsImplemented.0" file="shared_pseudocode.xml" hover="function: integer NumContextAwareBreakpointsImplemented()">NumContextAwareBreakpointsImplemented</a>();</line>
<line></line>
<line>    if b &lt;= 16 then</line>
<line>        return (b - c, b - 1);</line>
<line>    elsif c &lt;= 16 then</line>
<line>        return (16 - c, 15);</line>
<line>    else</line>
<line>        return (0, c - 1);</line>
</pstext>
    </ps>
    <ps name="shared/debug/breakpoint/IsContextMatchingBreakpoint" mylink="shared.debug.breakpoint.IsContextMatchingBreakpoint" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsContextMatchingBreakpoint()</line>
<line>// =============================</line>
<line>// Returns TRUE if DBGBCR_EL1[n] is a context-aware breakpoint.</line>
<line></line>
<line link="impl-shared.IsContextMatchingBreakpoint.1" hover="function: boolean IsContextMatchingBreakpoint(integer n)" conts="IsContextMatchingBreakpoint">boolean <anchor link="impl-shared.IsContextMatchingBreakpoint.1" hover="function: boolean IsContextMatchingBreakpoint(integer n)">IsContextMatchingBreakpoint</anchor>(integer n)</line>
<line>    (lower, upper) = <a link="impl-shared.ContextMatchingBreakpointRange.0" file="shared_pseudocode.xml" hover="function: (integer, integer) ContextMatchingBreakpointRange()">ContextMatchingBreakpointRange</a>();</line>
<line>    return n &gt;= lower &amp;&amp; n &lt;= upper;</line>
</pstext>
    </ps>
    <ps name="shared/debug/breakpoint/NumBreakpointsImplemented" mylink="shared.debug.breakpoint.NumBreakpointsImplemented" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// NumBreakpointsImplemented()</line>
<line>// ===========================</line>
<line>// Returns the number of breakpoints implemented. This is indicated to software by</line>
<line>// DBGDIDR.BRPs in AArch32 state, and ID_AA64DFR0_EL1.BRPs in AArch64 state.</line>
<line></line>
<line link="impl-shared.NumBreakpointsImplemented.0" hover="function: integer NumBreakpointsImplemented()" conts="NumBreakpointsImplemented">integer <anchor link="impl-shared.NumBreakpointsImplemented.0" hover="function: integer NumBreakpointsImplemented()">NumBreakpointsImplemented</anchor>()</line>
<line>    return integer IMPLEMENTATION_DEFINED "Number of breakpoints";</line>
</pstext>
    </ps>
    <ps name="shared/debug/breakpoint/NumContextAwareBreakpointsImplemented" mylink="shared.debug.breakpoint.NumContextAwareBreakpointsImplemented" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// NumContextAwareBreakpointsImplemented()</line>
<line>// =======================================</line>
<line>// Returns the number of context-aware breakpoints implemented. This is indicated to software by</line>
<line>// DBGDIDR.CTX_CMPs in AArch32 state, and ID_AA64DFR0_EL1.CTX_CMPs in AArch64 state.</line>
<line></line>
<line link="impl-shared.NumContextAwareBreakpointsImplemented.0" hover="function: integer NumContextAwareBreakpointsImplemented()" conts="NumContextAwareBreakpointsImplemented">integer <anchor link="impl-shared.NumContextAwareBreakpointsImplemented.0" hover="function: integer NumContextAwareBreakpointsImplemented()">NumContextAwareBreakpointsImplemented</anchor>()</line>
<line>    return integer IMPLEMENTATION_DEFINED "Number of context-aware breakpoints";</line>
</pstext>
    </ps>
    <ps name="shared/debug/breakpoint/NumWatchpointsImplemented" mylink="shared.debug.breakpoint.NumWatchpointsImplemented" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// NumWatchpointsImplemented()</line>
<line>// ===========================</line>
<line>// Returns the number of watchpoints implemented. This is indicated to software by</line>
<line>// DBGDIDR.WRPs in AArch32 state, and ID_AA64DFR0_EL1.WRPs in AArch64 state.</line>
<line></line>
<line link="impl-shared.NumWatchpointsImplemented.0" hover="function: integer NumWatchpointsImplemented()" conts="NumWatchpointsImplemented">integer <anchor link="impl-shared.NumWatchpointsImplemented.0" hover="function: integer NumWatchpointsImplemented()">NumWatchpointsImplemented</anchor>()</line>
<line>    return integer IMPLEMENTATION_DEFINED "Number of watchpoints";</line>
</pstext>
    </ps>
    <ps name="shared/debug/cti/CTI_SetEventLevel" mylink="shared.debug.cti.CTI_SetEventLevel" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CTI_SetEventLevel()</line>
<line>// ===================</line>
<line>// Set a Cross Trigger multi-cycle input event trigger to the specified level.</line>
<line></line>
<line>CTI_SetEventLevel(<a link="CrossTriggerIn" file="shared_pseudocode.xml" hover="enumeration CrossTriggerIn  {CrossTriggerIn_CrossHalt,     CrossTriggerIn_PMUOverflow, CrossTriggerIn_RSVD2,         CrossTriggerIn_RSVD3, CrossTriggerIn_TraceExtOut0,  CrossTriggerIn_TraceExtOut1, CrossTriggerIn_TraceExtOut2,  CrossTriggerIn_TraceExtOut3}">CrossTriggerIn</a> id, signal level);</line>
</pstext>
    </ps>
    <ps name="shared/debug/cti/CTI_SignalEvent" mylink="shared.debug.cti.CTI_SignalEvent" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CTI_SignalEvent()</line>
<line>// =================</line>
<line>// Signal a discrete event on a Cross Trigger input event trigger.</line>
<line></line>
<line link="impl-shared.CTI_SignalEvent.1" hover="function: CTI_SignalEvent(CrossTriggerIn id)" conts="CTI_SignalEvent"><anchor link="impl-shared.CTI_SignalEvent.1" hover="function: CTI_SignalEvent(CrossTriggerIn id)">CTI_SignalEvent</anchor>(<a link="CrossTriggerIn" file="shared_pseudocode.xml" hover="enumeration CrossTriggerIn  {CrossTriggerIn_CrossHalt,     CrossTriggerIn_PMUOverflow, CrossTriggerIn_RSVD2,         CrossTriggerIn_RSVD3, CrossTriggerIn_TraceExtOut0,  CrossTriggerIn_TraceExtOut1, CrossTriggerIn_TraceExtOut2,  CrossTriggerIn_TraceExtOut3}">CrossTriggerIn</a> id);</line>
</pstext>
    </ps>
    <ps name="shared/debug/cti/CrossTrigger" mylink="shared.debug.cti.CrossTrigger" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CrossTrigger</line>
<line>// ============</line>
<line></line>
<line link="CrossTriggerOut" hover="enumeration CrossTriggerOut {CrossTriggerOut_DebugRequest, CrossTriggerOut_RestartRequest, CrossTriggerOut_IRQ,          CrossTriggerOut_RSVD3, CrossTriggerOut_TraceExtIn0,  CrossTriggerOut_TraceExtIn1, CrossTriggerOut_TraceExtIn2,  CrossTriggerOut_TraceExtIn3}" conts="CrossTriggerOut">enumeration <anchor link="CrossTriggerOut" hover="enumeration CrossTriggerOut {CrossTriggerOut_DebugRequest, CrossTriggerOut_RestartRequest, CrossTriggerOut_IRQ,          CrossTriggerOut_RSVD3, CrossTriggerOut_TraceExtIn0,  CrossTriggerOut_TraceExtIn1, CrossTriggerOut_TraceExtIn2,  CrossTriggerOut_TraceExtIn3}">CrossTriggerOut</anchor> {<anchor link="CrossTriggerOut_DebugRequest" hover="enumeration CrossTriggerOut {CrossTriggerOut_DebugRequest, CrossTriggerOut_RestartRequest, CrossTriggerOut_IRQ,          CrossTriggerOut_RSVD3, CrossTriggerOut_TraceExtIn0,  CrossTriggerOut_TraceExtIn1, CrossTriggerOut_TraceExtIn2,  CrossTriggerOut_TraceExtIn3}">CrossTriggerOut_DebugRequest</anchor>, <anchor link="CrossTriggerOut_RestartRequest" hover="enumeration CrossTriggerOut {CrossTriggerOut_DebugRequest, CrossTriggerOut_RestartRequest, CrossTriggerOut_IRQ,          CrossTriggerOut_RSVD3, CrossTriggerOut_TraceExtIn0,  CrossTriggerOut_TraceExtIn1, CrossTriggerOut_TraceExtIn2,  CrossTriggerOut_TraceExtIn3}">CrossTriggerOut_RestartRequest</anchor>,</line>
<line link="CrossTriggerOut_IRQ" hover="enumeration CrossTriggerOut {CrossTriggerOut_DebugRequest, CrossTriggerOut_RestartRequest, CrossTriggerOut_IRQ,          CrossTriggerOut_RSVD3, CrossTriggerOut_TraceExtIn0,  CrossTriggerOut_TraceExtIn1, CrossTriggerOut_TraceExtIn2,  CrossTriggerOut_TraceExtIn3}" conts="CrossTriggerOut_IRQ">                             <anchor link="CrossTriggerOut_IRQ" hover="enumeration CrossTriggerOut {CrossTriggerOut_DebugRequest, CrossTriggerOut_RestartRequest, CrossTriggerOut_IRQ,          CrossTriggerOut_RSVD3, CrossTriggerOut_TraceExtIn0,  CrossTriggerOut_TraceExtIn1, CrossTriggerOut_TraceExtIn2,  CrossTriggerOut_TraceExtIn3}">CrossTriggerOut_IRQ</anchor>,          <anchor link="CrossTriggerOut_RSVD3" hover="enumeration CrossTriggerOut {CrossTriggerOut_DebugRequest, CrossTriggerOut_RestartRequest, CrossTriggerOut_IRQ,          CrossTriggerOut_RSVD3, CrossTriggerOut_TraceExtIn0,  CrossTriggerOut_TraceExtIn1, CrossTriggerOut_TraceExtIn2,  CrossTriggerOut_TraceExtIn3}">CrossTriggerOut_RSVD3</anchor>,</line>
<line link="CrossTriggerOut_TraceExtIn0" hover="enumeration CrossTriggerOut {CrossTriggerOut_DebugRequest, CrossTriggerOut_RestartRequest, CrossTriggerOut_IRQ,          CrossTriggerOut_RSVD3, CrossTriggerOut_TraceExtIn0,  CrossTriggerOut_TraceExtIn1, CrossTriggerOut_TraceExtIn2,  CrossTriggerOut_TraceExtIn3}" conts="CrossTriggerOut_TraceExtIn0">                             <anchor link="CrossTriggerOut_TraceExtIn0" hover="enumeration CrossTriggerOut {CrossTriggerOut_DebugRequest, CrossTriggerOut_RestartRequest, CrossTriggerOut_IRQ,          CrossTriggerOut_RSVD3, CrossTriggerOut_TraceExtIn0,  CrossTriggerOut_TraceExtIn1, CrossTriggerOut_TraceExtIn2,  CrossTriggerOut_TraceExtIn3}">CrossTriggerOut_TraceExtIn0</anchor>,  <anchor link="CrossTriggerOut_TraceExtIn1" hover="enumeration CrossTriggerOut {CrossTriggerOut_DebugRequest, CrossTriggerOut_RestartRequest, CrossTriggerOut_IRQ,          CrossTriggerOut_RSVD3, CrossTriggerOut_TraceExtIn0,  CrossTriggerOut_TraceExtIn1, CrossTriggerOut_TraceExtIn2,  CrossTriggerOut_TraceExtIn3}">CrossTriggerOut_TraceExtIn1</anchor>,</line>
<line link="CrossTriggerOut_TraceExtIn2" hover="enumeration CrossTriggerOut {CrossTriggerOut_DebugRequest, CrossTriggerOut_RestartRequest, CrossTriggerOut_IRQ,          CrossTriggerOut_RSVD3, CrossTriggerOut_TraceExtIn0,  CrossTriggerOut_TraceExtIn1, CrossTriggerOut_TraceExtIn2,  CrossTriggerOut_TraceExtIn3}" conts="CrossTriggerOut_TraceExtIn2">                             <anchor link="CrossTriggerOut_TraceExtIn2" hover="enumeration CrossTriggerOut {CrossTriggerOut_DebugRequest, CrossTriggerOut_RestartRequest, CrossTriggerOut_IRQ,          CrossTriggerOut_RSVD3, CrossTriggerOut_TraceExtIn0,  CrossTriggerOut_TraceExtIn1, CrossTriggerOut_TraceExtIn2,  CrossTriggerOut_TraceExtIn3}">CrossTriggerOut_TraceExtIn2</anchor>,  <anchor link="CrossTriggerOut_TraceExtIn3" hover="enumeration CrossTriggerOut {CrossTriggerOut_DebugRequest, CrossTriggerOut_RestartRequest, CrossTriggerOut_IRQ,          CrossTriggerOut_RSVD3, CrossTriggerOut_TraceExtIn0,  CrossTriggerOut_TraceExtIn1, CrossTriggerOut_TraceExtIn2,  CrossTriggerOut_TraceExtIn3}">CrossTriggerOut_TraceExtIn3</anchor>};</line>
<line></line>
<line link="CrossTriggerIn" hover="enumeration CrossTriggerIn  {CrossTriggerIn_CrossHalt,     CrossTriggerIn_PMUOverflow, CrossTriggerIn_RSVD2,         CrossTriggerIn_RSVD3, CrossTriggerIn_TraceExtOut0,  CrossTriggerIn_TraceExtOut1, CrossTriggerIn_TraceExtOut2,  CrossTriggerIn_TraceExtOut3}" conts="CrossTriggerIn">enumeration <anchor link="CrossTriggerIn" hover="enumeration CrossTriggerIn  {CrossTriggerIn_CrossHalt,     CrossTriggerIn_PMUOverflow, CrossTriggerIn_RSVD2,         CrossTriggerIn_RSVD3, CrossTriggerIn_TraceExtOut0,  CrossTriggerIn_TraceExtOut1, CrossTriggerIn_TraceExtOut2,  CrossTriggerIn_TraceExtOut3}">CrossTriggerIn</anchor>  {<anchor link="CrossTriggerIn_CrossHalt" hover="enumeration CrossTriggerIn  {CrossTriggerIn_CrossHalt,     CrossTriggerIn_PMUOverflow, CrossTriggerIn_RSVD2,         CrossTriggerIn_RSVD3, CrossTriggerIn_TraceExtOut0,  CrossTriggerIn_TraceExtOut1, CrossTriggerIn_TraceExtOut2,  CrossTriggerIn_TraceExtOut3}">CrossTriggerIn_CrossHalt</anchor>,     <anchor link="CrossTriggerIn_PMUOverflow" hover="enumeration CrossTriggerIn  {CrossTriggerIn_CrossHalt,     CrossTriggerIn_PMUOverflow, CrossTriggerIn_RSVD2,         CrossTriggerIn_RSVD3, CrossTriggerIn_TraceExtOut0,  CrossTriggerIn_TraceExtOut1, CrossTriggerIn_TraceExtOut2,  CrossTriggerIn_TraceExtOut3}">CrossTriggerIn_PMUOverflow</anchor>,</line>
<line link="CrossTriggerIn_RSVD2" hover="enumeration CrossTriggerIn  {CrossTriggerIn_CrossHalt,     CrossTriggerIn_PMUOverflow, CrossTriggerIn_RSVD2,         CrossTriggerIn_RSVD3, CrossTriggerIn_TraceExtOut0,  CrossTriggerIn_TraceExtOut1, CrossTriggerIn_TraceExtOut2,  CrossTriggerIn_TraceExtOut3}" conts="CrossTriggerIn_RSVD2">                             <anchor link="CrossTriggerIn_RSVD2" hover="enumeration CrossTriggerIn  {CrossTriggerIn_CrossHalt,     CrossTriggerIn_PMUOverflow, CrossTriggerIn_RSVD2,         CrossTriggerIn_RSVD3, CrossTriggerIn_TraceExtOut0,  CrossTriggerIn_TraceExtOut1, CrossTriggerIn_TraceExtOut2,  CrossTriggerIn_TraceExtOut3}">CrossTriggerIn_RSVD2</anchor>,         <anchor link="CrossTriggerIn_RSVD3" hover="enumeration CrossTriggerIn  {CrossTriggerIn_CrossHalt,     CrossTriggerIn_PMUOverflow, CrossTriggerIn_RSVD2,         CrossTriggerIn_RSVD3, CrossTriggerIn_TraceExtOut0,  CrossTriggerIn_TraceExtOut1, CrossTriggerIn_TraceExtOut2,  CrossTriggerIn_TraceExtOut3}">CrossTriggerIn_RSVD3</anchor>,</line>
<line link="CrossTriggerIn_TraceExtOut0" hover="enumeration CrossTriggerIn  {CrossTriggerIn_CrossHalt,     CrossTriggerIn_PMUOverflow, CrossTriggerIn_RSVD2,         CrossTriggerIn_RSVD3, CrossTriggerIn_TraceExtOut0,  CrossTriggerIn_TraceExtOut1, CrossTriggerIn_TraceExtOut2,  CrossTriggerIn_TraceExtOut3}" conts="CrossTriggerIn_TraceExtOut0">                             <anchor link="CrossTriggerIn_TraceExtOut0" hover="enumeration CrossTriggerIn  {CrossTriggerIn_CrossHalt,     CrossTriggerIn_PMUOverflow, CrossTriggerIn_RSVD2,         CrossTriggerIn_RSVD3, CrossTriggerIn_TraceExtOut0,  CrossTriggerIn_TraceExtOut1, CrossTriggerIn_TraceExtOut2,  CrossTriggerIn_TraceExtOut3}">CrossTriggerIn_TraceExtOut0</anchor>,  <anchor link="CrossTriggerIn_TraceExtOut1" hover="enumeration CrossTriggerIn  {CrossTriggerIn_CrossHalt,     CrossTriggerIn_PMUOverflow, CrossTriggerIn_RSVD2,         CrossTriggerIn_RSVD3, CrossTriggerIn_TraceExtOut0,  CrossTriggerIn_TraceExtOut1, CrossTriggerIn_TraceExtOut2,  CrossTriggerIn_TraceExtOut3}">CrossTriggerIn_TraceExtOut1</anchor>,</line>
<line link="CrossTriggerIn_TraceExtOut2" hover="enumeration CrossTriggerIn  {CrossTriggerIn_CrossHalt,     CrossTriggerIn_PMUOverflow, CrossTriggerIn_RSVD2,         CrossTriggerIn_RSVD3, CrossTriggerIn_TraceExtOut0,  CrossTriggerIn_TraceExtOut1, CrossTriggerIn_TraceExtOut2,  CrossTriggerIn_TraceExtOut3}" conts="CrossTriggerIn_TraceExtOut2">                             <anchor link="CrossTriggerIn_TraceExtOut2" hover="enumeration CrossTriggerIn  {CrossTriggerIn_CrossHalt,     CrossTriggerIn_PMUOverflow, CrossTriggerIn_RSVD2,         CrossTriggerIn_RSVD3, CrossTriggerIn_TraceExtOut0,  CrossTriggerIn_TraceExtOut1, CrossTriggerIn_TraceExtOut2,  CrossTriggerIn_TraceExtOut3}">CrossTriggerIn_TraceExtOut2</anchor>,  <anchor link="CrossTriggerIn_TraceExtOut3" hover="enumeration CrossTriggerIn  {CrossTriggerIn_CrossHalt,     CrossTriggerIn_PMUOverflow, CrossTriggerIn_RSVD2,         CrossTriggerIn_RSVD3, CrossTriggerIn_TraceExtOut0,  CrossTriggerIn_TraceExtOut1, CrossTriggerIn_TraceExtOut2,  CrossTriggerIn_TraceExtOut3}">CrossTriggerIn_TraceExtOut3</anchor>};</line>
</pstext>
    </ps>
    <ps name="shared/debug/dccanditr/CheckForDCCInterrupts" mylink="shared.debug.dccanditr.CheckForDCCInterrupts" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckForDCCInterrupts()</line>
<line>// =======================</line>
<line></line>
<line link="impl-shared.CheckForDCCInterrupts.0" hover="function: CheckForDCCInterrupts()" conts="CheckForDCCInterrupts"><anchor link="impl-shared.CheckForDCCInterrupts.0" hover="function: CheckForDCCInterrupts()">CheckForDCCInterrupts</anchor>()</line>
<line>    commrx = (EDSCR.RXfull == '1');</line>
<line>    commtx = (EDSCR.TXfull == '0');</line>
<line></line>
<line>    // COMMRX and COMMTX support is optional and not recommended for new designs.</line>
<line>    // SetInterruptRequestLevel(InterruptID_COMMRX, if commrx then HIGH else LOW);</line>
<line>    // SetInterruptRequestLevel(InterruptID_COMMTX, if commtx then HIGH else LOW);</line>
<line></line>
<line>    // The value to be driven onto the common COMMIRQ signal.</line>
<line>    boolean commirq;</line>
<line>    if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>        commirq = ((commrx &amp;&amp; DBGDCCINT.RX == '1') ||</line>
<line>                   (commtx &amp;&amp; DBGDCCINT.TX == '1'));</line>
<line>    else</line>
<line>        commirq = ((commrx &amp;&amp; MDCCINT_EL1.RX == '1') ||</line>
<line>                   (commtx &amp;&amp; MDCCINT_EL1.TX == '1'));</line>
<line>    SetInterruptRequestLevel(<a link="InterruptID_COMMIRQ" file="shared_pseudocode.xml" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_COMMIRQ</a>, if commirq then HIGH else LOW);</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/debug/dccanditr/DBGDTRRX_EL0" mylink="shared.debug.dccanditr.DBGDTRRX_EL0" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DBGDTRRX_EL0[] (external write)</line>
<line>// ===============================</line>
<line>// Called on writes to debug register 0x08C.</line>
<line></line>
<line link="impl-shared.DBGDTRRX_EL0.write.1" hover="accessor: DBGDTRRX_EL0[boolean memory_mapped] = bits(32) value" conts="DBGDTRRX_EL0"><anchor link="impl-shared.DBGDTRRX_EL0.write.1" hover="accessor: DBGDTRRX_EL0[boolean memory_mapped] = bits(32) value">DBGDTRRX_EL0</anchor>[boolean memory_mapped] = bits(32) value</line>
<line></line>
<line>    if EDPRSR&lt;6:5,0&gt; != '001' then                      // Check DLK, OSLK and PU bits</line>
<line>        IMPLEMENTATION_DEFINED "generate error response";</line>
<line>        return;</line>
<line></line>
<line>    if EDSCR.ERR == '1' then return;                    // Error flag set: ignore write</line>
<line></line>
<line>    // The Software lock is OPTIONAL.</line>
<line>    if memory_mapped &amp;&amp; EDLSR.SLK == '1' then return;   // Software lock locked: ignore write</line>
<line></line>
<line>    if EDSCR.RXfull == '1' || (<a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() &amp;&amp; EDSCR.MA == '1' &amp;&amp; EDSCR.ITE == '0') then</line>
<line>        EDSCR.RXO = '1';  EDSCR.ERR = '1';              // Overrun condition: ignore write</line>
<line>        return;</line>
<line></line>
<line>    EDSCR.RXfull = '1';</line>
<line>    DTRRX = value;</line>
<line></line>
<line>    if <a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() &amp;&amp; EDSCR.MA == '1' then</line>
<line>        EDSCR.ITE = '0';                            // See comments in EDITR[] (external write)</line>
<line>        if !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>            <a link="impl-shared.ExecuteA64.1" file="shared_pseudocode.xml" hover="function: ExecuteA64(bits(32) instr)">ExecuteA64</a>(0xD5330501&lt;31:0&gt;);               // A64 "MRS X1,DBGDTRRX_EL0"</line>
<line>            <a link="impl-shared.ExecuteA64.1" file="shared_pseudocode.xml" hover="function: ExecuteA64(bits(32) instr)">ExecuteA64</a>(0xB8004401&lt;31:0&gt;);               // A64 "STR W1,[X0],#4"</line>
<line>            <a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[1, 64] = bits(64) UNKNOWN;</line>
<line>        else</line>
<line>            <a link="impl-shared.ExecuteT32.2" file="shared_pseudocode.xml" hover="function: ExecuteT32(bits(16) hw1, bits(16) hw2)">ExecuteT32</a>(0xEE10&lt;15:0&gt; /*hw1*/, 0x1E15&lt;15:0&gt; /*hw2*/);  // T32 "MRS R1,DBGDTRRXint"</line>
<line>            <a link="impl-shared.ExecuteT32.2" file="shared_pseudocode.xml" hover="function: ExecuteT32(bits(16) hw1, bits(16) hw2)">ExecuteT32</a>(0xF840&lt;15:0&gt; /*hw1*/, 0x1B04&lt;15:0&gt; /*hw2*/);  // T32 "STR R1,[R0],#4"</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[1] = bits(32) UNKNOWN;</line>
<line>        // If the store aborts, the Data Abort exception is taken and EDSCR.ERR is set to 1</line>
<line>        if EDSCR.ERR == '1' then</line>
<line>            EDSCR.RXfull = bit UNKNOWN;</line>
<line>            DBGDTRRX_EL0 = bits(64) UNKNOWN;</line>
<line>        else</line>
<line>            // "MRS X1,DBGDTRRX_EL0" calls DBGDTR_EL0[] (read) which clears RXfull.</line>
<line>            assert EDSCR.RXfull == '0';</line>
<line></line>
<line>        EDSCR.ITE = '1';                                // See comments in EDITR[] (external write)</line>
<line>    return;</line>
<line></line>
<line>// DBGDTRRX_EL0[] (external read)</line>
<line>// ==============================</line>
<line></line>
<line link="impl-shared.DBGDTRRX_EL0.read.1" hover="accessor: bits(32) DBGDTRRX_EL0[boolean memory_mapped]" conts="DBGDTRRX_EL0">bits(32) <anchor link="impl-shared.DBGDTRRX_EL0.read.1" hover="accessor: bits(32) DBGDTRRX_EL0[boolean memory_mapped]">DBGDTRRX_EL0</anchor>[boolean memory_mapped]</line>
<line>    return DTRRX;</line>
</pstext>
    </ps>
    <ps name="shared/debug/dccanditr/DBGDTRTX_EL0" mylink="shared.debug.dccanditr.DBGDTRTX_EL0" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DBGDTRTX_EL0[] (external read)</line>
<line>// ==============================</line>
<line>// Called on reads of debug register 0x080.</line>
<line></line>
<line link="impl-shared.DBGDTRTX_EL0.read.1" hover="accessor: bits(32) DBGDTRTX_EL0[boolean memory_mapped]" conts="DBGDTRTX_EL0">bits(32) <anchor link="impl-shared.DBGDTRTX_EL0.read.1" hover="accessor: bits(32) DBGDTRTX_EL0[boolean memory_mapped]">DBGDTRTX_EL0</anchor>[boolean memory_mapped]</line>
<line></line>
<line>    if EDPRSR&lt;6:5,0&gt; != '001' then                      // Check DLK, OSLK and PU bits</line>
<line>        IMPLEMENTATION_DEFINED "generate error response";</line>
<line>        return bits(32) UNKNOWN;</line>
<line></line>
<line>    underrun = EDSCR.TXfull == '0' || (<a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() &amp;&amp; EDSCR.MA == '1' &amp;&amp; EDSCR.ITE == '0');</line>
<line>    value = if underrun then bits(32) UNKNOWN else DTRTX;</line>
<line></line>
<line>    if EDSCR.ERR == '1' then return value;              // Error flag set: no side-effects</line>
<line></line>
<line>    // The Software lock is OPTIONAL.</line>
<line>    if memory_mapped &amp;&amp; EDLSR.SLK == '1' then           // Software lock locked: no side-effects</line>
<line>        return value;</line>
<line></line>
<line>    if underrun then</line>
<line>        EDSCR.TXU = '1';  EDSCR.ERR = '1';              // Underrun condition: block side-effects</line>
<line>        return value;                                   // Return UNKNOWN</line>
<line></line>
<line>    EDSCR.TXfull = '0';</line>
<line>    if <a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() &amp;&amp; EDSCR.MA == '1' then</line>
<line>        EDSCR.ITE = '0';                                // See comments in EDITR[] (external write)</line>
<line></line>
<line>        if !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>            <a link="impl-shared.ExecuteA64.1" file="shared_pseudocode.xml" hover="function: ExecuteA64(bits(32) instr)">ExecuteA64</a>(0xB8404401&lt;31:0&gt;);               // A64 "LDR W1,[X0],#4"</line>
<line>        else</line>
<line>            <a link="impl-shared.ExecuteT32.2" file="shared_pseudocode.xml" hover="function: ExecuteT32(bits(16) hw1, bits(16) hw2)">ExecuteT32</a>(0xF850&lt;15:0&gt; /*hw1*/, 0x1B04&lt;15:0&gt; /*hw2*/);      // T32 "LDR R1,[R0],#4"</line>
<line>        // If the load aborts, the Data Abort exception is taken and EDSCR.ERR is set to 1</line>
<line>        if EDSCR.ERR == '1' then</line>
<line>            EDSCR.TXfull = bit UNKNOWN;</line>
<line>            DBGDTRTX_EL0 = bits(64) UNKNOWN;</line>
<line>        else</line>
<line>            if !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>                <a link="impl-shared.ExecuteA64.1" file="shared_pseudocode.xml" hover="function: ExecuteA64(bits(32) instr)">ExecuteA64</a>(0xD5130501&lt;31:0&gt;);           // A64 "MSR DBGDTRTX_EL0,X1"</line>
<line>            else</line>
<line>                <a link="impl-shared.ExecuteT32.2" file="shared_pseudocode.xml" hover="function: ExecuteT32(bits(16) hw1, bits(16) hw2)">ExecuteT32</a>(0xEE00&lt;15:0&gt; /*hw1*/, 0x1E15&lt;15:0&gt; /*hw2*/);  // T32 "MSR DBGDTRTXint,R1"</line>
<line>            // "MSR DBGDTRTX_EL0,X1" calls DBGDTR_EL0[] (write) which sets TXfull.</line>
<line>            assert EDSCR.TXfull == '1';</line>
<line>        if !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>            <a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[1, 64] = bits(64) UNKNOWN;</line>
<line>        else</line>
<line>            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[1] = bits(32) UNKNOWN;</line>
<line>        EDSCR.ITE = '1';                                // See comments in EDITR[] (external write)</line>
<line></line>
<line>    return value;</line>
<line></line>
<line>// DBGDTRTX_EL0[] (external write)</line>
<line>// ===============================</line>
<line></line>
<line link="impl-shared.DBGDTRTX_EL0.write.1" hover="accessor: DBGDTRTX_EL0[boolean memory_mapped] = bits(32) value" conts="DBGDTRTX_EL0"><anchor link="impl-shared.DBGDTRTX_EL0.write.1" hover="accessor: DBGDTRTX_EL0[boolean memory_mapped] = bits(32) value">DBGDTRTX_EL0</anchor>[boolean memory_mapped] = bits(32) value</line>
<line>    // The Software lock is OPTIONAL.</line>
<line>    if memory_mapped &amp;&amp; EDLSR.SLK == '1' then return;   // Software lock locked: ignore write</line>
<line>    DTRTX = value;</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/debug/dccanditr/DBGDTR_EL0" mylink="shared.debug.dccanditr.DBGDTR_EL0" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DBGDTR_EL0[] (write)</line>
<line>// ====================</line>
<line>// System register writes to DBGDTR_EL0, DBGDTRTX_EL0 (AArch64) and DBGDTRTXint (AArch32)</line>
<line></line>
<line>DBGDTR_EL0[] = bits(N) value_in</line>
<line>    bits(N) value = value_in;</line>
<line>    // For MSR DBGDTRTX_EL0,&lt;Rt&gt;  N=32, value=X[t]&lt;31:0&gt;, X[t]&lt;63:32&gt; is ignored</line>
<line>    // For MSR DBGDTR_EL0,&lt;Xt&gt;    N=64, value=X[t]&lt;63:0&gt;</line>
<line>    assert N IN {32,64};</line>
<line>    if EDSCR.TXfull == '1' then</line>
<line>        value = bits(N) UNKNOWN;</line>
<line>    // On a 64-bit write, implement a half-duplex channel</line>
<line>    if N == 64 then DTRRX = value&lt;63:32&gt;;</line>
<line>    DTRTX = value&lt;31:0&gt;;        // 32-bit or 64-bit write</line>
<line>    EDSCR.TXfull = '1';</line>
<line>    return;</line>
<line></line>
<line>// DBGDTR_EL0[] (read)</line>
<line>// ===================</line>
<line>// System register reads of DBGDTR_EL0, DBGDTRRX_EL0 (AArch64) and DBGDTRRXint (AArch32)</line>
<line></line>
<line link="impl-shared.DBGDTR_EL0.read.0" hover="accessor: bits(N) DBGDTR_EL0[]" conts="DBGDTR_EL0">bits(N) <anchor link="impl-shared.DBGDTR_EL0.read.0" hover="accessor: bits(N) DBGDTR_EL0[]">DBGDTR_EL0</anchor>[]</line>
<line>    // For MRS &lt;Rt&gt;,DBGDTRTX_EL0  N=32, X[t]=Zeros(32):result</line>
<line>    // For MRS &lt;Xt&gt;,DBGDTR_EL0    N=64, X[t]=result</line>
<line>    assert N IN {32,64};</line>
<line>    bits(N) result;</line>
<line>    if EDSCR.RXfull == '0' then</line>
<line>        result = bits(N) UNKNOWN;</line>
<line>    else</line>
<line>        // On a 64-bit read, implement a half-duplex channel</line>
<line>        // NOTE: the word order is reversed on reads with regards to writes</line>
<line>        if N == 64 then result&lt;63:32&gt; = DTRTX;</line>
<line>        result&lt;31:0&gt; = DTRRX;</line>
<line>    EDSCR.RXfull = '0';</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/debug/dccanditr/DTR" mylink="shared.debug.dccanditr.DTR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>bits(32) DTRRX;</line>
<line>bits(32) DTRTX;</line>
</pstext>
    </ps>
    <ps name="shared/debug/dccanditr/EDITR" mylink="shared.debug.dccanditr.EDITR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EDITR[] (external write)</line>
<line>// ========================</line>
<line>// Called on writes to debug register 0x084.</line>
<line></line>
<line link="impl-shared.EDITR.write.1" hover="accessor: EDITR[boolean memory_mapped] = bits(32) value" conts="EDITR"><anchor link="impl-shared.EDITR.write.1" hover="accessor: EDITR[boolean memory_mapped] = bits(32) value">EDITR</anchor>[boolean memory_mapped] = bits(32) value</line>
<line>    if EDPRSR&lt;6:5,0&gt; != '001' then                      // Check DLK, OSLK and PU bits</line>
<line>        IMPLEMENTATION_DEFINED "generate error response";</line>
<line>        return;</line>
<line></line>
<line>    if EDSCR.ERR == '1' then return;                    // Error flag set: ignore write</line>
<line></line>
<line>    // The Software lock is OPTIONAL.</line>
<line>    if memory_mapped &amp;&amp; EDLSR.SLK == '1' then return;   // Software lock locked: ignore write</line>
<line></line>
<line>    if !<a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() then return;                           // Non-debug state: ignore write</line>
<line></line>
<line>    if EDSCR.ITE == '0' || EDSCR.MA == '1' then</line>
<line>        EDSCR.ITO = '1';  EDSCR.ERR = '1';              // Overrun condition: block write</line>
<line>        return;</line>
<line></line>
<line>    // ITE indicates whether the processor is ready to accept another instruction; the processor</line>
<line>    // may support multiple outstanding instructions. Unlike the "InstrCompl" flag in [v7A] there</line>
<line>    // is no indication that the pipeline is empty (all instructions have completed). In this</line>
<line>    // pseudocode, the assumption is that only one instruction can be executed at a time,</line>
<line>    // meaning ITE acts like "InstrCompl".</line>
<line>    EDSCR.ITE = '0';</line>
<line></line>
<line>    if !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        <a link="impl-shared.ExecuteA64.1" file="shared_pseudocode.xml" hover="function: ExecuteA64(bits(32) instr)">ExecuteA64</a>(value);</line>
<line>    else</line>
<line>        <a link="impl-shared.ExecuteT32.2" file="shared_pseudocode.xml" hover="function: ExecuteT32(bits(16) hw1, bits(16) hw2)">ExecuteT32</a>(value&lt;15:0&gt;/*hw1*/, value&lt;31:16&gt; /*hw2*/);</line>
<line></line>
<line>    EDSCR.ITE = '1';</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/debug/halting/DCPSInstruction" mylink="shared.debug.halting.DCPSInstruction" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DCPSInstruction()</line>
<line>// =================</line>
<line>// Operation of the DCPS instruction in Debug state</line>
<line></line>
<line link="impl-shared.DCPSInstruction.1" hover="function: DCPSInstruction(bits(2) target_el)" conts="DCPSInstruction"><anchor link="impl-shared.DCPSInstruction.1" hover="function: DCPSInstruction(bits(2) target_el)">DCPSInstruction</anchor>(bits(2) target_el)</line>
<line></line>
<line>    <a link="impl-shared.SynchronizeContext.0" file="shared_pseudocode.xml" hover="function: SynchronizeContext()">SynchronizeContext</a>();</line>
<line></line>
<line>    bits(2) handle_el;</line>
<line>    case target_el of</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || (PSTATE.EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>()) then</line>
<line>                handle_el = PSTATE.EL;</line>
<line>            elsif <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.TGE == '1' then</line>
<line>                UNDEFINED;</line>
<line>            else</line>
<line>                handle_el = <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>                UNDEFINED;</line>
<line>            elsif PSTATE.EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>                handle_el = <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line>            elsif !<a link="impl-shared.IsSecureEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsSecureEL2Enabled()">IsSecureEL2Enabled</a>() &amp;&amp; <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>                UNDEFINED;</line>
<line>            else</line>
<line>                handle_el = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            if EDSCR.SDD == '1' || !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>                UNDEFINED;</line>
<line>            else</line>
<line>                handle_el = <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line>        otherwise</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    from_secure = <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>;</line>
<line>    if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(handle_el) then</line>
<line>        if PSTATE.M == <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a> then SCR.NS = '0';</line>
<line>        assert <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>();                  // Cannot move from AArch64 to AArch32</line>
<line>        case handle_el of</line>
<line>            when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>                <a link="AArch32.WriteMode.1" file="shared_pseudocode.xml" hover="function: AArch32.WriteMode(bits(5) mode)">AArch32.WriteMode</a>(<a link="M32_Svc" file="shared_pseudocode.xml" hover="constant bits(5) M32_Svc = '10011'">M32_Svc</a>);</line>
<line>                if <a link="impl-shared.HavePANExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePANExt()">HavePANExt</a>() &amp;&amp; SCTLR.SPAN == '0' then</line>
<line>                    PSTATE.PAN = '1';</line>
<line>            when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>  <a link="AArch32.WriteMode.1" file="shared_pseudocode.xml" hover="function: AArch32.WriteMode(bits(5) mode)">AArch32.WriteMode</a>(<a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a>);</line>
<line>            when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>                <a link="AArch32.WriteMode.1" file="shared_pseudocode.xml" hover="function: AArch32.WriteMode(bits(5) mode)">AArch32.WriteMode</a>(<a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a>);</line>
<line>                if <a link="impl-shared.HavePANExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePANExt()">HavePANExt</a>() then</line>
<line>                    if !from_secure then</line>
<line>                        PSTATE.PAN = '0';</line>
<line>                    elsif SCTLR.SPAN == '0' then</line>
<line>                        PSTATE.PAN = '1';</line>
<line>        if handle_el == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>            ELR_hyp = bits(32) UNKNOWN;  HSR = bits(32) UNKNOWN;</line>
<line>        else</line>
<line>            <a link="impl-aarch32.LR.write.none" file="shared_pseudocode.xml" hover="accessor: LR = bits(32) value">LR</a> = bits(32) UNKNOWN;</line>
<line>        <a link="impl-shared.SPSR.write.0" file="shared_pseudocode.xml" hover="accessor: SPSR[] = bits(N) value">SPSR</a>[] = bits(32) UNKNOWN;</line>
<line>        PSTATE.E = <a link="impl-aarch64.SCTLR.read.0" file="shared_pseudocode.xml" hover="accessor: SCTLRType SCTLR[]">SCTLR</a>[].EE;</line>
<line>        DLR = bits(32) UNKNOWN;  DSPSR = bits(32) UNKNOWN;</line>
<line></line>
<line>    else                                        // Targeting AArch64</line>
<line>        from_32 = <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>();</line>
<line>        if from_32 then <a link="AArch64.MaybeZeroRegisterUppers.0" file="shared_pseudocode.xml" hover="function: AArch64.MaybeZeroRegisterUppers()">AArch64.MaybeZeroRegisterUppers</a>();</line>
<line>        if from_32 &amp;&amp; <a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() &amp;&amp; PSTATE.SM == '1' then</line>
<line>            <a link="impl-aarch64.ResetSVEState.0" file="shared_pseudocode.xml" hover="function: ResetSVEState()">ResetSVEState</a>();</line>
<line>        else</line>
<line>            <a link="impl-aarch64.MaybeZeroSVEUppers.1" file="shared_pseudocode.xml" hover="function: MaybeZeroSVEUppers(bits(2) target_el)">MaybeZeroSVEUppers</a>(target_el);</line>
<line>        PSTATE.nRW = '0';  PSTATE.SP = '1';  PSTATE.EL = handle_el;</line>
<line>        if <a link="impl-shared.HavePANExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePANExt()">HavePANExt</a>() &amp;&amp; ((handle_el == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; SCTLR_EL1.SPAN == '0') ||</line>
<line>                            (handle_el == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> &amp;&amp; HCR_EL2.E2H == '1' &amp;&amp;</line>
<line>                             HCR_EL2.TGE == '1' &amp;&amp; SCTLR_EL2.SPAN == '0')) then</line>
<line>            PSTATE.PAN = '1';</line>
<line>        <a link="impl-aarch64.ELR.write.0" file="shared_pseudocode.xml" hover="accessor: ELR[] = bits(64) value">ELR</a>[] = bits(64) UNKNOWN;  <a link="impl-shared.SPSR.write.0" file="shared_pseudocode.xml" hover="accessor: SPSR[] = bits(N) value">SPSR</a>[] = bits(64) UNKNOWN;  <a link="impl-aarch64.ESR.write.0" file="shared_pseudocode.xml" hover="accessor: ESR[] = ESRType value">ESR</a>[] = bits(64) UNKNOWN;</line>
<line>        DLR_EL0 = bits(64) UNKNOWN;  DSPSR_EL0 = bits(64) UNKNOWN;</line>
<line>        if <a link="impl-shared.HaveUAOExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveUAOExt()">HaveUAOExt</a>() then PSTATE.UAO = '0';</line>
<line>        if <a link="impl-shared.HaveMTEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEExt()">HaveMTEExt</a>() then PSTATE.TCO = '1';</line>
<line>        if <a link="impl-shared.HaveGCS.0" file="shared_pseudocode.xml" hover="function: boolean HaveGCS()">HaveGCS</a>() then PSTATE.EXLOCK = '0';</line>
<line></line>
<line>    <a link="impl-shared.UpdateEDSCRFields.0" file="shared_pseudocode.xml" hover="function: UpdateEDSCRFields()">UpdateEDSCRFields</a>();                        // Update EDSCR PE state flags</line>
<line>    sync_errors = <a link="impl-shared.HaveIESB.0" file="shared_pseudocode.xml" hover="function: boolean HaveIESB()">HaveIESB</a>() &amp;&amp; <a link="impl-aarch64.SCTLR.read.0" file="shared_pseudocode.xml" hover="accessor: SCTLRType SCTLR[]">SCTLR</a>[].IESB == '1';</line>
<line>    if <a link="impl-shared.HaveDoubleFaultExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDoubleFaultExt()">HaveDoubleFaultExt</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        sync_errors = (sync_errors ||</line>
<line>                       (<a link="impl-shared.EffectiveEA.0" file="shared_pseudocode.xml" hover="function: bit EffectiveEA()">EffectiveEA</a>() == '1' &amp;&amp; SCR_EL3.NMEA == '1' &amp;&amp; PSTATE.EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>));</line>
<line>    // SCTLR[].IESB might be ignored in Debug state.</line>
<line>    if !<a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_IESBinDebug" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_IESBinDebug</a>) then</line>
<line>        sync_errors = FALSE;</line>
<line>    if sync_errors then</line>
<line>        <a link="impl-shared.SynchronizeErrors.0" file="shared_pseudocode.xml" hover="function: SynchronizeErrors()">SynchronizeErrors</a>();</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/debug/halting/DRPSInstruction" mylink="shared.debug.halting.DRPSInstruction" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DRPSInstruction()</line>
<line>// =================</line>
<line>// Operation of the A64 DRPS and T32 ERET instructions in Debug state</line>
<line></line>
<line link="impl-shared.DRPSInstruction.0" hover="function: DRPSInstruction()" conts="DRPSInstruction"><anchor link="impl-shared.DRPSInstruction.0" hover="function: DRPSInstruction()">DRPSInstruction</anchor>()</line>
<line></line>
<line>    <a link="impl-shared.SynchronizeContext.0" file="shared_pseudocode.xml" hover="function: SynchronizeContext()">SynchronizeContext</a>();</line>
<line></line>
<line>    sync_errors = <a link="impl-shared.HaveIESB.0" file="shared_pseudocode.xml" hover="function: boolean HaveIESB()">HaveIESB</a>() &amp;&amp; <a link="impl-aarch64.SCTLR.read.0" file="shared_pseudocode.xml" hover="accessor: SCTLRType SCTLR[]">SCTLR</a>[].IESB == '1';</line>
<line>    if <a link="impl-shared.HaveDoubleFaultExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDoubleFaultExt()">HaveDoubleFaultExt</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        sync_errors = (sync_errors ||</line>
<line>                       (<a link="impl-shared.EffectiveEA.0" file="shared_pseudocode.xml" hover="function: bit EffectiveEA()">EffectiveEA</a>() == '1' &amp;&amp; SCR_EL3.NMEA == '1' &amp;&amp; PSTATE.EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>));</line>
<line>    // SCTLR[].IESB might be ignored in Debug state.</line>
<line>    if !<a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_IESBinDebug" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_IESBinDebug</a>) then</line>
<line>        sync_errors = FALSE;</line>
<line>    if sync_errors then</line>
<line>        <a link="impl-shared.SynchronizeErrors.0" file="shared_pseudocode.xml" hover="function: SynchronizeErrors()">SynchronizeErrors</a>();</line>
<line></line>
<line>    <a link="impl-shared.DebugRestorePSR.0" file="shared_pseudocode.xml" hover="function: DebugRestorePSR()">DebugRestorePSR</a>();</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/debug/halting/DebugHalt" mylink="shared.debug.halting.DebugHalt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="DebugHalt_Breakpoint" hover="constant bits(6) DebugHalt_Breakpoint = '000111'" conts="DebugHalt_Breakpoint">constant bits(6) <anchor link="DebugHalt_Breakpoint" hover="constant bits(6) DebugHalt_Breakpoint = '000111'">DebugHalt_Breakpoint</anchor>      = '000111';</line>
<line link="DebugHalt_EDBGRQ" hover="constant bits(6) DebugHalt_EDBGRQ = '010011'" conts="DebugHalt_EDBGRQ">constant bits(6) <anchor link="DebugHalt_EDBGRQ" hover="constant bits(6) DebugHalt_EDBGRQ = '010011'">DebugHalt_EDBGRQ</anchor>          = '010011';</line>
<line link="DebugHalt_Step_Normal" hover="constant bits(6) DebugHalt_Step_Normal = '011011'" conts="DebugHalt_Step_Normal">constant bits(6) <anchor link="DebugHalt_Step_Normal" hover="constant bits(6) DebugHalt_Step_Normal = '011011'">DebugHalt_Step_Normal</anchor>     = '011011';</line>
<line link="DebugHalt_Step_Exclusive" hover="constant bits(6) DebugHalt_Step_Exclusive = '011111'" conts="DebugHalt_Step_Exclusive">constant bits(6) <anchor link="DebugHalt_Step_Exclusive" hover="constant bits(6) DebugHalt_Step_Exclusive = '011111'">DebugHalt_Step_Exclusive</anchor>  = '011111';</line>
<line link="DebugHalt_OSUnlockCatch" hover="constant bits(6) DebugHalt_OSUnlockCatch = '100011'" conts="DebugHalt_OSUnlockCatch">constant bits(6) <anchor link="DebugHalt_OSUnlockCatch" hover="constant bits(6) DebugHalt_OSUnlockCatch = '100011'">DebugHalt_OSUnlockCatch</anchor>   = '100011';</line>
<line link="DebugHalt_ResetCatch" hover="constant bits(6) DebugHalt_ResetCatch = '100111'" conts="DebugHalt_ResetCatch">constant bits(6) <anchor link="DebugHalt_ResetCatch" hover="constant bits(6) DebugHalt_ResetCatch = '100111'">DebugHalt_ResetCatch</anchor>      = '100111';</line>
<line link="DebugHalt_Watchpoint" hover="constant bits(6) DebugHalt_Watchpoint = '101011'" conts="DebugHalt_Watchpoint">constant bits(6) <anchor link="DebugHalt_Watchpoint" hover="constant bits(6) DebugHalt_Watchpoint = '101011'">DebugHalt_Watchpoint</anchor>      = '101011';</line>
<line link="DebugHalt_HaltInstruction" hover="constant bits(6) DebugHalt_HaltInstruction = '101111'" conts="DebugHalt_HaltInstruction">constant bits(6) <anchor link="DebugHalt_HaltInstruction" hover="constant bits(6) DebugHalt_HaltInstruction = '101111'">DebugHalt_HaltInstruction</anchor> = '101111';</line>
<line link="DebugHalt_SoftwareAccess" hover="constant bits(6) DebugHalt_SoftwareAccess = '110011'" conts="DebugHalt_SoftwareAccess">constant bits(6) <anchor link="DebugHalt_SoftwareAccess" hover="constant bits(6) DebugHalt_SoftwareAccess = '110011'">DebugHalt_SoftwareAccess</anchor>  = '110011';</line>
<line link="DebugHalt_ExceptionCatch" hover="constant bits(6) DebugHalt_ExceptionCatch = '110111'" conts="DebugHalt_ExceptionCatch">constant bits(6) <anchor link="DebugHalt_ExceptionCatch" hover="constant bits(6) DebugHalt_ExceptionCatch = '110111'">DebugHalt_ExceptionCatch</anchor>  = '110111';</line>
<line link="DebugHalt_Step_NoSyndrome" hover="constant bits(6) DebugHalt_Step_NoSyndrome = '111011'" conts="DebugHalt_Step_NoSyndrome">constant bits(6) <anchor link="DebugHalt_Step_NoSyndrome" hover="constant bits(6) DebugHalt_Step_NoSyndrome = '111011'">DebugHalt_Step_NoSyndrome</anchor> = '111011';</line>
</pstext>
    </ps>
    <ps name="shared/debug/halting/DebugRestorePSR" mylink="shared.debug.halting.DebugRestorePSR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DebugRestorePSR()</line>
<line>// =================</line>
<line></line>
<line link="impl-shared.DebugRestorePSR.0" hover="function: DebugRestorePSR()" conts="DebugRestorePSR"><anchor link="impl-shared.DebugRestorePSR.0" hover="function: DebugRestorePSR()">DebugRestorePSR</anchor>()</line>
<line>    // PSTATE.{N,Z,C,V,Q,GE,SS,D,A,I,F} are not observable and ignored in Debug state, so</line>
<line>    // behave as if UNKNOWN.</line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        bits(32) spsr = <a link="impl-shared.SPSR.read.0" file="shared_pseudocode.xml" hover="accessor: bits(N) SPSR[]">SPSR</a>[];</line>
<line>        <a link="impl-shared.SetPSTATEFromPSR.1" file="shared_pseudocode.xml" hover="function: SetPSTATEFromPSR(bits(N) spsr)">SetPSTATEFromPSR</a>(spsr);</line>
<line>        PSTATE.&lt;N,Z,C,V,Q,GE,SS,A,I,F&gt; = bits(13) UNKNOWN;</line>
<line>        //  In AArch32, all instructions are T32 and unconditional.</line>
<line>        PSTATE.IT = '00000000';  PSTATE.T = '1';        // PSTATE.J is RES0</line>
<line>        DLR = bits(32) UNKNOWN;  DSPSR = bits(32) UNKNOWN;</line>
<line>    else</line>
<line>        bits(64) spsr = <a link="impl-shared.SPSR.read.0" file="shared_pseudocode.xml" hover="accessor: bits(N) SPSR[]">SPSR</a>[];</line>
<line>        <a link="impl-shared.SetPSTATEFromPSR.1" file="shared_pseudocode.xml" hover="function: SetPSTATEFromPSR(bits(N) spsr)">SetPSTATEFromPSR</a>(spsr);</line>
<line>        PSTATE.&lt;N,Z,C,V,SS,D,A,I,F&gt; = bits(9) UNKNOWN;</line>
<line>        DLR_EL0 = bits(64) UNKNOWN;  DSPSR_EL0 = bits(64) UNKNOWN;</line>
<line>    <a link="impl-shared.UpdateEDSCRFields.0" file="shared_pseudocode.xml" hover="function: UpdateEDSCRFields()">UpdateEDSCRFields</a>();                                // Update EDSCR PE state flags</line>
</pstext>
    </ps>
    <ps name="shared/debug/halting/DisableITRAndResumeInstructionPrefetch" mylink="shared.debug.halting.DisableITRAndResumeInstructionPrefetch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DisableITRAndResumeInstructionPrefetch()</line>
<line>// ========================================</line>
<line></line>
<line link="impl-shared.DisableITRAndResumeInstructionPrefetch.0" hover="function: DisableITRAndResumeInstructionPrefetch()" conts="DisableITRAndResumeInstructionPrefetch"><anchor link="impl-shared.DisableITRAndResumeInstructionPrefetch.0" hover="function: DisableITRAndResumeInstructionPrefetch()">DisableITRAndResumeInstructionPrefetch</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/debug/halting/ExecuteA64" mylink="shared.debug.halting.ExecuteA64" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExecuteA64()</line>
<line>// ============</line>
<line>// Execute an A64 instruction in Debug state.</line>
<line></line>
<line link="impl-shared.ExecuteA64.1" hover="function: ExecuteA64(bits(32) instr)" conts="ExecuteA64"><anchor link="impl-shared.ExecuteA64.1" hover="function: ExecuteA64(bits(32) instr)">ExecuteA64</anchor>(bits(32) instr);</line>
</pstext>
    </ps>
    <ps name="shared/debug/halting/ExecuteT32" mylink="shared.debug.halting.ExecuteT32" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExecuteT32()</line>
<line>// ============</line>
<line>// Execute a T32 instruction in Debug state.</line>
<line></line>
<line link="impl-shared.ExecuteT32.2" hover="function: ExecuteT32(bits(16) hw1, bits(16) hw2)" conts="ExecuteT32"><anchor link="impl-shared.ExecuteT32.2" hover="function: ExecuteT32(bits(16) hw1, bits(16) hw2)">ExecuteT32</anchor>(bits(16) hw1, bits(16) hw2);</line>
</pstext>
    </ps>
    <ps name="shared/debug/halting/ExitDebugState" mylink="shared.debug.halting.ExitDebugState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExitDebugState()</line>
<line>// ================</line>
<line></line>
<line link="impl-shared.ExitDebugState.0" hover="function: ExitDebugState()" conts="ExitDebugState"><anchor link="impl-shared.ExitDebugState.0" hover="function: ExitDebugState()">ExitDebugState</anchor>()</line>
<line>    assert <a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>();</line>
<line>    <a link="impl-shared.SynchronizeContext.0" file="shared_pseudocode.xml" hover="function: SynchronizeContext()">SynchronizeContext</a>();</line>
<line></line>
<line>    // Although EDSCR.STATUS signals that the PE is restarting, debuggers must use EDPRSR.SDR to</line>
<line>    // detect that the PE has restarted.</line>
<line>    EDSCR.STATUS = '000001';                           // Signal restarting</line>
<line>    // Clear any pending Halting debug events</line>
<line>    if <a link="impl-shared.Havev8p8Debug.0" file="shared_pseudocode.xml" hover="function: boolean Havev8p8Debug()">Havev8p8Debug</a>() then</line>
<line>        EDESR&lt;3:0&gt; = '0000';</line>
<line>    else</line>
<line>        EDESR&lt;2:0&gt; = '000';</line>
<line></line>
<line>    bits(64) new_pc;</line>
<line>    bits(64) spsr;</line>
<line></line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        new_pc = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(DLR, 64);</line>
<line>        if <a link="impl-shared.Havev8p9Debug.0" file="shared_pseudocode.xml" hover="function: boolean Havev8p9Debug()">Havev8p9Debug</a>() then</line>
<line>            spsr = DSPSR2 : DSPSR;</line>
<line>        else</line>
<line>            spsr = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(DSPSR, 64);</line>
<line>    else</line>
<line>        new_pc = DLR_EL0;</line>
<line>        spsr = DSPSR_EL0;</line>
<line></line>
<line>    boolean illegal_psr_state = <a link="impl-shared.IllegalExceptionReturn.1" file="shared_pseudocode.xml" hover="function: boolean IllegalExceptionReturn(bits(N) spsr)">IllegalExceptionReturn</a>(spsr);</line>
<line>    // If this is an illegal return, SetPSTATEFromPSR() will set PSTATE.IL.</line>
<line>    <a link="impl-shared.SetPSTATEFromPSR.1" file="shared_pseudocode.xml" hover="function: SetPSTATEFromPSR(bits(N) spsr)">SetPSTATEFromPSR</a>(spsr);                            // Can update privileged bits, even at EL0</line>
<line></line>
<line>    boolean branch_conditional = FALSE;</line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        if <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_RESTARTALIGNPC" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESTARTALIGNPC</a>) then new_pc&lt;0&gt; = '0';</line>
<line>        // AArch32 branch</line>
<line>        <a link="impl-shared.BranchTo.3" file="shared_pseudocode.xml" hover="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(new_pc&lt;31:0&gt;, <a link="BranchType_DBGEXIT" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DBGEXIT</a>, branch_conditional);</line>
<line>    else</line>
<line>        // If targeting AArch32 then PC[63:32,1:0] might be set to UNKNOWN.</line>
<line>        if illegal_psr_state &amp;&amp; spsr&lt;4&gt; == '1' then</line>
<line>            new_pc&lt;63:32&gt; = bits(32) UNKNOWN;</line>
<line>            new_pc&lt;1:0&gt; = bits(2) UNKNOWN;</line>
<line>        if <a link="impl-shared.HaveBRBExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveBRBExt()">HaveBRBExt</a>() then</line>
<line>            <a link="impl-aarch64.BRBEDebugStateExit.1" file="shared_pseudocode.xml" hover="function: BRBEDebugStateExit(bits(64) target_address)">BRBEDebugStateExit</a>(new_pc);</line>
<line>        // A type of branch that is never predicted</line>
<line>        <a link="impl-shared.BranchTo.3" file="shared_pseudocode.xml" hover="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(new_pc, <a link="BranchType_DBGEXIT" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DBGEXIT</a>, branch_conditional);</line>
<line></line>
<line>    (EDSCR.STATUS,EDPRSR.SDR) = ('000010','1');        // Atomically signal restarted</line>
<line>    <a link="impl-shared.UpdateEDSCRFields.0" file="shared_pseudocode.xml" hover="function: UpdateEDSCRFields()">UpdateEDSCRFields</a>();                               // Stop signalling PE state</line>
<line>    <a link="impl-shared.DisableITRAndResumeInstructionPrefetch.0" file="shared_pseudocode.xml" hover="function: DisableITRAndResumeInstructionPrefetch()">DisableITRAndResumeInstructionPrefetch</a>();</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/debug/halting/Halt" mylink="shared.debug.halting.Halt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Halt()</line>
<line>// ======</line>
<line></line>
<line link="impl-shared.Halt.1" hover="function: Halt(bits(6) reason)" conts="Halt"><anchor link="impl-shared.Halt.1" hover="function: Halt(bits(6) reason)">Halt</anchor>(bits(6) reason)</line>
<line>    boolean is_async = FALSE;</line>
<line>    <a link="impl-shared.Halt.2" file="shared_pseudocode.xml" hover="function: Halt(bits(6) reason, boolean is_async)">Halt</a>(reason, is_async);</line>
<line></line>
<line>// Halt()</line>
<line>// ======</line>
<line></line>
<line link="impl-shared.Halt.2" hover="function: Halt(bits(6) reason, boolean is_async)" conts="Halt"><anchor link="impl-shared.Halt.2" hover="function: Halt(bits(6) reason, boolean is_async)">Halt</anchor>(bits(6) reason, boolean is_async)</line>
<line></line>
<line>    if <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0 then</line>
<line>        <a link="impl-aarch64.FailTransaction.2" file="shared_pseudocode.xml" hover="function: FailTransaction(TMFailure cause, boolean retry)">FailTransaction</a>(<a link="TMFailure_DBG" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_DBG</a>, FALSE);</line>
<line></line>
<line>    <a link="impl-shared.CTI_SignalEvent.1" file="shared_pseudocode.xml" hover="function: CTI_SignalEvent(CrossTriggerIn id)">CTI_SignalEvent</a>(<a link="CrossTriggerIn_CrossHalt" file="shared_pseudocode.xml" hover="enumeration CrossTriggerIn  {CrossTriggerIn_CrossHalt,     CrossTriggerIn_PMUOverflow, CrossTriggerIn_RSVD2,         CrossTriggerIn_RSVD3, CrossTriggerIn_TraceExtOut0,  CrossTriggerIn_TraceExtOut1, CrossTriggerIn_TraceExtOut2,  CrossTriggerIn_TraceExtOut3}">CrossTriggerIn_CrossHalt</a>);  // Trigger other cores to halt</line>
<line></line>
<line>    bits(64) preferred_restart_address = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    bits(64) spsr = <a link="impl-shared.GetPSRFromPSTATE.2" file="shared_pseudocode.xml" hover="function: bits(N) GetPSRFromPSTATE(ExceptionalOccurrenceTargetState targetELState, integer N)">GetPSRFromPSTATE</a>(<a link="DebugState" file="shared_pseudocode.xml" hover="enumeration ExceptionalOccurrenceTargetState { AArch32_NonDebugState, AArch64_NonDebugState, DebugState }">DebugState</a>, 64);</line>
<line></line>
<line>    if (<a link="impl-shared.HaveBTIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveBTIExt()">HaveBTIExt</a>() &amp;&amp; !is_async &amp;&amp; !(reason IN {<a link="DebugHalt_Step_Normal" file="shared_pseudocode.xml" hover="constant bits(6) DebugHalt_Step_Normal = '011011'">DebugHalt_Step_Normal</a>, <a link="DebugHalt_Step_Exclusive" file="shared_pseudocode.xml" hover="constant bits(6) DebugHalt_Step_Exclusive = '011111'">DebugHalt_Step_Exclusive</a>,</line>
<line>        <a link="DebugHalt_Step_NoSyndrome" file="shared_pseudocode.xml" hover="constant bits(6) DebugHalt_Step_NoSyndrome = '111011'">DebugHalt_Step_NoSyndrome</a>, <a link="DebugHalt_Breakpoint" file="shared_pseudocode.xml" hover="constant bits(6) DebugHalt_Breakpoint = '000111'">DebugHalt_Breakpoint</a>, <a link="DebugHalt_HaltInstruction" file="shared_pseudocode.xml" hover="constant bits(6) DebugHalt_HaltInstruction = '101111'">DebugHalt_HaltInstruction</a>}) &amp;&amp;</line>
<line>        <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_ZEROBTYPE" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_ZEROBTYPE</a>)) then</line>
<line>        spsr&lt;11:10&gt; = '00';</line>
<line></line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        DLR = preferred_restart_address&lt;31:0&gt;;</line>
<line>        DSPSR = spsr&lt;31:0&gt;;</line>
<line>        if <a link="impl-shared.Havev8p9Debug.0" file="shared_pseudocode.xml" hover="function: boolean Havev8p9Debug()">Havev8p9Debug</a>() then</line>
<line>            DSPSR2 = spsr&lt;63:32&gt;;</line>
<line>    else</line>
<line>        DLR_EL0 = preferred_restart_address;</line>
<line>        DSPSR_EL0 = spsr;</line>
<line></line>
<line>    EDSCR.ITE = '1';</line>
<line>    EDSCR.ITO = '0';</line>
<line>    if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then</line>
<line>        EDSCR.SDD = if <a link="impl-shared.ExternalRootInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalRootInvasiveDebugEnabled()">ExternalRootInvasiveDebugEnabled</a>() then '0' else '1';</line>
<line>    elsif <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>        EDSCR.SDD = '0';                        // If entered in Secure state, allow debug</line>
<line>    elsif <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        EDSCR.SDD = if <a link="impl-shared.ExternalSecureInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalSecureInvasiveDebugEnabled()">ExternalSecureInvasiveDebugEnabled</a>() then '0' else '1';</line>
<line>    else</line>
<line>        EDSCR.SDD = '1';                        // Otherwise EDSCR.SDD is RES1</line>
<line>    EDSCR.MA = '0';</line>
<line></line>
<line>    // In Debug state:</line>
<line>    // * PSTATE.{SS,SSBS,D,A,I,F} are not observable and ignored so behave-as-if UNKNOWN.</line>
<line>    // * PSTATE.{N,Z,C,V,Q,GE,E,M,nRW,EL,SP,DIT} are also not observable, but since these</line>
<line>    //     are not changed on exception entry, this function also leaves them unchanged.</line>
<line>    // * PSTATE.{IT,T} are ignored.</line>
<line>    // * PSTATE.IL is ignored and behave-as-if 0.</line>
<line>    // * PSTATE.BTYPE is ignored and behave-as-if 0.</line>
<line>    // * PSTATE.TCO is set 1.</line>
<line>    // * PSTATE.{UAO,PAN} are observable and not changed on entry into Debug state.</line>
<line></line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        PSTATE.&lt;IT,SS,SSBS,A,I,F,T&gt; = bits(14) UNKNOWN;</line>
<line>    else</line>
<line>        PSTATE.&lt;SS,SSBS,D,A,I,F&gt;    = bits(6)  UNKNOWN;</line>
<line></line>
<line>        PSTATE.TCO = '1';</line>
<line>        PSTATE.BTYPE = '00';</line>
<line>    PSTATE.IL = '0';</line>
<line>    <a link="impl-shared.StopInstructionPrefetchAndEnableITR.0" file="shared_pseudocode.xml" hover="function: StopInstructionPrefetchAndEnableITR()">StopInstructionPrefetchAndEnableITR</a>();</line>
<line>    EDSCR.STATUS = reason;                      // Signal entered Debug state</line>
<line>    <a link="impl-shared.UpdateEDSCRFields.0" file="shared_pseudocode.xml" hover="function: UpdateEDSCRFields()">UpdateEDSCRFields</a>();                        // Update EDSCR PE state flags.</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/debug/halting/HaltOnBreakpointOrWatchpoint" mylink="shared.debug.halting.HaltOnBreakpointOrWatchpoint" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaltOnBreakpointOrWatchpoint()</line>
<line>// ==============================</line>
<line>// Returns TRUE if the Breakpoint and Watchpoint debug events should be considered for Debug</line>
<line>// state entry, FALSE if they should be considered for a debug exception.</line>
<line></line>
<line link="impl-shared.HaltOnBreakpointOrWatchpoint.0" hover="function: boolean HaltOnBreakpointOrWatchpoint()" conts="HaltOnBreakpointOrWatchpoint">boolean <anchor link="impl-shared.HaltOnBreakpointOrWatchpoint.0" hover="function: boolean HaltOnBreakpointOrWatchpoint()">HaltOnBreakpointOrWatchpoint</anchor>()</line>
<line>    return <a link="impl-shared.HaltingAllowed.0" file="shared_pseudocode.xml" hover="function: boolean HaltingAllowed()">HaltingAllowed</a>() &amp;&amp; EDSCR.HDE == '1' &amp;&amp; OSLSR_EL1.OSLK == '0';</line>
</pstext>
    </ps>
    <ps name="shared/debug/halting/Halted" mylink="shared.debug.halting.Halted" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Halted()</line>
<line>// ========</line>
<line></line>
<line link="impl-shared.Halted.0" hover="function: boolean Halted()" conts="Halted">boolean <anchor link="impl-shared.Halted.0" hover="function: boolean Halted()">Halted</anchor>()</line>
<line>    return !(EDSCR.STATUS IN {'000001', '000010'});                     // Halted</line>
</pstext>
    </ps>
    <ps name="shared/debug/halting/HaltingAllowed" mylink="shared.debug.halting.HaltingAllowed" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaltingAllowed()</line>
<line>// ================</line>
<line>// Returns TRUE if halting is currently allowed, FALSE if halting is prohibited.</line>
<line></line>
<line link="impl-shared.HaltingAllowed.0" hover="function: boolean HaltingAllowed()" conts="HaltingAllowed">boolean <anchor link="impl-shared.HaltingAllowed.0" hover="function: boolean HaltingAllowed()">HaltingAllowed</anchor>()</line>
<line>    if <a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() || <a link="impl-shared.DoubleLockStatus.0" file="shared_pseudocode.xml" hover="function: boolean DoubleLockStatus()">DoubleLockStatus</a>() then</line>
<line>        return FALSE;</line>
<line>    ss = <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>();</line>
<line>    case ss of</line>
<line>        when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> return <a link="impl-shared.ExternalInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalInvasiveDebugEnabled()">ExternalInvasiveDebugEnabled</a>();</line>
<line>        when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>    return <a link="impl-shared.ExternalSecureInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalSecureInvasiveDebugEnabled()">ExternalSecureInvasiveDebugEnabled</a>();</line>
<line>        when <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>      return <a link="impl-shared.ExternalRootInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalRootInvasiveDebugEnabled()">ExternalRootInvasiveDebugEnabled</a>();</line>
<line>        when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>     return <a link="impl-shared.ExternalRealmInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalRealmInvasiveDebugEnabled()">ExternalRealmInvasiveDebugEnabled</a>();</line>
</pstext>
    </ps>
    <ps name="shared/debug/halting/Restarting" mylink="shared.debug.halting.Restarting" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Restarting()</line>
<line>// ============</line>
<line></line>
<line link="impl-shared.Restarting.0" hover="function: boolean Restarting()" conts="Restarting">boolean <anchor link="impl-shared.Restarting.0" hover="function: boolean Restarting()">Restarting</anchor>()</line>
<line>    return EDSCR.STATUS == '000001';                                    // Restarting</line>
</pstext>
    </ps>
    <ps name="shared/debug/halting/StopInstructionPrefetchAndEnableITR" mylink="shared.debug.halting.StopInstructionPrefetchAndEnableITR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// StopInstructionPrefetchAndEnableITR()</line>
<line>// =====================================</line>
<line></line>
<line link="impl-shared.StopInstructionPrefetchAndEnableITR.0" hover="function: StopInstructionPrefetchAndEnableITR()" conts="StopInstructionPrefetchAndEnableITR"><anchor link="impl-shared.StopInstructionPrefetchAndEnableITR.0" hover="function: StopInstructionPrefetchAndEnableITR()">StopInstructionPrefetchAndEnableITR</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/debug/halting/UpdateEDSCRFields" mylink="shared.debug.halting.UpdateEDSCRFields" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// UpdateEDSCRFields()</line>
<line>// ===================</line>
<line>// Update EDSCR PE state fields</line>
<line></line>
<line link="impl-shared.UpdateEDSCRFields.0" hover="function: UpdateEDSCRFields()" conts="UpdateEDSCRFields"><anchor link="impl-shared.UpdateEDSCRFields.0" hover="function: UpdateEDSCRFields()">UpdateEDSCRFields</anchor>()</line>
<line></line>
<line>    if !<a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() then</line>
<line>        EDSCR.EL = '00';</line>
<line>        if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then</line>
<line>            EDSCR.&lt;NSE,NS&gt; = bits(2) UNKNOWN;</line>
<line>        else</line>
<line>            EDSCR.NS = bit UNKNOWN;</line>
<line></line>
<line>        EDSCR.RW = '1111';</line>
<line>    else</line>
<line>        EDSCR.EL = PSTATE.EL;</line>
<line>        ss = <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>();</line>
<line>        if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then</line>
<line>            case ss of</line>
<line>                when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>    EDSCR.&lt;NSE,NS&gt; = '00';</line>
<line>                when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> EDSCR.&lt;NSE,NS&gt; = '01';</line>
<line>                when <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>      EDSCR.&lt;NSE,NS&gt; = '10';</line>
<line>                when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>     EDSCR.&lt;NSE,NS&gt; = '11';</line>
<line>        else</line>
<line>            EDSCR.NS = if ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then '0' else '1';</line>
<line></line>
<line>        bits(4) RW;</line>
<line>        RW&lt;1&gt; = if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then '0' else '1';</line>
<line>        if PSTATE.EL != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>            RW&lt;0&gt; = RW&lt;1&gt;;</line>
<line>        else</line>
<line>            RW&lt;0&gt; = if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then '0' else '1';</line>
<line>        if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) || (<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.SCR_GEN.read.0" file="shared_pseudocode.xml" hover="accessor: SCRType SCR_GEN[]">SCR_GEN</a>[].NS == '0' &amp;&amp; !<a link="impl-shared.IsSecureEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsSecureEL2Enabled()">IsSecureEL2Enabled</a>()) then</line>
<line>            RW&lt;2&gt; = RW&lt;1&gt;;</line>
<line>        else</line>
<line>            RW&lt;2&gt; = if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then '0' else '1';</line>
<line>        if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>            RW&lt;3&gt; = RW&lt;2&gt;;</line>
<line>        else</line>
<line>            RW&lt;3&gt; = if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then '0' else '1';</line>
<line></line>
<line>        // The least-significant bits of EDSCR.RW are UNKNOWN if any higher EL is using AArch32.</line>
<line>        if RW&lt;3&gt; == '0' then RW&lt;2:0&gt; = bits(3) UNKNOWN;</line>
<line>        elsif RW&lt;2&gt; == '0' then RW&lt;1:0&gt; = bits(2) UNKNOWN;</line>
<line>        elsif RW&lt;1&gt; == '0' then RW&lt;0&gt; = bit UNKNOWN;</line>
<line>        EDSCR.RW = RW;</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/debug/haltingevents/CheckExceptionCatch" mylink="shared.debug.haltingevents.CheckExceptionCatch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckExceptionCatch()</line>
<line>// =====================</line>
<line>// Check whether an Exception Catch debug event is set on the current Exception level</line>
<line></line>
<line link="impl-shared.CheckExceptionCatch.1" hover="function: CheckExceptionCatch(boolean exception_entry)" conts="CheckExceptionCatch"><anchor link="impl-shared.CheckExceptionCatch.1" hover="function: CheckExceptionCatch(boolean exception_entry)">CheckExceptionCatch</anchor>(boolean exception_entry)</line>
<line>    // Called after an exception entry or exit, that is, such that the Security state</line>
<line>    // and PSTATE.EL are correct for the exception target. When FEAT_Debugv8p2</line>
<line>    // is not implemented, this function might also be called at any time.</line>
<line>    ss = <a link="impl-shared.SecurityStateAtEL.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)">SecurityStateAtEL</a>(PSTATE.EL);</line>
<line>    integer base;</line>
<line></line>
<line>    case ss of</line>
<line>        when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>    base = 0;</line>
<line>        when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> base = 4;</line>
<line>        when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>     base = 16;</line>
<line>        when <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>      base = 0;</line>
<line>    if <a link="impl-shared.HaltingAllowed.0" file="shared_pseudocode.xml" hover="function: boolean HaltingAllowed()">HaltingAllowed</a>() then</line>
<line>        boolean halt;</line>
<line>        if <a link="impl-shared.HaveExtendedECDebugEvents.0" file="shared_pseudocode.xml" hover="function: boolean HaveExtendedECDebugEvents()">HaveExtendedECDebugEvents</a>() then</line>
<line>            exception_exit = !exception_entry;</line>
<line>            increment = if ss == <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a> then 4 else 8;</line>
<line>            ctrl = EDECCR&lt;<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL) + base + increment&gt;:EDECCR&lt;<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL) + base&gt;;</line>
<line>            case ctrl of</line>
<line>                when '00'  halt = FALSE;</line>
<line>                when '01'  halt = TRUE;</line>
<line>                when '10'  halt = (exception_exit == TRUE);</line>
<line>                when '11'  halt = (exception_entry == TRUE);</line>
<line>        else</line>
<line>            halt = (EDECCR&lt;<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL) + base&gt; == '1');</line>
<line></line>
<line>        if halt then</line>
<line>            if <a link="impl-shared.Havev8p8Debug.0" file="shared_pseudocode.xml" hover="function: boolean Havev8p8Debug()">Havev8p8Debug</a>() &amp;&amp; exception_entry then</line>
<line>                EDESR.EC = '1';</line>
<line>            else</line>
<line>                <a link="impl-shared.Halt.1" file="shared_pseudocode.xml" hover="function: Halt(bits(6) reason)">Halt</a>(<a link="DebugHalt_ExceptionCatch" file="shared_pseudocode.xml" hover="constant bits(6) DebugHalt_ExceptionCatch = '110111'">DebugHalt_ExceptionCatch</a>);</line>
</pstext>
    </ps>
    <ps name="shared/debug/haltingevents/CheckHaltingStep" mylink="shared.debug.haltingevents.CheckHaltingStep" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckHaltingStep()</line>
<line>// ==================</line>
<line>// Check whether EDESR.SS has been set by Halting Step</line>
<line></line>
<line link="impl-shared.CheckHaltingStep.1" hover="function: CheckHaltingStep(boolean is_async)" conts="CheckHaltingStep"><anchor link="impl-shared.CheckHaltingStep.1" hover="function: CheckHaltingStep(boolean is_async)">CheckHaltingStep</anchor>(boolean is_async)</line>
<line>    if <a link="impl-shared.HaltingAllowed.0" file="shared_pseudocode.xml" hover="function: boolean HaltingAllowed()">HaltingAllowed</a>() &amp;&amp; EDESR.SS == '1' then</line>
<line>        // The STATUS code depends on how we arrived at the state where EDESR.SS == 1.</line>
<line>        if <a link="impl-shared.HaltingStep_DidNotStep.0" file="shared_pseudocode.xml" hover="function: boolean HaltingStep_DidNotStep()">HaltingStep_DidNotStep</a>() then</line>
<line>            <a link="impl-shared.Halt.2" file="shared_pseudocode.xml" hover="function: Halt(bits(6) reason, boolean is_async)">Halt</a>(<a link="DebugHalt_Step_NoSyndrome" file="shared_pseudocode.xml" hover="constant bits(6) DebugHalt_Step_NoSyndrome = '111011'">DebugHalt_Step_NoSyndrome</a>, is_async);</line>
<line>        elsif <a link="impl-shared.HaltingStep_SteppedEX.0" file="shared_pseudocode.xml" hover="function: boolean HaltingStep_SteppedEX()">HaltingStep_SteppedEX</a>() then</line>
<line>            <a link="impl-shared.Halt.2" file="shared_pseudocode.xml" hover="function: Halt(bits(6) reason, boolean is_async)">Halt</a>(<a link="DebugHalt_Step_Exclusive" file="shared_pseudocode.xml" hover="constant bits(6) DebugHalt_Step_Exclusive = '011111'">DebugHalt_Step_Exclusive</a>, is_async);</line>
<line>        else</line>
<line>            <a link="impl-shared.Halt.2" file="shared_pseudocode.xml" hover="function: Halt(bits(6) reason, boolean is_async)">Halt</a>(<a link="DebugHalt_Step_Normal" file="shared_pseudocode.xml" hover="constant bits(6) DebugHalt_Step_Normal = '011011'">DebugHalt_Step_Normal</a>, is_async);</line>
</pstext>
    </ps>
    <ps name="shared/debug/haltingevents/CheckOSUnlockCatch" mylink="shared.debug.haltingevents.CheckOSUnlockCatch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckOSUnlockCatch()</line>
<line>// ====================</line>
<line>// Called on unlocking the OS Lock to pend an OS Unlock Catch debug event</line>
<line></line>
<line link="impl-shared.CheckOSUnlockCatch.0" hover="function: CheckOSUnlockCatch()" conts="CheckOSUnlockCatch"><anchor link="impl-shared.CheckOSUnlockCatch.0" hover="function: CheckOSUnlockCatch()">CheckOSUnlockCatch</anchor>()</line>
<line>    if ((<a link="impl-shared.HaveDoPD.0" file="shared_pseudocode.xml" hover="function: boolean HaveDoPD()">HaveDoPD</a>() &amp;&amp; CTIDEVCTL.OSUCE == '1') ||</line>
<line>        (!<a link="impl-shared.HaveDoPD.0" file="shared_pseudocode.xml" hover="function: boolean HaveDoPD()">HaveDoPD</a>() &amp;&amp; EDECR.OSUCE == '1')) then</line>
<line>        if !<a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() then EDESR.OSUC = '1';</line>
</pstext>
    </ps>
    <ps name="shared/debug/haltingevents/CheckPendingExceptionCatch" mylink="shared.debug.haltingevents.CheckPendingExceptionCatch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckPendingExceptionCatch()</line>
<line>// ============================</line>
<line>// Check whether EDESR.EC has been set by an Exception Catch debug event.</line>
<line></line>
<line link="impl-shared.CheckPendingExceptionCatch.1" hover="function: CheckPendingExceptionCatch(boolean is_async)" conts="CheckPendingExceptionCatch"><anchor link="impl-shared.CheckPendingExceptionCatch.1" hover="function: CheckPendingExceptionCatch(boolean is_async)">CheckPendingExceptionCatch</anchor>(boolean is_async)</line>
<line>    if <a link="impl-shared.Havev8p8Debug.0" file="shared_pseudocode.xml" hover="function: boolean Havev8p8Debug()">Havev8p8Debug</a>() &amp;&amp; <a link="impl-shared.HaltingAllowed.0" file="shared_pseudocode.xml" hover="function: boolean HaltingAllowed()">HaltingAllowed</a>() &amp;&amp; EDESR.EC == '1' then</line>
<line>        <a link="impl-shared.Halt.2" file="shared_pseudocode.xml" hover="function: Halt(bits(6) reason, boolean is_async)">Halt</a>(<a link="DebugHalt_ExceptionCatch" file="shared_pseudocode.xml" hover="constant bits(6) DebugHalt_ExceptionCatch = '110111'">DebugHalt_ExceptionCatch</a>, is_async);</line>
</pstext>
    </ps>
    <ps name="shared/debug/haltingevents/CheckPendingOSUnlockCatch" mylink="shared.debug.haltingevents.CheckPendingOSUnlockCatch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckPendingOSUnlockCatch()</line>
<line>// ===========================</line>
<line>// Check whether EDESR.OSUC has been set by an OS Unlock Catch debug event</line>
<line></line>
<line link="impl-shared.CheckPendingOSUnlockCatch.0" hover="function: CheckPendingOSUnlockCatch()" conts="CheckPendingOSUnlockCatch"><anchor link="impl-shared.CheckPendingOSUnlockCatch.0" hover="function: CheckPendingOSUnlockCatch()">CheckPendingOSUnlockCatch</anchor>()</line>
<line>    if <a link="impl-shared.HaltingAllowed.0" file="shared_pseudocode.xml" hover="function: boolean HaltingAllowed()">HaltingAllowed</a>() &amp;&amp; EDESR.OSUC == '1' then</line>
<line>        boolean is_async = TRUE;</line>
<line>        <a link="impl-shared.Halt.2" file="shared_pseudocode.xml" hover="function: Halt(bits(6) reason, boolean is_async)">Halt</a>(<a link="DebugHalt_OSUnlockCatch" file="shared_pseudocode.xml" hover="constant bits(6) DebugHalt_OSUnlockCatch = '100011'">DebugHalt_OSUnlockCatch</a>, is_async);</line>
</pstext>
    </ps>
    <ps name="shared/debug/haltingevents/CheckPendingResetCatch" mylink="shared.debug.haltingevents.CheckPendingResetCatch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckPendingResetCatch()</line>
<line>// ========================</line>
<line>// Check whether EDESR.RC has been set by a Reset Catch debug event</line>
<line></line>
<line link="impl-shared.CheckPendingResetCatch.0" hover="function: CheckPendingResetCatch()" conts="CheckPendingResetCatch"><anchor link="impl-shared.CheckPendingResetCatch.0" hover="function: CheckPendingResetCatch()">CheckPendingResetCatch</anchor>()</line>
<line>    if <a link="impl-shared.HaltingAllowed.0" file="shared_pseudocode.xml" hover="function: boolean HaltingAllowed()">HaltingAllowed</a>() &amp;&amp; EDESR.RC == '1' then</line>
<line>        boolean is_async = TRUE;</line>
<line>        <a link="impl-shared.Halt.2" file="shared_pseudocode.xml" hover="function: Halt(bits(6) reason, boolean is_async)">Halt</a>(<a link="DebugHalt_ResetCatch" file="shared_pseudocode.xml" hover="constant bits(6) DebugHalt_ResetCatch = '100111'">DebugHalt_ResetCatch</a>, is_async);</line>
</pstext>
    </ps>
    <ps name="shared/debug/haltingevents/CheckResetCatch" mylink="shared.debug.haltingevents.CheckResetCatch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckResetCatch()</line>
<line>// =================</line>
<line>// Called after reset</line>
<line></line>
<line link="impl-shared.CheckResetCatch.0" hover="function: CheckResetCatch()" conts="CheckResetCatch"><anchor link="impl-shared.CheckResetCatch.0" hover="function: CheckResetCatch()">CheckResetCatch</anchor>()</line>
<line>    if (<a link="impl-shared.HaveDoPD.0" file="shared_pseudocode.xml" hover="function: boolean HaveDoPD()">HaveDoPD</a>() &amp;&amp; CTIDEVCTL.RCE == '1') || (!<a link="impl-shared.HaveDoPD.0" file="shared_pseudocode.xml" hover="function: boolean HaveDoPD()">HaveDoPD</a>() &amp;&amp; EDECR.RCE == '1') then</line>
<line>        EDESR.RC = '1';</line>
<line>        // If halting is allowed then halt immediately</line>
<line>        if <a link="impl-shared.HaltingAllowed.0" file="shared_pseudocode.xml" hover="function: boolean HaltingAllowed()">HaltingAllowed</a>() then <a link="impl-shared.Halt.1" file="shared_pseudocode.xml" hover="function: Halt(bits(6) reason)">Halt</a>(<a link="DebugHalt_ResetCatch" file="shared_pseudocode.xml" hover="constant bits(6) DebugHalt_ResetCatch = '100111'">DebugHalt_ResetCatch</a>);</line>
</pstext>
    </ps>
    <ps name="shared/debug/haltingevents/CheckSoftwareAccessToDebugRegisters" mylink="shared.debug.haltingevents.CheckSoftwareAccessToDebugRegisters" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckSoftwareAccessToDebugRegisters()</line>
<line>// =====================================</line>
<line>// Check for access to Breakpoint and Watchpoint registers.</line>
<line></line>
<line link="impl-shared.CheckSoftwareAccessToDebugRegisters.0" hover="function: CheckSoftwareAccessToDebugRegisters()" conts="CheckSoftwareAccessToDebugRegisters"><anchor link="impl-shared.CheckSoftwareAccessToDebugRegisters.0" hover="function: CheckSoftwareAccessToDebugRegisters()">CheckSoftwareAccessToDebugRegisters</anchor>()</line>
<line>    os_lock = (if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then DBGOSLSR.OSLK else OSLSR_EL1.OSLK);</line>
<line>    if <a link="impl-shared.HaltingAllowed.0" file="shared_pseudocode.xml" hover="function: boolean HaltingAllowed()">HaltingAllowed</a>() &amp;&amp; EDSCR.TDA == '1' &amp;&amp; os_lock == '0' then</line>
<line>        <a link="impl-shared.Halt.1" file="shared_pseudocode.xml" hover="function: Halt(bits(6) reason)">Halt</a>(<a link="DebugHalt_SoftwareAccess" file="shared_pseudocode.xml" hover="constant bits(6) DebugHalt_SoftwareAccess = '110011'">DebugHalt_SoftwareAccess</a>);</line>
</pstext>
    </ps>
    <ps name="shared/debug/haltingevents/CheckTRBEHalt" mylink="shared.debug.haltingevents.CheckTRBEHalt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckTRBEHalt()</line>
<line>// ===============</line>
<line></line>
<line link="impl-shared.CheckTRBEHalt.0" hover="function: CheckTRBEHalt()" conts="CheckTRBEHalt"><anchor link="impl-shared.CheckTRBEHalt.0" hover="function: CheckTRBEHalt()">CheckTRBEHalt</anchor>()</line>
<line>    if !<a link="impl-shared.Havev8p9Debug.0" file="shared_pseudocode.xml" hover="function: boolean Havev8p9Debug()">Havev8p9Debug</a>() || !<a link="impl-shared.HaveFeatTRBEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatTRBEExt()">HaveFeatTRBEExt</a>() then</line>
<line>        return;</line>
<line></line>
<line>    if (<a link="impl-shared.HaltingAllowed.0" file="shared_pseudocode.xml" hover="function: boolean HaltingAllowed()">HaltingAllowed</a>() &amp;&amp; <a link="impl-shared.TraceBufferEnabled.0" file="shared_pseudocode.xml" hover="function: boolean TraceBufferEnabled()">TraceBufferEnabled</a>() &amp;&amp;</line>
<line>        TRBSR_EL1.IRQ == '1' &amp;&amp; EDECR.TRBE == '1') then</line>
<line>        <a link="impl-shared.Halt.1" file="shared_pseudocode.xml" hover="function: Halt(bits(6) reason)">Halt</a>(<a link="DebugHalt_EDBGRQ" file="shared_pseudocode.xml" hover="constant bits(6) DebugHalt_EDBGRQ = '010011'">DebugHalt_EDBGRQ</a>);</line>
</pstext>
    </ps>
    <ps name="shared/debug/haltingevents/ExternalDebugRequest" mylink="shared.debug.haltingevents.ExternalDebugRequest" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExternalDebugRequest()</line>
<line>// ======================</line>
<line></line>
<line link="impl-shared.ExternalDebugRequest.0" hover="function: ExternalDebugRequest()" conts="ExternalDebugRequest"><anchor link="impl-shared.ExternalDebugRequest.0" hover="function: ExternalDebugRequest()">ExternalDebugRequest</anchor>()</line>
<line>    if <a link="impl-shared.HaltingAllowed.0" file="shared_pseudocode.xml" hover="function: boolean HaltingAllowed()">HaltingAllowed</a>() then</line>
<line>        boolean is_async = TRUE;</line>
<line>        <a link="impl-shared.Halt.2" file="shared_pseudocode.xml" hover="function: Halt(bits(6) reason, boolean is_async)">Halt</a>(<a link="DebugHalt_EDBGRQ" file="shared_pseudocode.xml" hover="constant bits(6) DebugHalt_EDBGRQ = '010011'">DebugHalt_EDBGRQ</a>, is_async);</line>
<line>    // Otherwise the CTI continues to assert the debug request until it is taken.</line>
</pstext>
    </ps>
    <ps name="shared/debug/haltingevents/HaltingStep_DidNotStep" mylink="shared.debug.haltingevents.HaltingStep_DidNotStep" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaltingStep_DidNotStep()</line>
<line>// ========================</line>
<line>// Returns TRUE if the previously executed instruction was executed in the inactive state, that is,</line>
<line>// if it was not itself stepped.</line>
<line></line>
<line link="impl-shared.HaltingStep_DidNotStep.0" hover="function: boolean HaltingStep_DidNotStep()" conts="HaltingStep_DidNotStep">boolean <anchor link="impl-shared.HaltingStep_DidNotStep.0" hover="function: boolean HaltingStep_DidNotStep()">HaltingStep_DidNotStep</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/debug/haltingevents/HaltingStep_SteppedEX" mylink="shared.debug.haltingevents.HaltingStep_SteppedEX" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaltingStep_SteppedEX()</line>
<line>// =======================</line>
<line>// Returns TRUE if the previously executed instruction was a Load-Exclusive class instruction</line>
<line>// executed in the active-not-pending state.</line>
<line></line>
<line link="impl-shared.HaltingStep_SteppedEX.0" hover="function: boolean HaltingStep_SteppedEX()" conts="HaltingStep_SteppedEX">boolean <anchor link="impl-shared.HaltingStep_SteppedEX.0" hover="function: boolean HaltingStep_SteppedEX()">HaltingStep_SteppedEX</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/debug/haltingevents/RunHaltingStep" mylink="shared.debug.haltingevents.RunHaltingStep" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// RunHaltingStep()</line>
<line>// ================</line>
<line></line>
<line link="impl-shared.RunHaltingStep.4" hover="function: RunHaltingStep(boolean exception_generated, bits(2) exception_target, boolean syscall, boolean reset)" conts="RunHaltingStep"><anchor link="impl-shared.RunHaltingStep.4" hover="function: RunHaltingStep(boolean exception_generated, bits(2) exception_target, boolean syscall, boolean reset)">RunHaltingStep</anchor>(boolean exception_generated, bits(2) exception_target, boolean syscall,</line>
<line>               boolean reset)</line>
<line>    // "exception_generated" is TRUE if the previous instruction generated a synchronous exception</line>
<line>    // or was cancelled by an asynchronous exception.</line>
<line>    //</line>
<line>    // if "exception_generated" is TRUE then "exception_target" is the target of the exception, and</line>
<line>    // "syscall" is TRUE if the exception is a synchronous exception where the preferred return</line>
<line>    // address is the instruction following that which generated the exception.</line>
<line>    //</line>
<line>    // "reset" is TRUE if exiting reset state into the highest EL.</line>
<line></line>
<line>    if reset then assert !<a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>();             // Cannot come out of reset halted</line>
<line>    active = EDECR.SS == '1' &amp;&amp; !<a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>();</line>
<line></line>
<line>    if active &amp;&amp; reset then                     // Coming out of reset with EDECR.SS set</line>
<line>        EDESR.SS = '1';</line>
<line>    elsif active &amp;&amp; <a link="impl-shared.HaltingAllowed.0" file="shared_pseudocode.xml" hover="function: boolean HaltingAllowed()">HaltingAllowed</a>() then</line>
<line>        boolean advance;</line>
<line>        if exception_generated &amp;&amp; exception_target == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then</line>
<line>            advance = syscall || <a link="impl-shared.ExternalSecureInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalSecureInvasiveDebugEnabled()">ExternalSecureInvasiveDebugEnabled</a>();</line>
<line>        else</line>
<line>            advance = TRUE;</line>
<line>        if advance then EDESR.SS = '1';</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/debug/interrupts/ExternalDebugInterruptsDisabled" mylink="shared.debug.interrupts.ExternalDebugInterruptsDisabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExternalDebugInterruptsDisabled()</line>
<line>// =================================</line>
<line>// Determine whether EDSCR disables interrupts routed to 'target'.</line>
<line></line>
<line link="impl-shared.ExternalDebugInterruptsDisabled.1" hover="function: boolean ExternalDebugInterruptsDisabled(bits(2) target)" conts="ExternalDebugInterruptsDisabled">boolean <anchor link="impl-shared.ExternalDebugInterruptsDisabled.1" hover="function: boolean ExternalDebugInterruptsDisabled(bits(2) target)">ExternalDebugInterruptsDisabled</anchor>(bits(2) target)</line>
<line>    boolean int_dis;</line>
<line>    <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss = <a link="impl-shared.SecurityStateAtEL.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)">SecurityStateAtEL</a>(target);</line>
<line>    if <a link="impl-shared.Havev8p4Debug.0" file="shared_pseudocode.xml" hover="function: boolean Havev8p4Debug()">Havev8p4Debug</a>() then</line>
<line>        if EDSCR.INTdis[0] == '1' then</line>
<line>            case ss of</line>
<line>                when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> int_dis = <a link="impl-shared.ExternalInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalInvasiveDebugEnabled()">ExternalInvasiveDebugEnabled</a>();</line>
<line>                when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>    int_dis = <a link="impl-shared.ExternalSecureInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalSecureInvasiveDebugEnabled()">ExternalSecureInvasiveDebugEnabled</a>();</line>
<line>                when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>     int_dis = <a link="impl-shared.ExternalRealmInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalRealmInvasiveDebugEnabled()">ExternalRealmInvasiveDebugEnabled</a>();</line>
<line>                when <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>      int_dis = <a link="impl-shared.ExternalRootInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalRootInvasiveDebugEnabled()">ExternalRootInvasiveDebugEnabled</a>();</line>
<line>        else</line>
<line>            int_dis = FALSE;</line>
<line>    else</line>
<line>        case target of</line>
<line>            when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>                int_dis = (EDSCR.INTdis == '11' &amp;&amp; <a link="impl-shared.ExternalSecureInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalSecureInvasiveDebugEnabled()">ExternalSecureInvasiveDebugEnabled</a>());</line>
<line>            when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>                int_dis = (EDSCR.INTdis IN {'1x'} &amp;&amp; <a link="impl-shared.ExternalInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalInvasiveDebugEnabled()">ExternalInvasiveDebugEnabled</a>());</line>
<line>            when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>                if ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>                    int_dis = (EDSCR.INTdis IN {'1x'} &amp;&amp; <a link="impl-shared.ExternalSecureInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalSecureInvasiveDebugEnabled()">ExternalSecureInvasiveDebugEnabled</a>());</line>
<line>                else</line>
<line>                    int_dis = (EDSCR.INTdis != '00' &amp;&amp; <a link="impl-shared.ExternalInvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalInvasiveDebugEnabled()">ExternalInvasiveDebugEnabled</a>());</line>
<line>    return int_dis;</line>
</pstext>
    </ps>
    <ps name="shared/debug/pmu" mylink="shared.debug.pmu" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>array integer PMUEventAccumulator[0..30];  // Accumulates PMU events for a cycle</line>
<line></line>
<line>array boolean PMULastThresholdValue[0..30];// A record of the threshold result for each</line>
</pstext>
    </ps>
    <ps name="shared/debug/pmu/CYCLE_COUNTER_ID" mylink="shared.debug.pmu.CYCLE_COUNTER_ID" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="CYCLE_COUNTER_ID" hover="constant integer CYCLE_COUNTER_ID = 31" conts="CYCLE_COUNTER_ID">constant integer <anchor link="CYCLE_COUNTER_ID" hover="constant integer CYCLE_COUNTER_ID = 31">CYCLE_COUNTER_ID</anchor> = 31;</line>
</pstext>
    </ps>
    <ps name="shared/debug/pmu/CheckForPMUOverflow" mylink="shared.debug.pmu.CheckForPMUOverflow" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckForPMUOverflow()</line>
<line>// =====================</line>
<line>// Signal Performance Monitors overflow IRQ and CTI overflow events.</line>
<line>// Called before each instruction is executed.</line>
<line></line>
<line link="impl-shared.CheckForPMUOverflow.0" hover="function: CheckForPMUOverflow()" conts="CheckForPMUOverflow"><anchor link="impl-shared.CheckForPMUOverflow.0" hover="function: CheckForPMUOverflow()">CheckForPMUOverflow</anchor>()</line>
<line>    boolean check_cnten  = FALSE;</line>
<line>    boolean check_e      = TRUE;</line>
<line>    boolean check_inten  = TRUE;</line>
<line>    boolean include_lo   = TRUE;</line>
<line>    boolean include_hi   = TRUE;</line>
<line>    boolean exclude_cyc  = FALSE;</line>
<line>    boolean exclude_sync = FALSE;</line>
<line></line>
<line>    boolean pmuirq = <a link="impl-shared.PMUOverflowCondition.7" file="shared_pseudocode.xml" hover="function: boolean PMUOverflowCondition(boolean check_e, boolean check_cnten, boolean check_inten, boolean include_hi, boolean include_lo, boolean exclude_cyc, boolean exclude_sync)">PMUOverflowCondition</a>(check_e, check_cnten, check_inten,</line>
<line>                                          include_hi, include_lo,</line>
<line>                                          exclude_cyc, exclude_sync);</line>
<line></line>
<line>    SetInterruptRequestLevel(<a link="InterruptID_PMUIRQ" file="shared_pseudocode.xml" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_PMUIRQ</a>,  if pmuirq then HIGH else LOW);</line>
<line>    CTI_SetEventLevel(<a link="CrossTriggerIn_PMUOverflow" file="shared_pseudocode.xml" hover="enumeration CrossTriggerIn  {CrossTriggerIn_CrossHalt,     CrossTriggerIn_PMUOverflow, CrossTriggerIn_RSVD2,         CrossTriggerIn_RSVD3, CrossTriggerIn_TraceExtOut0,  CrossTriggerIn_TraceExtOut1, CrossTriggerIn_TraceExtOut2,  CrossTriggerIn_TraceExtOut3}">CrossTriggerIn_PMUOverflow</a>, if pmuirq then HIGH else LOW);</line>
<line></line>
<line>    // The request remains set until the condition is cleared.</line>
<line>    // For example, an interrupt handler or cross-triggered event handler clears</line>
<line>    // the overflow status flag by writing to PMOVSCLR_EL0.</line>
<line></line>
<line>    if <a link="impl-shared.HavePMUv3p9.0" file="shared_pseudocode.xml" hover="function: boolean HavePMUv3p9()">HavePMUv3p9</a>() &amp;&amp; <a link="impl-shared.Havev8p9Debug.0" file="shared_pseudocode.xml" hover="function: boolean Havev8p9Debug()">Havev8p9Debug</a>() then</line>
<line>        if pmuirq &amp;&amp; <a link="impl-shared.HaltingAllowed.0" file="shared_pseudocode.xml" hover="function: boolean HaltingAllowed()">HaltingAllowed</a>() &amp;&amp; EDECR.PME == '1' then</line>
<line>            <a link="impl-shared.Halt.1" file="shared_pseudocode.xml" hover="function: Halt(bits(6) reason)">Halt</a>(<a link="DebugHalt_EDBGRQ" file="shared_pseudocode.xml" hover="constant bits(6) DebugHalt_EDBGRQ = '010011'">DebugHalt_EDBGRQ</a>);</line>
<line></line>
<line>    if <a link="impl-aarch64.ShouldBRBEFreeze.0" file="shared_pseudocode.xml" hover="function: boolean ShouldBRBEFreeze()">ShouldBRBEFreeze</a>() then</line>
<line>        <a link="impl-aarch64.BRBEFreeze.0" file="shared_pseudocode.xml" hover="function: BRBEFreeze()">BRBEFreeze</a>();</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/debug/pmu/CountPMUEvents" mylink="shared.debug.pmu.CountPMUEvents" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CountPMUEvents()</line>
<line>// ================</line>
<line>// Return TRUE if counter "idx" should count its event.</line>
<line>// For the cycle counter, idx == CYCLE_COUNTER_ID (32).</line>
<line>// For the instruction counter, idx == INSTRUCTION_COUNTER_ID (33).</line>
<line></line>
<line link="impl-shared.CountPMUEvents.1" hover="function: boolean CountPMUEvents(integer idx)" conts="CountPMUEvents">boolean <anchor link="impl-shared.CountPMUEvents.1" hover="function: boolean CountPMUEvents(integer idx)">CountPMUEvents</anchor>(integer idx)</line>
<line>    constant integer num_counters = <a link="impl-shared.GetNumEventCounters.0" file="shared_pseudocode.xml" hover="function: integer GetNumEventCounters()">GetNumEventCounters</a>();</line>
<line>    assert (idx == <a link="CYCLE_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer CYCLE_COUNTER_ID = 31">CYCLE_COUNTER_ID</a> || idx &lt; num_counters ||</line>
<line>            (idx == <a link="INSTRUCTION_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer INSTRUCTION_COUNTER_ID = 32">INSTRUCTION_COUNTER_ID</a> &amp;&amp; <a link="impl-shared.HavePMUv3ICNTR.0" file="shared_pseudocode.xml" hover="function: boolean HavePMUv3ICNTR()">HavePMUv3ICNTR</a>()));</line>
<line></line>
<line>    boolean debug;</line>
<line>    boolean enabled;</line>
<line>    boolean prohibited;</line>
<line>    boolean filtered;</line>
<line>    boolean frozen;</line>
<line>    boolean resvd_for_el2;</line>
<line>    bit E;</line>
<line>    bit spme;</line>
<line>    bits(32) ovflws;</line>
<line></line>
<line>    // Event counting is disabled in Debug state</line>
<line>    debug = <a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>();</line>
<line></line>
<line>    // Software can reserve some counters for EL2</line>
<line>    resvd_for_el2 = <a link="impl-shared.PMUCounterIsHyp.1" file="shared_pseudocode.xml" hover="function: boolean PMUCounterIsHyp(integer n)">PMUCounterIsHyp</a>(idx);</line>
<line>    ss = <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>();</line>
<line></line>
<line>    // Main enable controls</line>
<line>    case idx of</line>
<line>        when <a link="INSTRUCTION_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer INSTRUCTION_COUNTER_ID = 32">INSTRUCTION_COUNTER_ID</a></line>
<line>            assert <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>();</line>
<line>            enabled = PMCR_EL0.E == '1' &amp;&amp; PMCNTENSET_EL0.F0 == '1';</line>
<line>        when <a link="CYCLE_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer CYCLE_COUNTER_ID = 31">CYCLE_COUNTER_ID</a></line>
<line>            if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then</line>
<line>                enabled = PMCR_EL0.E == '1' &amp;&amp; PMCNTENSET_EL0.C == '1';</line>
<line>            else</line>
<line>                enabled = PMCR.E == '1' &amp;&amp; PMCNTENSET.C == '1';</line>
<line>        otherwise</line>
<line>            if resvd_for_el2 then</line>
<line>                E = if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then MDCR_EL2.HPME else HDCR.HPME;</line>
<line>            else</line>
<line>                E = if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then PMCR_EL0.E else PMCR.E;</line>
<line></line>
<line>            if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then</line>
<line>                enabled = E == '1' &amp;&amp; PMCNTENSET_EL0&lt;idx&gt; == '1';</line>
<line>            else</line>
<line>                enabled = E == '1' &amp;&amp; PMCNTENSET&lt;idx&gt; == '1';</line>
<line></line>
<line>    // Event counting is allowed unless it is prohibited by any rule below</line>
<line>    prohibited = FALSE;</line>
<line></line>
<line>    // Event counting in Secure state is prohibited if all of:</line>
<line>    // * EL3 is implemented</line>
<line>    // * One of the following is true:</line>
<line>    //   - EL3 is using AArch64, MDCR_EL3.SPME == 0, and either:</line>
<line>    //     - FEAT_PMUv3p7 is not implemented</line>
<line>    //     - MDCR_EL3.MPMX == 0</line>
<line>    //   - EL3 is using AArch32 and SDCR.SPME == 0</line>
<line>    // * Executing at EL0 using AArch32 and one of the following is true:</line>
<line>    //     - EL3 is using AArch32 and SDER.SUNIDEN == 0</line>
<line>    //     - EL3 is using AArch64, EL1 is using AArch32, and SDER32_EL3.SUNIDEN == 0</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>        if !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>            prohibited = MDCR_EL3.SPME == '0' &amp;&amp; <a link="impl-shared.HavePMUv3p7.0" file="shared_pseudocode.xml" hover="function: boolean HavePMUv3p7()">HavePMUv3p7</a>() &amp;&amp; MDCR_EL3.MPMX == '0';</line>
<line>        else</line>
<line>            prohibited = SDCR.SPME == '0';</line>
<line></line>
<line>        if prohibited &amp;&amp; PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>            if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>                prohibited = SDER.SUNIDEN == '0';</line>
<line>            elsif <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>                prohibited = SDER32_EL3.SUNIDEN == '0';</line>
<line></line>
<line>    // Event counting at EL3 is prohibited if all of:</line>
<line>    // * FEAT_PMUv3p7 is implemented</line>
<line>    // * EL3 is using AArch64</line>
<line>    // * One of the following is true:</line>
<line>    //   - MDCR_EL3.SPME == 0</line>
<line>    //   - PMNx is not reserved for EL2</line>
<line>    // * MDCR_EL3.MPMX == 1</line>
<line>    if !prohibited &amp;&amp; <a link="impl-shared.HavePMUv3p7.0" file="shared_pseudocode.xml" hover="function: boolean HavePMUv3p7()">HavePMUv3p7</a>() &amp;&amp; PSTATE.EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> &amp;&amp; <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then</line>
<line>        prohibited = MDCR_EL3.MPMX == '1' &amp;&amp; (MDCR_EL3.SPME == '0' || !resvd_for_el2);</line>
<line></line>
<line>    // Event counting at EL2 is prohibited if all of:</line>
<line>    // * The HPMD Extension is implemented</line>
<line>    // * PMNx is not reserved for EL2</line>
<line>    // * EL2 is using AArch64 and MDCR_EL2.HPMD == 1 or EL2 is using AArch32 and HDCR.HPMD == 1</line>
<line>    if !prohibited &amp;&amp; PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> &amp;&amp; <a link="impl-shared.HaveHPMDExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveHPMDExt()">HaveHPMDExt</a>() &amp;&amp; !resvd_for_el2 then</line>
<line>        hpmd = if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then MDCR_EL2.HPMD else HDCR.HPMD;</line>
<line>        prohibited = hpmd == '1';</line>
<line></line>
<line>    // The IMPLEMENTATION DEFINED authentication interface might override software</line>
<line>    if prohibited &amp;&amp; !<a link="impl-shared.HaveNoSecurePMUDisableOverride.0" file="shared_pseudocode.xml" hover="function: boolean HaveNoSecurePMUDisableOverride()">HaveNoSecurePMUDisableOverride</a>() then</line>
<line>        prohibited = !<a link="impl-shared.ExternalSecureNoninvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalSecureNoninvasiveDebugEnabled()">ExternalSecureNoninvasiveDebugEnabled</a>();</line>
<line></line>
<line>    // Event counting might be frozen</line>
<line>    frozen = FALSE;</line>
<line></line>
<line>    // If FEAT_PMUv3p7 is implemented, event counting can be frozen</line>
<line>    if <a link="impl-shared.HavePMUv3p7.0" file="shared_pseudocode.xml" hover="function: boolean HavePMUv3p7()">HavePMUv3p7</a>() then</line>
<line>        bit FZ;</line>
<line>        if resvd_for_el2 then</line>
<line>            FZ = if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then MDCR_EL2.HPMFZO else HDCR.HPMFZO;</line>
<line>        else</line>
<line>            FZ = if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then PMCR_EL0.FZO else PMCR.FZO;</line>
<line></line>
<line>        frozen = (FZ == '1') &amp;&amp; <a link="impl-shared.HiLoPMUOverflow.1" file="shared_pseudocode.xml" hover="function: boolean HiLoPMUOverflow(boolean resvd_for_el2)">HiLoPMUOverflow</a>(resvd_for_el2);</line>
<line></line>
<line>    // PMCR_EL0.DP or PMCR.DP disables the cycle counter when event counting is prohibited</line>
<line>    if (prohibited || frozen) &amp;&amp; idx == <a link="CYCLE_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer CYCLE_COUNTER_ID = 31">CYCLE_COUNTER_ID</a> then</line>
<line>        dp = if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then PMCR_EL0.DP else PMCR.DP;</line>
<line>        enabled = enabled &amp;&amp; dp == '0';</line>
<line>        // Otherwise whether event counting is prohibited does not affect the cycle counter</line>
<line>        prohibited = FALSE;</line>
<line>        frozen = FALSE;</line>
<line></line>
<line>    // Freeze-on-SPE event is not implemented.</line>
<line></line>
<line>    // If FEAT_PMUv3p5 is implemented, cycle counting can be prohibited.</line>
<line>    // This is not overridden by PMCR_EL0.DP.</line>
<line>    if <a link="impl-shared.HavePMUv3p5.0" file="shared_pseudocode.xml" hover="function: boolean HavePMUv3p5()">HavePMUv3p5</a>() &amp;&amp; idx == <a link="CYCLE_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer CYCLE_COUNTER_ID = 31">CYCLE_COUNTER_ID</a> then</line>
<line>        if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>            sccd = if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then MDCR_EL3.SCCD else SDCR.SCCD;</line>
<line>            if sccd == '1' then</line>
<line>                prohibited = TRUE;</line>
<line></line>
<line>        if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>            hccd = if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then MDCR_EL2.HCCD else HDCR.HCCD;</line>
<line>            if hccd == '1' then</line>
<line>                prohibited = TRUE;</line>
<line></line>
<line>    // If FEAT_PMUv3p7 is implemented, cycle counting an be prohibited at EL3.</line>
<line>    // This is not overriden by PMCR_EL0.DP.</line>
<line>    if <a link="impl-shared.HavePMUv3p7.0" file="shared_pseudocode.xml" hover="function: boolean HavePMUv3p7()">HavePMUv3p7</a>() &amp;&amp; idx == <a link="CYCLE_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer CYCLE_COUNTER_ID = 31">CYCLE_COUNTER_ID</a> then</line>
<line>        if PSTATE.EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> &amp;&amp; <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() &amp;&amp; MDCR_EL3.MCCD == '1' then</line>
<line>            prohibited = TRUE;</line>
<line></line>
<line>    // Event counting can be filtered by the {P, U, NSK, NSU, NSH, M, SH, RLK, RLU, RLH} bits</line>
<line>    bits(32) filter;</line>
<line>    case idx of</line>
<line>        when <a link="INSTRUCTION_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer INSTRUCTION_COUNTER_ID = 32">INSTRUCTION_COUNTER_ID</a></line>
<line>            filter = PMICFILTR_EL0&lt;31:0&gt;;</line>
<line>        when <a link="CYCLE_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer CYCLE_COUNTER_ID = 31">CYCLE_COUNTER_ID</a></line>
<line>            filter = if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then PMCCFILTR_EL0&lt;31:0&gt; else PMCCFILTR;</line>
<line>        otherwise</line>
<line>            filter = if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then PMEVTYPER_EL0[idx]&lt;31:0&gt; else PMEVTYPER[idx];</line>
<line></line>
<line>    P   = filter&lt;31&gt;;</line>
<line>    U   = filter&lt;30&gt;;</line>
<line>    NSK = if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then filter&lt;29&gt; else '0';</line>
<line>    NSU = if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then filter&lt;28&gt; else '0';</line>
<line>    NSH = if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then filter&lt;27&gt; else '0';</line>
<line>    M   = if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then filter&lt;26&gt; else '0';</line>
<line>    SH  = if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>() then filter&lt;24&gt; else '0';</line>
<line>    RLK = if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then filter&lt;22&gt; else '0';</line>
<line>    RLU = if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then filter&lt;21&gt; else '0';</line>
<line>    RLH = if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then filter&lt;20&gt; else '0';</line>
<line></line>
<line>    ss = <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>();</line>
<line>    case PSTATE.EL of</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>            case ss of</line>
<line>                when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> filtered = U != NSU;</line>
<line>                when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>    filtered = U == '1';</line>
<line>                when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>     filtered = U != RLU;</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            case ss of</line>
<line>                when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> filtered = P != NSK;</line>
<line>                when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>    filtered = P == '1';</line>
<line>                when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>     filtered = P != RLK;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            case ss of</line>
<line>                when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> filtered = NSH == '0';</line>
<line>                when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>    filtered = NSH == SH;</line>
<line>                when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>     filtered = NSH == RLH;</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then</line>
<line>                filtered = M != P;</line>
<line>            else</line>
<line>                filtered = P == '1';</line>
<line></line>
<line>    return !debug &amp;&amp; enabled &amp;&amp; !prohibited &amp;&amp; !filtered &amp;&amp; !frozen;</line>
</pstext>
    </ps>
    <ps name="shared/debug/pmu/GetNumEventCounters" mylink="shared.debug.pmu.GetNumEventCounters" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GetNumEventCounters()</line>
<line>// =====================</line>
<line>// Returns the number of event counters implemented. This is indicated to software at the</line>
<line>// highest Exception level by PMCR.N in AArch32 state, and PMCR_EL0.N in AArch64 state.</line>
<line></line>
<line link="impl-shared.GetNumEventCounters.0" hover="function: integer GetNumEventCounters()" conts="GetNumEventCounters">integer <anchor link="impl-shared.GetNumEventCounters.0" hover="function: integer GetNumEventCounters()">GetNumEventCounters</anchor>()</line>
<line>    return integer IMPLEMENTATION_DEFINED "Number of event counters";</line>
</pstext>
    </ps>
    <ps name="shared/debug/pmu/HasElapsed64Cycles" mylink="shared.debug.pmu.HasElapsed64Cycles" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HasElapsed64Cycles()</line>
<line>// ====================</line>
<line>// Returns TRUE if 64 cycles have elapsed between the last count, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HasElapsed64Cycles.0" hover="function: boolean HasElapsed64Cycles()" conts="HasElapsed64Cycles">boolean <anchor link="impl-shared.HasElapsed64Cycles.0" hover="function: boolean HasElapsed64Cycles()">HasElapsed64Cycles</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/debug/pmu/HiLoPMUOverflow" mylink="shared.debug.pmu.HiLoPMUOverflow" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HiLoPMUOverflow()</line>
<line>// =================</line>
<line></line>
<line link="impl-shared.HiLoPMUOverflow.1" hover="function: boolean HiLoPMUOverflow(boolean resvd_for_el2)" conts="HiLoPMUOverflow">boolean <anchor link="impl-shared.HiLoPMUOverflow.1" hover="function: boolean HiLoPMUOverflow(boolean resvd_for_el2)">HiLoPMUOverflow</anchor>(boolean resvd_for_el2)</line>
<line>    boolean check_cnten  = FALSE;</line>
<line>    boolean check_e      = FALSE;</line>
<line>    boolean check_inten  = FALSE;</line>
<line>    boolean include_lo   = !resvd_for_el2;</line>
<line>    boolean include_hi   = resvd_for_el2;</line>
<line>    boolean exclude_cyc  = FALSE;</line>
<line>    boolean exclude_sync = FALSE;</line>
<line></line>
<line>    boolean overflow = <a link="impl-shared.PMUOverflowCondition.7" file="shared_pseudocode.xml" hover="function: boolean PMUOverflowCondition(boolean check_e, boolean check_cnten, boolean check_inten, boolean include_hi, boolean include_lo, boolean exclude_cyc, boolean exclude_sync)">PMUOverflowCondition</a>(check_e, check_cnten, check_inten,</line>
<line>                                            include_hi, include_lo,</line>
<line>                                            exclude_cyc, exclude_sync);</line>
<line>    return overflow;</line>
</pstext>
    </ps>
    <ps name="shared/debug/pmu/INSTRUCTION_COUNTER_ID" mylink="shared.debug.pmu.INSTRUCTION_COUNTER_ID" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="INSTRUCTION_COUNTER_ID" hover="constant integer INSTRUCTION_COUNTER_ID = 32" conts="INSTRUCTION_COUNTER_ID">constant integer <anchor link="INSTRUCTION_COUNTER_ID" hover="constant integer INSTRUCTION_COUNTER_ID = 32">INSTRUCTION_COUNTER_ID</anchor> = 32;</line>
</pstext>
    </ps>
    <ps name="shared/debug/pmu/IncrementInstructionCounter" mylink="shared.debug.pmu.IncrementInstructionCounter" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IncrementInstructionCounter()</line>
<line>// =============================</line>
<line>// Increment the instruction counter and possibly set overflow bits.</line>
<line></line>
<line link="impl-shared.IncrementInstructionCounter.1" hover="function: IncrementInstructionCounter(integer increment)" conts="IncrementInstructionCounter"><anchor link="impl-shared.IncrementInstructionCounter.1" hover="function: IncrementInstructionCounter(integer increment)">IncrementInstructionCounter</anchor>(integer increment)</line>
<line>    if <a link="impl-shared.CountPMUEvents.1" file="shared_pseudocode.xml" hover="function: boolean CountPMUEvents(integer idx)">CountPMUEvents</a>(<a link="INSTRUCTION_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer INSTRUCTION_COUNTER_ID = 32">INSTRUCTION_COUNTER_ID</a>) then</line>
<line>        integer old_value = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PMICNTR_EL0);</line>
<line>        integer new_value = old_value + increment;</line>
<line>        PMICNTR_EL0       = new_value&lt;63:0&gt;;</line>
<line></line>
<line>        // The effective value of PMCR_EL0.LP is '1' for the instruction counter</line>
<line>        if old_value&lt;64&gt; != new_value&lt;64&gt; then</line>
<line>            PMOVSSET_EL0.F0 = '1';</line>
<line>            PMOVSCLR_EL0.F0 = '1';</line>
</pstext>
    </ps>
    <ps name="shared/debug/pmu/PMUCountValue" mylink="shared.debug.pmu.PMUCountValue" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PMUCountValue()</line>
<line>// ===============</line>
<line>// Implements the PMU threshold function, if implemented.</line>
<line>// Returns the value to increment event counter 'n' by.</line>
<line>// 'Vb' is the base value of the event that event counter 'n' is configured to count.</line>
<line></line>
<line link="impl-shared.PMUCountValue.2" hover="function: integer PMUCountValue(integer n, integer Vb)" conts="PMUCountValue">integer <anchor link="impl-shared.PMUCountValue.2" hover="function: integer PMUCountValue(integer n, integer Vb)">PMUCountValue</anchor>(integer n, integer Vb)</line>
<line>    if !<a link="impl-shared.HavePMUv3TH.0" file="shared_pseudocode.xml" hover="function: boolean HavePMUv3TH()">HavePMUv3TH</a>() || !<a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then</line>
<line>        return Vb;</line>
<line></line>
<line>    integer T = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PMEVTYPER_EL0[n].TH);</line>
<line>    boolean Vc;</line>
<line></line>
<line>    case PMEVTYPER_EL0[n].TC&lt;2:1&gt; of</line>
<line>        when '00' Vc = (Vb != T);       // Disabled or not-equal</line>
<line>        when '01' Vc = (Vb == T);       // Equals</line>
<line>        when '10' Vc = (Vb &gt;= T);       // Greater-than-or-equal</line>
<line>        when '11' Vc = (Vb &lt;  T);       // Less-than</line>
<line></line>
<line>    if PMEVTYPER_EL0[n].TC&lt;0&gt; == '0' then</line>
<line>        Vt = (if Vc then Vb else 0);    // Count values</line>
<line>    else</line>
<line>        Vt = (if Vc then 1 else 0);     // Count matches</line>
<line></line>
<line>    integer V;</line>
<line>    if <a link="impl-shared.HavePMUv3EDGE.0" file="shared_pseudocode.xml" hover="function: boolean HavePMUv3EDGE()">HavePMUv3EDGE</a>() &amp;&amp; PMEVTYPER_EL0[n].TE == '1' then</line>
<line>        Vp = PMULastThresholdValue[n];</line>
<line></line>
<line>        tc = PMEVTYPER_EL0[n].TC&lt;1:0&gt;;</line>
<line>        // Check for reserved case</line>
<line>        if tc == '00' then</line>
<line>            <a link="Constraint" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint</a> c;</line>
<line>            (c, tc) = <a link="impl-shared.ConstrainUnpredictableBits.2" file="shared_pseudocode.xml" hover="function: (Constraint,bits(width)) ConstrainUnpredictableBits(Unpredictable which, integer width)">ConstrainUnpredictableBits</a>(<a link="Unpredictable_RESTC" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESTC</a>, 2);</line>
<line>            if c == <a link="Constraint_DISABLED" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_DISABLED</a> then tc = '00';</line>
<line>            // Otherwise the value returned by ConstrainUnpredictableBits</line>
<line>            // must be a not-reserved value.</line>
<line></line>
<line>        case tc of</line>
<line>            when '00' V = Vt;                           // Reserved - treat as disabled</line>
<line>            when '10' V = (if Vp != Vc  then 1 else 0); // Both edges</line>
<line>            when 'x1' V = (if !Vp &amp;&amp; Vc then 1 else 0); // Single edge</line>
<line>    else</line>
<line>        V = Vt;</line>
<line></line>
<line>    PMULastThresholdValue[n] = Vc;</line>
<line></line>
<line>    return V;</line>
</pstext>
    </ps>
    <ps name="shared/debug/pmu/PMUCounterIsHyp" mylink="shared.debug.pmu.PMUCounterIsHyp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PMUCounterIsHyp()</line>
<line>// =================</line>
<line>// Returns TRUE if a counter is reserved for use by EL2, FALSE otherwise.</line>
<line></line>
<line link="impl-shared.PMUCounterIsHyp.1" hover="function: boolean PMUCounterIsHyp(integer n)" conts="PMUCounterIsHyp">boolean <anchor link="impl-shared.PMUCounterIsHyp.1" hover="function: boolean PMUCounterIsHyp(integer n)">PMUCounterIsHyp</anchor>(integer n)</line>
<line>    if n == <a link="INSTRUCTION_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer INSTRUCTION_COUNTER_ID = 32">INSTRUCTION_COUNTER_ID</a> then return FALSE;</line>
<line>    if n == <a link="CYCLE_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer CYCLE_COUNTER_ID = 31">CYCLE_COUNTER_ID</a> then return FALSE;</line>
<line></line>
<line>    boolean resvd_for_el2;</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then     // Software can reserve some event counters for EL2</line>
<line>        bits(5) hpmn_bits = if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then MDCR_EL2.HPMN else HDCR.HPMN;</line>
<line>        resvd_for_el2 = n &gt;= <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(hpmn_bits);</line>
<line>        if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(hpmn_bits) &gt; <a link="impl-shared.GetNumEventCounters.0" file="shared_pseudocode.xml" hover="function: integer GetNumEventCounters()">GetNumEventCounters</a>() || (!<a link="impl-shared.HaveFeatHPMN0.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatHPMN0()">HaveFeatHPMN0</a>() &amp;&amp; <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(hpmn_bits)) then</line>
<line>            resvd_for_el2 = <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_CounterReservedForEL2" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_CounterReservedForEL2</a>);</line>
<line>    else</line>
<line>        resvd_for_el2 = FALSE;</line>
<line></line>
<line>    return resvd_for_el2;</line>
</pstext>
    </ps>
    <ps name="shared/debug/pmu/PMUCounterMask" mylink="shared.debug.pmu.PMUCounterMask" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PMUCounterMask()</line>
<line>// ================</line>
<line>// Return bitmask of accessible PMU counters.</line>
<line></line>
<line link="impl-shared.PMUCounterMask.0" hover="function: bits(64) PMUCounterMask()" conts="PMUCounterMask">bits(64) <anchor link="impl-shared.PMUCounterMask.0" hover="function: bits(64) PMUCounterMask()">PMUCounterMask</anchor>()</line>
<line>    integer n;</line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        n = <a link="AArch32.GetNumEventCountersAccessible.0" file="shared_pseudocode.xml" hover="function: integer AArch32.GetNumEventCountersAccessible()">AArch32.GetNumEventCountersAccessible</a>();</line>
<line>    else</line>
<line>        n = <a link="AArch64.GetNumEventCountersAccessible.0" file="shared_pseudocode.xml" hover="function: integer AArch64.GetNumEventCountersAccessible()">AArch64.GetNumEventCountersAccessible</a>();</line>
<line></line>
<line>    mask = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(n), 64);</line>
<line>    mask&lt;<a link="CYCLE_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer CYCLE_COUNTER_ID = 31">CYCLE_COUNTER_ID</a>&gt; = '1';</line>
<line>    if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() &amp;&amp; <a link="impl-shared.HavePMUv3ICNTR.0" file="shared_pseudocode.xml" hover="function: boolean HavePMUv3ICNTR()">HavePMUv3ICNTR</a>() then mask&lt;<a link="INSTRUCTION_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer INSTRUCTION_COUNTER_ID = 32">INSTRUCTION_COUNTER_ID</a>&gt; = '1';</line>
<line>    return mask;</line>
</pstext>
    </ps>
    <ps name="shared/debug/pmu/PMUEvent" mylink="shared.debug.pmu.PMUEvent" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PMUEvent()</line>
<line>// ==========</line>
<line>// Generate a PMU event. By default, increment by 1.</line>
<line></line>
<line link="impl-shared.PMUEvent.1" hover="function: PMUEvent(bits(16) event)" conts="PMUEvent"><anchor link="impl-shared.PMUEvent.1" hover="function: PMUEvent(bits(16) event)">PMUEvent</anchor>(bits(16) event)</line>
<line>    <a link="impl-shared.PMUEvent.2" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event, integer increment)">PMUEvent</a>(event, 1);</line>
<line></line>
<line>// PMUEvent()</line>
<line>// ==========</line>
<line>// Accumulate a PMU Event.</line>
<line></line>
<line link="impl-shared.PMUEvent.2" hover="function: PMUEvent(bits(16) event, integer increment)" conts="PMUEvent"><anchor link="impl-shared.PMUEvent.2" hover="function: PMUEvent(bits(16) event, integer increment)">PMUEvent</anchor>(bits(16) event, integer increment)</line>
<line>    if SPESampleInFlight then</line>
<line>        <a link="impl-aarch64.SPEEvent.1" file="shared_pseudocode.xml" hover="function: SPEEvent(bits(16) event)">SPEEvent</a>(event);</line>
<line>    integer counters = <a link="impl-shared.GetNumEventCounters.0" file="shared_pseudocode.xml" hover="function: integer GetNumEventCounters()">GetNumEventCounters</a>();</line>
<line>    if counters != 0 then</line>
<line>        for idx = 0 to counters - 1</line>
<line>            <a link="impl-shared.PMUEvent.3" file="shared_pseudocode.xml" hover="function: PMUEvent(bits(16) event, integer increment, integer idx)">PMUEvent</a>(event, increment, idx);</line>
<line></line>
<line>    if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() &amp;&amp; <a link="impl-shared.HavePMUv3ICNTR.0" file="shared_pseudocode.xml" hover="function: boolean HavePMUv3ICNTR()">HavePMUv3ICNTR</a>() &amp;&amp; event == PMU_EVENT_INST_RETIRED then</line>
<line>        <a link="impl-shared.IncrementInstructionCounter.1" file="shared_pseudocode.xml" hover="function: IncrementInstructionCounter(integer increment)">IncrementInstructionCounter</a>(increment);</line>
<line></line>
<line>// PMUEvent()</line>
<line>// ==========</line>
<line>// Accumulate a PMU Event for a specific event counter.</line>
<line></line>
<line link="impl-shared.PMUEvent.3" hover="function: PMUEvent(bits(16) event, integer increment, integer idx)" conts="PMUEvent"><anchor link="impl-shared.PMUEvent.3" hover="function: PMUEvent(bits(16) event, integer increment, integer idx)">PMUEvent</anchor>(bits(16) event, integer increment, integer idx)</line>
<line>    if !<a link="impl-shared.HavePMUv3.0" file="shared_pseudocode.xml" hover="function: boolean HavePMUv3()">HavePMUv3</a>() then</line>
<line>        return;</line>
<line></line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        if PMEVTYPER[idx].evtCount == event then</line>
<line>            PMUEventAccumulator[idx] = PMUEventAccumulator[idx] + increment;</line>
<line>    else</line>
<line>        if PMEVTYPER_EL0[idx].evtCount == event then</line>
<line>            PMUEventAccumulator[idx] = PMUEventAccumulator[idx] + increment;</line>
</pstext>
    </ps>
    <ps name="shared/debug/pmu/PMUOverflowCondition" mylink="shared.debug.pmu.PMUOverflowCondition" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PMUOverflowCondition()</line>
<line>// ======================</line>
<line>// Checks for PMU overflow under certain parameter conditions</line>
<line>// If 'check_e' is TRUE, then check the applicable one of PMCR_EL0.E and MDCR_EL2.HPME.</line>
<line>// If 'check_cnten' is TRUE, then check the applicable PMCNTENCLR_EL0 bit.</line>
<line>// If 'check_cnten' is TRUE, then check the applicable PMINTENCLR_EL1 bit.</line>
<line>// If 'include_lo' is TRUE, then check counters in the set [0..(HPMN-1)], CCNTR</line>
<line>//     and ICNTR, unless excluded by other flags.</line>
<line>// If 'include_hi' is TRUE, then check counters in the set [HPMN..(N-1)].</line>
<line>// If 'exclude_cyc' is TRUE, then CCNTR is NOT checked.</line>
<line>// If 'exclude_sync' is TRUE, then counters in synchronous mode are NOT checked.</line>
<line></line>
<line link="impl-shared.PMUOverflowCondition.7" hover="function: boolean PMUOverflowCondition(boolean check_e, boolean check_cnten, boolean check_inten, boolean include_hi, boolean include_lo, boolean exclude_cyc, boolean exclude_sync)" conts="PMUOverflowCondition">boolean <anchor link="impl-shared.PMUOverflowCondition.7" hover="function: boolean PMUOverflowCondition(boolean check_e, boolean check_cnten, boolean check_inten, boolean include_hi, boolean include_lo, boolean exclude_cyc, boolean exclude_sync)">PMUOverflowCondition</anchor>(boolean check_e, boolean check_cnten,</line>
<line>                             boolean check_inten,</line>
<line>                             boolean include_hi, boolean include_lo,</line>
<line>                             boolean exclude_cyc, boolean exclude_sync)</line>
<line>    integer counters = <a link="impl-shared.GetNumEventCounters.0" file="shared_pseudocode.xml" hover="function: integer GetNumEventCounters()">GetNumEventCounters</a>();</line>
<line></line>
<line>    bits(64) ovsf;</line>
<line></line>
<line>    if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then</line>
<line>        ovsf = PMOVSCLR_EL0;</line>
<line></line>
<line>        // Remove unimplemented counters - these fields are RES0</line>
<line>        ovsf&lt;63:33&gt; = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(31);</line>
<line></line>
<line>        if !<a link="impl-shared.HavePMUv3ICNTR.0" file="shared_pseudocode.xml" hover="function: boolean HavePMUv3ICNTR()">HavePMUv3ICNTR</a>() then</line>
<line>            ovsf&lt;<a link="INSTRUCTION_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer INSTRUCTION_COUNTER_ID = 32">INSTRUCTION_COUNTER_ID</a>&gt; = '0';</line>
<line>    else</line>
<line>        ovsf = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(PMOVSR, 64);</line>
<line></line>
<line>    if counters &lt; 31 then</line>
<line>        ovsf&lt;30:counters&gt; = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(31-counters);</line>
<line></line>
<line>    for idx = 0 to counters - 1</line>
<line>        bit E;</line>
<line></line>
<line>        boolean is_hyp = <a link="impl-shared.PMUCounterIsHyp.1" file="shared_pseudocode.xml" hover="function: boolean PMUCounterIsHyp(integer n)">PMUCounterIsHyp</a>(idx);</line>
<line>        if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then</line>
<line>            E = (if is_hyp then MDCR_EL2.HPME else PMCR_EL0.E);</line>
<line>        else</line>
<line>            E = (if is_hyp then HDCR.HPME else PMCR.E);</line>
<line></line>
<line>        if check_e then</line>
<line>            ovsf&lt;idx&gt; = ovsf&lt;idx&gt; AND E;</line>
<line></line>
<line>        if (!is_hyp &amp;&amp; !include_lo) || (is_hyp &amp;&amp; !include_hi) then</line>
<line>            ovsf&lt;idx&gt; = '0';</line>
<line></line>
<line>    // Cycle counter</line>
<line>    if exclude_cyc || !include_lo then</line>
<line>        ovsf&lt;<a link="CYCLE_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer CYCLE_COUNTER_ID = 31">CYCLE_COUNTER_ID</a>&gt; = '0';</line>
<line></line>
<line>    if check_e then</line>
<line>        ovsf&lt;<a link="CYCLE_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer CYCLE_COUNTER_ID = 31">CYCLE_COUNTER_ID</a>&gt; = ovsf&lt;<a link="CYCLE_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer CYCLE_COUNTER_ID = 31">CYCLE_COUNTER_ID</a>&gt; AND PMCR_EL0.E;</line>
<line></line>
<line>    // Instruction counter</line>
<line>    if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() &amp;&amp; <a link="impl-shared.HavePMUv3ICNTR.0" file="shared_pseudocode.xml" hover="function: boolean HavePMUv3ICNTR()">HavePMUv3ICNTR</a>() then</line>
<line>        if !include_lo then</line>
<line>            ovsf&lt;<a link="INSTRUCTION_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer INSTRUCTION_COUNTER_ID = 32">INSTRUCTION_COUNTER_ID</a>&gt; = '0';</line>
<line>        if check_e then</line>
<line>            ovsf&lt;<a link="INSTRUCTION_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer INSTRUCTION_COUNTER_ID = 32">INSTRUCTION_COUNTER_ID</a>&gt; = ovsf&lt;<a link="INSTRUCTION_COUNTER_ID" file="shared_pseudocode.xml" hover="constant integer INSTRUCTION_COUNTER_ID = 32">INSTRUCTION_COUNTER_ID</a>&gt; AND PMCR_EL0.E;</line>
<line></line>
<line>    if check_cnten then</line>
<line>        bits(64) cnten = if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then PMCNTENCLR_EL0 else <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(PMCNTENCLR, 64);</line>
<line>        ovsf = ovsf AND cnten;</line>
<line></line>
<line>    if check_inten then</line>
<line>        bits(64) inten = if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then PMINTENCLR_EL1 else <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(PMINTENCLR, 64);</line>
<line>        ovsf = ovsf AND inten;</line>
<line></line>
<line>    return !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(ovsf);</line>
</pstext>
    </ps>
    <ps name="shared/debug/samplebasedprofiling/CreatePCSample" mylink="shared.debug.samplebasedprofiling.CreatePCSample" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreatePCSample()</line>
<line>// ================</line>
<line></line>
<line link="impl-shared.CreatePCSample.0" hover="function: CreatePCSample()" conts="CreatePCSample"><anchor link="impl-shared.CreatePCSample.0" hover="function: CreatePCSample()">CreatePCSample</anchor>()</line>
<line>    // In a simple sequential execution of the program, CreatePCSample is executed each time the PE</line>
<line>    // executes an instruction that can be sampled. An implementation is not constrained such that</line>
<line>    // reads of EDPCSRlo return the current values of PC, etc.</line>
<line></line>
<line>    pc_sample.valid = <a link="impl-shared.ExternalNoninvasiveDebugAllowed.0" file="shared_pseudocode.xml" hover="function: boolean ExternalNoninvasiveDebugAllowed()">ExternalNoninvasiveDebugAllowed</a>() &amp;&amp; !<a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>();</line>
<line>    pc_sample.pc = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>    pc_sample.el = PSTATE.EL;</line>
<line>    pc_sample.rw = if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then '0' else '1';</line>
<line>    pc_sample.ss = <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>();</line>
<line>    pc_sample.contextidr = if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then CONTEXTIDR else CONTEXTIDR_EL1&lt;31:0&gt;;</line>
<line>    pc_sample.has_el2 = PSTATE.EL != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>();</line>
<line></line>
<line>    if pc_sample.has_el2 then</line>
<line>        if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>            pc_sample.vmid = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(VTTBR.VMID, 16);</line>
<line>        elsif !<a link="impl-shared.Have16bitVMID.0" file="shared_pseudocode.xml" hover="function: boolean Have16bitVMID()">Have16bitVMID</a>() || VTCR_EL2.VS == '0' then</line>
<line>            pc_sample.vmid = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(VTTBR_EL2.VMID&lt;7:0&gt;, 16);</line>
<line>        else</line>
<line>            pc_sample.vmid = VTTBR_EL2.VMID;</line>
<line>        if (<a link="impl-shared.HaveVirtHostExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</a>() || <a link="impl-shared.HaveV82Debug.0" file="shared_pseudocode.xml" hover="function: boolean HaveV82Debug()">HaveV82Debug</a>()) &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>            pc_sample.contextidr_el2 = CONTEXTIDR_EL2&lt;31:0&gt;;</line>
<line>        else</line>
<line>            pc_sample.contextidr_el2 = bits(32) UNKNOWN;</line>
<line>        pc_sample.el0h = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>();</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/debug/samplebasedprofiling/EDPCSRlo" mylink="shared.debug.samplebasedprofiling.EDPCSRlo" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EDPCSRlo[] (read)</line>
<line>// =================</line>
<line></line>
<line link="impl-shared.EDPCSRlo.read.1" hover="accessor: bits(32) EDPCSRlo[boolean memory_mapped]" conts="EDPCSRlo">bits(32) <anchor link="impl-shared.EDPCSRlo.read.1" hover="accessor: bits(32) EDPCSRlo[boolean memory_mapped]">EDPCSRlo</anchor>[boolean memory_mapped]</line>
<line></line>
<line>    if EDPRSR&lt;6:5,0&gt; != '001' then                      // Check DLK, OSLK and PU bits</line>
<line>        IMPLEMENTATION_DEFINED "generate error response";</line>
<line>        return bits(32) UNKNOWN;</line>
<line></line>
<line>    // The Software lock is OPTIONAL.</line>
<line>    update = !memory_mapped || EDLSR.SLK == '0';        // Software locked: no side-effects</line>
<line></line>
<line>    bits(32) sample;</line>
<line>    if pc_sample.valid then</line>
<line>        sample = pc_sample.pc&lt;31:0&gt;;</line>
<line>        if update then</line>
<line>            if <a link="impl-shared.HaveVirtHostExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</a>() &amp;&amp; EDSCR.SC2 == '1' then</line>
<line>                EDPCSRhi.PC = (if pc_sample.rw == '0' then <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(24) else pc_sample.pc&lt;55:32&gt;);</line>
<line>                EDPCSRhi.EL = pc_sample.el;</line>
<line>                EDPCSRhi.NS = (if pc_sample.ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then '0' else '1');</line>
<line>            else</line>
<line>                EDPCSRhi = (if pc_sample.rw == '0' then <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(32) else pc_sample.pc&lt;63:32&gt;);</line>
<line>            EDCIDSR = pc_sample.contextidr;</line>
<line>            if (<a link="impl-shared.HaveVirtHostExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</a>() || <a link="impl-shared.HaveV82Debug.0" file="shared_pseudocode.xml" hover="function: boolean HaveV82Debug()">HaveV82Debug</a>()) &amp;&amp; EDSCR.SC2 == '1' then</line>
<line>                EDVIDSR = (if pc_sample.has_el2 then pc_sample.contextidr_el2</line>
<line>                           else bits(32) UNKNOWN);</line>
<line>            else</line>
<line>                EDVIDSR.VMID = (if pc_sample.has_el2 &amp;&amp; pc_sample.el IN {<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>,<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>}</line>
<line>                                then pc_sample.vmid else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16));</line>
<line>                EDVIDSR.NS = (if pc_sample.ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then '0' else '1');</line>
<line>                EDVIDSR.E2 = (if pc_sample.el == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then '1' else '0');</line>
<line>                EDVIDSR.E3 = (if pc_sample.el == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then '1' else '0') AND pc_sample.rw;</line>
<line>                // The conditions for setting HV are not specified if PCSRhi is zero.</line>
<line>                // An example implementation may be "pc_sample.rw".</line>
<line>                EDVIDSR.HV = (if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(EDPCSRhi) then '1'</line>
<line>                              else bit IMPLEMENTATION_DEFINED "0 or 1");</line>
<line>    else</line>
<line>        sample = <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(32);</line>
<line>        if update then</line>
<line>            EDPCSRhi = bits(32) UNKNOWN;</line>
<line>            EDCIDSR = bits(32) UNKNOWN;</line>
<line>            EDVIDSR = bits(32) UNKNOWN;</line>
<line></line>
<line>    return sample;</line>
</pstext>
    </ps>
    <ps name="shared/debug/samplebasedprofiling/PCSample" mylink="shared.debug.samplebasedprofiling.PCSample" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line><a link="PCSample" file="shared_pseudocode.xml" hover="type PCSample is ( boolean valid, bits(64) pc, bits(2) el, bit rw, SecurityState ss, boolean has_el2, bits(32) contextidr, bits(32) contextidr_el2, boolean el0h, bits(16) vmid )">PCSample</a> pc_sample;</line>
<line></line>
<line>// PCSample</line>
<line>// ========</line>
<line></line>
<line link="PCSample" hover="type PCSample is ( boolean valid, bits(64) pc, bits(2) el, bit rw, SecurityState ss, boolean has_el2, bits(32) contextidr, bits(32) contextidr_el2, boolean el0h, bits(16) vmid )" conts="PCSample">type <anchor link="PCSample" hover="type PCSample is ( boolean valid, bits(64) pc, bits(2) el, bit rw, SecurityState ss, boolean has_el2, bits(32) contextidr, bits(32) contextidr_el2, boolean el0h, bits(16) vmid )">PCSample</anchor> is (</line>
<line>    boolean valid,</line>
<line>    bits(64) pc,</line>
<line>    bits(2) el,</line>
<line>    bit rw,</line>
<line>    <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss,</line>
<line>    boolean has_el2,</line>
<line>    bits(32) contextidr,</line>
<line>    bits(32) contextidr_el2,</line>
<line>    boolean el0h,</line>
<line>    bits(16) vmid</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="shared/debug/samplebasedprofiling/PMPCSR" mylink="shared.debug.samplebasedprofiling.PMPCSR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PMPCSR[] (read)</line>
<line>// ===============</line>
<line></line>
<line link="impl-shared.PMPCSR.read.1" hover="accessor: bits(32) PMPCSR[boolean memory_mapped]" conts="PMPCSR">bits(32) <anchor link="impl-shared.PMPCSR.read.1" hover="accessor: bits(32) PMPCSR[boolean memory_mapped]">PMPCSR</anchor>[boolean memory_mapped]</line>
<line>    if EDPRSR&lt;6:5,0&gt; != '001' then                      // Check DLK, OSLK and PU bits</line>
<line>        IMPLEMENTATION_DEFINED "generate error response";</line>
<line>        return bits(32) UNKNOWN;</line>
<line></line>
<line>    // The Software lock is OPTIONAL.</line>
<line>    update = !memory_mapped || PMLSR.SLK == '0';        // Software locked: no side-effects</line>
<line></line>
<line>    bits(32) sample;</line>
<line>    if pc_sample.valid then</line>
<line>        sample = pc_sample.pc&lt;31:0&gt;;</line>
<line>        if update then</line>
<line>            PMPCSR&lt;55:32&gt; = (if pc_sample.rw == '0' then <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(24) else pc_sample.pc&lt;55:32&gt;);</line>
<line>            PMPCSR.EL = pc_sample.el;</line>
<line>            if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then</line>
<line>                case pc_sample.ss of</line>
<line>                    when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a></line>
<line>                        PMPCSR.NSE = '0'; PMPCSR.NS = '0';</line>
<line>                    when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a></line>
<line>                        PMPCSR.NSE = '0'; PMPCSR.NS = '1';</line>
<line>                    when <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a></line>
<line>                        PMPCSR.NSE = '1'; PMPCSR.NS = '0';</line>
<line>                    when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a></line>
<line>                        PMPCSR.NSE = '1'; PMPCSR.NS = '1';</line>
<line>            else</line>
<line>                PMPCSR.NS = (if pc_sample.ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then '0' else '1');</line>
<line></line>
<line>            PMCID1SR = pc_sample.contextidr;</line>
<line>            PMCID2SR = if pc_sample.has_el2 then pc_sample.contextidr_el2 else bits(32) UNKNOWN;</line>
<line></line>
<line>            PMVIDSR.VMID = (if pc_sample.has_el2 &amp;&amp; pc_sample.el IN {<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>,<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>} &amp;&amp; !pc_sample.el0h</line>
<line>                            then pc_sample.vmid else bits(16) UNKNOWN);</line>
<line>    else</line>
<line>        sample = <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(32);</line>
<line>        if update then</line>
<line>            PMPCSR&lt;55:32&gt;  = bits(24) UNKNOWN;</line>
<line>            PMPCSR.EL = bits(2) UNKNOWN;</line>
<line>            PMPCSR.NS = bit UNKNOWN;</line>
<line></line>
<line>            PMCID1SR = bits(32) UNKNOWN;</line>
<line>            PMCID2SR = bits(32) UNKNOWN;</line>
<line></line>
<line>            PMVIDSR.VMID = bits(16) UNKNOWN;</line>
<line></line>
<line>    return sample;</line>
</pstext>
    </ps>
    <ps name="shared/debug/softwarestep/CheckSoftwareStep" mylink="shared.debug.softwarestep.CheckSoftwareStep" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CheckSoftwareStep()</line>
<line>// ===================</line>
<line>// Take a Software Step exception if in the active-pending state</line>
<line></line>
<line link="impl-shared.CheckSoftwareStep.0" hover="function: CheckSoftwareStep()" conts="CheckSoftwareStep"><anchor link="impl-shared.CheckSoftwareStep.0" hover="function: CheckSoftwareStep()">CheckSoftwareStep</anchor>()</line>
<line></line>
<line>    // Other self-hosted debug functions will call AArch32.GenerateDebugExceptions() if called from</line>
<line>    // AArch32 state. However, because Software Step is only active when the debug target Exception</line>
<line>    // level is using AArch64, CheckSoftwareStep only calls AArch64.GenerateDebugExceptions().</line>
<line>    step_enabled = (!<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="impl-shared.DebugTarget.0" file="shared_pseudocode.xml" hover="function: bits(2) DebugTarget()">DebugTarget</a>()) &amp;&amp; <a link="AArch64.GenerateDebugExceptions.0" file="shared_pseudocode.xml" hover="function: boolean AArch64.GenerateDebugExceptions()">AArch64.GenerateDebugExceptions</a>() &amp;&amp;</line>
<line>                    MDSCR_EL1.SS == '1');</line>
<line>    if step_enabled &amp;&amp; PSTATE.SS == '0' then</line>
<line>        <a link="AArch64.SoftwareStepException.0" file="shared_pseudocode.xml" hover="function: AArch64.SoftwareStepException()">AArch64.SoftwareStepException</a>();</line>
</pstext>
    </ps>
    <ps name="shared/debug/softwarestep/DebugExceptionReturnSS" mylink="shared.debug.softwarestep.DebugExceptionReturnSS" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DebugExceptionReturnSS()</line>
<line>// ========================</line>
<line>// Returns value to write to PSTATE.SS on an exception return or Debug state exit.</line>
<line></line>
<line link="impl-shared.DebugExceptionReturnSS.1" hover="function: bit DebugExceptionReturnSS(bits(N) spsr)" conts="DebugExceptionReturnSS">bit <anchor link="impl-shared.DebugExceptionReturnSS.1" hover="function: bit DebugExceptionReturnSS(bits(N) spsr)">DebugExceptionReturnSS</anchor>(bits(N) spsr)</line>
<line>    assert <a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() || <a link="impl-shared.Restarting.0" file="shared_pseudocode.xml" hover="function: boolean Restarting()">Restarting</a>() ||  PSTATE.EL != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;</line>
<line></line>
<line>    boolean enabled_at_source;</line>
<line>    if <a link="impl-shared.Restarting.0" file="shared_pseudocode.xml" hover="function: boolean Restarting()">Restarting</a>() then</line>
<line>        enabled_at_source = FALSE;</line>
<line>    elsif <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        enabled_at_source = <a link="AArch32.GenerateDebugExceptions.0" file="shared_pseudocode.xml" hover="function: boolean AArch32.GenerateDebugExceptions()">AArch32.GenerateDebugExceptions</a>();</line>
<line>    else</line>
<line>        enabled_at_source = <a link="AArch64.GenerateDebugExceptions.0" file="shared_pseudocode.xml" hover="function: boolean AArch64.GenerateDebugExceptions()">AArch64.GenerateDebugExceptions</a>();</line>
<line></line>
<line>    boolean valid;</line>
<line>    bits(2) dest_el;</line>
<line>    if <a link="impl-shared.IllegalExceptionReturn.1" file="shared_pseudocode.xml" hover="function: boolean IllegalExceptionReturn(bits(N) spsr)">IllegalExceptionReturn</a>(spsr) then</line>
<line>        dest_el = PSTATE.EL;</line>
<line>    else</line>
<line>        (valid, dest_el) = <a link="impl-shared.ELFromSPSR.1" file="shared_pseudocode.xml" hover="function: (boolean,bits(2)) ELFromSPSR(bits(N) spsr)">ELFromSPSR</a>(spsr);  assert valid;</line>
<line></line>
<line>    dest_ss = <a link="impl-shared.SecurityStateAtEL.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)">SecurityStateAtEL</a>(dest_el);</line>
<line>    bit mask;</line>
<line>    boolean enabled_at_dest;</line>
<line>    dest_using_32 = (if dest_el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then spsr&lt;4&gt; == '1' else <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(dest_el));</line>
<line>    if dest_using_32 then</line>
<line>        enabled_at_dest = <a link="AArch32.GenerateDebugExceptionsFrom.2" file="shared_pseudocode.xml" hover="function: boolean AArch32.GenerateDebugExceptionsFrom(bits(2) from_el, SecurityState from_state)">AArch32.GenerateDebugExceptionsFrom</a>(dest_el, dest_ss);</line>
<line>    else</line>
<line>        mask = spsr&lt;9&gt;;</line>
<line>        enabled_at_dest = <a link="AArch64.GenerateDebugExceptionsFrom.3" file="shared_pseudocode.xml" hover="function: boolean AArch64.GenerateDebugExceptionsFrom(bits(2) from_el, SecurityState from_state, bit mask)">AArch64.GenerateDebugExceptionsFrom</a>(dest_el, dest_ss, mask);</line>
<line></line>
<line>    ELd = <a link="impl-shared.DebugTargetFrom.1" file="shared_pseudocode.xml" hover="function: bits(2) DebugTargetFrom(SecurityState from_state)">DebugTargetFrom</a>(dest_ss);</line>
<line>    bit SS_bit;</line>
<line>    if !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(ELd) &amp;&amp; MDSCR_EL1.SS == '1' &amp;&amp; !enabled_at_source &amp;&amp; enabled_at_dest then</line>
<line>        SS_bit = spsr&lt;21&gt;;</line>
<line>    else</line>
<line>        SS_bit = '0';</line>
<line></line>
<line>    return SS_bit;</line>
</pstext>
    </ps>
    <ps name="shared/debug/softwarestep/SSAdvance" mylink="shared.debug.softwarestep.SSAdvance" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SSAdvance()</line>
<line>// ===========</line>
<line>// Advance the Software Step state machine.</line>
<line></line>
<line link="impl-shared.SSAdvance.0" hover="function: SSAdvance()" conts="SSAdvance"><anchor link="impl-shared.SSAdvance.0" hover="function: SSAdvance()">SSAdvance</anchor>()</line>
<line></line>
<line>    // A simpler implementation of this function just clears PSTATE.SS to zero regardless of the</line>
<line>    // current Software Step state machine. However, this check is made to illustrate that the</line>
<line>    // processor only needs to consider advancing the state machine from the active-not-pending</line>
<line>    // state.</line>
<line>    target = <a link="impl-shared.DebugTarget.0" file="shared_pseudocode.xml" hover="function: bits(2) DebugTarget()">DebugTarget</a>();</line>
<line>    step_enabled = !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(target) &amp;&amp; MDSCR_EL1.SS == '1';</line>
<line>    active_not_pending = step_enabled &amp;&amp; PSTATE.SS == '1';</line>
<line></line>
<line>    if active_not_pending then PSTATE.SS = '0';</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/debug/softwarestep/SoftwareStep_DidNotStep" mylink="shared.debug.softwarestep.SoftwareStep_DidNotStep" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SoftwareStep_DidNotStep()</line>
<line>// =========================</line>
<line>// Returns TRUE if the previously executed instruction was executed in the</line>
<line>// inactive state, that is, if it was not itself stepped.</line>
<line>// Might return TRUE or FALSE if the previously executed instruction was an ISB</line>
<line>// or ERET executed in the active-not-pending state, or if another exception</line>
<line>// was taken before the Software Step exception.  Returns FALSE otherwise,</line>
<line>// indicating that the previously executed instruction was executed in the</line>
<line>// active-not-pending state, that is, the instruction was stepped.</line>
<line></line>
<line link="impl-shared.SoftwareStep_DidNotStep.0" hover="function: boolean SoftwareStep_DidNotStep()" conts="SoftwareStep_DidNotStep">boolean <anchor link="impl-shared.SoftwareStep_DidNotStep.0" hover="function: boolean SoftwareStep_DidNotStep()">SoftwareStep_DidNotStep</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/debug/softwarestep/SoftwareStep_SteppedEX" mylink="shared.debug.softwarestep.SoftwareStep_SteppedEX" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SoftwareStep_SteppedEX()</line>
<line>// ========================</line>
<line>// Returns a value that describes the previously executed instruction. The</line>
<line>// result is valid only if SoftwareStep_DidNotStep() returns FALSE.</line>
<line>// Might return TRUE or FALSE if the instruction was an AArch32 LDREX or LDAEX</line>
<line>// that failed its condition code test.  Otherwise returns TRUE if the</line>
<line>// instruction was a Load-Exclusive class instruction, and FALSE if the</line>
<line>// instruction was not a Load-Exclusive class instruction.</line>
<line link="impl-shared.SoftwareStep_SteppedEX.0" hover="function: boolean SoftwareStep_SteppedEX()" conts="SoftwareStep_SteppedEX">boolean <anchor link="impl-shared.SoftwareStep_SteppedEX.0" hover="function: boolean SoftwareStep_SteppedEX()">SoftwareStep_SteppedEX</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/exceptions/exceptions/ConditionSyndrome" mylink="shared.exceptions.exceptions.ConditionSyndrome" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ConditionSyndrome()</line>
<line>// ===================</line>
<line>// Return CV and COND fields of instruction syndrome</line>
<line></line>
<line link="impl-shared.ConditionSyndrome.0" hover="function: bits(5) ConditionSyndrome()" conts="ConditionSyndrome">bits(5) <anchor link="impl-shared.ConditionSyndrome.0" hover="function: bits(5) ConditionSyndrome()">ConditionSyndrome</anchor>()</line>
<line></line>
<line>    bits(5) syndrome;</line>
<line></line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        cond = <a link="AArch32.CurrentCond.0" file="shared_pseudocode.xml" hover="function: bits(4) AArch32.CurrentCond()">AArch32.CurrentCond</a>();</line>
<line>        if PSTATE.T == '0' then             // A32</line>
<line>            syndrome&lt;4&gt; = '1';</line>
<line>            // A conditional A32 instruction that is known to pass its condition code check</line>
<line>            // can be presented either with COND set to 0xE, the value for unconditional, or</line>
<line>            // the COND value held in the instruction.</line>
<line>            if <a link="impl-shared.ConditionHolds.1" file="shared_pseudocode.xml" hover="function: boolean ConditionHolds(bits(4) cond)">ConditionHolds</a>(cond) &amp;&amp; <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_ESRCONDPASS" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_ESRCONDPASS</a>) then</line>
<line>                syndrome&lt;3:0&gt; = '1110';</line>
<line>            else</line>
<line>                syndrome&lt;3:0&gt; = cond;</line>
<line>        else                                // T32</line>
<line>            // When a T32 instruction is trapped, it is IMPLEMENTATION DEFINED whether:</line>
<line>            //  * CV set to 0 and COND is set to an UNKNOWN value</line>
<line>            //  * CV set to 1 and COND is set to the condition code for the condition that</line>
<line>            //    applied to the instruction.</line>
<line>            if boolean IMPLEMENTATION_DEFINED "Condition valid for trapped T32" then</line>
<line>                syndrome&lt;4&gt; = '1';</line>
<line>                syndrome&lt;3:0&gt; = cond;</line>
<line>            else</line>
<line>                syndrome&lt;4&gt; = '0';</line>
<line>                syndrome&lt;3:0&gt; = bits(4) UNKNOWN;</line>
<line>    else</line>
<line>        syndrome&lt;4&gt; = '1';</line>
<line>        syndrome&lt;3:0&gt; = '1110';</line>
<line></line>
<line>    return syndrome;</line>
</pstext>
    </ps>
    <ps name="shared/exceptions/exceptions/Exception" mylink="shared.exceptions.exceptions.Exception" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Exception</line>
<line>// =========</line>
<line>// Classes of exception.</line>
<line></line>
<line link="Exception" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception">enumeration <anchor link="Exception" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception</anchor> {</line>
<line link="Exception_Uncategorized" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_Uncategorized">        <anchor link="Exception_Uncategorized" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Uncategorized</anchor>,        // Uncategorized or unknown reason</line>
<line link="Exception_WFxTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_WFxTrap">        <anchor link="Exception_WFxTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_WFxTrap</anchor>,              // Trapped WFI or WFE instruction</line>
<line link="Exception_CP15RTTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_CP15RTTrap">        <anchor link="Exception_CP15RTTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP15RTTrap</anchor>,           // Trapped AArch32 MCR or MRC access, coproc=0b111</line>
<line link="Exception_CP15RRTTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_CP15RRTTrap">        <anchor link="Exception_CP15RRTTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP15RRTTrap</anchor>,          // Trapped AArch32 MCRR or MRRC access, coproc=0b1111</line>
<line link="Exception_CP14RTTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_CP14RTTrap">        <anchor link="Exception_CP14RTTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14RTTrap</anchor>,           // Trapped AArch32 MCR or MRC access, coproc=0b1110</line>
<line link="Exception_CP14DTTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_CP14DTTrap">        <anchor link="Exception_CP14DTTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14DTTrap</anchor>,           // Trapped AArch32 LDC or STC access, coproc=0b1110</line>
<line link="Exception_CP14RRTTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_CP14RRTTrap">        <anchor link="Exception_CP14RRTTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_CP14RRTTrap</anchor>,          // Trapped AArch32 MRRC access, coproc=0b1110</line>
<line link="Exception_AdvSIMDFPAccessTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_AdvSIMDFPAccessTrap">        <anchor link="Exception_AdvSIMDFPAccessTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_AdvSIMDFPAccessTrap</anchor>,  // HCPTR-trapped access to SIMD or FP</line>
<line link="Exception_FPIDTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_FPIDTrap">        <anchor link="Exception_FPIDTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FPIDTrap</anchor>,             // Trapped access to SIMD or FP ID register</line>
<line link="Exception_LDST64BTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_LDST64BTrap">        <anchor link="Exception_LDST64BTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_LDST64BTrap</anchor>,          // Trapped access to ST64BV, ST64BV0, ST64B and LD64B</line>
<line>        // Trapped BXJ instruction not supported in Armv8</line>
<line link="Exception_PACTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_PACTrap">        <anchor link="Exception_PACTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_PACTrap</anchor>,               // Trapped invalid PAC use</line>
<line link="Exception_IllegalState" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_IllegalState">        <anchor link="Exception_IllegalState" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_IllegalState</anchor>,          // Illegal Execution state</line>
<line link="Exception_SupervisorCall" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_SupervisorCall">        <anchor link="Exception_SupervisorCall" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SupervisorCall</anchor>,        // Supervisor Call</line>
<line link="Exception_HypervisorCall" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_HypervisorCall">        <anchor link="Exception_HypervisorCall" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_HypervisorCall</anchor>,        // Hypervisor Call</line>
<line link="Exception_MonitorCall" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_MonitorCall">        <anchor link="Exception_MonitorCall" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_MonitorCall</anchor>,           // Monitor Call or Trapped SMC instruction</line>
<line link="Exception_SystemRegisterTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_SystemRegisterTrap">        <anchor link="Exception_SystemRegisterTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SystemRegisterTrap</anchor>,    // Trapped MRS or MSR System register access</line>
<line link="Exception_ERetTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_ERetTrap">        <anchor link="Exception_ERetTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_ERetTrap</anchor>,              // Trapped invalid ERET use</line>
<line link="Exception_InstructionAbort" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_InstructionAbort">        <anchor link="Exception_InstructionAbort" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_InstructionAbort</anchor>,      // Instruction Abort or Prefetch Abort</line>
<line link="Exception_PCAlignment" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_PCAlignment">        <anchor link="Exception_PCAlignment" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_PCAlignment</anchor>,           // PC alignment fault</line>
<line link="Exception_DataAbort" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_DataAbort">        <anchor link="Exception_DataAbort" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_DataAbort</anchor>,             // Data Abort</line>
<line link="Exception_NV2DataAbort" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_NV2DataAbort">        <anchor link="Exception_NV2DataAbort" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_NV2DataAbort</anchor>,          // Data abort at EL1 reported as being from EL2</line>
<line link="Exception_PACFail" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_PACFail">        <anchor link="Exception_PACFail" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_PACFail</anchor>,               // PAC Authentication failure</line>
<line link="Exception_SPAlignment" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_SPAlignment">        <anchor link="Exception_SPAlignment" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SPAlignment</anchor>,           // SP alignment fault</line>
<line link="Exception_FPTrappedException" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_FPTrappedException">        <anchor link="Exception_FPTrappedException" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FPTrappedException</anchor>,    // IEEE trapped FP exception</line>
<line link="Exception_SError" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_SError">        <anchor link="Exception_SError" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SError</anchor>,                // SError interrupt</line>
<line link="Exception_Breakpoint" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_Breakpoint">        <anchor link="Exception_Breakpoint" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Breakpoint</anchor>,            // (Hardware) Breakpoint</line>
<line link="Exception_SoftwareStep" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_SoftwareStep">        <anchor link="Exception_SoftwareStep" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SoftwareStep</anchor>,          // Software Step</line>
<line link="Exception_Watchpoint" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_Watchpoint">        <anchor link="Exception_Watchpoint" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_Watchpoint</anchor>,            // Watchpoint</line>
<line link="Exception_NV2Watchpoint" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_NV2Watchpoint">        <anchor link="Exception_NV2Watchpoint" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_NV2Watchpoint</anchor>,         // Watchpoint at EL1 reported as being from EL2</line>
<line link="Exception_SoftwareBreakpoint" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_SoftwareBreakpoint">        <anchor link="Exception_SoftwareBreakpoint" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SoftwareBreakpoint</anchor>,    // Software Breakpoint Instruction</line>
<line link="Exception_VectorCatch" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_VectorCatch">        <anchor link="Exception_VectorCatch" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_VectorCatch</anchor>,           // AArch32 Vector Catch</line>
<line link="Exception_IRQ" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_IRQ">        <anchor link="Exception_IRQ" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_IRQ</anchor>,                   // IRQ interrupt</line>
<line link="Exception_SVEAccessTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_SVEAccessTrap">        <anchor link="Exception_SVEAccessTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SVEAccessTrap</anchor>,         // HCPTR trapped access to SVE</line>
<line link="Exception_SMEAccessTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_SMEAccessTrap">        <anchor link="Exception_SMEAccessTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SMEAccessTrap</anchor>,         // HCPTR trapped access to SME</line>
<line link="Exception_TSTARTAccessTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_TSTARTAccessTrap">        <anchor link="Exception_TSTARTAccessTrap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_TSTARTAccessTrap</anchor>,      // Trapped TSTART access</line>
<line link="Exception_GPC" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_GPC">        <anchor link="Exception_GPC" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_GPC</anchor>,                   // Granule protection check</line>
<line link="Exception_BranchTarget" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_BranchTarget">        <anchor link="Exception_BranchTarget" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_BranchTarget</anchor>,          // Branch Target Identification</line>
<line link="Exception_MemCpyMemSet" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_MemCpyMemSet">        <anchor link="Exception_MemCpyMemSet" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_MemCpyMemSet</anchor>,          // Exception from a CPY* or SET* instruction</line>
<line link="Exception_GCSFail" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_GCSFail">        <anchor link="Exception_GCSFail" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_GCSFail</anchor>,               // GCS Exceptions</line>
<line link="Exception_SystemRegister128Trap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_SystemRegister128Trap">        <anchor link="Exception_SystemRegister128Trap" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_SystemRegister128Trap</anchor>, // Trapped MRRS or MSRR System register or SYSP access</line>
<line link="Exception_FIQ" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}" conts="Exception_FIQ">        <anchor link="Exception_FIQ" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception_FIQ</anchor>};                 // FIQ interrupt</line>
</pstext>
    </ps>
    <ps name="shared/exceptions/exceptions/ExceptionRecord" mylink="shared.exceptions.exceptions.ExceptionRecord" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExceptionRecord</line>
<line>// ===============</line>
<line></line>
<line link="ExceptionRecord" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)" conts="ExceptionRecord">type <anchor link="ExceptionRecord" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</anchor> is (</line>
<line>    <a link="Exception" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception</a>   exceptype,           // Exception class</line>
<line>    bits(25)    syndrome,            // Syndrome record</line>
<line>    bits(24)    syndrome2,           // Syndrome record</line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> paddress,            // Physical fault address</line>
<line>    bits(64)    vaddress,            // Virtual fault address</line>
<line>    boolean     ipavalid,            // Validity of Intermediate Physical fault address</line>
<line>    boolean     pavalid,             // Validity of Physical fault address</line>
<line>    bit         NS,                  // Intermediate Physical fault address space</line>
<line>    bits(56)    ipaddress,           // Intermediate Physical fault address</line>
<line>    boolean     trappedsyscallinst)  // Trapped SVC or SMC instruction</line>
</pstext>
    </ps>
    <ps name="shared/exceptions/exceptions/ExceptionSyndrome" mylink="shared.exceptions.exceptions.ExceptionSyndrome" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExceptionSyndrome()</line>
<line>// ===================</line>
<line>// Return a blank exception syndrome record for an exception of the given type.</line>
<line></line>
<line link="impl-shared.ExceptionSyndrome.1" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)" conts="ExceptionSyndrome">ExceptionRecord <anchor link="impl-shared.ExceptionSyndrome.1" hover="function: ExceptionRecord ExceptionSyndrome(Exception exceptype)">ExceptionSyndrome</anchor>(<a link="Exception" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception</a> exceptype)</line>
<line></line>
<line>    <a link="ExceptionRecord" file="shared_pseudocode.xml" hover="type ExceptionRecord is ( Exception exceptype, bits(25) syndrome, bits(24) syndrome2, FullAddress paddress, bits(64) vaddress, boolean ipavalid, boolean pavalid, bit NS, bits(56) ipaddress, boolean trappedsyscallinst)">ExceptionRecord</a> r;</line>
<line></line>
<line>    r.exceptype = exceptype;</line>
<line></line>
<line>    // Initialize all other fields</line>
<line>    r.syndrome  = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(25);</line>
<line>    r.syndrome2 = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(24);</line>
<line>    r.vaddress  = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>    r.ipavalid  = FALSE;</line>
<line>    r.NS        = '0';</line>
<line>    r.ipaddress = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(56);</line>
<line>    r.paddress.paspace = <a link="PASpace" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PASpace</a> UNKNOWN;</line>
<line>    r.paddress.address = bits(56) UNKNOWN;</line>
<line>    r.trappedsyscallinst = FALSE;</line>
<line>    return r;</line>
</pstext>
    </ps>
    <ps name="shared/functions/aborts/EncodeLDFSC" mylink="shared.functions.aborts.EncodeLDFSC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EncodeLDFSC()</line>
<line>// =============</line>
<line>// Function that gives the Long-descriptor FSC code for types of Fault</line>
<line></line>
<line link="impl-shared.EncodeLDFSC.2" hover="function: bits(6) EncodeLDFSC(Fault statuscode, integer level)" conts="EncodeLDFSC">bits(6) <anchor link="impl-shared.EncodeLDFSC.2" hover="function: bits(6) EncodeLDFSC(Fault statuscode, integer level)">EncodeLDFSC</anchor>(<a link="Fault" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault</a> statuscode, integer level)</line>
<line>    bits(6) result;</line>
<line></line>
<line>    // 128-bit descriptors will start from level -2 for 4KB to resolve bits IA[55:51]</line>
<line>    if level == -2 then</line>
<line>        assert <a link="impl-shared.Have56BitPAExt.0" file="shared_pseudocode.xml" hover="function: boolean Have56BitPAExt()">Have56BitPAExt</a>();</line>
<line>        case statuscode of</line>
<line>            when <a link="Fault_AddressSize" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AddressSize</a>          result = '101100';</line>
<line>            when <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>          result = '101010';</line>
<line>            when <a link="Fault_SyncExternalOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncExternalOnWalk</a>   result = '010010';</line>
<line>            when <a link="Fault_SyncParityOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncParityOnWalk</a>     result = '011010'; assert !<a link="impl-shared.HaveRASExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveRASExt()">HaveRASExt</a>();</line>
<line>            when <a link="Fault_GPCFOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_GPCFOnWalk</a>           result = '100010';</line>
<line>            otherwise                       <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>        return result;</line>
<line></line>
<line>    if level == -1 then</line>
<line>        assert <a link="impl-shared.Have52BitIPAAndPASpaceExt.0" file="shared_pseudocode.xml" hover="function: boolean Have52BitIPAAndPASpaceExt()">Have52BitIPAAndPASpaceExt</a>();</line>
<line>        case statuscode of</line>
<line>            when <a link="Fault_AddressSize" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AddressSize</a>          result = '101001';</line>
<line>            when <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>          result = '101011';</line>
<line>            when <a link="Fault_SyncExternalOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncExternalOnWalk</a>   result = '010011';</line>
<line>            when <a link="Fault_SyncParityOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncParityOnWalk</a>     result = '011011'; assert !<a link="impl-shared.HaveRASExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveRASExt()">HaveRASExt</a>();</line>
<line>            when <a link="Fault_GPCFOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_GPCFOnWalk</a>           result = '100011';</line>
<line>            otherwise                       <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>        return result;</line>
<line>    case statuscode of</line>
<line>        when <a link="Fault_AddressSize" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AddressSize</a>         result = '0000':level&lt;1:0&gt;; assert level IN {0,1,2,3};</line>
<line>        when <a link="Fault_AccessFlag" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AccessFlag</a>          result = '0010':level&lt;1:0&gt;; assert level IN {0,1,2,3};</line>
<line>        when <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>          result = '0011':level&lt;1:0&gt;; assert level IN {0,1,2,3};</line>
<line>        when <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>         result = '0001':level&lt;1:0&gt;; assert level IN {0,1,2,3};</line>
<line>        when <a link="Fault_SyncExternal" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncExternal</a>        result = '010000';</line>
<line>        when <a link="Fault_SyncExternalOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncExternalOnWalk</a>  result = '0101':level&lt;1:0&gt;; assert level IN {0,1,2,3};</line>
<line>        when <a link="Fault_SyncParity" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncParity</a>          result = '011000';</line>
<line>        when <a link="Fault_SyncParityOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncParityOnWalk</a>    result = '0111':level&lt;1:0&gt;; assert level IN {0,1,2,3};</line>
<line>        when <a link="Fault_AsyncParity" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncParity</a>         result = '011001';</line>
<line>        when <a link="Fault_AsyncExternal" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncExternal</a>       result = '010001'; assert <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>();</line>
<line>        when <a link="Fault_TagCheck" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_TagCheck</a>            result = '010001'; assert <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>();</line>
<line>        when <a link="Fault_Alignment" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Alignment</a>           result = '100001';</line>
<line>        when <a link="Fault_Debug" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Debug</a>               result = '100010';</line>
<line>        when <a link="Fault_GPCFOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_GPCFOnWalk</a>          result = '1001':level&lt;1:0&gt;; assert level IN {0,1,2,3};</line>
<line>        when <a link="Fault_GPCFOnOutput" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_GPCFOnOutput</a>        result = '101000';</line>
<line>        when <a link="Fault_TLBConflict" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_TLBConflict</a>         result = '110000';</line>
<line>        when <a link="Fault_HWUpdateAccessFlag" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_HWUpdateAccessFlag</a>  result = '110001';</line>
<line>        when <a link="Fault_Lockdown" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Lockdown</a>            result = '110100';  // IMPLEMENTATION DEFINED</line>
<line>        when <a link="Fault_Exclusive" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Exclusive</a>           result = '110101';  // IMPLEMENTATION DEFINED</line>
<line>        otherwise                      <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/aborts/IPAValid" mylink="shared.functions.aborts.IPAValid" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IPAValid()</line>
<line>// ==========</line>
<line>// Return TRUE if the IPA is reported for the abort</line>
<line></line>
<line link="impl-shared.IPAValid.1" hover="function: boolean IPAValid(FaultRecord fault)" conts="IPAValid">boolean <anchor link="impl-shared.IPAValid.1" hover="function: boolean IPAValid(FaultRecord fault)">IPAValid</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    assert fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a>;</line>
<line></line>
<line>    if fault.gpcf.gpf != <a link="GPCF_None" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_None</a> then</line>
<line>        return fault.secondstage;</line>
<line>    elsif fault.s2fs1walk then</line>
<line>        return fault.statuscode IN {</line>
<line>            <a link="Fault_AccessFlag" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AccessFlag</a>,</line>
<line>            <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a>,</line>
<line>            <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>,</line>
<line>            <a link="Fault_AddressSize" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AddressSize</a></line>
<line>        };</line>
<line>    elsif fault.secondstage then</line>
<line>        return fault.statuscode IN {</line>
<line>            <a link="Fault_AccessFlag" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AccessFlag</a>,</line>
<line>            <a link="Fault_Translation" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</a>,</line>
<line>            <a link="Fault_AddressSize" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AddressSize</a></line>
<line>        };</line>
<line>    else</line>
<line>        return FALSE;</line>
</pstext>
    </ps>
    <ps name="shared/functions/aborts/IsAsyncAbort" mylink="shared.functions.aborts.IsAsyncAbort" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsAsyncAbort()</line>
<line>// ==============</line>
<line>// Returns TRUE if the abort currently being processed is an asynchronous abort, and FALSE</line>
<line>// otherwise.</line>
<line></line>
<line link="impl-shared.IsAsyncAbort.1" hover="function: boolean IsAsyncAbort(Fault statuscode)" conts="IsAsyncAbort">boolean <anchor link="impl-shared.IsAsyncAbort.1" hover="function: boolean IsAsyncAbort(Fault statuscode)">IsAsyncAbort</anchor>(<a link="Fault" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault</a> statuscode)</line>
<line>    assert statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a>;</line>
<line></line>
<line>    return (statuscode IN {<a link="Fault_AsyncExternal" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncExternal</a>, <a link="Fault_AsyncParity" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncParity</a>});</line>
<line></line>
<line>// IsAsyncAbort()</line>
<line>// ==============</line>
<line></line>
<line>boolean <a link="impl-shared.IsAsyncAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsAsyncAbort(Fault statuscode)">IsAsyncAbort</a>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    return <a link="impl-shared.IsAsyncAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsAsyncAbort(Fault statuscode)">IsAsyncAbort</a>(fault.statuscode);</line>
</pstext>
    </ps>
    <ps name="shared/functions/aborts/IsDebugException" mylink="shared.functions.aborts.IsDebugException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsDebugException()</line>
<line>// ==================</line>
<line></line>
<line link="impl-shared.IsDebugException.1" hover="function: boolean IsDebugException(FaultRecord fault)" conts="IsDebugException">boolean <anchor link="impl-shared.IsDebugException.1" hover="function: boolean IsDebugException(FaultRecord fault)">IsDebugException</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    assert fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a>;</line>
<line>    return fault.statuscode == <a link="Fault_Debug" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Debug</a>;</line>
</pstext>
    </ps>
    <ps name="shared/functions/aborts/IsExternalAbort" mylink="shared.functions.aborts.IsExternalAbort" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsExternalAbort()</line>
<line>// =================</line>
<line>// Returns TRUE if the abort currently being processed is an External abort and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.IsExternalAbort.1" hover="function: boolean IsExternalAbort(Fault statuscode)" conts="IsExternalAbort">boolean <anchor link="impl-shared.IsExternalAbort.1" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</anchor>(<a link="Fault" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault</a> statuscode)</line>
<line>    assert statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a>;</line>
<line></line>
<line>    return (statuscode IN {</line>
<line>        <a link="Fault_SyncExternal" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncExternal</a>,</line>
<line>        <a link="Fault_SyncParity" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncParity</a>,</line>
<line>        <a link="Fault_SyncExternalOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncExternalOnWalk</a>,</line>
<line>        <a link="Fault_SyncParityOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncParityOnWalk</a>,</line>
<line>        <a link="Fault_AsyncExternal" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncExternal</a>,</line>
<line>        <a link="Fault_AsyncParity" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncParity</a></line>
<line>    });</line>
<line></line>
<line>// IsExternalAbort()</line>
<line>// =================</line>
<line></line>
<line>boolean <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    return <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault.statuscode) || fault.gpcf.gpf == <a link="GPCF_EABT" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_EABT</a>;</line>
</pstext>
    </ps>
    <ps name="shared/functions/aborts/IsExternalSyncAbort" mylink="shared.functions.aborts.IsExternalSyncAbort" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsExternalSyncAbort()</line>
<line>// =====================</line>
<line>// Returns TRUE if the abort currently being processed is an external</line>
<line>// synchronous abort and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.IsExternalSyncAbort.1" hover="function: boolean IsExternalSyncAbort(Fault statuscode)" conts="IsExternalSyncAbort">boolean <anchor link="impl-shared.IsExternalSyncAbort.1" hover="function: boolean IsExternalSyncAbort(Fault statuscode)">IsExternalSyncAbort</anchor>(<a link="Fault" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault</a> statuscode)</line>
<line>    assert statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a>;</line>
<line></line>
<line>    return (statuscode IN {</line>
<line>        <a link="Fault_SyncExternal" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncExternal</a>,</line>
<line>        <a link="Fault_SyncParity" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncParity</a>,</line>
<line>        <a link="Fault_SyncExternalOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncExternalOnWalk</a>,</line>
<line>        <a link="Fault_SyncParityOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncParityOnWalk</a></line>
<line>    });</line>
<line></line>
<line>// IsExternalSyncAbort()</line>
<line>// =====================</line>
<line></line>
<line>boolean <a link="impl-shared.IsExternalSyncAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalSyncAbort(Fault statuscode)">IsExternalSyncAbort</a>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    return <a link="impl-shared.IsExternalSyncAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalSyncAbort(Fault statuscode)">IsExternalSyncAbort</a>(fault.statuscode) || fault.gpcf.gpf == <a link="GPCF_EABT" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_EABT</a>;</line>
</pstext>
    </ps>
    <ps name="shared/functions/aborts/IsFault" mylink="shared.functions.aborts.IsFault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsFault()</line>
<line>// =========</line>
<line>// Return TRUE if a fault is associated with an address descriptor</line>
<line></line>
<line link="impl-shared.IsFault.1" hover="function: boolean IsFault(AddressDescriptor addrdesc)" conts="IsFault">boolean <anchor link="impl-shared.IsFault.1" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</anchor>(<a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> addrdesc)</line>
<line>    return addrdesc.fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a>;</line>
<line></line>
<line>// IsFault()</line>
<line>// =========</line>
<line>// Return TRUE if a fault is associated with a memory access.</line>
<line></line>
<line>boolean <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(<a link="Fault" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault</a> fault)</line>
<line>    return fault != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a>;</line>
<line></line>
<line>// IsFault()</line>
<line>// =========</line>
<line>// Return TRUE if a fault is associated with status returned by memory.</line>
<line></line>
<line>boolean <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(<a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> retstatus)</line>
<line>    return retstatus.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a>;</line>
</pstext>
    </ps>
    <ps name="shared/functions/aborts/IsSErrorInterrupt" mylink="shared.functions.aborts.IsSErrorInterrupt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsSErrorInterrupt()</line>
<line>// ===================</line>
<line>// Returns TRUE if the abort currently being processed is an SError interrupt, and FALSE</line>
<line>// otherwise.</line>
<line></line>
<line link="impl-shared.IsSErrorInterrupt.1" hover="function: boolean IsSErrorInterrupt(Fault statuscode)" conts="IsSErrorInterrupt">boolean <anchor link="impl-shared.IsSErrorInterrupt.1" hover="function: boolean IsSErrorInterrupt(Fault statuscode)">IsSErrorInterrupt</anchor>(<a link="Fault" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault</a> statuscode)</line>
<line>    assert statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a>;</line>
<line></line>
<line>    return (statuscode IN {<a link="Fault_AsyncExternal" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncExternal</a>, <a link="Fault_AsyncParity" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncParity</a>});</line>
<line></line>
<line>// IsSErrorInterrupt()</line>
<line>// ===================</line>
<line></line>
<line>boolean <a link="impl-shared.IsSErrorInterrupt.1" file="shared_pseudocode.xml" hover="function: boolean IsSErrorInterrupt(Fault statuscode)">IsSErrorInterrupt</a>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    return <a link="impl-shared.IsSErrorInterrupt.1" file="shared_pseudocode.xml" hover="function: boolean IsSErrorInterrupt(Fault statuscode)">IsSErrorInterrupt</a>(fault.statuscode);</line>
</pstext>
    </ps>
    <ps name="shared/functions/aborts/IsSecondStage" mylink="shared.functions.aborts.IsSecondStage" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsSecondStage()</line>
<line>// ===============</line>
<line></line>
<line link="impl-shared.IsSecondStage.1" hover="function: boolean IsSecondStage(FaultRecord fault)" conts="IsSecondStage">boolean <anchor link="impl-shared.IsSecondStage.1" hover="function: boolean IsSecondStage(FaultRecord fault)">IsSecondStage</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    assert fault.statuscode != <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a>;</line>
<line></line>
<line>    return fault.secondstage;</line>
</pstext>
    </ps>
    <ps name="shared/functions/aborts/LSInstructionSyndrome" mylink="shared.functions.aborts.LSInstructionSyndrome" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// LSInstructionSyndrome()</line>
<line>// =======================</line>
<line>// Returns the extended syndrome information for a second stage fault.</line>
<line>//  &lt;10&gt;  - Syndrome valid bit. The syndrome is valid only for certain types of access instruction.</line>
<line>//  &lt;9:8&gt; - Access size.</line>
<line>//  &lt;7&gt;   - Sign extended (for loads).</line>
<line>//  &lt;6:2&gt; - Transfer register.</line>
<line>//  &lt;1&gt;   - Transfer register is 64-bit.</line>
<line>//  &lt;0&gt;   - Instruction has acquire/release semantics.</line>
<line></line>
<line link="impl-shared.LSInstructionSyndrome.0" hover="function: bits(11) LSInstructionSyndrome()" conts="LSInstructionSyndrome">bits(11) <anchor link="impl-shared.LSInstructionSyndrome.0" hover="function: bits(11) LSInstructionSyndrome()">LSInstructionSyndrome</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/aborts/ReportAsGPCException" mylink="shared.functions.aborts.ReportAsGPCException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ReportAsGPCException()</line>
<line>// ======================</line>
<line>// Determine whether the given GPCF is reported as a Granule Protection Check Exception</line>
<line>// rather than a Data or Instruction Abort</line>
<line></line>
<line link="impl-shared.ReportAsGPCException.1" hover="function: boolean ReportAsGPCException(FaultRecord fault)" conts="ReportAsGPCException">boolean <anchor link="impl-shared.ReportAsGPCException.1" hover="function: boolean ReportAsGPCException(FaultRecord fault)">ReportAsGPCException</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    assert <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>();</line>
<line>    assert fault.statuscode IN {<a link="Fault_GPCFOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_GPCFOnWalk</a>, <a link="Fault_GPCFOnOutput" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_GPCFOnOutput</a>};</line>
<line>    assert fault.gpcf.gpf != <a link="GPCF_None" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_None</a>;</line>
<line></line>
<line>    case fault.gpcf.gpf of</line>
<line>        when <a link="GPCF_Walk" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_Walk</a>        return TRUE;</line>
<line>        when <a link="GPCF_AddressSize" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_AddressSize</a> return TRUE;</line>
<line>        when <a link="GPCF_EABT" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_EABT</a>        return TRUE;</line>
<line>        when <a link="GPCF_Fail" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_Fail</a>        return SCR_EL3.GPF == '1' &amp;&amp; PSTATE.EL != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
</pstext>
    </ps>
    <ps name="shared/functions/cache/CACHE_OP" mylink="shared.functions.cache.CACHE_OP" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CACHE_OP()</line>
<line>// ==========</line>
<line>// Performs Cache maintenance operations as per CacheRecord.</line>
<line></line>
<line link="impl-shared.CACHE_OP.1" hover="function: CACHE_OP(CacheRecord cache)" conts="CACHE_OP"><anchor link="impl-shared.CACHE_OP.1" hover="function: CACHE_OP(CacheRecord cache)">CACHE_OP</anchor>(<a link="CacheRecord" file="shared_pseudocode.xml" hover="type CacheRecord is ( AccessType acctype, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, bits(64) regval, FullAddress paddress, bits(64) vaddress, integer set, integer way, integer level, Shareability shareability, boolean translated, boolean is_vmid_valid, bits(16) vmid, boolean is_asid_valid, bits(16) asid, SecurityState security, CachePASpace cpas )">CacheRecord</a> cache)</line>
<line>    IMPLEMENTATION_DEFINED;</line>
</pstext>
    </ps>
    <ps name="shared/functions/cache/CPASAtPAS" mylink="shared.functions.cache.CPASAtPAS" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CPASAtPAS()</line>
<line>// ===========</line>
<line>// Get cache PA space for given PA space.</line>
<line></line>
<line link="impl-shared.CPASAtPAS.1" hover="function: CachePASpace CPASAtPAS(PASpace pas)" conts="CPASAtPAS">CachePASpace <anchor link="impl-shared.CPASAtPAS.1" hover="function: CachePASpace CPASAtPAS(PASpace pas)">CPASAtPAS</anchor>(<a link="PASpace" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PASpace</a> pas)</line>
<line>    case pas of</line>
<line>        when <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a></line>
<line>            return <a link="CPAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }">CPAS_NonSecure</a>;</line>
<line>        when <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a></line>
<line>            return <a link="CPAS_Secure" file="shared_pseudocode.xml" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }">CPAS_Secure</a>;</line>
<line>        when <a link="PAS_Root" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Root</a></line>
<line>            return <a link="CPAS_Root" file="shared_pseudocode.xml" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }">CPAS_Root</a>;</line>
<line>        when <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a></line>
<line>            return <a link="CPAS_Realm" file="shared_pseudocode.xml" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }">CPAS_Realm</a>;</line>
</pstext>
    </ps>
    <ps name="shared/functions/cache/CPASAtSecurityState" mylink="shared.functions.cache.CPASAtSecurityState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CPASAtSecurityState()</line>
<line>// =====================</line>
<line>// Get cache PA space for given security state.</line>
<line></line>
<line link="impl-shared.CPASAtSecurityState.1" hover="function: CachePASpace CPASAtSecurityState(SecurityState ss)" conts="CPASAtSecurityState">CachePASpace <anchor link="impl-shared.CPASAtSecurityState.1" hover="function: CachePASpace CPASAtSecurityState(SecurityState ss)">CPASAtSecurityState</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss)</line>
<line>    case ss of</line>
<line>        when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a></line>
<line>            return <a link="CPAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }">CPAS_NonSecure</a>;</line>
<line>        when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a></line>
<line>            return <a link="CPAS_SecureNonSecure" file="shared_pseudocode.xml" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }">CPAS_SecureNonSecure</a>;</line>
<line>        when <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a></line>
<line>            return <a link="CPAS_Any" file="shared_pseudocode.xml" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }">CPAS_Any</a>;</line>
<line>        when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a></line>
<line>            return <a link="CPAS_RealmNonSecure" file="shared_pseudocode.xml" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }">CPAS_RealmNonSecure</a>;</line>
</pstext>
    </ps>
    <ps name="shared/functions/cache/CacheRecord" mylink="shared.functions.cache.CacheRecord" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CacheRecord</line>
<line>// ===========</line>
<line>// Details related to a cache operation.</line>
<line></line>
<line link="CacheRecord" hover="type CacheRecord is ( AccessType acctype, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, bits(64) regval, FullAddress paddress, bits(64) vaddress, integer set, integer way, integer level, Shareability shareability, boolean translated, boolean is_vmid_valid, bits(16) vmid, boolean is_asid_valid, bits(16) asid, SecurityState security, CachePASpace cpas )" conts="CacheRecord">type <anchor link="CacheRecord" hover="type CacheRecord is ( AccessType acctype, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, bits(64) regval, FullAddress paddress, bits(64) vaddress, integer set, integer way, integer level, Shareability shareability, boolean translated, boolean is_vmid_valid, bits(16) vmid, boolean is_asid_valid, bits(16) asid, SecurityState security, CachePASpace cpas )">CacheRecord</anchor> is (</line>
<line>    <a link="AccessType" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType</a>       acctype,           // Access type</line>
<line>    <a link="CacheOp" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp</a>          cacheop,           // Cache operation</line>
<line>    <a link="CacheOpScope" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope</a>     opscope,           // Cache operation type</line>
<line>    <a link="CacheType" file="shared_pseudocode.xml" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }">CacheType</a>        cachetype,         // Cache type</line>
<line>    bits(64)         regval,</line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a>      paddress,</line>
<line>    bits(64)         vaddress,          // For VA operations</line>
<line>    integer          set,               // For SW operations</line>
<line>    integer          way,               // For SW operations</line>
<line>    integer          level,             // For SW operations</line>
<line>    <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a>     shareability,</line>
<line>    boolean          translated,</line>
<line>    boolean          is_vmid_valid,     // is vmid valid for current context</line>
<line>    bits(16)         vmid,</line>
<line>    boolean          is_asid_valid,     // is asid valid for current context</line>
<line>    bits(16)         asid,</line>
<line>    <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a>    security,</line>
<line>    // For cache operations to full cache or by set/way</line>
<line>    // For operations by address, PA space in paddress</line>
<line>    <a link="CachePASpace" file="shared_pseudocode.xml" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }">CachePASpace</a>     cpas</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="shared/functions/cache/DCInstNeedsTranslation" mylink="shared.functions.cache.DCInstNeedsTranslation" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DCInstNeedsTranslation()</line>
<line>// ========================</line>
<line>// Check whether Data Cache operation needs translation.</line>
<line></line>
<line link="impl-shared.DCInstNeedsTranslation.1" hover="function: boolean DCInstNeedsTranslation(CacheOpScope opscope)" conts="DCInstNeedsTranslation">boolean <anchor link="impl-shared.DCInstNeedsTranslation.1" hover="function: boolean DCInstNeedsTranslation(CacheOpScope opscope)">DCInstNeedsTranslation</anchor>(<a link="CacheOpScope" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope</a> opscope)</line>
<line>    if opscope == <a link="CacheOpScope_PoE" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_PoE</a> then</line>
<line>        return FALSE;</line>
<line></line>
<line>    if CLIDR_EL1.LoC == '000' then</line>
<line>        return !(boolean IMPLEMENTATION_DEFINED</line>
<line>                 "No fault generated for DC operations if PoC is before any level of cache");</line>
<line></line>
<line>    if CLIDR_EL1.LoUU == '000' &amp;&amp; opscope == <a link="CacheOpScope_PoU" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_PoU</a> then</line>
<line>        return !(boolean IMPLEMENTATION_DEFINED</line>
<line>                 "No fault generated for DC operations if PoU is before any level of cache");</line>
<line></line>
<line>    return TRUE;</line>
</pstext>
    </ps>
    <ps name="shared/functions/cache/DecodeSW" mylink="shared.functions.cache.DecodeSW" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DecodeSW()</line>
<line>// ==========</line>
<line>// Decode input value into set, way and level for SW instructions.</line>
<line></line>
<line link="impl-shared.DecodeSW.2" hover="function: (integer, integer, integer) DecodeSW(bits(64) regval, CacheType cachetype)" conts="DecodeSW">(integer, integer, integer) <anchor link="impl-shared.DecodeSW.2" hover="function: (integer, integer, integer) DecodeSW(bits(64) regval, CacheType cachetype)">DecodeSW</anchor>(bits(64) regval, <a link="CacheType" file="shared_pseudocode.xml" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }">CacheType</a> cachetype)</line>
<line>    level = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(regval[3:1]);</line>
<line>    (set, way, linesize) = <a link="impl-shared.GetCacheInfo.2" file="shared_pseudocode.xml" hover="function: (integer, integer, integer) GetCacheInfo(integer level, CacheType cachetype)">GetCacheInfo</a>(level, cachetype);</line>
<line>    return (set, way, level);</line>
</pstext>
    </ps>
    <ps name="shared/functions/cache/GetCacheInfo" mylink="shared.functions.cache.GetCacheInfo" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GetCacheInfo()</line>
<line>// ==============</line>
<line>// Returns numsets, assosciativity &amp; linesize.</line>
<line></line>
<line link="impl-shared.GetCacheInfo.2" hover="function: (integer, integer, integer) GetCacheInfo(integer level, CacheType cachetype)" conts="GetCacheInfo">(integer, integer, integer) <anchor link="impl-shared.GetCacheInfo.2" hover="function: (integer, integer, integer) GetCacheInfo(integer level, CacheType cachetype)">GetCacheInfo</anchor>(integer level, <a link="CacheType" file="shared_pseudocode.xml" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }">CacheType</a> cachetype);</line>
</pstext>
    </ps>
    <ps name="shared/functions/cache/ICInstNeedsTranslation" mylink="shared.functions.cache.ICInstNeedsTranslation" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ICInstNeedsTranslation()</line>
<line>// ========================</line>
<line>// Check whether Instruction Cache operation needs translation.</line>
<line></line>
<line link="impl-shared.ICInstNeedsTranslation.1" hover="function: boolean ICInstNeedsTranslation(CacheOpScope opscope)" conts="ICInstNeedsTranslation">boolean <anchor link="impl-shared.ICInstNeedsTranslation.1" hover="function: boolean ICInstNeedsTranslation(CacheOpScope opscope)">ICInstNeedsTranslation</anchor>(<a link="CacheOpScope" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope</a> opscope)</line>
<line>    return boolean IMPLEMENTATION_DEFINED "Instruction Cache needs translation";</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/ASR" mylink="shared.functions.common.ASR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ASR()</line>
<line>// =====</line>
<line></line>
<line link="impl-shared.ASR.2" hover="function: bits(N) ASR(bits(N) x, integer shift)" conts="ASR">bits(N) <anchor link="impl-shared.ASR.2" hover="function: bits(N) ASR(bits(N) x, integer shift)">ASR</anchor>(bits(N) x, integer shift)</line>
<line>    assert shift &gt;= 0;</line>
<line>    bits(N) result;</line>
<line>    if shift == 0 then</line>
<line>        result = x;</line>
<line>    else</line>
<line>        (result, -) = <a link="impl-shared.ASR_C.2" file="shared_pseudocode.xml" hover="function: (bits(N), bit) ASR_C(bits(N) x, integer shift)">ASR_C</a>(x, shift);</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/ASR_C" mylink="shared.functions.common.ASR_C" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ASR_C()</line>
<line>// =======</line>
<line></line>
<line link="impl-shared.ASR_C.2" hover="function: (bits(N), bit) ASR_C(bits(N) x, integer shift)" conts="ASR_C">(bits(N), bit) <anchor link="impl-shared.ASR_C.2" hover="function: (bits(N), bit) ASR_C(bits(N) x, integer shift)">ASR_C</anchor>(bits(N) x, integer shift)</line>
<line>    assert shift &gt; 0 &amp;&amp; shift &lt; 256;</line>
<line>    extended_x = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(x, shift+N);</line>
<line>    result = extended_x&lt;(shift+N)-1:shift&gt;;</line>
<line>    carry_out = extended_x&lt;shift-1&gt;;</line>
<line>    return (result, carry_out);</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/Abs" mylink="shared.functions.common.Abs" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Abs()</line>
<line>// =====</line>
<line></line>
<line link="impl-shared.Abs.1" hover="function: integer Abs(integer x)" conts="Abs">integer <anchor link="impl-shared.Abs.1" hover="function: integer Abs(integer x)">Abs</anchor>(integer x)</line>
<line>    return if x &gt;= 0 then x else -x;</line>
<line></line>
<line>// Abs()</line>
<line>// =====</line>
<line></line>
<line>real <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(real x)</line>
<line>    return if x &gt;= 0.0 then x else -x;</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/Align" mylink="shared.functions.common.Align" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Align()</line>
<line>// =======</line>
<line></line>
<line link="impl-shared.Align.2" hover="function: integer Align(integer x, integer y)" conts="Align">integer <anchor link="impl-shared.Align.2" hover="function: integer Align(integer x, integer y)">Align</anchor>(integer x, integer y)</line>
<line>    return y * (x DIV y);</line>
<line></line>
<line>// Align()</line>
<line>// =======</line>
<line></line>
<line>bits(N) <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(bits(N) x, integer y)</line>
<line>    return <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(x), y)&lt;N-1:0&gt;;</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/BitCount" mylink="shared.functions.common.BitCount" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BitCount()</line>
<line>// ==========</line>
<line></line>
<line link="impl-shared.BitCount.1" hover="function: integer BitCount(bits(N) x)" conts="BitCount">integer <anchor link="impl-shared.BitCount.1" hover="function: integer BitCount(bits(N) x)">BitCount</anchor>(bits(N) x)</line>
<line>    integer result = 0;</line>
<line>    for i = 0 to N-1</line>
<line>        if x&lt;i&gt; == '1' then</line>
<line>            result = result + 1;</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/CountLeadingSignBits" mylink="shared.functions.common.CountLeadingSignBits" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CountLeadingSignBits()</line>
<line>// ======================</line>
<line></line>
<line link="impl-shared.CountLeadingSignBits.1" hover="function: integer CountLeadingSignBits(bits(N) x)" conts="CountLeadingSignBits">integer <anchor link="impl-shared.CountLeadingSignBits.1" hover="function: integer CountLeadingSignBits(bits(N) x)">CountLeadingSignBits</anchor>(bits(N) x)</line>
<line>    return <a link="impl-shared.CountLeadingZeroBits.1" file="shared_pseudocode.xml" hover="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</a>(x&lt;N-1:1&gt; EOR x&lt;N-2:0&gt;);</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/CountLeadingZeroBits" mylink="shared.functions.common.CountLeadingZeroBits" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CountLeadingZeroBits()</line>
<line>// ======================</line>
<line></line>
<line link="impl-shared.CountLeadingZeroBits.1" hover="function: integer CountLeadingZeroBits(bits(N) x)" conts="CountLeadingZeroBits">integer <anchor link="impl-shared.CountLeadingZeroBits.1" hover="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</anchor>(bits(N) x)</line>
<line>    return N - (<a link="impl-shared.HighestSetBit.1" file="shared_pseudocode.xml" hover="function: integer HighestSetBit(bits(N) x)">HighestSetBit</a>(x) + 1);</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/Elem" mylink="shared.functions.common.Elem" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Elem[] - non-assignment form</line>
<line>// ============================</line>
<line></line>
<line link="impl-shared.Elem.read.3" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]" conts="Elem">bits(size) <anchor link="impl-shared.Elem.read.3" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</anchor>[bits(N) vector, integer e, integer size]</line>
<line>    assert e &gt;= 0 &amp;&amp; (e+1)*size &lt;= N;</line>
<line>    return vector&lt;(e*size+size)-1 : e*size&gt;;</line>
<line></line>
<line>// Elem[] - assignment form</line>
<line>// ========================</line>
<line></line>
<line link="impl-shared.Elem.write.3" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value" conts="Elem"><anchor link="impl-shared.Elem.write.3" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</anchor>[bits(N) &amp;vector, integer e, integer size] = bits(size) value</line>
<line>    assert e &gt;= 0 &amp;&amp; (e+1)*size &lt;= N;</line>
<line>    vector&lt;(e+1)*size-1:e*size&gt; = value;</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/Extend" mylink="shared.functions.common.Extend" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Extend()</line>
<line>// ========</line>
<line></line>
<line link="impl-shared.Extend.3" hover="function: bits(N) Extend(bits(M) x, integer N, boolean unsigned)" conts="Extend">bits(N) <anchor link="impl-shared.Extend.3" hover="function: bits(N) Extend(bits(M) x, integer N, boolean unsigned)">Extend</anchor>(bits(M) x, integer N, boolean unsigned)</line>
<line>    return if unsigned then <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(x, N) else <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(x, N);</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/HighestSetBit" mylink="shared.functions.common.HighestSetBit" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HighestSetBit()</line>
<line>// ===============</line>
<line></line>
<line link="impl-shared.HighestSetBit.1" hover="function: integer HighestSetBit(bits(N) x)" conts="HighestSetBit">integer <anchor link="impl-shared.HighestSetBit.1" hover="function: integer HighestSetBit(bits(N) x)">HighestSetBit</anchor>(bits(N) x)</line>
<line>    for i = N-1 downto 0</line>
<line>        if x&lt;i&gt; == '1' then return i;</line>
<line>    return -1;</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/Int" mylink="shared.functions.common.Int" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Int()</line>
<line>// =====</line>
<line></line>
<line link="impl-shared.Int.2" hover="function: integer Int(bits(N) x, boolean unsigned)" conts="Int">integer <anchor link="impl-shared.Int.2" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</anchor>(bits(N) x, boolean unsigned)</line>
<line>    result = if unsigned then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(x) else <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(x);</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/IsAligned" mylink="shared.functions.common.IsAligned" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsAligned()</line>
<line>// ===========</line>
<line></line>
<line link="impl-shared.IsAligned.2" hover="function: boolean IsAligned(integer x, integer y)" conts="IsAligned">boolean <anchor link="impl-shared.IsAligned.2" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</anchor>(integer x, integer y)</line>
<line>    return x == <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(x, y);</line>
<line></line>
<line>// IsAligned()</line>
<line>// ===========</line>
<line></line>
<line>boolean <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(bits(N) x, integer y)</line>
<line>    return x == <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(x, y);</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/IsOnes" mylink="shared.functions.common.IsOnes" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsOnes()</line>
<line>// ========</line>
<line></line>
<line link="impl-shared.IsOnes.1" hover="function: boolean IsOnes(bits(N) x)" conts="IsOnes">boolean <anchor link="impl-shared.IsOnes.1" hover="function: boolean IsOnes(bits(N) x)">IsOnes</anchor>(bits(N) x)</line>
<line>    return x == <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(N);</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/IsZero" mylink="shared.functions.common.IsZero" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsZero()</line>
<line>// ========</line>
<line></line>
<line link="impl-shared.IsZero.1" hover="function: boolean IsZero(bits(N) x)" conts="IsZero">boolean <anchor link="impl-shared.IsZero.1" hover="function: boolean IsZero(bits(N) x)">IsZero</anchor>(bits(N) x)</line>
<line>    return x == <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(N);</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/IsZeroBit" mylink="shared.functions.common.IsZeroBit" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsZeroBit()</line>
<line>// ===========</line>
<line></line>
<line link="impl-shared.IsZeroBit.1" hover="function: bit IsZeroBit(bits(N) x)" conts="IsZeroBit">bit <anchor link="impl-shared.IsZeroBit.1" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</anchor>(bits(N) x)</line>
<line>    return if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(x) then '1' else '0';</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/LSL" mylink="shared.functions.common.LSL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// LSL()</line>
<line>// =====</line>
<line></line>
<line link="impl-shared.LSL.2" hover="function: bits(N) LSL(bits(N) x, integer shift)" conts="LSL">bits(N) <anchor link="impl-shared.LSL.2" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</anchor>(bits(N) x, integer shift)</line>
<line>    assert shift &gt;= 0;</line>
<line>    bits(N) result;</line>
<line>    if shift == 0 then</line>
<line>        result = x;</line>
<line>    else</line>
<line>        (result, -) = <a link="impl-shared.LSL_C.2" file="shared_pseudocode.xml" hover="function: (bits(N), bit) LSL_C(bits(N) x, integer shift)">LSL_C</a>(x, shift);</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/LSL_C" mylink="shared.functions.common.LSL_C" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// LSL_C()</line>
<line>// =======</line>
<line></line>
<line link="impl-shared.LSL_C.2" hover="function: (bits(N), bit) LSL_C(bits(N) x, integer shift)" conts="LSL_C">(bits(N), bit) <anchor link="impl-shared.LSL_C.2" hover="function: (bits(N), bit) LSL_C(bits(N) x, integer shift)">LSL_C</anchor>(bits(N) x, integer shift)</line>
<line>    assert shift &gt; 0 &amp;&amp; shift &lt; 256;</line>
<line>    extended_x = x : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(shift);</line>
<line>    result = extended_x&lt;N-1:0&gt;;</line>
<line>    carry_out = extended_x&lt;N&gt;;</line>
<line>    return (result, carry_out);</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/LSR" mylink="shared.functions.common.LSR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// LSR()</line>
<line>// =====</line>
<line></line>
<line link="impl-shared.LSR.2" hover="function: bits(N) LSR(bits(N) x, integer shift)" conts="LSR">bits(N) <anchor link="impl-shared.LSR.2" hover="function: bits(N) LSR(bits(N) x, integer shift)">LSR</anchor>(bits(N) x, integer shift)</line>
<line>    assert shift &gt;= 0;</line>
<line>    bits(N) result;</line>
<line>    if shift == 0 then</line>
<line>        result = x;</line>
<line>    else</line>
<line>        (result, -) = <a link="impl-shared.LSR_C.2" file="shared_pseudocode.xml" hover="function: (bits(N), bit) LSR_C(bits(N) x, integer shift)">LSR_C</a>(x, shift);</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/LSR_C" mylink="shared.functions.common.LSR_C" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// LSR_C()</line>
<line>// =======</line>
<line></line>
<line link="impl-shared.LSR_C.2" hover="function: (bits(N), bit) LSR_C(bits(N) x, integer shift)" conts="LSR_C">(bits(N), bit) <anchor link="impl-shared.LSR_C.2" hover="function: (bits(N), bit) LSR_C(bits(N) x, integer shift)">LSR_C</anchor>(bits(N) x, integer shift)</line>
<line>    assert shift &gt; 0 &amp;&amp; shift &lt; 256;</line>
<line>    extended_x = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(x, shift+N);</line>
<line>    result = extended_x&lt;(shift+N)-1:shift&gt;;</line>
<line>    carry_out = extended_x&lt;shift-1&gt;;</line>
<line>    return (result, carry_out);</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/LowestSetBit" mylink="shared.functions.common.LowestSetBit" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// LowestSetBit()</line>
<line>// ==============</line>
<line></line>
<line link="impl-shared.LowestSetBit.1" hover="function: integer LowestSetBit(bits(N) x)" conts="LowestSetBit">integer <anchor link="impl-shared.LowestSetBit.1" hover="function: integer LowestSetBit(bits(N) x)">LowestSetBit</anchor>(bits(N) x)</line>
<line>    for i = 0 to N-1</line>
<line>        if x&lt;i&gt; == '1' then return i;</line>
<line>    return N;</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/Max" mylink="shared.functions.common.Max" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Max()</line>
<line>// =====</line>
<line></line>
<line link="impl-shared.Max.2" hover="function: integer Max(integer a, integer b)" conts="Max">integer <anchor link="impl-shared.Max.2" hover="function: integer Max(integer a, integer b)">Max</anchor>(integer a, integer b)</line>
<line>    return if a &gt;= b then a else b;</line>
<line></line>
<line>// Max()</line>
<line>// =====</line>
<line></line>
<line>real <a link="impl-shared.Max.2" file="shared_pseudocode.xml" hover="function: integer Max(integer a, integer b)">Max</a>(real a, real b)</line>
<line>    return if a &gt;= b then a else b;</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/Min" mylink="shared.functions.common.Min" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Min()</line>
<line>// =====</line>
<line></line>
<line link="impl-shared.Min.2" hover="function: integer Min(integer a, integer b)" conts="Min">integer <anchor link="impl-shared.Min.2" hover="function: integer Min(integer a, integer b)">Min</anchor>(integer a, integer b)</line>
<line>    return if a &lt;= b then a else b;</line>
<line></line>
<line>// Min()</line>
<line>// =====</line>
<line></line>
<line>real <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(real a, real b)</line>
<line>    return if a &lt;= b then a else b;</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/Ones" mylink="shared.functions.common.Ones" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Ones()</line>
<line>// ======</line>
<line></line>
<line link="impl-shared.Ones.1" hover="function: bits(N) Ones(integer N)" conts="Ones">bits(N) <anchor link="impl-shared.Ones.1" hover="function: bits(N) Ones(integer N)">Ones</anchor>(integer N)</line>
<line>    return <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>('1',N);</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/ROR" mylink="shared.functions.common.ROR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ROR()</line>
<line>// =====</line>
<line></line>
<line link="impl-shared.ROR.2" hover="function: bits(N) ROR(bits(N) x, integer shift)" conts="ROR">bits(N) <anchor link="impl-shared.ROR.2" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</anchor>(bits(N) x, integer shift)</line>
<line>    assert shift &gt;= 0;</line>
<line>    bits(N) result;</line>
<line>    if shift == 0 then</line>
<line>        result = x;</line>
<line>    else</line>
<line>        (result, -) = <a link="impl-shared.ROR_C.2" file="shared_pseudocode.xml" hover="function: (bits(N), bit) ROR_C(bits(N) x, integer shift)">ROR_C</a>(x, shift);</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/ROR_C" mylink="shared.functions.common.ROR_C" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ROR_C()</line>
<line>// =======</line>
<line></line>
<line link="impl-shared.ROR_C.2" hover="function: (bits(N), bit) ROR_C(bits(N) x, integer shift)" conts="ROR_C">(bits(N), bit) <anchor link="impl-shared.ROR_C.2" hover="function: (bits(N), bit) ROR_C(bits(N) x, integer shift)">ROR_C</anchor>(bits(N) x, integer shift)</line>
<line>    assert shift != 0 &amp;&amp; shift &lt; 256;</line>
<line>    m = shift MOD N;</line>
<line>    result = <a link="impl-shared.LSR.2" file="shared_pseudocode.xml" hover="function: bits(N) LSR(bits(N) x, integer shift)">LSR</a>(x,m) OR <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(x,N-m);</line>
<line>    carry_out = result&lt;N-1&gt;;</line>
<line>    return (result, carry_out);</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/Replicate" mylink="shared.functions.common.Replicate" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Replicate()</line>
<line>// ===========</line>
<line></line>
<line link="impl-shared.Replicate.2" hover="function: bits(M*N) Replicate(bits(M) x, integer N)" conts="Replicate">bits(M*N) <anchor link="impl-shared.Replicate.2" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</anchor>(bits(M) x, integer N);</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/RoundDown" mylink="shared.functions.common.RoundDown" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// RoundDown()</line>
<line>// ===========</line>
<line></line>
<line link="impl-shared.RoundDown.1" hover="function: integer RoundDown(real x)" conts="RoundDown">integer <anchor link="impl-shared.RoundDown.1" hover="function: integer RoundDown(real x)">RoundDown</anchor>(real x);</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/RoundTowardsZero" mylink="shared.functions.common.RoundTowardsZero" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// RoundTowardsZero()</line>
<line>// ==================</line>
<line></line>
<line link="impl-shared.RoundTowardsZero.1" hover="function: integer RoundTowardsZero(real x)" conts="RoundTowardsZero">integer <anchor link="impl-shared.RoundTowardsZero.1" hover="function: integer RoundTowardsZero(real x)">RoundTowardsZero</anchor>(real x)</line>
<line>    return if x == 0.0 then 0 else if x &gt;= 0.0 then <a link="impl-shared.RoundDown.1" file="shared_pseudocode.xml" hover="function: integer RoundDown(real x)">RoundDown</a>(x) else <a link="impl-shared.RoundUp.1" file="shared_pseudocode.xml" hover="function: integer RoundUp(real x)">RoundUp</a>(x);</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/RoundUp" mylink="shared.functions.common.RoundUp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// RoundUp()</line>
<line>// =========</line>
<line></line>
<line link="impl-shared.RoundUp.1" hover="function: integer RoundUp(real x)" conts="RoundUp">integer <anchor link="impl-shared.RoundUp.1" hover="function: integer RoundUp(real x)">RoundUp</anchor>(real x);</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/SInt" mylink="shared.functions.common.SInt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SInt()</line>
<line>// ======</line>
<line></line>
<line link="impl-shared.SInt.1" hover="function: integer SInt(bits(N) x)" conts="SInt">integer <anchor link="impl-shared.SInt.1" hover="function: integer SInt(bits(N) x)">SInt</anchor>(bits(N) x)</line>
<line>    result = 0;</line>
<line>    for i = 0 to N-1</line>
<line>        if x&lt;i&gt; == '1' then result = result + 2^i;</line>
<line>    if x&lt;N-1&gt; == '1' then result = result - 2^N;</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/SignExtend" mylink="shared.functions.common.SignExtend" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SignExtend()</line>
<line>// ============</line>
<line></line>
<line link="impl-shared.SignExtend.2" hover="function: bits(N) SignExtend(bits(M) x, integer N)" conts="SignExtend">bits(N) <anchor link="impl-shared.SignExtend.2" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</anchor>(bits(M) x, integer N)</line>
<line>    assert N &gt;= M;</line>
<line>    return <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(x&lt;M-1&gt;, N-M) : x;</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/Split64to32" mylink="shared.functions.common.Split64to32" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Split64to32()</line>
<line>// =============</line>
<line></line>
<line link="impl-shared.Split64to32.1" hover="function: (bits(32), bits(32)) Split64to32(bits(64) value)" conts="Split64to32">(bits(32), bits(32)) <anchor link="impl-shared.Split64to32.1" hover="function: (bits(32), bits(32)) Split64to32(bits(64) value)">Split64to32</anchor>(bits(64) value)</line>
<line>    return (value&lt;63:32&gt;, value&lt;31:0&gt;);</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/UInt" mylink="shared.functions.common.UInt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// UInt()</line>
<line>// ======</line>
<line></line>
<line link="impl-shared.UInt.1" hover="function: integer UInt(bits(N) x)" conts="UInt">integer <anchor link="impl-shared.UInt.1" hover="function: integer UInt(bits(N) x)">UInt</anchor>(bits(N) x)</line>
<line>    result = 0;</line>
<line>    for i = 0 to N-1</line>
<line>        if x&lt;i&gt; == '1' then result = result + 2^i;</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/ZeroExtend" mylink="shared.functions.common.ZeroExtend" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ZeroExtend()</line>
<line>// ============</line>
<line></line>
<line link="impl-shared.ZeroExtend.2" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)" conts="ZeroExtend">bits(N) <anchor link="impl-shared.ZeroExtend.2" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</anchor>(bits(M) x, integer N)</line>
<line>    assert N &gt;= M;</line>
<line>    return <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(N-M) : x;</line>
</pstext>
    </ps>
    <ps name="shared/functions/common/Zeros" mylink="shared.functions.common.Zeros" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Zeros()</line>
<line>// =======</line>
<line></line>
<line link="impl-shared.Zeros.1" hover="function: bits(N) Zeros(integer N)" conts="Zeros">bits(N) <anchor link="impl-shared.Zeros.1" hover="function: bits(N) Zeros(integer N)">Zeros</anchor>(integer N)</line>
<line>    return <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>('0',N);</line>
</pstext>
    </ps>
    <ps name="shared/functions/counters/AArch32.CheckTimerConditions" mylink="shared.functions.counters.AArch32.CheckTimerConditions" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.CheckTimerConditions()</line>
<line>// ==============================</line>
<line>// Checking timer conditions for all A32 timer registers</line>
<line></line>
<line link="AArch32.CheckTimerConditions.0" hover="function: AArch32.CheckTimerConditions()" conts="AArch32.CheckTimerConditions"><anchor link="AArch32.CheckTimerConditions.0" hover="function: AArch32.CheckTimerConditions()">AArch32.CheckTimerConditions</anchor>()</line>
<line>    boolean status;</line>
<line>    bits(64) offset;</line>
<line>    offset = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>    assert !<a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>();</line>
<line></line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        if CNTP_CTL_S.ENABLE == '1' then</line>
<line>            status = <a link="impl-shared.IsTimerConditionMet.4" file="shared_pseudocode.xml" hover="function: boolean IsTimerConditionMet(bits(64) offset, bits(64) compare_value, bits(1) imask, InterruptID intid)">IsTimerConditionMet</a>(offset, CNTP_CVAL_S,</line>
<line>                                         CNTP_CTL_S.IMASK, <a link="InterruptID_CNTPS" file="shared_pseudocode.xml" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_CNTPS</a>);</line>
<line>            CNTP_CTL_S.ISTATUS = if status then '1' else '0';</line>
<line></line>
<line>        if CNTP_CTL_NS.ENABLE == '1' then</line>
<line>            status = <a link="impl-shared.IsTimerConditionMet.4" file="shared_pseudocode.xml" hover="function: boolean IsTimerConditionMet(bits(64) offset, bits(64) compare_value, bits(1) imask, InterruptID intid)">IsTimerConditionMet</a>(offset, CNTP_CVAL_NS,</line>
<line>                                         CNTP_CTL_NS.IMASK, <a link="InterruptID_CNTP" file="shared_pseudocode.xml" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_CNTP</a>);</line>
<line>            CNTP_CTL_NS.ISTATUS = if status then '1' else '0';</line>
<line>    else</line>
<line>        if CNTP_CTL.ENABLE == '1' then</line>
<line>            status = <a link="impl-shared.IsTimerConditionMet.4" file="shared_pseudocode.xml" hover="function: boolean IsTimerConditionMet(bits(64) offset, bits(64) compare_value, bits(1) imask, InterruptID intid)">IsTimerConditionMet</a>(offset, CNTP_CVAL,</line>
<line>                                         CNTP_CTL.IMASK, <a link="InterruptID_CNTP" file="shared_pseudocode.xml" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_CNTP</a>);</line>
<line>            CNTP_CTL.ISTATUS = if status then '1' else '0';</line>
<line></line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; CNTHP_CTL.ENABLE == '1' then</line>
<line>        status = <a link="impl-shared.IsTimerConditionMet.4" file="shared_pseudocode.xml" hover="function: boolean IsTimerConditionMet(bits(64) offset, bits(64) compare_value, bits(1) imask, InterruptID intid)">IsTimerConditionMet</a>(offset, CNTHP_CVAL,</line>
<line>                                     CNTHP_CTL.IMASK, <a link="InterruptID_CNTHP" file="shared_pseudocode.xml" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_CNTHP</a>);</line>
<line>        CNTHP_CTL.ISTATUS = if status then '1' else '0';</line>
<line></line>
<line>    if CNTV_CTL_EL0.ENABLE == '1' then</line>
<line>        status = <a link="impl-shared.IsTimerConditionMet.4" file="shared_pseudocode.xml" hover="function: boolean IsTimerConditionMet(bits(64) offset, bits(64) compare_value, bits(1) imask, InterruptID intid)">IsTimerConditionMet</a>(CNTVOFF_EL2, CNTV_CVAL_EL0,</line>
<line>                                     CNTV_CTL_EL0.IMASK, <a link="InterruptID_CNTV" file="shared_pseudocode.xml" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_CNTV</a>);</line>
<line>        CNTV_CTL_EL0.ISTATUS = if status then '1' else '0';</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/functions/counters/AArch64.CheckTimerConditions" mylink="shared.functions.counters.AArch64.CheckTimerConditions" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.CheckTimerConditions()</line>
<line>// ==============================</line>
<line>// Checking timer conditions for all A64 timer registers</line>
<line></line>
<line link="AArch64.CheckTimerConditions.0" hover="function: AArch64.CheckTimerConditions()" conts="AArch64.CheckTimerConditions"><anchor link="AArch64.CheckTimerConditions.0" hover="function: AArch64.CheckTimerConditions()">AArch64.CheckTimerConditions</anchor>()</line>
<line>    boolean status;</line>
<line>    bits(64) offset;</line>
<line>    bit imask;</line>
<line>    <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss = <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>();</line>
<line>    boolean ecv = FALSE;</line>
<line>    if <a link="impl-shared.HaveECVExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveECVExt()">HaveECVExt</a>() then</line>
<line>        ecv = CNTHCTL_EL2.ECV == '1' &amp;&amp; SCR_EL3.ECVEn == '1' &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>();</line>
<line>    if ecv then</line>
<line>        offset = CNTPOFF_EL2;</line>
<line>    else</line>
<line>        offset = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>    if CNTP_CTL_EL0.ENABLE == '1' then</line>
<line>        imask = CNTP_CTL_EL0.IMASK;</line>
<line>        if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() &amp;&amp; ss IN {<a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>, <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>} &amp;&amp; CNTHCTL_EL2.CNTPMASK == '1' then</line>
<line>            imask = '1';</line>
<line>        status = <a link="impl-shared.IsTimerConditionMet.4" file="shared_pseudocode.xml" hover="function: boolean IsTimerConditionMet(bits(64) offset, bits(64) compare_value, bits(1) imask, InterruptID intid)">IsTimerConditionMet</a>(offset, CNTP_CVAL_EL0,</line>
<line>                                     imask, <a link="InterruptID_CNTP" file="shared_pseudocode.xml" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_CNTP</a>);</line>
<line>        CNTP_CTL_EL0.ISTATUS = if status then '1' else '0';</line>
<line>    if ((<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) || (<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; !<a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>())) &amp;&amp;</line>
<line>       CNTHP_CTL_EL2.ENABLE == '1') then</line>
<line>        status = <a link="impl-shared.IsTimerConditionMet.4" file="shared_pseudocode.xml" hover="function: boolean IsTimerConditionMet(bits(64) offset, bits(64) compare_value, bits(1) imask, InterruptID intid)">IsTimerConditionMet</a>(<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64), CNTHP_CVAL_EL2,</line>
<line>                                     CNTHP_CTL_EL2.IMASK, <a link="InterruptID_CNTHP" file="shared_pseudocode.xml" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_CNTHP</a>);</line>
<line>        CNTHP_CTL_EL2.ISTATUS = if status then '1' else '0';</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; <a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>() &amp;&amp; CNTHPS_CTL_EL2.ENABLE == '1' then</line>
<line>        status = <a link="impl-shared.IsTimerConditionMet.4" file="shared_pseudocode.xml" hover="function: boolean IsTimerConditionMet(bits(64) offset, bits(64) compare_value, bits(1) imask, InterruptID intid)">IsTimerConditionMet</a>(<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64), CNTHPS_CVAL_EL2,</line>
<line>                                     CNTHPS_CTL_EL2.IMASK, <a link="InterruptID_CNTHPS" file="shared_pseudocode.xml" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_CNTHPS</a>);</line>
<line>        CNTHPS_CTL_EL2.ISTATUS = if status then '1' else '0';</line>
<line></line>
<line>    if CNTPS_CTL_EL1.ENABLE == '1' then</line>
<line>        status = <a link="impl-shared.IsTimerConditionMet.4" file="shared_pseudocode.xml" hover="function: boolean IsTimerConditionMet(bits(64) offset, bits(64) compare_value, bits(1) imask, InterruptID intid)">IsTimerConditionMet</a>(offset, CNTPS_CVAL_EL1,</line>
<line>                                     CNTPS_CTL_EL1.IMASK, <a link="InterruptID_CNTPS" file="shared_pseudocode.xml" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_CNTPS</a>);</line>
<line>        CNTPS_CTL_EL1.ISTATUS = if status then '1' else '0';</line>
<line></line>
<line>    if CNTV_CTL_EL0.ENABLE == '1' then</line>
<line>        imask = CNTV_CTL_EL0.IMASK;</line>
<line>        if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() &amp;&amp; ss IN {<a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>, <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>} &amp;&amp; CNTHCTL_EL2.CNTVMASK == '1' then</line>
<line>            imask = '1';</line>
<line>        status = <a link="impl-shared.IsTimerConditionMet.4" file="shared_pseudocode.xml" hover="function: boolean IsTimerConditionMet(bits(64) offset, bits(64) compare_value, bits(1) imask, InterruptID intid)">IsTimerConditionMet</a>(CNTVOFF_EL2, CNTV_CVAL_EL0,</line>
<line>                                     imask, <a link="InterruptID_CNTV" file="shared_pseudocode.xml" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_CNTV</a>);</line>
<line>        CNTV_CTL_EL0.ISTATUS = if status then '1' else '0';</line>
<line></line>
<line>    if ((<a link="impl-shared.HaveVirtHostExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</a>() &amp;&amp; (<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) || !<a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>())) &amp;&amp;</line>
<line>        CNTHV_CTL_EL2.ENABLE == '1') then</line>
<line>        status = <a link="impl-shared.IsTimerConditionMet.4" file="shared_pseudocode.xml" hover="function: boolean IsTimerConditionMet(bits(64) offset, bits(64) compare_value, bits(1) imask, InterruptID intid)">IsTimerConditionMet</a>(<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64), CNTHV_CVAL_EL2,</line>
<line>                                     CNTHV_CTL_EL2.IMASK, <a link="InterruptID_CNTHV" file="shared_pseudocode.xml" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_CNTHV</a>);</line>
<line>        CNTHV_CTL_EL2.ISTATUS = if status then '1' else '0';</line>
<line></line>
<line>    if ((<a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>() &amp;&amp; <a link="impl-shared.HaveVirtHostExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</a>()) &amp;&amp;</line>
<line>        CNTHVS_CTL_EL2.ENABLE == '1') then</line>
<line>        status = <a link="impl-shared.IsTimerConditionMet.4" file="shared_pseudocode.xml" hover="function: boolean IsTimerConditionMet(bits(64) offset, bits(64) compare_value, bits(1) imask, InterruptID intid)">IsTimerConditionMet</a>(<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64), CNTHVS_CVAL_EL2,</line>
<line>                                     CNTHVS_CTL_EL2.IMASK, <a link="InterruptID_CNTHVS" file="shared_pseudocode.xml" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_CNTHVS</a>);</line>
<line>        CNTHVS_CTL_EL2.ISTATUS = if status then '1' else '0';</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/functions/counters/GenericCounterTick" mylink="shared.functions.counters.GenericCounterTick" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GenericCounterTick()</line>
<line>// ====================</line>
<line>// Increments PhysicalCount value for every clock tick.</line>
<line></line>
<line link="impl-shared.GenericCounterTick.0" hover="function: GenericCounterTick()" conts="GenericCounterTick"><anchor link="impl-shared.GenericCounterTick.0" hover="function: GenericCounterTick()">GenericCounterTick</anchor>()</line>
<line>    bits(64) prev_physical_count;</line>
<line>    if CNTCR.EN == '0' then</line>
<line>        if !<a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then</line>
<line>            <a link="AArch32.CheckTimerConditions.0" file="shared_pseudocode.xml" hover="function: AArch32.CheckTimerConditions()">AArch32.CheckTimerConditions</a>();</line>
<line>        else</line>
<line>            <a link="AArch64.CheckTimerConditions.0" file="shared_pseudocode.xml" hover="function: AArch64.CheckTimerConditions()">AArch64.CheckTimerConditions</a>();</line>
<line>        return;</line>
<line>    prev_physical_count = <a link="impl-shared.PhysicalCountInt.0" file="shared_pseudocode.xml" hover="function: bits(64) PhysicalCountInt()">PhysicalCountInt</a>();</line>
<line>    if <a link="impl-shared.HaveCNTSCExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveCNTSCExt()">HaveCNTSCExt</a>() &amp;&amp; CNTCR.SCEN == '1' then</line>
<line>        PhysicalCount = PhysicalCount + <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(CNTSCR, 88);</line>
<line>    else</line>
<line>        PhysicalCount&lt;87:24&gt; = PhysicalCount&lt;87:24&gt; + 1;</line>
<line>    if !<a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then</line>
<line>        <a link="AArch32.CheckTimerConditions.0" file="shared_pseudocode.xml" hover="function: AArch32.CheckTimerConditions()">AArch32.CheckTimerConditions</a>();</line>
<line>    else</line>
<line>        <a link="AArch64.CheckTimerConditions.0" file="shared_pseudocode.xml" hover="function: AArch64.CheckTimerConditions()">AArch64.CheckTimerConditions</a>();</line>
<line>    <a link="impl-shared.TestEventCNTP.2" file="shared_pseudocode.xml" hover="function: TestEventCNTP(bits(64) prev_physical_count, bits(64) current_physical_count)">TestEventCNTP</a>(prev_physical_count, <a link="impl-shared.PhysicalCountInt.0" file="shared_pseudocode.xml" hover="function: bits(64) PhysicalCountInt()">PhysicalCountInt</a>());</line>
<line>    <a link="impl-shared.TestEventCNTV.2" file="shared_pseudocode.xml" hover="function: TestEventCNTV(bits(64) prev_physical_count, bits(64) current_physical_count)">TestEventCNTV</a>(prev_physical_count, <a link="impl-shared.PhysicalCountInt.0" file="shared_pseudocode.xml" hover="function: bits(64) PhysicalCountInt()">PhysicalCountInt</a>());</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/functions/counters/IsTimerConditionMet" mylink="shared.functions.counters.IsTimerConditionMet" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsTimerConditionMet()</line>
<line>// =====================</line>
<line></line>
<line link="impl-shared.IsTimerConditionMet.4" hover="function: boolean IsTimerConditionMet(bits(64) offset, bits(64) compare_value, bits(1) imask, InterruptID intid)" conts="IsTimerConditionMet">boolean <anchor link="impl-shared.IsTimerConditionMet.4" hover="function: boolean IsTimerConditionMet(bits(64) offset, bits(64) compare_value, bits(1) imask, InterruptID intid)">IsTimerConditionMet</anchor>(bits(64) offset, bits(64) compare_value,</line>
<line>                            bits(1) imask, <a link="InterruptID" file="shared_pseudocode.xml" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID</a> intid)</line>
<line>    boolean conditon_met;</line>
<line>    signal level;</line>
<line>    condition_met = (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.PhysicalCountInt.0" file="shared_pseudocode.xml" hover="function: bits(64) PhysicalCountInt()">PhysicalCountInt</a>() - offset) -</line>
<line>                                        <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(compare_value)) &gt;= 0;</line>
<line>    level = if condition_met &amp;&amp; imask == '0' then HIGH else LOW;</line>
<line>    SetInterruptRequestLevel(intid, level);</line>
<line>    return condition_met;</line>
</pstext>
    </ps>
    <ps name="shared/functions/counters/PhysicalCount" mylink="shared.functions.counters.PhysicalCount" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>bits(88) PhysicalCount;</line>
</pstext>
    </ps>
    <ps name="shared/functions/counters/SetEventRegister" mylink="shared.functions.counters.SetEventRegister" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SetEventRegister()</line>
<line>// ==================</line>
<line>// Sets the Event Register of this PE</line>
<line></line>
<line link="impl-shared.SetEventRegister.0" hover="function: SetEventRegister()" conts="SetEventRegister"><anchor link="impl-shared.SetEventRegister.0" hover="function: SetEventRegister()">SetEventRegister</anchor>()</line>
<line>    EventRegister = '1';</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/functions/counters/TestEventCNTP" mylink="shared.functions.counters.TestEventCNTP" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TestEventCNTP()</line>
<line>// ===============</line>
<line>// Generate Event stream from the physical counter</line>
<line></line>
<line link="impl-shared.TestEventCNTP.2" hover="function: TestEventCNTP(bits(64) prev_physical_count, bits(64) current_physical_count)" conts="TestEventCNTP"><anchor link="impl-shared.TestEventCNTP.2" hover="function: TestEventCNTP(bits(64) prev_physical_count, bits(64) current_physical_count)">TestEventCNTP</anchor>(bits(64) prev_physical_count, bits(64) current_physical_count)</line>
<line>    bits(64) offset;</line>
<line>    bits(1) samplebit, previousbit;</line>
<line>    if CNTHCTL_EL2.EVNTEN == '1' then</line>
<line>        n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(CNTHCTL_EL2.EVNTI);</line>
<line>        if <a link="impl-shared.HaveECVExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveECVExt()">HaveECVExt</a>() &amp;&amp; CNTHCTL_EL2.EVNTIS == '1' then</line>
<line>            n = n + 8;</line>
<line>        boolean ecv = FALSE;</line>
<line>        if <a link="impl-shared.HaveECVExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveECVExt()">HaveECVExt</a>() then</line>
<line>            ecv = (<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; CNTHCTL_EL2.ECV == '1' &amp;&amp;</line>
<line>                   SCR_EL3.ECVEn == '1');</line>
<line>            offset = if ecv then CNTPOFF_EL2 else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>        samplebit   = (current_physical_count - offset)&lt;n&gt;;</line>
<line>        previousbit = (prev_physical_count - offset)&lt;n&gt;;</line>
<line>        if CNTHCTL_EL2.EVNTDIR == '0' then</line>
<line>            if previousbit == '0' &amp;&amp; samplebit == '1' then <a link="impl-shared.SetEventRegister.0" file="shared_pseudocode.xml" hover="function: SetEventRegister()">SetEventRegister</a>();</line>
<line>        else</line>
<line>            if previousbit == '1' &amp;&amp; samplebit == '0' then <a link="impl-shared.SetEventRegister.0" file="shared_pseudocode.xml" hover="function: SetEventRegister()">SetEventRegister</a>();</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/functions/counters/TestEventCNTV" mylink="shared.functions.counters.TestEventCNTV" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TestEventCNTV()</line>
<line>// ===============</line>
<line>// Generate Event stream from the virtual counter</line>
<line></line>
<line link="impl-shared.TestEventCNTV.2" hover="function: TestEventCNTV(bits(64) prev_physical_count, bits(64) current_physical_count)" conts="TestEventCNTV"><anchor link="impl-shared.TestEventCNTV.2" hover="function: TestEventCNTV(bits(64) prev_physical_count, bits(64) current_physical_count)">TestEventCNTV</anchor>(bits(64) prev_physical_count, bits(64) current_physical_count)</line>
<line>    bits(64) offset;</line>
<line>    bits(1) samplebit, previousbit;</line>
<line>    if (!(<a link="impl-shared.HaveVirtHostExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</a>() &amp;&amp; HCR_EL2.&lt;E2H,TGE&gt; == '11') &amp;&amp;</line>
<line>        CNTKCTL_EL1.EVNTEN == '1') then</line>
<line>        n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(CNTKCTL_EL1.EVNTI);</line>
<line>        if <a link="impl-shared.HaveECVExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveECVExt()">HaveECVExt</a>() &amp;&amp; CNTKCTL_EL1.EVNTIS == '1' then</line>
<line>            n = n + 8;</line>
<line>        if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; (!<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() || HCR_EL2.&lt;E2H,TGE&gt; != '11') then</line>
<line>            offset = CNTVOFF_EL2;</line>
<line>        else</line>
<line>            offset = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>        samplebit   = (current_physical_count - offset)&lt;n&gt;;</line>
<line>        previousbit = (prev_physical_count - offset)&lt;n&gt;;</line>
<line>        if CNTKCTL_EL1.EVNTDIR == '0' then</line>
<line>            if previousbit == '0' &amp;&amp; samplebit == '1' then <a link="impl-shared.SetEventRegister.0" file="shared_pseudocode.xml" hover="function: SetEventRegister()">SetEventRegister</a>();</line>
<line>        else</line>
<line>            if previousbit == '1' &amp;&amp; samplebit == '0' then <a link="impl-shared.SetEventRegister.0" file="shared_pseudocode.xml" hover="function: SetEventRegister()">SetEventRegister</a>();</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/functions/crc/BitReverse" mylink="shared.functions.crc.BitReverse" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BitReverse()</line>
<line>// ============</line>
<line></line>
<line link="impl-shared.BitReverse.1" hover="function: bits(N) BitReverse(bits(N) data)" conts="BitReverse">bits(N) <anchor link="impl-shared.BitReverse.1" hover="function: bits(N) BitReverse(bits(N) data)">BitReverse</anchor>(bits(N) data)</line>
<line>    bits(N) result;</line>
<line>    for i = 0 to N-1</line>
<line>        result&lt;(N-i)-1&gt; = data&lt;i&gt;;</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/crc/HaveCRCExt" mylink="shared.functions.crc.HaveCRCExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveCRCExt()</line>
<line>// ============</line>
<line></line>
<line link="impl-shared.HaveCRCExt.0" hover="function: boolean HaveCRCExt()" conts="HaveCRCExt">boolean <anchor link="impl-shared.HaveCRCExt.0" hover="function: boolean HaveCRCExt()">HaveCRCExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_CRC32);</line>
</pstext>
    </ps>
    <ps name="shared/functions/crc/Poly32Mod2" mylink="shared.functions.crc.Poly32Mod2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Poly32Mod2()</line>
<line>// ============</line>
<line></line>
<line>// Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation</line>
<line></line>
<line link="impl-shared.Poly32Mod2.2" hover="function: bits(32) Poly32Mod2(bits(N) data_in, bits(32) poly)" conts="Poly32Mod2">bits(32) <anchor link="impl-shared.Poly32Mod2.2" hover="function: bits(32) Poly32Mod2(bits(N) data_in, bits(32) poly)">Poly32Mod2</anchor>(bits(N) data_in, bits(32) poly)</line>
<line>    assert N &gt; 32;</line>
<line>    bits(N) data = data_in;</line>
<line>    for i = N-1 downto 32</line>
<line>        if data&lt;i&gt; == '1' then</line>
<line>            data&lt;i-1:0&gt; = data&lt;i-1:0&gt; EOR (poly:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(i-32));</line>
<line>    return data&lt;31:0&gt;;</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/AESInvMixColumns" mylink="shared.functions.crypto.AESInvMixColumns" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AESInvMixColumns()</line>
<line>// ==================</line>
<line>// Transformation in the Inverse Cipher that is the inverse of AESMixColumns.</line>
<line></line>
<line link="impl-shared.AESInvMixColumns.1" hover="function: bits(128) AESInvMixColumns(bits (128) op)" conts="AESInvMixColumns">bits(128) <anchor link="impl-shared.AESInvMixColumns.1" hover="function: bits(128) AESInvMixColumns(bits (128) op)">AESInvMixColumns</anchor>(bits (128) op)</line>
<line>    bits(4*8) in0 = op&lt; 96+:8&gt; : op&lt; 64+:8&gt; : op&lt; 32+:8&gt; : op&lt;  0+:8&gt;;</line>
<line>    bits(4*8) in1 = op&lt;104+:8&gt; : op&lt; 72+:8&gt; : op&lt; 40+:8&gt; : op&lt;  8+:8&gt;;</line>
<line>    bits(4*8) in2 = op&lt;112+:8&gt; : op&lt; 80+:8&gt; : op&lt; 48+:8&gt; : op&lt; 16+:8&gt;;</line>
<line>    bits(4*8) in3 = op&lt;120+:8&gt; : op&lt; 88+:8&gt; : op&lt; 56+:8&gt; : op&lt; 24+:8&gt;;</line>
<line></line>
<line>    bits(4*8) out0;</line>
<line>    bits(4*8) out1;</line>
<line>    bits(4*8) out2;</line>
<line>    bits(4*8) out3;</line>
<line></line>
<line>    for c = 0 to 3</line>
<line>        out0&lt;c*8+:8&gt; =  (<a link="impl-shared.FFmul0E.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul0E(bits(8) b)">FFmul0E</a>(in0&lt;c*8+:8&gt;) EOR <a link="impl-shared.FFmul0B.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul0B(bits(8) b)">FFmul0B</a>(in1&lt;c*8+:8&gt;) EOR <a link="impl-shared.FFmul0D.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul0D(bits(8) b)">FFmul0D</a>(in2&lt;c*8+:8&gt;) EOR</line>
<line>                         <a link="impl-shared.FFmul09.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul09(bits(8) b)">FFmul09</a>(in3&lt;c*8+:8&gt;));</line>
<line>        out1&lt;c*8+:8&gt; =  (<a link="impl-shared.FFmul09.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul09(bits(8) b)">FFmul09</a>(in0&lt;c*8+:8&gt;) EOR <a link="impl-shared.FFmul0E.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul0E(bits(8) b)">FFmul0E</a>(in1&lt;c*8+:8&gt;) EOR <a link="impl-shared.FFmul0B.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul0B(bits(8) b)">FFmul0B</a>(in2&lt;c*8+:8&gt;) EOR</line>
<line>                         <a link="impl-shared.FFmul0D.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul0D(bits(8) b)">FFmul0D</a>(in3&lt;c*8+:8&gt;));</line>
<line>        out2&lt;c*8+:8&gt; =  (<a link="impl-shared.FFmul0D.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul0D(bits(8) b)">FFmul0D</a>(in0&lt;c*8+:8&gt;) EOR <a link="impl-shared.FFmul09.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul09(bits(8) b)">FFmul09</a>(in1&lt;c*8+:8&gt;) EOR <a link="impl-shared.FFmul0E.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul0E(bits(8) b)">FFmul0E</a>(in2&lt;c*8+:8&gt;) EOR</line>
<line>                         <a link="impl-shared.FFmul0B.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul0B(bits(8) b)">FFmul0B</a>(in3&lt;c*8+:8&gt;));</line>
<line>        out3&lt;c*8+:8&gt; =  (<a link="impl-shared.FFmul0B.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul0B(bits(8) b)">FFmul0B</a>(in0&lt;c*8+:8&gt;) EOR <a link="impl-shared.FFmul0D.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul0D(bits(8) b)">FFmul0D</a>(in1&lt;c*8+:8&gt;) EOR <a link="impl-shared.FFmul09.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul09(bits(8) b)">FFmul09</a>(in2&lt;c*8+:8&gt;) EOR</line>
<line>                         <a link="impl-shared.FFmul0E.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul0E(bits(8) b)">FFmul0E</a>(in3&lt;c*8+:8&gt;));</line>
<line></line>
<line>    return (</line>
<line>        out3&lt;3*8+:8&gt; : out2&lt;3*8+:8&gt; : out1&lt;3*8+:8&gt; : out0&lt;3*8+:8&gt; :</line>
<line>        out3&lt;2*8+:8&gt; : out2&lt;2*8+:8&gt; : out1&lt;2*8+:8&gt; : out0&lt;2*8+:8&gt; :</line>
<line>        out3&lt;1*8+:8&gt; : out2&lt;1*8+:8&gt; : out1&lt;1*8+:8&gt; : out0&lt;1*8+:8&gt; :</line>
<line>        out3&lt;0*8+:8&gt; : out2&lt;0*8+:8&gt; : out1&lt;0*8+:8&gt; : out0&lt;0*8+:8&gt;</line>
<line>    );</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/AESInvShiftRows" mylink="shared.functions.crypto.AESInvShiftRows" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AESInvShiftRows()</line>
<line>// =================</line>
<line>// Transformation in the Inverse Cipher that is inverse of AESShiftRows.</line>
<line></line>
<line link="impl-shared.AESInvShiftRows.1" hover="function: bits(128) AESInvShiftRows(bits(128) op)" conts="AESInvShiftRows">bits(128) <anchor link="impl-shared.AESInvShiftRows.1" hover="function: bits(128) AESInvShiftRows(bits(128) op)">AESInvShiftRows</anchor>(bits(128) op)</line>
<line>    return (</line>
<line>        op&lt; 31: 24&gt; : op&lt; 55: 48&gt; : op&lt; 79: 72&gt; : op&lt;103: 96&gt; :</line>
<line>        op&lt;127:120&gt; : op&lt; 23: 16&gt; : op&lt; 47: 40&gt; : op&lt; 71: 64&gt; :</line>
<line>        op&lt; 95: 88&gt; : op&lt;119:112&gt; : op&lt; 15:  8&gt; : op&lt; 39: 32&gt; :</line>
<line>        op&lt; 63: 56&gt; : op&lt; 87: 80&gt; : op&lt;111:104&gt; : op&lt;  7:  0&gt;</line>
<line>    );</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/AESInvSubBytes" mylink="shared.functions.crypto.AESInvSubBytes" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AESInvSubBytes()</line>
<line>// ================</line>
<line>// Transformation in the Inverse Cipher that is the inverse of AESSubBytes.</line>
<line></line>
<line link="impl-shared.AESInvSubBytes.1" hover="function: bits(128) AESInvSubBytes(bits(128) op)" conts="AESInvSubBytes">bits(128) <anchor link="impl-shared.AESInvSubBytes.1" hover="function: bits(128) AESInvSubBytes(bits(128) op)">AESInvSubBytes</anchor>(bits(128) op)</line>
<line>    // Inverse S-box values</line>
<line>    bits(16*16*8) GF2_inv = (</line>
<line>        /*       F E D C B A 9 8 7 6 5 4 3 2 1 0       */</line>
<line>        /*F*/ 0x7d0c2155631469e126d677ba7e042b17&lt;127:0&gt; :</line>
<line>        /*E*/ 0x619953833cbbebc8b0f52aae4d3be0a0&lt;127:0&gt; :</line>
<line>        /*D*/ 0xef9cc9939f7ae52d0d4ab519a97f5160&lt;127:0&gt; :</line>
<line>        /*C*/ 0x5fec8027591012b131c7078833a8dd1f&lt;127:0&gt; :</line>
<line>        /*B*/ 0xf45acd78fec0db9a2079d2c64b3e56fc&lt;127:0&gt; :</line>
<line>        /*A*/ 0x1bbe18aa0e62b76f89c5291d711af147&lt;127:0&gt; :</line>
<line>        /*9*/ 0x6edf751ce837f9e28535ade72274ac96&lt;127:0&gt; :</line>
<line>        /*8*/ 0x73e6b4f0cecff297eadc674f4111913a&lt;127:0&gt; :</line>
<line>        /*7*/ 0x6b8a130103bdafc1020f3fca8f1e2cd0&lt;127:0&gt; :</line>
<line>        /*6*/ 0x0645b3b80558e4f70ad3bc8c00abd890&lt;127:0&gt; :</line>
<line>        /*5*/ 0x849d8da75746155edab9edfd5048706c&lt;127:0&gt; :</line>
<line>        /*4*/ 0x92b6655dcc5ca4d41698688664f6f872&lt;127:0&gt; :</line>
<line>        /*3*/ 0x25d18b6d49a25b76b224d92866a12e08&lt;127:0&gt; :</line>
<line>        /*2*/ 0x4ec3fa420b954cee3d23c2a632947b54&lt;127:0&gt; :</line>
<line>        /*1*/ 0xcbe9dec444438e3487ff2f9b8239e37c&lt;127:0&gt; :</line>
<line>        /*0*/ 0xfbd7f3819ea340bf38a53630d56a0952&lt;127:0&gt;</line>
<line>    );</line>
<line>    bits(128) out;</line>
<line>    for i = 0 to 15</line>
<line>        out&lt;i*8+:8&gt; = GF2_inv&lt;<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op&lt;i*8+:8&gt;)*8+:8&gt;;</line>
<line>    return out;</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/AESMixColumns" mylink="shared.functions.crypto.AESMixColumns" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AESMixColumns()</line>
<line>// ===============</line>
<line>// Transformation in the Cipher that takes all of the columns of the</line>
<line>// State and mixes their data (independently of one another) to</line>
<line>// produce new columns.</line>
<line></line>
<line link="impl-shared.AESMixColumns.1" hover="function: bits(128) AESMixColumns(bits (128) op)" conts="AESMixColumns">bits(128) <anchor link="impl-shared.AESMixColumns.1" hover="function: bits(128) AESMixColumns(bits (128) op)">AESMixColumns</anchor>(bits (128) op)</line>
<line>    bits(4*8) in0 = op&lt; 96+:8&gt; : op&lt; 64+:8&gt; : op&lt; 32+:8&gt; : op&lt;  0+:8&gt;;</line>
<line>    bits(4*8) in1 = op&lt;104+:8&gt; : op&lt; 72+:8&gt; : op&lt; 40+:8&gt; : op&lt;  8+:8&gt;;</line>
<line>    bits(4*8) in2 = op&lt;112+:8&gt; : op&lt; 80+:8&gt; : op&lt; 48+:8&gt; : op&lt; 16+:8&gt;;</line>
<line>    bits(4*8) in3 = op&lt;120+:8&gt; : op&lt; 88+:8&gt; : op&lt; 56+:8&gt; : op&lt; 24+:8&gt;;</line>
<line></line>
<line>    bits(4*8) out0;</line>
<line>    bits(4*8) out1;</line>
<line>    bits(4*8) out2;</line>
<line>    bits(4*8) out3;</line>
<line></line>
<line>    for c = 0 to 3</line>
<line>        out0&lt;c*8+:8&gt; = (<a link="impl-shared.FFmul02.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul02(bits(8) b)">FFmul02</a>(in0&lt;c*8+:8&gt;) EOR <a link="impl-shared.FFmul03.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul03(bits(8) b)">FFmul03</a>(in1&lt;c*8+:8&gt;) EOR</line>
<line>                                 in2&lt;c*8+:8&gt;  EOR         in3&lt;c*8+:8&gt;);</line>
<line>        out1&lt;c*8+:8&gt; = (<a link="impl-shared.FFmul02.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul02(bits(8) b)">FFmul02</a>(in1&lt;c*8+:8&gt;)  EOR <a link="impl-shared.FFmul03.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul03(bits(8) b)">FFmul03</a>(in2&lt;c*8+:8&gt;) EOR</line>
<line>                                in3&lt;c*8+:8&gt;   EOR         in0&lt;c*8+:8&gt;);</line>
<line>        out2&lt;c*8+:8&gt; = (<a link="impl-shared.FFmul02.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul02(bits(8) b)">FFmul02</a>(in2&lt;c*8+:8&gt;)  EOR <a link="impl-shared.FFmul03.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul03(bits(8) b)">FFmul03</a>(in3&lt;c*8+:8&gt;) EOR</line>
<line>                                in0&lt;c*8+:8&gt;   EOR         in1&lt;c*8+:8&gt;);</line>
<line>        out3&lt;c*8+:8&gt; = (<a link="impl-shared.FFmul02.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul02(bits(8) b)">FFmul02</a>(in3&lt;c*8+:8&gt;)  EOR <a link="impl-shared.FFmul03.1" file="shared_pseudocode.xml" hover="function: bits(8) FFmul03(bits(8) b)">FFmul03</a>(in0&lt;c*8+:8&gt;) EOR</line>
<line>                                in1&lt;c*8+:8&gt;   EOR         in2&lt;c*8+:8&gt;);</line>
<line></line>
<line>    return (</line>
<line>        out3&lt;3*8+:8&gt; : out2&lt;3*8+:8&gt; : out1&lt;3*8+:8&gt; : out0&lt;3*8+:8&gt; :</line>
<line>        out3&lt;2*8+:8&gt; : out2&lt;2*8+:8&gt; : out1&lt;2*8+:8&gt; : out0&lt;2*8+:8&gt; :</line>
<line>        out3&lt;1*8+:8&gt; : out2&lt;1*8+:8&gt; : out1&lt;1*8+:8&gt; : out0&lt;1*8+:8&gt; :</line>
<line>        out3&lt;0*8+:8&gt; : out2&lt;0*8+:8&gt; : out1&lt;0*8+:8&gt; : out0&lt;0*8+:8&gt;</line>
<line>    );</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/AESShiftRows" mylink="shared.functions.crypto.AESShiftRows" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AESShiftRows()</line>
<line>// ==============</line>
<line>// Transformation in the Cipher that processes the State by cyclically</line>
<line>// shifting the last three rows of the State by different offsets.</line>
<line></line>
<line link="impl-shared.AESShiftRows.1" hover="function: bits(128) AESShiftRows(bits(128) op)" conts="AESShiftRows">bits(128) <anchor link="impl-shared.AESShiftRows.1" hover="function: bits(128) AESShiftRows(bits(128) op)">AESShiftRows</anchor>(bits(128) op)</line>
<line>    return (</line>
<line>        op&lt; 95: 88&gt; : op&lt; 55: 48&gt; : op&lt; 15:  8&gt; : op&lt;103: 96&gt; :</line>
<line>        op&lt; 63: 56&gt; : op&lt; 23: 16&gt; : op&lt;111:104&gt; : op&lt; 71: 64&gt; :</line>
<line>        op&lt; 31: 24&gt; : op&lt;119:112&gt; : op&lt; 79: 72&gt; : op&lt; 39: 32&gt; :</line>
<line>        op&lt;127:120&gt; : op&lt; 87: 80&gt; : op&lt; 47: 40&gt; : op&lt;  7:  0&gt;</line>
<line>    );</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/AESSubBytes" mylink="shared.functions.crypto.AESSubBytes" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AESSubBytes()</line>
<line>// =============</line>
<line>// Transformation in the Cipher that processes the State using a nonlinear</line>
<line>// byte substitution table (S-box) that operates on each of the State bytes</line>
<line>// independently.</line>
<line></line>
<line link="impl-shared.AESSubBytes.1" hover="function: bits(128) AESSubBytes(bits(128) op)" conts="AESSubBytes">bits(128) <anchor link="impl-shared.AESSubBytes.1" hover="function: bits(128) AESSubBytes(bits(128) op)">AESSubBytes</anchor>(bits(128) op)</line>
<line>    // S-box values</line>
<line>    bits(16*16*8) GF2 = (</line>
<line>        /*       F E D C B A 9 8 7 6 5 4 3 2 1 0       */</line>
<line>        /*F*/ 0x16bb54b00f2d99416842e6bf0d89a18c&lt;127:0&gt; :</line>
<line>        /*E*/ 0xdf2855cee9871e9b948ed9691198f8e1&lt;127:0&gt; :</line>
<line>        /*D*/ 0x9e1dc186b95735610ef6034866b53e70&lt;127:0&gt; :</line>
<line>        /*C*/ 0x8a8bbd4b1f74dde8c6b4a61c2e2578ba&lt;127:0&gt; :</line>
<line>        /*B*/ 0x08ae7a65eaf4566ca94ed58d6d37c8e7&lt;127:0&gt; :</line>
<line>        /*A*/ 0x79e4959162acd3c25c2406490a3a32e0&lt;127:0&gt; :</line>
<line>        /*9*/ 0xdb0b5ede14b8ee4688902a22dc4f8160&lt;127:0&gt; :</line>
<line>        /*8*/ 0x73195d643d7ea7c41744975fec130ccd&lt;127:0&gt; :</line>
<line>        /*7*/ 0xd2f3ff1021dab6bcf5389d928f40a351&lt;127:0&gt; :</line>
<line>        /*6*/ 0xa89f3c507f02f94585334d43fbaaefd0&lt;127:0&gt; :</line>
<line>        /*5*/ 0xcf584c4a39becb6a5bb1fc20ed00d153&lt;127:0&gt; :</line>
<line>        /*4*/ 0x842fe329b3d63b52a05a6e1b1a2c8309&lt;127:0&gt; :</line>
<line>        /*3*/ 0x75b227ebe28012079a059618c323c704&lt;127:0&gt; :</line>
<line>        /*2*/ 0x1531d871f1e5a534ccf73f362693fdb7&lt;127:0&gt; :</line>
<line>        /*1*/ 0xc072a49cafa2d4adf04759fa7dc982ca&lt;127:0&gt; :</line>
<line>        /*0*/ 0x76abd7fe2b670130c56f6bf27b777c63&lt;127:0&gt;</line>
<line>    );</line>
<line>    bits(128) out;</line>
<line>    for i = 0 to 15</line>
<line>        out&lt;i*8+:8&gt; = GF2&lt;<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op&lt;i*8+:8&gt;)*8+:8&gt;;</line>
<line>    return out;</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/FFmul02" mylink="shared.functions.crypto.FFmul02" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FFmul02()</line>
<line>// =========</line>
<line></line>
<line link="impl-shared.FFmul02.1" hover="function: bits(8) FFmul02(bits(8) b)" conts="FFmul02">bits(8) <anchor link="impl-shared.FFmul02.1" hover="function: bits(8) FFmul02(bits(8) b)">FFmul02</anchor>(bits(8) b)</line>
<line>    bits(256*8) FFmul_02 = (</line>
<line>        /*       F E D C B A 9 8 7 6 5 4 3 2 1 0       */</line>
<line>        /*F*/ 0xE5E7E1E3EDEFE9EBF5F7F1F3FDFFF9FB&lt;127:0&gt; :</line>
<line>        /*E*/ 0xC5C7C1C3CDCFC9CBD5D7D1D3DDDFD9DB&lt;127:0&gt; :</line>
<line>        /*D*/ 0xA5A7A1A3ADAFA9ABB5B7B1B3BDBFB9BB&lt;127:0&gt; :</line>
<line>        /*C*/ 0x858781838D8F898B959791939D9F999B&lt;127:0&gt; :</line>
<line>        /*B*/ 0x656761636D6F696B757771737D7F797B&lt;127:0&gt; :</line>
<line>        /*A*/ 0x454741434D4F494B555751535D5F595B&lt;127:0&gt; :</line>
<line>        /*9*/ 0x252721232D2F292B353731333D3F393B&lt;127:0&gt; :</line>
<line>        /*8*/ 0x050701030D0F090B151711131D1F191B&lt;127:0&gt; :</line>
<line>        /*7*/ 0xFEFCFAF8F6F4F2F0EEECEAE8E6E4E2E0&lt;127:0&gt; :</line>
<line>        /*6*/ 0xDEDCDAD8D6D4D2D0CECCCAC8C6C4C2C0&lt;127:0&gt; :</line>
<line>        /*5*/ 0xBEBCBAB8B6B4B2B0AEACAAA8A6A4A2A0&lt;127:0&gt; :</line>
<line>        /*4*/ 0x9E9C9A98969492908E8C8A8886848280&lt;127:0&gt; :</line>
<line>        /*3*/ 0x7E7C7A78767472706E6C6A6866646260&lt;127:0&gt; :</line>
<line>        /*2*/ 0x5E5C5A58565452504E4C4A4846444240&lt;127:0&gt; :</line>
<line>        /*1*/ 0x3E3C3A38363432302E2C2A2826242220&lt;127:0&gt; :</line>
<line>        /*0*/ 0x1E1C1A18161412100E0C0A0806040200&lt;127:0&gt;</line>
<line>    );</line>
<line>    return FFmul_02&lt;<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(b)*8+:8&gt;;</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/FFmul03" mylink="shared.functions.crypto.FFmul03" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FFmul03()</line>
<line>// =========</line>
<line></line>
<line link="impl-shared.FFmul03.1" hover="function: bits(8) FFmul03(bits(8) b)" conts="FFmul03">bits(8) <anchor link="impl-shared.FFmul03.1" hover="function: bits(8) FFmul03(bits(8) b)">FFmul03</anchor>(bits(8) b)</line>
<line>    bits(256*8) FFmul_03 = (</line>
<line>        /*       F E D C B A 9 8 7 6 5 4 3 2 1 0       */</line>
<line>        /*F*/ 0x1A191C1F16151013020104070E0D080B&lt;127:0&gt; :</line>
<line>        /*E*/ 0x2A292C2F26252023323134373E3D383B&lt;127:0&gt; :</line>
<line>        /*D*/ 0x7A797C7F76757073626164676E6D686B&lt;127:0&gt; :</line>
<line>        /*C*/ 0x4A494C4F46454043525154575E5D585B&lt;127:0&gt; :</line>
<line>        /*B*/ 0xDAD9DCDFD6D5D0D3C2C1C4C7CECDC8CB&lt;127:0&gt; :</line>
<line>        /*A*/ 0xEAE9ECEFE6E5E0E3F2F1F4F7FEFDF8FB&lt;127:0&gt; :</line>
<line>        /*9*/ 0xBAB9BCBFB6B5B0B3A2A1A4A7AEADA8AB&lt;127:0&gt; :</line>
<line>        /*8*/ 0x8A898C8F86858083929194979E9D989B&lt;127:0&gt; :</line>
<line>        /*7*/ 0x818287848D8E8B88999A9F9C95969390&lt;127:0&gt; :</line>
<line>        /*6*/ 0xB1B2B7B4BDBEBBB8A9AAAFACA5A6A3A0&lt;127:0&gt; :</line>
<line>        /*5*/ 0xE1E2E7E4EDEEEBE8F9FAFFFCF5F6F3F0&lt;127:0&gt; :</line>
<line>        /*4*/ 0xD1D2D7D4DDDEDBD8C9CACFCCC5C6C3C0&lt;127:0&gt; :</line>
<line>        /*3*/ 0x414247444D4E4B48595A5F5C55565350&lt;127:0&gt; :</line>
<line>        /*2*/ 0x717277747D7E7B78696A6F6C65666360&lt;127:0&gt; :</line>
<line>        /*1*/ 0x212227242D2E2B28393A3F3C35363330&lt;127:0&gt; :</line>
<line>        /*0*/ 0x111217141D1E1B18090A0F0C05060300&lt;127:0&gt;</line>
<line>    );</line>
<line>    return FFmul_03&lt;<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(b)*8+:8&gt;;</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/FFmul09" mylink="shared.functions.crypto.FFmul09" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FFmul09()</line>
<line>// =========</line>
<line></line>
<line link="impl-shared.FFmul09.1" hover="function: bits(8) FFmul09(bits(8) b)" conts="FFmul09">bits(8) <anchor link="impl-shared.FFmul09.1" hover="function: bits(8) FFmul09(bits(8) b)">FFmul09</anchor>(bits(8) b)</line>
<line>    bits(256*8) FFmul_09 = (</line>
<line>        /*       F E D C B A 9 8 7 6 5 4 3 2 1 0       */</line>
<line>        /*F*/ 0x464F545D626B70790E071C152A233831&lt;127:0&gt; :</line>
<line>        /*E*/ 0xD6DFC4CDF2FBE0E99E978C85BAB3A8A1&lt;127:0&gt; :</line>
<line>        /*D*/ 0x7D746F6659504B42353C272E1118030A&lt;127:0&gt; :</line>
<line>        /*C*/ 0xEDE4FFF6C9C0DBD2A5ACB7BE8188939A&lt;127:0&gt; :</line>
<line>        /*B*/ 0x3039222B141D060F78716A635C554E47&lt;127:0&gt; :</line>
<line>        /*A*/ 0xA0A9B2BB848D969FE8E1FAF3CCC5DED7&lt;127:0&gt; :</line>
<line>        /*9*/ 0x0B0219102F263D34434A5158676E757C&lt;127:0&gt; :</line>
<line>        /*8*/ 0x9B928980BFB6ADA4D3DAC1C8F7FEE5EC&lt;127:0&gt; :</line>
<line>        /*7*/ 0xAAA3B8B18E879C95E2EBF0F9C6CFD4DD&lt;127:0&gt; :</line>
<line>        /*6*/ 0x3A3328211E170C05727B6069565F444D&lt;127:0&gt; :</line>
<line>        /*5*/ 0x9198838AB5BCA7AED9D0CBC2FDF4EFE6&lt;127:0&gt; :</line>
<line>        /*4*/ 0x0108131A252C373E49405B526D647F76&lt;127:0&gt; :</line>
<line>        /*3*/ 0xDCD5CEC7F8F1EAE3949D868FB0B9A2AB&lt;127:0&gt; :</line>
<line>        /*2*/ 0x4C455E5768617A73040D161F2029323B&lt;127:0&gt; :</line>
<line>        /*1*/ 0xE7EEF5FCC3CAD1D8AFA6BDB48B829990&lt;127:0&gt; :</line>
<line>        /*0*/ 0x777E656C535A41483F362D241B120900&lt;127:0&gt;</line>
<line>    );</line>
<line>    return FFmul_09&lt;<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(b)*8+:8&gt;;</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/FFmul0B" mylink="shared.functions.crypto.FFmul0B" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FFmul0B()</line>
<line>// =========</line>
<line></line>
<line link="impl-shared.FFmul0B.1" hover="function: bits(8) FFmul0B(bits(8) b)" conts="FFmul0B">bits(8) <anchor link="impl-shared.FFmul0B.1" hover="function: bits(8) FFmul0B(bits(8) b)">FFmul0B</anchor>(bits(8) b)</line>
<line>    bits(256*8) FFmul_0B = (</line>
<line>        /*       F E D C B A 9 8 7 6 5 4 3 2 1 0       */</line>
<line>        /*F*/ 0xA3A8B5BE8F849992FBF0EDE6D7DCC1CA&lt;127:0&gt; :</line>
<line>        /*E*/ 0x1318050E3F3429224B405D56676C717A&lt;127:0&gt; :</line>
<line>        /*D*/ 0xD8D3CEC5F4FFE2E9808B969DACA7BAB1&lt;127:0&gt; :</line>
<line>        /*C*/ 0x68637E75444F5259303B262D1C170A01&lt;127:0&gt; :</line>
<line>        /*B*/ 0x555E434879726F640D061B10212A373C&lt;127:0&gt; :</line>
<line>        /*A*/ 0xE5EEF3F8C9C2DFD4BDB6ABA0919A878C&lt;127:0&gt; :</line>
<line>        /*9*/ 0x2E2538330209141F767D606B5A514C47&lt;127:0&gt; :</line>
<line>        /*8*/ 0x9E958883B2B9A4AFC6CDD0DBEAE1FCF7&lt;127:0&gt; :</line>
<line>        /*7*/ 0x545F424978736E650C071A11202B363D&lt;127:0&gt; :</line>
<line>        /*6*/ 0xE4EFF2F9C8C3DED5BCB7AAA1909B868D&lt;127:0&gt; :</line>
<line>        /*5*/ 0x2F2439320308151E777C616A5B504D46&lt;127:0&gt; :</line>
<line>        /*4*/ 0x9F948982B3B8A5AEC7CCD1DAEBE0FDF6&lt;127:0&gt; :</line>
<line>        /*3*/ 0xA2A9B4BF8E859893FAF1ECE7D6DDC0CB&lt;127:0&gt; :</line>
<line>        /*2*/ 0x1219040F3E3528234A415C57666D707B&lt;127:0&gt; :</line>
<line>        /*1*/ 0xD9D2CFC4F5FEE3E8818A979CADA6BBB0&lt;127:0&gt; :</line>
<line>        /*0*/ 0x69627F74454E5358313A272C1D160B00&lt;127:0&gt;</line>
<line>    );</line>
<line>    return FFmul_0B&lt;<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(b)*8+:8&gt;;</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/FFmul0D" mylink="shared.functions.crypto.FFmul0D" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FFmul0D()</line>
<line>// =========</line>
<line></line>
<line link="impl-shared.FFmul0D.1" hover="function: bits(8) FFmul0D(bits(8) b)" conts="FFmul0D">bits(8) <anchor link="impl-shared.FFmul0D.1" hover="function: bits(8) FFmul0D(bits(8) b)">FFmul0D</anchor>(bits(8) b)</line>
<line>    bits(256*8) FFmul_0D = (</line>
<line>        /*       F E D C B A 9 8 7 6 5 4 3 2 1 0       */</line>
<line>        /*F*/ 0x979A8D80A3AEB9B4FFF2E5E8CBC6D1DC&lt;127:0&gt; :</line>
<line>        /*E*/ 0x474A5D50737E69642F2235381B16010C&lt;127:0&gt; :</line>
<line>        /*D*/ 0x2C21363B1815020F44495E53707D6A67&lt;127:0&gt; :</line>
<line>        /*C*/ 0xFCF1E6EBC8C5D2DF94998E83A0ADBAB7&lt;127:0&gt; :</line>
<line>        /*B*/ 0xFAF7E0EDCEC3D4D9929F8885A6ABBCB1&lt;127:0&gt; :</line>
<line>        /*A*/ 0x2A27303D1E130409424F5855767B6C61&lt;127:0&gt; :</line>
<line>        /*9*/ 0x414C5B5675786F622924333E1D10070A&lt;127:0&gt; :</line>
<line>        /*8*/ 0x919C8B86A5A8BFB2F9F4E3EECDC0D7DA&lt;127:0&gt; :</line>
<line>        /*7*/ 0x4D40575A7974636E25283F32111C0B06&lt;127:0&gt; :</line>
<line>        /*6*/ 0x9D90878AA9A4B3BEF5F8EFE2C1CCDBD6&lt;127:0&gt; :</line>
<line>        /*5*/ 0xF6FBECE1C2CFD8D59E938489AAA7B0BD&lt;127:0&gt; :</line>
<line>        /*4*/ 0x262B3C31121F08054E4354597A77606D&lt;127:0&gt; :</line>
<line>        /*3*/ 0x202D3A3714190E034845525F7C71666B&lt;127:0&gt; :</line>
<line>        /*2*/ 0xF0FDEAE7C4C9DED39895828FACA1B6BB&lt;127:0&gt; :</line>
<line>        /*1*/ 0x9B96818CAFA2B5B8F3FEE9E4C7CADDD0&lt;127:0&gt; :</line>
<line>        /*0*/ 0x4B46515C7F726568232E3934171A0D00&lt;127:0&gt;</line>
<line>    );</line>
<line>    return FFmul_0D&lt;<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(b)*8+:8&gt;;</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/FFmul0E" mylink="shared.functions.crypto.FFmul0E" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FFmul0E()</line>
<line>// =========</line>
<line></line>
<line link="impl-shared.FFmul0E.1" hover="function: bits(8) FFmul0E(bits(8) b)" conts="FFmul0E">bits(8) <anchor link="impl-shared.FFmul0E.1" hover="function: bits(8) FFmul0E(bits(8) b)">FFmul0E</anchor>(bits(8) b)</line>
<line>    bits(256*8) FFmul_0E = (</line>
<line>        /*       F E D C B A 9 8 7 6 5 4 3 2 1 0       */</line>
<line>        /*F*/ 0x8D83919FB5BBA9A7FDF3E1EFC5CBD9D7&lt;127:0&gt; :</line>
<line>        /*E*/ 0x6D63717F555B49471D13010F252B3937&lt;127:0&gt; :</line>
<line>        /*D*/ 0x56584A446E60727C26283A341E10020C&lt;127:0&gt; :</line>
<line>        /*C*/ 0xB6B8AAA48E80929CC6C8DAD4FEF0E2EC&lt;127:0&gt; :</line>
<line>        /*B*/ 0x202E3C321816040A505E4C426866747A&lt;127:0&gt; :</line>
<line>        /*A*/ 0xC0CEDCD2F8F6E4EAB0BEACA28886949A&lt;127:0&gt; :</line>
<line>        /*9*/ 0xFBF5E7E9C3CDDFD18B859799B3BDAFA1&lt;127:0&gt; :</line>
<line>        /*8*/ 0x1B150709232D3F316B657779535D4F41&lt;127:0&gt; :</line>
<line>        /*7*/ 0xCCC2D0DEF4FAE8E6BCB2A0AE848A9896&lt;127:0&gt; :</line>
<line>        /*6*/ 0x2C22303E141A08065C52404E646A7876&lt;127:0&gt; :</line>
<line>        /*5*/ 0x17190B052F21333D67697B755F51434D&lt;127:0&gt; :</line>
<line>        /*4*/ 0xF7F9EBE5CFC1D3DD87899B95BFB1A3AD&lt;127:0&gt; :</line>
<line>        /*3*/ 0x616F7D735957454B111F0D032927353B&lt;127:0&gt; :</line>
<line>        /*2*/ 0x818F9D93B9B7A5ABF1FFEDE3C9C7D5DB&lt;127:0&gt; :</line>
<line>        /*1*/ 0xBAB4A6A8828C9E90CAC4D6D8F2FCEEE0&lt;127:0&gt; :</line>
<line>        /*0*/ 0x5A544648626C7E702A243638121C0E00&lt;127:0&gt;</line>
<line>    );</line>
<line>    return FFmul_0E&lt;<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(b)*8+:8&gt;;</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/HaveAESExt" mylink="shared.functions.crypto.HaveAESExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveAESExt()</line>
<line>// ============</line>
<line>// TRUE if AES cryptographic instructions support is implemented,</line>
<line>// FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveAESExt.0" hover="function: boolean HaveAESExt()" conts="HaveAESExt">boolean <anchor link="impl-shared.HaveAESExt.0" hover="function: boolean HaveAESExt()">HaveAESExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_AES);</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/HaveBit128PMULLExt" mylink="shared.functions.crypto.HaveBit128PMULLExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveBit128PMULLExt()</line>
<line>// ====================</line>
<line>// TRUE if 128 bit form of PMULL instructions support is implemented,</line>
<line>// FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveBit128PMULLExt.0" hover="function: boolean HaveBit128PMULLExt()" conts="HaveBit128PMULLExt">boolean <anchor link="impl-shared.HaveBit128PMULLExt.0" hover="function: boolean HaveBit128PMULLExt()">HaveBit128PMULLExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_PMULL);</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/HaveSHA1Ext" mylink="shared.functions.crypto.HaveSHA1Ext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSHA1Ext()</line>
<line>// =============</line>
<line>// TRUE if SHA1 cryptographic instructions support is implemented,</line>
<line>// FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveSHA1Ext.0" hover="function: boolean HaveSHA1Ext()" conts="HaveSHA1Ext">boolean <anchor link="impl-shared.HaveSHA1Ext.0" hover="function: boolean HaveSHA1Ext()">HaveSHA1Ext</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SHA1);</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/HaveSHA256Ext" mylink="shared.functions.crypto.HaveSHA256Ext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSHA256Ext()</line>
<line>// ===============</line>
<line>// TRUE if SHA256 cryptographic instructions support is implemented,</line>
<line>// FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveSHA256Ext.0" hover="function: boolean HaveSHA256Ext()" conts="HaveSHA256Ext">boolean <anchor link="impl-shared.HaveSHA256Ext.0" hover="function: boolean HaveSHA256Ext()">HaveSHA256Ext</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SHA256);</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/HaveSHA3Ext" mylink="shared.functions.crypto.HaveSHA3Ext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSHA3Ext()</line>
<line>// =============</line>
<line>// TRUE if SHA3 cryptographic instructions support is implemented,</line>
<line>// and when SHA1 and SHA2 basic cryptographic instructions support is implemented,</line>
<line>// FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveSHA3Ext.0" hover="function: boolean HaveSHA3Ext()" conts="HaveSHA3Ext">boolean <anchor link="impl-shared.HaveSHA3Ext.0" hover="function: boolean HaveSHA3Ext()">HaveSHA3Ext</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SHA3);</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/HaveSHA512Ext" mylink="shared.functions.crypto.HaveSHA512Ext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSHA512Ext()</line>
<line>// ===============</line>
<line>// TRUE if SHA512 cryptographic instructions support is implemented,</line>
<line>// and when SHA1 and SHA2 basic cryptographic instructions support is implemented,</line>
<line>// FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveSHA512Ext.0" hover="function: boolean HaveSHA512Ext()" conts="HaveSHA512Ext">boolean <anchor link="impl-shared.HaveSHA512Ext.0" hover="function: boolean HaveSHA512Ext()">HaveSHA512Ext</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SHA512);</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/HaveSM3Ext" mylink="shared.functions.crypto.HaveSM3Ext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSM3Ext()</line>
<line>// ============</line>
<line>// TRUE if SM3 cryptographic instructions support is implemented,</line>
<line>// FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveSM3Ext.0" hover="function: boolean HaveSM3Ext()" conts="HaveSM3Ext">boolean <anchor link="impl-shared.HaveSM3Ext.0" hover="function: boolean HaveSM3Ext()">HaveSM3Ext</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SM3);</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/HaveSM4Ext" mylink="shared.functions.crypto.HaveSM4Ext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSM4Ext()</line>
<line>// ============</line>
<line>// TRUE if SM4 cryptographic instructions support is implemented,</line>
<line>// FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveSM4Ext.0" hover="function: boolean HaveSM4Ext()" conts="HaveSM4Ext">boolean <anchor link="impl-shared.HaveSM4Ext.0" hover="function: boolean HaveSM4Ext()">HaveSM4Ext</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SM4);</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/ROL" mylink="shared.functions.crypto.ROL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ROL()</line>
<line>// =====</line>
<line></line>
<line link="impl-shared.ROL.2" hover="function: bits(N) ROL(bits(N) x, integer shift)" conts="ROL">bits(N) <anchor link="impl-shared.ROL.2" hover="function: bits(N) ROL(bits(N) x, integer shift)">ROL</anchor>(bits(N) x, integer shift)</line>
<line>    assert shift &gt;= 0 &amp;&amp; shift &lt;= N;</line>
<line>    if (shift == 0) then</line>
<line>        return x;</line>
<line>    return <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(x, N-shift);</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/SHA256hash" mylink="shared.functions.crypto.SHA256hash" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SHA256hash()</line>
<line>// ============</line>
<line></line>
<line link="impl-shared.SHA256hash.4" hover="function: bits(128) SHA256hash(bits (128) x_in, bits(128) y_in, bits(128) w, boolean part1)" conts="SHA256hash">bits(128) <anchor link="impl-shared.SHA256hash.4" hover="function: bits(128) SHA256hash(bits (128) x_in, bits(128) y_in, bits(128) w, boolean part1)">SHA256hash</anchor>(bits (128) x_in, bits(128) y_in, bits(128) w, boolean part1)</line>
<line>    bits(32) chs, maj, t;</line>
<line>    bits(128) x = x_in;</line>
<line>    bits(128) y = y_in;</line>
<line></line>
<line>    for e = 0 to 3</line>
<line>        chs = <a link="impl-shared.SHAchoose.3" file="shared_pseudocode.xml" hover="function: bits(32) SHAchoose(bits(32) x, bits(32) y, bits(32) z)">SHAchoose</a>(y&lt;31:0&gt;, y&lt;63:32&gt;, y&lt;95:64&gt;);</line>
<line>        maj = <a link="impl-shared.SHAmajority.3" file="shared_pseudocode.xml" hover="function: bits(32) SHAmajority(bits(32) x, bits(32) y, bits(32) z)">SHAmajority</a>(x&lt;31:0&gt;, x&lt;63:32&gt;, x&lt;95:64&gt;);</line>
<line>        t = y&lt;127:96&gt; + <a link="impl-shared.SHAhashSIGMA1.1" file="shared_pseudocode.xml" hover="function: bits(32) SHAhashSIGMA1(bits(32) x)">SHAhashSIGMA1</a>(y&lt;31:0&gt;) + chs + <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[w, e, 32];</line>
<line>        x&lt;127:96&gt; = t + x&lt;127:96&gt;;</line>
<line>        y&lt;127:96&gt; = t + <a link="impl-shared.SHAhashSIGMA0.1" file="shared_pseudocode.xml" hover="function: bits(32) SHAhashSIGMA0(bits(32) x)">SHAhashSIGMA0</a>(x&lt;31:0&gt;) + maj;</line>
<line>        &lt;y, x&gt; = <a link="impl-shared.ROL.2" file="shared_pseudocode.xml" hover="function: bits(N) ROL(bits(N) x, integer shift)">ROL</a>(y : x, 32);</line>
<line>    return (if part1 then x else y);</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/SHAchoose" mylink="shared.functions.crypto.SHAchoose" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SHAchoose()</line>
<line>// ===========</line>
<line></line>
<line link="impl-shared.SHAchoose.3" hover="function: bits(32) SHAchoose(bits(32) x, bits(32) y, bits(32) z)" conts="SHAchoose">bits(32) <anchor link="impl-shared.SHAchoose.3" hover="function: bits(32) SHAchoose(bits(32) x, bits(32) y, bits(32) z)">SHAchoose</anchor>(bits(32) x, bits(32) y, bits(32) z)</line>
<line>    return (((y EOR z) AND x) EOR z);</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/SHAhashSIGMA0" mylink="shared.functions.crypto.SHAhashSIGMA0" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SHAhashSIGMA0()</line>
<line>// ===============</line>
<line></line>
<line link="impl-shared.SHAhashSIGMA0.1" hover="function: bits(32) SHAhashSIGMA0(bits(32) x)" conts="SHAhashSIGMA0">bits(32) <anchor link="impl-shared.SHAhashSIGMA0.1" hover="function: bits(32) SHAhashSIGMA0(bits(32) x)">SHAhashSIGMA0</anchor>(bits(32) x)</line>
<line>    return <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(x, 2) EOR <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(x, 13) EOR <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(x, 22);</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/SHAhashSIGMA1" mylink="shared.functions.crypto.SHAhashSIGMA1" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SHAhashSIGMA1()</line>
<line>// ===============</line>
<line></line>
<line link="impl-shared.SHAhashSIGMA1.1" hover="function: bits(32) SHAhashSIGMA1(bits(32) x)" conts="SHAhashSIGMA1">bits(32) <anchor link="impl-shared.SHAhashSIGMA1.1" hover="function: bits(32) SHAhashSIGMA1(bits(32) x)">SHAhashSIGMA1</anchor>(bits(32) x)</line>
<line>    return <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(x, 6) EOR <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(x, 11) EOR <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(x, 25);</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/SHAmajority" mylink="shared.functions.crypto.SHAmajority" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SHAmajority()</line>
<line>// =============</line>
<line></line>
<line link="impl-shared.SHAmajority.3" hover="function: bits(32) SHAmajority(bits(32) x, bits(32) y, bits(32) z)" conts="SHAmajority">bits(32) <anchor link="impl-shared.SHAmajority.3" hover="function: bits(32) SHAmajority(bits(32) x, bits(32) y, bits(32) z)">SHAmajority</anchor>(bits(32) x, bits(32) y, bits(32) z)</line>
<line>    return ((x AND y) OR ((x OR y) AND z));</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/SHAparity" mylink="shared.functions.crypto.SHAparity" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SHAparity()</line>
<line>// ===========</line>
<line></line>
<line link="impl-shared.SHAparity.3" hover="function: bits(32) SHAparity(bits(32) x, bits(32) y, bits(32) z)" conts="SHAparity">bits(32) <anchor link="impl-shared.SHAparity.3" hover="function: bits(32) SHAparity(bits(32) x, bits(32) y, bits(32) z)">SHAparity</anchor>(bits(32) x, bits(32) y, bits(32) z)</line>
<line>    return (x EOR y EOR z);</line>
</pstext>
    </ps>
    <ps name="shared/functions/crypto/Sbox" mylink="shared.functions.crypto.Sbox" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Sbox()</line>
<line>// ======</line>
<line>// Used in SM4E crypto instruction</line>
<line></line>
<line link="impl-shared.Sbox.1" hover="function: bits(8) Sbox(bits(8) sboxin)" conts="Sbox">bits(8) <anchor link="impl-shared.Sbox.1" hover="function: bits(8) Sbox(bits(8) sboxin)">Sbox</anchor>(bits(8) sboxin)</line>
<line>    bits(8) sboxout;</line>
<line>    bits(2048) sboxstring = (</line>
<line>        /*       F E D C B A 9 8 7 6 5 4 3 2 1 0       */</line>
<line>        /*F*/ 0xd690e9fecce13db716b614c228fb2c05&lt;127:0&gt; :</line>
<line>        /*E*/ 0x2b679a762abe04c3aa44132649860699&lt;127:0&gt; :</line>
<line>        /*D*/ 0x9c4250f491ef987a33540b43edcfac62&lt;127:0&gt; :</line>
<line>        /*C*/ 0xe4b31ca9c908e89580df94fa758f3fa6&lt;127:0&gt; :</line>
<line>        /*B*/ 0x4707a7fcf37317ba83593c19e6854fa8&lt;127:0&gt; :</line>
<line>        /*A*/ 0x686b81b27164da8bf8eb0f4b70569d35&lt;127:0&gt; :</line>
<line>        /*9*/ 0x1e240e5e6358d1a225227c3b01217887&lt;127:0&gt; :</line>
<line>        /*8*/ 0xd40046579fd327524c3602e7a0c4c89e&lt;127:0&gt; :</line>
<line>        /*7*/ 0xeabf8ad240c738b5a3f7f2cef96115a1&lt;127:0&gt; :</line>
<line>        /*6*/ 0xe0ae5da49b341a55ad933230f58cb1e3&lt;127:0&gt; :</line>
<line>        /*5*/ 0x1df6e22e8266ca60c02923ab0d534e6f&lt;127:0&gt; :</line>
<line>        /*4*/ 0xd5db3745defd8e2f03ff6a726d6c5b51&lt;127:0&gt; :</line>
<line>        /*3*/ 0x8d1baf92bbddbc7f11d95c411f105ad8&lt;127:0&gt; :</line>
<line>        /*2*/ 0x0ac13188a5cd7bbd2d74d012b8e5b4b0&lt;127:0&gt; :</line>
<line>        /*1*/ 0x8969974a0c96777e65b9f109c56ec684&lt;127:0&gt; :</line>
<line>        /*0*/ 0x18f07dec3adc4d2079ee5f3ed7cb3948&lt;127:0&gt;</line>
<line>    );</line>
<line></line>
<line>    sboxout = sboxstring&lt;(255-<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sboxin))*8+7:(255-<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sboxin))*8&gt;;</line>
<line>    return sboxout;</line>
</pstext>
    </ps>
    <ps name="shared/functions/exclusive/ClearExclusiveByAddress" mylink="shared.functions.exclusive.ClearExclusiveByAddress" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ClearExclusiveByAddress()</line>
<line>// =========================</line>
<line>// Clear the global Exclusives monitors for all PEs EXCEPT processorid if they</line>
<line>// record any part of the physical address region of size bytes starting at paddress.</line>
<line>// It is IMPLEMENTATION DEFINED whether the global Exclusives monitor for processorid</line>
<line>// is also cleared if it records any part of the address region.</line>
<line></line>
<line link="impl-shared.ClearExclusiveByAddress.3" hover="function: ClearExclusiveByAddress(FullAddress paddress, integer processorid, integer size)" conts="ClearExclusiveByAddress"><anchor link="impl-shared.ClearExclusiveByAddress.3" hover="function: ClearExclusiveByAddress(FullAddress paddress, integer processorid, integer size)">ClearExclusiveByAddress</anchor>(<a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> paddress, integer processorid, integer size);</line>
</pstext>
    </ps>
    <ps name="shared/functions/exclusive/ClearExclusiveLocal" mylink="shared.functions.exclusive.ClearExclusiveLocal" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ClearExclusiveLocal()</line>
<line>// =====================</line>
<line>// Clear the local Exclusives monitor for the specified processorid.</line>
<line></line>
<line link="impl-shared.ClearExclusiveLocal.1" hover="function: ClearExclusiveLocal(integer processorid)" conts="ClearExclusiveLocal"><anchor link="impl-shared.ClearExclusiveLocal.1" hover="function: ClearExclusiveLocal(integer processorid)">ClearExclusiveLocal</anchor>(integer processorid);</line>
</pstext>
    </ps>
    <ps name="shared/functions/exclusive/ClearExclusiveMonitors" mylink="shared.functions.exclusive.ClearExclusiveMonitors" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ClearExclusiveMonitors()</line>
<line>// ========================</line>
<line>// Clear the local Exclusives monitor for the executing PE.</line>
<line></line>
<line link="impl-shared.ClearExclusiveMonitors.0" hover="function: ClearExclusiveMonitors()" conts="ClearExclusiveMonitors"><anchor link="impl-shared.ClearExclusiveMonitors.0" hover="function: ClearExclusiveMonitors()">ClearExclusiveMonitors</anchor>()</line>
<line>    <a link="impl-shared.ClearExclusiveLocal.1" file="shared_pseudocode.xml" hover="function: ClearExclusiveLocal(integer processorid)">ClearExclusiveLocal</a>(<a link="impl-shared.ProcessorID.0" file="shared_pseudocode.xml" hover="function: integer ProcessorID()">ProcessorID</a>());</line>
</pstext>
    </ps>
    <ps name="shared/functions/exclusive/ExclusiveMonitorsStatus" mylink="shared.functions.exclusive.ExclusiveMonitorsStatus" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExclusiveMonitorsStatus()</line>
<line>// =========================</line>
<line>// Returns '0' to indicate success if the last memory write by this PE was to</line>
<line>// the same physical address region endorsed by ExclusiveMonitorsPass().</line>
<line>// Returns '1' to indicate failure if address translation resulted in a different</line>
<line>// physical address.</line>
<line></line>
<line link="impl-shared.ExclusiveMonitorsStatus.0" hover="function: bit ExclusiveMonitorsStatus()" conts="ExclusiveMonitorsStatus">bit <anchor link="impl-shared.ExclusiveMonitorsStatus.0" hover="function: bit ExclusiveMonitorsStatus()">ExclusiveMonitorsStatus</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/exclusive/IsExclusiveGlobal" mylink="shared.functions.exclusive.IsExclusiveGlobal" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsExclusiveGlobal()</line>
<line>// ===================</line>
<line>// Return TRUE if the global Exclusives monitor for processorid includes all of</line>
<line>// the physical address region of size bytes starting at paddress.</line>
<line></line>
<line link="impl-shared.IsExclusiveGlobal.3" hover="function: boolean IsExclusiveGlobal(FullAddress paddress, integer processorid, integer size)" conts="IsExclusiveGlobal">boolean <anchor link="impl-shared.IsExclusiveGlobal.3" hover="function: boolean IsExclusiveGlobal(FullAddress paddress, integer processorid, integer size)">IsExclusiveGlobal</anchor>(<a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> paddress, integer processorid, integer size);</line>
</pstext>
    </ps>
    <ps name="shared/functions/exclusive/IsExclusiveLocal" mylink="shared.functions.exclusive.IsExclusiveLocal" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsExclusiveLocal()</line>
<line>// ==================</line>
<line>// Return TRUE if the local Exclusives monitor for processorid includes all of</line>
<line>// the physical address region of size bytes starting at paddress.</line>
<line></line>
<line link="impl-shared.IsExclusiveLocal.3" hover="function: boolean IsExclusiveLocal(FullAddress paddress, integer processorid, integer size)" conts="IsExclusiveLocal">boolean <anchor link="impl-shared.IsExclusiveLocal.3" hover="function: boolean IsExclusiveLocal(FullAddress paddress, integer processorid, integer size)">IsExclusiveLocal</anchor>(<a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> paddress, integer processorid, integer size);</line>
</pstext>
    </ps>
    <ps name="shared/functions/exclusive/MarkExclusiveGlobal" mylink="shared.functions.exclusive.MarkExclusiveGlobal" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MarkExclusiveGlobal()</line>
<line>// =====================</line>
<line>// Record the physical address region of size bytes starting at paddress in</line>
<line>// the global Exclusives monitor for processorid.</line>
<line></line>
<line link="impl-shared.MarkExclusiveGlobal.3" hover="function: MarkExclusiveGlobal(FullAddress paddress, integer processorid, integer size)" conts="MarkExclusiveGlobal"><anchor link="impl-shared.MarkExclusiveGlobal.3" hover="function: MarkExclusiveGlobal(FullAddress paddress, integer processorid, integer size)">MarkExclusiveGlobal</anchor>(<a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> paddress, integer processorid, integer size);</line>
</pstext>
    </ps>
    <ps name="shared/functions/exclusive/MarkExclusiveLocal" mylink="shared.functions.exclusive.MarkExclusiveLocal" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MarkExclusiveLocal()</line>
<line>// ====================</line>
<line>// Record the physical address region of size bytes starting at paddress in</line>
<line>// the local Exclusives monitor for processorid.</line>
<line></line>
<line link="impl-shared.MarkExclusiveLocal.3" hover="function: MarkExclusiveLocal(FullAddress paddress, integer processorid, integer size)" conts="MarkExclusiveLocal"><anchor link="impl-shared.MarkExclusiveLocal.3" hover="function: MarkExclusiveLocal(FullAddress paddress, integer processorid, integer size)">MarkExclusiveLocal</anchor>(<a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> paddress, integer processorid, integer size);</line>
</pstext>
    </ps>
    <ps name="shared/functions/exclusive/ProcessorID" mylink="shared.functions.exclusive.ProcessorID" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ProcessorID()</line>
<line>// =============</line>
<line>// Return the ID of the currently executing PE.</line>
<line></line>
<line link="impl-shared.ProcessorID.0" hover="function: integer ProcessorID()" conts="ProcessorID">integer <anchor link="impl-shared.ProcessorID.0" hover="function: integer ProcessorID()">ProcessorID</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/AArch32.HaveHPDExt" mylink="shared.functions.extension.AArch32.HaveHPDExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.HaveHPDExt()</line>
<line>// ====================</line>
<line></line>
<line link="AArch32.HaveHPDExt.0" hover="function: boolean AArch32.HaveHPDExt()" conts="AArch32.HaveHPDExt">boolean <anchor link="AArch32.HaveHPDExt.0" hover="function: boolean AArch32.HaveHPDExt()">AArch32.HaveHPDExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_AA32HPD);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/AArch64.HaveHPDExt" mylink="shared.functions.extension.AArch64.HaveHPDExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.HaveHPDExt()</line>
<line>// ====================</line>
<line></line>
<line link="AArch64.HaveHPDExt.0" hover="function: boolean AArch64.HaveHPDExt()" conts="AArch64.HaveHPDExt">boolean <anchor link="AArch64.HaveHPDExt.0" hover="function: boolean AArch64.HaveHPDExt()">AArch64.HaveHPDExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_HPDS);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/Have128BitDescriptorExt" mylink="shared.functions.extension.Have128BitDescriptorExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Have128BitDescriptorExt()</line>
<line>// =========================</line>
<line>// Returns TRUE if 128-bit Descriptor extension</line>
<line>// support is implemented and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.Have128BitDescriptorExt.0" hover="function: boolean Have128BitDescriptorExt()" conts="Have128BitDescriptorExt">boolean <anchor link="impl-shared.Have128BitDescriptorExt.0" hover="function: boolean Have128BitDescriptorExt()">Have128BitDescriptorExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_D128);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/Have16bitVMID" mylink="shared.functions.extension.Have16bitVMID" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Have16bitVMID()</line>
<line>// ===============</line>
<line>// Returns TRUE if EL2 and support for a 16-bit VMID are implemented.</line>
<line></line>
<line link="impl-shared.Have16bitVMID.0" hover="function: boolean Have16bitVMID()" conts="Have16bitVMID">boolean <anchor link="impl-shared.Have16bitVMID.0" hover="function: boolean Have16bitVMID()">Have16bitVMID</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_VMID16);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/Have52BitIPAAndPASpaceExt" mylink="shared.functions.extension.Have52BitIPAAndPASpaceExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Have52BitIPAAndPASpaceExt()</line>
<line>// ===========================</line>
<line>// Returns TRUE if 52-bit IPA and PA extension support</line>
<line>// is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.Have52BitIPAAndPASpaceExt.0" hover="function: boolean Have52BitIPAAndPASpaceExt()" conts="Have52BitIPAAndPASpaceExt">boolean <anchor link="impl-shared.Have52BitIPAAndPASpaceExt.0" hover="function: boolean Have52BitIPAAndPASpaceExt()">Have52BitIPAAndPASpaceExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_LPA2);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/Have52BitPAExt" mylink="shared.functions.extension.Have52BitPAExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Have52BitPAExt()</line>
<line>// ================</line>
<line>// Returns TRUE if Large Physical Address extension</line>
<line>// support is implemented and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.Have52BitPAExt.0" hover="function: boolean Have52BitPAExt()" conts="Have52BitPAExt">boolean <anchor link="impl-shared.Have52BitPAExt.0" hover="function: boolean Have52BitPAExt()">Have52BitPAExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_LPA);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/Have52BitVAExt" mylink="shared.functions.extension.Have52BitVAExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Have52BitVAExt()</line>
<line>// ================</line>
<line>// Returns TRUE if Large Virtual Address extension</line>
<line>// support is implemented and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.Have52BitVAExt.0" hover="function: boolean Have52BitVAExt()" conts="Have52BitVAExt">boolean <anchor link="impl-shared.Have52BitVAExt.0" hover="function: boolean Have52BitVAExt()">Have52BitVAExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_LVA);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/Have56BitPAExt" mylink="shared.functions.extension.Have56BitPAExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Have56BitPAExt()</line>
<line>// ================</line>
<line>// Returns TRUE if 56-bit Physical Address extension</line>
<line>// support is implemented and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.Have56BitPAExt.0" hover="function: boolean Have56BitPAExt()" conts="Have56BitPAExt">boolean <anchor link="impl-shared.Have56BitPAExt.0" hover="function: boolean Have56BitPAExt()">Have56BitPAExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_D128);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/Have56BitVAExt" mylink="shared.functions.extension.Have56BitVAExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Have56BitVAExt()</line>
<line>// ================</line>
<line>// Returns TRUE if 56-bit Virtual Address extension</line>
<line>// support is implemented and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.Have56BitVAExt.0" hover="function: boolean Have56BitVAExt()" conts="Have56BitVAExt">boolean <anchor link="impl-shared.Have56BitVAExt.0" hover="function: boolean Have56BitVAExt()">Have56BitVAExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_LVA3);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveAArch32BF16Ext" mylink="shared.functions.extension.HaveAArch32BF16Ext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveAArch32BF16Ext()</line>
<line>// ====================</line>
<line>// Returns TRUE if AArch32 BFloat16 instruction support is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveAArch32BF16Ext.0" hover="function: boolean HaveAArch32BF16Ext()" conts="HaveAArch32BF16Ext">boolean <anchor link="impl-shared.HaveAArch32BF16Ext.0" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_AA32BF16);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveAArch32Int8MatMulExt" mylink="shared.functions.extension.HaveAArch32Int8MatMulExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveAArch32Int8MatMulExt()</line>
<line>// ==========================</line>
<line>// Returns TRUE if AArch32 8-bit integer matrix multiply instruction support</line>
<line>// implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveAArch32Int8MatMulExt.0" hover="function: boolean HaveAArch32Int8MatMulExt()" conts="HaveAArch32Int8MatMulExt">boolean <anchor link="impl-shared.HaveAArch32Int8MatMulExt.0" hover="function: boolean HaveAArch32Int8MatMulExt()">HaveAArch32Int8MatMulExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_AA32I8MM);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveAIEExt" mylink="shared.functions.extension.HaveAIEExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveAIEExt()</line>
<line>// ============</line>
<line>// Returns TRUE if AIE extension</line>
<line>// support is implemented and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveAIEExt.0" hover="function: boolean HaveAIEExt()" conts="HaveAIEExt">boolean <anchor link="impl-shared.HaveAIEExt.0" hover="function: boolean HaveAIEExt()">HaveAIEExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_AIE);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveAccessFlagUpdateExt" mylink="shared.functions.extension.HaveAccessFlagUpdateExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveAccessFlagUpdateExt()</line>
<line>// =========================</line>
<line></line>
<line link="impl-shared.HaveAccessFlagUpdateExt.0" hover="function: boolean HaveAccessFlagUpdateExt()" conts="HaveAccessFlagUpdateExt">boolean <anchor link="impl-shared.HaveAccessFlagUpdateExt.0" hover="function: boolean HaveAccessFlagUpdateExt()">HaveAccessFlagUpdateExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_HAFDBS);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveAccessFlagUpdateForTableExt" mylink="shared.functions.extension.HaveAccessFlagUpdateForTableExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveAccessFlagUpdateForTableExt()</line>
<line>// =================================</line>
<line>// Returns TRUE if support for Access Flag Update for Table Descriptors</line>
<line>// is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveAccessFlagUpdateForTableExt.0" hover="function: boolean HaveAccessFlagUpdateForTableExt()" conts="HaveAccessFlagUpdateForTableExt">boolean <anchor link="impl-shared.HaveAccessFlagUpdateForTableExt.0" hover="function: boolean HaveAccessFlagUpdateForTableExt()">HaveAccessFlagUpdateForTableExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_HAFT);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveAltFP" mylink="shared.functions.extension.HaveAltFP" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveAltFP()</line>
<line>// ===========</line>
<line>// Returns TRUE if alternative Floating-point extension support</line>
<line>// is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveAltFP.0" hover="function: boolean HaveAltFP()" conts="HaveAltFP">boolean <anchor link="impl-shared.HaveAltFP.0" hover="function: boolean HaveAltFP()">HaveAltFP</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_AFP);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveAtomicExt" mylink="shared.functions.extension.HaveAtomicExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveAtomicExt()</line>
<line>// ===============</line>
<line></line>
<line link="impl-shared.HaveAtomicExt.0" hover="function: boolean HaveAtomicExt()" conts="HaveAtomicExt">boolean <anchor link="impl-shared.HaveAtomicExt.0" hover="function: boolean HaveAtomicExt()">HaveAtomicExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_LSE);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveBF16Ext" mylink="shared.functions.extension.HaveBF16Ext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveBF16Ext()</line>
<line>// =============</line>
<line>// Returns TRUE if AArch64 BFloat16 instruction support is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveBF16Ext.0" hover="function: boolean HaveBF16Ext()" conts="HaveBF16Ext">boolean <anchor link="impl-shared.HaveBF16Ext.0" hover="function: boolean HaveBF16Ext()">HaveBF16Ext</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_BF16);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveBRBEv1p1" mylink="shared.functions.extension.HaveBRBEv1p1" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveBRBEv1p1()</line>
<line>// ==============</line>
<line>// Returns TRUE if BRBEv1p1 extension is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveBRBEv1p1.0" hover="function: boolean HaveBRBEv1p1()" conts="HaveBRBEv1p1">boolean <anchor link="impl-shared.HaveBRBEv1p1.0" hover="function: boolean HaveBRBEv1p1()">HaveBRBEv1p1</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_BRBEv1p1);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveBRBExt" mylink="shared.functions.extension.HaveBRBExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveBRBExt()</line>
<line>// ============</line>
<line>// Returns TRUE if Branch Record Buffer Extension is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveBRBExt.0" hover="function: boolean HaveBRBExt()" conts="HaveBRBExt">boolean <anchor link="impl-shared.HaveBRBExt.0" hover="function: boolean HaveBRBExt()">HaveBRBExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_BRBE);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveBTIExt" mylink="shared.functions.extension.HaveBTIExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveBTIExt()</line>
<line>// ============</line>
<line>// Returns TRUE if support for Branch Target Indentification is implemented.</line>
<line></line>
<line link="impl-shared.HaveBTIExt.0" hover="function: boolean HaveBTIExt()" conts="HaveBTIExt">boolean <anchor link="impl-shared.HaveBTIExt.0" hover="function: boolean HaveBTIExt()">HaveBTIExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_BTI);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveBlockBBM" mylink="shared.functions.extension.HaveBlockBBM" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveBlockBBM()</line>
<line>// ==============</line>
<line>// Returns TRUE if support for changing block size without requiring</line>
<line>// break-before-make is implemented.</line>
<line></line>
<line link="impl-shared.HaveBlockBBM.0" hover="function: boolean HaveBlockBBM()" conts="HaveBlockBBM">boolean <anchor link="impl-shared.HaveBlockBBM.0" hover="function: boolean HaveBlockBBM()">HaveBlockBBM</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_BBM);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveCNTSCExt" mylink="shared.functions.extension.HaveCNTSCExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveCNTSCExt()</line>
<line>// ==============</line>
<line>// Returns TRUE if the Generic Counter Scaling is implemented, and FALSE</line>
<line>// otherwise.</line>
<line></line>
<line link="impl-shared.HaveCNTSCExt.0" hover="function: boolean HaveCNTSCExt()" conts="HaveCNTSCExt">boolean <anchor link="impl-shared.HaveCNTSCExt.0" hover="function: boolean HaveCNTSCExt()">HaveCNTSCExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_CNTSC);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveCSSC" mylink="shared.functions.extension.HaveCSSC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveCSSC()</line>
<line>// ==========</line>
<line>// Returns TRUE if the Common Short Sequence Compression instructions extension is implemented,</line>
<line>// and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveCSSC.0" hover="function: boolean HaveCSSC()" conts="HaveCSSC">boolean <anchor link="impl-shared.HaveCSSC.0" hover="function: boolean HaveCSSC()">HaveCSSC</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_CSSC);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveCommonNotPrivateTransExt" mylink="shared.functions.extension.HaveCommonNotPrivateTransExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveCommonNotPrivateTransExt()</line>
<line>// ==============================</line>
<line></line>
<line link="impl-shared.HaveCommonNotPrivateTransExt.0" hover="function: boolean HaveCommonNotPrivateTransExt()" conts="HaveCommonNotPrivateTransExt">boolean <anchor link="impl-shared.HaveCommonNotPrivateTransExt.0" hover="function: boolean HaveCommonNotPrivateTransExt()">HaveCommonNotPrivateTransExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_TTCNP);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveDGHExt" mylink="shared.functions.extension.HaveDGHExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveDGHExt()</line>
<line>// ============</line>
<line>// Returns TRUE if Data Gathering Hint instruction support is implemented, and</line>
<line>// FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveDGHExt.0" hover="function: boolean HaveDGHExt()" conts="HaveDGHExt">boolean <anchor link="impl-shared.HaveDGHExt.0" hover="function: boolean HaveDGHExt()">HaveDGHExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_DGH);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveDITExt" mylink="shared.functions.extension.HaveDITExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveDITExt()</line>
<line>// ============</line>
<line></line>
<line link="impl-shared.HaveDITExt.0" hover="function: boolean HaveDITExt()" conts="HaveDITExt">boolean <anchor link="impl-shared.HaveDITExt.0" hover="function: boolean HaveDITExt()">HaveDITExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_DIT);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveDOTPExt" mylink="shared.functions.extension.HaveDOTPExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveDOTPExt()</line>
<line>// =============</line>
<line>// Returns TRUE if Dot Product feature support is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveDOTPExt.0" hover="function: boolean HaveDOTPExt()" conts="HaveDOTPExt">boolean <anchor link="impl-shared.HaveDOTPExt.0" hover="function: boolean HaveDOTPExt()">HaveDOTPExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_DotProd);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveDirtyBitModifierExt" mylink="shared.functions.extension.HaveDirtyBitModifierExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveDirtyBitModifierExt()</line>
<line>// =========================</line>
<line></line>
<line link="impl-shared.HaveDirtyBitModifierExt.0" hover="function: boolean HaveDirtyBitModifierExt()" conts="HaveDirtyBitModifierExt">boolean <anchor link="impl-shared.HaveDirtyBitModifierExt.0" hover="function: boolean HaveDirtyBitModifierExt()">HaveDirtyBitModifierExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_HAFDBS);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveDoPD" mylink="shared.functions.extension.HaveDoPD" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveDoPD()</line>
<line>// ==========</line>
<line>// Returns TRUE if Debug Over Power Down extension</line>
<line>// support is implemented and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveDoPD.0" hover="function: boolean HaveDoPD()" conts="HaveDoPD">boolean <anchor link="impl-shared.HaveDoPD.0" hover="function: boolean HaveDoPD()">HaveDoPD</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_DoPD);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveDoubleFault2Ext" mylink="shared.functions.extension.HaveDoubleFault2Ext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveDoubleFault2Ext()</line>
<line>// =====================</line>
<line>// Returns TRUE if support for the DoubleFault2 feature is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveDoubleFault2Ext.0" hover="function: boolean HaveDoubleFault2Ext()" conts="HaveDoubleFault2Ext">boolean <anchor link="impl-shared.HaveDoubleFault2Ext.0" hover="function: boolean HaveDoubleFault2Ext()">HaveDoubleFault2Ext</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_DoubleFault2);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveDoubleFaultExt" mylink="shared.functions.extension.HaveDoubleFaultExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveDoubleFaultExt()</line>
<line>// ====================</line>
<line></line>
<line link="impl-shared.HaveDoubleFaultExt.0" hover="function: boolean HaveDoubleFaultExt()" conts="HaveDoubleFaultExt">boolean <anchor link="impl-shared.HaveDoubleFaultExt.0" hover="function: boolean HaveDoubleFaultExt()">HaveDoubleFaultExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_DoubleFault);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveDoubleLock" mylink="shared.functions.extension.HaveDoubleLock" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveDoubleLock()</line>
<line>// ================</line>
<line>// Returns TRUE if support for the OS Double Lock is implemented.</line>
<line></line>
<line link="impl-shared.HaveDoubleLock.0" hover="function: boolean HaveDoubleLock()" conts="HaveDoubleLock">boolean <anchor link="impl-shared.HaveDoubleLock.0" hover="function: boolean HaveDoubleLock()">HaveDoubleLock</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_DoubleLock);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveE0PDExt" mylink="shared.functions.extension.HaveE0PDExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveE0PDExt()</line>
<line>// =============</line>
<line>// Returns TRUE if support for constant fault times for unprivileged accesses</line>
<line>// to the memory map is implemented.</line>
<line></line>
<line link="impl-shared.HaveE0PDExt.0" hover="function: boolean HaveE0PDExt()" conts="HaveE0PDExt">boolean <anchor link="impl-shared.HaveE0PDExt.0" hover="function: boolean HaveE0PDExt()">HaveE0PDExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_E0PD);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveEBF16" mylink="shared.functions.extension.HaveEBF16" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveEBF16()</line>
<line>// ===========</line>
<line>// Returns TRUE if the EBF16 extension is implemented, FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveEBF16.0" hover="function: boolean HaveEBF16()" conts="HaveEBF16">boolean <anchor link="impl-shared.HaveEBF16.0" hover="function: boolean HaveEBF16()">HaveEBF16</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_EBF16);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveECVExt" mylink="shared.functions.extension.HaveECVExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveECVExt()</line>
<line>// ============</line>
<line>// Returns TRUE if Enhanced Counter Virtualization extension</line>
<line>// support is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveECVExt.0" hover="function: boolean HaveECVExt()" conts="HaveECVExt">boolean <anchor link="impl-shared.HaveECVExt.0" hover="function: boolean HaveECVExt()">HaveECVExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_ECV);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveETExt" mylink="shared.functions.extension.HaveETExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveETExt()</line>
<line>// ===========</line>
<line>// Returns TRUE if Embedded Trace Extension is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveETExt.0" hover="function: boolean HaveETExt()" conts="HaveETExt">boolean <anchor link="impl-shared.HaveETExt.0" hover="function: boolean HaveETExt()">HaveETExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_ETE);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveExtendedCacheSets" mylink="shared.functions.extension.HaveExtendedCacheSets" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveExtendedCacheSets()</line>
<line>// =======================</line>
<line></line>
<line link="impl-shared.HaveExtendedCacheSets.0" hover="function: boolean HaveExtendedCacheSets()" conts="HaveExtendedCacheSets">boolean <anchor link="impl-shared.HaveExtendedCacheSets.0" hover="function: boolean HaveExtendedCacheSets()">HaveExtendedCacheSets</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_CCIDX);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveExtendedECDebugEvents" mylink="shared.functions.extension.HaveExtendedECDebugEvents" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveExtendedECDebugEvents()</line>
<line>// ===========================</line>
<line></line>
<line link="impl-shared.HaveExtendedECDebugEvents.0" hover="function: boolean HaveExtendedECDebugEvents()" conts="HaveExtendedECDebugEvents">boolean <anchor link="impl-shared.HaveExtendedECDebugEvents.0" hover="function: boolean HaveExtendedECDebugEvents()">HaveExtendedECDebugEvents</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_Debugv8p2);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveExtendedExecuteNeverExt" mylink="shared.functions.extension.HaveExtendedExecuteNeverExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveExtendedExecuteNeverExt()</line>
<line>// =============================</line>
<line></line>
<line link="impl-shared.HaveExtendedExecuteNeverExt.0" hover="function: boolean HaveExtendedExecuteNeverExt()" conts="HaveExtendedExecuteNeverExt">boolean <anchor link="impl-shared.HaveExtendedExecuteNeverExt.0" hover="function: boolean HaveExtendedExecuteNeverExt()">HaveExtendedExecuteNeverExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_XNX);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFCADDExt" mylink="shared.functions.extension.HaveFCADDExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFCADDExt()</line>
<line>// ==============</line>
<line></line>
<line link="impl-shared.HaveFCADDExt.0" hover="function: boolean HaveFCADDExt()" conts="HaveFCADDExt">boolean <anchor link="impl-shared.HaveFCADDExt.0" hover="function: boolean HaveFCADDExt()">HaveFCADDExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_FCMA);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFGTExt" mylink="shared.functions.extension.HaveFGTExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFGTExt()</line>
<line>// ============</line>
<line>// Returns TRUE if Fine Grained Trap is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveFGTExt.0" hover="function: boolean HaveFGTExt()" conts="HaveFGTExt">boolean <anchor link="impl-shared.HaveFGTExt.0" hover="function: boolean HaveFGTExt()">HaveFGTExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_FGT);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFJCVTZSExt" mylink="shared.functions.extension.HaveFJCVTZSExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFJCVTZSExt()</line>
<line>// ================</line>
<line></line>
<line link="impl-shared.HaveFJCVTZSExt.0" hover="function: boolean HaveFJCVTZSExt()" conts="HaveFJCVTZSExt">boolean <anchor link="impl-shared.HaveFJCVTZSExt.0" hover="function: boolean HaveFJCVTZSExt()">HaveFJCVTZSExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_JSCVT);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFP16MulNoRoundingToFP32Ext" mylink="shared.functions.extension.HaveFP16MulNoRoundingToFP32Ext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFP16MulNoRoundingToFP32Ext()</line>
<line>// ================================</line>
<line>// Returns TRUE if has FP16 multiply with no intermediate rounding accumulate</line>
<line>// to FP32 instructions, and FALSE otherwise</line>
<line></line>
<line link="impl-shared.HaveFP16MulNoRoundingToFP32Ext.0" hover="function: boolean HaveFP16MulNoRoundingToFP32Ext()" conts="HaveFP16MulNoRoundingToFP32Ext">boolean <anchor link="impl-shared.HaveFP16MulNoRoundingToFP32Ext.0" hover="function: boolean HaveFP16MulNoRoundingToFP32Ext()">HaveFP16MulNoRoundingToFP32Ext</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_FHM);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFeatCLRBHB" mylink="shared.functions.extension.HaveFeatCLRBHB" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFeatCLRBHB()</line>
<line>// ================</line>
<line>// Returns TRUE if the CLRBHB instruction is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveFeatCLRBHB.0" hover="function: boolean HaveFeatCLRBHB()" conts="HaveFeatCLRBHB">boolean <anchor link="impl-shared.HaveFeatCLRBHB.0" hover="function: boolean HaveFeatCLRBHB()">HaveFeatCLRBHB</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_CLRBHB);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFeatCMOW" mylink="shared.functions.extension.HaveFeatCMOW" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFeatCMOW()</line>
<line>// ==============</line>
<line>// Returns TRUE if the SCTLR_EL1.CMOW bit is implemented and the SCTLR_EL2.CMOW and</line>
<line>// HCRX_EL2.CMOW bits are implemented if EL2 is implemented.</line>
<line></line>
<line link="impl-shared.HaveFeatCMOW.0" hover="function: boolean HaveFeatCMOW()" conts="HaveFeatCMOW">boolean <anchor link="impl-shared.HaveFeatCMOW.0" hover="function: boolean HaveFeatCMOW()">HaveFeatCMOW</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_CMOW);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFeatEBEP" mylink="shared.functions.extension.HaveFeatEBEP" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFeatEBEP()</line>
<line>// ==============</line>
<line>// Returns TRUE if the PMU exception is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveFeatEBEP.0" hover="function: boolean HaveFeatEBEP()" conts="HaveFeatEBEP">boolean <anchor link="impl-shared.HaveFeatEBEP.0" hover="function: boolean HaveFeatEBEP()">HaveFeatEBEP</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_EBEP);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFeatHBC" mylink="shared.functions.extension.HaveFeatHBC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFeatHBC()</line>
<line>// =============</line>
<line>// Returns TRUE if the BC instruction is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveFeatHBC.0" hover="function: boolean HaveFeatHBC()" conts="HaveFeatHBC">boolean <anchor link="impl-shared.HaveFeatHBC.0" hover="function: boolean HaveFeatHBC()">HaveFeatHBC</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_HBC);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFeatHCX" mylink="shared.functions.extension.HaveFeatHCX" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFeatHCX()</line>
<line>// =============</line>
<line>// Returns TRUE if HCRX_EL2 Trap Control register is implemented,</line>
<line>// and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveFeatHCX.0" hover="function: boolean HaveFeatHCX()" conts="HaveFeatHCX">boolean <anchor link="impl-shared.HaveFeatHCX.0" hover="function: boolean HaveFeatHCX()">HaveFeatHCX</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_HCX);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFeatHPMN0" mylink="shared.functions.extension.HaveFeatHPMN0" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFeatHPMN0()</line>
<line>// ===============</line>
<line>// Returns TRUE if HDCR.HPMN or MDCR_EL2.HPMN is permitted to be 0 without</line>
<line>// generating UNPREDICTABLE behavior, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveFeatHPMN0.0" hover="function: boolean HaveFeatHPMN0()" conts="HaveFeatHPMN0">boolean <anchor link="impl-shared.HaveFeatHPMN0.0" hover="function: boolean HaveFeatHPMN0()">HaveFeatHPMN0</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_HPMN0);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFeatLS64" mylink="shared.functions.extension.HaveFeatLS64" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFeatLS64()</line>
<line>// ==============</line>
<line>// Returns TRUE if the LD64B, ST64B instructions are</line>
<line>// supported, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveFeatLS64.0" hover="function: boolean HaveFeatLS64()" conts="HaveFeatLS64">boolean <anchor link="impl-shared.HaveFeatLS64.0" hover="function: boolean HaveFeatLS64()">HaveFeatLS64</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_LS64);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFeatLS64_ACCDATA" mylink="shared.functions.extension.HaveFeatLS64_ACCDATA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFeatLS64_ACCDATA()</line>
<line>// ======================</line>
<line>// Returns TRUE if the ST64BV0 instruction is</line>
<line>// supported, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveFeatLS64_ACCDATA.0" hover="function: boolean HaveFeatLS64_ACCDATA()" conts="HaveFeatLS64_ACCDATA">boolean <anchor link="impl-shared.HaveFeatLS64_ACCDATA.0" hover="function: boolean HaveFeatLS64_ACCDATA()">HaveFeatLS64_ACCDATA</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_LS64_ACCDATA);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFeatLS64_V" mylink="shared.functions.extension.HaveFeatLS64_V" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFeatLS64_V()</line>
<line>// ================</line>
<line>// Returns TRUE if the ST64BV instruction is</line>
<line>// supported, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveFeatLS64_V.0" hover="function: boolean HaveFeatLS64_V()" conts="HaveFeatLS64_V">boolean <anchor link="impl-shared.HaveFeatLS64_V.0" hover="function: boolean HaveFeatLS64_V()">HaveFeatLS64_V</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_LS64_V);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFeatMEC" mylink="shared.functions.extension.HaveFeatMEC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFeatMEC()</line>
<line>// =============</line>
<line>// Returns TRUE if Memory Encryption Contexts are implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveFeatMEC.0" hover="function: boolean HaveFeatMEC()" conts="HaveFeatMEC">boolean <anchor link="impl-shared.HaveFeatMEC.0" hover="function: boolean HaveFeatMEC()">HaveFeatMEC</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_MEC);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFeatMOPS" mylink="shared.functions.extension.HaveFeatMOPS" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFeatMOPS()</line>
<line>// ==============</line>
<line>// Returns TRUE if the CPY* and SET* instructions are supported, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveFeatMOPS.0" hover="function: boolean HaveFeatMOPS()" conts="HaveFeatMOPS">boolean <anchor link="impl-shared.HaveFeatMOPS.0" hover="function: boolean HaveFeatMOPS()">HaveFeatMOPS</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_MOPS);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFeatNMI" mylink="shared.functions.extension.HaveFeatNMI" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFeatNMI()</line>
<line>// =============</line>
<line>// Returns TRUE if the Non-Maskable Interrupt extension is</line>
<line>// implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveFeatNMI.0" hover="function: boolean HaveFeatNMI()" conts="HaveFeatNMI">boolean <anchor link="impl-shared.HaveFeatNMI.0" hover="function: boolean HaveFeatNMI()">HaveFeatNMI</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_NMI);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFeatRPRES" mylink="shared.functions.extension.HaveFeatRPRES" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFeatRPRES()</line>
<line>// ===============</line>
<line>// Returns TRUE if reciprocal estimate implements 12-bit precision</line>
<line>// when FPCR.AH=1, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveFeatRPRES.0" hover="function: boolean HaveFeatRPRES()" conts="HaveFeatRPRES">boolean <anchor link="impl-shared.HaveFeatRPRES.0" hover="function: boolean HaveFeatRPRES()">HaveFeatRPRES</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_RPRES);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFeatSCTLR2" mylink="shared.functions.extension.HaveFeatSCTLR2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFeatSCTLR2()</line>
<line>// ================</line>
<line>// Returns TRUE if SCTLR2 extension</line>
<line>// support is implemented and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveFeatSCTLR2.0" hover="function: boolean HaveFeatSCTLR2()" conts="HaveFeatSCTLR2">boolean <anchor link="impl-shared.HaveFeatSCTLR2.0" hover="function: boolean HaveFeatSCTLR2()">HaveFeatSCTLR2</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SCTLR2);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFeatTCR2" mylink="shared.functions.extension.HaveFeatTCR2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFeatTCR2()</line>
<line>// ==============</line>
<line>// Returns TRUE if TCR2 extension</line>
<line>// support is implemented and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveFeatTCR2.0" hover="function: boolean HaveFeatTCR2()" conts="HaveFeatTCR2">boolean <anchor link="impl-shared.HaveFeatTCR2.0" hover="function: boolean HaveFeatTCR2()">HaveFeatTCR2</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_TCR2);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFeatTIDCP1" mylink="shared.functions.extension.HaveFeatTIDCP1" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFeatTIDCP1()</line>
<line>// ================</line>
<line>// Returns TRUE if the SCTLR_EL1.TIDCP bit is implemented and the SCTLR_EL2.TIDCP bit</line>
<line>// is implemented if EL2 is implemented.</line>
<line></line>
<line link="impl-shared.HaveFeatTIDCP1.0" hover="function: boolean HaveFeatTIDCP1()" conts="HaveFeatTIDCP1">boolean <anchor link="impl-shared.HaveFeatTIDCP1.0" hover="function: boolean HaveFeatTIDCP1()">HaveFeatTIDCP1</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_TIDCP1);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFeatTRBEExt" mylink="shared.functions.extension.HaveFeatTRBEExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFeatTRBEExt()</line>
<line>// =================</line>
<line>// Returns TRUE if the Trace Buffer Extension external mode is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveFeatTRBEExt.0" hover="function: boolean HaveFeatTRBEExt()" conts="HaveFeatTRBEExt">boolean <anchor link="impl-shared.HaveFeatTRBEExt.0" hover="function: boolean HaveFeatTRBEExt()">HaveFeatTRBEExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_TRBE_EXT);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFeatWFxT" mylink="shared.functions.extension.HaveFeatWFxT" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFeatWFxT()</line>
<line>// ==============</line>
<line>// Returns TRUE if WFET and WFIT instruction support is implemented,</line>
<line>// and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveFeatWFxT.0" hover="function: boolean HaveFeatWFxT()" conts="HaveFeatWFxT">boolean <anchor link="impl-shared.HaveFeatWFxT.0" hover="function: boolean HaveFeatWFxT()">HaveFeatWFxT</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_WFxT);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFeatXS" mylink="shared.functions.extension.HaveFeatXS" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFeatXS()</line>
<line>// ============</line>
<line>// Returns TRUE if XS attribute and the TLBI and DSB instructions with nXS qualifier</line>
<line>// are supported, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveFeatXS.0" hover="function: boolean HaveFeatXS()" conts="HaveFeatXS">boolean <anchor link="impl-shared.HaveFeatXS.0" hover="function: boolean HaveFeatXS()">HaveFeatXS</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_XS);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFlagFormatExt" mylink="shared.functions.extension.HaveFlagFormatExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFlagFormatExt()</line>
<line>// ===================</line>
<line>// Returns TRUE if flag format conversion instructions implemented.</line>
<line></line>
<line link="impl-shared.HaveFlagFormatExt.0" hover="function: boolean HaveFlagFormatExt()" conts="HaveFlagFormatExt">boolean <anchor link="impl-shared.HaveFlagFormatExt.0" hover="function: boolean HaveFlagFormatExt()">HaveFlagFormatExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_FlagM2);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFlagManipulateExt" mylink="shared.functions.extension.HaveFlagManipulateExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFlagManipulateExt()</line>
<line>// =======================</line>
<line>// Returns TRUE if flag manipulate instructions are implemented.</line>
<line></line>
<line link="impl-shared.HaveFlagManipulateExt.0" hover="function: boolean HaveFlagManipulateExt()" conts="HaveFlagManipulateExt">boolean <anchor link="impl-shared.HaveFlagManipulateExt.0" hover="function: boolean HaveFlagManipulateExt()">HaveFlagManipulateExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_FlagM);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveFrintExt" mylink="shared.functions.extension.HaveFrintExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFrintExt()</line>
<line>// ==============</line>
<line>// Returns TRUE if FRINT instructions are implemented.</line>
<line></line>
<line link="impl-shared.HaveFrintExt.0" hover="function: boolean HaveFrintExt()" conts="HaveFrintExt">boolean <anchor link="impl-shared.HaveFrintExt.0" hover="function: boolean HaveFrintExt()">HaveFrintExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_FRINTTS);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveGCS" mylink="shared.functions.extension.HaveGCS" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveGCS()</line>
<line>// =========</line>
<line>// Returns TRUE if support for Guarded Control Stack is</line>
<line>// implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveGCS.0" hover="function: boolean HaveGCS()" conts="HaveGCS">boolean <anchor link="impl-shared.HaveGCS.0" hover="function: boolean HaveGCS()">HaveGCS</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_GCS);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveGTGExt" mylink="shared.functions.extension.HaveGTGExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveGTGExt()</line>
<line>// ============</line>
<line>// Returns TRUE if support for guest translation granule size is implemented.</line>
<line></line>
<line link="impl-shared.HaveGTGExt.0" hover="function: boolean HaveGTGExt()" conts="HaveGTGExt">boolean <anchor link="impl-shared.HaveGTGExt.0" hover="function: boolean HaveGTGExt()">HaveGTGExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_GTG);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveHPMDExt" mylink="shared.functions.extension.HaveHPMDExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveHPMDExt()</line>
<line>// =============</line>
<line></line>
<line link="impl-shared.HaveHPMDExt.0" hover="function: boolean HaveHPMDExt()" conts="HaveHPMDExt">boolean <anchor link="impl-shared.HaveHPMDExt.0" hover="function: boolean HaveHPMDExt()">HaveHPMDExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_PMUv3p1);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveIDSExt" mylink="shared.functions.extension.HaveIDSExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveIDSExt()</line>
<line>// ============</line>
<line>// Returns TRUE if ID register handling feature is implemented.</line>
<line></line>
<line link="impl-shared.HaveIDSExt.0" hover="function: boolean HaveIDSExt()" conts="HaveIDSExt">boolean <anchor link="impl-shared.HaveIDSExt.0" hover="function: boolean HaveIDSExt()">HaveIDSExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_IDST);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveIESB" mylink="shared.functions.extension.HaveIESB" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveIESB()</line>
<line>// ==========</line>
<line></line>
<line link="impl-shared.HaveIESB.0" hover="function: boolean HaveIESB()" conts="HaveIESB">boolean <anchor link="impl-shared.HaveIESB.0" hover="function: boolean HaveIESB()">HaveIESB</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_IESB);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveInt8MatMulExt" mylink="shared.functions.extension.HaveInt8MatMulExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveInt8MatMulExt()</line>
<line>// ===================</line>
<line>// Returns TRUE if AArch64 8-bit integer matrix multiply instruction support</line>
<line>// implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveInt8MatMulExt.0" hover="function: boolean HaveInt8MatMulExt()" conts="HaveInt8MatMulExt">boolean <anchor link="impl-shared.HaveInt8MatMulExt.0" hover="function: boolean HaveInt8MatMulExt()">HaveInt8MatMulExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_I8MM);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveLRCPC3Ext" mylink="shared.functions.extension.HaveLRCPC3Ext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveLRCPC3Ext()</line>
<line>// ===============</line>
<line>// Returns TRUE if FEAT_LRCPC3 instructions are supported, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveLRCPC3Ext.0" hover="function: boolean HaveLRCPC3Ext()" conts="HaveLRCPC3Ext">boolean <anchor link="impl-shared.HaveLRCPC3Ext.0" hover="function: boolean HaveLRCPC3Ext()">HaveLRCPC3Ext</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_LRCPC3);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveLSE128" mylink="shared.functions.extension.HaveLSE128" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveLSE128()</line>
<line>// ============</line>
<line>// Returns TRUE if LSE128 is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveLSE128.0" hover="function: boolean HaveLSE128()" conts="HaveLSE128">boolean <anchor link="impl-shared.HaveLSE128.0" hover="function: boolean HaveLSE128()">HaveLSE128</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_LSE128);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveLSE2Ext" mylink="shared.functions.extension.HaveLSE2Ext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveLSE2Ext()</line>
<line>// =============</line>
<line>// Returns TRUE if LSE2 is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveLSE2Ext.0" hover="function: boolean HaveLSE2Ext()" conts="HaveLSE2Ext">boolean <anchor link="impl-shared.HaveLSE2Ext.0" hover="function: boolean HaveLSE2Ext()">HaveLSE2Ext</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_LSE2);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveMPAMExt" mylink="shared.functions.extension.HaveMPAMExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveMPAMExt()</line>
<line>// =============</line>
<line>// Returns TRUE if MPAM is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveMPAMExt.0" hover="function: boolean HaveMPAMExt()" conts="HaveMPAMExt">boolean <anchor link="impl-shared.HaveMPAMExt.0" hover="function: boolean HaveMPAMExt()">HaveMPAMExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_MPAM);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveMPAMv0p1Ext" mylink="shared.functions.extension.HaveMPAMv0p1Ext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveMPAMv0p1Ext()</line>
<line>// =================</line>
<line>// Returns TRUE if MPAMv0p1 is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveMPAMv0p1Ext.0" hover="function: boolean HaveMPAMv0p1Ext()" conts="HaveMPAMv0p1Ext">boolean <anchor link="impl-shared.HaveMPAMv0p1Ext.0" hover="function: boolean HaveMPAMv0p1Ext()">HaveMPAMv0p1Ext</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_MPAMv0p1);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveMPAMv1p1Ext" mylink="shared.functions.extension.HaveMPAMv1p1Ext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveMPAMv1p1Ext()</line>
<line>// =================</line>
<line>// Returns TRUE if MPAMv1p1 is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveMPAMv1p1Ext.0" hover="function: boolean HaveMPAMv1p1Ext()" conts="HaveMPAMv1p1Ext">boolean <anchor link="impl-shared.HaveMPAMv1p1Ext.0" hover="function: boolean HaveMPAMv1p1Ext()">HaveMPAMv1p1Ext</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_MPAMv1p1);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveMTE2Ext" mylink="shared.functions.extension.HaveMTE2Ext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveMTE2Ext()</line>
<line>// =============</line>
<line>// Returns TRUE if MTE support is beyond EL0, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveMTE2Ext.0" hover="function: boolean HaveMTE2Ext()" conts="HaveMTE2Ext">boolean <anchor link="impl-shared.HaveMTE2Ext.0" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_MTE2);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveMTE4Ext" mylink="shared.functions.extension.HaveMTE4Ext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveMTE4Ext()</line>
<line>// =============</line>
<line>// Returns TRUE if functionality in FEAT_MTE4 is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveMTE4Ext.0" hover="function: boolean HaveMTE4Ext()" conts="HaveMTE4Ext">boolean <anchor link="impl-shared.HaveMTE4Ext.0" hover="function: boolean HaveMTE4Ext()">HaveMTE4Ext</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_MTE4);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveMTEAsymFaultExt" mylink="shared.functions.extension.HaveMTEAsymFaultExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveMTEAsymFaultExt()</line>
<line>// =====================</line>
<line>// Returns TRUE if MTE Asymmetric Fault Handling support is</line>
<line>// implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveMTEAsymFaultExt.0" hover="function: boolean HaveMTEAsymFaultExt()" conts="HaveMTEAsymFaultExt">boolean <anchor link="impl-shared.HaveMTEAsymFaultExt.0" hover="function: boolean HaveMTEAsymFaultExt()">HaveMTEAsymFaultExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_MTE4);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveMTEAsyncExt" mylink="shared.functions.extension.HaveMTEAsyncExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveMTEAsyncExt()</line>
<line>// =================</line>
<line>// Returns TRUE if MTE supports Asynchronous faulting, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveMTEAsyncExt.0" hover="function: boolean HaveMTEAsyncExt()" conts="HaveMTEAsyncExt">boolean <anchor link="impl-shared.HaveMTEAsyncExt.0" hover="function: boolean HaveMTEAsyncExt()">HaveMTEAsyncExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_MTE4);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveMTECanonicalTagCheckingExt" mylink="shared.functions.extension.HaveMTECanonicalTagCheckingExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveMTECanonicalTagCheckingExt()</line>
<line>// ================================</line>
<line>// Returns TRUE if MTE Canonical Tag Checking functionality is</line>
<line>// implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveMTECanonicalTagCheckingExt.0" hover="function: boolean HaveMTECanonicalTagCheckingExt()" conts="HaveMTECanonicalTagCheckingExt">boolean <anchor link="impl-shared.HaveMTECanonicalTagCheckingExt.0" hover="function: boolean HaveMTECanonicalTagCheckingExt()">HaveMTECanonicalTagCheckingExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_MTE_CANONICAL_TAGS);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveMTEExt" mylink="shared.functions.extension.HaveMTEExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveMTEExt()</line>
<line>// ============</line>
<line>// Returns TRUE if instruction-only MTE implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveMTEExt.0" hover="function: boolean HaveMTEExt()" conts="HaveMTEExt">boolean <anchor link="impl-shared.HaveMTEExt.0" hover="function: boolean HaveMTEExt()">HaveMTEExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_MTE);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveMTEPermExt" mylink="shared.functions.extension.HaveMTEPermExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveMTEPermExt()</line>
<line>// ================</line>
<line>// Returns TRUE if MTE_PERM implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveMTEPermExt.0" hover="function: boolean HaveMTEPermExt()" conts="HaveMTEPermExt">boolean <anchor link="impl-shared.HaveMTEPermExt.0" hover="function: boolean HaveMTEPermExt()">HaveMTEPermExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_MTE_PERM);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveMTEStoreOnlyExt" mylink="shared.functions.extension.HaveMTEStoreOnlyExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveMTEStoreOnlyExt()</line>
<line>// =====================</line>
<line>// Returns TRUE if MTE Store-only Tag Checking functionality is</line>
<line>// implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveMTEStoreOnlyExt.0" hover="function: boolean HaveMTEStoreOnlyExt()" conts="HaveMTEStoreOnlyExt">boolean <anchor link="impl-shared.HaveMTEStoreOnlyExt.0" hover="function: boolean HaveMTEStoreOnlyExt()">HaveMTEStoreOnlyExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_MTE_STORE_ONLY);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveNV2Ext" mylink="shared.functions.extension.HaveNV2Ext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveNV2Ext()</line>
<line>// ============</line>
<line>// Returns TRUE if Enhanced Nested Virtualization is implemented.</line>
<line></line>
<line link="impl-shared.HaveNV2Ext.0" hover="function: boolean HaveNV2Ext()" conts="HaveNV2Ext">boolean <anchor link="impl-shared.HaveNV2Ext.0" hover="function: boolean HaveNV2Ext()">HaveNV2Ext</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_NV2);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveNVExt" mylink="shared.functions.extension.HaveNVExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveNVExt()</line>
<line>// ===========</line>
<line>// Returns TRUE if Nested Virtualization is implemented.</line>
<line></line>
<line link="impl-shared.HaveNVExt.0" hover="function: boolean HaveNVExt()" conts="HaveNVExt">boolean <anchor link="impl-shared.HaveNVExt.0" hover="function: boolean HaveNVExt()">HaveNVExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_NV);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveNoSecurePMUDisableOverride" mylink="shared.functions.extension.HaveNoSecurePMUDisableOverride" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveNoSecurePMUDisableOverride()</line>
<line>// ================================</line>
<line></line>
<line link="impl-shared.HaveNoSecurePMUDisableOverride.0" hover="function: boolean HaveNoSecurePMUDisableOverride()" conts="HaveNoSecurePMUDisableOverride">boolean <anchor link="impl-shared.HaveNoSecurePMUDisableOverride.0" hover="function: boolean HaveNoSecurePMUDisableOverride()">HaveNoSecurePMUDisableOverride</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_Debugv8p2);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveNoninvasiveDebugAuth" mylink="shared.functions.extension.HaveNoninvasiveDebugAuth" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveNoninvasiveDebugAuth()</line>
<line>// ==========================</line>
<line>// Returns TRUE if the Non-invasive debug controls are implemented.</line>
<line></line>
<line link="impl-shared.HaveNoninvasiveDebugAuth.0" hover="function: boolean HaveNoninvasiveDebugAuth()" conts="HaveNoninvasiveDebugAuth">boolean <anchor link="impl-shared.HaveNoninvasiveDebugAuth.0" hover="function: boolean HaveNoninvasiveDebugAuth()">HaveNoninvasiveDebugAuth</anchor>()</line>
<line>    return !IsFeatureImplemented(FEAT_Debugv8p4);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HavePAN3Ext" mylink="shared.functions.extension.HavePAN3Ext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HavePAN3Ext()</line>
<line>// =============</line>
<line>// Returns TRUE if SCTLR_EL1.EPAN and SCTLR_EL2.EPAN support is implemented,</line>
<line>// and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HavePAN3Ext.0" hover="function: boolean HavePAN3Ext()" conts="HavePAN3Ext">boolean <anchor link="impl-shared.HavePAN3Ext.0" hover="function: boolean HavePAN3Ext()">HavePAN3Ext</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_PAN3);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HavePANExt" mylink="shared.functions.extension.HavePANExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HavePANExt()</line>
<line>// ============</line>
<line></line>
<line link="impl-shared.HavePANExt.0" hover="function: boolean HavePANExt()" conts="HavePANExt">boolean <anchor link="impl-shared.HavePANExt.0" hover="function: boolean HavePANExt()">HavePANExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_PAN);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HavePFAR" mylink="shared.functions.extension.HavePFAR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HavePFAR()</line>
<line>// ==========</line>
<line>// Returns TRUE if the Physical Fault Address Extension is implemented, and FALSE</line>
<line>// otherwise.</line>
<line></line>
<line link="impl-shared.HavePFAR.0" hover="function: boolean HavePFAR()" conts="HavePFAR">boolean <anchor link="impl-shared.HavePFAR.0" hover="function: boolean HavePFAR()">HavePFAR</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_PFAR);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HavePMUv3" mylink="shared.functions.extension.HavePMUv3" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HavePMUv3()</line>
<line>// ===========</line>
<line>// Returns TRUE if the Performance Monitors extension is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HavePMUv3.0" hover="function: boolean HavePMUv3()" conts="HavePMUv3">boolean <anchor link="impl-shared.HavePMUv3.0" hover="function: boolean HavePMUv3()">HavePMUv3</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_PMUv3);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HavePMUv3EDGE" mylink="shared.functions.extension.HavePMUv3EDGE" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HavePMUv3EDGE()</line>
<line>// ===============</line>
<line>// Returns TRUE if support for PMU event edge detection is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HavePMUv3EDGE.0" hover="function: boolean HavePMUv3EDGE()" conts="HavePMUv3EDGE">boolean <anchor link="impl-shared.HavePMUv3EDGE.0" hover="function: boolean HavePMUv3EDGE()">HavePMUv3EDGE</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_PMUv3_EDGE);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HavePMUv3ICNTR" mylink="shared.functions.extension.HavePMUv3ICNTR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HavePMUv3ICNTR()</line>
<line>// ================</line>
<line>// Returns TRUE if support for the Fixed-function instruction counter is</line>
<line>// implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HavePMUv3ICNTR.0" hover="function: boolean HavePMUv3ICNTR()" conts="HavePMUv3ICNTR">boolean <anchor link="impl-shared.HavePMUv3ICNTR.0" hover="function: boolean HavePMUv3ICNTR()">HavePMUv3ICNTR</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_PMUv3_ICNTR);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HavePMUv3TH" mylink="shared.functions.extension.HavePMUv3TH" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HavePMUv3TH()</line>
<line>// =============</line>
<line>// Returns TRUE if the PMUv3 threshold extension is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HavePMUv3TH.0" hover="function: boolean HavePMUv3TH()" conts="HavePMUv3TH">boolean <anchor link="impl-shared.HavePMUv3TH.0" hover="function: boolean HavePMUv3TH()">HavePMUv3TH</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_PMUv3_TH);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HavePMUv3p1" mylink="shared.functions.extension.HavePMUv3p1" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HavePMUv3p1()</line>
<line>// =============</line>
<line>// Returns TRUE if the Performance Monitors extension is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HavePMUv3p1.0" hover="function: boolean HavePMUv3p1()" conts="HavePMUv3p1">boolean <anchor link="impl-shared.HavePMUv3p1.0" hover="function: boolean HavePMUv3p1()">HavePMUv3p1</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_PMUv3p1);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HavePMUv3p4" mylink="shared.functions.extension.HavePMUv3p4" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HavePMUv3p4()</line>
<line>// =============</line>
<line>// Returns TRUE if the PMUv3.4 extension is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HavePMUv3p4.0" hover="function: boolean HavePMUv3p4()" conts="HavePMUv3p4">boolean <anchor link="impl-shared.HavePMUv3p4.0" hover="function: boolean HavePMUv3p4()">HavePMUv3p4</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_PMUv3p4);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HavePMUv3p5" mylink="shared.functions.extension.HavePMUv3p5" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HavePMUv3p5()</line>
<line>// =============</line>
<line>// Returns TRUE if the PMUv3.5 extension is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HavePMUv3p5.0" hover="function: boolean HavePMUv3p5()" conts="HavePMUv3p5">boolean <anchor link="impl-shared.HavePMUv3p5.0" hover="function: boolean HavePMUv3p5()">HavePMUv3p5</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_PMUv3p5);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HavePMUv3p7" mylink="shared.functions.extension.HavePMUv3p7" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HavePMUv3p7()</line>
<line>// =============</line>
<line>// Returns TRUE if the PMUv3.7 extension is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HavePMUv3p7.0" hover="function: boolean HavePMUv3p7()" conts="HavePMUv3p7">boolean <anchor link="impl-shared.HavePMUv3p7.0" hover="function: boolean HavePMUv3p7()">HavePMUv3p7</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_PMUv3p7);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HavePMUv3p9" mylink="shared.functions.extension.HavePMUv3p9" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HavePMUv3p9()</line>
<line>// =============</line>
<line>// Returns TRUE if the PMUv3.9 extension is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HavePMUv3p9.0" hover="function: boolean HavePMUv3p9()" conts="HavePMUv3p9">boolean <anchor link="impl-shared.HavePMUv3p9.0" hover="function: boolean HavePMUv3p9()">HavePMUv3p9</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_PMUv3p9);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HavePageBasedHardwareAttributes" mylink="shared.functions.extension.HavePageBasedHardwareAttributes" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HavePageBasedHardwareAttributes()</line>
<line>// =================================</line>
<line></line>
<line link="impl-shared.HavePageBasedHardwareAttributes.0" hover="function: boolean HavePageBasedHardwareAttributes()" conts="HavePageBasedHardwareAttributes">boolean <anchor link="impl-shared.HavePageBasedHardwareAttributes.0" hover="function: boolean HavePageBasedHardwareAttributes()">HavePageBasedHardwareAttributes</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_HPDS2);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveQRDMLAHExt" mylink="shared.functions.extension.HaveQRDMLAHExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveQRDMLAHExt()</line>
<line>// ================</line>
<line></line>
<line link="impl-shared.HaveQRDMLAHExt.0" hover="function: boolean HaveQRDMLAHExt()" conts="HaveQRDMLAHExt">boolean <anchor link="impl-shared.HaveQRDMLAHExt.0" hover="function: boolean HaveQRDMLAHExt()">HaveQRDMLAHExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_RDM);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveRASExt" mylink="shared.functions.extension.HaveRASExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveRASExt()</line>
<line>// ============</line>
<line></line>
<line link="impl-shared.HaveRASExt.0" hover="function: boolean HaveRASExt()" conts="HaveRASExt">boolean <anchor link="impl-shared.HaveRASExt.0" hover="function: boolean HaveRASExt()">HaveRASExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_RAS);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveRASv2Ext" mylink="shared.functions.extension.HaveRASv2Ext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveRASv2Ext()</line>
<line>// ==============</line>
<line>// Returns TRUE if support for RASv2 is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveRASv2Ext.0" hover="function: boolean HaveRASv2Ext()" conts="HaveRASv2Ext">boolean <anchor link="impl-shared.HaveRASv2Ext.0" hover="function: boolean HaveRASv2Ext()">HaveRASv2Ext</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_RASv2);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveRME" mylink="shared.functions.extension.HaveRME" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveRME()</line>
<line>// =========</line>
<line>// Returns TRUE if the Realm Management Extension is implemented, and FALSE</line>
<line>// otherwise.</line>
<line></line>
<line link="impl-shared.HaveRME.0" hover="function: boolean HaveRME()" conts="HaveRME">boolean <anchor link="impl-shared.HaveRME.0" hover="function: boolean HaveRME()">HaveRME</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_RME);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveRNG" mylink="shared.functions.extension.HaveRNG" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveRNG()</line>
<line>// =========</line>
<line>// Returns TRUE if Random Number Generator extension</line>
<line>// support is implemented and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveRNG.0" hover="function: boolean HaveRNG()" conts="HaveRNG">boolean <anchor link="impl-shared.HaveRNG.0" hover="function: boolean HaveRNG()">HaveRNG</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_RNG);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveS1PIExt" mylink="shared.functions.extension.HaveS1PIExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveS1PIExt()</line>
<line>// =============</line>
<line>// Returns TRUE if the S1 Permission Indirection extension is</line>
<line>// implemented and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveS1PIExt.0" hover="function: boolean HaveS1PIExt()" conts="HaveS1PIExt">boolean <anchor link="impl-shared.HaveS1PIExt.0" hover="function: boolean HaveS1PIExt()">HaveS1PIExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_S1PIE);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveS1POExt" mylink="shared.functions.extension.HaveS1POExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveS1POExt()</line>
<line>// =============</line>
<line>// Returns TRUE if the S1 Permission Overlay extension is</line>
<line>// implemented and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveS1POExt.0" hover="function: boolean HaveS1POExt()" conts="HaveS1POExt">boolean <anchor link="impl-shared.HaveS1POExt.0" hover="function: boolean HaveS1POExt()">HaveS1POExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_S1POE);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveS2PIExt" mylink="shared.functions.extension.HaveS2PIExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveS2PIExt()</line>
<line>// =============</line>
<line>// Returns TRUE if the S2 Permission Indirection extension is</line>
<line>// implemented and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveS2PIExt.0" hover="function: boolean HaveS2PIExt()" conts="HaveS2PIExt">boolean <anchor link="impl-shared.HaveS2PIExt.0" hover="function: boolean HaveS2PIExt()">HaveS2PIExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_S2PIE);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveS2POExt" mylink="shared.functions.extension.HaveS2POExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveS2POExt()</line>
<line>// =============</line>
<line>// Returns TRUE if the S2 Permission Overlay extension is</line>
<line>// implemented and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveS2POExt.0" hover="function: boolean HaveS2POExt()" conts="HaveS2POExt">boolean <anchor link="impl-shared.HaveS2POExt.0" hover="function: boolean HaveS2POExt()">HaveS2POExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_S2POE);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveSBExt" mylink="shared.functions.extension.HaveSBExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSBExt()</line>
<line>// ===========</line>
<line>// Returns TRUE if support for SB is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveSBExt.0" hover="function: boolean HaveSBExt()" conts="HaveSBExt">boolean <anchor link="impl-shared.HaveSBExt.0" hover="function: boolean HaveSBExt()">HaveSBExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SB);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveSSBSExt" mylink="shared.functions.extension.HaveSSBSExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSSBSExt()</line>
<line>// =============</line>
<line>// Returns TRUE if support for SSBS is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveSSBSExt.0" hover="function: boolean HaveSSBSExt()" conts="HaveSSBSExt">boolean <anchor link="impl-shared.HaveSSBSExt.0" hover="function: boolean HaveSSBSExt()">HaveSSBSExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SSBS);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveSecureEL2Ext" mylink="shared.functions.extension.HaveSecureEL2Ext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSecureEL2Ext()</line>
<line>// ==================</line>
<line>// Returns TRUE if Secure EL2 is implemented.</line>
<line></line>
<line link="impl-shared.HaveSecureEL2Ext.0" hover="function: boolean HaveSecureEL2Ext()" conts="HaveSecureEL2Ext">boolean <anchor link="impl-shared.HaveSecureEL2Ext.0" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SEL2);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveSecureExtDebugView" mylink="shared.functions.extension.HaveSecureExtDebugView" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSecureExtDebugView()</line>
<line>// ========================</line>
<line>// Returns TRUE if support for Secure and Non-secure views of debug peripherals</line>
<line>// is implemented.</line>
<line></line>
<line link="impl-shared.HaveSecureExtDebugView.0" hover="function: boolean HaveSecureExtDebugView()" conts="HaveSecureExtDebugView">boolean <anchor link="impl-shared.HaveSecureExtDebugView.0" hover="function: boolean HaveSecureExtDebugView()">HaveSecureExtDebugView</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_Debugv8p4);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveSelfHostedTrace" mylink="shared.functions.extension.HaveSelfHostedTrace" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSelfHostedTrace()</line>
<line>// =====================</line>
<line></line>
<line link="impl-shared.HaveSelfHostedTrace.0" hover="function: boolean HaveSelfHostedTrace()" conts="HaveSelfHostedTrace">boolean <anchor link="impl-shared.HaveSelfHostedTrace.0" hover="function: boolean HaveSelfHostedTrace()">HaveSelfHostedTrace</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_TRF);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveSmallTranslationTblExt" mylink="shared.functions.extension.HaveSmallTranslationTblExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSmallTranslationTblExt()</line>
<line>// ============================</line>
<line>// Returns TRUE if Small Translation Table Support is implemented.</line>
<line></line>
<line link="impl-shared.HaveSmallTranslationTableExt.0" hover="function: boolean HaveSmallTranslationTableExt()" conts="HaveSmallTranslationTableExt">boolean <anchor link="impl-shared.HaveSmallTranslationTableExt.0" hover="function: boolean HaveSmallTranslationTableExt()">HaveSmallTranslationTableExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_TTST);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveSoftwareLock" mylink="shared.functions.extension.HaveSoftwareLock" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSoftwareLock()</line>
<line>// ==================</line>
<line>// Returns TRUE if Software Lock is implemented.</line>
<line></line>
<line link="impl-shared.HaveSoftwareLock.1" hover="function: boolean HaveSoftwareLock(Component component)" conts="HaveSoftwareLock">boolean <anchor link="impl-shared.HaveSoftwareLock.1" hover="function: boolean HaveSoftwareLock(Component component)">HaveSoftwareLock</anchor>(<a link="Component" file="shared_pseudocode.xml" hover="enumeration Component { Component_PMU, Component_Debug, Component_CTI }">Component</a> component)</line>
<line>    if <a link="impl-shared.Havev8p4Debug.0" file="shared_pseudocode.xml" hover="function: boolean Havev8p4Debug()">Havev8p4Debug</a>() then</line>
<line>        return FALSE;</line>
<line>    if <a link="impl-shared.HaveDoPD.0" file="shared_pseudocode.xml" hover="function: boolean HaveDoPD()">HaveDoPD</a>() &amp;&amp; component != <a link="Component_CTI" file="shared_pseudocode.xml" hover="enumeration Component { Component_PMU, Component_Debug, Component_CTI }">Component_CTI</a> then</line>
<line>        return FALSE;</line>
<line>    case component of</line>
<line>        when <a link="Component_Debug" file="shared_pseudocode.xml" hover="enumeration Component { Component_PMU, Component_Debug, Component_CTI }">Component_Debug</a></line>
<line>            return boolean IMPLEMENTATION_DEFINED "Debug has Software Lock";</line>
<line>        when <a link="Component_PMU" file="shared_pseudocode.xml" hover="enumeration Component { Component_PMU, Component_Debug, Component_CTI }">Component_PMU</a></line>
<line>            return boolean IMPLEMENTATION_DEFINED "PMU has Software Lock";</line>
<line>        when <a link="Component_CTI" file="shared_pseudocode.xml" hover="enumeration Component { Component_PMU, Component_Debug, Component_CTI }">Component_CTI</a></line>
<line>            return boolean IMPLEMENTATION_DEFINED "CTI has Software Lock";</line>
<line>        otherwise</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveStage2MemAttrControl" mylink="shared.functions.extension.HaveStage2MemAttrControl" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveStage2MemAttrControl()</line>
<line>// ==========================</line>
<line>// Returns TRUE if support for Stage2 control of memory types and cacheability</line>
<line>// attributes is implemented.</line>
<line></line>
<line link="impl-shared.HaveStage2MemAttrControl.0" hover="function: boolean HaveStage2MemAttrControl()" conts="HaveStage2MemAttrControl">boolean <anchor link="impl-shared.HaveStage2MemAttrControl.0" hover="function: boolean HaveStage2MemAttrControl()">HaveStage2MemAttrControl</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_S2FWB);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveStatisticalProfiling" mylink="shared.functions.extension.HaveStatisticalProfiling" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveStatisticalProfiling()</line>
<line>// ==========================</line>
<line>// Returns TRUE if Statistical Profiling Extension is implemented,</line>
<line>// and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveStatisticalProfiling.0" hover="function: boolean HaveStatisticalProfiling()" conts="HaveStatisticalProfiling">boolean <anchor link="impl-shared.HaveStatisticalProfiling.0" hover="function: boolean HaveStatisticalProfiling()">HaveStatisticalProfiling</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SPE);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveStatisticalProfilingFDS" mylink="shared.functions.extension.HaveStatisticalProfilingFDS" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveStatisticalProfilingFDS()</line>
<line>// =============================</line>
<line>// Returns TRUE if the SPE_FDS extension is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveStatisticalProfilingFDS.0" hover="function: boolean HaveStatisticalProfilingFDS()" conts="HaveStatisticalProfilingFDS">boolean <anchor link="impl-shared.HaveStatisticalProfilingFDS.0" hover="function: boolean HaveStatisticalProfilingFDS()">HaveStatisticalProfilingFDS</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SPE_FDS);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveStatisticalProfilingv1p1" mylink="shared.functions.extension.HaveStatisticalProfilingv1p1" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveStatisticalProfilingv1p1()</line>
<line>// ==============================</line>
<line>// Returns TRUE if the SPEv1p1 extension is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveStatisticalProfilingv1p1.0" hover="function: boolean HaveStatisticalProfilingv1p1()" conts="HaveStatisticalProfilingv1p1">boolean <anchor link="impl-shared.HaveStatisticalProfilingv1p1.0" hover="function: boolean HaveStatisticalProfilingv1p1()">HaveStatisticalProfilingv1p1</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SPEv1p1);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveStatisticalProfilingv1p2" mylink="shared.functions.extension.HaveStatisticalProfilingv1p2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveStatisticalProfilingv1p2()</line>
<line>// ==============================</line>
<line>// Returns TRUE if the SPEv1p2 extension is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveStatisticalProfilingv1p2.0" hover="function: boolean HaveStatisticalProfilingv1p2()" conts="HaveStatisticalProfilingv1p2">boolean <anchor link="impl-shared.HaveStatisticalProfilingv1p2.0" hover="function: boolean HaveStatisticalProfilingv1p2()">HaveStatisticalProfilingv1p2</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SPEv1p2);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveStatisticalProfilingv1p4" mylink="shared.functions.extension.HaveStatisticalProfilingv1p4" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveStatisticalProfilingv1p4()</line>
<line>// ==============================</line>
<line>// Returns TRUE if the SPEv1p4 extension is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveStatisticalProfilingv1p4.0" hover="function: boolean HaveStatisticalProfilingv1p4()" conts="HaveStatisticalProfilingv1p4">boolean <anchor link="impl-shared.HaveStatisticalProfilingv1p4.0" hover="function: boolean HaveStatisticalProfilingv1p4()">HaveStatisticalProfilingv1p4</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SPEv1p4);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveSysInstr128" mylink="shared.functions.extension.HaveSysInstr128" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSysInstr128()</line>
<line>// =================</line>
<line>// Returns TRUE if support for System Instructions that can</line>
<line>// take 128-bit inputs is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveSysInstr128.0" hover="function: boolean HaveSysInstr128()" conts="HaveSysInstr128">boolean <anchor link="impl-shared.HaveSysInstr128.0" hover="function: boolean HaveSysInstr128()">HaveSysInstr128</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SYSINSTR128);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveSysReg128" mylink="shared.functions.extension.HaveSysReg128" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSysReg128()</line>
<line>// ===============</line>
<line>// Returns TRUE if support for 128-bit System Registers is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveSysReg128.0" hover="function: boolean HaveSysReg128()" conts="HaveSysReg128">boolean <anchor link="impl-shared.HaveSysReg128.0" hover="function: boolean HaveSysReg128()">HaveSysReg128</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_SYSREG128);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveTHExt" mylink="shared.functions.extension.HaveTHExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveTHExt()</line>
<line>// ===========</line>
<line>// Returns TRUE if support for Translation Hardening Extension is implemented.</line>
<line></line>
<line link="impl-shared.HaveTHExt.0" hover="function: boolean HaveTHExt()" conts="HaveTHExt">boolean <anchor link="impl-shared.HaveTHExt.0" hover="function: boolean HaveTHExt()">HaveTHExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_THE);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveTME" mylink="shared.functions.extension.HaveTME" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveTME()</line>
<line>// =========</line>
<line></line>
<line link="impl-shared.HaveTME.0" hover="function: boolean HaveTME()" conts="HaveTME">boolean <anchor link="impl-shared.HaveTME.0" hover="function: boolean HaveTME()">HaveTME</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_TME);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveTWEDExt" mylink="shared.functions.extension.HaveTWEDExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveTWEDExt()</line>
<line>// =============</line>
<line>// Returns TRUE if Delayed Trapping of WFE instruction support is implemented,</line>
<line>// and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveTWEDExt.0" hover="function: boolean HaveTWEDExt()" conts="HaveTWEDExt">boolean <anchor link="impl-shared.HaveTWEDExt.0" hover="function: boolean HaveTWEDExt()">HaveTWEDExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_TWED);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveTraceBufferExtension" mylink="shared.functions.extension.HaveTraceBufferExtension" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveTraceBufferExtension()</line>
<line>// ==========================</line>
<line>// Returns TRUE if Trace Buffer Extension is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveTraceBufferExtension.0" hover="function: boolean HaveTraceBufferExtension()" conts="HaveTraceBufferExtension">boolean <anchor link="impl-shared.HaveTraceBufferExtension.0" hover="function: boolean HaveTraceBufferExtension()">HaveTraceBufferExtension</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_TRBE);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveTraceExt" mylink="shared.functions.extension.HaveTraceExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveTraceExt()</line>
<line>// ==============</line>
<line>// Returns TRUE if Trace functionality as described by the Trace Architecture</line>
<line>// is implemented.</line>
<line></line>
<line link="impl-shared.HaveTraceExt.0" hover="function: boolean HaveTraceExt()" conts="HaveTraceExt">boolean <anchor link="impl-shared.HaveTraceExt.0" hover="function: boolean HaveTraceExt()">HaveTraceExt</anchor>()</line>
<line>    return boolean IMPLEMENTATION_DEFINED "Has Trace Architecture functionality";</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveTrapLoadStoreMultipleDeviceExt" mylink="shared.functions.extension.HaveTrapLoadStoreMultipleDeviceExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveTrapLoadStoreMultipleDeviceExt()</line>
<line>// ====================================</line>
<line></line>
<line link="impl-shared.HaveTrapLoadStoreMultipleDeviceExt.0" hover="function: boolean HaveTrapLoadStoreMultipleDeviceExt()" conts="HaveTrapLoadStoreMultipleDeviceExt">boolean <anchor link="impl-shared.HaveTrapLoadStoreMultipleDeviceExt.0" hover="function: boolean HaveTrapLoadStoreMultipleDeviceExt()">HaveTrapLoadStoreMultipleDeviceExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_LSMAOC);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveUAOExt" mylink="shared.functions.extension.HaveUAOExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveUAOExt()</line>
<line>// ============</line>
<line></line>
<line link="impl-shared.HaveUAOExt.0" hover="function: boolean HaveUAOExt()" conts="HaveUAOExt">boolean <anchor link="impl-shared.HaveUAOExt.0" hover="function: boolean HaveUAOExt()">HaveUAOExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_UAO);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveV82Debug" mylink="shared.functions.extension.HaveV82Debug" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveV82Debug()</line>
<line>// ==============</line>
<line></line>
<line link="impl-shared.HaveV82Debug.0" hover="function: boolean HaveV82Debug()" conts="HaveV82Debug">boolean <anchor link="impl-shared.HaveV82Debug.0" hover="function: boolean HaveV82Debug()">HaveV82Debug</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_Debugv8p2);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/HaveVirtHostExt" mylink="shared.functions.extension.HaveVirtHostExt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveVirtHostExt()</line>
<line>// =================</line>
<line></line>
<line link="impl-shared.HaveVirtHostExt.0" hover="function: boolean HaveVirtHostExt()" conts="HaveVirtHostExt">boolean <anchor link="impl-shared.HaveVirtHostExt.0" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_VHE);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/Havev8p4Debug" mylink="shared.functions.extension.Havev8p4Debug" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Havev8p4Debug()</line>
<line>// ===============</line>
<line>// Returns TRUE if support for the Debugv8p4 feature is implemented and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.Havev8p4Debug.0" hover="function: boolean Havev8p4Debug()" conts="Havev8p4Debug">boolean <anchor link="impl-shared.Havev8p4Debug.0" hover="function: boolean Havev8p4Debug()">Havev8p4Debug</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_Debugv8p4);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/Havev8p8Debug" mylink="shared.functions.extension.Havev8p8Debug" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Havev8p8Debug()</line>
<line>// ===============</line>
<line>// Returns TRUE if support for the Debugv8p8 feature is implemented and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.Havev8p8Debug.0" hover="function: boolean Havev8p8Debug()" conts="Havev8p8Debug">boolean <anchor link="impl-shared.Havev8p8Debug.0" hover="function: boolean Havev8p8Debug()">Havev8p8Debug</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_Debugv8p8);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/Havev8p9Debug" mylink="shared.functions.extension.Havev8p9Debug" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Havev8p9Debug()</line>
<line>// ===============</line>
<line>// Returns TRUE if support for the Debugv8p9 feature is implemented, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.Havev8p9Debug.0" hover="function: boolean Havev8p9Debug()" conts="Havev8p9Debug">boolean <anchor link="impl-shared.Havev8p9Debug.0" hover="function: boolean Havev8p9Debug()">Havev8p9Debug</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_Debugv8p9);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/InsertIESBBeforeException" mylink="shared.functions.extension.InsertIESBBeforeException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// InsertIESBBeforeException()</line>
<line>// ===========================</line>
<line>// Returns an implementation defined choice whether to insert an implicit error synchronization</line>
<line>// barrier before exception.</line>
<line>// If SCTLR_ELx.IESB is 1 when an exception is generated to ELx, any pending Unrecoverable</line>
<line>// SError interrupt must be taken before executing any instructions in the exception handler.</line>
<line>// However, this can be before the branch to the exception handler is made.</line>
<line></line>
<line link="impl-shared.InsertIESBBeforeException.1" hover="function: boolean InsertIESBBeforeException(bits(2) el)" conts="InsertIESBBeforeException">boolean <anchor link="impl-shared.InsertIESBBeforeException.1" hover="function: boolean InsertIESBBeforeException(bits(2) el)">InsertIESBBeforeException</anchor>(bits(2) el)</line>
<line>    return (<a link="impl-shared.HaveIESB.0" file="shared_pseudocode.xml" hover="function: boolean HaveIESB()">HaveIESB</a>() &amp;&amp; boolean IMPLEMENTATION_DEFINED</line>
<line>            "Has Implicit Error Synchronization Barrier before <a link="Exception" file="shared_pseudocode.xml" hover="enumeration Exception { Exception_Uncategorized, Exception_WFxTrap, Exception_CP15RTTrap, Exception_CP15RRTTrap, Exception_CP14RTTrap, Exception_CP14DTTrap, Exception_CP14RRTTrap, Exception_AdvSIMDFPAccessTrap, Exception_FPIDTrap, Exception_LDST64BTrap,  Exception_PACTrap, Exception_IllegalState, Exception_SupervisorCall, Exception_HypervisorCall, Exception_MonitorCall, Exception_SystemRegisterTrap, Exception_ERetTrap, Exception_InstructionAbort, Exception_PCAlignment, Exception_DataAbort, Exception_NV2DataAbort, Exception_PACFail, Exception_SPAlignment, Exception_FPTrappedException, Exception_SError, Exception_Breakpoint, Exception_SoftwareStep, Exception_Watchpoint, Exception_NV2Watchpoint, Exception_SoftwareBreakpoint, Exception_VectorCatch, Exception_IRQ, Exception_SVEAccessTrap, Exception_SMEAccessTrap, Exception_TSTARTAccessTrap, Exception_GPC, Exception_BranchTarget, Exception_MemCpyMemSet, Exception_GCSFail, Exception_SystemRegister128Trap, Exception_FIQ}">Exception</a>");</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/IsG1ActivityMonitorImplemented" mylink="shared.functions.extension.IsG1ActivityMonitorImplemented" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsG1ActivityMonitorImplemented()</line>
<line>// ================================</line>
<line>// Returns TRUE if a G1 activity monitor is implemented for the counter</line>
<line>// and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.IsG1ActivityMonitorImplemented.1" hover="function: boolean IsG1ActivityMonitorImplemented(integer i)" conts="IsG1ActivityMonitorImplemented">boolean <anchor link="impl-shared.IsG1ActivityMonitorImplemented.1" hover="function: boolean IsG1ActivityMonitorImplemented(integer i)">IsG1ActivityMonitorImplemented</anchor>(integer i);</line>
</pstext>
    </ps>
    <ps name="shared/functions/extension/IsG1ActivityMonitorOffsetImplemented" mylink="shared.functions.extension.IsG1ActivityMonitorOffsetImplemented" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsG1ActivityMonitorOffsetImplemented()</line>
<line>// ======================================</line>
<line>// Returns TRUE if a G1 activity monitor offset is implemented for the counter,</line>
<line>// and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.IsG1ActivityMonitorOffsetImplemented.1" hover="function: boolean IsG1ActivityMonitorOffsetImplemented(integer i)" conts="IsG1ActivityMonitorOffsetImplemented">boolean <anchor link="impl-shared.IsG1ActivityMonitorOffsetImplemented.1" hover="function: boolean IsG1ActivityMonitorOffsetImplemented(integer i)">IsG1ActivityMonitorOffsetImplemented</anchor>(integer i);</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/AArch32.PEErrorState" mylink="shared.functions.externalaborts.AArch32.PEErrorState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch32.PEErrorState()</line>
<line>// ======================</line>
<line>// Returns the error state by PE on taking an SError Interrupt</line>
<line>// to AArch32 level.</line>
<line></line>
<line link="AArch32.PEErrorState.1" hover="function: ErrorState AArch32.PEErrorState(FaultRecord fault)" conts="AArch32.PEErrorState">ErrorState <anchor link="AArch32.PEErrorState.1" hover="function: ErrorState AArch32.PEErrorState(FaultRecord fault)">AArch32.PEErrorState</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    if (!<a link="impl-shared.ErrorIsContained.0" file="shared_pseudocode.xml" hover="function: boolean ErrorIsContained()">ErrorIsContained</a>() ||</line>
<line>        (!<a link="impl-shared.ErrorIsSynchronized.0" file="shared_pseudocode.xml" hover="function: boolean ErrorIsSynchronized()">ErrorIsSynchronized</a>() &amp;&amp; !<a link="impl-shared.StateIsRecoverable.0" file="shared_pseudocode.xml" hover="function: boolean StateIsRecoverable()">StateIsRecoverable</a>()) ||</line>
<line>         <a link="impl-shared.ReportErrorAsUC.0" file="shared_pseudocode.xml" hover="function: boolean ReportErrorAsUC()">ReportErrorAsUC</a>()) then</line>
<line>        return <a link="ErrorState_UC" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UC</a>;</line>
<line></line>
<line>    if !<a link="impl-shared.StateIsRecoverable.0" file="shared_pseudocode.xml" hover="function: boolean StateIsRecoverable()">StateIsRecoverable</a>() || <a link="impl-shared.ReportErrorAsUEU.0" file="shared_pseudocode.xml" hover="function: boolean ReportErrorAsUEU()">ReportErrorAsUEU</a>() then</line>
<line>        return <a link="ErrorState_UEU" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UEU</a>;</line>
<line></line>
<line>    if <a link="impl-shared.ActionRequired.0" file="shared_pseudocode.xml" hover="function: boolean ActionRequired()">ActionRequired</a>() || <a link="impl-shared.ReportErrorAsUER.0" file="shared_pseudocode.xml" hover="function: boolean ReportErrorAsUER()">ReportErrorAsUER</a>() then</line>
<line>        return <a link="ErrorState_UER" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UER</a>;</line>
<line></line>
<line>    return <a link="ErrorState_UEO" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UEO</a>;</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/AArch64.PEErrorState" mylink="shared.functions.externalaborts.AArch64.PEErrorState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.PEErrorState()</line>
<line>// ======================</line>
<line>// Returns the error state by PE on taking a Synchronous</line>
<line>// or Asynchronous exception.</line>
<line></line>
<line link="AArch64.PEErrorState.1" hover="function: ErrorState AArch64.PEErrorState(FaultRecord fault)" conts="AArch64.PEErrorState">ErrorState <anchor link="AArch64.PEErrorState.1" hover="function: ErrorState AArch64.PEErrorState(FaultRecord fault)">AArch64.PEErrorState</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    if !<a link="impl-shared.IsExternalSyncAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalSyncAbort(Fault statuscode)">IsExternalSyncAbort</a>(fault) &amp;&amp; <a link="impl-shared.ExtAbortToA64.1" file="shared_pseudocode.xml" hover="function: boolean ExtAbortToA64(FaultRecord fault)">ExtAbortToA64</a>(fault) then</line>
<line>        if <a link="impl-shared.ReportErrorAsUncategorized.0" file="shared_pseudocode.xml" hover="function: boolean ReportErrorAsUncategorized()">ReportErrorAsUncategorized</a>() then</line>
<line>            return <a link="ErrorState_Uncategorized" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_Uncategorized</a>;</line>
<line>        if <a link="impl-shared.ReportErrorAsIMPDEF.0" file="shared_pseudocode.xml" hover="function: boolean ReportErrorAsIMPDEF()">ReportErrorAsIMPDEF</a>() then</line>
<line>            return <a link="ErrorState_IMPDEF" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_IMPDEF</a>;</line>
<line></line>
<line>    assert !<a link="impl-shared.FaultIsCorrected.0" file="shared_pseudocode.xml" hover="function: boolean FaultIsCorrected()">FaultIsCorrected</a>();</line>
<line>    if (!<a link="impl-shared.ErrorIsContained.0" file="shared_pseudocode.xml" hover="function: boolean ErrorIsContained()">ErrorIsContained</a>() ||</line>
<line>        (!<a link="impl-shared.ErrorIsSynchronized.0" file="shared_pseudocode.xml" hover="function: boolean ErrorIsSynchronized()">ErrorIsSynchronized</a>() &amp;&amp; !<a link="impl-shared.StateIsRecoverable.0" file="shared_pseudocode.xml" hover="function: boolean StateIsRecoverable()">StateIsRecoverable</a>()) ||</line>
<line>         <a link="impl-shared.ReportErrorAsUC.0" file="shared_pseudocode.xml" hover="function: boolean ReportErrorAsUC()">ReportErrorAsUC</a>()) then</line>
<line>        return <a link="ErrorState_UC" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UC</a>;</line>
<line></line>
<line>    if !<a link="impl-shared.StateIsRecoverable.0" file="shared_pseudocode.xml" hover="function: boolean StateIsRecoverable()">StateIsRecoverable</a>() || <a link="impl-shared.ReportErrorAsUEU.0" file="shared_pseudocode.xml" hover="function: boolean ReportErrorAsUEU()">ReportErrorAsUEU</a>() then</line>
<line>        if <a link="impl-shared.IsExternalSyncAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalSyncAbort(Fault statuscode)">IsExternalSyncAbort</a>(fault) then  // Implies taken to AArch64</line>
<line>            return <a link="ErrorState_UC" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UC</a>;</line>
<line>        else</line>
<line>            return <a link="ErrorState_UEU" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UEU</a>;</line>
<line></line>
<line>    if (<a link="impl-shared.ActionRequired.0" file="shared_pseudocode.xml" hover="function: boolean ActionRequired()">ActionRequired</a>() || <a link="impl-shared.ReportErrorAsUER.0" file="shared_pseudocode.xml" hover="function: boolean ReportErrorAsUER()">ReportErrorAsUER</a>()) then</line>
<line>        return <a link="ErrorState_UER" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UER</a>;</line>
<line></line>
<line>    return <a link="ErrorState_UEO" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UEO</a>;</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/ActionRequired" mylink="shared.functions.externalaborts.ActionRequired" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ActionRequired()</line>
<line>// ================</line>
<line>// Return an implementation specific value:</line>
<line>// returns TRUE if action is required, FALSE otherwise.</line>
<line></line>
<line link="impl-shared.ActionRequired.0" hover="function: boolean ActionRequired()" conts="ActionRequired">boolean <anchor link="impl-shared.ActionRequired.0" hover="function: boolean ActionRequired()">ActionRequired</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/ClearPendingPhysicalSError" mylink="shared.functions.externalaborts.ClearPendingPhysicalSError" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ClearPendingPhysicalSError()</line>
<line>// ============================</line>
<line>// Clear a pending physical SError interrupt.</line>
<line></line>
<line link="impl-shared.ClearPendingPhysicalSError.0" hover="function: ClearPendingPhysicalSError()" conts="ClearPendingPhysicalSError"><anchor link="impl-shared.ClearPendingPhysicalSError.0" hover="function: ClearPendingPhysicalSError()">ClearPendingPhysicalSError</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/ClearPendingVirtualSError" mylink="shared.functions.externalaborts.ClearPendingVirtualSError" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ClearPendingVirtualSError()</line>
<line>// ===========================</line>
<line>// Clear a pending virtual SError interrupt.</line>
<line></line>
<line link="impl-shared.ClearPendingVirtualSError.0" hover="function: ClearPendingVirtualSError()" conts="ClearPendingVirtualSError"><anchor link="impl-shared.ClearPendingVirtualSError.0" hover="function: ClearPendingVirtualSError()">ClearPendingVirtualSError</anchor>()</line>
<line>    if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>        HCR.VA = '0';</line>
<line>    else</line>
<line>        HCR_EL2.VSE = '0';</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/ErrorIsContained" mylink="shared.functions.externalaborts.ErrorIsContained" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ErrorIsContained()</line>
<line>// ==================</line>
<line>// Return an implementation specific value:</line>
<line>// TRUE if Error is contained by the PE, FALSE otherwise.</line>
<line></line>
<line link="impl-shared.ErrorIsContained.0" hover="function: boolean ErrorIsContained()" conts="ErrorIsContained">boolean <anchor link="impl-shared.ErrorIsContained.0" hover="function: boolean ErrorIsContained()">ErrorIsContained</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/ErrorIsSynchronized" mylink="shared.functions.externalaborts.ErrorIsSynchronized" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ErrorIsSynchronized()</line>
<line>// =====================</line>
<line>// Return an implementation specific value:</line>
<line>// returns TRUE if Error is synchronized by any synchronization event</line>
<line>// FALSE otherwise.</line>
<line></line>
<line link="impl-shared.ErrorIsSynchronized.0" hover="function: boolean ErrorIsSynchronized()" conts="ErrorIsSynchronized">boolean <anchor link="impl-shared.ErrorIsSynchronized.0" hover="function: boolean ErrorIsSynchronized()">ErrorIsSynchronized</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/ExtAbortToA64" mylink="shared.functions.externalaborts.ExtAbortToA64" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExtAbortToA64()</line>
<line>// ===============</line>
<line>// Returns TRUE if synchronous exception is being taken to A64 exception</line>
<line>// level.</line>
<line></line>
<line link="impl-shared.ExtAbortToA64.1" hover="function: boolean ExtAbortToA64(FaultRecord fault)" conts="ExtAbortToA64">boolean <anchor link="impl-shared.ExtAbortToA64.1" hover="function: boolean ExtAbortToA64(FaultRecord fault)">ExtAbortToA64</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    // Check if routed to AArch64 state</line>
<line>    route_to_aarch64 = PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line></line>
<line>    if !route_to_aarch64 &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>        route_to_aarch64 = (HCR_EL2.TGE == '1' || <a link="impl-shared.IsSecondStage.1" file="shared_pseudocode.xml" hover="function: boolean IsSecondStage(FaultRecord fault)">IsSecondStage</a>(fault) ||</line>
<line>                            (<a link="impl-shared.HaveRASExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveRASExt()">HaveRASExt</a>() &amp;&amp; HCR_EL2.TEA == '1' &amp;&amp; <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault)) ||</line>
<line>                            (<a link="impl-shared.IsDebugException.1" file="shared_pseudocode.xml" hover="function: boolean IsDebugException(FaultRecord fault)">IsDebugException</a>(fault) &amp;&amp; MDCR_EL2.TDE == '1'));</line>
<line></line>
<line>    if !route_to_aarch64 &amp;&amp; <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        route_to_aarch64 = <a link="impl-shared.SCR_GEN.read.0" file="shared_pseudocode.xml" hover="accessor: SCRType SCR_GEN[]">SCR_GEN</a>[].EA == '1' &amp;&amp; <a link="impl-shared.IsExternalAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbort(Fault statuscode)">IsExternalAbort</a>(fault);</line>
<line></line>
<line>    return route_to_aarch64 &amp;&amp; <a link="impl-shared.IsExternalSyncAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalSyncAbort(Fault statuscode)">IsExternalSyncAbort</a>(fault.statuscode);</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/FaultIsCorrected" mylink="shared.functions.externalaborts.FaultIsCorrected" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FaultIsCorrected()</line>
<line>// ==================</line>
<line>// Return an implementation specific value:</line>
<line>// TRUE if fault is corrected by the PE, FALSE otherwise.</line>
<line></line>
<line link="impl-shared.FaultIsCorrected.0" hover="function: boolean FaultIsCorrected()" conts="FaultIsCorrected">boolean <anchor link="impl-shared.FaultIsCorrected.0" hover="function: boolean FaultIsCorrected()">FaultIsCorrected</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/GetPendingPhysicalSError" mylink="shared.functions.externalaborts.GetPendingPhysicalSError" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GetPendingPhysicalSError()</line>
<line>// ==========================</line>
<line>// Returns the FaultRecord containing details of pending Physical SError</line>
<line>// interrupt.</line>
<line></line>
<line link="impl-shared.GetPendingPhysicalSError.0" hover="function: FaultRecord GetPendingPhysicalSError()" conts="GetPendingPhysicalSError">FaultRecord <anchor link="impl-shared.GetPendingPhysicalSError.0" hover="function: FaultRecord GetPendingPhysicalSError()">GetPendingPhysicalSError</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/HandleExternalAbort" mylink="shared.functions.externalaborts.HandleExternalAbort" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HandleExternalAbort()</line>
<line>// =====================</line>
<line>// Takes a Synchronous/Asynchronous abort based on fault.</line>
<line></line>
<line link="impl-shared.HandleExternalAbort.5" hover="function: HandleExternalAbort(PhysMemRetStatus memretstatus, boolean iswrite, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)" conts="HandleExternalAbort"><anchor link="impl-shared.HandleExternalAbort.5" hover="function: HandleExternalAbort(PhysMemRetStatus memretstatus, boolean iswrite, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalAbort</anchor>(<a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> memretstatus, boolean iswrite,</line>
<line>                    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc, integer size,</line>
<line>                    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    assert (memretstatus.statuscode IN {<a link="Fault_SyncExternal" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncExternal</a>, <a link="Fault_AsyncExternal" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncExternal</a>} ||</line>
<line>           (!<a link="impl-shared.HaveRASExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveRASExt()">HaveRASExt</a>() &amp;&amp; memretstatus.statuscode IN {<a link="Fault_SyncParity" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncParity</a>,</line>
<line>                                                         <a link="Fault_AsyncParity" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncParity</a>}));</line>
<line></line>
<line>    fault = <a link="impl-shared.NoFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord NoFault(AccessDescriptor accdesc)">NoFault</a>(accdesc);</line>
<line>    fault.statuscode = memretstatus.statuscode;</line>
<line>    fault.write      = iswrite;</line>
<line>    fault.extflag    = memretstatus.extflag;</line>
<line>    // It is implementation specific whether External aborts signaled</line>
<line>    // in-band synchronously are taken synchronously or asynchronously</line>
<line>    if (<a link="impl-shared.IsExternalSyncAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalSyncAbort(Fault statuscode)">IsExternalSyncAbort</a>(fault) &amp;&amp;</line>
<line>            !<a link="impl-shared.IsExternalAbortTakenSynchronously.5" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbortTakenSynchronously(PhysMemRetStatus memstatus, boolean iswrite, AddressDescriptor desc, integer size, AccessDescriptor accdesc)">IsExternalAbortTakenSynchronously</a>(memretstatus, iswrite, memaddrdesc,</line>
<line>                                               size, accdesc)) then</line>
<line>        if fault.statuscode == <a link="Fault_SyncParity" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncParity</a> then</line>
<line>            fault.statuscode = <a link="Fault_AsyncParity" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncParity</a>;</line>
<line>        else</line>
<line>            fault.statuscode = <a link="Fault_AsyncExternal" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncExternal</a>;</line>
<line></line>
<line>    if <a link="impl-shared.HaveRASExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveRASExt()">HaveRASExt</a>() then</line>
<line>        fault.merrorstate = memretstatus.merrorstate;</line>
<line></line>
<line>    if <a link="impl-shared.IsExternalSyncAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalSyncAbort(Fault statuscode)">IsExternalSyncAbort</a>(fault) then</line>
<line>        if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>            <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(memaddrdesc.vaddress&lt;31:0&gt;, fault);</line>
<line>        else</line>
<line>            <a link="AArch64.Abort.2" file="shared_pseudocode.xml" hover="function: AArch64.Abort(bits(64) vaddress, FaultRecord fault)">AArch64.Abort</a>(memaddrdesc.vaddress, fault);</line>
<line></line>
<line>    else</line>
<line>        <a link="impl-shared.PendSErrorInterrupt.1" file="shared_pseudocode.xml" hover="function: PendSErrorInterrupt(FaultRecord fault)">PendSErrorInterrupt</a>(fault);</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/HandleExternalReadAbort" mylink="shared.functions.externalaborts.HandleExternalReadAbort" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HandleExternalReadAbort()</line>
<line>// =========================</line>
<line>// Wrapper function for HandleExternalAbort function in case of an External</line>
<line>// Abort on memory read.</line>
<line></line>
<line link="impl-shared.HandleExternalReadAbort.4" hover="function: HandleExternalReadAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)" conts="HandleExternalReadAbort"><anchor link="impl-shared.HandleExternalReadAbort.4" hover="function: HandleExternalReadAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalReadAbort</anchor>(<a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> memstatus, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc,</line>
<line>                        integer size, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    iswrite = FALSE;</line>
<line>    <a link="impl-shared.HandleExternalAbort.5" file="shared_pseudocode.xml" hover="function: HandleExternalAbort(PhysMemRetStatus memretstatus, boolean iswrite, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalAbort</a>(memstatus, iswrite, memaddrdesc, size, accdesc);</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/HandleExternalTTWAbort" mylink="shared.functions.externalaborts.HandleExternalTTWAbort" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HandleExternalTTWAbort()</line>
<line>// ========================</line>
<line>// Take Asynchronous abort or update FaultRecord for Translation Table Walk</line>
<line>// based on PhysMemRetStatus.</line>
<line></line>
<line link="impl-shared.HandleExternalTTWAbort.6" hover="function: FaultRecord HandleExternalTTWAbort(PhysMemRetStatus memretstatus, boolean iswrite, AddressDescriptor memaddrdesc, AccessDescriptor accdesc, integer size, FaultRecord input_fault)" conts="HandleExternalTTWAbort">FaultRecord <anchor link="impl-shared.HandleExternalTTWAbort.6" hover="function: FaultRecord HandleExternalTTWAbort(PhysMemRetStatus memretstatus, boolean iswrite, AddressDescriptor memaddrdesc, AccessDescriptor accdesc, integer size, FaultRecord input_fault)">HandleExternalTTWAbort</anchor>(<a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> memretstatus, boolean iswrite,</line>
<line>                                   <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc,</line>
<line>                                   <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc, integer size,</line>
<line>                                   <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> input_fault)</line>
<line>    output_fault = input_fault;</line>
<line>    output_fault.extflag = memretstatus.extflag;</line>
<line>    output_fault.statuscode = memretstatus.statuscode;</line>
<line>    if (<a link="impl-shared.IsExternalSyncAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalSyncAbort(Fault statuscode)">IsExternalSyncAbort</a>(output_fault) &amp;&amp;</line>
<line>            !<a link="impl-shared.IsExternalAbortTakenSynchronously.5" file="shared_pseudocode.xml" hover="function: boolean IsExternalAbortTakenSynchronously(PhysMemRetStatus memstatus, boolean iswrite, AddressDescriptor desc, integer size, AccessDescriptor accdesc)">IsExternalAbortTakenSynchronously</a>(memretstatus, iswrite, memaddrdesc,</line>
<line>                                               size, accdesc)) then</line>
<line>        if output_fault.statuscode == <a link="Fault_SyncParity" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncParity</a> then</line>
<line>            output_fault.statuscode = <a link="Fault_AsyncParity" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncParity</a>;</line>
<line>        else</line>
<line>            output_fault.statuscode = <a link="Fault_AsyncExternal" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncExternal</a>;</line>
<line></line>
<line>    // If a synchronous fault is on a translation table walk, then update</line>
<line>    // the fault type</line>
<line>    if <a link="impl-shared.IsExternalSyncAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalSyncAbort(Fault statuscode)">IsExternalSyncAbort</a>(output_fault) then</line>
<line>        if output_fault.statuscode == <a link="Fault_SyncParity" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncParity</a> then</line>
<line>            output_fault.statuscode = <a link="Fault_SyncParityOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncParityOnWalk</a>;</line>
<line>        else</line>
<line>            output_fault.statuscode = <a link="Fault_SyncExternalOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncExternalOnWalk</a>;</line>
<line>    if <a link="impl-shared.HaveRASExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveRASExt()">HaveRASExt</a>() then</line>
<line>        output_fault.merrorstate = memretstatus.merrorstate;</line>
<line>    if !<a link="impl-shared.IsExternalSyncAbort.1" file="shared_pseudocode.xml" hover="function: boolean IsExternalSyncAbort(Fault statuscode)">IsExternalSyncAbort</a>(output_fault) then</line>
<line>        <a link="impl-shared.PendSErrorInterrupt.1" file="shared_pseudocode.xml" hover="function: PendSErrorInterrupt(FaultRecord fault)">PendSErrorInterrupt</a>(output_fault);</line>
<line>        output_fault.statuscode = <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a>;</line>
<line>    return output_fault;</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/HandleExternalWriteAbort" mylink="shared.functions.externalaborts.HandleExternalWriteAbort" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HandleExternalWriteAbort()</line>
<line>// ==========================</line>
<line>// Wrapper function for HandleExternalAbort function in case of an External</line>
<line>// Abort on memory write.</line>
<line></line>
<line link="impl-shared.HandleExternalWriteAbort.4" hover="function: HandleExternalWriteAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)" conts="HandleExternalWriteAbort"><anchor link="impl-shared.HandleExternalWriteAbort.4" hover="function: HandleExternalWriteAbort(PhysMemRetStatus memstatus, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalWriteAbort</anchor>(<a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> memstatus, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> memaddrdesc,</line>
<line>                         integer size, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    iswrite = TRUE;</line>
<line>    <a link="impl-shared.HandleExternalAbort.5" file="shared_pseudocode.xml" hover="function: HandleExternalAbort(PhysMemRetStatus memretstatus, boolean iswrite, AddressDescriptor memaddrdesc, integer size, AccessDescriptor accdesc)">HandleExternalAbort</a>(memstatus, iswrite, memaddrdesc, size, accdesc);</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/IsExternalAbortTakenSynchronously" mylink="shared.functions.externalaborts.IsExternalAbortTakenSynchronously" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsExternalAbortTakenSynchronously()</line>
<line>// ===================================</line>
<line>// Return an implementation specific value:</line>
<line>// TRUE if the fault returned for the access can be taken synchronously,</line>
<line>// FALSE otherwise.</line>
<line>//</line>
<line>// This might vary between accesses, for example depending on the error type</line>
<line>// or memory type being accessed.</line>
<line>// External aborts on data accesses and translation table walks on data accesses</line>
<line>// can be either synchronous or asynchronous.</line>
<line>//</line>
<line>// When FEAT_DoubleFault is not implemented, External aborts on instruction</line>
<line>// fetches and translation table walks on instruction fetches can be either</line>
<line>// synchronous or asynchronous.</line>
<line>// When FEAT_DoubleFault is implemented, all External abort exceptions on</line>
<line>// instruction fetches and translation table walks on instruction fetches</line>
<line>// must be synchronous.</line>
<line></line>
<line link="impl-shared.IsExternalAbortTakenSynchronously.5" hover="function: boolean IsExternalAbortTakenSynchronously(PhysMemRetStatus memstatus, boolean iswrite, AddressDescriptor desc, integer size, AccessDescriptor accdesc)" conts="IsExternalAbortTakenSynchronously">boolean <anchor link="impl-shared.IsExternalAbortTakenSynchronously.5" hover="function: boolean IsExternalAbortTakenSynchronously(PhysMemRetStatus memstatus, boolean iswrite, AddressDescriptor desc, integer size, AccessDescriptor accdesc)">IsExternalAbortTakenSynchronously</anchor>(<a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> memstatus,</line>
<line>                                          boolean iswrite,</line>
<line>                                          <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> desc,</line>
<line>                                          integer size,</line>
<line>                                          <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc);</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/IsPhysicalSErrorPending" mylink="shared.functions.externalaborts.IsPhysicalSErrorPending" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsPhysicalSErrorPending()</line>
<line>// =========================</line>
<line>// Returns TRUE if a physical SError interrupt is pending.</line>
<line></line>
<line link="impl-shared.IsPhysicalSErrorPending.0" hover="function: boolean IsPhysicalSErrorPending()" conts="IsPhysicalSErrorPending">boolean <anchor link="impl-shared.IsPhysicalSErrorPending.0" hover="function: boolean IsPhysicalSErrorPending()">IsPhysicalSErrorPending</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/IsSErrorEdgeTriggered" mylink="shared.functions.externalaborts.IsSErrorEdgeTriggered" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsSErrorEdgeTriggered()</line>
<line>// =======================</line>
<line>// Returns TRUE if the physical SError interrupt is edge-triggered</line>
<line>// and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.IsSErrorEdgeTriggered.0" hover="function: boolean IsSErrorEdgeTriggered()" conts="IsSErrorEdgeTriggered">boolean <anchor link="impl-shared.IsSErrorEdgeTriggered.0" hover="function: boolean IsSErrorEdgeTriggered()">IsSErrorEdgeTriggered</anchor>()</line>
<line>    if <a link="impl-shared.HaveDoubleFaultExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDoubleFaultExt()">HaveDoubleFaultExt</a>() then</line>
<line>        return TRUE;</line>
<line>    else</line>
<line>        return boolean IMPLEMENTATION_DEFINED "Edge-triggered SError";</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/IsSynchronizablePhysicalSErrorPending" mylink="shared.functions.externalaborts.IsSynchronizablePhysicalSErrorPending" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsSynchronizablePhysicalSErrorPending()</line>
<line>// =======================================</line>
<line>// Returns TRUE if a synchronizable physical SError interrupt is pending.</line>
<line></line>
<line link="impl-shared.IsSynchronizablePhysicalSErrorPending.0" hover="function: boolean IsSynchronizablePhysicalSErrorPending()" conts="IsSynchronizablePhysicalSErrorPending">boolean <anchor link="impl-shared.IsSynchronizablePhysicalSErrorPending.0" hover="function: boolean IsSynchronizablePhysicalSErrorPending()">IsSynchronizablePhysicalSErrorPending</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/IsVirtualSErrorPending" mylink="shared.functions.externalaborts.IsVirtualSErrorPending" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsVirtualSErrorPending()</line>
<line>// ========================</line>
<line>// Return TRUE if a virtual SError interrupt is pending.</line>
<line></line>
<line link="impl-shared.IsVirtualSErrorPending.0" hover="function: boolean IsVirtualSErrorPending()" conts="IsVirtualSErrorPending">boolean <anchor link="impl-shared.IsVirtualSErrorPending.0" hover="function: boolean IsVirtualSErrorPending()">IsVirtualSErrorPending</anchor>()</line>
<line>    if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>        return HCR.VA == '1';</line>
<line>    else</line>
<line>        return HCR_EL2.VSE == '1';</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/PendSErrorInterrupt" mylink="shared.functions.externalaborts.PendSErrorInterrupt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PendSErrorInterrupt()</line>
<line>// =====================</line>
<line>// Pend the SError Interrupt.</line>
<line></line>
<line link="impl-shared.PendSErrorInterrupt.1" hover="function: PendSErrorInterrupt(FaultRecord fault)" conts="PendSErrorInterrupt"><anchor link="impl-shared.PendSErrorInterrupt.1" hover="function: PendSErrorInterrupt(FaultRecord fault)">PendSErrorInterrupt</anchor>(<a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault);</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/ReportErrorAsIMPDEF" mylink="shared.functions.externalaborts.ReportErrorAsIMPDEF" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ReportErrorAsIMPDEF()</line>
<line>// =====================</line>
<line>// Return an implementation specific value:</line>
<line>// returns TRUE if Error is IMPDEF, FALSE otherwise.</line>
<line></line>
<line link="impl-shared.ReportErrorAsIMPDEF.0" hover="function: boolean ReportErrorAsIMPDEF()" conts="ReportErrorAsIMPDEF">boolean <anchor link="impl-shared.ReportErrorAsIMPDEF.0" hover="function: boolean ReportErrorAsIMPDEF()">ReportErrorAsIMPDEF</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/ReportErrorAsUC" mylink="shared.functions.externalaborts.ReportErrorAsUC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ReportErrorAsUC()</line>
<line>// =================</line>
<line>// Return an implementation specific value:</line>
<line>// returns TRUE if Error is Uncontainable, FALSE otherwise.</line>
<line></line>
<line link="impl-shared.ReportErrorAsUC.0" hover="function: boolean ReportErrorAsUC()" conts="ReportErrorAsUC">boolean <anchor link="impl-shared.ReportErrorAsUC.0" hover="function: boolean ReportErrorAsUC()">ReportErrorAsUC</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/ReportErrorAsUER" mylink="shared.functions.externalaborts.ReportErrorAsUER" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ReportErrorAsUER()</line>
<line>// ==================</line>
<line>// Return an implementation specific value:</line>
<line>// returns TRUE if Error is Recoverable, FALSE otherwise.</line>
<line></line>
<line link="impl-shared.ReportErrorAsUER.0" hover="function: boolean ReportErrorAsUER()" conts="ReportErrorAsUER">boolean <anchor link="impl-shared.ReportErrorAsUER.0" hover="function: boolean ReportErrorAsUER()">ReportErrorAsUER</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/ReportErrorAsUEU" mylink="shared.functions.externalaborts.ReportErrorAsUEU" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ReportErrorAsUEU()</line>
<line>// ==================</line>
<line>// Return an implementation specific value:</line>
<line>// returns TRUE if Error is Unrecoverable, FALSE otherwise.</line>
<line></line>
<line link="impl-shared.ReportErrorAsUEU.0" hover="function: boolean ReportErrorAsUEU()" conts="ReportErrorAsUEU">boolean <anchor link="impl-shared.ReportErrorAsUEU.0" hover="function: boolean ReportErrorAsUEU()">ReportErrorAsUEU</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/ReportErrorAsUncategorized" mylink="shared.functions.externalaborts.ReportErrorAsUncategorized" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ReportErrorAsUncategorized()</line>
<line>// ===========================</line>
<line>// Return an implementation specific value:</line>
<line>// returns TRUE if Error is uncategorized, FALSE otherwise.</line>
<line></line>
<line link="impl-shared.ReportErrorAsUncategorized.0" hover="function: boolean ReportErrorAsUncategorized()" conts="ReportErrorAsUncategorized">boolean <anchor link="impl-shared.ReportErrorAsUncategorized.0" hover="function: boolean ReportErrorAsUncategorized()">ReportErrorAsUncategorized</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/externalaborts/StateIsRecoverable" mylink="shared.functions.externalaborts.StateIsRecoverable" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// StateIsRecoverable()</line>
<line>// =====================</line>
<line>// Return an implementation specific value:</line>
<line>// returns TRUE is PE State is unrecoverable else FALSE.</line>
<line></line>
<line link="impl-shared.StateIsRecoverable.0" hover="function: boolean StateIsRecoverable()" conts="StateIsRecoverable">boolean <anchor link="impl-shared.StateIsRecoverable.0" hover="function: boolean StateIsRecoverable()">StateIsRecoverable</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/BFAdd" mylink="shared.functions.float.bfloat.BFAdd" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BFAdd()</line>
<line>// =======</line>
<line>// Non-widening BFloat16 addition used by SVE2 instructions.</line>
<line></line>
<line link="impl-shared.BFAdd.3" hover="function: bits(16) BFAdd(bits(16) op1, bits(16) op2, FPCRType fpcr)" conts="BFAdd">bits(16) <anchor link="impl-shared.BFAdd.3" hover="function: bits(16) BFAdd(bits(16) op1, bits(16) op2, FPCRType fpcr)">BFAdd</anchor>(bits(16) op1, bits(16) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    boolean fpexc = TRUE;</line>
<line>    return <a link="impl-shared.BFAdd.4" file="shared_pseudocode.xml" hover="function: bits(16) BFAdd(bits(16) op1, bits(16) op2, FPCRType fpcr, boolean fpexc)">BFAdd</a>(op1, op2, fpcr, fpexc);</line>
<line></line>
<line>// BFAdd()</line>
<line>// =======</line>
<line>// Non-widening BFloat16 addition following computational behaviors</line>
<line>// corresponding to instructions that read and write BFloat16 values.</line>
<line>// Calculates op1 + op2.</line>
<line>// The 'fpcr' argument supplies the FPCR control bits.</line>
<line></line>
<line link="impl-shared.BFAdd.4" hover="function: bits(16) BFAdd(bits(16) op1, bits(16) op2, FPCRType fpcr, boolean fpexc)" conts="BFAdd">bits(16) <anchor link="impl-shared.BFAdd.4" hover="function: bits(16) BFAdd(bits(16) op1, bits(16) op2, FPCRType fpcr, boolean fpexc)">BFAdd</anchor>(bits(16) op1, bits(16) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, boolean fpexc)</line>
<line></line>
<line>    <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(fpcr);</line>
<line>    boolean done;</line>
<line>    bits(32) result;</line>
<line></line>
<line>    bits(32) op1_s = op1 : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>    bits(32) op2_s = op2 : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op1_s, fpcr, fpexc);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op2_s, fpcr, fpexc);</line>
<line></line>
<line>    (done,result) = <a link="impl-shared.FPProcessNaNs.6" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs(FPType type1, FPType type2, bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)">FPProcessNaNs</a>(type1, type2, op1_s, op2_s, fpcr, fpexc);</line>
<line></line>
<line>    if !done then</line>
<line>        inf1 = (type1 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        inf2 = (type2 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        zero1 = (type1 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line>        zero2 = (type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line></line>
<line>        if inf1 &amp;&amp; inf2 &amp;&amp; sign1 == NOT(sign2) then</line>
<line>            result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, 32);</line>
<line>            if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>        elsif (inf1 &amp;&amp; sign1 == '0') || (inf2 &amp;&amp; sign2 == '0') then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('0', 32);</line>
<line>        elsif (inf1 &amp;&amp; sign1 == '1') || (inf2 &amp;&amp; sign2 == '1') then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('1', 32);</line>
<line>        elsif zero1 &amp;&amp; zero2 &amp;&amp; sign1 == sign2 then</line>
<line>            result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign1, 32);</line>
<line>        else</line>
<line>            result_value = value1 + value2;</line>
<line>            if result_value == 0.0 then  // Sign of exact zero result depends on rounding mode</line>
<line>                result_sign = if rounding == <a link="FPRounding_NEGINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_NEGINF</a> then '1' else '0';</line>
<line>                result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(result_sign, 32);</line>
<line>            else</line>
<line>                result = <a link="impl-shared.FPRoundBF.4" file="shared_pseudocode.xml" hover="function: bits(32) FPRoundBF(real op, FPCRType fpcr, FPRounding rounding, boolean fpexc)">FPRoundBF</a>(result_value, fpcr, rounding, fpexc);</line>
<line></line>
<line>        if fpexc then <a link="impl-shared.FPProcessDenorms.4" file="shared_pseudocode.xml" hover="function: FPProcessDenorms(FPType type1, FPType type2, integer N, FPCRType fpcr)">FPProcessDenorms</a>(type1, type2, 32, fpcr);</line>
<line></line>
<line>    return result&lt;31:16&gt;;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/BFAdd_ZA" mylink="shared.functions.float.bfloat.BFAdd_ZA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BFAdd_ZA()</line>
<line>// ==========</line>
<line>// Non-widening BFloat16 addition used by SME2 ZA-targeting instructions.</line>
<line></line>
<line link="impl-shared.BFAdd_ZA.3" hover="function: bits(16) BFAdd_ZA(bits(16) op1, bits(16) op2, FPCRType fpcr_in)" conts="BFAdd_ZA">bits(16) <anchor link="impl-shared.BFAdd_ZA.3" hover="function: bits(16) BFAdd_ZA(bits(16) op1, bits(16) op2, FPCRType fpcr_in)">BFAdd_ZA</anchor>(bits(16) op1, bits(16) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in)</line>
<line>    boolean fpexc = FALSE;</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    fpcr.DN = '1';          // Generate default NaN values</line>
<line>    return <a link="impl-shared.BFAdd.4" file="shared_pseudocode.xml" hover="function: bits(16) BFAdd(bits(16) op1, bits(16) op2, FPCRType fpcr, boolean fpexc)">BFAdd</a>(op1, op2, fpcr, fpexc);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/BFDotAdd" mylink="shared.functions.float.bfloat.BFDotAdd" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BFDotAdd()</line>
<line>// ==========</line>
<line>// BFloat16 2-way dot-product and add to single-precision</line>
<line>// result = addend + op1_a*op2_a + op1_b*op2_b</line>
<line></line>
<line link="impl-shared.BFDotAdd.6" hover="function: bits(32) BFDotAdd(bits(32) addend, bits(16) op1_a, bits(16) op1_b, bits(16) op2_a, bits(16) op2_b, FPCRType fpcr_in)" conts="BFDotAdd">bits(32) <anchor link="impl-shared.BFDotAdd.6" hover="function: bits(32) BFDotAdd(bits(32) addend, bits(16) op1_a, bits(16) op1_b, bits(16) op2_a, bits(16) op2_b, FPCRType fpcr_in)">BFDotAdd</anchor>(bits(32) addend, bits(16) op1_a, bits(16) op1_b,</line>
<line>                  bits(16) op2_a, bits(16) op2_b, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in)</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line></line>
<line>    bits(32) prod;</line>
<line></line>
<line>    bits(32) result;</line>
<line>    if !<a link="impl-shared.HaveEBF16.0" file="shared_pseudocode.xml" hover="function: boolean HaveEBF16()">HaveEBF16</a>() || fpcr.EBF == '0' then   // Standard BFloat16 behaviors</line>
<line>        prod = <a link="impl-shared.FPAdd_BF16.2" file="shared_pseudocode.xml" hover="function: bits(32) FPAdd_BF16(bits(32) op1, bits(32) op2)">FPAdd_BF16</a>(<a link="impl-shared.BFMulH.2" file="shared_pseudocode.xml" hover="function: bits(32) BFMulH(bits(16) op1, bits(16) op2)">BFMulH</a>(op1_a, op2_a), <a link="impl-shared.BFMulH.2" file="shared_pseudocode.xml" hover="function: bits(32) BFMulH(bits(16) op1, bits(16) op2)">BFMulH</a>(op1_b, op2_b));</line>
<line>        result = <a link="impl-shared.FPAdd_BF16.2" file="shared_pseudocode.xml" hover="function: bits(32) FPAdd_BF16(bits(32) op1, bits(32) op2)">FPAdd_BF16</a>(addend, prod);</line>
<line>    else                                      // Extended BFloat16 behaviors</line>
<line>        boolean isbfloat16 = TRUE;</line>
<line>        boolean fpexc = FALSE;  // Do not generate floating-point exceptions</line>
<line>        fpcr.DN = '1';          // Generate default NaN values</line>
<line>        prod = <a link="impl-shared.FPDot.7" file="shared_pseudocode.xml" hover="function: bits(N) FPDot(bits(N DIV 2) op1_a, bits(N DIV 2) op1_b, bits(N DIV 2) op2_a, bits(N DIV 2) op2_b, FPCRType fpcr_in, boolean isbfloat16, boolean fpexc)">FPDot</a>(op1_a, op1_b, op2_a, op2_b, fpcr, isbfloat16, fpexc);</line>
<line>        result = <a link="impl-shared.FPAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)">FPAdd</a>(addend, prod, fpcr, fpexc);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/BFInfinity" mylink="shared.functions.float.bfloat.BFInfinity" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BFInfinity()</line>
<line>// ============</line>
<line></line>
<line link="impl-shared.BFInfinity.1" hover="function: bits(16) BFInfinity(bit sign)" conts="BFInfinity">bits(16) <anchor link="impl-shared.BFInfinity.1" hover="function: bits(16) BFInfinity(bit sign)">BFInfinity</anchor>(bit sign)</line>
<line>    return sign : <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(8) : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(7);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/BFMatMulAdd" mylink="shared.functions.float.bfloat.BFMatMulAdd" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BFMatMulAdd()</line>
<line>// =============</line>
<line>// BFloat16 matrix multiply and add to single-precision matrix</line>
<line>// result[2, 2] = addend[2, 2] + (op1[2, 4] * op2[4, 2])</line>
<line></line>
<line link="impl-shared.BFMatMulAdd.3" hover="function: bits(N) BFMatMulAdd(bits(N) addend, bits(N) op1, bits(N) op2)" conts="BFMatMulAdd">bits(N) <anchor link="impl-shared.BFMatMulAdd.3" hover="function: bits(N) BFMatMulAdd(bits(N) addend, bits(N) op1, bits(N) op2)">BFMatMulAdd</anchor>(bits(N) addend, bits(N) op1, bits(N) op2)</line>
<line></line>
<line>    assert N == 128;</line>
<line></line>
<line>    bits(N) result;</line>
<line>    bits(32) sum;</line>
<line></line>
<line>    for i = 0 to 1</line>
<line>        for j = 0 to 1</line>
<line>            sum = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[addend, 2*i + j, 32];</line>
<line>            for k = 0 to 1</line>
<line>                bits(16) elt1_a = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[op1, 4*i + 2*k + 0, 16];</line>
<line>                bits(16) elt1_b = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[op1, 4*i + 2*k + 1, 16];</line>
<line>                bits(16) elt2_a = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[op2, 4*j + 2*k + 0, 16];</line>
<line>                bits(16) elt2_b = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[op2, 4*j + 2*k + 1, 16];</line>
<line>                sum = <a link="impl-shared.BFDotAdd.6" file="shared_pseudocode.xml" hover="function: bits(32) BFDotAdd(bits(32) addend, bits(16) op1_a, bits(16) op1_b, bits(16) op2_a, bits(16) op2_b, FPCRType fpcr_in)">BFDotAdd</a>(sum, elt1_a, elt1_b, elt2_a, elt2_b, FPCR[]);</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*i + j, 32] = sum;</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/BFMax" mylink="shared.functions.float.bfloat.BFMax" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BFMax()</line>
<line>// =======</line>
<line>// BFloat16 maximum.</line>
<line></line>
<line link="impl-shared.BFMax.3" hover="function: bits(16) BFMax(bits(16) op1, bits(16) op2, FPCRType fpcr)" conts="BFMax">bits(16) <anchor link="impl-shared.BFMax.3" hover="function: bits(16) BFMax(bits(16) op1, bits(16) op2, FPCRType fpcr)">BFMax</anchor>(bits(16) op1, bits(16) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    boolean altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1';</line>
<line>    return <a link="impl-shared.BFMax.4" file="shared_pseudocode.xml" hover="function: bits(16) BFMax(bits(16) op1, bits(16) op2, FPCRType fpcr_in, boolean altfp)">BFMax</a>(op1, op2, fpcr, altfp);</line>
<line></line>
<line>// BFMax()</line>
<line>// =======</line>
<line>// BFloat16 maximum following computational behaviors</line>
<line>// corresponding to instructions that read and write BFloat16 values.</line>
<line>// Compare op1 and op2 and return the larger value after rounding.</line>
<line>// The 'fpcr' argument supplies the FPCR control bits and 'altfp' determines</line>
<line>// if the function should use alternative floating-point behavior.</line>
<line></line>
<line link="impl-shared.BFMax.4" hover="function: bits(16) BFMax(bits(16) op1, bits(16) op2, FPCRType fpcr_in, boolean altfp)" conts="BFMax">bits(16) <anchor link="impl-shared.BFMax.4" hover="function: bits(16) BFMax(bits(16) op1, bits(16) op2, FPCRType fpcr_in, boolean altfp)">BFMax</anchor>(bits(16) op1, bits(16) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in, boolean altfp)</line>
<line></line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    boolean fpexc = TRUE;</line>
<line>    <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(fpcr);</line>
<line>    boolean done;</line>
<line>    bits(32) result;</line>
<line></line>
<line>    bits(32) op1_s = op1 : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>    bits(32) op2_s = op2 : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op1_s, fpcr, fpexc);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op2_s, fpcr, fpexc);</line>
<line></line>
<line>    if altfp &amp;&amp; type1 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> &amp;&amp; type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> &amp;&amp; sign1 != sign2 then</line>
<line>        // Alternate handling of zeros with differing sign</line>
<line>        return <a link="impl-shared.BFZero.1" file="shared_pseudocode.xml" hover="function: bits(16) BFZero(bit sign)">BFZero</a>(sign2);</line>
<line>    elsif altfp &amp;&amp; (type1 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>} || type2 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>}) then</line>
<line>        // Alternate handling of NaN inputs</line>
<line>        <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>        return (if type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> then <a link="impl-shared.BFZero.1" file="shared_pseudocode.xml" hover="function: bits(16) BFZero(bit sign)">BFZero</a>(sign2) else op2);</line>
<line></line>
<line>    (done,result) = <a link="impl-shared.FPProcessNaNs.5" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs(FPType type1, FPType type2, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPProcessNaNs</a>(type1, type2, op1_s, op2_s, fpcr);</line>
<line>    if !done then</line>
<line>        <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> fptype;</line>
<line>        bit sign;</line>
<line>        real value;</line>
<line>        if value1 &gt; value2 then</line>
<line>            (fptype,sign,value) = (type1,sign1,value1);</line>
<line>        else</line>
<line>            (fptype,sign,value) = (type2,sign2,value2);</line>
<line>        if fptype == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a> then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>(sign, 32);</line>
<line>        elsif fptype == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> then</line>
<line>            sign = sign1 AND sign2;              // Use most positive sign</line>
<line>            result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign, 32);</line>
<line>        else</line>
<line>            if altfp then    // Denormal output is not flushed to zero</line>
<line>                fpcr.FZ = '0';</line>
<line>            result = <a link="impl-shared.FPRoundBF.4" file="shared_pseudocode.xml" hover="function: bits(32) FPRoundBF(real op, FPCRType fpcr, FPRounding rounding, boolean fpexc)">FPRoundBF</a>(value, fpcr, rounding, fpexc);</line>
<line></line>
<line>        if fpexc then <a link="impl-shared.FPProcessDenorms.4" file="shared_pseudocode.xml" hover="function: FPProcessDenorms(FPType type1, FPType type2, integer N, FPCRType fpcr)">FPProcessDenorms</a>(type1, type2, 32, fpcr);</line>
<line></line>
<line>    return result&lt;31:16&gt;;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/BFMaxNum" mylink="shared.functions.float.bfloat.BFMaxNum" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BFMaxNum()</line>
<line>// ==========</line>
<line>// BFloat16 maximum number following computational behaviors corresponding</line>
<line>// to instructions that read and write BFloat16 values.</line>
<line>// Compare op1 and op2 and return the smaller number operand after rounding.</line>
<line>// The 'fpcr' argument supplies the FPCR control bits.</line>
<line></line>
<line link="impl-shared.BFMaxNum.3" hover="function: bits(16) BFMaxNum(bits(16) op1_in, bits(16) op2_in, FPCRType fpcr)" conts="BFMaxNum">bits(16) <anchor link="impl-shared.BFMaxNum.3" hover="function: bits(16) BFMaxNum(bits(16) op1_in, bits(16) op2_in, FPCRType fpcr)">BFMaxNum</anchor>(bits(16) op1_in, bits(16) op2_in, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line></line>
<line>    boolean fpexc = TRUE;</line>
<line>    boolean isbfloat16 = TRUE;</line>
<line>    bits(16) op1 = op1_in;</line>
<line>    bits(16) op2 = op2_in;</line>
<line>    boolean altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1';</line>
<line>    bits(16) result;</line>
<line></line>
<line>    (type1,-,-) = <a link="impl-shared.FPUnpackBase.4" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpackBase(bits(N) fpval, FPCRType fpcr_in, boolean fpexc, boolean isbfloat16)">FPUnpackBase</a>(op1, fpcr, fpexc, isbfloat16);</line>
<line>    (type2,-,-) = <a link="impl-shared.FPUnpackBase.4" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpackBase(bits(N) fpval, FPCRType fpcr_in, boolean fpexc, boolean isbfloat16)">FPUnpackBase</a>(op2, fpcr, fpexc, isbfloat16);</line>
<line></line>
<line>    boolean type1_nan = type1 IN {<a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>, <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>};</line>
<line>    boolean type2_nan = type2 IN {<a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>, <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>};</line>
<line></line>
<line>    if !(altfp &amp;&amp; type1_nan &amp;&amp; type2_nan) then</line>
<line>        // Treat a single quiet-NaN as -Infinity.</line>
<line>        if type1 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> &amp;&amp; type2 != <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>            op1 = <a link="impl-shared.BFInfinity.1" file="shared_pseudocode.xml" hover="function: bits(16) BFInfinity(bit sign)">BFInfinity</a>('1');</line>
<line>        elsif type1 != <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> &amp;&amp; type2 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>            op2 = <a link="impl-shared.BFInfinity.1" file="shared_pseudocode.xml" hover="function: bits(16) BFInfinity(bit sign)">BFInfinity</a>('1');</line>
<line></line>
<line>    boolean altfmaxfmin = FALSE;    // Do not use alternate NaN handling</line>
<line>    result = <a link="impl-shared.BFMax.4" file="shared_pseudocode.xml" hover="function: bits(16) BFMax(bits(16) op1, bits(16) op2, FPCRType fpcr_in, boolean altfp)">BFMax</a>(op1, op2, fpcr, altfmaxfmin);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/BFMin" mylink="shared.functions.float.bfloat.BFMin" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BFMin()</line>
<line>// =======</line>
<line>// BFloat16 minimum.</line>
<line></line>
<line link="impl-shared.BFMin.3" hover="function: bits(16) BFMin(bits(16) op1, bits(16) op2, FPCRType fpcr)" conts="BFMin">bits(16) <anchor link="impl-shared.BFMin.3" hover="function: bits(16) BFMin(bits(16) op1, bits(16) op2, FPCRType fpcr)">BFMin</anchor>(bits(16) op1, bits(16) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    boolean altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1';</line>
<line>    return <a link="impl-shared.BFMin.4" file="shared_pseudocode.xml" hover="function: bits(16) BFMin(bits(16) op1, bits(16) op2, FPCRType fpcr_in, boolean altfp)">BFMin</a>(op1, op2, fpcr, altfp);</line>
<line></line>
<line>// BFMin()</line>
<line>// =======</line>
<line>// BFloat16 minimum following computational behaviors</line>
<line>// corresponding to instructions that read and write BFloat16 values.</line>
<line>// Compare op1 and op2 and return the smaller value after rounding.</line>
<line>// The 'fpcr' argument supplies the FPCR control bits and 'altfp' determines</line>
<line>// if the function should use alternative floating-point behavior.</line>
<line></line>
<line link="impl-shared.BFMin.4" hover="function: bits(16) BFMin(bits(16) op1, bits(16) op2, FPCRType fpcr_in, boolean altfp)" conts="BFMin">bits(16) <anchor link="impl-shared.BFMin.4" hover="function: bits(16) BFMin(bits(16) op1, bits(16) op2, FPCRType fpcr_in, boolean altfp)">BFMin</anchor>(bits(16) op1, bits(16) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in, boolean altfp)</line>
<line></line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    boolean fpexc = TRUE;</line>
<line>    <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(fpcr);</line>
<line>    boolean done;</line>
<line>    bits(32) result;</line>
<line></line>
<line>    bits(32) op1_s = op1 : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>    bits(32) op2_s = op2 : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op1_s, fpcr, fpexc);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op2_s, fpcr, fpexc);</line>
<line></line>
<line>    if altfp &amp;&amp; type1 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> &amp;&amp; type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> &amp;&amp; sign1 != sign2 then</line>
<line>        // Alternate handling of zeros with differing sign</line>
<line>        return <a link="impl-shared.BFZero.1" file="shared_pseudocode.xml" hover="function: bits(16) BFZero(bit sign)">BFZero</a>(sign2);</line>
<line>    elsif altfp &amp;&amp; (type1 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>} || type2 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>}) then</line>
<line>        // Alternate handling of NaN inputs</line>
<line>        <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>        return (if type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> then <a link="impl-shared.BFZero.1" file="shared_pseudocode.xml" hover="function: bits(16) BFZero(bit sign)">BFZero</a>(sign2) else op2);</line>
<line></line>
<line>    (done,result) = <a link="impl-shared.FPProcessNaNs.5" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs(FPType type1, FPType type2, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPProcessNaNs</a>(type1, type2, op1_s, op2_s, fpcr);</line>
<line>    if !done then</line>
<line>        <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> fptype;</line>
<line>        bit sign;</line>
<line>        real value;</line>
<line>        if value1 &lt; value2 then</line>
<line>            (fptype,sign,value) = (type1,sign1,value1);</line>
<line>        else</line>
<line>            (fptype,sign,value) = (type2,sign2,value2);</line>
<line>        if fptype == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a> then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>(sign, 32);</line>
<line>        elsif fptype == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> then</line>
<line>            sign = sign1 OR sign2;              // Use most negative sign</line>
<line>            result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign, 32);</line>
<line>        else</line>
<line>            if altfp then    // Denormal output is not flushed to zero</line>
<line>                fpcr.FZ = '0';</line>
<line>            result = <a link="impl-shared.FPRoundBF.4" file="shared_pseudocode.xml" hover="function: bits(32) FPRoundBF(real op, FPCRType fpcr, FPRounding rounding, boolean fpexc)">FPRoundBF</a>(value, fpcr, rounding, fpexc);</line>
<line></line>
<line>        if fpexc then <a link="impl-shared.FPProcessDenorms.4" file="shared_pseudocode.xml" hover="function: FPProcessDenorms(FPType type1, FPType type2, integer N, FPCRType fpcr)">FPProcessDenorms</a>(type1, type2, 32, fpcr);</line>
<line></line>
<line>    return result&lt;31:16&gt;;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/BFMinNum" mylink="shared.functions.float.bfloat.BFMinNum" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BFMinNum()</line>
<line>// ==========</line>
<line>// BFloat16 minimum number following computational behaviors corresponding</line>
<line>// to instructions that read and write BFloat16 values.</line>
<line>// Compare op1 and op2 and return the smaller number operand after rounding.</line>
<line>// The 'fpcr' argument supplies the FPCR control bits.</line>
<line></line>
<line link="impl-shared.BFMinNum.3" hover="function: bits(16) BFMinNum(bits(16) op1_in, bits(16) op2_in, FPCRType fpcr)" conts="BFMinNum">bits(16) <anchor link="impl-shared.BFMinNum.3" hover="function: bits(16) BFMinNum(bits(16) op1_in, bits(16) op2_in, FPCRType fpcr)">BFMinNum</anchor>(bits(16) op1_in, bits(16) op2_in, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line></line>
<line>    boolean fpexc = TRUE;</line>
<line>    boolean isbfloat16 = TRUE;</line>
<line>    bits(16) op1 = op1_in;</line>
<line>    bits(16) op2 = op2_in;</line>
<line>    boolean altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1';</line>
<line>    bits(16) result;</line>
<line></line>
<line>    (type1,-,-) = <a link="impl-shared.FPUnpackBase.4" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpackBase(bits(N) fpval, FPCRType fpcr_in, boolean fpexc, boolean isbfloat16)">FPUnpackBase</a>(op1, fpcr, fpexc, isbfloat16);</line>
<line>    (type2,-,-) = <a link="impl-shared.FPUnpackBase.4" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpackBase(bits(N) fpval, FPCRType fpcr_in, boolean fpexc, boolean isbfloat16)">FPUnpackBase</a>(op2, fpcr, fpexc, isbfloat16);</line>
<line></line>
<line>    boolean type1_nan = type1 IN {<a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>, <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>};</line>
<line>    boolean type2_nan = type2 IN {<a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>, <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>};</line>
<line></line>
<line>    if !(altfp &amp;&amp; type1_nan &amp;&amp; type2_nan) then</line>
<line>        // Treat a single quiet-NaN as +Infinity.</line>
<line>        if type1 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> &amp;&amp; type2 != <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>            op1 = <a link="impl-shared.BFInfinity.1" file="shared_pseudocode.xml" hover="function: bits(16) BFInfinity(bit sign)">BFInfinity</a>('0');</line>
<line>        elsif type1 != <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> &amp;&amp; type2 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>            op2 = <a link="impl-shared.BFInfinity.1" file="shared_pseudocode.xml" hover="function: bits(16) BFInfinity(bit sign)">BFInfinity</a>('0');</line>
<line></line>
<line>    boolean altfmaxfmin = FALSE;    // Do not use alternate NaN handling</line>
<line>    result = <a link="impl-shared.BFMin.4" file="shared_pseudocode.xml" hover="function: bits(16) BFMin(bits(16) op1, bits(16) op2, FPCRType fpcr_in, boolean altfp)">BFMin</a>(op1, op2, fpcr, altfmaxfmin);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/BFMul" mylink="shared.functions.float.bfloat.BFMul" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BFMul()</line>
<line>// =======</line>
<line>// Non-widening BFloat16 multiply used by SVE2 instructions.</line>
<line></line>
<line link="impl-shared.BFMul.3" hover="function: bits(16) BFMul(bits(16) op1, bits(16) op2, FPCRType fpcr)" conts="BFMul">bits(16) <anchor link="impl-shared.BFMul.3" hover="function: bits(16) BFMul(bits(16) op1, bits(16) op2, FPCRType fpcr)">BFMul</anchor>(bits(16) op1, bits(16) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    boolean fpexc = TRUE;</line>
<line>    return <a link="impl-shared.BFMul.4" file="shared_pseudocode.xml" hover="function: bits(16) BFMul(bits(16) op1, bits(16) op2, FPCRType fpcr, boolean fpexc)">BFMul</a>(op1, op2, fpcr, fpexc);</line>
<line></line>
<line>// BFMul()</line>
<line>// =======</line>
<line>// Non-widening BFloat16 multiply following computational behaviors</line>
<line>// corresponding to instructions that read and write BFloat16 values.</line>
<line>// Calculates op1 * op2.</line>
<line>// The 'fpcr' argument supplies the FPCR control bits.</line>
<line></line>
<line link="impl-shared.BFMul.4" hover="function: bits(16) BFMul(bits(16) op1, bits(16) op2, FPCRType fpcr, boolean fpexc)" conts="BFMul">bits(16) <anchor link="impl-shared.BFMul.4" hover="function: bits(16) BFMul(bits(16) op1, bits(16) op2, FPCRType fpcr, boolean fpexc)">BFMul</anchor>(bits(16) op1, bits(16) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, boolean fpexc)</line>
<line></line>
<line>    <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(fpcr);</line>
<line>    boolean done;</line>
<line>    bits(32) result;</line>
<line></line>
<line>    bits(32) op1_s = op1 : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>    bits(32) op2_s = op2 : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op1_s, fpcr, fpexc);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op2_s, fpcr, fpexc);</line>
<line></line>
<line>    (done,result) = <a link="impl-shared.FPProcessNaNs.6" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs(FPType type1, FPType type2, bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)">FPProcessNaNs</a>(type1, type2, op1_s, op2_s, fpcr, fpexc);</line>
<line></line>
<line>    if !done then</line>
<line>        inf1 = (type1 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        inf2 = (type2 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        zero1 = (type1 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line>        zero2 = (type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line></line>
<line>        if (inf1 &amp;&amp; zero2) || (zero1 &amp;&amp; inf2) then</line>
<line>            result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, 32);</line>
<line>            if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>        elsif inf1 || inf2 then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>(sign1 EOR sign2, 32);</line>
<line>        elsif zero1 || zero2 then</line>
<line>            result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign1 EOR sign2, 32);</line>
<line>        else</line>
<line>            result = <a link="impl-shared.FPRoundBF.4" file="shared_pseudocode.xml" hover="function: bits(32) FPRoundBF(real op, FPCRType fpcr, FPRounding rounding, boolean fpexc)">FPRoundBF</a>(value1*value2, fpcr, rounding, fpexc);</line>
<line></line>
<line>        if fpexc then <a link="impl-shared.FPProcessDenorms.4" file="shared_pseudocode.xml" hover="function: FPProcessDenorms(FPType type1, FPType type2, integer N, FPCRType fpcr)">FPProcessDenorms</a>(type1, type2, 32, fpcr);</line>
<line></line>
<line>    return result&lt;31:16&gt;;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/BFMulAdd" mylink="shared.functions.float.bfloat.BFMulAdd" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BFMulAdd()</line>
<line>// ==========</line>
<line>// Non-widening BFloat16 fused multiply-add used by SVE2 instructions.</line>
<line></line>
<line link="impl-shared.BFMulAdd.4" hover="function: bits(16) BFMulAdd(bits(16) addend, bits(16) op1, bits(16) op2, FPCRType fpcr)" conts="BFMulAdd">bits(16) <anchor link="impl-shared.BFMulAdd.4" hover="function: bits(16) BFMulAdd(bits(16) addend, bits(16) op1, bits(16) op2, FPCRType fpcr)">BFMulAdd</anchor>(bits(16) addend, bits(16) op1, bits(16) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    boolean fpexc = TRUE;</line>
<line>    return <a link="impl-shared.BFMulAdd.5" file="shared_pseudocode.xml" hover="function: bits(16) BFMulAdd(bits(16) addend, bits(16) op1, bits(16) op2, FPCRType fpcr, boolean fpexc)">BFMulAdd</a>(addend, op1, op2, fpcr, fpexc);</line>
<line></line>
<line>// BFMulAdd()</line>
<line>// ==========</line>
<line>// Non-widening BFloat16 fused multiply-add following computational behaviors</line>
<line>// corresponding to instructions that read and write BFloat16 values.</line>
<line>// Calculates addend + op1*op2 with a single rounding.</line>
<line>// The 'fpcr' argument supplies the FPCR control bits.</line>
<line></line>
<line link="impl-shared.BFMulAdd.5" hover="function: bits(16) BFMulAdd(bits(16) addend, bits(16) op1, bits(16) op2, FPCRType fpcr, boolean fpexc)" conts="BFMulAdd">bits(16) <anchor link="impl-shared.BFMulAdd.5" hover="function: bits(16) BFMulAdd(bits(16) addend, bits(16) op1, bits(16) op2, FPCRType fpcr, boolean fpexc)">BFMulAdd</anchor>(bits(16) addend, bits(16) op1, bits(16) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, boolean fpexc)</line>
<line></line>
<line>    <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(fpcr);</line>
<line>    boolean done;</line>
<line>    bits(32) result;</line>
<line></line>
<line>    bits(32) addend_s = addend : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>    bits(32) op1_s = op1 : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>    bits(32) op2_s = op2 : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>    (typeA,signA,valueA) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(addend_s, fpcr, fpexc);</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op1_s, fpcr, fpexc);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op2_s, fpcr, fpexc);</line>
<line></line>
<line>    inf1 = (type1 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>    inf2 = (type2 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>    zero1 = (type1 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line>    zero2 = (type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line></line>
<line>    (done,result) = <a link="impl-shared.FPProcessNaNs3.8" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs3(FPType type1, FPType type2, FPType type3, bits(N) op1, bits(N) op2, bits(N) op3, FPCRType fpcr, boolean fpexc)">FPProcessNaNs3</a>(typeA, type1, type2, addend_s, op1_s, op2_s, fpcr, fpexc);</line>
<line></line>
<line>    if !(<a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1') then</line>
<line>        if typeA == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> &amp;&amp; ((inf1 &amp;&amp; zero2) || (zero1 &amp;&amp; inf2)) then</line>
<line>            result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, 32);</line>
<line>            if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line></line>
<line>    if !done then</line>
<line>        infA = (typeA == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        zeroA = (typeA == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line></line>
<line>        // Determine sign and type product will have if it does not cause an</line>
<line>        // Invalid Operation.</line>
<line>        signP = sign1 EOR sign2;</line>
<line>        infP  = inf1 || inf2;</line>
<line>        zeroP = zero1 || zero2;</line>
<line></line>
<line>        // Non SNaN-generated Invalid Operation cases are multiplies of zero</line>
<line>        // by infinity and additions of opposite-signed infinities.</line>
<line>        invalidop = (inf1 &amp;&amp; zero2) || (zero1 &amp;&amp; inf2) || (infA &amp;&amp; infP &amp;&amp; signA != signP);</line>
<line></line>
<line>        if invalidop then</line>
<line>            result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, 32);</line>
<line>            if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line></line>
<line>        // Other cases involving infinities produce an infinity of the same sign.</line>
<line>        elsif (infA &amp;&amp; signA == '0') || (infP &amp;&amp; signP == '0') then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('0', 32);</line>
<line>        elsif (infA &amp;&amp; signA == '1') || (infP &amp;&amp; signP == '1') then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('1', 32);</line>
<line></line>
<line>        // Cases where the result is exactly zero and its sign is not determined by the</line>
<line>        // rounding mode are additions of same-signed zeros.</line>
<line>        elsif zeroA &amp;&amp; zeroP &amp;&amp; signA == signP then</line>
<line>            result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(signA, 32);</line>
<line></line>
<line>        // Otherwise calculate numerical result and round it.</line>
<line>        else</line>
<line>            result_value = valueA + (value1 * value2);</line>
<line>            if result_value == 0.0 then  // Sign of exact zero result depends on rounding mode</line>
<line>                result_sign = if rounding == <a link="FPRounding_NEGINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_NEGINF</a> then '1' else '0';</line>
<line>                result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(result_sign, 32);</line>
<line>            else</line>
<line>                result = <a link="impl-shared.FPRoundBF.4" file="shared_pseudocode.xml" hover="function: bits(32) FPRoundBF(real op, FPCRType fpcr, FPRounding rounding, boolean fpexc)">FPRoundBF</a>(result_value, fpcr, rounding, fpexc);</line>
<line></line>
<line>        if !invalidop &amp;&amp; fpexc then</line>
<line>            <a link="impl-shared.FPProcessDenorms3.5" file="shared_pseudocode.xml" hover="function: FPProcessDenorms3(FPType type1, FPType type2, FPType type3, integer N, FPCRType fpcr)">FPProcessDenorms3</a>(typeA, type1, type2, 32, fpcr);</line>
<line></line>
<line>    return result&lt;31:16&gt;;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/BFMulAddH" mylink="shared.functions.float.bfloat.BFMulAddH" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BFMulAddH()</line>
<line>// ===========</line>
<line>// Used by BFMLALB, BFMLALT, BFMLSLB and BFMLSLT instructions.</line>
<line></line>
<line link="impl-shared.BFMulAddH.4" hover="function: bits(N) BFMulAddH(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, FPCRType fpcr_in)" conts="BFMulAddH">bits(N) <anchor link="impl-shared.BFMulAddH.4" hover="function: bits(N) BFMulAddH(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, FPCRType fpcr_in)">BFMulAddH</anchor>(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in)</line>
<line>    bits(N) value1 = op1 : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(N DIV 2);</line>
<line>    bits(N) value2 = op2 : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(N DIV 2);</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    boolean altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; fpcr.AH == '1';  // When TRUE:</line>
<line>    boolean fpexc = !altfp;                         //     Do not generate floating point exceptions</line>
<line>    if altfp then fpcr.&lt;FIZ,FZ&gt; = '11';             //     Flush denormal input and output to zero</line>
<line>    if altfp then fpcr.RMode    = '00';             //     Use RNE rounding mode</line>
<line>    return <a link="impl-shared.FPMulAdd.5" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)">FPMulAdd</a>(addend, value1, value2, fpcr, fpexc);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/BFMulAddH_ZA" mylink="shared.functions.float.bfloat.BFMulAddH_ZA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BFMulAddH_ZA()</line>
<line>// ==============</line>
<line>// Used by SME2 ZA-targeting BFMLAL and BFMLSL instructions.</line>
<line></line>
<line link="impl-shared.BFMulAddH_ZA.4" hover="function: bits(N) BFMulAddH_ZA(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, FPCRType fpcr)" conts="BFMulAddH_ZA">bits(N) <anchor link="impl-shared.BFMulAddH_ZA.4" hover="function: bits(N) BFMulAddH_ZA(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, FPCRType fpcr)">BFMulAddH_ZA</anchor>(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    bits(N) value1 = op1 : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(N DIV 2);</line>
<line>    bits(N) value2 = op2 : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(N DIV 2);</line>
<line>    return <a link="impl-shared.FPMulAdd_ZA.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd_ZA(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr_in)">FPMulAdd_ZA</a>(addend, value1, value2, fpcr);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/BFMulAdd_ZA" mylink="shared.functions.float.bfloat.BFMulAdd_ZA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BFMulAdd_ZA()</line>
<line>// =============</line>
<line>// Non-widening BFloat16 fused multiply-add used by SME2 ZA-targeting instructions.</line>
<line></line>
<line link="impl-shared.BFMulAdd_ZA.4" hover="function: bits(16) BFMulAdd_ZA(bits(16) addend, bits(16) op1, bits(16) op2, FPCRType fpcr_in)" conts="BFMulAdd_ZA">bits(16) <anchor link="impl-shared.BFMulAdd_ZA.4" hover="function: bits(16) BFMulAdd_ZA(bits(16) addend, bits(16) op1, bits(16) op2, FPCRType fpcr_in)">BFMulAdd_ZA</anchor>(bits(16) addend, bits(16) op1, bits(16) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in)</line>
<line>    boolean fpexc = FALSE;</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    fpcr.DN = '1';          // Generate default NaN values</line>
<line>    return <a link="impl-shared.BFMulAdd.5" file="shared_pseudocode.xml" hover="function: bits(16) BFMulAdd(bits(16) addend, bits(16) op1, bits(16) op2, FPCRType fpcr, boolean fpexc)">BFMulAdd</a>(addend, op1, op2, fpcr, fpexc);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/BFMulH" mylink="shared.functions.float.bfloat.BFMulH" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BFMulH()</line>
<line>// ========</line>
<line>// BFloat16 widening multiply to single-precision following BFloat16</line>
<line>// computation behaviors.</line>
<line></line>
<line link="impl-shared.BFMulH.2" hover="function: bits(32) BFMulH(bits(16) op1, bits(16) op2)" conts="BFMulH">bits(32) <anchor link="impl-shared.BFMulH.2" hover="function: bits(32) BFMulH(bits(16) op1, bits(16) op2)">BFMulH</anchor>(bits(16) op1, bits(16) op2)</line>
<line></line>
<line>    bits(32) result;</line>
<line></line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = FPCR[];</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.BFUnpack.1" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) BFUnpack(bits(N) fpval)">BFUnpack</a>(op1);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.BFUnpack.1" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) BFUnpack(bits(N) fpval)">BFUnpack</a>(op2);</line>
<line>    if type1 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> || type2 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, 32);</line>
<line>    else</line>
<line>        inf1 = (type1 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        inf2 = (type2 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        zero1 = (type1 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line>        zero2 = (type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line>        if (inf1 &amp;&amp; zero2) || (zero1 &amp;&amp; inf2) then</line>
<line>            result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, 32);</line>
<line>        elsif inf1 || inf2 then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>(sign1 EOR sign2, 32);</line>
<line>        elsif zero1 || zero2 then</line>
<line>            result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign1 EOR sign2, 32);</line>
<line>        else</line>
<line>            result = <a link="impl-shared.BFRound.1" file="shared_pseudocode.xml" hover="function: bits(32) BFRound(real op)">BFRound</a>(value1*value2);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/BFNeg" mylink="shared.functions.float.bfloat.BFNeg" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BFNeg()</line>
<line>// =======</line>
<line></line>
<line link="impl-shared.BFNeg.1" hover="function: bits(16) BFNeg(bits(16) op)" conts="BFNeg">bits(16) <anchor link="impl-shared.BFNeg.1" hover="function: bits(16) BFNeg(bits(16) op)">BFNeg</anchor>(bits(16) op)</line>
<line>    boolean honor_altfp = TRUE;    // Honor alternate handling</line>
<line>    return <a link="impl-shared.BFNeg.2" file="shared_pseudocode.xml" hover="function: bits(16) BFNeg(bits(16) op, boolean honor_altfp)">BFNeg</a>(op, honor_altfp);</line>
<line></line>
<line>// BFNeg()</line>
<line>// =======</line>
<line></line>
<line link="impl-shared.BFNeg.2" hover="function: bits(16) BFNeg(bits(16) op, boolean honor_altfp)" conts="BFNeg">bits(16) <anchor link="impl-shared.BFNeg.2" hover="function: bits(16) BFNeg(bits(16) op, boolean honor_altfp)">BFNeg</anchor>(bits(16) op, boolean honor_altfp)</line>
<line></line>
<line>    if honor_altfp &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() then</line>
<line>        <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = FPCR[];</line>
<line>        if fpcr.AH == '1' then</line>
<line>            boolean fpexc = FALSE;</line>
<line>            boolean isbfloat16 = TRUE;</line>
<line>            (fptype, -, -) = <a link="impl-shared.FPUnpackBase.4" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpackBase(bits(N) fpval, FPCRType fpcr_in, boolean fpexc, boolean isbfloat16)">FPUnpackBase</a>(op, fpcr, fpexc, isbfloat16);</line>
<line>            if fptype IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>} then</line>
<line></line>
<line>                return op;        // When fpcr.AH=1, sign of NaN has no consequence</line>
<line></line>
<line>    return NOT(op&lt;15&gt;) : op&lt;14:0&gt;;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/BFRound" mylink="shared.functions.float.bfloat.BFRound" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BFRound()</line>
<line>// =========</line>
<line>// Converts a real number OP into a single-precision value using the</line>
<line>// Round to Odd rounding mode and following BFloat16 computation behaviors.</line>
<line></line>
<line link="impl-shared.BFRound.1" hover="function: bits(32) BFRound(real op)" conts="BFRound">bits(32) <anchor link="impl-shared.BFRound.1" hover="function: bits(32) BFRound(real op)">BFRound</anchor>(real op)</line>
<line></line>
<line>    assert op != 0.0;</line>
<line>    bits(32) result;</line>
<line></line>
<line>    // Format parameters - minimum exponent, numbers of exponent and fraction bits.</line>
<line>    minimum_exp = -126;  E = 8;  F = 23;</line>
<line></line>
<line>    // Split value into sign, unrounded mantissa and exponent.</line>
<line>    bit sign;</line>
<line>    real mantissa;</line>
<line>    if op &lt; 0.0 then</line>
<line>        sign = '1';  mantissa = -op;</line>
<line>    else</line>
<line>        sign = '0';  mantissa = op;</line>
<line>    exponent = 0;</line>
<line>    while mantissa &lt; 1.0 do</line>
<line>        mantissa = mantissa * 2.0;  exponent = exponent - 1;</line>
<line>    while mantissa &gt;= 2.0 do</line>
<line>        mantissa = mantissa / 2.0;  exponent = exponent + 1;</line>
<line></line>
<line>    // Fixed Flush-to-zero.</line>
<line>    if exponent &lt; minimum_exp then</line>
<line>        return <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign, 32);</line>
<line></line>
<line>    // Start creating the exponent value for the result. Start by biasing the actual exponent</line>
<line>    // so that the minimum exponent becomes 1, lower values 0 (indicating possible underflow).</line>
<line>    biased_exp = <a link="impl-shared.Max.2" file="shared_pseudocode.xml" hover="function: integer Max(integer a, integer b)">Max</a>((exponent - minimum_exp) + 1, 0);</line>
<line>    if biased_exp == 0 then mantissa = mantissa / 2.0^(minimum_exp - exponent);</line>
<line></line>
<line>    // Get the unrounded mantissa as an integer, and the "units in last place" rounding error.</line>
<line>    int_mant = <a link="impl-shared.RoundDown.1" file="shared_pseudocode.xml" hover="function: integer RoundDown(real x)">RoundDown</a>(mantissa * 2.0^F);  // &lt; 2.0^F if biased_exp == 0, &gt;= 2.0^F if not</line>
<line>    error = mantissa * 2.0^F - Real(int_mant);</line>
<line></line>
<line>    // Round to Odd</line>
<line>    if error != 0.0 then</line>
<line>        int_mant&lt;0&gt; = '1';</line>
<line></line>
<line>    // Deal with overflow and generate result.</line>
<line>    if biased_exp &gt;= 2^E - 1 then</line>
<line>        result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>(sign, 32);      // Overflows generate appropriately-signed Infinity</line>
<line>    else</line>
<line>        result = sign : biased_exp&lt;30-F:0&gt; : int_mant&lt;F-1:0&gt;;</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/BFSub" mylink="shared.functions.float.bfloat.BFSub" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BFSub()</line>
<line>// =======</line>
<line>// Non-widening BFloat16 subtraction used by SVE2 instructions.</line>
<line></line>
<line link="impl-shared.BFSub.3" hover="function: bits(16) BFSub(bits(16) op1, bits(16) op2, FPCRType fpcr)" conts="BFSub">bits(16) <anchor link="impl-shared.BFSub.3" hover="function: bits(16) BFSub(bits(16) op1, bits(16) op2, FPCRType fpcr)">BFSub</anchor>(bits(16) op1, bits(16) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    boolean fpexc = TRUE;</line>
<line>    return <a link="impl-shared.BFSub.4" file="shared_pseudocode.xml" hover="function: bits(16) BFSub(bits(16) op1, bits(16) op2, FPCRType fpcr, boolean fpexc)">BFSub</a>(op1, op2, fpcr, fpexc);</line>
<line></line>
<line>// BFSub()</line>
<line>// =======</line>
<line>// Non-widening BFloat16 subtraction following computational behaviors</line>
<line>// corresponding to instructions that read and write BFloat16 values.</line>
<line>// Calculates op1 - op2.</line>
<line>// The 'fpcr' argument supplies the FPCR control bits.</line>
<line></line>
<line link="impl-shared.BFSub.4" hover="function: bits(16) BFSub(bits(16) op1, bits(16) op2, FPCRType fpcr, boolean fpexc)" conts="BFSub">bits(16) <anchor link="impl-shared.BFSub.4" hover="function: bits(16) BFSub(bits(16) op1, bits(16) op2, FPCRType fpcr, boolean fpexc)">BFSub</anchor>(bits(16) op1, bits(16) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, boolean fpexc)</line>
<line></line>
<line>    <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(fpcr);</line>
<line>    boolean done;</line>
<line>    bits(32) result;</line>
<line></line>
<line>    bits(32) op1_s = op1 : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>    bits(32) op2_s = op2 : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op1_s, fpcr, fpexc);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op2_s, fpcr, fpexc);</line>
<line></line>
<line>    (done,result) = <a link="impl-shared.FPProcessNaNs.6" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs(FPType type1, FPType type2, bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)">FPProcessNaNs</a>(type1, type2, op1_s, op2_s, fpcr, fpexc);</line>
<line></line>
<line>    if !done then</line>
<line>        inf1 = (type1 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        inf2 = (type2 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        zero1 = (type1 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line>        zero2 = (type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line></line>
<line>        if inf1 &amp;&amp; inf2 &amp;&amp; sign1 == sign2 then</line>
<line>            result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, 32);</line>
<line>            if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>        elsif (inf1 &amp;&amp; sign1 == '0') || (inf2 &amp;&amp; sign2 == '1') then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('0', 32);</line>
<line>        elsif (inf1 &amp;&amp; sign1 == '1') || (inf2 &amp;&amp; sign2 == '0') then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('1', 32);</line>
<line>        elsif zero1 &amp;&amp; zero2 &amp;&amp; sign1 == NOT(sign2) then</line>
<line>            result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign1, 32);</line>
<line>        else</line>
<line>            result_value = value1 - value2;</line>
<line>            if result_value == 0.0 then  // Sign of exact zero result depends on rounding mode</line>
<line>                result_sign = if rounding == <a link="FPRounding_NEGINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_NEGINF</a> then '1' else '0';</line>
<line>                result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(result_sign, 32);</line>
<line>            else</line>
<line>                result = <a link="impl-shared.FPRoundBF.4" file="shared_pseudocode.xml" hover="function: bits(32) FPRoundBF(real op, FPCRType fpcr, FPRounding rounding, boolean fpexc)">FPRoundBF</a>(result_value, fpcr, rounding, fpexc);</line>
<line></line>
<line>        if fpexc then <a link="impl-shared.FPProcessDenorms.4" file="shared_pseudocode.xml" hover="function: FPProcessDenorms(FPType type1, FPType type2, integer N, FPCRType fpcr)">FPProcessDenorms</a>(type1, type2, 32, fpcr);</line>
<line></line>
<line>    return result&lt;31:16&gt;;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/BFSub_ZA" mylink="shared.functions.float.bfloat.BFSub_ZA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BFSub_ZA()</line>
<line>// ==========</line>
<line>// Non-widening BFloat16 subtraction used by SME2 ZA-targeting instructions.</line>
<line></line>
<line link="impl-shared.BFSub_ZA.3" hover="function: bits(16) BFSub_ZA(bits(16) op1, bits(16) op2, FPCRType fpcr_in)" conts="BFSub_ZA">bits(16) <anchor link="impl-shared.BFSub_ZA.3" hover="function: bits(16) BFSub_ZA(bits(16) op1, bits(16) op2, FPCRType fpcr_in)">BFSub_ZA</anchor>(bits(16) op1, bits(16) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in)</line>
<line>    boolean fpexc = FALSE;</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    fpcr.DN = '1';          // Generate default NaN values</line>
<line>    return <a link="impl-shared.BFSub.4" file="shared_pseudocode.xml" hover="function: bits(16) BFSub(bits(16) op1, bits(16) op2, FPCRType fpcr, boolean fpexc)">BFSub</a>(op1, op2, fpcr, fpexc);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/BFUnpack" mylink="shared.functions.float.bfloat.BFUnpack" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BFUnpack()</line>
<line>// ==========</line>
<line>// Unpacks a BFloat16 or single-precision value into its type,</line>
<line>// sign bit and real number that it represents.</line>
<line>// The real number result has the correct sign for numbers and infinities,</line>
<line>// is very large in magnitude for infinities, and is 0.0 for NaNs.</line>
<line>// (These values are chosen to simplify the description of</line>
<line>// comparisons and conversions.)</line>
<line></line>
<line link="impl-shared.BFUnpack.1" hover="function: (FPType, bit, real) BFUnpack(bits(N) fpval)" conts="BFUnpack">(FPType, bit, real) <anchor link="impl-shared.BFUnpack.1" hover="function: (FPType, bit, real) BFUnpack(bits(N) fpval)">BFUnpack</anchor>(bits(N) fpval)</line>
<line></line>
<line>    assert N IN {16,32};</line>
<line></line>
<line>    bit sign;</line>
<line>    bits(8) exp;</line>
<line>    bits(23) frac;</line>
<line>    if N == 16 then</line>
<line>        sign   = fpval&lt;15&gt;;</line>
<line>        exp    = fpval&lt;14:7&gt;;</line>
<line>        frac   = fpval&lt;6:0&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>    else  // N == 32</line>
<line>        sign   = fpval&lt;31&gt;;</line>
<line>        exp    = fpval&lt;30:23&gt;;</line>
<line>        frac   = fpval&lt;22:0&gt;;</line>
<line></line>
<line>    <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> fptype;</line>
<line>    real value;</line>
<line>    if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(exp) then</line>
<line>        fptype = <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>;  value = 0.0;    // Fixed Flush to Zero</line>
<line>    elsif <a link="impl-shared.IsOnes.1" file="shared_pseudocode.xml" hover="function: boolean IsOnes(bits(N) x)">IsOnes</a>(exp) then</line>
<line>        if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(frac) then</line>
<line>            fptype = <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>;  value = 2.0^1000000;</line>
<line>        else    // no SNaN for BF16 arithmetic</line>
<line>            fptype = <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>; value = 0.0;</line>
<line>    else</line>
<line>        fptype = <a link="FPType_Nonzero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Nonzero</a>;</line>
<line>        value = 2.0^(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(exp)-127) * (1.0 + Real(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(frac)) * 2.0^-23);</line>
<line></line>
<line>    if sign == '1' then value = -value;</line>
<line></line>
<line>    return (fptype, sign, value);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/BFZero" mylink="shared.functions.float.bfloat.BFZero" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BFZero()</line>
<line>// ========</line>
<line></line>
<line link="impl-shared.BFZero.1" hover="function: bits(16) BFZero(bit sign)" conts="BFZero">bits(16) <anchor link="impl-shared.BFZero.1" hover="function: bits(16) BFZero(bit sign)">BFZero</anchor>(bit sign)</line>
<line>    return sign : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8) : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(7);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/FPAdd_BF16" mylink="shared.functions.float.bfloat.FPAdd_BF16" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPAdd_BF16()</line>
<line>// ============</line>
<line>// Single-precision add following BFloat16 computation behaviors.</line>
<line></line>
<line link="impl-shared.FPAdd_BF16.2" hover="function: bits(32) FPAdd_BF16(bits(32) op1, bits(32) op2)" conts="FPAdd_BF16">bits(32) <anchor link="impl-shared.FPAdd_BF16.2" hover="function: bits(32) FPAdd_BF16(bits(32) op1, bits(32) op2)">FPAdd_BF16</anchor>(bits(32) op1, bits(32) op2)</line>
<line></line>
<line>    bits(32) result;</line>
<line></line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = FPCR[];</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.BFUnpack.1" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) BFUnpack(bits(N) fpval)">BFUnpack</a>(op1);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.BFUnpack.1" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) BFUnpack(bits(N) fpval)">BFUnpack</a>(op2);</line>
<line>    if type1 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> || type2 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, 32);</line>
<line>    else</line>
<line>        inf1 = (type1 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        inf2 = (type2 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        zero1 = (type1 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line>        zero2 = (type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line>        if inf1 &amp;&amp; inf2 &amp;&amp; sign1 == NOT(sign2) then</line>
<line>            result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, 32);</line>
<line>        elsif (inf1 &amp;&amp; sign1 == '0') || (inf2 &amp;&amp; sign2 == '0') then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('0', 32);</line>
<line>        elsif (inf1 &amp;&amp; sign1 == '1') || (inf2 &amp;&amp; sign2 == '1') then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('1', 32);</line>
<line>        elsif zero1 &amp;&amp; zero2 &amp;&amp; sign1 == sign2 then</line>
<line>            result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign1, 32);</line>
<line>        else</line>
<line>            result_value = value1 + value2;</line>
<line>            if result_value == 0.0 then</line>
<line>                result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>('0', 32);    // Positive sign when Round to Odd</line>
<line>            else</line>
<line>                result = <a link="impl-shared.BFRound.1" file="shared_pseudocode.xml" hover="function: bits(32) BFRound(real op)">BFRound</a>(result_value);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/FPConvertBF" mylink="shared.functions.float.bfloat.FPConvertBF" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPConvertBF()</line>
<line>// =============</line>
<line>// Converts a single-precision OP to BFloat16 value with using rounding mode of</line>
<line>// Round to Nearest Even when executed from AArch64 state and</line>
<line>// FPCR.AH == '1', otherwise rounding is controlled by FPCR/FPSCR.</line>
<line></line>
<line link="impl-shared.FPConvertBF.3" hover="function: bits(16) FPConvertBF(bits(32) op, FPCRType fpcr_in, FPRounding rounding_in)" conts="FPConvertBF">bits(16) <anchor link="impl-shared.FPConvertBF.3" hover="function: bits(16) FPConvertBF(bits(32) op, FPCRType fpcr_in, FPRounding rounding_in)">FPConvertBF</anchor>(bits(32) op, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in, <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding_in)</line>
<line></line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = rounding_in;</line>
<line>    bits(32) result;                                // BF16 value in top 16 bits</line>
<line>    boolean altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1';</line>
<line>    boolean fpexc = !altfp;                         // Generate no floating-point exceptions</line>
<line>    if altfp then fpcr.&lt;FIZ,FZ&gt; = '11';             // Flush denormal input and output to zero</line>
<line>    if altfp then rounding = <a link="FPRounding_TIEEVEN" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEEVEN</a>;    // Use RNE rounding mode</line>
<line></line>
<line>    // Unpack floating-point operand, with always flush-to-zero if fpcr.AH == '1'.</line>
<line>    (fptype,sign,value) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op, fpcr, fpexc);</line>
<line></line>
<line>    if fptype == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> || fptype == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        if fpcr.DN == '1' then</line>
<line>            result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, 32);</line>
<line>        else</line>
<line>            result = <a link="impl-shared.FPConvertNaN.2" file="shared_pseudocode.xml" hover="function: bits(M) FPConvertNaN(bits(N) op, integer M)">FPConvertNaN</a>(op, 32);</line>
<line>        if fptype == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> then</line>
<line>            if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>    elsif fptype == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a> then</line>
<line>        result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>(sign, 32);</line>
<line>    elsif fptype == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> then</line>
<line>        result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign, 32);</line>
<line>    else</line>
<line>        result = <a link="impl-shared.FPRoundBF.4" file="shared_pseudocode.xml" hover="function: bits(32) FPRoundBF(real op, FPCRType fpcr, FPRounding rounding, boolean fpexc)">FPRoundBF</a>(value, fpcr, rounding, fpexc);</line>
<line></line>
<line>    // Returns correctly rounded BF16 value from top 16 bits</line>
<line>    return result&lt;31:16&gt;;</line>
<line></line>
<line>// FPConvertBF()</line>
<line>// =============</line>
<line>// Converts a single-precision operand to BFloat16 value.</line>
<line></line>
<line link="impl-shared.FPConvertBF.2" hover="function: bits(16) FPConvertBF(bits(32) op, FPCRType fpcr)" conts="FPConvertBF">bits(16) <anchor link="impl-shared.FPConvertBF.2" hover="function: bits(16) FPConvertBF(bits(32) op, FPCRType fpcr)">FPConvertBF</anchor>(bits(32) op, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    return <a link="impl-shared.FPConvertBF.3" file="shared_pseudocode.xml" hover="function: bits(16) FPConvertBF(bits(32) op, FPCRType fpcr_in, FPRounding rounding_in)">FPConvertBF</a>(op, fpcr, <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(fpcr));</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/bfloat/FPRoundBF" mylink="shared.functions.float.bfloat.FPRoundBF" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPRoundBF()</line>
<line>// ===========</line>
<line>// Converts a real number OP into a BFloat16 value using the supplied</line>
<line>// rounding mode RMODE. The 'fpexc' argument controls the generation of</line>
<line>// floating-point exceptions.</line>
<line></line>
<line link="impl-shared.FPRoundBF.4" hover="function: bits(32) FPRoundBF(real op, FPCRType fpcr, FPRounding rounding, boolean fpexc)" conts="FPRoundBF">bits(32) <anchor link="impl-shared.FPRoundBF.4" hover="function: bits(32) FPRoundBF(real op, FPCRType fpcr, FPRounding rounding, boolean fpexc)">FPRoundBF</anchor>(real op, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding, boolean fpexc)</line>
<line>    boolean isbfloat16 = TRUE;</line>
<line>    return <a link="impl-shared.FPRoundBase.6" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundBase(real op, FPCRType fpcr, FPRounding rounding, boolean isbfloat16, boolean fpexc, integer N)">FPRoundBase</a>(op, fpcr, rounding, isbfloat16, fpexc, 32);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fixedtofp/FixedToFP" mylink="shared.functions.float.fixedtofp.FixedToFP" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FixedToFP()</line>
<line>// ===========</line>
<line></line>
<line>// Convert M-bit fixed point 'op' with FBITS fractional bits to</line>
<line>// N-bit precision floating point, controlled by UNSIGNED and ROUNDING.</line>
<line></line>
<line link="impl-shared.FixedToFP.6" hover="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer N)" conts="FixedToFP">bits(N) <anchor link="impl-shared.FixedToFP.6" hover="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer N)">FixedToFP</anchor>(bits(M) op, integer fbits, boolean unsigned, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr,</line>
<line>                  <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding, integer N)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    assert M IN {16,32,64};</line>
<line>    bits(N) result;</line>
<line>    assert fbits &gt;= 0;</line>
<line>    assert rounding != <a link="FPRounding_ODD" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ODD</a>;</line>
<line></line>
<line>    // Correct signed-ness</line>
<line>    int_operand = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op, unsigned);</line>
<line></line>
<line>    // Scale by fractional bits and generate a real value</line>
<line>    real_operand = Real(int_operand) / 2.0^fbits;</line>
<line></line>
<line>    if real_operand == 0.0 then</line>
<line>        result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>('0', N);</line>
<line>    else</line>
<line>        result = <a link="impl-shared.FPRound.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRound(real op, FPCRType fpcr_in, FPRounding rounding, integer N)">FPRound</a>(real_operand, fpcr, rounding, N);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpabs/FPAbs" mylink="shared.functions.float.fpabs.FPAbs" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPAbs()</line>
<line>// =======</line>
<line></line>
<line link="impl-shared.FPAbs.1" hover="function: bits(N) FPAbs(bits(N) op)" conts="FPAbs">bits(N) <anchor link="impl-shared.FPAbs.1" hover="function: bits(N) FPAbs(bits(N) op)">FPAbs</anchor>(bits(N) op)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    if !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() then</line>
<line>        <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = FPCR[];</line>
<line>        if fpcr.AH == '1' then</line>
<line>            (fptype, -, -) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op, fpcr, FALSE);</line>
<line>            if fptype IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>} then</line>
<line>                return op;        // When fpcr.AH=1, sign of NaN has no consequence</line>
<line></line>
<line>    return '0' : op&lt;N-2:0&gt;;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpadd/FPAdd" mylink="shared.functions.float.fpadd.FPAdd" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPAdd()</line>
<line>// =======</line>
<line></line>
<line link="impl-shared.FPAdd.3" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)" conts="FPAdd">bits(N) <anchor link="impl-shared.FPAdd.3" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</anchor>(bits(N) op1, bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    boolean fpexc = TRUE;       // Generate floating-point exceptions</line>
<line>    return <a link="impl-shared.FPAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)">FPAdd</a>(op1, op2, fpcr, fpexc);</line>
<line></line>
<line>// FPAdd()</line>
<line>// =======</line>
<line></line>
<line link="impl-shared.FPAdd.4" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)" conts="FPAdd">bits(N) <anchor link="impl-shared.FPAdd.4" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)">FPAdd</anchor>(bits(N) op1, bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, boolean fpexc)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(fpcr);</line>
<line></line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op1, fpcr, fpexc);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op2, fpcr, fpexc);</line>
<line></line>
<line>    (done,result) = <a link="impl-shared.FPProcessNaNs.6" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs(FPType type1, FPType type2, bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)">FPProcessNaNs</a>(type1, type2, op1, op2, fpcr, fpexc);</line>
<line>    if !done then</line>
<line>        inf1  = (type1 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);  inf2  = (type2 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        zero1 = (type1 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);      zero2 = (type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line>        if inf1 &amp;&amp; inf2 &amp;&amp; sign1 == NOT(sign2) then</line>
<line>            result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, N);</line>
<line>            if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>        elsif (inf1 &amp;&amp; sign1 == '0') || (inf2 &amp;&amp; sign2 == '0') then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('0', N);</line>
<line>        elsif (inf1 &amp;&amp; sign1 == '1') || (inf2 &amp;&amp; sign2 == '1') then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('1', N);</line>
<line>        elsif zero1 &amp;&amp; zero2 &amp;&amp; sign1 == sign2 then</line>
<line>            result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign1, N);</line>
<line>        else</line>
<line>            result_value = value1 + value2;</line>
<line>            if result_value == 0.0 then  // Sign of exact zero result depends on rounding mode</line>
<line>                result_sign = if rounding == <a link="FPRounding_NEGINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_NEGINF</a> then '1' else '0';</line>
<line>                result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(result_sign, N);</line>
<line>            else</line>
<line>                result = <a link="impl-shared.FPRound.5" file="shared_pseudocode.xml" hover="function: bits(N) FPRound(real op, FPCRType fpcr_in, FPRounding rounding, boolean fpexc, integer N)">FPRound</a>(result_value, fpcr, rounding, fpexc, N);</line>
<line></line>
<line>        if fpexc then <a link="impl-shared.FPProcessDenorms.4" file="shared_pseudocode.xml" hover="function: FPProcessDenorms(FPType type1, FPType type2, integer N, FPCRType fpcr)">FPProcessDenorms</a>(type1, type2, N, fpcr);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpadd/FPAdd_ZA" mylink="shared.functions.float.fpadd.FPAdd_ZA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPAdd_ZA()</line>
<line>// ==========</line>
<line>// Calculates op1+op2 for SME2 ZA-targeting instructions.</line>
<line></line>
<line link="impl-shared.FPAdd_ZA.3" hover="function: bits(N) FPAdd_ZA(bits(N) op1, bits(N) op2, FPCRType fpcr_in)" conts="FPAdd_ZA">bits(N) <anchor link="impl-shared.FPAdd_ZA.3" hover="function: bits(N) FPAdd_ZA(bits(N) op1, bits(N) op2, FPCRType fpcr_in)">FPAdd_ZA</anchor>(bits(N) op1, bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in)</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    boolean fpexc = FALSE;      // Do not generate floating-point exceptions</line>
<line>    fpcr.DN = '1';              // Generate default NaN values</line>
<line>    return <a link="impl-shared.FPAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)">FPAdd</a>(op1, op2, fpcr, fpexc);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpcompare/FPCompare" mylink="shared.functions.float.fpcompare.FPCompare" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPCompare()</line>
<line>// ===========</line>
<line></line>
<line link="impl-shared.FPCompare.4" hover="function: bits(4) FPCompare(bits(N) op1, bits(N) op2, boolean signal_nans, FPCRType fpcr)" conts="FPCompare">bits(4) <anchor link="impl-shared.FPCompare.4" hover="function: bits(4) FPCompare(bits(N) op1, bits(N) op2, boolean signal_nans, FPCRType fpcr)">FPCompare</anchor>(bits(N) op1, bits(N) op2, boolean signal_nans, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op1, fpcr);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op2, fpcr);</line>
<line></line>
<line>    bits(4) result;</line>
<line>    if type1 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>} || type2 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>} then</line>
<line>        result = '0011';</line>
<line>        if type1 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> || type2 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> || signal_nans then</line>
<line>            <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>    else</line>
<line>        // All non-NaN cases can be evaluated on the values produced by FPUnpack()</line>
<line>        if value1 == value2 then</line>
<line>            result = '0110';</line>
<line>        elsif value1 &lt; value2 then</line>
<line>            result = '1000';</line>
<line>        else  // value1 &gt; value2</line>
<line>            result = '0010';</line>
<line></line>
<line>        <a link="impl-shared.FPProcessDenorms.4" file="shared_pseudocode.xml" hover="function: FPProcessDenorms(FPType type1, FPType type2, integer N, FPCRType fpcr)">FPProcessDenorms</a>(type1, type2, N, fpcr);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpcompareeq/FPCompareEQ" mylink="shared.functions.float.fpcompareeq.FPCompareEQ" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPCompareEQ()</line>
<line>// =============</line>
<line></line>
<line link="impl-shared.FPCompareEQ.3" hover="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)" conts="FPCompareEQ">boolean <anchor link="impl-shared.FPCompareEQ.3" hover="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</anchor>(bits(N) op1, bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op1, fpcr);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op2, fpcr);</line>
<line></line>
<line>    boolean result;</line>
<line>    if type1 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>} || type2 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>} then</line>
<line>        result = FALSE;</line>
<line>        if type1 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> || type2 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> then</line>
<line>            <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>    else</line>
<line>        // All non-NaN cases can be evaluated on the values produced by FPUnpack()</line>
<line>        result = (value1 == value2);</line>
<line>        <a link="impl-shared.FPProcessDenorms.4" file="shared_pseudocode.xml" hover="function: FPProcessDenorms(FPType type1, FPType type2, integer N, FPCRType fpcr)">FPProcessDenorms</a>(type1, type2, N, fpcr);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpcomparege/FPCompareGE" mylink="shared.functions.float.fpcomparege.FPCompareGE" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPCompareGE()</line>
<line>// =============</line>
<line></line>
<line link="impl-shared.FPCompareGE.3" hover="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)" conts="FPCompareGE">boolean <anchor link="impl-shared.FPCompareGE.3" hover="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</anchor>(bits(N) op1, bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op1, fpcr);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op2, fpcr);</line>
<line></line>
<line>    boolean result;</line>
<line>    if type1 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>} || type2 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>} then</line>
<line>        result = FALSE;</line>
<line>        <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>    else</line>
<line>        // All non-NaN cases can be evaluated on the values produced by FPUnpack()</line>
<line>        result = (value1 &gt;= value2);</line>
<line>        <a link="impl-shared.FPProcessDenorms.4" file="shared_pseudocode.xml" hover="function: FPProcessDenorms(FPType type1, FPType type2, integer N, FPCRType fpcr)">FPProcessDenorms</a>(type1, type2, N, fpcr);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpcomparegt/FPCompareGT" mylink="shared.functions.float.fpcomparegt.FPCompareGT" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPCompareGT()</line>
<line>// =============</line>
<line></line>
<line link="impl-shared.FPCompareGT.3" hover="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)" conts="FPCompareGT">boolean <anchor link="impl-shared.FPCompareGT.3" hover="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</anchor>(bits(N) op1, bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op1, fpcr);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op2, fpcr);</line>
<line></line>
<line>    boolean result;</line>
<line>    if type1 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>} || type2 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>} then</line>
<line>        result = FALSE;</line>
<line>        <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>    else</line>
<line>        // All non-NaN cases can be evaluated on the values produced by FPUnpack()</line>
<line>        result = (value1 &gt; value2);</line>
<line>        <a link="impl-shared.FPProcessDenorms.4" file="shared_pseudocode.xml" hover="function: FPProcessDenorms(FPType type1, FPType type2, integer N, FPCRType fpcr)">FPProcessDenorms</a>(type1, type2, N, fpcr);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpconvert/FPConvert" mylink="shared.functions.float.fpconvert.FPConvert" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPConvert()</line>
<line>// ===========</line>
<line></line>
<line>// Convert floating point 'op' with N-bit precision to M-bit precision,</line>
<line>// with rounding controlled by ROUNDING.</line>
<line>// This is used by the FP-to-FP conversion instructions and so for</line>
<line>// half-precision data ignores FZ16, but observes AHP.</line>
<line></line>
<line link="impl-shared.FPConvert.4" hover="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, FPRounding rounding, integer M)" conts="FPConvert">bits(M) <anchor link="impl-shared.FPConvert.4" hover="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, FPRounding rounding, integer M)">FPConvert</anchor>(bits(N) op, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding, integer M)</line>
<line></line>
<line>    assert M IN {16,32,64};</line>
<line>    assert N IN {16,32,64};</line>
<line>    bits(M) result;</line>
<line></line>
<line>    // Unpack floating-point operand optionally with flush-to-zero.</line>
<line>    (fptype,sign,value) = <a link="impl-shared.FPUnpackCV.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpackCV(bits(N) fpval, FPCRType fpcr_in)">FPUnpackCV</a>(op, fpcr);</line>
<line></line>
<line>    alt_hp = (M == 16) &amp;&amp; (fpcr.AHP == '1');</line>
<line></line>
<line>    if fptype == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> || fptype == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        if alt_hp then</line>
<line>            result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign, M);</line>
<line>        elsif fpcr.DN == '1' then</line>
<line>            result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, M);</line>
<line>        else</line>
<line>            result = <a link="impl-shared.FPConvertNaN.2" file="shared_pseudocode.xml" hover="function: bits(M) FPConvertNaN(bits(N) op, integer M)">FPConvertNaN</a>(op, M);</line>
<line>        if fptype == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> || alt_hp then</line>
<line>            <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>,fpcr);</line>
<line>    elsif fptype == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a> then</line>
<line>        if alt_hp then</line>
<line>            result = sign:<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(M-1);</line>
<line>            <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>        else</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>(sign, M);</line>
<line>    elsif fptype == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> then</line>
<line>        result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign, M);</line>
<line>    else</line>
<line>        result = <a link="impl-shared.FPRoundCV.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundCV(real op, FPCRType fpcr_in, FPRounding rounding, integer N)">FPRoundCV</a>(value, fpcr, rounding, M);</line>
<line>        <a link="impl-shared.FPProcessDenorm.3" file="shared_pseudocode.xml" hover="function: FPProcessDenorm(FPType fptype, integer N, FPCRType fpcr)">FPProcessDenorm</a>(fptype, N, fpcr);</line>
<line></line>
<line>    return result;</line>
<line></line>
<line>// FPConvert()</line>
<line>// ===========</line>
<line></line>
<line link="impl-shared.FPConvert.3" hover="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, integer M)" conts="FPConvert">bits(M) <anchor link="impl-shared.FPConvert.3" hover="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, integer M)">FPConvert</anchor>(bits(N) op, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, integer M)</line>
<line>    return <a link="impl-shared.FPConvert.4" file="shared_pseudocode.xml" hover="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, FPRounding rounding, integer M)">FPConvert</a>(op, fpcr, <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(fpcr), M);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpconvertnan/FPConvertNaN" mylink="shared.functions.float.fpconvertnan.FPConvertNaN" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPConvertNaN()</line>
<line>// ==============</line>
<line>// Converts a NaN of one floating-point type to another</line>
<line></line>
<line link="impl-shared.FPConvertNaN.2" hover="function: bits(M) FPConvertNaN(bits(N) op, integer M)" conts="FPConvertNaN">bits(M) <anchor link="impl-shared.FPConvertNaN.2" hover="function: bits(M) FPConvertNaN(bits(N) op, integer M)">FPConvertNaN</anchor>(bits(N) op, integer M)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    assert M IN {16,32,64};</line>
<line>    bits(M) result;</line>
<line>    bits(51) frac;</line>
<line></line>
<line>    sign = op&lt;N-1&gt;;</line>
<line></line>
<line>    // Unpack payload from input NaN</line>
<line>    case N of</line>
<line>        when 64 frac = op&lt;50:0&gt;;</line>
<line>        when 32 frac = op&lt;21:0&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(29);</line>
<line>        when 16 frac = op&lt;8:0&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(42);</line>
<line></line>
<line>    // Repack payload into output NaN, while</line>
<line>    // converting an SNaN to a QNaN.</line>
<line>    case M of</line>
<line>        when 64 result = sign:<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(M-52):frac;</line>
<line>        when 32 result = sign:<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(M-23):frac&lt;50:29&gt;;</line>
<line>        when 16 result = sign:<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(M-10):frac&lt;50:42&gt;;</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpcrtype/FPCRType" mylink="shared.functions.float.fpcrtype.FPCRType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="FPCRType" hover="type FPCRType" conts="FPCRType">type <anchor link="FPCRType" hover="type FPCRType">FPCRType</anchor>;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpdecoderm/FPDecodeRM" mylink="shared.functions.float.fpdecoderm.FPDecodeRM" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPDecodeRM()</line>
<line>// ============</line>
<line></line>
<line>// Decode most common AArch32 floating-point rounding encoding.</line>
<line></line>
<line link="impl-shared.FPDecodeRM.1" hover="function: FPRounding FPDecodeRM(bits(2) rm)" conts="FPDecodeRM">FPRounding <anchor link="impl-shared.FPDecodeRM.1" hover="function: FPRounding FPDecodeRM(bits(2) rm)">FPDecodeRM</anchor>(bits(2) rm)</line>
<line></line>
<line>    <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> result;</line>
<line>    case rm of</line>
<line>        when '00' result = <a link="FPRounding_TIEAWAY" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEAWAY</a>; // A</line>
<line>        when '01' result = <a link="FPRounding_TIEEVEN" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEEVEN</a>; // N</line>
<line>        when '10' result = <a link="FPRounding_POSINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_POSINF</a>;  // P</line>
<line>        when '11' result = <a link="FPRounding_NEGINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_NEGINF</a>;  // M</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpdecoderounding/FPDecodeRounding" mylink="shared.functions.float.fpdecoderounding.FPDecodeRounding" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPDecodeRounding()</line>
<line>// ==================</line>
<line></line>
<line>// Decode floating-point rounding mode and common AArch64 encoding.</line>
<line></line>
<line link="impl-shared.FPDecodeRounding.1" hover="function: FPRounding FPDecodeRounding(bits(2) rmode)" conts="FPDecodeRounding">FPRounding <anchor link="impl-shared.FPDecodeRounding.1" hover="function: FPRounding FPDecodeRounding(bits(2) rmode)">FPDecodeRounding</anchor>(bits(2) rmode)</line>
<line>    case rmode of</line>
<line>        when '00' return <a link="FPRounding_TIEEVEN" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEEVEN</a>; // N</line>
<line>        when '01' return <a link="FPRounding_POSINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_POSINF</a>;  // P</line>
<line>        when '10' return <a link="FPRounding_NEGINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_NEGINF</a>;  // M</line>
<line>        when '11' return <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>;    // Z</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpdefaultnan/FPDefaultNaN" mylink="shared.functions.float.fpdefaultnan.FPDefaultNaN" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPDefaultNaN()</line>
<line>// ==============</line>
<line></line>
<line link="impl-shared.FPDefaultNaN.1" hover="function: bits(N) FPDefaultNaN(integer N)" conts="FPDefaultNaN">bits(N) <anchor link="impl-shared.FPDefaultNaN.1" hover="function: bits(N) FPDefaultNaN(integer N)">FPDefaultNaN</anchor>(integer N)</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = FPCR[];</line>
<line>    return <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, N);</line>
<line></line>
<line link="impl-shared.FPDefaultNaN.2" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)" conts="FPDefaultNaN">bits(N) <anchor link="impl-shared.FPDefaultNaN.2" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</anchor>(<a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, integer N)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    constant integer E = (if N == 16 then 5 elsif N == 32 then 8 else 11);</line>
<line>    constant integer F = N - (E + 1);</line>
<line>    bit sign = if <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then fpcr.AH else '0';</line>
<line></line>
<line>    bits(E) exp  = <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(E);</line>
<line>    bits(F) frac = '1':<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(F-1);</line>
<line></line>
<line>    return sign : exp : frac;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpdiv/FPDiv" mylink="shared.functions.float.fpdiv.FPDiv" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPDiv()</line>
<line>// =======</line>
<line></line>
<line link="impl-shared.FPDiv.3" hover="function: bits(N) FPDiv(bits(N) op1, bits(N) op2, FPCRType fpcr)" conts="FPDiv">bits(N) <anchor link="impl-shared.FPDiv.3" hover="function: bits(N) FPDiv(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPDiv</anchor>(bits(N) op1, bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op1, fpcr);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op2, fpcr);</line>
<line>    (done,result) = <a link="impl-shared.FPProcessNaNs.5" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs(FPType type1, FPType type2, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPProcessNaNs</a>(type1, type2, op1, op2, fpcr);</line>
<line></line>
<line>    if !done then</line>
<line>        inf1  = type1 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>;</line>
<line>        inf2  = type2 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>;</line>
<line>        zero1 = type1 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>;</line>
<line>        zero2 = type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>;</line>
<line></line>
<line>        if (inf1 &amp;&amp; inf2) || (zero1 &amp;&amp; zero2) then</line>
<line>            result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, N);</line>
<line>            <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>        elsif inf1 || zero2 then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>(sign1 EOR sign2, N);</line>
<line>            if !inf1 then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_DivideByZero" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_DivideByZero</a>, fpcr);</line>
<line>        elsif zero1 || inf2 then</line>
<line>            result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign1 EOR sign2, N);</line>
<line>        else</line>
<line>            result = <a link="impl-shared.FPRound.3" file="shared_pseudocode.xml" hover="function: bits(N) FPRound(real op, FPCRType fpcr, integer N)">FPRound</a>(value1/value2, fpcr, N);</line>
<line></line>
<line>        if !zero2 then</line>
<line>            <a link="impl-shared.FPProcessDenorms.4" file="shared_pseudocode.xml" hover="function: FPProcessDenorms(FPType type1, FPType type2, integer N, FPCRType fpcr)">FPProcessDenorms</a>(type1, type2, N, fpcr);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpdot/FPDot" mylink="shared.functions.float.fpdot.FPDot" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPDot()</line>
<line>// =======</line>
<line>// Calculates single-precision result of 2-way 16-bit floating-point dot-product</line>
<line>// with a single rounding.</line>
<line>// The 'fpcr' argument supplies the FPCR control bits and 'isbfloat16'</line>
<line>// determines whether input operands are BFloat16 or half-precision type.</line>
<line>// and 'fpexc' controls the generation of floating-point exceptions.</line>
<line></line>
<line link="impl-shared.FPDot.6" hover="function: bits(N) FPDot(bits(N DIV 2) op1_a, bits(N DIV 2) op1_b, bits(N DIV 2) op2_a, bits(N DIV 2) op2_b, FPCRType fpcr, boolean isbfloat16)" conts="FPDot">bits(N) <anchor link="impl-shared.FPDot.6" hover="function: bits(N) FPDot(bits(N DIV 2) op1_a, bits(N DIV 2) op1_b, bits(N DIV 2) op2_a, bits(N DIV 2) op2_b, FPCRType fpcr, boolean isbfloat16)">FPDot</anchor>(bits(N DIV 2) op1_a, bits(N DIV 2) op1_b, bits(N DIV 2) op2_a,</line>
<line>              bits(N DIV 2) op2_b, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, boolean isbfloat16)</line>
<line>    boolean fpexc = TRUE;       // Generate floating-point exceptions</line>
<line>    return <a link="impl-shared.FPDot.7" file="shared_pseudocode.xml" hover="function: bits(N) FPDot(bits(N DIV 2) op1_a, bits(N DIV 2) op1_b, bits(N DIV 2) op2_a, bits(N DIV 2) op2_b, FPCRType fpcr_in, boolean isbfloat16, boolean fpexc)">FPDot</a>(op1_a, op1_b, op2_a, op2_b, fpcr, isbfloat16, fpexc);</line>
<line></line>
<line link="impl-shared.FPDot.7" hover="function: bits(N) FPDot(bits(N DIV 2) op1_a, bits(N DIV 2) op1_b, bits(N DIV 2) op2_a, bits(N DIV 2) op2_b, FPCRType fpcr_in, boolean isbfloat16, boolean fpexc)" conts="FPDot">bits(N) <anchor link="impl-shared.FPDot.7" hover="function: bits(N) FPDot(bits(N DIV 2) op1_a, bits(N DIV 2) op1_b, bits(N DIV 2) op2_a, bits(N DIV 2) op2_b, FPCRType fpcr_in, boolean isbfloat16, boolean fpexc)">FPDot</anchor>(bits(N DIV 2) op1_a, bits(N DIV 2) op1_b, bits(N DIV 2) op2_a,</line>
<line>              bits(N DIV 2) op2_b, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in, boolean isbfloat16, boolean fpexc)</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line></line>
<line>    assert N == 32;</line>
<line>    bits(N) result;</line>
<line>    boolean done;</line>
<line>    fpcr.AHP = '0';           // Ignore alternative half-precision option</line>
<line>    rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(fpcr);</line>
<line></line>
<line>    (type1_a,sign1_a,value1_a) = <a link="impl-shared.FPUnpackBase.4" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpackBase(bits(N) fpval, FPCRType fpcr_in, boolean fpexc, boolean isbfloat16)">FPUnpackBase</a>(op1_a, fpcr, fpexc, isbfloat16);</line>
<line>    (type1_b,sign1_b,value1_b) = <a link="impl-shared.FPUnpackBase.4" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpackBase(bits(N) fpval, FPCRType fpcr_in, boolean fpexc, boolean isbfloat16)">FPUnpackBase</a>(op1_b, fpcr, fpexc, isbfloat16);</line>
<line>    (type2_a,sign2_a,value2_a) = <a link="impl-shared.FPUnpackBase.4" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpackBase(bits(N) fpval, FPCRType fpcr_in, boolean fpexc, boolean isbfloat16)">FPUnpackBase</a>(op2_a, fpcr, fpexc, isbfloat16);</line>
<line>    (type2_b,sign2_b,value2_b) = <a link="impl-shared.FPUnpackBase.4" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpackBase(bits(N) fpval, FPCRType fpcr_in, boolean fpexc, boolean isbfloat16)">FPUnpackBase</a>(op2_b, fpcr, fpexc, isbfloat16);</line>
<line></line>
<line>    inf1_a = (type1_a == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>); zero1_a = (type1_a == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line>    inf1_b = (type1_b == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>); zero1_b = (type1_b == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line>    inf2_a = (type2_a == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>); zero2_a = (type2_a == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line>    inf2_b = (type2_b == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>); zero2_b = (type2_b == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line></line>
<line>    (done,result) = <a link="impl-shared.FPProcessNaNs4.10" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs4(FPType type1, FPType type2, FPType type3, FPType type4, bits(N DIV 2) op1, bits(N DIV 2) op2, bits(N DIV 2) op3, bits(N DIV 2) op4, FPCRType fpcr, boolean fpexc)">FPProcessNaNs4</a>(type1_a, type1_b, type2_a, type2_b,</line>
<line>                                   op1_a, op1_b, op2_a, op2_b, fpcr, fpexc);</line>
<line></line>
<line>    if (((inf1_a &amp;&amp; zero2_a) || (zero1_a &amp;&amp; inf2_a)) &amp;&amp;</line>
<line>        ((inf1_b &amp;&amp; zero2_b) || (zero1_b &amp;&amp; inf2_b))) then</line>
<line>        result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, N);</line>
<line>        if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line></line>
<line>    if !done then</line>
<line>        // Determine sign and type products will have if it does not cause an Invalid</line>
<line>        // Operation.</line>
<line>        signPa = sign1_a EOR sign2_a;</line>
<line>        signPb = sign1_b EOR sign2_b;</line>
<line>        infPa = inf1_a || inf2_a;</line>
<line>        infPb = inf1_b || inf2_b;</line>
<line>        zeroPa = zero1_a || zero2_a;</line>
<line>        zeroPb = zero1_b || zero2_b;</line>
<line></line>
<line>        // Non SNaN-generated Invalid Operation cases are multiplies of zero</line>
<line>        // by infinity and additions of opposite-signed infinities.</line>
<line>        invalidop = ((inf1_a &amp;&amp; zero2_a) || (zero1_a &amp;&amp; inf2_a) ||</line>
<line>            (inf1_b &amp;&amp; zero2_b) || (zero1_b &amp;&amp; inf2_b) || (infPa &amp;&amp; infPb &amp;&amp; signPa != signPb));</line>
<line></line>
<line>        if invalidop then</line>
<line>            result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, N);</line>
<line>            if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line></line>
<line>       // Other cases involving infinities produce an infinity of the same sign.</line>
<line>        elsif (infPa &amp;&amp; signPa == '0') || (infPb &amp;&amp; signPb == '0') then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('0', N);</line>
<line>        elsif (infPa &amp;&amp; signPa == '1') || (infPb &amp;&amp; signPb == '1') then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('1', N);</line>
<line></line>
<line>        // Cases where the result is exactly zero and its sign is not determined by the</line>
<line>        // rounding mode are additions of same-signed zeros.</line>
<line>        elsif zeroPa &amp;&amp; zeroPb &amp;&amp; signPa == signPb then</line>
<line>            result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(signPa, N);</line>
<line></line>
<line>        // Otherwise calculate fused sum of products and round it.</line>
<line>        else</line>
<line>            result_value = (value1_a * value2_a) + (value1_b * value2_b);</line>
<line>            if result_value == 0.0 then  // Sign of exact zero result depends on rounding mode</line>
<line>                result_sign = if rounding == <a link="FPRounding_NEGINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_NEGINF</a> then '1' else '0';</line>
<line>                result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(result_sign, N);</line>
<line>            else</line>
<line>                result = <a link="impl-shared.FPRound.5" file="shared_pseudocode.xml" hover="function: bits(N) FPRound(real op, FPCRType fpcr_in, FPRounding rounding, boolean fpexc, integer N)">FPRound</a>(result_value, fpcr, rounding, fpexc, N);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpdot/FPDotAdd" mylink="shared.functions.float.fpdot.FPDotAdd" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPDotAdd()</line>
<line>// ==========</line>
<line>// Half-precision 2-way dot-product and add to single-precision.</line>
<line></line>
<line link="impl-shared.FPDotAdd.6" hover="function: bits(N) FPDotAdd(bits(N) addend, bits(N DIV 2) op1_a, bits(N DIV 2) op1_b, bits(N DIV 2) op2_a, bits(N DIV 2) op2_b, FPCRType fpcr)" conts="FPDotAdd">bits(N) <anchor link="impl-shared.FPDotAdd.6" hover="function: bits(N) FPDotAdd(bits(N) addend, bits(N DIV 2) op1_a, bits(N DIV 2) op1_b, bits(N DIV 2) op2_a, bits(N DIV 2) op2_b, FPCRType fpcr)">FPDotAdd</anchor>(bits(N) addend, bits(N DIV 2) op1_a, bits(N DIV 2) op1_b,</line>
<line>                 bits(N DIV 2) op2_a, bits(N DIV 2) op2_b, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    assert N == 32;</line>
<line></line>
<line>    bits(N) prod;</line>
<line>    boolean isbfloat16 = FALSE;</line>
<line>    boolean fpexc = TRUE;     // Generate floating-point exceptions</line>
<line>    prod = <a link="impl-shared.FPDot.7" file="shared_pseudocode.xml" hover="function: bits(N) FPDot(bits(N DIV 2) op1_a, bits(N DIV 2) op1_b, bits(N DIV 2) op2_a, bits(N DIV 2) op2_b, FPCRType fpcr_in, boolean isbfloat16, boolean fpexc)">FPDot</a>(op1_a, op1_b, op2_a, op2_b, fpcr, isbfloat16, fpexc);</line>
<line>    result = <a link="impl-shared.FPAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)">FPAdd</a>(addend, prod, fpcr, fpexc);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpdot/FPDotAdd_ZA" mylink="shared.functions.float.fpdot.FPDotAdd_ZA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPDotAdd_ZA()</line>
<line>// =============</line>
<line>// Half-precision 2-way dot-product and add to single-precision</line>
<line>// for SME ZA-targeting instructions.</line>
<line></line>
<line link="impl-shared.FPDotAdd_ZA.6" hover="function: bits(N) FPDotAdd_ZA(bits(N) addend, bits(N DIV 2) op1_a, bits(N DIV 2) op1_b, bits(N DIV 2) op2_a, bits(N DIV 2) op2_b, FPCRType fpcr_in)" conts="FPDotAdd_ZA">bits(N) <anchor link="impl-shared.FPDotAdd_ZA.6" hover="function: bits(N) FPDotAdd_ZA(bits(N) addend, bits(N DIV 2) op1_a, bits(N DIV 2) op1_b, bits(N DIV 2) op2_a, bits(N DIV 2) op2_b, FPCRType fpcr_in)">FPDotAdd_ZA</anchor>(bits(N) addend, bits(N DIV 2) op1_a, bits(N DIV 2) op1_b,</line>
<line>                    bits(N DIV 2) op2_a, bits(N DIV 2) op2_b, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in)</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    assert N == 32;</line>
<line></line>
<line>    bits(N) prod;</line>
<line>    boolean isbfloat16 = FALSE;</line>
<line>    boolean fpexc = FALSE;    // Do not generate floating-point exceptions</line>
<line>    fpcr.DN = '1';            // Generate default NaN values</line>
<line>    prod = <a link="impl-shared.FPDot.7" file="shared_pseudocode.xml" hover="function: bits(N) FPDot(bits(N DIV 2) op1_a, bits(N DIV 2) op1_b, bits(N DIV 2) op2_a, bits(N DIV 2) op2_b, FPCRType fpcr_in, boolean isbfloat16, boolean fpexc)">FPDot</a>(op1_a, op1_b, op2_a, op2_b, fpcr, isbfloat16, fpexc);</line>
<line>    result = <a link="impl-shared.FPAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)">FPAdd</a>(addend, prod, fpcr, fpexc);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpexc/FPExc" mylink="shared.functions.float.fpexc.FPExc" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPExc</line>
<line>// =====</line>
<line></line>
<line link="FPExc" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}" conts="FPExc">enumeration <anchor link="FPExc" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc</anchor>       {<anchor link="FPExc_InvalidOp" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</anchor>, <anchor link="FPExc_DivideByZero" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_DivideByZero</anchor>, <anchor link="FPExc_Overflow" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_Overflow</anchor>,</line>
<line link="FPExc_Underflow" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}" conts="FPExc_Underflow">                         <anchor link="FPExc_Underflow" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_Underflow</anchor>, <anchor link="FPExc_Inexact" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_Inexact</anchor>, <anchor link="FPExc_InputDenorm" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InputDenorm</anchor>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpinfinity/FPInfinity" mylink="shared.functions.float.fpinfinity.FPInfinity" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPInfinity()</line>
<line>// ============</line>
<line></line>
<line link="impl-shared.FPInfinity.2" hover="function: bits(N) FPInfinity(bit sign, integer N)" conts="FPInfinity">bits(N) <anchor link="impl-shared.FPInfinity.2" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</anchor>(bit sign, integer N)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    constant integer E = (if N == 16 then 5 elsif N == 32 then 8 else 11);</line>
<line>    constant integer F = N - (E + 1);</line>
<line>    bits(E) exp  = <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(E);</line>
<line>    bits(F) frac = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(F);</line>
<line></line>
<line>    return sign : exp : frac;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpmatmul/FPMatMulAdd" mylink="shared.functions.float.fpmatmul.FPMatMulAdd" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPMatMulAdd()</line>
<line>// =============</line>
<line>//</line>
<line>// Floating point matrix multiply and add to same precision matrix</line>
<line>// result[2, 2] = addend[2, 2] + (op1[2, 2] * op2[2, 2])</line>
<line></line>
<line link="impl-shared.FPMatMulAdd.5" hover="function: bits(N) FPMatMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, integer esize, FPCRType fpcr)" conts="FPMatMulAdd">bits(N) <anchor link="impl-shared.FPMatMulAdd.5" hover="function: bits(N) FPMatMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, integer esize, FPCRType fpcr)">FPMatMulAdd</anchor>(bits(N) addend, bits(N) op1, bits(N) op2, integer esize, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line></line>
<line>    assert N == esize * 2 * 2;</line>
<line>    bits(N)  result;</line>
<line>    bits(esize) prod0, prod1, sum;</line>
<line></line>
<line>    for i = 0 to 1</line>
<line>        for j = 0 to 1</line>
<line>            sum   = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[addend, 2*i + j, esize];</line>
<line>            prod0 = <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[op1, 2*i + 0, esize],</line>
<line>                          <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[op2, 2*j + 0, esize], fpcr);</line>
<line>            prod1 = <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[op1, 2*i + 1, esize],</line>
<line>                          <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[op2, 2*j + 1, esize], fpcr);</line>
<line>            sum   = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(sum, <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(prod0, prod1, fpcr), fpcr);</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*i + j, esize] = sum;</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpmax/FPMax" mylink="shared.functions.float.fpmax.FPMax" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPMax()</line>
<line>// =======</line>
<line></line>
<line link="impl-shared.FPMax.3" hover="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)" conts="FPMax">bits(N) <anchor link="impl-shared.FPMax.3" hover="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</anchor>(bits(N) op1, bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    boolean altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1';</line>
<line>    return <a link="impl-shared.FPMax.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr_in, boolean altfp)">FPMax</a>(op1, op2, fpcr, altfp);</line>
<line></line>
<line>// FPMax()</line>
<line>// =======</line>
<line>// Compare two inputs and return the larger value after rounding. The</line>
<line>// 'fpcr' argument supplies the FPCR control bits and 'altfp' determines</line>
<line>// if the function should use alternative floating-point behavior.</line>
<line></line>
<line link="impl-shared.FPMax.4" hover="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr_in, boolean altfp)" conts="FPMax">bits(N) <anchor link="impl-shared.FPMax.4" hover="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr_in, boolean altfp)">FPMax</anchor>(bits(N) op1, bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in, boolean altfp)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    boolean done;</line>
<line>    bits(N) result;</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op1, fpcr);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op2, fpcr);</line>
<line></line>
<line>    if altfp &amp;&amp; type1 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> &amp;&amp; type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> &amp;&amp; sign1 != sign2 then</line>
<line>        // Alternate handling of zeros with differing sign</line>
<line>        return <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign2, N);</line>
<line>    elsif altfp &amp;&amp; (type1 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>} || type2 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>}) then</line>
<line>        // Alternate handling of NaN inputs</line>
<line>        <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>        return (if type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> then <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign2, N) else op2);</line>
<line></line>
<line>    (done,result) = <a link="impl-shared.FPProcessNaNs.5" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs(FPType type1, FPType type2, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPProcessNaNs</a>(type1, type2, op1, op2, fpcr);</line>
<line>    if !done then</line>
<line>        <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> fptype;</line>
<line>        bit sign;</line>
<line>        real value;</line>
<line>        if value1 &gt; value2 then</line>
<line>            (fptype,sign,value) = (type1,sign1,value1);</line>
<line>        else</line>
<line>            (fptype,sign,value) = (type2,sign2,value2);</line>
<line>        if fptype == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a> then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>(sign, N);</line>
<line>        elsif fptype == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> then</line>
<line>            sign = sign1 AND sign2;         // Use most positive sign</line>
<line>            result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign, N);</line>
<line>        else</line>
<line>            // The use of FPRound() covers the case where there is a trapped underflow exception</line>
<line>            // for a denormalized number even though the result is exact.</line>
<line>            rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(fpcr);</line>
<line>            if altfp then    // Denormal output is not flushed to zero</line>
<line>                fpcr.FZ = '0';</line>
<line>                fpcr.FZ16 = '0';</line>
<line></line>
<line>            result = <a link="impl-shared.FPRound.5" file="shared_pseudocode.xml" hover="function: bits(N) FPRound(real op, FPCRType fpcr_in, FPRounding rounding, boolean fpexc, integer N)">FPRound</a>(value, fpcr, rounding, TRUE, N);</line>
<line></line>
<line>        <a link="impl-shared.FPProcessDenorms.4" file="shared_pseudocode.xml" hover="function: FPProcessDenorms(FPType type1, FPType type2, integer N, FPCRType fpcr)">FPProcessDenorms</a>(type1, type2, N, fpcr);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpmaxnormal/FPMaxNormal" mylink="shared.functions.float.fpmaxnormal.FPMaxNormal" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPMaxNormal()</line>
<line>// =============</line>
<line></line>
<line link="impl-shared.FPMaxNormal.2" hover="function: bits(N) FPMaxNormal(bit sign, integer N)" conts="FPMaxNormal">bits(N) <anchor link="impl-shared.FPMaxNormal.2" hover="function: bits(N) FPMaxNormal(bit sign, integer N)">FPMaxNormal</anchor>(bit sign, integer N)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    constant integer E = (if N == 16 then 5 elsif N == 32 then 8 else 11);</line>
<line>    constant integer F = N - (E + 1);</line>
<line>    exp  = <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(E-1):'0';</line>
<line>    frac = <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(F);</line>
<line></line>
<line>    return sign : exp : frac;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpmaxnum/FPMaxNum" mylink="shared.functions.float.fpmaxnum.FPMaxNum" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPMaxNum()</line>
<line>// ==========</line>
<line></line>
<line link="impl-shared.FPMaxNum.3" hover="function: bits(N) FPMaxNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)" conts="FPMaxNum">bits(N) <anchor link="impl-shared.FPMaxNum.3" hover="function: bits(N) FPMaxNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)">FPMaxNum</anchor>(bits(N) op1_in, bits(N) op2_in, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    bits(N) op1 = op1_in;</line>
<line>    bits(N) op2 = op2_in;</line>
<line>    (type1,-,-) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op1, fpcr);</line>
<line>    (type2,-,-) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op2, fpcr);</line>
<line></line>
<line>    boolean type1_nan = type1 IN {<a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>, <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>};</line>
<line>    boolean type2_nan = type2 IN {<a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>, <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>};</line>
<line>    boolean altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1';</line>
<line></line>
<line>    if !(altfp &amp;&amp; type1_nan &amp;&amp; type2_nan) then</line>
<line>        // Treat a single quiet-NaN as -Infinity.</line>
<line>        if type1 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> &amp;&amp; type2 != <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>            op1 = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('1', N);</line>
<line>        elsif type1 != <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> &amp;&amp; type2 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>            op2 = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('1', N);</line>
<line></line>
<line>    altfmaxfmin = FALSE;    // Restrict use of FMAX/FMIN NaN propagation rules</line>
<line>    result = <a link="impl-shared.FPMax.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr_in, boolean altfp)">FPMax</a>(op1, op2, fpcr, altfmaxfmin);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpmerge/IsMerging" mylink="shared.functions.float.fpmerge.IsMerging" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsMerging()</line>
<line>// ===========</line>
<line>// Returns TRUE if the output elements other than the lowest are taken from</line>
<line>// the destination register.</line>
<line></line>
<line link="impl-shared.IsMerging.1" hover="function: boolean IsMerging(FPCRType fpcr)" conts="IsMerging">boolean <anchor link="impl-shared.IsMerging.1" hover="function: boolean IsMerging(FPCRType fpcr)">IsMerging</anchor>(<a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    bit nep = if <a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() &amp;&amp; PSTATE.SM == '1' &amp;&amp; !<a link="impl-aarch64.IsFullA64Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsFullA64Enabled()">IsFullA64Enabled</a>() then '0' else fpcr.NEP;</line>
<line>    return <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; nep == '1';</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpmin/FPMin" mylink="shared.functions.float.fpmin.FPMin" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPMin()</line>
<line>// =======</line>
<line></line>
<line link="impl-shared.FPMin.3" hover="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)" conts="FPMin">bits(N) <anchor link="impl-shared.FPMin.3" hover="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMin</anchor>(bits(N) op1, bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    boolean altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1';</line>
<line>    return <a link="impl-shared.FPMin.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr_in, boolean altfp)">FPMin</a>(op1, op2, fpcr, altfp);</line>
<line></line>
<line>// FPMin()</line>
<line>// =======</line>
<line>// Compare two operands and return the smaller operand after rounding. The</line>
<line>// 'fpcr' argument supplies the FPCR control bits and 'altfp' determines</line>
<line>// if the function should use alternative behavior.</line>
<line></line>
<line link="impl-shared.FPMin.4" hover="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr_in, boolean altfp)" conts="FPMin">bits(N) <anchor link="impl-shared.FPMin.4" hover="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr_in, boolean altfp)">FPMin</anchor>(bits(N) op1, bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in, boolean altfp)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    boolean done;</line>
<line>    bits(N) result;</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op1, fpcr);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op2, fpcr);</line>
<line></line>
<line>    if altfp &amp;&amp; type1 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> &amp;&amp; type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> &amp;&amp; sign1 != sign2 then</line>
<line>        // Alternate handling of zeros with differing sign</line>
<line>        return <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign2, N);</line>
<line>    elsif altfp &amp;&amp; (type1 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>} || type2 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>}) then</line>
<line>        // Alternate handling of NaN inputs</line>
<line>        <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>        return (if type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> then <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign2, N) else op2);</line>
<line></line>
<line>    (done,result) = <a link="impl-shared.FPProcessNaNs.5" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs(FPType type1, FPType type2, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPProcessNaNs</a>(type1, type2, op1, op2, fpcr);</line>
<line>    if !done then</line>
<line>        <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> fptype;</line>
<line>        bit sign;</line>
<line>        real value;</line>
<line>        <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding;</line>
<line>        if value1 &lt; value2 then</line>
<line>            (fptype,sign,value) = (type1,sign1,value1);</line>
<line>        else</line>
<line>            (fptype,sign,value) = (type2,sign2,value2);</line>
<line>        if fptype == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a> then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>(sign, N);</line>
<line>        elsif fptype == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> then</line>
<line>            sign = sign1 OR sign2;              // Use most negative sign</line>
<line>            result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign, N);</line>
<line>        else</line>
<line>            // The use of FPRound() covers the case where there is a trapped underflow exception</line>
<line>            // for a denormalized number even though the result is exact.</line>
<line>            rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(fpcr);</line>
<line>            if altfp then    // Denormal output is not flushed to zero</line>
<line>                fpcr.FZ = '0';</line>
<line>                fpcr.FZ16 = '0';</line>
<line></line>
<line>            result = <a link="impl-shared.FPRound.5" file="shared_pseudocode.xml" hover="function: bits(N) FPRound(real op, FPCRType fpcr_in, FPRounding rounding, boolean fpexc, integer N)">FPRound</a>(value, fpcr, rounding, TRUE, N);</line>
<line></line>
<line>        <a link="impl-shared.FPProcessDenorms.4" file="shared_pseudocode.xml" hover="function: FPProcessDenorms(FPType type1, FPType type2, integer N, FPCRType fpcr)">FPProcessDenorms</a>(type1, type2, N, fpcr);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpminnum/FPMinNum" mylink="shared.functions.float.fpminnum.FPMinNum" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPMinNum()</line>
<line>// ==========</line>
<line></line>
<line link="impl-shared.FPMinNum.3" hover="function: bits(N) FPMinNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)" conts="FPMinNum">bits(N) <anchor link="impl-shared.FPMinNum.3" hover="function: bits(N) FPMinNum(bits(N) op1_in, bits(N) op2_in, FPCRType fpcr)">FPMinNum</anchor>(bits(N) op1_in, bits(N) op2_in, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    bits(N) op1 = op1_in;</line>
<line>    bits(N) op2 = op2_in;</line>
<line>    (type1,-,-) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op1, fpcr);</line>
<line>    (type2,-,-) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op2, fpcr);</line>
<line></line>
<line>    boolean type1_nan = type1 IN {<a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>, <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>};</line>
<line>    boolean type2_nan = type2 IN {<a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>, <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>};</line>
<line>    boolean altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1';</line>
<line></line>
<line>    if !(altfp &amp;&amp; type1_nan &amp;&amp; type2_nan) then</line>
<line>        // Treat a single quiet-NaN as +Infinity.</line>
<line>        if type1 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> &amp;&amp; type2 != <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>            op1 = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('0', N);</line>
<line>        elsif type1 != <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> &amp;&amp; type2 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>            op2 = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('0', N);</line>
<line></line>
<line>    altfmaxfmin = FALSE;    // Restrict use of FMAX/FMIN NaN propagation rules</line>
<line>    result = <a link="impl-shared.FPMin.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMin(bits(N) op1, bits(N) op2, FPCRType fpcr_in, boolean altfp)">FPMin</a>(op1, op2, fpcr, altfmaxfmin);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpmul/FPMul" mylink="shared.functions.float.fpmul.FPMul" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPMul()</line>
<line>// =======</line>
<line></line>
<line link="impl-shared.FPMul.3" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)" conts="FPMul">bits(N) <anchor link="impl-shared.FPMul.3" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</anchor>(bits(N) op1, bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op1, fpcr);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op2, fpcr);</line>
<line>    (done,result) = <a link="impl-shared.FPProcessNaNs.5" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs(FPType type1, FPType type2, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPProcessNaNs</a>(type1, type2, op1, op2, fpcr);</line>
<line>    if !done then</line>
<line>        inf1 = (type1 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        inf2 = (type2 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        zero1 = (type1 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line>        zero2 = (type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line></line>
<line>        if (inf1 &amp;&amp; zero2) || (zero1 &amp;&amp; inf2) then</line>
<line>            result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, N);</line>
<line>            <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>        elsif inf1 || inf2 then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>(sign1 EOR sign2, N);</line>
<line>        elsif zero1 || zero2 then</line>
<line>            result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign1 EOR sign2, N);</line>
<line>        else</line>
<line>            result = <a link="impl-shared.FPRound.3" file="shared_pseudocode.xml" hover="function: bits(N) FPRound(real op, FPCRType fpcr, integer N)">FPRound</a>(value1*value2, fpcr, N);</line>
<line></line>
<line>        <a link="impl-shared.FPProcessDenorms.4" file="shared_pseudocode.xml" hover="function: FPProcessDenorms(FPType type1, FPType type2, integer N, FPCRType fpcr)">FPProcessDenorms</a>(type1, type2, N, fpcr);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpmuladd/FPMulAdd" mylink="shared.functions.float.fpmuladd.FPMulAdd" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPMulAdd()</line>
<line>// ==========</line>
<line></line>
<line link="impl-shared.FPMulAdd.4" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)" conts="FPMulAdd">bits(N) <anchor link="impl-shared.FPMulAdd.4" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</anchor>(bits(N) addend, bits(N) op1, bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    boolean fpexc = TRUE;       // Generate floating-point exceptions</line>
<line>    return <a link="impl-shared.FPMulAdd.5" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)">FPMulAdd</a>(addend, op1, op2, fpcr, fpexc);</line>
<line></line>
<line>// FPMulAdd()</line>
<line>// ==========</line>
<line>//</line>
<line>// Calculates addend + op1*op2 with a single rounding. The 'fpcr' argument</line>
<line>// supplies the FPCR control bits, and 'fpexc' controls the generation of</line>
<line>// floating-point exceptions.</line>
<line></line>
<line link="impl-shared.FPMulAdd.5" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)" conts="FPMulAdd">bits(N) <anchor link="impl-shared.FPMulAdd.5" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)">FPMulAdd</anchor>(bits(N) addend, bits(N) op1, bits(N) op2,</line>
<line>                 <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, boolean fpexc)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line></line>
<line>    (typeA,signA,valueA) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(addend, fpcr, fpexc);</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op1, fpcr, fpexc);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op2, fpcr, fpexc);</line>
<line>    rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(fpcr);</line>
<line>    inf1 = (type1 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>); zero1 = (type1 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line>    inf2 = (type2 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>); zero2 = (type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line></line>
<line>    (done,result) = <a link="impl-shared.FPProcessNaNs3.8" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs3(FPType type1, FPType type2, FPType type3, bits(N) op1, bits(N) op2, bits(N) op3, FPCRType fpcr, boolean fpexc)">FPProcessNaNs3</a>(typeA, type1, type2, addend, op1, op2, fpcr, fpexc);</line>
<line></line>
<line>    if !(<a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1') then</line>
<line>        if typeA == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> &amp;&amp; ((inf1 &amp;&amp; zero2) || (zero1 &amp;&amp; inf2)) then</line>
<line>            result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, N);</line>
<line>            if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line></line>
<line>    if !done then</line>
<line>        infA = (typeA == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>); zeroA = (typeA == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line></line>
<line>        // Determine sign and type product will have if it does not cause an</line>
<line>        // Invalid Operation.</line>
<line>        signP = sign1 EOR sign2;</line>
<line>        infP  = inf1 || inf2;</line>
<line>        zeroP = zero1 || zero2;</line>
<line></line>
<line>        // Non SNaN-generated Invalid Operation cases are multiplies of zero</line>
<line>        // by infinity and additions of opposite-signed infinities.</line>
<line>        invalidop = (inf1 &amp;&amp; zero2) || (zero1 &amp;&amp; inf2) || (infA &amp;&amp; infP &amp;&amp; signA != signP);</line>
<line></line>
<line>        if invalidop then</line>
<line>            result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, N);</line>
<line>            if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>        // Other cases involving infinities produce an infinity of the same sign.</line>
<line>        elsif (infA &amp;&amp; signA == '0') || (infP &amp;&amp; signP == '0') then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('0', N);</line>
<line>        elsif (infA &amp;&amp; signA == '1') || (infP &amp;&amp; signP == '1') then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('1', N);</line>
<line></line>
<line>        // Cases where the result is exactly zero and its sign is not determined by the</line>
<line>        // rounding mode are additions of same-signed zeros.</line>
<line>        elsif zeroA &amp;&amp; zeroP &amp;&amp; signA == signP then</line>
<line>            result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(signA, N);</line>
<line></line>
<line>        // Otherwise calculate numerical result and round it.</line>
<line>        else</line>
<line>            result_value = valueA + (value1 * value2);</line>
<line>            if result_value == 0.0 then  // Sign of exact zero result depends on rounding mode</line>
<line>                result_sign = if rounding == <a link="FPRounding_NEGINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_NEGINF</a> then '1' else '0';</line>
<line>                result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(result_sign, N);</line>
<line>            else</line>
<line>                result = <a link="impl-shared.FPRound.5" file="shared_pseudocode.xml" hover="function: bits(N) FPRound(real op, FPCRType fpcr_in, FPRounding rounding, boolean fpexc, integer N)">FPRound</a>(result_value, fpcr, rounding, fpexc, N);</line>
<line></line>
<line>        if !invalidop &amp;&amp; fpexc then</line>
<line>            <a link="impl-shared.FPProcessDenorms3.5" file="shared_pseudocode.xml" hover="function: FPProcessDenorms3(FPType type1, FPType type2, FPType type3, integer N, FPCRType fpcr)">FPProcessDenorms3</a>(typeA, type1, type2, N, fpcr);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpmuladd/FPMulAdd_ZA" mylink="shared.functions.float.fpmuladd.FPMulAdd_ZA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPMulAdd_ZA()</line>
<line>// =============</line>
<line>// Calculates addend + op1*op2 with a single rounding for SME ZA-targeting</line>
<line>// instructions.</line>
<line></line>
<line link="impl-shared.FPMulAdd_ZA.4" hover="function: bits(N) FPMulAdd_ZA(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr_in)" conts="FPMulAdd_ZA">bits(N) <anchor link="impl-shared.FPMulAdd_ZA.4" hover="function: bits(N) FPMulAdd_ZA(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr_in)">FPMulAdd_ZA</anchor>(bits(N) addend, bits(N) op1, bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in)</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    boolean fpexc = FALSE;      // Do not generate floating-point exceptions</line>
<line>    fpcr.DN = '1';              // Generate default NaN values</line>
<line>    return <a link="impl-shared.FPMulAdd.5" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)">FPMulAdd</a>(addend, op1, op2, fpcr, fpexc);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpmuladdh/FPMulAddH" mylink="shared.functions.float.fpmuladdh.FPMulAddH" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPMulAddH()</line>
<line>// ===========</line>
<line>// Calculates addend + op1*op2.</line>
<line></line>
<line link="impl-shared.FPMulAddH.4" hover="function: bits(N) FPMulAddH(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, FPCRType fpcr)" conts="FPMulAddH">bits(N) <anchor link="impl-shared.FPMulAddH.4" hover="function: bits(N) FPMulAddH(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, FPCRType fpcr)">FPMulAddH</anchor>(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    boolean fpexc = TRUE;       // Generate floating-point exceptions</line>
<line>    return <a link="impl-shared.FPMulAddH.5" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAddH(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, FPCRType fpcr, boolean fpexc)">FPMulAddH</a>(addend, op1, op2, fpcr, fpexc);</line>
<line></line>
<line>// FPMulAddH()</line>
<line>// ===========</line>
<line>// Calculates addend + op1*op2.</line>
<line></line>
<line link="impl-shared.FPMulAddH.5" hover="function: bits(N) FPMulAddH(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, FPCRType fpcr, boolean fpexc)" conts="FPMulAddH">bits(N) <anchor link="impl-shared.FPMulAddH.5" hover="function: bits(N) FPMulAddH(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, FPCRType fpcr, boolean fpexc)">FPMulAddH</anchor>(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2,</line>
<line>                  <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, boolean fpexc)</line>
<line></line>
<line>    assert N == 32;</line>
<line>    rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(fpcr);</line>
<line>    (typeA,signA,valueA) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(addend, fpcr, fpexc);</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op1, fpcr, fpexc);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op2, fpcr, fpexc);</line>
<line>    inf1 = (type1 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>); zero1 = (type1 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line>    inf2 = (type2 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>); zero2 = (type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line></line>
<line>    (done,result) = <a link="impl-shared.FPProcessNaNs3H.8" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs3H(FPType type1, FPType type2, FPType type3, bits(N) op1, bits(N DIV 2) op2, bits(N DIV 2) op3, FPCRType fpcr, boolean fpexc)">FPProcessNaNs3H</a>(typeA, type1, type2, addend, op1, op2, fpcr, fpexc);</line>
<line></line>
<line>    if !(<a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1') then</line>
<line>        if typeA == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> &amp;&amp; ((inf1 &amp;&amp; zero2) || (zero1 &amp;&amp; inf2)) then</line>
<line>            result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, N);</line>
<line>            if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line></line>
<line>    if !done then</line>
<line>        infA = (typeA == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>); zeroA = (typeA == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line></line>
<line>        // Determine sign and type product will have if it does not cause an</line>
<line>        // Invalid Operation.</line>
<line>        signP = sign1 EOR sign2;</line>
<line>        infP = inf1 || inf2;</line>
<line>        zeroP = zero1 || zero2;</line>
<line></line>
<line>        // Non SNaN-generated Invalid Operation cases are multiplies of zero by infinity and</line>
<line>        // additions of opposite-signed infinities.</line>
<line>        invalidop = (inf1 &amp;&amp; zero2) || (zero1 &amp;&amp; inf2) || (infA &amp;&amp; infP &amp;&amp; signA != signP);</line>
<line></line>
<line>        if invalidop then</line>
<line>            result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, N);</line>
<line>            if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line></line>
<line>        // Other cases involving infinities produce an infinity of the same sign.</line>
<line>        elsif (infA &amp;&amp; signA == '0') || (infP &amp;&amp; signP == '0') then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('0', N);</line>
<line>        elsif (infA &amp;&amp; signA == '1') || (infP &amp;&amp; signP == '1') then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('1', N);</line>
<line></line>
<line>        // Cases where the result is exactly zero and its sign is not determined by the</line>
<line>        // rounding mode are additions of same-signed zeros.</line>
<line>        elsif zeroA &amp;&amp; zeroP &amp;&amp; signA == signP then</line>
<line>            result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(signA, N);</line>
<line></line>
<line>        // Otherwise calculate numerical result and round it.</line>
<line>        else</line>
<line>            result_value = valueA + (value1 * value2);</line>
<line>            if result_value == 0.0 then // Sign of exact zero result depends on rounding mode</line>
<line>                result_sign = if rounding == <a link="FPRounding_NEGINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_NEGINF</a> then '1' else '0';</line>
<line>                result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(result_sign, N);</line>
<line>            else</line>
<line>                result = <a link="impl-shared.FPRound.5" file="shared_pseudocode.xml" hover="function: bits(N) FPRound(real op, FPCRType fpcr_in, FPRounding rounding, boolean fpexc, integer N)">FPRound</a>(result_value, fpcr, rounding, fpexc, N);</line>
<line></line>
<line>        if !invalidop &amp;&amp; fpexc then</line>
<line>            <a link="impl-shared.FPProcessDenorm.3" file="shared_pseudocode.xml" hover="function: FPProcessDenorm(FPType fptype, integer N, FPCRType fpcr)">FPProcessDenorm</a>(typeA, N, fpcr);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpmuladdh/FPMulAddH_ZA" mylink="shared.functions.float.fpmuladdh.FPMulAddH_ZA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPMulAddH_ZA()</line>
<line>// ==============</line>
<line>// Calculates addend + op1*op2 for SME2 ZA-targeting instructions.</line>
<line></line>
<line link="impl-shared.FPMulAddH_ZA.4" hover="function: bits(N) FPMulAddH_ZA(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, FPCRType fpcr_in)" conts="FPMulAddH_ZA">bits(N) <anchor link="impl-shared.FPMulAddH_ZA.4" hover="function: bits(N) FPMulAddH_ZA(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, FPCRType fpcr_in)">FPMulAddH_ZA</anchor>(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in)</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    boolean fpexc = FALSE;      // Do not generate floating-point exceptions</line>
<line>    fpcr.DN = '1';              // Generate default NaN values</line>
<line>    return <a link="impl-shared.FPMulAddH.5" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAddH(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, FPCRType fpcr, boolean fpexc)">FPMulAddH</a>(addend, op1, op2, fpcr, fpexc);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpmuladdh/FPProcessNaNs3H" mylink="shared.functions.float.fpmuladdh.FPProcessNaNs3H" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPProcessNaNs3H()</line>
<line>// =================</line>
<line></line>
<line link="impl-shared.FPProcessNaNs3H.8" hover="function: (boolean, bits(N)) FPProcessNaNs3H(FPType type1, FPType type2, FPType type3, bits(N) op1, bits(N DIV 2) op2, bits(N DIV 2) op3, FPCRType fpcr, boolean fpexc)" conts="FPProcessNaNs3H">(boolean, bits(N)) <anchor link="impl-shared.FPProcessNaNs3H.8" hover="function: (boolean, bits(N)) FPProcessNaNs3H(FPType type1, FPType type2, FPType type3, bits(N) op1, bits(N DIV 2) op2, bits(N DIV 2) op3, FPCRType fpcr, boolean fpexc)">FPProcessNaNs3H</anchor>(<a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type1, <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type2, <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type3,</line>
<line>                                   bits(N) op1, bits(N DIV 2) op2, bits(N DIV 2) op3,</line>
<line>                                   <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, boolean fpexc)</line>
<line></line>
<line>    assert N IN {32,64};</line>
<line></line>
<line>    bits(N) result;</line>
<line>    <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type_nan;</line>
<line>    // When TRUE, use alternative NaN propagation rules.</line>
<line>    boolean altfp   = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1';</line>
<line>    boolean op1_nan = type1 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>};</line>
<line>    boolean op2_nan = type2 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>};</line>
<line>    boolean op3_nan = type3 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>};</line>
<line>    if altfp then</line>
<line>        if (type1 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> || type2 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> || type3 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>) then</line>
<line>            type_nan = <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>;</line>
<line>        else</line>
<line>            type_nan = <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>;</line>
<line></line>
<line>    boolean done;</line>
<line>    if altfp &amp;&amp; op1_nan &amp;&amp; op2_nan &amp;&amp; op3_nan then          // &lt;n&gt; register NaN selected</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPConvertNaN.2" file="shared_pseudocode.xml" hover="function: bits(M) FPConvertNaN(bits(N) op, integer M)">FPConvertNaN</a>(<a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type_nan, op2, fpcr, fpexc), N);</line>
<line>    elsif altfp &amp;&amp; op2_nan &amp;&amp; (op1_nan || op3_nan) then     // &lt;n&gt; register NaN selected</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPConvertNaN.2" file="shared_pseudocode.xml" hover="function: bits(M) FPConvertNaN(bits(N) op, integer M)">FPConvertNaN</a>(<a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type_nan, op2, fpcr, fpexc), N);</line>
<line>    elsif altfp &amp;&amp; op3_nan &amp;&amp; op1_nan then                  // &lt;m&gt; register NaN selected</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPConvertNaN.2" file="shared_pseudocode.xml" hover="function: bits(M) FPConvertNaN(bits(N) op, integer M)">FPConvertNaN</a>(<a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type_nan, op3, fpcr, fpexc), N);</line>
<line>    elsif type1 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> then</line>
<line>        done = TRUE; result = <a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type1, op1, fpcr, fpexc);</line>
<line>    elsif type2 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> then</line>
<line>        done = TRUE; result = <a link="impl-shared.FPConvertNaN.2" file="shared_pseudocode.xml" hover="function: bits(M) FPConvertNaN(bits(N) op, integer M)">FPConvertNaN</a>(<a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type2, op2, fpcr, fpexc), N);</line>
<line>    elsif type3 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> then</line>
<line>        done = TRUE; result = <a link="impl-shared.FPConvertNaN.2" file="shared_pseudocode.xml" hover="function: bits(M) FPConvertNaN(bits(N) op, integer M)">FPConvertNaN</a>(<a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type3, op3, fpcr, fpexc), N);</line>
<line>    elsif type1 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        done = TRUE; result = <a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type1, op1, fpcr, fpexc);</line>
<line>    elsif type2 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        done = TRUE; result = <a link="impl-shared.FPConvertNaN.2" file="shared_pseudocode.xml" hover="function: bits(M) FPConvertNaN(bits(N) op, integer M)">FPConvertNaN</a>(<a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type2, op2, fpcr, fpexc), N);</line>
<line>    elsif type3 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        done = TRUE; result = <a link="impl-shared.FPConvertNaN.2" file="shared_pseudocode.xml" hover="function: bits(M) FPConvertNaN(bits(N) op, integer M)">FPConvertNaN</a>(<a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type3, op3, fpcr, fpexc), N);</line>
<line>    else</line>
<line>        done = FALSE; result = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(N); // 'Don't care' result</line>
<line>    return (done, result);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpmulx/FPMulX" mylink="shared.functions.float.fpmulx.FPMulX" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPMulX()</line>
<line>// ========</line>
<line></line>
<line link="impl-shared.FPMulX.3" hover="function: bits(N) FPMulX(bits(N) op1, bits(N) op2, FPCRType fpcr)" conts="FPMulX">bits(N) <anchor link="impl-shared.FPMulX.3" hover="function: bits(N) FPMulX(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulX</anchor>(bits(N) op1, bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    bits(N) result;</line>
<line>    boolean done;</line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op1, fpcr);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op2, fpcr);</line>
<line></line>
<line>    (done,result) = <a link="impl-shared.FPProcessNaNs.5" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs(FPType type1, FPType type2, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPProcessNaNs</a>(type1, type2, op1, op2, fpcr);</line>
<line>    if !done then</line>
<line>        inf1 = (type1 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        inf2 = (type2 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        zero1 = (type1 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line>        zero2 = (type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line></line>
<line>        if (inf1 &amp;&amp; zero2) || (zero1 &amp;&amp; inf2) then</line>
<line>            result = <a link="impl-shared.FPTwo.2" file="shared_pseudocode.xml" hover="function: bits(N) FPTwo(bit sign, integer N)">FPTwo</a>(sign1 EOR sign2, N);</line>
<line>        elsif inf1 || inf2 then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>(sign1 EOR sign2, N);</line>
<line>        elsif zero1 || zero2 then</line>
<line>            result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign1 EOR sign2, N);</line>
<line>        else</line>
<line>            result = <a link="impl-shared.FPRound.3" file="shared_pseudocode.xml" hover="function: bits(N) FPRound(real op, FPCRType fpcr, integer N)">FPRound</a>(value1*value2, fpcr, N);</line>
<line></line>
<line>        <a link="impl-shared.FPProcessDenorms.4" file="shared_pseudocode.xml" hover="function: FPProcessDenorms(FPType type1, FPType type2, integer N, FPCRType fpcr)">FPProcessDenorms</a>(type1, type2, N, fpcr);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpneg/FPNeg" mylink="shared.functions.float.fpneg.FPNeg" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPNeg()</line>
<line>// =======</line>
<line></line>
<line link="impl-shared.FPNeg.1" hover="function: bits(N) FPNeg(bits(N) op)" conts="FPNeg">bits(N) <anchor link="impl-shared.FPNeg.1" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</anchor>(bits(N) op)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    if !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() then</line>
<line>        <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = FPCR[];</line>
<line>        if fpcr.AH == '1' then</line>
<line>            (fptype, -, -) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op, fpcr, FALSE);</line>
<line>            if fptype IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>} then</line>
<line></line>
<line>                return op;        // When fpcr.AH=1, sign of NaN has no consequence</line>
<line></line>
<line>    return NOT(op&lt;N-1&gt;) : op&lt;N-2:0&gt;;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fponepointfive/FPOnePointFive" mylink="shared.functions.float.fponepointfive.FPOnePointFive" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPOnePointFive()</line>
<line>// ================</line>
<line></line>
<line link="impl-shared.FPOnePointFive.2" hover="function: bits(N) FPOnePointFive(bit sign, integer N)" conts="FPOnePointFive">bits(N) <anchor link="impl-shared.FPOnePointFive.2" hover="function: bits(N) FPOnePointFive(bit sign, integer N)">FPOnePointFive</anchor>(bit sign, integer N)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    constant integer E = (if N == 16 then 5 elsif N == 32 then 8 else 11);</line>
<line>    constant integer F = N - (E + 1);</line>
<line>    exp  = '0':<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(E-1);</line>
<line>    frac = '1':<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(F-1);</line>
<line>    result = sign : exp : frac;</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpprocessdenorms/FPProcessDenorm" mylink="shared.functions.float.fpprocessdenorms.FPProcessDenorm" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPProcessDenorm()</line>
<line>// =================</line>
<line>// Handles denormal input in case of single-precision or double-precision</line>
<line>// when using alternative floating-point mode.</line>
<line></line>
<line link="impl-shared.FPProcessDenorm.3" hover="function: FPProcessDenorm(FPType fptype, integer N, FPCRType fpcr)" conts="FPProcessDenorm"><anchor link="impl-shared.FPProcessDenorm.3" hover="function: FPProcessDenorm(FPType fptype, integer N, FPCRType fpcr)">FPProcessDenorm</anchor>(<a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> fptype, integer N, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    boolean altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1';</line>
<line>    if altfp &amp;&amp; N != 16 &amp;&amp; fptype == <a link="FPType_Denormal" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Denormal</a> then</line>
<line>        <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InputDenorm" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InputDenorm</a>, fpcr);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpprocessdenorms/FPProcessDenorms" mylink="shared.functions.float.fpprocessdenorms.FPProcessDenorms" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPProcessDenorms()</line>
<line>// ==================</line>
<line>// Handles denormal input in case of single-precision or double-precision</line>
<line>// when using alternative floating-point mode.</line>
<line></line>
<line link="impl-shared.FPProcessDenorms.4" hover="function: FPProcessDenorms(FPType type1, FPType type2, integer N, FPCRType fpcr)" conts="FPProcessDenorms"><anchor link="impl-shared.FPProcessDenorms.4" hover="function: FPProcessDenorms(FPType type1, FPType type2, integer N, FPCRType fpcr)">FPProcessDenorms</anchor>(<a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type1, <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type2, integer N, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    boolean altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1';</line>
<line>    if altfp &amp;&amp; N != 16 &amp;&amp; (type1 == <a link="FPType_Denormal" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Denormal</a> || type2 == <a link="FPType_Denormal" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Denormal</a>) then</line>
<line>        <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InputDenorm" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InputDenorm</a>, fpcr);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpprocessdenorms/FPProcessDenorms3" mylink="shared.functions.float.fpprocessdenorms.FPProcessDenorms3" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPProcessDenorms3()</line>
<line>// ===================</line>
<line>// Handles denormal input in case of single-precision or double-precision</line>
<line>// when using alternative floating-point mode.</line>
<line></line>
<line link="impl-shared.FPProcessDenorms3.5" hover="function: FPProcessDenorms3(FPType type1, FPType type2, FPType type3, integer N, FPCRType fpcr)" conts="FPProcessDenorms3"><anchor link="impl-shared.FPProcessDenorms3.5" hover="function: FPProcessDenorms3(FPType type1, FPType type2, FPType type3, integer N, FPCRType fpcr)">FPProcessDenorms3</anchor>(<a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type1, <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type2, <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type3, integer N, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    boolean altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1';</line>
<line>    if altfp &amp;&amp; N != 16 &amp;&amp; (type1 == <a link="FPType_Denormal" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Denormal</a> || type2 == <a link="FPType_Denormal" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Denormal</a> ||</line>
<line>        type3 == <a link="FPType_Denormal" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Denormal</a>) then</line>
<line>        <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InputDenorm" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InputDenorm</a>, fpcr);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpprocessdenorms/FPProcessDenorms4" mylink="shared.functions.float.fpprocessdenorms.FPProcessDenorms4" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPProcessDenorms4()</line>
<line>// ===================</line>
<line>// Handles denormal input in case of single-precision or double-precision</line>
<line>// when using alternative floating-point mode.</line>
<line></line>
<line link="impl-shared.FPProcessDenorms4.6" hover="function: FPProcessDenorms4(FPType type1, FPType type2, FPType type3, FPType type4, integer N, FPCRType fpcr)" conts="FPProcessDenorms4"><anchor link="impl-shared.FPProcessDenorms4.6" hover="function: FPProcessDenorms4(FPType type1, FPType type2, FPType type3, FPType type4, integer N, FPCRType fpcr)">FPProcessDenorms4</anchor>(<a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type1, <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type2, <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type3, <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type4, integer N, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    boolean altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1';</line>
<line>    if altfp &amp;&amp; N != 16 &amp;&amp; (type1 == <a link="FPType_Denormal" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Denormal</a> || type2 == <a link="FPType_Denormal" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Denormal</a> ||</line>
<line>        type3 == <a link="FPType_Denormal" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Denormal</a> || type4 == <a link="FPType_Denormal" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Denormal</a>) then</line>
<line>        <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InputDenorm" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InputDenorm</a>, fpcr);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpprocessexception/FPProcessException" mylink="shared.functions.float.fpprocessexception.FPProcessException" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPProcessException()</line>
<line>// ====================</line>
<line>//</line>
<line>// The 'fpcr' argument supplies FPCR control bits. Status information is</line>
<line>// updated directly in the FPSR where appropriate.</line>
<line></line>
<line link="impl-shared.FPProcessException.2" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)" conts="FPProcessException"><anchor link="impl-shared.FPProcessException.2" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</anchor>(<a link="FPExc" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc</a> exception, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line></line>
<line>    integer cumul;</line>
<line>    // Determine the cumulative exception bit number</line>
<line>    case exception of</line>
<line>        when <a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>     cumul = 0;</line>
<line>        when <a link="FPExc_DivideByZero" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_DivideByZero</a>  cumul = 1;</line>
<line>        when <a link="FPExc_Overflow" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_Overflow</a>      cumul = 2;</line>
<line>        when <a link="FPExc_Underflow" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_Underflow</a>     cumul = 3;</line>
<line>        when <a link="FPExc_Inexact" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_Inexact</a>       cumul = 4;</line>
<line>        when <a link="FPExc_InputDenorm" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InputDenorm</a>   cumul = 7;</line>
<line>    enable = cumul + 8;</line>
<line>    if fpcr&lt;enable&gt; == '1' &amp;&amp; (!<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() || PSTATE.SM == '0' || <a link="impl-aarch64.IsFullA64Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsFullA64Enabled()">IsFullA64Enabled</a>()) then</line>
<line>        // Trapping of the exception enabled.</line>
<line>        // It is IMPLEMENTATION DEFINED whether the enable bit may be set at all,</line>
<line>        // and if so then how exceptions and in what order that they may be</line>
<line>        // accumulated before calling FPTrappedException().</line>
<line>        bits(8) accumulated_exceptions = <a link="impl-shared.GetAccumulatedFPExceptions.0" file="shared_pseudocode.xml" hover="function: bits(8) GetAccumulatedFPExceptions()">GetAccumulatedFPExceptions</a>();</line>
<line>        accumulated_exceptions&lt;cumul&gt; = '1';</line>
<line>        if boolean IMPLEMENTATION_DEFINED "Support trapping of floating-point exceptions" then</line>
<line>            if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>                <a link="AArch32.FPTrappedException.1" file="shared_pseudocode.xml" hover="function: AArch32.FPTrappedException(bits(8) accumulated_exceptions)">AArch32.FPTrappedException</a>(accumulated_exceptions);</line>
<line>            else</line>
<line>                is_ase = <a link="impl-shared.IsASEInstruction.0" file="shared_pseudocode.xml" hover="function: boolean IsASEInstruction()">IsASEInstruction</a>();</line>
<line>                <a link="AArch64.FPTrappedException.2" file="shared_pseudocode.xml" hover="function: AArch64.FPTrappedException(boolean is_ase, bits(8) accumulated_exceptions)">AArch64.FPTrappedException</a>(is_ase, accumulated_exceptions);</line>
<line>        else</line>
<line>            // The exceptions generated by this instruction are accumulated by the PE and</line>
<line>            // FPTrappedException is called later during its execution, before the next</line>
<line>            // instruction is executed. This field is cleared at the start of each FP instruction.</line>
<line>            <a link="impl-shared.SetAccumulatedFPExceptions.1" file="shared_pseudocode.xml" hover="function: SetAccumulatedFPExceptions(bits(8) accumulated_exceptions)">SetAccumulatedFPExceptions</a>(accumulated_exceptions);</line>
<line>    elsif <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        // Set the cumulative exception bit</line>
<line>        FPSCR&lt;cumul&gt; = '1';</line>
<line>    else</line>
<line>        // Set the cumulative exception bit</line>
<line>        FPSR&lt;cumul&gt; = '1';</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpprocessnan/FPProcessNaN" mylink="shared.functions.float.fpprocessnan.FPProcessNaN" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPProcessNaN()</line>
<line>// ==============</line>
<line></line>
<line link="impl-shared.FPProcessNaN.3" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr)" conts="FPProcessNaN">bits(N) <anchor link="impl-shared.FPProcessNaN.3" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr)">FPProcessNaN</anchor>(<a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> fptype, bits(N) op, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    boolean fpexc = TRUE;   // Generate floating-point exceptions</line>
<line>    return <a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(fptype, op, fpcr, fpexc);</line>
<line></line>
<line>// FPProcessNaN()</line>
<line>// ==============</line>
<line>// Handle NaN input operands, returning the operand or default NaN value</line>
<line>// if fpcr.DN is selected. The 'fpcr' argument supplies the FPCR control bits.</line>
<line>// The 'fpexc' argument controls the generation of exceptions, regardless of</line>
<line>// whether 'fptype' is a signalling NaN or a quiet NaN.</line>
<line></line>
<line link="impl-shared.FPProcessNaN.4" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)" conts="FPProcessNaN">bits(N) <anchor link="impl-shared.FPProcessNaN.4" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</anchor>(<a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> fptype, bits(N) op, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, boolean fpexc)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    assert fptype IN {<a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>, <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>};</line>
<line>    integer topfrac;</line>
<line></line>
<line>    case N of</line>
<line>        when 16 topfrac =  9;</line>
<line>        when 32 topfrac = 22;</line>
<line>        when 64 topfrac = 51;</line>
<line></line>
<line>    result = op;</line>
<line>    if fptype == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> then</line>
<line>        result&lt;topfrac&gt; = '1';</line>
<line>        if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>    if fpcr.DN == '1' then  // DefaultNaN requested</line>
<line>        result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, N);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpprocessnans/FPProcessNaNs" mylink="shared.functions.float.fpprocessnans.FPProcessNaNs" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPProcessNaNs()</line>
<line>// ===============</line>
<line></line>
<line link="impl-shared.FPProcessNaNs.5" hover="function: (boolean, bits(N)) FPProcessNaNs(FPType type1, FPType type2, bits(N) op1, bits(N) op2, FPCRType fpcr)" conts="FPProcessNaNs">(boolean, bits(N)) <anchor link="impl-shared.FPProcessNaNs.5" hover="function: (boolean, bits(N)) FPProcessNaNs(FPType type1, FPType type2, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPProcessNaNs</anchor>(<a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type1, <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type2, bits(N) op1,</line>
<line>                                 bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    boolean fpexc       = TRUE;     // Generate floating-point exceptions</line>
<line>    return <a link="impl-shared.FPProcessNaNs.6" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs(FPType type1, FPType type2, bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)">FPProcessNaNs</a>(type1, type2, op1, op2, fpcr, fpexc);</line>
<line></line>
<line>// FPProcessNaNs()</line>
<line>// ===============</line>
<line>//</line>
<line>// The boolean part of the return value says whether a NaN has been found and</line>
<line>// processed. The bits(N) part is only relevant if it has and supplies the</line>
<line>// result of the operation.</line>
<line>//</line>
<line>// The 'fpcr' argument supplies FPCR control bits and 'altfmaxfmin' controls</line>
<line>// alternative floating-point behavior for FMAX, FMIN and variants. 'fpexc'</line>
<line>// controls the generation of floating-point exceptions. Status information</line>
<line>// is updated directly in the FPSR where appropriate.</line>
<line></line>
<line link="impl-shared.FPProcessNaNs.6" hover="function: (boolean, bits(N)) FPProcessNaNs(FPType type1, FPType type2, bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)" conts="FPProcessNaNs">(boolean, bits(N)) <anchor link="impl-shared.FPProcessNaNs.6" hover="function: (boolean, bits(N)) FPProcessNaNs(FPType type1, FPType type2, bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)">FPProcessNaNs</anchor>(<a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type1, <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type2, bits(N) op1, bits(N) op2,</line>
<line>                                 <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, boolean fpexc)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    boolean done;</line>
<line>    bits(N) result;</line>
<line>    boolean altfp    = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1';</line>
<line>    boolean op1_nan  = type1 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>};</line>
<line>    boolean op2_nan  = type2 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>};</line>
<line>    boolean any_snan = type1 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> || type2 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>;</line>
<line>    <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a>  type_nan = if any_snan then <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> else <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>;</line>
<line></line>
<line>    if altfp &amp;&amp; op1_nan &amp;&amp; op2_nan then</line>
<line>        // &lt;n&gt; register NaN selected</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type_nan, op1, fpcr, fpexc);</line>
<line>    elsif type1 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> then</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type1, op1, fpcr, fpexc);</line>
<line>    elsif type2 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> then</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type2, op2, fpcr, fpexc);</line>
<line>    elsif type1 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type1, op1, fpcr, fpexc);</line>
<line>    elsif type2 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type2, op2, fpcr, fpexc);</line>
<line>    else</line>
<line>        done = FALSE;  result = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(N);  // 'Don't care' result</line>
<line></line>
<line>    return (done, result);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpprocessnans3/FPProcessNaNs3" mylink="shared.functions.float.fpprocessnans3.FPProcessNaNs3" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPProcessNaNs3()</line>
<line>// ================</line>
<line></line>
<line link="impl-shared.FPProcessNaNs3.7" hover="function: (boolean, bits(N)) FPProcessNaNs3(FPType type1, FPType type2, FPType type3, bits(N) op1, bits(N) op2, bits(N) op3, FPCRType fpcr)" conts="FPProcessNaNs3">(boolean, bits(N)) <anchor link="impl-shared.FPProcessNaNs3.7" hover="function: (boolean, bits(N)) FPProcessNaNs3(FPType type1, FPType type2, FPType type3, bits(N) op1, bits(N) op2, bits(N) op3, FPCRType fpcr)">FPProcessNaNs3</anchor>(<a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type1, <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type2, <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type3,</line>
<line>                                  bits(N) op1, bits(N) op2, bits(N) op3,</line>
<line>                                  <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    boolean fpexc = TRUE;   // Generate floating-point exceptions</line>
<line>    return <a link="impl-shared.FPProcessNaNs3.8" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs3(FPType type1, FPType type2, FPType type3, bits(N) op1, bits(N) op2, bits(N) op3, FPCRType fpcr, boolean fpexc)">FPProcessNaNs3</a>(type1, type2, type3, op1, op2, op3, fpcr, fpexc);</line>
<line></line>
<line>// FPProcessNaNs3()</line>
<line>// ================</line>
<line>// The boolean part of the return value says whether a NaN has been found and</line>
<line>// processed. The bits(N) part is only relevant if it has and supplies the</line>
<line>// result of the operation.</line>
<line>//</line>
<line>// The 'fpcr' argument supplies FPCR control bits and 'fpexc' controls the</line>
<line>// generation of floating-point exceptions. Status information is updated</line>
<line>// directly in the FPSR where appropriate.</line>
<line></line>
<line link="impl-shared.FPProcessNaNs3.8" hover="function: (boolean, bits(N)) FPProcessNaNs3(FPType type1, FPType type2, FPType type3, bits(N) op1, bits(N) op2, bits(N) op3, FPCRType fpcr, boolean fpexc)" conts="FPProcessNaNs3">(boolean, bits(N)) <anchor link="impl-shared.FPProcessNaNs3.8" hover="function: (boolean, bits(N)) FPProcessNaNs3(FPType type1, FPType type2, FPType type3, bits(N) op1, bits(N) op2, bits(N) op3, FPCRType fpcr, boolean fpexc)">FPProcessNaNs3</anchor>(<a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type1, <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type2, <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type3,</line>
<line>                                  bits(N) op1, bits(N) op2, bits(N) op3,</line>
<line>                                  <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, boolean fpexc)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    bits(N) result;</line>
<line>    boolean op1_nan = type1 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>};</line>
<line>    boolean op2_nan = type2 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>};</line>
<line>    boolean op3_nan = type3 IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>};</line>
<line></line>
<line>    boolean altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1';</line>
<line>    <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type_nan;</line>
<line>    if altfp then</line>
<line>        if type1 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> || type2 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> || type3 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> then</line>
<line>            type_nan = <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>;</line>
<line>        else</line>
<line>            type_nan = <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>;</line>
<line></line>
<line>    boolean done;</line>
<line>    if altfp &amp;&amp; op1_nan &amp;&amp; op2_nan &amp;&amp; op3_nan then</line>
<line>        // &lt;n&gt; register NaN selected</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type_nan, op2, fpcr, fpexc);</line>
<line>    elsif altfp &amp;&amp; op2_nan &amp;&amp; (op1_nan || op3_nan) then</line>
<line>        // &lt;n&gt; register NaN selected</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type_nan, op2, fpcr, fpexc);</line>
<line>    elsif altfp &amp;&amp; op3_nan &amp;&amp; op1_nan then</line>
<line>        // &lt;m&gt; register NaN selected</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type_nan, op3, fpcr, fpexc);</line>
<line>    elsif type1 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> then</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type1, op1, fpcr, fpexc);</line>
<line>    elsif type2 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> then</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type2, op2, fpcr, fpexc);</line>
<line>    elsif type3 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> then</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type3, op3, fpcr, fpexc);</line>
<line>    elsif type1 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type1, op1, fpcr, fpexc);</line>
<line>    elsif type2 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type2, op2, fpcr, fpexc);</line>
<line>    elsif type3 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type3, op3, fpcr, fpexc);</line>
<line>    else</line>
<line>        done = FALSE;  result = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(N);  // 'Don't care' result</line>
<line></line>
<line>    return (done, result);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpprocessnans4/FPProcessNaNs4" mylink="shared.functions.float.fpprocessnans4.FPProcessNaNs4" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPProcessNaNs4()</line>
<line>// ================</line>
<line>// The boolean part of the return value says whether a NaN has been found and</line>
<line>// processed. The bits(N) part is only relevant if it has and supplies the</line>
<line>// result of the operation.</line>
<line>//</line>
<line>// The 'fpcr' argument supplies FPCR control bits.</line>
<line>// Status information is updated directly in the FPSR where appropriate.</line>
<line>// The 'fpexc' controls the generation of floating-point exceptions.</line>
<line></line>
<line link="impl-shared.FPProcessNaNs4.10" hover="function: (boolean, bits(N)) FPProcessNaNs4(FPType type1, FPType type2, FPType type3, FPType type4, bits(N DIV 2) op1, bits(N DIV 2) op2, bits(N DIV 2) op3, bits(N DIV 2) op4, FPCRType fpcr, boolean fpexc)" conts="FPProcessNaNs4">(boolean, bits(N)) <anchor link="impl-shared.FPProcessNaNs4.10" hover="function: (boolean, bits(N)) FPProcessNaNs4(FPType type1, FPType type2, FPType type3, FPType type4, bits(N DIV 2) op1, bits(N DIV 2) op2, bits(N DIV 2) op3, bits(N DIV 2) op4, FPCRType fpcr, boolean fpexc)">FPProcessNaNs4</anchor>(<a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type1, <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type2, <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type3, <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> type4,</line>
<line>                                  bits(N DIV 2) op1, bits(N DIV 2) op2, bits(N DIV 2) op3,</line>
<line>                                  bits(N DIV 2) op4, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, boolean fpexc)</line>
<line></line>
<line>    assert N == 32;</line>
<line></line>
<line>    bits(N) result;</line>
<line>    boolean done;</line>
<line>    // The FPCR.AH control does not affect these checks</line>
<line>    if type1 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> then</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPConvertNaN.2" file="shared_pseudocode.xml" hover="function: bits(M) FPConvertNaN(bits(N) op, integer M)">FPConvertNaN</a>(<a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type1, op1, fpcr, fpexc), N);</line>
<line>    elsif type2 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> then</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPConvertNaN.2" file="shared_pseudocode.xml" hover="function: bits(M) FPConvertNaN(bits(N) op, integer M)">FPConvertNaN</a>(<a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type2, op2, fpcr, fpexc), N);</line>
<line>    elsif type3 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> then</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPConvertNaN.2" file="shared_pseudocode.xml" hover="function: bits(M) FPConvertNaN(bits(N) op, integer M)">FPConvertNaN</a>(<a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type3, op3, fpcr, fpexc), N);</line>
<line>    elsif type4 == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> then</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPConvertNaN.2" file="shared_pseudocode.xml" hover="function: bits(M) FPConvertNaN(bits(N) op, integer M)">FPConvertNaN</a>(<a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type4, op4, fpcr, fpexc), N);</line>
<line>    elsif type1 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPConvertNaN.2" file="shared_pseudocode.xml" hover="function: bits(M) FPConvertNaN(bits(N) op, integer M)">FPConvertNaN</a>(<a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type1, op1, fpcr, fpexc), N);</line>
<line>    elsif type2 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPConvertNaN.2" file="shared_pseudocode.xml" hover="function: bits(M) FPConvertNaN(bits(N) op, integer M)">FPConvertNaN</a>(<a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type2, op2, fpcr, fpexc), N);</line>
<line>    elsif type3 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPConvertNaN.2" file="shared_pseudocode.xml" hover="function: bits(M) FPConvertNaN(bits(N) op, integer M)">FPConvertNaN</a>(<a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type3, op3, fpcr, fpexc), N);</line>
<line>    elsif type4 == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        done = TRUE;  result = <a link="impl-shared.FPConvertNaN.2" file="shared_pseudocode.xml" hover="function: bits(M) FPConvertNaN(bits(N) op, integer M)">FPConvertNaN</a>(<a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(type4, op4, fpcr, fpexc), N);</line>
<line>    else</line>
<line>        done = FALSE;  result = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(N);  // 'Don't care' result</line>
<line></line>
<line>    return (done, result);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fprecipestimate/FPRecipEstimate" mylink="shared.functions.float.fprecipestimate.FPRecipEstimate" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPRecipEstimate()</line>
<line>// =================</line>
<line></line>
<line link="impl-shared.FPRecipEstimate.2" hover="function: bits(N) FPRecipEstimate(bits(N) operand, FPCRType fpcr_in)" conts="FPRecipEstimate">bits(N) <anchor link="impl-shared.FPRecipEstimate.2" hover="function: bits(N) FPRecipEstimate(bits(N) operand, FPCRType fpcr_in)">FPRecipEstimate</anchor>(bits(N) operand, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    bits(N) result;</line>
<line>    boolean overflow_to_inf;</line>
<line>    // When using alternative floating-point behavior, do not generate</line>
<line>    // floating-point exceptions, flush denormal input and output to zero,</line>
<line>    // and use RNE rounding mode.</line>
<line>    boolean altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1';</line>
<line>    boolean fpexc = !altfp;</line>
<line>    if altfp then fpcr.&lt;FIZ,FZ&gt; = '11';</line>
<line>    if altfp then fpcr.RMode    = '00';</line>
<line></line>
<line>    (fptype,sign,value) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(operand, fpcr, fpexc);</line>
<line></line>
<line>    <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(fpcr);</line>
<line>    if fptype == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> || fptype == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        result = <a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(fptype, operand, fpcr, fpexc);</line>
<line>    elsif fptype == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a> then</line>
<line>        result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign, N);</line>
<line>    elsif fptype == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> then</line>
<line>        result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>(sign, N);</line>
<line>        if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_DivideByZero" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_DivideByZero</a>, fpcr);</line>
<line>    elsif (</line>
<line>            (N == 16 &amp;&amp; <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(value) &lt; 2.0^-16) ||</line>
<line>            (N == 32 &amp;&amp; <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(value) &lt; 2.0^-128) ||</line>
<line>            (N == 64 &amp;&amp; <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(value) &lt; 2.0^-1024)</line>
<line>          ) then</line>
<line>        case rounding of</line>
<line>            when <a link="FPRounding_TIEEVEN" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEEVEN</a></line>
<line>                overflow_to_inf = TRUE;</line>
<line>            when <a link="FPRounding_POSINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_POSINF</a></line>
<line>                overflow_to_inf = (sign == '0');</line>
<line>            when <a link="FPRounding_NEGINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_NEGINF</a></line>
<line>                overflow_to_inf = (sign == '1');</line>
<line>            when <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a></line>
<line>                overflow_to_inf = FALSE;</line>
<line>        result = if overflow_to_inf then <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>(sign, N) else <a link="impl-shared.FPMaxNormal.2" file="shared_pseudocode.xml" hover="function: bits(N) FPMaxNormal(bit sign, integer N)">FPMaxNormal</a>(sign, N);</line>
<line>        if fpexc then</line>
<line>            <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_Overflow" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_Overflow</a>, fpcr);</line>
<line>            <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_Inexact" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_Inexact</a>, fpcr);</line>
<line>    elsif ((fpcr.FZ == '1' &amp;&amp; N != 16) || (fpcr.FZ16 == '1' &amp;&amp; N == 16))</line>
<line>          &amp;&amp; (</line>
<line>               (N == 16 &amp;&amp; <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(value) &gt;= 2.0^14) ||</line>
<line>               (N == 32 &amp;&amp; <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(value) &gt;= 2.0^126) ||</line>
<line>               (N == 64 &amp;&amp; <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(value) &gt;= 2.0^1022)</line>
<line>             ) then</line>
<line>        // Result flushed to zero of correct sign</line>
<line>        result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign, N);</line>
<line></line>
<line>        // Flush-to-zero never generates a trapped exception.</line>
<line>        if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>            FPSCR.UFC = '1';</line>
<line>        else</line>
<line>            if fpexc then FPSR.UFC = '1';</line>
<line>    else</line>
<line>        // Scale to a fixed point value in the range 0.5 &lt;= x &lt; 1.0 in steps of 1/512, and</line>
<line>        // calculate result exponent. Scaled value has copied sign bit,</line>
<line>        // exponent = 1022 = double-precision biased version of -1,</line>
<line>        // fraction = original fraction</line>
<line>        bits(52) fraction;</line>
<line>        integer exp;</line>
<line>        case N of</line>
<line>            when 16</line>
<line>                fraction = operand&lt;9:0&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(42);</line>
<line>                exp = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(operand&lt;14:10&gt;);</line>
<line>            when 32</line>
<line>                fraction = operand&lt;22:0&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(29);</line>
<line>                exp = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(operand&lt;30:23&gt;);</line>
<line>            when 64</line>
<line>                fraction = operand&lt;51:0&gt;;</line>
<line>                exp = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(operand&lt;62:52&gt;);</line>
<line></line>
<line>        if exp == 0 then</line>
<line>            if fraction&lt;51&gt; == '0' then</line>
<line>                exp = -1;</line>
<line>                fraction = fraction&lt;49:0&gt;:'00';</line>
<line>            else</line>
<line>                fraction = fraction&lt;50:0&gt;:'0';</line>
<line></line>
<line>        integer scaled;</line>
<line>        boolean increasedprecision = N==32 &amp;&amp; <a link="impl-shared.HaveFeatRPRES.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatRPRES()">HaveFeatRPRES</a>() &amp;&amp; altfp;</line>
<line></line>
<line>        if !increasedprecision then</line>
<line>            scaled = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('1':fraction&lt;51:44&gt;);</line>
<line>        else</line>
<line>            scaled = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('1':fraction&lt;51:41&gt;);</line>
<line></line>
<line>        integer result_exp;</line>
<line>        case N of</line>
<line>            when 16 result_exp =   29 - exp; // In range 29-30 = -1 to 29+1 = 30</line>
<line>            when 32 result_exp =  253 - exp; // In range 253-254 = -1 to 253+1 = 254</line>
<line>            when 64 result_exp = 2045 - exp; // In range 2045-2046 = -1 to 2045+1 = 2046</line>
<line></line>
<line>        // Scaled is in range 256 .. 511 or 2048 .. 4095 range representing a</line>
<line>        // fixed-point number in range [0.5 .. 1.0].</line>
<line>        estimate = <a link="impl-shared.RecipEstimate.2" file="shared_pseudocode.xml" hover="function: integer RecipEstimate(integer a_in, boolean increasedprecision)">RecipEstimate</a>(scaled, increasedprecision);</line>
<line></line>
<line>        // Estimate is in the range 256 .. 511 or 4096 .. 8191 representing a</line>
<line>        // fixed-point result in the range [1.0 .. 2.0].</line>
<line>        // Convert to scaled floating point result with copied sign bit,</line>
<line>        // high-order bits from estimate, and exponent calculated above.</line>
<line>        if !increasedprecision then</line>
<line>            fraction = estimate&lt;7:0&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(44);</line>
<line>        else</line>
<line>            fraction = estimate&lt;11:0&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(40);</line>
<line></line>
<line>        if result_exp == 0 then</line>
<line>            fraction = '1' : fraction&lt;51:1&gt;;</line>
<line>        elsif result_exp == -1 then</line>
<line>            fraction = '01' : fraction&lt;51:2&gt;;</line>
<line>            result_exp = 0;</line>
<line></line>
<line>        case N of</line>
<line>            when 16 result = sign : result_exp&lt;N-12:0&gt; : fraction&lt;51:42&gt;;</line>
<line>            when 32 result = sign : result_exp&lt;N-25:0&gt; : fraction&lt;51:29&gt;;</line>
<line>            when 64 result = sign : result_exp&lt;N-54:0&gt; : fraction&lt;51:0&gt;;</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fprecipestimate/RecipEstimate" mylink="shared.functions.float.fprecipestimate.RecipEstimate" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// RecipEstimate()</line>
<line>// ===============</line>
<line>// Compute estimate of reciprocal of 9-bit fixed-point number.</line>
<line>//</line>
<line>// a is in range 256 .. 511 or 2048 .. 4096 representing a number in</line>
<line>// the range 0.5 &lt;= x &lt; 1.0.</line>
<line>// increasedprecision determines if the mantissa is 8-bit or 12-bit.</line>
<line>// result is in the range 256 .. 511 or 4096 .. 8191 representing a</line>
<line>// number in the range 1.0 to 511/256 or 1.00 to 8191/4096.</line>
<line></line>
<line link="impl-shared.RecipEstimate.2" hover="function: integer RecipEstimate(integer a_in, boolean increasedprecision)" conts="RecipEstimate">integer <anchor link="impl-shared.RecipEstimate.2" hover="function: integer RecipEstimate(integer a_in, boolean increasedprecision)">RecipEstimate</anchor>(integer a_in, boolean increasedprecision)</line>
<line></line>
<line>    integer a = a_in;</line>
<line>    integer r;</line>
<line>    if !increasedprecision then</line>
<line>        assert 256 &lt;= a &amp;&amp; a &lt; 512;</line>
<line>        a = a*2+1;                       // Round to nearest</line>
<line>        integer b = (2 ^ 19) DIV a;</line>
<line>        r = (b+1) DIV 2;                 // Round to nearest</line>
<line>        assert 256 &lt;= r &amp;&amp; r &lt; 512;</line>
<line>    else</line>
<line>        assert 2048 &lt;= a &amp;&amp; a &lt; 4096;</line>
<line>        a = a*2+1;                       // Round to nearest</line>
<line>        real real_val = Real(2^25)/Real(a);</line>
<line>        r = <a link="impl-shared.RoundDown.1" file="shared_pseudocode.xml" hover="function: integer RoundDown(real x)">RoundDown</a>(real_val);</line>
<line>        real error = real_val - Real(r);</line>
<line>        boolean round_up = error &gt; 0.5;  // Error cannot be exactly 0.5 so do not need tie case</line>
<line>        if round_up then r = r+1;</line>
<line>        assert 4096 &lt;= r &amp;&amp; r &lt; 8192;</line>
<line></line>
<line>    return r;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fprecpx/FPRecpX" mylink="shared.functions.float.fprecpx.FPRecpX" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPRecpX()</line>
<line>// =========</line>
<line></line>
<line link="impl-shared.FPRecpX.2" hover="function: bits(N) FPRecpX(bits(N) op, FPCRType fpcr_in)" conts="FPRecpX">bits(N) <anchor link="impl-shared.FPRecpX.2" hover="function: bits(N) FPRecpX(bits(N) op, FPCRType fpcr_in)">FPRecpX</anchor>(bits(N) op, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    integer esize;</line>
<line>    case N of</line>
<line>        when 16 esize =  5;</line>
<line>        when 32 esize =  8;</line>
<line>        when 64 esize = 11;</line>
<line></line>
<line>    bits(N)           result;</line>
<line>    bits(esize)       exp;</line>
<line>    bits(esize)       max_exp;</line>
<line>    bits(N-(esize+1)) frac = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(N-(esize+1));</line>
<line></line>
<line>    boolean altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; fpcr.AH == '1';</line>
<line>    boolean fpexc = !altfp;                 // Generate no floating-point exceptions</line>
<line>    if altfp then fpcr.&lt;FIZ,FZ&gt; = '11';     // Flush denormal input and output to zero</line>
<line>    (fptype,sign,value) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op, fpcr, fpexc);</line>
<line></line>
<line>    case N of</line>
<line>        when 16 exp = op&lt;(10+esize)-1:10&gt;;</line>
<line>        when 32 exp = op&lt;(23+esize)-1:23&gt;;</line>
<line>        when 64 exp = op&lt;(52+esize)-1:52&gt;;</line>
<line></line>
<line>    max_exp = <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(esize) - 1;</line>
<line></line>
<line>    if fptype == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> || fptype == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        result = <a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(fptype, op, fpcr, fpexc);</line>
<line>    else</line>
<line>        if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(exp) then                 // Zero and denormals</line>
<line>            result = sign:max_exp:frac;</line>
<line>        else                                // Infinities and normals</line>
<line>            result = sign:NOT(exp):frac;</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpround/FPRound" mylink="shared.functions.float.fpround.FPRound" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPRound()</line>
<line>// =========</line>
<line>// Generic conversion from precise, unbounded real data type to IEEE format.</line>
<line></line>
<line link="impl-shared.FPRound.3" hover="function: bits(N) FPRound(real op, FPCRType fpcr, integer N)" conts="FPRound">bits(N) <anchor link="impl-shared.FPRound.3" hover="function: bits(N) FPRound(real op, FPCRType fpcr, integer N)">FPRound</anchor>(real op, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, integer N)</line>
<line>    return <a link="impl-shared.FPRound.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRound(real op, FPCRType fpcr_in, FPRounding rounding, integer N)">FPRound</a>(op, fpcr, <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(fpcr), N);</line>
<line></line>
<line>// FPRound()</line>
<line>// =========</line>
<line>// For directed FP conversion, includes an explicit 'rounding' argument.</line>
<line></line>
<line link="impl-shared.FPRound.4" hover="function: bits(N) FPRound(real op, FPCRType fpcr_in, FPRounding rounding, integer N)" conts="FPRound">bits(N) <anchor link="impl-shared.FPRound.4" hover="function: bits(N) FPRound(real op, FPCRType fpcr_in, FPRounding rounding, integer N)">FPRound</anchor>(real op, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in, <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding, integer N)</line>
<line>    boolean fpexc = TRUE;    // Generate floating-point exceptions</line>
<line>    return <a link="impl-shared.FPRound.5" file="shared_pseudocode.xml" hover="function: bits(N) FPRound(real op, FPCRType fpcr_in, FPRounding rounding, boolean fpexc, integer N)">FPRound</a>(op, fpcr_in, rounding, fpexc, N);</line>
<line></line>
<line>// FPRound()</line>
<line>// =========</line>
<line>// For AltFP, includes an explicit FPEXC argument to disable exception</line>
<line>// generation and switches off Arm alternate half-precision mode.</line>
<line></line>
<line link="impl-shared.FPRound.5" hover="function: bits(N) FPRound(real op, FPCRType fpcr_in, FPRounding rounding, boolean fpexc, integer N)" conts="FPRound">bits(N) <anchor link="impl-shared.FPRound.5" hover="function: bits(N) FPRound(real op, FPCRType fpcr_in, FPRounding rounding, boolean fpexc, integer N)">FPRound</anchor>(real op, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in, <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding, boolean fpexc, integer N)</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    fpcr.AHP = '0';</line>
<line>    boolean isbfloat16 = FALSE;</line>
<line>    return <a link="impl-shared.FPRoundBase.6" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundBase(real op, FPCRType fpcr, FPRounding rounding, boolean isbfloat16, boolean fpexc, integer N)">FPRoundBase</a>(op, fpcr, rounding, isbfloat16, fpexc, N);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpround/FPRoundBase" mylink="shared.functions.float.fpround.FPRoundBase" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPRoundBase()</line>
<line>// =============</line>
<line>// For BFloat16, includes an explicit 'isbfloat16' argument.</line>
<line></line>
<line link="impl-shared.FPRoundBase.5" hover="function: bits(N) FPRoundBase(real op, FPCRType fpcr, FPRounding rounding, boolean isbfloat16, integer N)" conts="FPRoundBase">bits(N) <anchor link="impl-shared.FPRoundBase.5" hover="function: bits(N) FPRoundBase(real op, FPCRType fpcr, FPRounding rounding, boolean isbfloat16, integer N)">FPRoundBase</anchor>(real op, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding, boolean isbfloat16, integer N)</line>
<line>    boolean fpexc = TRUE;    // Generate floating-point exceptions</line>
<line>    return <a link="impl-shared.FPRoundBase.6" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundBase(real op, FPCRType fpcr, FPRounding rounding, boolean isbfloat16, boolean fpexc, integer N)">FPRoundBase</a>(op, fpcr, rounding, isbfloat16, fpexc, N);</line>
<line></line>
<line>// FPRoundBase()</line>
<line>// =============</line>
<line>// Convert a real number 'op' into an N-bit floating-point value using the</line>
<line>// supplied rounding mode 'rounding'.</line>
<line>//</line>
<line>// The 'fpcr' argument supplies FPCR control bits and 'fpexc' controls the</line>
<line>// generation of floating-point exceptions. Status information is updated</line>
<line>// directly in the FPSR where appropriate.</line>
<line></line>
<line link="impl-shared.FPRoundBase.6" hover="function: bits(N) FPRoundBase(real op, FPCRType fpcr, FPRounding rounding, boolean isbfloat16, boolean fpexc, integer N)" conts="FPRoundBase">bits(N) <anchor link="impl-shared.FPRoundBase.6" hover="function: bits(N) FPRoundBase(real op, FPCRType fpcr, FPRounding rounding, boolean isbfloat16, boolean fpexc, integer N)">FPRoundBase</anchor>(real op, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding,</line>
<line>                    boolean isbfloat16, boolean fpexc, integer N)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    assert op != 0.0;</line>
<line>    assert rounding != <a link="FPRounding_TIEAWAY" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEAWAY</a>;</line>
<line>    bits(N) result;</line>
<line></line>
<line>    // Obtain format parameters - minimum exponent, numbers of exponent and fraction bits.</line>
<line>    integer minimum_exp;</line>
<line>    integer F;</line>
<line>    integer E;</line>
<line>    if N == 16 then</line>
<line>        minimum_exp = -14;  E = 5;  F = 10;</line>
<line>    elsif N == 32 &amp;&amp; isbfloat16 then</line>
<line>        minimum_exp = -126;  E = 8;  F = 7;</line>
<line>    elsif N == 32 then</line>
<line>        minimum_exp = -126;  E = 8;  F = 23;</line>
<line>    else  // N == 64</line>
<line>        minimum_exp = -1022;  E = 11;  F = 52;</line>
<line></line>
<line>    // Split value into sign, unrounded mantissa and exponent.</line>
<line>    bit sign;</line>
<line>    real mantissa;</line>
<line>    if op &lt; 0.0 then</line>
<line>        sign = '1';  mantissa = -op;</line>
<line>    else</line>
<line>        sign = '0';  mantissa = op;</line>
<line>    exponent = 0;</line>
<line>    while mantissa &lt; 1.0 do</line>
<line>        mantissa = mantissa * 2.0;  exponent = exponent - 1;</line>
<line>    while mantissa &gt;= 2.0 do</line>
<line>        mantissa = mantissa / 2.0;  exponent = exponent + 1;</line>
<line></line>
<line>    // When TRUE, detection of underflow occurs after rounding and the test for a</line>
<line>    // denormalized number for single and double precision values occurs after rounding.</line>
<line>    altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1';</line>
<line></line>
<line>    // Deal with flush-to-zero before rounding if FPCR.AH != '1'.</line>
<line>    if (!altfp &amp;&amp; ((fpcr.FZ == '1' &amp;&amp; N != 16) || (fpcr.FZ16 == '1' &amp;&amp; N == 16)) &amp;&amp;</line>
<line>        exponent &lt; minimum_exp) then</line>
<line>        // Flush-to-zero never generates a trapped exception.</line>
<line>        if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>            FPSCR.UFC = '1';</line>
<line>        else</line>
<line>            if fpexc then FPSR.UFC = '1';</line>
<line>        return <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign, N);</line>
<line></line>
<line>    biased_exp_unconstrained = (exponent - minimum_exp) + 1;</line>
<line>    int_mant_unconstrained = <a link="impl-shared.RoundDown.1" file="shared_pseudocode.xml" hover="function: integer RoundDown(real x)">RoundDown</a>(mantissa * 2.0^F);</line>
<line>    error_unconstrained = mantissa * 2.0^F - Real(int_mant_unconstrained);</line>
<line></line>
<line>    // Start creating the exponent value for the result. Start by biasing the actual exponent</line>
<line>    // so that the minimum exponent becomes 1, lower values 0 (indicating possible underflow).</line>
<line>    biased_exp = <a link="impl-shared.Max.2" file="shared_pseudocode.xml" hover="function: integer Max(integer a, integer b)">Max</a>((exponent - minimum_exp) + 1, 0);</line>
<line>    if biased_exp == 0 then mantissa = mantissa / 2.0^(minimum_exp - exponent);</line>
<line></line>
<line>    // Get the unrounded mantissa as an integer, and the "units in last place" rounding error.</line>
<line>    int_mant = <a link="impl-shared.RoundDown.1" file="shared_pseudocode.xml" hover="function: integer RoundDown(real x)">RoundDown</a>(mantissa * 2.0^F);  // &lt; 2.0^F if biased_exp == 0, &gt;= 2.0^F if not</line>
<line>    error = mantissa * 2.0^F - Real(int_mant);</line>
<line></line>
<line>    // Underflow occurs if exponent is too small before rounding, and result is inexact or</line>
<line>    // the Underflow exception is trapped. This applies before rounding if FPCR.AH != '1'.</line>
<line>    boolean trapped_UF = fpcr.UFE == '1' &amp;&amp; (!<a link="impl-aarch64.InStreamingMode.0" file="shared_pseudocode.xml" hover="function: boolean InStreamingMode()">InStreamingMode</a>() || <a link="impl-aarch64.IsFullA64Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsFullA64Enabled()">IsFullA64Enabled</a>());</line>
<line>    if !altfp &amp;&amp; biased_exp == 0 &amp;&amp; (error != 0.0 || trapped_UF) then</line>
<line>        if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_Underflow" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_Underflow</a>, fpcr);</line>
<line></line>
<line>    // Round result according to rounding mode.</line>
<line>    boolean round_up_unconstrained;</line>
<line>    boolean round_up;</line>
<line>    boolean overflow_to_inf;</line>
<line>    if altfp then</line>
<line></line>
<line>        case rounding of</line>
<line>            when <a link="FPRounding_TIEEVEN" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEEVEN</a></line>
<line>                round_up_unconstrained = (error_unconstrained &gt; 0.5 ||</line>
<line>                   (error_unconstrained == 0.5 &amp;&amp; int_mant_unconstrained&lt;0&gt; == '1'));</line>
<line>                round_up = (error &gt; 0.5 || (error == 0.5 &amp;&amp; int_mant&lt;0&gt; == '1'));</line>
<line>                overflow_to_inf = TRUE;</line>
<line>            when <a link="FPRounding_POSINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_POSINF</a></line>
<line>                round_up_unconstrained = (error_unconstrained != 0.0 &amp;&amp; sign == '0');</line>
<line>                round_up = (error != 0.0 &amp;&amp; sign == '0');</line>
<line>                overflow_to_inf = (sign == '0');</line>
<line>            when <a link="FPRounding_NEGINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_NEGINF</a></line>
<line>                round_up_unconstrained = (error_unconstrained != 0.0 &amp;&amp; sign == '1');</line>
<line>                round_up = (error != 0.0 &amp;&amp; sign == '1');</line>
<line>                overflow_to_inf = (sign == '1');</line>
<line>            when <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>, <a link="FPRounding_ODD" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ODD</a></line>
<line>                round_up_unconstrained = FALSE;</line>
<line>                round_up = FALSE;</line>
<line>                overflow_to_inf = FALSE;</line>
<line></line>
<line>        if round_up_unconstrained then</line>
<line>            int_mant_unconstrained = int_mant_unconstrained + 1;</line>
<line>            if int_mant_unconstrained == 2^(F+1) then    // Rounded up to next exponent</line>
<line>                biased_exp_unconstrained = biased_exp_unconstrained + 1;</line>
<line>                int_mant_unconstrained   = int_mant_unconstrained DIV 2;</line>
<line></line>
<line>        // Deal with flush-to-zero and underflow after rounding if FPCR.AH == '1'.</line>
<line>        if biased_exp_unconstrained &lt; 1 &amp;&amp; int_mant_unconstrained != 0 then</line>
<line>            // the result of unconstrained rounding is less than the minimum normalized number</line>
<line>            if (fpcr.FZ == '1' &amp;&amp; N != 16) || (fpcr.FZ16 == '1' &amp;&amp; N == 16) then   // Flush-to-zero</line>
<line>                if fpexc then</line>
<line>                    FPSR.UFC = '1';</line>
<line>                    <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_Inexact" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_Inexact</a>, fpcr);</line>
<line>                return <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign, N);</line>
<line>            elsif error != 0.0 || trapped_UF then</line>
<line>                if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_Underflow" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_Underflow</a>, fpcr);</line>
<line>    else    // altfp == FALSE</line>
<line>        case rounding of</line>
<line>            when <a link="FPRounding_TIEEVEN" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEEVEN</a></line>
<line>                round_up = (error &gt; 0.5 || (error == 0.5 &amp;&amp; int_mant&lt;0&gt; == '1'));</line>
<line>                overflow_to_inf = TRUE;</line>
<line>            when <a link="FPRounding_POSINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_POSINF</a></line>
<line>                round_up = (error != 0.0 &amp;&amp; sign == '0');</line>
<line>                overflow_to_inf = (sign == '0');</line>
<line>            when <a link="FPRounding_NEGINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_NEGINF</a></line>
<line>                round_up = (error != 0.0 &amp;&amp; sign == '1');</line>
<line>                overflow_to_inf = (sign == '1');</line>
<line>            when <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>, <a link="FPRounding_ODD" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ODD</a></line>
<line>                round_up = FALSE;</line>
<line>                overflow_to_inf = FALSE;</line>
<line></line>
<line>    if round_up then</line>
<line>        int_mant = int_mant + 1;</line>
<line>        if int_mant == 2^F then      // Rounded up from denormalized to normalized</line>
<line>            biased_exp = 1;</line>
<line>        if int_mant == 2^(F+1) then  // Rounded up to next exponent</line>
<line>            biased_exp = biased_exp + 1;</line>
<line>            int_mant = int_mant DIV 2;</line>
<line></line>
<line>    // Handle rounding to odd</line>
<line>    if error != 0.0 &amp;&amp; rounding == <a link="FPRounding_ODD" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ODD</a> then</line>
<line>        int_mant&lt;0&gt; = '1';</line>
<line></line>
<line>    // Deal with overflow and generate result.</line>
<line>    if N != 16 || fpcr.AHP == '0' then  // Single, double or IEEE half precision</line>
<line>        if biased_exp &gt;= 2^E - 1 then</line>
<line>            result = if overflow_to_inf then <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>(sign, N) else <a link="impl-shared.FPMaxNormal.2" file="shared_pseudocode.xml" hover="function: bits(N) FPMaxNormal(bit sign, integer N)">FPMaxNormal</a>(sign, N);</line>
<line>            if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_Overflow" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_Overflow</a>, fpcr);</line>
<line>            error = 1.0;  // Ensure that an Inexact exception occurs</line>
<line>        else</line>
<line>            result = sign : biased_exp&lt;E-1:0&gt; : int_mant&lt;F-1:0&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(N-(E+F+1));</line>
<line>    else                                     // Alternative half precision</line>
<line>        if biased_exp &gt;= 2^E then</line>
<line>            result = sign : <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(N-1);</line>
<line>            if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>            error = 0.0;  // Ensure that an Inexact exception does not occur</line>
<line>        else</line>
<line>            result = sign : biased_exp&lt;E-1:0&gt; : int_mant&lt;F-1:0&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(N-(E+F+1));</line>
<line></line>
<line>    // Deal with Inexact exception.</line>
<line>    if error != 0.0 then</line>
<line>        if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_Inexact" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_Inexact</a>, fpcr);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpround/FPRoundCV" mylink="shared.functions.float.fpround.FPRoundCV" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPRoundCV()</line>
<line>// ===========</line>
<line>// Used for FP to FP conversion instructions.</line>
<line>// For half-precision data ignores FZ16 and observes AHP.</line>
<line></line>
<line link="impl-shared.FPRoundCV.4" hover="function: bits(N) FPRoundCV(real op, FPCRType fpcr_in, FPRounding rounding, integer N)" conts="FPRoundCV">bits(N) <anchor link="impl-shared.FPRoundCV.4" hover="function: bits(N) FPRoundCV(real op, FPCRType fpcr_in, FPRounding rounding, integer N)">FPRoundCV</anchor>(real op, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in, <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding, integer N)</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    fpcr.FZ16 = '0';</line>
<line>    boolean fpexc = TRUE;    // Generate floating-point exceptions</line>
<line>    boolean isbfloat16 = FALSE;</line>
<line>    return <a link="impl-shared.FPRoundBase.6" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundBase(real op, FPCRType fpcr, FPRounding rounding, boolean isbfloat16, boolean fpexc, integer N)">FPRoundBase</a>(op, fpcr, rounding, isbfloat16, fpexc, N);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fprounding/FPRounding" mylink="shared.functions.float.fprounding.FPRounding" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPRounding</line>
<line>// ==========</line>
<line>// The conversion and rounding functions take an explicit</line>
<line>// rounding mode enumeration instead of booleans or FPCR values.</line>
<line></line>
<line link="FPRounding" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}" conts="FPRounding">enumeration <anchor link="FPRounding" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</anchor>  {<anchor link="FPRounding_TIEEVEN" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEEVEN</anchor>, <anchor link="FPRounding_POSINF" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_POSINF</anchor>,</line>
<line link="FPRounding_NEGINF" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}" conts="FPRounding_NEGINF">                         <anchor link="FPRounding_NEGINF" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_NEGINF</anchor>,  <anchor link="FPRounding_ZERO" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</anchor>,</line>
<line link="FPRounding_TIEAWAY" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}" conts="FPRounding_TIEAWAY">                         <anchor link="FPRounding_TIEAWAY" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEAWAY</anchor>, <anchor link="FPRounding_ODD" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ODD</anchor>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fproundingmode/FPRoundingMode" mylink="shared.functions.float.fproundingmode.FPRoundingMode" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPRoundingMode()</line>
<line>// ================</line>
<line>// Return the current floating-point rounding mode.</line>
<line></line>
<line link="impl-shared.FPRoundingMode.1" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)" conts="FPRoundingMode">FPRounding <anchor link="impl-shared.FPRoundingMode.1" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</anchor>(<a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    return <a link="impl-shared.FPDecodeRounding.1" file="shared_pseudocode.xml" hover="function: FPRounding FPDecodeRounding(bits(2) rmode)">FPDecodeRounding</a>(fpcr.RMode);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fproundint/FPRoundInt" mylink="shared.functions.float.fproundint.FPRoundInt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPRoundInt()</line>
<line>// ============</line>
<line></line>
<line>// Round op to nearest integral floating point value using rounding mode in FPCR/FPSCR.</line>
<line>// If EXACT is TRUE, set FPSR.IXC if result is not numerically equal to op.</line>
<line></line>
<line link="impl-shared.FPRoundInt.4" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)" conts="FPRoundInt">bits(N) <anchor link="impl-shared.FPRoundInt.4" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</anchor>(bits(N) op, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding, boolean exact)</line>
<line></line>
<line>    assert rounding != <a link="FPRounding_ODD" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ODD</a>;</line>
<line>    assert N IN {16,32,64};</line>
<line></line>
<line>    // When alternative floating-point support is TRUE, do not generate</line>
<line>    // Input Denormal floating-point exceptions.</line>
<line>    altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1';</line>
<line>    fpexc = !altfp;</line>
<line></line>
<line>    // Unpack using FPCR to determine if subnormals are flushed-to-zero.</line>
<line>    (fptype,sign,value) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op, fpcr, fpexc);</line>
<line></line>
<line>    bits(N) result;</line>
<line>    if fptype == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> || fptype == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        result = <a link="impl-shared.FPProcessNaN.3" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr)">FPProcessNaN</a>(fptype, op, fpcr);</line>
<line>    elsif fptype == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a> then</line>
<line>        result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>(sign, N);</line>
<line>    elsif fptype == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> then</line>
<line>        result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign, N);</line>
<line>    else</line>
<line>        // Extract integer component.</line>
<line>        int_result = <a link="impl-shared.RoundDown.1" file="shared_pseudocode.xml" hover="function: integer RoundDown(real x)">RoundDown</a>(value);</line>
<line>        error = value - Real(int_result);</line>
<line></line>
<line>        // Determine whether supplied rounding mode requires an increment.</line>
<line>        boolean round_up;</line>
<line>        case rounding of</line>
<line>            when <a link="FPRounding_TIEEVEN" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEEVEN</a></line>
<line>                round_up = (error &gt; 0.5 || (error == 0.5 &amp;&amp; int_result&lt;0&gt; == '1'));</line>
<line>            when <a link="FPRounding_POSINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_POSINF</a></line>
<line>                round_up = (error != 0.0);</line>
<line>            when <a link="FPRounding_NEGINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_NEGINF</a></line>
<line>                round_up = FALSE;</line>
<line>            when <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a></line>
<line>                round_up = (error != 0.0 &amp;&amp; int_result &lt; 0);</line>
<line>            when <a link="FPRounding_TIEAWAY" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEAWAY</a></line>
<line>                round_up = (error &gt; 0.5 || (error == 0.5 &amp;&amp; int_result &gt;= 0));</line>
<line></line>
<line>        if round_up then int_result = int_result + 1;</line>
<line></line>
<line>        // Convert integer value into an equivalent real value.</line>
<line>        real_result = Real(int_result);</line>
<line></line>
<line>        // Re-encode as a floating-point value, result is always exact.</line>
<line>        if real_result == 0.0 then</line>
<line>            result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign, N);</line>
<line>        else</line>
<line>            result = <a link="impl-shared.FPRound.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRound(real op, FPCRType fpcr_in, FPRounding rounding, integer N)">FPRound</a>(real_result, fpcr, <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>, N);</line>
<line></line>
<line>        // Generate inexact exceptions.</line>
<line>        if error != 0.0 &amp;&amp; exact then</line>
<line>            <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_Inexact" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_Inexact</a>, fpcr);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fproundintn/FPRoundIntN" mylink="shared.functions.float.fproundintn.FPRoundIntN" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPRoundIntN()</line>
<line>// =============</line>
<line></line>
<line link="impl-shared.FPRoundIntN.4" hover="function: bits(N) FPRoundIntN(bits(N) op, FPCRType fpcr, FPRounding rounding, integer intsize)" conts="FPRoundIntN">bits(N) <anchor link="impl-shared.FPRoundIntN.4" hover="function: bits(N) FPRoundIntN(bits(N) op, FPCRType fpcr, FPRounding rounding, integer intsize)">FPRoundIntN</anchor>(bits(N) op, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding, integer intsize)</line>
<line>    assert rounding != <a link="FPRounding_ODD" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ODD</a>;</line>
<line>    assert N IN {32,64};</line>
<line>    assert intsize IN {32, 64};</line>
<line>    integer exp;</line>
<line>    bits(N) result;</line>
<line>    boolean round_up;</line>
<line>    constant integer E = (if N == 32 then 8 else 11);</line>
<line>    constant integer F = N - (E + 1);</line>
<line></line>
<line>    // When alternative floating-point support is TRUE, do not generate</line>
<line>    // Input Denormal floating-point exceptions.</line>
<line>    altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1';</line>
<line>    fpexc = !altfp;</line>
<line></line>
<line>    // Unpack using FPCR to determine if subnormals are flushed-to-zero.</line>
<line>    (fptype,sign,value) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op, fpcr, fpexc);</line>
<line></line>
<line>    if fptype IN {<a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>, <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a>, <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>} then</line>
<line>        if N == 32 then</line>
<line>            exp = 126 + intsize;</line>
<line>            result = '1':exp&lt;(E-1):0&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(F);</line>
<line>        else</line>
<line>            exp = 1022+intsize;</line>
<line>            result = '1':exp&lt;(E-1):0&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(F);</line>
<line>        <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>    elsif fptype == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> then</line>
<line>        result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign, N);</line>
<line>    else</line>
<line>        // Extract integer component.</line>
<line>        int_result = <a link="impl-shared.RoundDown.1" file="shared_pseudocode.xml" hover="function: integer RoundDown(real x)">RoundDown</a>(value);</line>
<line>        error = value - Real(int_result);</line>
<line></line>
<line>        // Determine whether supplied rounding mode requires an increment.</line>
<line>        case rounding of</line>
<line>            when <a link="FPRounding_TIEEVEN" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEEVEN</a></line>
<line>                round_up = error &gt; 0.5 || (error == 0.5 &amp;&amp; int_result&lt;0&gt; == '1');</line>
<line>            when <a link="FPRounding_POSINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_POSINF</a></line>
<line>                round_up = error != 0.0;</line>
<line>            when <a link="FPRounding_NEGINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_NEGINF</a></line>
<line>                round_up = FALSE;</line>
<line>            when <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a></line>
<line>                round_up = error != 0.0 &amp;&amp; int_result &lt; 0;</line>
<line>            when <a link="FPRounding_TIEAWAY" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEAWAY</a></line>
<line>                round_up = error &gt; 0.5 || (error == 0.5 &amp;&amp; int_result &gt;= 0);</line>
<line></line>
<line>        if round_up then int_result = int_result + 1;</line>
<line>        overflow = int_result &gt; 2^(intsize-1)-1 || int_result &lt; -1*2^(intsize-1);</line>
<line></line>
<line>        if overflow then</line>
<line>            if N == 32 then</line>
<line>                exp = 126 + intsize;</line>
<line>                result = '1':exp&lt;(E-1):0&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(F);</line>
<line>            else</line>
<line>                exp = 1022 + intsize;</line>
<line>                result = '1':exp&lt;(E-1):0&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(F);</line>
<line>            <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>            // This case shouldn't set Inexact.</line>
<line>            error = 0.0;</line>
<line></line>
<line>        else</line>
<line>            // Convert integer value into an equivalent real value.</line>
<line>            real_result = Real(int_result);</line>
<line></line>
<line>            // Re-encode as a floating-point value, result is always exact.</line>
<line>            if real_result == 0.0 then</line>
<line>                result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign, N);</line>
<line>            else</line>
<line>                result = <a link="impl-shared.FPRound.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRound(real op, FPCRType fpcr_in, FPRounding rounding, integer N)">FPRound</a>(real_result, fpcr, <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>, N);</line>
<line></line>
<line>        // Generate inexact exceptions.</line>
<line>        if error != 0.0 then</line>
<line>            <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_Inexact" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_Inexact</a>, fpcr);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fprsqrtestimate/FPRSqrtEstimate" mylink="shared.functions.float.fprsqrtestimate.FPRSqrtEstimate" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPRSqrtEstimate()</line>
<line>// =================</line>
<line></line>
<line link="impl-shared.FPRSqrtEstimate.2" hover="function: bits(N) FPRSqrtEstimate(bits(N) operand, FPCRType fpcr_in)" conts="FPRSqrtEstimate">bits(N) <anchor link="impl-shared.FPRSqrtEstimate.2" hover="function: bits(N) FPRSqrtEstimate(bits(N) operand, FPCRType fpcr_in)">FPRSqrtEstimate</anchor>(bits(N) operand, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line></line>
<line>    // When using alternative floating-point behavior, do not generate</line>
<line>    // floating-point exceptions and flush denormal input to zero.</line>
<line>    boolean altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1';</line>
<line>    boolean fpexc = !altfp;</line>
<line>    if altfp then fpcr.&lt;FIZ,FZ&gt; = '11';</line>
<line></line>
<line>    (fptype,sign,value) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(operand, fpcr, fpexc);</line>
<line></line>
<line>    bits(N) result;</line>
<line>    if fptype == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> || fptype == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        result = <a link="impl-shared.FPProcessNaN.4" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr, boolean fpexc)">FPProcessNaN</a>(fptype, operand, fpcr, fpexc);</line>
<line>    elsif fptype == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> then</line>
<line>        result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>(sign, N);</line>
<line>        if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_DivideByZero" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_DivideByZero</a>, fpcr);</line>
<line>    elsif sign == '1' then</line>
<line>        result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, N);</line>
<line>        if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>    elsif fptype == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a> then</line>
<line>        result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>('0', N);</line>
<line>    else</line>
<line>        // Scale to a fixed-point value in the range 0.25 &lt;= x &lt; 1.0 in steps of 512, with the</line>
<line>        // evenness or oddness of the exponent unchanged, and calculate result exponent.</line>
<line>        // Scaled value has copied sign bit, exponent = 1022 or 1021 = double-precision</line>
<line>        // biased version of -1 or -2, fraction = original fraction extended with zeros.</line>
<line></line>
<line>        bits(52) fraction;</line>
<line>        integer exp;</line>
<line>        case N of</line>
<line>            when 16</line>
<line>                fraction = operand&lt;9:0&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(42);</line>
<line>                exp = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(operand&lt;14:10&gt;);</line>
<line>            when 32</line>
<line>                fraction = operand&lt;22:0&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(29);</line>
<line>                exp = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(operand&lt;30:23&gt;);</line>
<line>            when 64</line>
<line>                fraction = operand&lt;51:0&gt;;</line>
<line>                exp = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(operand&lt;62:52&gt;);</line>
<line></line>
<line>        if exp == 0 then</line>
<line>            while fraction&lt;51&gt; == '0' do</line>
<line>                fraction = fraction&lt;50:0&gt; : '0';</line>
<line>                exp = exp - 1;</line>
<line>            fraction = fraction&lt;50:0&gt; : '0';</line>
<line></line>
<line>        integer scaled;</line>
<line>        boolean increasedprecision = N==32 &amp;&amp; <a link="impl-shared.HaveFeatRPRES.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatRPRES()">HaveFeatRPRES</a>() &amp;&amp; altfp;</line>
<line></line>
<line>        if !increasedprecision then</line>
<line>            if exp&lt;0&gt; == '0' then</line>
<line>                scaled = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('1':fraction&lt;51:44&gt;);</line>
<line>            else</line>
<line>                scaled = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('01':fraction&lt;51:45&gt;);</line>
<line>        else</line>
<line>            if exp&lt;0&gt; == '0' then</line>
<line>                scaled = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('1':fraction&lt;51:41&gt;);</line>
<line>            else</line>
<line>                scaled = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('01':fraction&lt;51:42&gt;);</line>
<line></line>
<line>        integer result_exp;</line>
<line>        case N of</line>
<line>            when 16 result_exp = (  44 - exp) DIV 2;</line>
<line>            when 32 result_exp = ( 380 - exp) DIV 2;</line>
<line>            when 64 result_exp = (3068 - exp) DIV 2;</line>
<line></line>
<line>        estimate = <a link="impl-shared.RecipSqrtEstimate.2" file="shared_pseudocode.xml" hover="function: integer RecipSqrtEstimate(integer a_in, boolean increasedprecision)">RecipSqrtEstimate</a>(scaled, increasedprecision);</line>
<line></line>
<line>        // Estimate is in the range 256 .. 511 or 4096 .. 8191 representing a</line>
<line>        // fixed-point result in the range [1.0 .. 2.0].</line>
<line>        // Convert to scaled floating point result with copied sign bit and high-order</line>
<line>        // fraction bits, and exponent calculated above.</line>
<line>        case N of</line>
<line>            when 16 result = '0' : result_exp&lt;N-12:0&gt; : estimate&lt;7:0&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(2);</line>
<line>            when 32</line>
<line>                if !increasedprecision then</line>
<line>                    result = '0' : result_exp&lt;N-25:0&gt; : estimate&lt;7:0&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(15);</line>
<line>                else</line>
<line>                    result = '0' : result_exp&lt;N-25:0&gt; : estimate&lt;11:0&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(11);</line>
<line>            when 64 result = '0' : result_exp&lt;N-54:0&gt; : estimate&lt;7:0&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(44);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fprsqrtestimate/RecipSqrtEstimate" mylink="shared.functions.float.fprsqrtestimate.RecipSqrtEstimate" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// RecipSqrtEstimate()</line>
<line>// ===================</line>
<line>// Compute estimate of reciprocal square root of 9-bit fixed-point number.</line>
<line>//</line>
<line>// a_in is in range 128 .. 511 or 1024 .. 4095, with increased precision,</line>
<line>// representing a number in the range 0.25 &lt;= x &lt; 1.0.</line>
<line>// increasedprecision determines if the mantissa is 8-bit or 12-bit.</line>
<line>// result is in the range 256 .. 511 or 4096 .. 8191, with increased precision,</line>
<line>// representing a number in the range 1.0 to 511/256 or 8191/4096.</line>
<line></line>
<line link="impl-shared.RecipSqrtEstimate.2" hover="function: integer RecipSqrtEstimate(integer a_in, boolean increasedprecision)" conts="RecipSqrtEstimate">integer <anchor link="impl-shared.RecipSqrtEstimate.2" hover="function: integer RecipSqrtEstimate(integer a_in, boolean increasedprecision)">RecipSqrtEstimate</anchor>(integer a_in, boolean increasedprecision)</line>
<line></line>
<line>    integer a = a_in;</line>
<line>    integer r;</line>
<line>    if !increasedprecision then</line>
<line>        assert 128 &lt;= a &amp;&amp; a &lt; 512;</line>
<line>        if a &lt; 256 then                      // 0.25 .. 0.5</line>
<line>            a = a*2+1;                       // a in units of 1/512 rounded to nearest</line>
<line>        else                                 // 0.5 .. 1.0</line>
<line>            a = (a &gt;&gt; 1) &lt;&lt; 1;               // Discard bottom bit</line>
<line>            a = (a+1)*2;                     // a in units of 1/256 rounded to nearest</line>
<line>        integer b = 512;</line>
<line>        while a*(b+1)*(b+1) &lt; 2^28 do</line>
<line>            b = b+1;</line>
<line>        // b = largest b such that b &lt; 2^14 / sqrt(a)</line>
<line>        r = (b+1) DIV 2;                     // Round to nearest</line>
<line>        assert 256 &lt;= r &amp;&amp; r &lt; 512;</line>
<line>    else</line>
<line>        assert 1024 &lt;= a &amp;&amp; a &lt; 4096;</line>
<line>        real real_val;</line>
<line>        real error;</line>
<line>        integer int_val;</line>
<line></line>
<line>        if a &lt; 2048 then                     // 0.25... 0.5</line>
<line>            a = a*2 + 1;                     // Take 10 bits of fraction and force a 1 at the bottom</line>
<line>            real_val = Real(a)/2.0;</line>
<line>        else                                 // 0.5..1.0</line>
<line>            a = (a &gt;&gt; 1) &lt;&lt; 1;               // Discard bottom bit</line>
<line>            a = a+1;                         // Take 10 bits of fraction and force a 1 at the bottom</line>
<line>            real_val = Real(a);</line>
<line></line>
<line>        real_val = Sqrt(real_val);           // This number will lie in the range of 32 to 64</line>
<line>                                             // Round to nearest even for a DP float number</line>
<line>        real_val = real_val * Real(2^47);    // The integer is the size of the whole DP mantissa</line>
<line>        int_val  = <a link="impl-shared.RoundDown.1" file="shared_pseudocode.xml" hover="function: integer RoundDown(real x)">RoundDown</a>(real_val);      // Calculate rounding value</line>
<line>        error    = real_val - Real(int_val);</line>
<line>        round_up = error &gt; 0.5;              // Error cannot be exactly 0.5 so do not need tie case</line>
<line>        if round_up then int_val = int_val+1;</line>
<line></line>
<line>        real_val = Real(2^65)/Real(int_val); // Lies in the range 4096 &lt;= real_val &lt; 8192</line>
<line>        int_val  = <a link="impl-shared.RoundDown.1" file="shared_pseudocode.xml" hover="function: integer RoundDown(real x)">RoundDown</a>(real_val);      // Round that (to nearest even) to give integer</line>
<line>        error    = real_val - Real(int_val);</line>
<line>        round_up = (error &gt; 0.5 || (error == 0.5 &amp;&amp; int_val&lt;0&gt; == '1'));</line>
<line>        if round_up then int_val = int_val+1;</line>
<line></line>
<line>        r = int_val;</line>
<line>        assert 4096 &lt;= r &amp;&amp; r &lt; 8192;</line>
<line></line>
<line>    return r;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpsqrt/FPSqrt" mylink="shared.functions.float.fpsqrt.FPSqrt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPSqrt()</line>
<line>// ========</line>
<line></line>
<line link="impl-shared.FPSqrt.2" hover="function: bits(N) FPSqrt(bits(N) op, FPCRType fpcr)" conts="FPSqrt">bits(N) <anchor link="impl-shared.FPSqrt.2" hover="function: bits(N) FPSqrt(bits(N) op, FPCRType fpcr)">FPSqrt</anchor>(bits(N) op, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    (fptype,sign,value) = <a link="impl-shared.FPUnpack.2" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</a>(op, fpcr);</line>
<line></line>
<line>    bits(N) result;</line>
<line>    if fptype == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> || fptype == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        result = <a link="impl-shared.FPProcessNaN.3" file="shared_pseudocode.xml" hover="function: bits(N) FPProcessNaN(FPType fptype, bits(N) op, FPCRType fpcr)">FPProcessNaN</a>(fptype, op, fpcr);</line>
<line>    elsif fptype == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a> then</line>
<line>        result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign, N);</line>
<line>    elsif fptype == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a> &amp;&amp; sign == '0' then</line>
<line>        result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>(sign, N);</line>
<line>    elsif sign == '1' then</line>
<line>        result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, N);</line>
<line>        <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>    else</line>
<line>        result = <a link="impl-shared.FPRound.3" file="shared_pseudocode.xml" hover="function: bits(N) FPRound(real op, FPCRType fpcr, integer N)">FPRound</a>(Sqrt(value), fpcr, N);</line>
<line>        <a link="impl-shared.FPProcessDenorm.3" file="shared_pseudocode.xml" hover="function: FPProcessDenorm(FPType fptype, integer N, FPCRType fpcr)">FPProcessDenorm</a>(fptype, N, fpcr);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpsub/FPSub" mylink="shared.functions.float.fpsub.FPSub" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPSub()</line>
<line>// =======</line>
<line></line>
<line link="impl-shared.FPSub.3" hover="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr)" conts="FPSub">bits(N) <anchor link="impl-shared.FPSub.3" hover="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPSub</anchor>(bits(N) op1, bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr)</line>
<line>    boolean fpexc = TRUE;       // Generate floating-point exceptions</line>
<line>    return <a link="impl-shared.FPSub.4" file="shared_pseudocode.xml" hover="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)">FPSub</a>(op1, op2, fpcr, fpexc);</line>
<line></line>
<line>// FPSub()</line>
<line>// =======</line>
<line></line>
<line link="impl-shared.FPSub.4" hover="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)" conts="FPSub">bits(N) <anchor link="impl-shared.FPSub.4" hover="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)">FPSub</anchor>(bits(N) op1, bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, boolean fpexc)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(fpcr);</line>
<line></line>
<line>    (type1,sign1,value1) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op1, fpcr, fpexc);</line>
<line>    (type2,sign2,value2) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op2, fpcr, fpexc);</line>
<line></line>
<line>    (done,result) = <a link="impl-shared.FPProcessNaNs.6" file="shared_pseudocode.xml" hover="function: (boolean, bits(N)) FPProcessNaNs(FPType type1, FPType type2, bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)">FPProcessNaNs</a>(type1, type2, op1, op2, fpcr, fpexc);</line>
<line>    if !done then</line>
<line>        inf1 = (type1 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        inf2 = (type2 == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>);</line>
<line>        zero1 = (type1 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line>        zero2 = (type2 == <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>);</line>
<line></line>
<line>        if inf1 &amp;&amp; inf2 &amp;&amp; sign1 == sign2 then</line>
<line>            result = <a link="impl-shared.FPDefaultNaN.2" file="shared_pseudocode.xml" hover="function: bits(N) FPDefaultNaN(FPCRType fpcr, integer N)">FPDefaultNaN</a>(fpcr, N);</line>
<line>            if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>        elsif (inf1 &amp;&amp; sign1 == '0') || (inf2 &amp;&amp; sign2 == '1') then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('0', N);</line>
<line>        elsif (inf1 &amp;&amp; sign1 == '1') || (inf2 &amp;&amp; sign2 == '0') then</line>
<line>            result = <a link="impl-shared.FPInfinity.2" file="shared_pseudocode.xml" hover="function: bits(N) FPInfinity(bit sign, integer N)">FPInfinity</a>('1', N);</line>
<line>        elsif zero1 &amp;&amp; zero2 &amp;&amp; sign1 == NOT(sign2) then</line>
<line>            result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(sign1, N);</line>
<line>        else</line>
<line>            result_value = value1 - value2;</line>
<line>            if result_value == 0.0 then  // Sign of exact zero result depends on rounding mode</line>
<line>                result_sign = if rounding == <a link="FPRounding_NEGINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_NEGINF</a> then '1' else '0';</line>
<line>                result = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>(result_sign, N);</line>
<line>            else</line>
<line>                result = <a link="impl-shared.FPRound.5" file="shared_pseudocode.xml" hover="function: bits(N) FPRound(real op, FPCRType fpcr_in, FPRounding rounding, boolean fpexc, integer N)">FPRound</a>(result_value, fpcr, rounding, fpexc, N);</line>
<line></line>
<line>        if fpexc then <a link="impl-shared.FPProcessDenorms.4" file="shared_pseudocode.xml" hover="function: FPProcessDenorms(FPType type1, FPType type2, integer N, FPCRType fpcr)">FPProcessDenorms</a>(type1, type2, N, fpcr);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpsub/FPSub_ZA" mylink="shared.functions.float.fpsub.FPSub_ZA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPSub_ZA()</line>
<line>// ==========</line>
<line>// Calculates op1-op2 for SME2 ZA-targeting instructions.</line>
<line></line>
<line link="impl-shared.FPSub_ZA.3" hover="function: bits(N) FPSub_ZA(bits(N) op1, bits(N) op2, FPCRType fpcr_in)" conts="FPSub_ZA">bits(N) <anchor link="impl-shared.FPSub_ZA.3" hover="function: bits(N) FPSub_ZA(bits(N) op1, bits(N) op2, FPCRType fpcr_in)">FPSub_ZA</anchor>(bits(N) op1, bits(N) op2, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in)</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    boolean fpexc = FALSE;      // Do not generate floating-point exceptions</line>
<line>    fpcr.DN = '1';              // Generate default NaN values</line>
<line>    return <a link="impl-shared.FPSub.4" file="shared_pseudocode.xml" hover="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr, boolean fpexc)">FPSub</a>(op1, op2, fpcr, fpexc);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpthree/FPThree" mylink="shared.functions.float.fpthree.FPThree" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPThree()</line>
<line>// =========</line>
<line></line>
<line link="impl-shared.FPThree.2" hover="function: bits(N) FPThree(bit sign, integer N)" conts="FPThree">bits(N) <anchor link="impl-shared.FPThree.2" hover="function: bits(N) FPThree(bit sign, integer N)">FPThree</anchor>(bit sign, integer N)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    constant integer E = (if N == 16 then 5 elsif N == 32 then 8 else 11);</line>
<line>    constant integer F = N - (E + 1);</line>
<line>    exp  = '1':<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(E-1);</line>
<line>    frac = '1':<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(F-1);</line>
<line>    result = sign : exp : frac;</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fptofixed/FPToFixed" mylink="shared.functions.float.fptofixed.FPToFixed" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPToFixed()</line>
<line>// ===========</line>
<line></line>
<line>// Convert N-bit precision floating point 'op' to M-bit fixed point with</line>
<line>// FBITS fractional bits, controlled by UNSIGNED and ROUNDING.</line>
<line></line>
<line link="impl-shared.FPToFixed.6" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)" conts="FPToFixed">bits(M) <anchor link="impl-shared.FPToFixed.6" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</anchor>(bits(N) op, integer fbits, boolean unsigned, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr,</line>
<line>                  <a link="FPRounding" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding</a> rounding, integer M)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    assert M IN {16,32,64};</line>
<line>    assert fbits &gt;= 0;</line>
<line>    assert rounding != <a link="FPRounding_ODD" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ODD</a>;</line>
<line></line>
<line>    // When alternative floating-point support is TRUE, do not generate</line>
<line>    // Input Denormal floating-point exceptions.</line>
<line>    altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1';</line>
<line>    fpexc = !altfp;</line>
<line></line>
<line>    // Unpack using fpcr to determine if subnormals are flushed-to-zero.</line>
<line>    (fptype,sign,value) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op, fpcr, fpexc);</line>
<line></line>
<line>    // If NaN, set cumulative flag or take exception.</line>
<line>    if fptype == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> || fptype == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line></line>
<line>    // Scale by fractional bits and produce integer rounded towards minus-infinity.</line>
<line>    value = value * 2.0^fbits;</line>
<line>    int_result = <a link="impl-shared.RoundDown.1" file="shared_pseudocode.xml" hover="function: integer RoundDown(real x)">RoundDown</a>(value);</line>
<line>    error = value - Real(int_result);</line>
<line></line>
<line>    // Determine whether supplied rounding mode requires an increment.</line>
<line>    boolean round_up;</line>
<line>    case rounding of</line>
<line>        when <a link="FPRounding_TIEEVEN" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEEVEN</a></line>
<line>            round_up = (error &gt; 0.5 || (error == 0.5 &amp;&amp; int_result&lt;0&gt; == '1'));</line>
<line>        when <a link="FPRounding_POSINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_POSINF</a></line>
<line>            round_up = (error != 0.0);</line>
<line>        when <a link="FPRounding_NEGINF" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_NEGINF</a></line>
<line>            round_up = FALSE;</line>
<line>        when <a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a></line>
<line>            round_up = (error != 0.0 &amp;&amp; int_result &lt; 0);</line>
<line>        when <a link="FPRounding_TIEAWAY" file="shared_pseudocode.xml" hover="enumeration FPRounding  {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF,  FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEAWAY</a></line>
<line>            round_up = (error &gt; 0.5 || (error == 0.5 &amp;&amp; int_result &gt;= 0));</line>
<line></line>
<line>    if round_up then int_result = int_result + 1;</line>
<line></line>
<line>    // Generate saturated result and exceptions.</line>
<line>    (result, overflow) = <a link="impl-shared.SatQ.3" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(int_result, M, unsigned);</line>
<line>    if overflow then</line>
<line>        <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>    elsif error != 0.0 then</line>
<line>        <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_Inexact" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_Inexact</a>, fpcr);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fptofixedjs/FPToFixedJS" mylink="shared.functions.float.fptofixedjs.FPToFixedJS" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPToFixedJS()</line>
<line>// =============</line>
<line></line>
<line>// Converts a double precision floating point input value</line>
<line>// to a signed integer, with rounding to zero.</line>
<line></line>
<line link="impl-shared.FPToFixedJS.4" hover="function: (bits(N), bit) FPToFixedJS(bits(M) op, FPCRType fpcr, boolean Is64, integer N)" conts="FPToFixedJS">(bits(N), bit) <anchor link="impl-shared.FPToFixedJS.4" hover="function: (bits(N), bit) FPToFixedJS(bits(M) op, FPCRType fpcr, boolean Is64, integer N)">FPToFixedJS</anchor>(bits(M) op, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, boolean Is64, integer N)</line>
<line></line>
<line>    assert M == 64 &amp;&amp; N == 32;</line>
<line></line>
<line>    // If FALSE, never generate Input Denormal floating-point exceptions.</line>
<line>    fpexc_idenorm = !(<a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; fpcr.AH == '1');</line>
<line></line>
<line>    // Unpack using fpcr to determine if subnormals are flushed-to-zero.</line>
<line>    (fptype,sign,value) = <a link="impl-shared.FPUnpack.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</a>(op, fpcr, fpexc_idenorm);</line>
<line></line>
<line>    z = '1';</line>
<line>    // If NaN, set cumulative flag or take exception.</line>
<line>    if fptype == <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a> || fptype == <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> then</line>
<line>        <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>        z = '0';</line>
<line></line>
<line>    int_result = <a link="impl-shared.RoundDown.1" file="shared_pseudocode.xml" hover="function: integer RoundDown(real x)">RoundDown</a>(value);</line>
<line>    error = value - Real(int_result);</line>
<line></line>
<line>    // Determine whether supplied rounding mode requires an increment.</line>
<line></line>
<line>    round_it_up = (error != 0.0 &amp;&amp; int_result &lt; 0);</line>
<line>    if round_it_up then int_result = int_result + 1;</line>
<line></line>
<line>    integer result;</line>
<line>    if int_result &lt; 0 then</line>
<line>        result = int_result - 2^32*<a link="impl-shared.RoundUp.1" file="shared_pseudocode.xml" hover="function: integer RoundUp(real x)">RoundUp</a>(Real(int_result)/Real(2^32));</line>
<line>    else</line>
<line>        result = int_result - 2^32*<a link="impl-shared.RoundDown.1" file="shared_pseudocode.xml" hover="function: integer RoundDown(real x)">RoundDown</a>(Real(int_result)/Real(2^32));</line>
<line></line>
<line>    // Generate exceptions.</line>
<line>    if int_result &lt; -(2^31) || int_result &gt; (2^31)-1 then</line>
<line>        <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InvalidOp" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InvalidOp</a>, fpcr);</line>
<line>        z = '0';</line>
<line>    elsif error != 0.0 then</line>
<line>        <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_Inexact" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_Inexact</a>, fpcr);</line>
<line>        z = '0';</line>
<line>    elsif sign == '1' &amp;&amp; value == 0.0 then</line>
<line>        z = '0';</line>
<line>    elsif sign == '0' &amp;&amp; value == 0.0 &amp;&amp; !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(op&lt;51:0&gt;) then</line>
<line>        z = '0';</line>
<line></line>
<line>    if fptype == <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a> then result = 0;</line>
<line></line>
<line>    return (result&lt;N-1:0&gt;, z);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fptwo/FPTwo" mylink="shared.functions.float.fptwo.FPTwo" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPTwo()</line>
<line>// =======</line>
<line></line>
<line link="impl-shared.FPTwo.2" hover="function: bits(N) FPTwo(bit sign, integer N)" conts="FPTwo">bits(N) <anchor link="impl-shared.FPTwo.2" hover="function: bits(N) FPTwo(bit sign, integer N)">FPTwo</anchor>(bit sign, integer N)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    constant integer E = (if N == 16 then 5 elsif N == 32 then 8 else 11);</line>
<line>    constant integer F = N - (E + 1);</line>
<line>    exp  = '1':<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(E-1);</line>
<line>    frac = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(F);</line>
<line>    result = sign : exp : frac;</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fptype/FPType" mylink="shared.functions.float.fptype.FPType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPType</line>
<line>// ======</line>
<line></line>
<line link="FPType" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}" conts="FPType">enumeration <anchor link="FPType" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</anchor> {<anchor link="FPType_Zero" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</anchor>,</line>
<line link="FPType_Denormal" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}" conts="FPType_Denormal">                    <anchor link="FPType_Denormal" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Denormal</anchor>,</line>
<line link="FPType_Nonzero" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}" conts="FPType_Nonzero">                    <anchor link="FPType_Nonzero" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Nonzero</anchor>,</line>
<line link="FPType_Infinity" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}" conts="FPType_Infinity">                    <anchor link="FPType_Infinity" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</anchor>,</line>
<line link="FPType_QNaN" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}" conts="FPType_QNaN">                    <anchor link="FPType_QNaN" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</anchor>,</line>
<line link="FPType_SNaN" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}" conts="FPType_SNaN">                    <anchor link="FPType_SNaN" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</anchor>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpunpack/FPUnpack" mylink="shared.functions.float.fpunpack.FPUnpack" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPUnpack()</line>
<line>// ==========</line>
<line></line>
<line link="impl-shared.FPUnpack.2" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)" conts="FPUnpack">(FPType, bit, real) <anchor link="impl-shared.FPUnpack.2" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in)">FPUnpack</anchor>(bits(N) fpval, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in)</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    fpcr.AHP = '0';</line>
<line>    boolean fpexc = TRUE;   // Generate floating-point exceptions</line>
<line>    (fp_type, sign, value) = <a link="impl-shared.FPUnpackBase.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpackBase(bits(N) fpval, FPCRType fpcr, boolean fpexc)">FPUnpackBase</a>(fpval, fpcr, fpexc);</line>
<line>    return (fp_type, sign, value);</line>
<line></line>
<line>// FPUnpack()</line>
<line>// ==========</line>
<line>//</line>
<line>// Used by data processing, int/fixed to FP and FP to int/fixed conversion instructions.</line>
<line>// For half-precision data it ignores AHP, and observes FZ16.</line>
<line></line>
<line link="impl-shared.FPUnpack.3" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)" conts="FPUnpack">(FPType, bit, real) <anchor link="impl-shared.FPUnpack.3" hover="function: (FPType, bit, real) FPUnpack(bits(N) fpval, FPCRType fpcr_in, boolean fpexc)">FPUnpack</anchor>(bits(N) fpval, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in, boolean fpexc)</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    fpcr.AHP = '0';</line>
<line>    (fp_type, sign, value) = <a link="impl-shared.FPUnpackBase.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpackBase(bits(N) fpval, FPCRType fpcr, boolean fpexc)">FPUnpackBase</a>(fpval, fpcr, fpexc);</line>
<line>    return (fp_type, sign, value);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpunpack/FPUnpackBase" mylink="shared.functions.float.fpunpack.FPUnpackBase" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPUnpackBase()</line>
<line>// ==============</line>
<line></line>
<line link="impl-shared.FPUnpackBase.3" hover="function: (FPType, bit, real) FPUnpackBase(bits(N) fpval, FPCRType fpcr, boolean fpexc)" conts="FPUnpackBase">(FPType, bit, real) <anchor link="impl-shared.FPUnpackBase.3" hover="function: (FPType, bit, real) FPUnpackBase(bits(N) fpval, FPCRType fpcr, boolean fpexc)">FPUnpackBase</anchor>(bits(N) fpval, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr, boolean fpexc)</line>
<line>    boolean isbfloat16 = FALSE;</line>
<line>    (fp_type, sign, value) = <a link="impl-shared.FPUnpackBase.4" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpackBase(bits(N) fpval, FPCRType fpcr_in, boolean fpexc, boolean isbfloat16)">FPUnpackBase</a>(fpval, fpcr, fpexc, isbfloat16);</line>
<line>    return (fp_type, sign, value);</line>
<line></line>
<line>// FPUnpackBase()</line>
<line>// ==============</line>
<line>//</line>
<line>// Unpack a floating-point number into its type, sign bit and the real number</line>
<line>// that it represents. The real number result has the correct sign for numbers</line>
<line>// and infinities, is very large in magnitude for infinities, and is 0.0 for</line>
<line>// NaNs. (These values are chosen to simplify the description of comparisons</line>
<line>// and conversions.)</line>
<line>//</line>
<line>// The 'fpcr_in' argument supplies FPCR control bits, 'fpexc' controls the</line>
<line>// generation of floating-point exceptions and 'isbfloat16' determines whether</line>
<line>// N=16 signifies BFloat16 or half-precision type. Status information is updated</line>
<line>// directly in the FPSR where appropriate.</line>
<line></line>
<line link="impl-shared.FPUnpackBase.4" hover="function: (FPType, bit, real) FPUnpackBase(bits(N) fpval, FPCRType fpcr_in, boolean fpexc, boolean isbfloat16)" conts="FPUnpackBase">(FPType, bit, real) <anchor link="impl-shared.FPUnpackBase.4" hover="function: (FPType, bit, real) FPUnpackBase(bits(N) fpval, FPCRType fpcr_in, boolean fpexc, boolean isbfloat16)">FPUnpackBase</anchor>(bits(N) fpval, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in, boolean fpexc,</line>
<line>                                 boolean isbfloat16)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line></line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line></line>
<line>    boolean altfp = <a link="impl-shared.HaveAltFP.0" file="shared_pseudocode.xml" hover="function: boolean HaveAltFP()">HaveAltFP</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>();</line>
<line>    boolean fiz   = altfp &amp;&amp; fpcr.FIZ == '1';</line>
<line>    boolean fz    = fpcr.FZ == '1' &amp;&amp; !(altfp &amp;&amp; fpcr.AH == '1');</line>
<line>    real value;</line>
<line>    bit sign;</line>
<line>    <a link="FPType" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType</a> fptype;</line>
<line></line>
<line>    if N == 16 &amp;&amp; !isbfloat16 then</line>
<line>        sign   = fpval&lt;15&gt;;</line>
<line>        exp16  = fpval&lt;14:10&gt;;</line>
<line>        frac16 = fpval&lt;9:0&gt;;</line>
<line>        if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(exp16) then</line>
<line>            if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(frac16) || fpcr.FZ16 == '1' then</line>
<line>                fptype = <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>;  value = 0.0;</line>
<line>            else</line>
<line>                fptype = <a link="FPType_Denormal" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Denormal</a>;  value = 2.0^-14 * (Real(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(frac16)) * 2.0^-10);</line>
<line>        elsif <a link="impl-shared.IsOnes.1" file="shared_pseudocode.xml" hover="function: boolean IsOnes(bits(N) x)">IsOnes</a>(exp16) &amp;&amp; fpcr.AHP == '0' then  // Infinity or NaN in IEEE format</line>
<line>            if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(frac16) then</line>
<line>                fptype = <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>;  value = 2.0^1000000;</line>
<line>            else</line>
<line>                fptype = if frac16&lt;9&gt; == '1' then <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> else <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>;</line>
<line>                value = 0.0;</line>
<line>        else</line>
<line>            fptype = <a link="FPType_Nonzero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Nonzero</a>;</line>
<line>            value = 2.0^(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(exp16)-15) * (1.0 + Real(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(frac16)) * 2.0^-10);</line>
<line></line>
<line>    elsif N == 32 || isbfloat16 then</line>
<line>        bits(8) exp32;</line>
<line>        bits(23) frac32;</line>
<line>        if isbfloat16 then</line>
<line>            sign   = fpval&lt;15&gt;;</line>
<line>            exp32  = fpval&lt;14:7&gt;;</line>
<line>            frac32 = fpval&lt;6:0&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>        else</line>
<line>            sign   = fpval&lt;31&gt;;</line>
<line>            exp32  = fpval&lt;30:23&gt;;</line>
<line>            frac32 = fpval&lt;22:0&gt;;</line>
<line></line>
<line>        if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(exp32) then</line>
<line>            if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(frac32) then</line>
<line>                // Produce zero if value is zero.</line>
<line>                fptype = <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>;  value = 0.0;</line>
<line>            elsif fz || fiz then        // Flush-to-zero if FIZ==1 or AH,FZ==01</line>
<line>                fptype = <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>;  value = 0.0;</line>
<line>                // Check whether to raise Input Denormal floating-point exception.</line>
<line>                // fpcr.FIZ==1 does not raise Input Denormal exception.</line>
<line>                if fz then</line>
<line>                    // Denormalized input flushed to zero</line>
<line>                    if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InputDenorm" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InputDenorm</a>, fpcr);</line>
<line>            else</line>
<line>                fptype = <a link="FPType_Denormal" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Denormal</a>;  value = 2.0^-126 * (Real(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(frac32)) * 2.0^-23);</line>
<line>        elsif <a link="impl-shared.IsOnes.1" file="shared_pseudocode.xml" hover="function: boolean IsOnes(bits(N) x)">IsOnes</a>(exp32) then</line>
<line>            if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(frac32) then</line>
<line>                fptype = <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>;  value = 2.0^1000000;</line>
<line>            else</line>
<line>                fptype = if frac32&lt;22&gt; == '1' then <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> else <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>;</line>
<line>                value = 0.0;</line>
<line>        else</line>
<line>            fptype = <a link="FPType_Nonzero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Nonzero</a>;</line>
<line>            value = 2.0^(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(exp32)-127) * (1.0 + Real(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(frac32)) * 2.0^-23);</line>
<line></line>
<line>    else // N == 64</line>
<line>        sign   = fpval&lt;63&gt;;</line>
<line>        exp64  = fpval&lt;62:52&gt;;</line>
<line>        frac64 = fpval&lt;51:0&gt;;</line>
<line></line>
<line>        if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(exp64) then</line>
<line>            if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(frac64) then</line>
<line>                // Produce zero if value is zero.</line>
<line>                fptype = <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>;  value = 0.0;</line>
<line>            elsif fz || fiz then        // Flush-to-zero if FIZ==1 or AH,FZ==01</line>
<line>                fptype = <a link="FPType_Zero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Zero</a>;  value = 0.0;</line>
<line>                // Check whether to raise Input Denormal floating-point exception.</line>
<line>                // fpcr.FIZ==1 does not raise Input Denormal exception.</line>
<line>                if fz then</line>
<line>                    // Denormalized input flushed to zero</line>
<line>                    if fpexc then <a link="impl-shared.FPProcessException.2" file="shared_pseudocode.xml" hover="function: FPProcessException(FPExc exception, FPCRType fpcr)">FPProcessException</a>(<a link="FPExc_InputDenorm" file="shared_pseudocode.xml" hover="enumeration FPExc       {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}">FPExc_InputDenorm</a>, fpcr);</line>
<line>            else</line>
<line>                fptype = <a link="FPType_Denormal" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Denormal</a>;  value = 2.0^-1022 * (Real(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(frac64)) * 2.0^-52);</line>
<line>        elsif <a link="impl-shared.IsOnes.1" file="shared_pseudocode.xml" hover="function: boolean IsOnes(bits(N) x)">IsOnes</a>(exp64) then</line>
<line>            if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(frac64) then</line>
<line>                fptype = <a link="FPType_Infinity" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Infinity</a>;  value = 2.0^1000000;</line>
<line>            else</line>
<line>                fptype = if frac64&lt;51&gt; == '1' then <a link="FPType_QNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_QNaN</a> else <a link="FPType_SNaN" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_SNaN</a>;</line>
<line>                value = 0.0;</line>
<line>        else</line>
<line>            fptype = <a link="FPType_Nonzero" file="shared_pseudocode.xml" hover="enumeration FPType {FPType_Zero, FPType_Denormal, FPType_Nonzero, FPType_Infinity, FPType_QNaN, FPType_SNaN}">FPType_Nonzero</a>;</line>
<line>            value = 2.0^(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(exp64)-1023) * (1.0 + Real(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(frac64)) * 2.0^-52);</line>
<line></line>
<line>    if sign == '1' then value = -value;</line>
<line></line>
<line>    return (fptype, sign, value);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpunpack/FPUnpackCV" mylink="shared.functions.float.fpunpack.FPUnpackCV" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPUnpackCV()</line>
<line>// ============</line>
<line>//</line>
<line>// Used for FP to FP conversion instructions.</line>
<line>// For half-precision data ignores FZ16 and observes AHP.</line>
<line></line>
<line link="impl-shared.FPUnpackCV.2" hover="function: (FPType, bit, real) FPUnpackCV(bits(N) fpval, FPCRType fpcr_in)" conts="FPUnpackCV">(FPType, bit, real) <anchor link="impl-shared.FPUnpackCV.2" hover="function: (FPType, bit, real) FPUnpackCV(bits(N) fpval, FPCRType fpcr_in)">FPUnpackCV</anchor>(bits(N) fpval, <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr_in)</line>
<line>    <a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = fpcr_in;</line>
<line>    fpcr.FZ16 = '0';</line>
<line>    boolean fpexc = TRUE;   // Generate floating-point exceptions</line>
<line>    (fp_type, sign, value) = <a link="impl-shared.FPUnpackBase.3" file="shared_pseudocode.xml" hover="function: (FPType, bit, real) FPUnpackBase(bits(N) fpval, FPCRType fpcr, boolean fpexc)">FPUnpackBase</a>(fpval, fpcr, fpexc);</line>
<line>    return (fp_type, sign, value);</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/fpzero/FPZero" mylink="shared.functions.float.fpzero.FPZero" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FPZero()</line>
<line>// ========</line>
<line></line>
<line link="impl-shared.FPZero.2" hover="function: bits(N) FPZero(bit sign, integer N)" conts="FPZero">bits(N) <anchor link="impl-shared.FPZero.2" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</anchor>(bit sign, integer N)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    constant integer E = (if N == 16 then 5 elsif N == 32 then 8 else 11);</line>
<line>    constant integer F = N - (E + 1);</line>
<line>    exp  = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(E);</line>
<line>    frac = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(F);</line>
<line>    result = sign : exp : frac;</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/float/vfpexpandimm/VFPExpandImm" mylink="shared.functions.float.vfpexpandimm.VFPExpandImm" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// VFPExpandImm()</line>
<line>// ==============</line>
<line></line>
<line link="impl-shared.VFPExpandImm.2" hover="function: bits(N) VFPExpandImm(bits(8) imm8, integer N)" conts="VFPExpandImm">bits(N) <anchor link="impl-shared.VFPExpandImm.2" hover="function: bits(N) VFPExpandImm(bits(8) imm8, integer N)">VFPExpandImm</anchor>(bits(8) imm8, integer N)</line>
<line></line>
<line>    assert N IN {16,32,64};</line>
<line>    constant integer E = (if N == 16 then 5 elsif N == 32 then 8 else 11);</line>
<line>    constant integer F = (N - E) - 1;</line>
<line>    sign = imm8&lt;7&gt;;</line>
<line>    exp  = NOT(imm8&lt;6&gt;):<a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(imm8&lt;6&gt;,E-3):imm8&lt;5:4&gt;;</line>
<line>    frac = imm8&lt;3:0&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(F-4);</line>
<line>    result = sign : exp : frac;</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/integer/AddWithCarry" mylink="shared.functions.integer.AddWithCarry" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AddWithCarry()</line>
<line>// ==============</line>
<line>// Integer addition with carry input, returning result and NZCV flags</line>
<line></line>
<line link="impl-shared.AddWithCarry.3" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)" conts="AddWithCarry">(bits(N), bits(4)) <anchor link="impl-shared.AddWithCarry.3" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</anchor>(bits(N) x, bits(N) y, bit carry_in)</line>
<line>    integer unsigned_sum = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(x) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(y) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(carry_in);</line>
<line>    integer signed_sum = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(x) + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(y) + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(carry_in);</line>
<line>    bits(N) result = unsigned_sum&lt;N-1:0&gt;; // same value as signed_sum&lt;N-1:0&gt;</line>
<line>    bit n = result&lt;N-1&gt;;</line>
<line>    bit z = if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(result) then '1' else '0';</line>
<line>    bit c = if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(result) == unsigned_sum then '0' else '1';</line>
<line>    bit v = if <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(result) == signed_sum then '0' else '1';</line>
<line>    return (result, n:z:c:v);</line>
</pstext>
    </ps>
    <ps name="shared/functions/interrupts/InterruptID" mylink="shared.functions.interrupts.InterruptID" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// InterruptID</line>
<line>// ===========</line>
<line></line>
<line link="InterruptID" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }" conts="InterruptID">enumeration <anchor link="InterruptID" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID</anchor> {</line>
<line link="InterruptID_PMUIRQ" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }" conts="InterruptID_PMUIRQ">    <anchor link="InterruptID_PMUIRQ" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_PMUIRQ</anchor>,</line>
<line link="InterruptID_COMMIRQ" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }" conts="InterruptID_COMMIRQ">    <anchor link="InterruptID_COMMIRQ" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_COMMIRQ</anchor>,</line>
<line link="InterruptID_CTIIRQ" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }" conts="InterruptID_CTIIRQ">    <anchor link="InterruptID_CTIIRQ" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_CTIIRQ</anchor>,</line>
<line link="InterruptID_COMMRX" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }" conts="InterruptID_COMMRX">    <anchor link="InterruptID_COMMRX" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_COMMRX</anchor>,</line>
<line link="InterruptID_COMMTX" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }" conts="InterruptID_COMMTX">    <anchor link="InterruptID_COMMTX" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_COMMTX</anchor>,</line>
<line link="InterruptID_CNTP" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }" conts="InterruptID_CNTP">    <anchor link="InterruptID_CNTP" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_CNTP</anchor>,</line>
<line link="InterruptID_CNTHP" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }" conts="InterruptID_CNTHP">    <anchor link="InterruptID_CNTHP" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_CNTHP</anchor>,</line>
<line link="InterruptID_CNTHPS" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }" conts="InterruptID_CNTHPS">    <anchor link="InterruptID_CNTHPS" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_CNTHPS</anchor>,</line>
<line link="InterruptID_CNTPS" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }" conts="InterruptID_CNTPS">    <anchor link="InterruptID_CNTPS" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_CNTPS</anchor>,</line>
<line link="InterruptID_CNTV" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }" conts="InterruptID_CNTV">    <anchor link="InterruptID_CNTV" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_CNTV</anchor>,</line>
<line link="InterruptID_CNTHV" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }" conts="InterruptID_CNTHV">    <anchor link="InterruptID_CNTHV" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_CNTHV</anchor>,</line>
<line link="InterruptID_CNTHVS" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }" conts="InterruptID_CNTHVS">    <anchor link="InterruptID_CNTHVS" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_CNTHVS</anchor>,</line>
<line link="InterruptID_PMBIRQ" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }" conts="InterruptID_PMBIRQ">    <anchor link="InterruptID_PMBIRQ" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID_PMBIRQ</anchor>,</line>
<line>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/interrupts/SetInterruptRequestLevel" mylink="shared.functions.interrupts.SetInterruptRequestLevel" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SetInterruptRequestLevel()</line>
<line>// ==========================</line>
<line>// Set a level-sensitive interrupt to the specified level.</line>
<line></line>
<line>SetInterruptRequestLevel(<a link="InterruptID" file="shared_pseudocode.xml" hover="enumeration InterruptID { InterruptID_PMUIRQ, InterruptID_COMMIRQ, InterruptID_CTIIRQ, InterruptID_COMMRX, InterruptID_COMMTX, InterruptID_CNTP, InterruptID_CNTHP, InterruptID_CNTHPS, InterruptID_CNTPS, InterruptID_CNTV, InterruptID_CNTHV, InterruptID_CNTHVS, InterruptID_PMBIRQ, }">InterruptID</a> id, signal level);</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/AArch64.BranchAddr" mylink="shared.functions.memory.AArch64.BranchAddr" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.BranchAddr()</line>
<line>// ====================</line>
<line>// Return the virtual address with tag bits removed.</line>
<line>// This is typically used when the address will be stored to the program counter.</line>
<line></line>
<line link="AArch64.BranchAddr.2" hover="function: bits(64) AArch64.BranchAddr(bits(64) vaddress, bits(2) el)" conts="AArch64.BranchAddr">bits(64) <anchor link="AArch64.BranchAddr.2" hover="function: bits(64) AArch64.BranchAddr(bits(64) vaddress, bits(2) el)">AArch64.BranchAddr</anchor>(bits(64) vaddress, bits(2) el)</line>
<line>    assert !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>();</line>
<line>    msbit = <a link="impl-shared.AddrTop.3" file="shared_pseudocode.xml" hover="function: integer AddrTop(bits(64) address, boolean IsInstr, bits(2) el)">AddrTop</a>(vaddress, TRUE, el);</line>
<line>    if msbit == 63 then</line>
<line>        return vaddress;</line>
<line>    elsif (el IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} || <a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>()) &amp;&amp; vaddress&lt;msbit&gt; == '1' then</line>
<line>        return <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(vaddress&lt;msbit:0&gt;, 64);</line>
<line>    else</line>
<line>        return <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(vaddress&lt;msbit:0&gt;, 64);</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/AccessDescriptor" mylink="shared.functions.memory.AccessDescriptor" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AccessDescriptor</line>
<line>// ================</line>
<line>// Memory access or translation invocation details that steer architectural behavior</line>
<line></line>
<line link="AccessDescriptor" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )" conts="AccessDescriptor">type <anchor link="AccessDescriptor" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</anchor> is (</line>
<line>    <a link="AccessType" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType</a> acctype,</line>
<line>    bits(2) el,             // Acting EL for the access</line>
<line>    <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss,       // Acting Security State for the access</line>
<line>    boolean acqsc,          // Acquire with Sequential Consistency</line>
<line>    boolean acqpc,          // FEAT_LRCPC: Acquire with Processor Consistency</line>
<line>    boolean relsc,          // Release with Sequential Consistency</line>
<line>    boolean limitedordered, // FEAT_LOR: Acquire/Release with limited ordering</line>
<line>    boolean exclusive,      // Access has Exclusive semantics</line>
<line>    boolean atomicop,       // FEAT_LSE: Atomic read-modify-write access</line>
<line>    <a link="MemAtomicOp" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp</a> modop,      // FEAT_LSE: The modification operation in the 'atomicop' access</line>
<line>    boolean nontemporal,    // Hints the access is non-temporal</line>
<line>    boolean read,           // Read from memory or only require read permissions</line>
<line>    boolean write,          // Write to memory or only require write permissions</line>
<line>    <a link="CacheOp" file="shared_pseudocode.xml" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp</a> cacheop,        // DC/IC: Cache operation</line>
<line>    <a link="CacheOpScope" file="shared_pseudocode.xml" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope</a> opscope,   // DC/IC: Scope of cache operation</line>
<line>    <a link="CacheType" file="shared_pseudocode.xml" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }">CacheType</a> cachetype,    // DC/IC: Type of target cache</line>
<line>    boolean pan,            // FEAT_PAN: The access is subject to PSTATE.PAN</line>
<line>    boolean transactional,  // FEAT_TME: Access is part of a transaction</line>
<line>    boolean nonfault,       // SVE: Non-faulting load</line>
<line>    boolean firstfault,     // SVE: First-fault load</line>
<line>    boolean first,          // SVE: First-fault load for the first active element</line>
<line>    boolean contiguous,     // SVE: Contiguous load/store not gather load/scatter store</line>
<line>    boolean streamingsve,   // SME: Access made by PE while in streaming SVE mode</line>
<line>    boolean ls64,           // FEAT_LS64: Accesses by accelerator support loads/stores</line>
<line>    boolean mops,           // FEAT_MOPS: Memory operation (CPY/SET) accesses</line>
<line>    boolean rcw,            // FEAT_THE: Read-Check-Write access</line>
<line>    boolean rcws,           // FEAT_THE: Read-Check-Write Software access</line>
<line>    boolean toplevel,       // FEAT_THE: Translation table walk access for TTB address</line>
<line>    <a link="VARange" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange</a> varange,        // FEAT_THE: The corresponding TTBR supplying the TTB</line>
<line>    boolean a32lsmd,        // A32 Load/Store Multiple Data access</line>
<line>    boolean tagchecked,     // FEAT_MTE2: Access is tag checked</line>
<line>    boolean tagaccess,      // FEAT_MTE: Access targets the tag bits</line>
<line>    <a link="MPAMinfo" file="shared_pseudocode.xml" hover="type MPAMinfo is ( PARTIDspaceType mpam_sp, PARTIDtype partid, PMGtype pmg )">MPAMinfo</a> mpam           // FEAT_MPAM: MPAM information</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/AccessType" mylink="shared.functions.memory.AccessType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AccessType</line>
<line>// ==========</line>
<line></line>
<line link="AccessType" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }" conts="AccessType">enumeration <anchor link="AccessType" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType</anchor> {</line>
<line link="AccessType_IFETCH" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }" conts="AccessType_IFETCH">    <anchor link="AccessType_IFETCH" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</anchor>,  // Instruction FETCH</line>
<line link="AccessType_GPR" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }" conts="AccessType_GPR">    <anchor link="AccessType_GPR" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</anchor>,     // Software load/store to a General Purpose Register</line>
<line link="AccessType_ASIMD" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }" conts="AccessType_ASIMD">    <anchor link="AccessType_ASIMD" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_ASIMD</anchor>,   // Software ASIMD extension load/store instructions</line>
<line link="AccessType_SVE" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }" conts="AccessType_SVE">    <anchor link="AccessType_SVE" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_SVE</anchor>,     // Software SVE load/store instructions</line>
<line link="AccessType_SME" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }" conts="AccessType_SME">    <anchor link="AccessType_SME" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_SME</anchor>,     // Software SME load/store instructions</line>
<line link="AccessType_IC" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }" conts="AccessType_IC">    <anchor link="AccessType_IC" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</anchor>,      // Sysop IC</line>
<line link="AccessType_DC" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }" conts="AccessType_DC">    <anchor link="AccessType_DC" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</anchor>,      // Sysop DC (not DC {Z,G,GZ}VA)</line>
<line link="AccessType_DCZero" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }" conts="AccessType_DCZero">    <anchor link="AccessType_DCZero" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DCZero</anchor>,  // Sysop DC {Z,G,GZ}VA</line>
<line link="AccessType_AT" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }" conts="AccessType_AT">    <anchor link="AccessType_AT" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_AT</anchor>,      // Sysop AT</line>
<line link="AccessType_NV2" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }" conts="AccessType_NV2">    <anchor link="AccessType_NV2" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_NV2</anchor>,     // NV2 memory redirected access</line>
<line link="AccessType_SPE" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }" conts="AccessType_SPE">    <anchor link="AccessType_SPE" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_SPE</anchor>,     // Statistical Profiling buffer access</line>
<line link="AccessType_GCS" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }" conts="AccessType_GCS">    <anchor link="AccessType_GCS" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GCS</anchor>,     // Guarded Control Stack access</line>
<line link="AccessType_TRBE" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }" conts="AccessType_TRBE">    <anchor link="AccessType_TRBE" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_TRBE</anchor>,    // Trace Buffer access</line>
<line link="AccessType_GPTW" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }" conts="AccessType_GPTW">    <anchor link="AccessType_GPTW" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPTW</anchor>,    // Granule Protection Table Walk</line>
<line link="AccessType_TTW" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }" conts="AccessType_TTW">    <anchor link="AccessType_TTW" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_TTW</anchor>      // Translation Table Walk</line>
<line>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/AddrTop" mylink="shared.functions.memory.AddrTop" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AddrTop()</line>
<line>// =========</line>
<line>// Return the MSB number of a virtual address in the stage 1 translation regime for "el".</line>
<line>// If EL1 is using AArch64 then addresses from EL0 using AArch32 are zero-extended to 64 bits.</line>
<line></line>
<line link="impl-shared.AddrTop.3" hover="function: integer AddrTop(bits(64) address, boolean IsInstr, bits(2) el)" conts="AddrTop">integer <anchor link="impl-shared.AddrTop.3" hover="function: integer AddrTop(bits(64) address, boolean IsInstr, bits(2) el)">AddrTop</anchor>(bits(64) address, boolean IsInstr, bits(2) el)</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(el);</line>
<line>    regime = <a link="impl-shared.S1TranslationRegime.1" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime(bits(2) el)">S1TranslationRegime</a>(el);</line>
<line>    if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(regime) then</line>
<line>        // AArch32 translation regime.</line>
<line>        return 31;</line>
<line>    else</line>
<line>        if <a link="impl-shared.EffectiveTBI.3" file="shared_pseudocode.xml" hover="function: bit EffectiveTBI(bits(64) address, boolean IsInstr, bits(2) el)">EffectiveTBI</a>(address, IsInstr, el) == '1' then</line>
<line>            return 55;</line>
<line>        else</line>
<line>            return 63;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/AlignmentEnforced" mylink="shared.functions.memory.AlignmentEnforced" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AlignmentEnforced()</line>
<line>// ===================</line>
<line>// For the active translation regime, determine if alignment is required by all accesses</line>
<line></line>
<line link="impl-shared.AlignmentEnforced.0" hover="function: boolean AlignmentEnforced()" conts="AlignmentEnforced">boolean <anchor link="impl-shared.AlignmentEnforced.0" hover="function: boolean AlignmentEnforced()">AlignmentEnforced</anchor>()</line>
<line>    <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime = <a link="impl-shared.TranslationRegime.1" file="shared_pseudocode.xml" hover="function: Regime TranslationRegime(bits(2) el)">TranslationRegime</a>(PSTATE.EL);</line>
<line></line>
<line>    bit A;</line>
<line>    case regime of</line>
<line>        when <a link="Regime_EL3" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL3</a>  A = SCTLR_EL3.A;</line>
<line>        when <a link="Regime_EL30" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL30</a> A = SCTLR.A;</line>
<line>        when <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>  A = if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then HSCTLR.A else SCTLR_EL2.A;</line>
<line>        when <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a> A = SCTLR_EL2.A;</line>
<line>        when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> A = if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then SCTLR.A  else SCTLR_EL1.A;</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    return A == '1';</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/Allocation" mylink="shared.functions.memory.Allocation" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="MemHint_No" hover="constant bits(2) MemHint_No = '00'" conts="MemHint_No">constant bits(2) <anchor link="MemHint_No" hover="constant bits(2) MemHint_No = '00'">MemHint_No</anchor> = '00';     // No Read-Allocate, No Write-Allocate</line>
<line link="MemHint_WA" hover="constant bits(2) MemHint_WA = '01'" conts="MemHint_WA">constant bits(2) <anchor link="MemHint_WA" hover="constant bits(2) MemHint_WA = '01'">MemHint_WA</anchor> = '01';     // No Read-Allocate, Write-Allocate</line>
<line link="MemHint_RA" hover="constant bits(2) MemHint_RA = '10'" conts="MemHint_RA">constant bits(2) <anchor link="MemHint_RA" hover="constant bits(2) MemHint_RA = '10'">MemHint_RA</anchor> = '10';     // Read-Allocate, No Write-Allocate</line>
<line link="MemHint_RWA" hover="constant bits(2) MemHint_RWA = '11'" conts="MemHint_RWA">constant bits(2) <anchor link="MemHint_RWA" hover="constant bits(2) MemHint_RWA = '11'">MemHint_RWA</anchor> = '11';    // Read-Allocate, Write-Allocate</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/BigEndian" mylink="shared.functions.memory.BigEndian" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BigEndian()</line>
<line>// ===========</line>
<line></line>
<line link="impl-shared.BigEndian.1" hover="function: boolean BigEndian(AccessType acctype)" conts="BigEndian">boolean <anchor link="impl-shared.BigEndian.1" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</anchor>(<a link="AccessType" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType</a> acctype)</line>
<line>    boolean bigend;</line>
<line>    if <a link="impl-shared.HaveNV2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveNV2Ext()">HaveNV2Ext</a>() &amp;&amp; acctype == <a link="AccessType_NV2" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_NV2</a> then</line>
<line>        return SCTLR_EL2.EE == '1';</line>
<line></line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        bigend = (PSTATE.E != '0');</line>
<line>    elsif PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        bigend = (<a link="impl-aarch64.SCTLR.read.0" file="shared_pseudocode.xml" hover="accessor: SCTLRType SCTLR[]">SCTLR</a>[].E0E != '0');</line>
<line>    else</line>
<line>        bigend = (<a link="impl-aarch64.SCTLR.read.0" file="shared_pseudocode.xml" hover="accessor: SCTLRType SCTLR[]">SCTLR</a>[].EE != '0');</line>
<line>    return bigend;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/BigEndianReverse" mylink="shared.functions.memory.BigEndianReverse" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BigEndianReverse()</line>
<line>// ==================</line>
<line></line>
<line link="impl-shared.BigEndianReverse.1" hover="function: bits(width) BigEndianReverse (bits(width) value)" conts="BigEndianReverse">bits(width) <anchor link="impl-shared.BigEndianReverse.1" hover="function: bits(width) BigEndianReverse (bits(width) value)">BigEndianReverse</anchor> (bits(width) value)</line>
<line>    assert width IN {8, 16, 32, 64, 128};</line>
<line>    integer half = width DIV 2;</line>
<line>    if width == 8 then return value;</line>
<line>    return <a link="impl-shared.BigEndianReverse.1" file="shared_pseudocode.xml" hover="function: bits(width) BigEndianReverse (bits(width) value)">BigEndianReverse</a>(value&lt;half-1:0&gt;) : <a link="impl-shared.BigEndianReverse.1" file="shared_pseudocode.xml" hover="function: bits(width) BigEndianReverse (bits(width) value)">BigEndianReverse</a>(value&lt;width-1:half&gt;);</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/Cacheability" mylink="shared.functions.memory.Cacheability" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="MemAttr_NC" hover="constant bits(2) MemAttr_NC = '00'" conts="MemAttr_NC">constant bits(2) <anchor link="MemAttr_NC" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</anchor> = '00';     // Non-cacheable</line>
<line link="MemAttr_WT" hover="constant bits(2) MemAttr_WT = '10'" conts="MemAttr_WT">constant bits(2) <anchor link="MemAttr_WT" hover="constant bits(2) MemAttr_WT = '10'">MemAttr_WT</anchor> = '10';     // Write-through</line>
<line link="MemAttr_WB" hover="constant bits(2) MemAttr_WB = '11'" conts="MemAttr_WB">constant bits(2) <anchor link="MemAttr_WB" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</anchor> = '11';     // Write-back</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescA32LSMD" mylink="shared.functions.memory.CreateAccDescA32LSMD" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescA32LSMD()</line>
<line>// ======================</line>
<line>// Access descriptor for A32 loads/store multiple general purpose registers</line>
<line></line>
<line link="impl-shared.CreateAccDescA32LSMD.1" hover="function: AccessDescriptor CreateAccDescA32LSMD(MemOp memop)" conts="CreateAccDescA32LSMD">AccessDescriptor <anchor link="impl-shared.CreateAccDescA32LSMD.1" hover="function: AccessDescriptor CreateAccDescA32LSMD(MemOp memop)">CreateAccDescA32LSMD</anchor>(<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>);</line>
<line></line>
<line>    accdesc.read            = memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>;</line>
<line>    accdesc.write           = memop == <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;</line>
<line>    accdesc.pan             = TRUE;</line>
<line>    accdesc.a32lsmd         = TRUE;</line>
<line>    accdesc.transactional   = <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescASIMD" mylink="shared.functions.memory.CreateAccDescASIMD" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescASIMD()</line>
<line>// ====================</line>
<line>// Access descriptor for ASIMD&amp;FP loads/stores</line>
<line></line>
<line link="impl-shared.CreateAccDescASIMD.3" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)" conts="CreateAccDescASIMD">AccessDescriptor <anchor link="impl-shared.CreateAccDescASIMD.3" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</anchor>(<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop, boolean nontemporal, boolean tagchecked)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_ASIMD" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_ASIMD</a>);</line>
<line></line>
<line>    accdesc.nontemporal     = nontemporal;</line>
<line>    accdesc.read            = memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>;</line>
<line>    accdesc.write           = memop == <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;</line>
<line>    accdesc.pan             = TRUE;</line>
<line>    accdesc.streamingsve    = <a link="impl-aarch64.InStreamingMode.0" file="shared_pseudocode.xml" hover="function: boolean InStreamingMode()">InStreamingMode</a>();</line>
<line>    if (accdesc.streamingsve &amp;&amp; boolean IMPLEMENTATION_DEFINED</line>
<line>          "No tag checking of SIMD&amp;FP loads and stores in Streaming SVE mode") then</line>
<line>        accdesc.tagchecked  = FALSE;</line>
<line>    else</line>
<line>        accdesc.tagchecked  = tagchecked;</line>
<line>    accdesc.transactional   = <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescASIMDAcqRel" mylink="shared.functions.memory.CreateAccDescASIMDAcqRel" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescASIMDAcqRel()</line>
<line>// ==========================</line>
<line>// Access descriptor for ASIMD&amp;FP loads/stores with ordering semantics</line>
<line></line>
<line link="impl-shared.CreateAccDescASIMDAcqRel.2" hover="function: AccessDescriptor CreateAccDescASIMDAcqRel(MemOp memop, boolean tagchecked)" conts="CreateAccDescASIMDAcqRel">AccessDescriptor <anchor link="impl-shared.CreateAccDescASIMDAcqRel.2" hover="function: AccessDescriptor CreateAccDescASIMDAcqRel(MemOp memop, boolean tagchecked)">CreateAccDescASIMDAcqRel</anchor>(<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop, boolean tagchecked)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_ASIMD" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_ASIMD</a>);</line>
<line></line>
<line>    accdesc.acqpc           = memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>;</line>
<line>    accdesc.relsc           = memop == <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;</line>
<line>    accdesc.read            = memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>;</line>
<line>    accdesc.write           = memop == <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;</line>
<line>    accdesc.pan             = TRUE;</line>
<line>    accdesc.streamingsve    = <a link="impl-aarch64.InStreamingMode.0" file="shared_pseudocode.xml" hover="function: boolean InStreamingMode()">InStreamingMode</a>();</line>
<line>    if (accdesc.streamingsve &amp;&amp; boolean IMPLEMENTATION_DEFINED</line>
<line>          "No tag checking of SIMD&amp;FP loads and stores in Streaming SVE mode") then</line>
<line>        accdesc.tagchecked  = FALSE;</line>
<line>    else</line>
<line>        accdesc.tagchecked  = tagchecked;</line>
<line>    accdesc.transactional   = <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescAT" mylink="shared.functions.memory.CreateAccDescAT" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescAT()</line>
<line>// =================</line>
<line>// Access descriptor for address translation operations</line>
<line></line>
<line link="impl-shared.CreateAccDescAT.4" hover="function: AccessDescriptor CreateAccDescAT(SecurityState ss, bits(2) el, boolean write, boolean pan)" conts="CreateAccDescAT">AccessDescriptor <anchor link="impl-shared.CreateAccDescAT.4" hover="function: AccessDescriptor CreateAccDescAT(SecurityState ss, bits(2) el, boolean write, boolean pan)">CreateAccDescAT</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss, bits(2) el, boolean write, boolean pan)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_AT" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_AT</a>);</line>
<line></line>
<line>    accdesc.el              = el;</line>
<line>    accdesc.ss              = ss;</line>
<line>    accdesc.read            = !write;</line>
<line>    accdesc.write           = write;</line>
<line>    accdesc.pan             = pan;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescAcqRel" mylink="shared.functions.memory.CreateAccDescAcqRel" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescAcqRel()</line>
<line>// =====================</line>
<line>// Access descriptor for general purpose register loads/stores with ordering semantics</line>
<line></line>
<line link="impl-shared.CreateAccDescAcqRel.2" hover="function: AccessDescriptor CreateAccDescAcqRel(MemOp memop, boolean tagchecked)" conts="CreateAccDescAcqRel">AccessDescriptor <anchor link="impl-shared.CreateAccDescAcqRel.2" hover="function: AccessDescriptor CreateAccDescAcqRel(MemOp memop, boolean tagchecked)">CreateAccDescAcqRel</anchor>(<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop, boolean tagchecked)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>);</line>
<line></line>
<line>    accdesc.acqsc           = memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>;</line>
<line>    accdesc.relsc           = memop == <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;</line>
<line>    accdesc.read            = memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>;</line>
<line>    accdesc.write           = memop == <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;</line>
<line>    accdesc.pan             = TRUE;</line>
<line>    accdesc.tagchecked      = tagchecked;</line>
<line>    accdesc.transactional   = <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescAtomicOp" mylink="shared.functions.memory.CreateAccDescAtomicOp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescAtomicOp()</line>
<line>// =======================</line>
<line>// Access descriptor for atomic read-modify-write memory accesses</line>
<line></line>
<line link="impl-shared.CreateAccDescAtomicOp.4" hover="function: AccessDescriptor CreateAccDescAtomicOp(MemAtomicOp modop, boolean acquire, boolean release, boolean tagchecked)" conts="CreateAccDescAtomicOp">AccessDescriptor <anchor link="impl-shared.CreateAccDescAtomicOp.4" hover="function: AccessDescriptor CreateAccDescAtomicOp(MemAtomicOp modop, boolean acquire, boolean release, boolean tagchecked)">CreateAccDescAtomicOp</anchor>(<a link="MemAtomicOp" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp</a> modop, boolean acquire, boolean release,</line>
<line>                                       boolean tagchecked)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>);</line>
<line></line>
<line>    accdesc.acqsc           = acquire;</line>
<line>    accdesc.relsc           = release;</line>
<line>    accdesc.atomicop        = TRUE;</line>
<line>    accdesc.modop           = modop;</line>
<line>    accdesc.read            = TRUE;</line>
<line>    accdesc.write           = TRUE;</line>
<line>    accdesc.pan             = TRUE;</line>
<line>    accdesc.tagchecked      = tagchecked;</line>
<line>    accdesc.transactional   = <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescDC" mylink="shared.functions.memory.CreateAccDescDC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescDC()</line>
<line>// =================</line>
<line>// Access descriptor for data cache operations</line>
<line></line>
<line link="impl-shared.CreateAccDescDC.1" hover="function: AccessDescriptor CreateAccDescDC(CacheRecord cache)" conts="CreateAccDescDC">AccessDescriptor <anchor link="impl-shared.CreateAccDescDC.1" hover="function: AccessDescriptor CreateAccDescDC(CacheRecord cache)">CreateAccDescDC</anchor>(<a link="CacheRecord" file="shared_pseudocode.xml" hover="type CacheRecord is ( AccessType acctype, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, bits(64) regval, FullAddress paddress, bits(64) vaddress, integer set, integer way, integer level, Shareability shareability, boolean translated, boolean is_vmid_valid, bits(16) vmid, boolean is_asid_valid, bits(16) asid, SecurityState security, CachePASpace cpas )">CacheRecord</a> cache)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>);</line>
<line></line>
<line>    accdesc.cacheop         = cache.cacheop;</line>
<line>    accdesc.cachetype       = cache.cachetype;</line>
<line>    accdesc.opscope         = cache.opscope;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescDCZero" mylink="shared.functions.memory.CreateAccDescDCZero" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescDCZero()</line>
<line>// =====================</line>
<line>// Access descriptor for data cache zero operations</line>
<line></line>
<line link="impl-shared.CreateAccDescDCZero.2" hover="function: AccessDescriptor CreateAccDescDCZero(boolean tagaccess, boolean tagchecked)" conts="CreateAccDescDCZero">AccessDescriptor <anchor link="impl-shared.CreateAccDescDCZero.2" hover="function: AccessDescriptor CreateAccDescDCZero(boolean tagaccess, boolean tagchecked)">CreateAccDescDCZero</anchor>(boolean tagaccess, boolean tagchecked)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_DCZero" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DCZero</a>);</line>
<line></line>
<line>    accdesc.write           = TRUE;</line>
<line>    accdesc.pan             = TRUE;</line>
<line>    accdesc.tagchecked      = tagchecked;</line>
<line>    accdesc.tagaccess       = tagaccess;</line>
<line>    accdesc.transactional   = <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescExLDST" mylink="shared.functions.memory.CreateAccDescExLDST" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescExLDST()</line>
<line>// =====================</line>
<line>// Access descriptor for general purpose register loads/stores with exclusive semantics</line>
<line></line>
<line link="impl-shared.CreateAccDescExLDST.3" hover="function: AccessDescriptor CreateAccDescExLDST(MemOp memop, boolean acqrel, boolean tagchecked)" conts="CreateAccDescExLDST">AccessDescriptor <anchor link="impl-shared.CreateAccDescExLDST.3" hover="function: AccessDescriptor CreateAccDescExLDST(MemOp memop, boolean acqrel, boolean tagchecked)">CreateAccDescExLDST</anchor>(<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop, boolean acqrel, boolean tagchecked)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>);</line>
<line></line>
<line>    accdesc.acqsc           = acqrel &amp;&amp; memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>;</line>
<line>    accdesc.relsc           = acqrel &amp;&amp; memop == <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;</line>
<line>    accdesc.exclusive       = TRUE;</line>
<line>    accdesc.read            = memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>;</line>
<line>    accdesc.write           = memop == <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;</line>
<line>    accdesc.pan             = TRUE;</line>
<line>    accdesc.tagchecked      = tagchecked;</line>
<line>    accdesc.transactional   = <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescGCS" mylink="shared.functions.memory.CreateAccDescGCS" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescGCS()</line>
<line>// ==================</line>
<line>// Access descriptor for memory accesses to the Guarded Control Stack</line>
<line></line>
<line link="impl-shared.CreateAccDescGCS.2" hover="function: AccessDescriptor CreateAccDescGCS(bits(2) el, MemOp memop)" conts="CreateAccDescGCS">AccessDescriptor <anchor link="impl-shared.CreateAccDescGCS.2" hover="function: AccessDescriptor CreateAccDescGCS(bits(2) el, MemOp memop)">CreateAccDescGCS</anchor>(bits(2) el, <a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_GCS" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GCS</a>);</line>
<line></line>
<line>    accdesc.el              = el;</line>
<line>    accdesc.read            = memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>;</line>
<line>    accdesc.write           = memop == <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescGCSSS1" mylink="shared.functions.memory.CreateAccDescGCSSS1" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescGCSSS1()</line>
<line>// =====================</line>
<line>// Access descriptor for memory accesses to the Guarded Control Stack that switch stacks</line>
<line></line>
<line link="impl-shared.CreateAccDescGCSSS1.1" hover="function: AccessDescriptor CreateAccDescGCSSS1(bits(2) el)" conts="CreateAccDescGCSSS1">AccessDescriptor <anchor link="impl-shared.CreateAccDescGCSSS1.1" hover="function: AccessDescriptor CreateAccDescGCSSS1(bits(2) el)">CreateAccDescGCSSS1</anchor>(bits(2) el)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_GCS" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GCS</a>);</line>
<line></line>
<line>    accdesc.el              = el;</line>
<line>    accdesc.atomicop        = TRUE;</line>
<line>    accdesc.modop           = <a link="MemAtomicOp_GCSSS1" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_GCSSS1</a>;</line>
<line>    accdesc.read            = TRUE;</line>
<line>    accdesc.write           = TRUE;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescGPR" mylink="shared.functions.memory.CreateAccDescGPR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescGPR()</line>
<line>// ==================</line>
<line>// Access descriptor for general purpose register loads/stores</line>
<line>// without exclusive or ordering semantics</line>
<line></line>
<line link="impl-shared.CreateAccDescGPR.4" hover="function: AccessDescriptor CreateAccDescGPR(MemOp memop, boolean nontemporal, boolean privileged, boolean tagchecked)" conts="CreateAccDescGPR">AccessDescriptor <anchor link="impl-shared.CreateAccDescGPR.4" hover="function: AccessDescriptor CreateAccDescGPR(MemOp memop, boolean nontemporal, boolean privileged, boolean tagchecked)">CreateAccDescGPR</anchor>(<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop, boolean nontemporal, boolean privileged,</line>
<line>                                  boolean tagchecked)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>);</line>
<line></line>
<line>    accdesc.el              = if !privileged then <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> else PSTATE.EL;</line>
<line>    accdesc.nontemporal     = nontemporal;</line>
<line>    accdesc.read            = memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>;</line>
<line>    accdesc.write           = memop == <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;</line>
<line>    accdesc.pan             = TRUE;</line>
<line>    accdesc.tagchecked      = tagchecked;</line>
<line>    accdesc.transactional   = <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescGPTW" mylink="shared.functions.memory.CreateAccDescGPTW" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescGPTW()</line>
<line>// ===================</line>
<line>// Access descriptor for Granule Protection Table walks</line>
<line></line>
<line link="impl-shared.CreateAccDescGPTW.1" hover="function: AccessDescriptor CreateAccDescGPTW(AccessDescriptor accdesc_in)" conts="CreateAccDescGPTW">AccessDescriptor <anchor link="impl-shared.CreateAccDescGPTW.1" hover="function: AccessDescriptor CreateAccDescGPTW(AccessDescriptor accdesc_in)">CreateAccDescGPTW</anchor>(<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc_in)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_GPTW" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPTW</a>);</line>
<line></line>
<line>    accdesc.el              = accdesc_in.el;</line>
<line>    accdesc.ss              = accdesc_in.ss;</line>
<line>    accdesc.read            = TRUE;</line>
<line>    accdesc.mpam            = accdesc_in.mpam;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescIC" mylink="shared.functions.memory.CreateAccDescIC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescIC()</line>
<line>// =================</line>
<line>// Access descriptor for instruction cache operations</line>
<line></line>
<line link="impl-shared.CreateAccDescIC.1" hover="function: AccessDescriptor CreateAccDescIC(CacheRecord cache)" conts="CreateAccDescIC">AccessDescriptor <anchor link="impl-shared.CreateAccDescIC.1" hover="function: AccessDescriptor CreateAccDescIC(CacheRecord cache)">CreateAccDescIC</anchor>(<a link="CacheRecord" file="shared_pseudocode.xml" hover="type CacheRecord is ( AccessType acctype, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, bits(64) regval, FullAddress paddress, bits(64) vaddress, integer set, integer way, integer level, Shareability shareability, boolean translated, boolean is_vmid_valid, bits(16) vmid, boolean is_asid_valid, bits(16) asid, SecurityState security, CachePASpace cpas )">CacheRecord</a> cache)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a>);</line>
<line></line>
<line>    accdesc.cacheop         = cache.cacheop;</line>
<line>    accdesc.cachetype       = cache.cachetype;</line>
<line>    accdesc.opscope         = cache.opscope;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescIFetch" mylink="shared.functions.memory.CreateAccDescIFetch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescIFetch()</line>
<line>// =====================</line>
<line>// Access descriptor for instruction fetches</line>
<line></line>
<line link="impl-shared.CreateAccDescIFetch.0" hover="function: AccessDescriptor CreateAccDescIFetch()" conts="CreateAccDescIFetch">AccessDescriptor <anchor link="impl-shared.CreateAccDescIFetch.0" hover="function: AccessDescriptor CreateAccDescIFetch()">CreateAccDescIFetch</anchor>()</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a>);</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescLDAcqPC" mylink="shared.functions.memory.CreateAccDescLDAcqPC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescLDAcqPC()</line>
<line>// ======================</line>
<line>// Access descriptor for general purpose register loads with local ordering semantics</line>
<line></line>
<line link="impl-shared.CreateAccDescLDAcqPC.1" hover="function: AccessDescriptor CreateAccDescLDAcqPC(boolean tagchecked)" conts="CreateAccDescLDAcqPC">AccessDescriptor <anchor link="impl-shared.CreateAccDescLDAcqPC.1" hover="function: AccessDescriptor CreateAccDescLDAcqPC(boolean tagchecked)">CreateAccDescLDAcqPC</anchor>(boolean tagchecked)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>);</line>
<line></line>
<line>    accdesc.acqpc           = TRUE;</line>
<line>    accdesc.read            = TRUE;</line>
<line>    accdesc.pan             = TRUE;</line>
<line>    accdesc.tagchecked      = tagchecked;</line>
<line>    accdesc.transactional   = <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescLDGSTG" mylink="shared.functions.memory.CreateAccDescLDGSTG" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescLDGSTG()</line>
<line>// =====================</line>
<line>// Access descriptor for tag memory loads/stores</line>
<line></line>
<line link="impl-shared.CreateAccDescLDGSTG.1" hover="function: AccessDescriptor CreateAccDescLDGSTG(MemOp memop)" conts="CreateAccDescLDGSTG">AccessDescriptor <anchor link="impl-shared.CreateAccDescLDGSTG.1" hover="function: AccessDescriptor CreateAccDescLDGSTG(MemOp memop)">CreateAccDescLDGSTG</anchor>(<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>);</line>
<line></line>
<line>    accdesc.read            = memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>;</line>
<line>    accdesc.write           = memop == <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;</line>
<line>    accdesc.pan             = TRUE;</line>
<line>    accdesc.tagaccess       = TRUE;</line>
<line>    accdesc.transactional   = <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescLOR" mylink="shared.functions.memory.CreateAccDescLOR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescLOR()</line>
<line>// ==================</line>
<line>// Access descriptor for general purpose register loads/stores with limited ordering semantics</line>
<line></line>
<line link="impl-shared.CreateAccDescLOR.2" hover="function: AccessDescriptor CreateAccDescLOR(MemOp memop, boolean tagchecked)" conts="CreateAccDescLOR">AccessDescriptor <anchor link="impl-shared.CreateAccDescLOR.2" hover="function: AccessDescriptor CreateAccDescLOR(MemOp memop, boolean tagchecked)">CreateAccDescLOR</anchor>(<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop, boolean tagchecked)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>);</line>
<line></line>
<line>    accdesc.acqsc           = memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>;</line>
<line>    accdesc.relsc           = memop == <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;</line>
<line>    accdesc.limitedordered  = TRUE;</line>
<line>    accdesc.read            = memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>;</line>
<line>    accdesc.write           = memop == <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;</line>
<line>    accdesc.pan             = TRUE;</line>
<line>    accdesc.tagchecked      = tagchecked;</line>
<line>    accdesc.transactional   = <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescLS64" mylink="shared.functions.memory.CreateAccDescLS64" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescLS64()</line>
<line>// ===================</line>
<line>// Access descriptor for accelerator-supporting memory accesses</line>
<line></line>
<line link="impl-shared.CreateAccDescLS64.2" hover="function: AccessDescriptor CreateAccDescLS64(MemOp memop, boolean tagchecked)" conts="CreateAccDescLS64">AccessDescriptor <anchor link="impl-shared.CreateAccDescLS64.2" hover="function: AccessDescriptor CreateAccDescLS64(MemOp memop, boolean tagchecked)">CreateAccDescLS64</anchor>(<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop, boolean tagchecked)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>);</line>
<line></line>
<line>    accdesc.read            = memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>;</line>
<line>    accdesc.write           = memop == <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;</line>
<line>    accdesc.pan             = TRUE;</line>
<line>    accdesc.ls64            = TRUE;</line>
<line>    accdesc.tagchecked      = tagchecked;</line>
<line>    accdesc.transactional   = <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescMOPS" mylink="shared.functions.memory.CreateAccDescMOPS" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescMOPS()</line>
<line>// ===================</line>
<line>// Access descriptor for data memory copy and set instructions</line>
<line></line>
<line link="impl-shared.CreateAccDescMOPS.3" hover="function: AccessDescriptor CreateAccDescMOPS(MemOp memop, boolean privileged, boolean nontemporal)" conts="CreateAccDescMOPS">AccessDescriptor <anchor link="impl-shared.CreateAccDescMOPS.3" hover="function: AccessDescriptor CreateAccDescMOPS(MemOp memop, boolean privileged, boolean nontemporal)">CreateAccDescMOPS</anchor>(<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop, boolean privileged, boolean nontemporal)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>);</line>
<line></line>
<line>    accdesc.el              = if !privileged then <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> else PSTATE.EL;</line>
<line>    accdesc.nontemporal     = nontemporal;</line>
<line>    accdesc.read            = memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>;</line>
<line>    accdesc.write           = memop == <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;</line>
<line>    accdesc.pan             = TRUE;</line>
<line>    accdesc.mops            = TRUE;</line>
<line>    accdesc.tagchecked      = TRUE;</line>
<line>    accdesc.transactional   = <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescNV2" mylink="shared.functions.memory.CreateAccDescNV2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescNV2()</line>
<line>// ==================</line>
<line>// Access descriptor nested virtualization memory indirection loads/stores</line>
<line></line>
<line link="impl-shared.CreateAccDescNV2.1" hover="function: AccessDescriptor CreateAccDescNV2(MemOp memop)" conts="CreateAccDescNV2">AccessDescriptor <anchor link="impl-shared.CreateAccDescNV2.1" hover="function: AccessDescriptor CreateAccDescNV2(MemOp memop)">CreateAccDescNV2</anchor>(<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_NV2" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_NV2</a>);</line>
<line></line>
<line>    accdesc.el              = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>    accdesc.ss              = <a link="impl-shared.SecurityStateAtEL.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)">SecurityStateAtEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>    accdesc.read            = memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>;</line>
<line>    accdesc.write           = memop == <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;</line>
<line>    accdesc.transactional   = <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescRCW" mylink="shared.functions.memory.CreateAccDescRCW" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescRCW()</line>
<line>// ==================</line>
<line>// Access descriptor for atomic read-check-write memory accesses</line>
<line></line>
<line link="impl-shared.CreateAccDescRCW.5" hover="function: AccessDescriptor CreateAccDescRCW(MemAtomicOp modop, boolean soft, boolean acquire, boolean release, boolean tagchecked)" conts="CreateAccDescRCW">AccessDescriptor <anchor link="impl-shared.CreateAccDescRCW.5" hover="function: AccessDescriptor CreateAccDescRCW(MemAtomicOp modop, boolean soft, boolean acquire, boolean release, boolean tagchecked)">CreateAccDescRCW</anchor>(<a link="MemAtomicOp" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp</a> modop, boolean soft, boolean acquire,</line>
<line>                                  boolean release, boolean tagchecked)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>);</line>
<line></line>
<line>    accdesc.acqsc           = acquire;</line>
<line>    accdesc.relsc           = release;</line>
<line>    accdesc.rcw             = TRUE;</line>
<line>    accdesc.rcws            = soft;</line>
<line>    accdesc.atomicop        = TRUE;</line>
<line>    accdesc.modop           = modop;</line>
<line>    accdesc.read            = TRUE;</line>
<line>    accdesc.write           = TRUE;</line>
<line>    accdesc.pan             = TRUE;</line>
<line>    accdesc.tagchecked      = tagchecked;</line>
<line>    accdesc.transactional   = <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescS1TTW" mylink="shared.functions.memory.CreateAccDescS1TTW" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescS1TTW()</line>
<line>// ====================</line>
<line>// Access descriptor for stage 1 translation table walks</line>
<line></line>
<line link="impl-shared.CreateAccDescS1TTW.3" hover="function: AccessDescriptor CreateAccDescS1TTW(boolean toplevel, VARange varange, AccessDescriptor accdesc_in)" conts="CreateAccDescS1TTW">AccessDescriptor <anchor link="impl-shared.CreateAccDescS1TTW.3" hover="function: AccessDescriptor CreateAccDescS1TTW(boolean toplevel, VARange varange, AccessDescriptor accdesc_in)">CreateAccDescS1TTW</anchor>(boolean toplevel, <a link="VARange" file="shared_pseudocode.xml" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange</a> varange, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc_in)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_TTW" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_TTW</a>);</line>
<line></line>
<line>    accdesc.el              = accdesc_in.el;</line>
<line>    accdesc.ss              = accdesc_in.ss;</line>
<line>    accdesc.read            = TRUE;</line>
<line>    accdesc.toplevel        = toplevel;</line>
<line>    accdesc.varange         = varange;</line>
<line>    accdesc.mpam            = accdesc_in.mpam;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescS2TTW" mylink="shared.functions.memory.CreateAccDescS2TTW" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescS2TTW()</line>
<line>// ====================</line>
<line>// Access descriptor for stage 2 translation table walks</line>
<line></line>
<line link="impl-shared.CreateAccDescS2TTW.1" hover="function: AccessDescriptor CreateAccDescS2TTW(AccessDescriptor accdesc_in)" conts="CreateAccDescS2TTW">AccessDescriptor <anchor link="impl-shared.CreateAccDescS2TTW.1" hover="function: AccessDescriptor CreateAccDescS2TTW(AccessDescriptor accdesc_in)">CreateAccDescS2TTW</anchor>(<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc_in)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_TTW" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_TTW</a>);</line>
<line></line>
<line>    accdesc.el              = accdesc_in.el;</line>
<line>    accdesc.ss              = accdesc_in.ss;</line>
<line>    accdesc.read            = TRUE;</line>
<line>    accdesc.mpam            = accdesc_in.mpam;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescSME" mylink="shared.functions.memory.CreateAccDescSME" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescSME()</line>
<line>// ==================</line>
<line>// Access descriptor for SME loads/stores</line>
<line></line>
<line link="impl-shared.CreateAccDescSME.4" hover="function: AccessDescriptor CreateAccDescSME(MemOp memop, boolean nontemporal, boolean contiguous, boolean tagchecked)" conts="CreateAccDescSME">AccessDescriptor <anchor link="impl-shared.CreateAccDescSME.4" hover="function: AccessDescriptor CreateAccDescSME(MemOp memop, boolean nontemporal, boolean contiguous, boolean tagchecked)">CreateAccDescSME</anchor>(<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop, boolean nontemporal, boolean contiguous,</line>
<line>                                  boolean tagchecked)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_SME" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_SME</a>);</line>
<line></line>
<line>    accdesc.nontemporal     = nontemporal;</line>
<line>    accdesc.read            = memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>;</line>
<line>    accdesc.write           = memop == <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;</line>
<line>    accdesc.pan             = TRUE;</line>
<line>    accdesc.contiguous      = contiguous;</line>
<line>    accdesc.streamingsve    = TRUE;</line>
<line>    if boolean IMPLEMENTATION_DEFINED "No tag checking of SME LDR &amp; STR instructions" then</line>
<line>        accdesc.tagchecked  = FALSE;</line>
<line>    else</line>
<line>        accdesc.tagchecked  = tagchecked;</line>
<line>    accdesc.transactional   = <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescSPE" mylink="shared.functions.memory.CreateAccDescSPE" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescSPE()</line>
<line>// ==================</line>
<line>// Access descriptor for memory accesses by Statistical Profiling unit</line>
<line></line>
<line link="impl-shared.CreateAccDescSPE.2" hover="function: AccessDescriptor CreateAccDescSPE(SecurityState owning_ss, bits(2) owning_el)" conts="CreateAccDescSPE">AccessDescriptor <anchor link="impl-shared.CreateAccDescSPE.2" hover="function: AccessDescriptor CreateAccDescSPE(SecurityState owning_ss, bits(2) owning_el)">CreateAccDescSPE</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> owning_ss, bits(2) owning_el)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_SPE" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_SPE</a>);</line>
<line></line>
<line>    accdesc.el              = owning_el;</line>
<line>    accdesc.ss              = owning_ss;</line>
<line>    accdesc.write           = TRUE;</line>
<line>    accdesc.mpam            = <a link="impl-shared.GenMPAMatEL.2" file="shared_pseudocode.xml" hover="function: MPAMinfo GenMPAMatEL(AccessType acctype, bits(2) el)">GenMPAMatEL</a>(<a link="AccessType_SPE" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_SPE</a>, owning_el);</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescSTGMOPS" mylink="shared.functions.memory.CreateAccDescSTGMOPS" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescSTGMOPS()</line>
<line>// ======================</line>
<line>// Access descriptor for tag memory set instructions</line>
<line></line>
<line link="impl-shared.CreateAccDescSTGMOPS.2" hover="function: AccessDescriptor CreateAccDescSTGMOPS(boolean privileged, boolean nontemporal)" conts="CreateAccDescSTGMOPS">AccessDescriptor <anchor link="impl-shared.CreateAccDescSTGMOPS.2" hover="function: AccessDescriptor CreateAccDescSTGMOPS(boolean privileged, boolean nontemporal)">CreateAccDescSTGMOPS</anchor>(boolean privileged, boolean nontemporal)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>);</line>
<line></line>
<line>    accdesc.el              = if !privileged then <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> else PSTATE.EL;</line>
<line>    accdesc.nontemporal     = nontemporal;</line>
<line>    accdesc.write           = TRUE;</line>
<line>    accdesc.pan             = TRUE;</line>
<line>    accdesc.mops            = TRUE;</line>
<line>    accdesc.tagaccess       = TRUE;</line>
<line>    accdesc.transactional   = <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescSVE" mylink="shared.functions.memory.CreateAccDescSVE" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescSVE()</line>
<line>// ==================</line>
<line>// Access descriptor for general SVE loads/stores</line>
<line></line>
<line link="impl-shared.CreateAccDescSVE.4" hover="function: AccessDescriptor CreateAccDescSVE(MemOp memop, boolean nontemporal, boolean contiguous, boolean tagchecked)" conts="CreateAccDescSVE">AccessDescriptor <anchor link="impl-shared.CreateAccDescSVE.4" hover="function: AccessDescriptor CreateAccDescSVE(MemOp memop, boolean nontemporal, boolean contiguous, boolean tagchecked)">CreateAccDescSVE</anchor>(<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop, boolean nontemporal, boolean contiguous,</line>
<line>                                  boolean tagchecked)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_SVE" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_SVE</a>);</line>
<line></line>
<line>    accdesc.nontemporal     = nontemporal;</line>
<line>    accdesc.read            = memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>;</line>
<line>    accdesc.write           = memop == <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;</line>
<line>    accdesc.pan             = TRUE;</line>
<line>    accdesc.contiguous      = contiguous;</line>
<line>    accdesc.streamingsve    = <a link="impl-aarch64.InStreamingMode.0" file="shared_pseudocode.xml" hover="function: boolean InStreamingMode()">InStreamingMode</a>();</line>
<line>    if (accdesc.streamingsve &amp;&amp; boolean IMPLEMENTATION_DEFINED</line>
<line>          "No tag checking of SIMD&amp;FP loads and stores in Streaming SVE mode") then</line>
<line>        accdesc.tagchecked  = FALSE;</line>
<line>    else</line>
<line>        accdesc.tagchecked  = tagchecked;</line>
<line>    accdesc.transactional   = <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescSVEFF" mylink="shared.functions.memory.CreateAccDescSVEFF" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescSVEFF()</line>
<line>// ====================</line>
<line>// Access descriptor for first-fault SVE loads</line>
<line></line>
<line link="impl-shared.CreateAccDescSVEFF.2" hover="function: AccessDescriptor CreateAccDescSVEFF(boolean contiguous, boolean tagchecked)" conts="CreateAccDescSVEFF">AccessDescriptor <anchor link="impl-shared.CreateAccDescSVEFF.2" hover="function: AccessDescriptor CreateAccDescSVEFF(boolean contiguous, boolean tagchecked)">CreateAccDescSVEFF</anchor>(boolean contiguous, boolean tagchecked)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_SVE" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_SVE</a>);</line>
<line></line>
<line>    accdesc.read            = TRUE;</line>
<line>    accdesc.pan             = TRUE;</line>
<line>    accdesc.firstfault      = TRUE;</line>
<line>    accdesc.first           = TRUE;</line>
<line>    accdesc.contiguous      = contiguous;</line>
<line>    accdesc.streamingsve    = <a link="impl-aarch64.InStreamingMode.0" file="shared_pseudocode.xml" hover="function: boolean InStreamingMode()">InStreamingMode</a>();</line>
<line>    if (accdesc.streamingsve &amp;&amp; boolean IMPLEMENTATION_DEFINED</line>
<line>          "No tag checking of SIMD&amp;FP loads and stores in Streaming SVE mode") then</line>
<line>        accdesc.tagchecked  = FALSE;</line>
<line>    else</line>
<line>        accdesc.tagchecked  = tagchecked;</line>
<line>    accdesc.transactional   = <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescSVENF" mylink="shared.functions.memory.CreateAccDescSVENF" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescSVENF()</line>
<line>// ====================</line>
<line>// Access descriptor for non-fault SVE loads</line>
<line></line>
<line link="impl-shared.CreateAccDescSVENF.2" hover="function: AccessDescriptor CreateAccDescSVENF(boolean contiguous, boolean tagchecked)" conts="CreateAccDescSVENF">AccessDescriptor <anchor link="impl-shared.CreateAccDescSVENF.2" hover="function: AccessDescriptor CreateAccDescSVENF(boolean contiguous, boolean tagchecked)">CreateAccDescSVENF</anchor>(boolean contiguous, boolean tagchecked)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_SVE" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_SVE</a>);</line>
<line></line>
<line>    accdesc.read            = TRUE;</line>
<line>    accdesc.pan             = TRUE;</line>
<line>    accdesc.nonfault        = TRUE;</line>
<line>    accdesc.contiguous      = contiguous;</line>
<line>    accdesc.streamingsve    = <a link="impl-aarch64.InStreamingMode.0" file="shared_pseudocode.xml" hover="function: boolean InStreamingMode()">InStreamingMode</a>();</line>
<line>    if (accdesc.streamingsve &amp;&amp; boolean IMPLEMENTATION_DEFINED</line>
<line>          "No tag checking of SIMD&amp;FP loads and stores in Streaming SVE mode") then</line>
<line>        accdesc.tagchecked  = FALSE;</line>
<line>    else</line>
<line>        accdesc.tagchecked  = tagchecked;</line>
<line>    accdesc.transactional   = <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescTRBE" mylink="shared.functions.memory.CreateAccDescTRBE" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescTRBE()</line>
<line>// ===================</line>
<line>// Access descriptor for memory accesses by Trace Buffer Unit</line>
<line></line>
<line link="impl-shared.CreateAccDescTRBE.2" hover="function: AccessDescriptor CreateAccDescTRBE(SecurityState owning_ss, bits(2) owning_el)" conts="CreateAccDescTRBE">AccessDescriptor <anchor link="impl-shared.CreateAccDescTRBE.2" hover="function: AccessDescriptor CreateAccDescTRBE(SecurityState owning_ss, bits(2) owning_el)">CreateAccDescTRBE</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> owning_ss, bits(2) owning_el)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_TRBE" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_TRBE</a>);</line>
<line></line>
<line>    accdesc.el              = owning_el;</line>
<line>    accdesc.ss              = owning_ss;</line>
<line>    accdesc.write           = TRUE;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/CreateAccDescTTEUpdate" mylink="shared.functions.memory.CreateAccDescTTEUpdate" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAccDescTTEUpdate()</line>
<line>// ========================</line>
<line>// Access descriptor for translation table entry HW update</line>
<line></line>
<line link="impl-shared.CreateAccDescTTEUpdate.1" hover="function: AccessDescriptor CreateAccDescTTEUpdate(AccessDescriptor accdesc_in)" conts="CreateAccDescTTEUpdate">AccessDescriptor <anchor link="impl-shared.CreateAccDescTTEUpdate.1" hover="function: AccessDescriptor CreateAccDescTTEUpdate(AccessDescriptor accdesc_in)">CreateAccDescTTEUpdate</anchor>(<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc_in)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.NewAccDesc.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</a>(<a link="AccessType_TTW" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_TTW</a>);</line>
<line></line>
<line>    accdesc.el              = accdesc_in.el;</line>
<line>    accdesc.ss              = accdesc_in.ss;</line>
<line>    accdesc.atomicop        = TRUE;</line>
<line>    accdesc.modop           = <a link="MemAtomicOp_CAS" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_CAS</a>;</line>
<line>    accdesc.read            = TRUE;</line>
<line>    accdesc.write           = TRUE;</line>
<line>    accdesc.mpam            = accdesc_in.mpam;</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/DataMemoryBarrier" mylink="shared.functions.memory.DataMemoryBarrier" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DataMemoryBarrier()</line>
<line>// ===================</line>
<line></line>
<line link="impl-shared.DataMemoryBarrier.2" hover="function: DataMemoryBarrier(MBReqDomain domain, MBReqTypes types)" conts="DataMemoryBarrier"><anchor link="impl-shared.DataMemoryBarrier.2" hover="function: DataMemoryBarrier(MBReqDomain domain, MBReqTypes types)">DataMemoryBarrier</anchor>(<a link="MBReqDomain" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain</a> domain, <a link="MBReqTypes" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes</a> types);</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/DataSynchronizationBarrier" mylink="shared.functions.memory.DataSynchronizationBarrier" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DataSynchronizationBarrier()</line>
<line>// ============================</line>
<line></line>
<line link="impl-shared.DataSynchronizationBarrier.3" hover="function: DataSynchronizationBarrier(MBReqDomain domain, MBReqTypes types, boolean nXS)" conts="DataSynchronizationBarrier"><anchor link="impl-shared.DataSynchronizationBarrier.3" hover="function: DataSynchronizationBarrier(MBReqDomain domain, MBReqTypes types, boolean nXS)">DataSynchronizationBarrier</anchor>(<a link="MBReqDomain" file="shared_pseudocode.xml" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain</a> domain, <a link="MBReqTypes" file="shared_pseudocode.xml" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes</a> types, boolean nXS);</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/DeviceType" mylink="shared.functions.memory.DeviceType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DeviceType</line>
<line>// ==========</line>
<line>// Extended memory types for Device memory.</line>
<line></line>
<line link="DeviceType" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}" conts="DeviceType">enumeration <anchor link="DeviceType" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType</anchor> {<anchor link="DeviceType_GRE" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_GRE</anchor>, <anchor link="DeviceType_nGRE" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGRE</anchor>, <anchor link="DeviceType_nGnRE" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGnRE</anchor>, <anchor link="DeviceType_nGnRnE" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGnRnE</anchor>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/EffectiveMTX" mylink="shared.functions.memory.EffectiveMTX" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EffectiveMTX()</line>
<line>// ==============</line>
<line>// Returns the effective MTX in the AArch64 stage 1 translation regime for "el".</line>
<line></line>
<line link="impl-shared.EffectiveMTX.3" hover="function: bit EffectiveMTX(bits(64) address, boolean is_instr, bits(2) el)" conts="EffectiveMTX">bit <anchor link="impl-shared.EffectiveMTX.3" hover="function: bit EffectiveMTX(bits(64) address, boolean is_instr, bits(2) el)">EffectiveMTX</anchor>(bits(64) address, boolean is_instr, bits(2) el)</line>
<line>    bit mtx;</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(el);</line>
<line>    regime = <a link="impl-shared.S1TranslationRegime.1" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime(bits(2) el)">S1TranslationRegime</a>(el);</line>
<line>    assert(!<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(regime));</line>
<line></line>
<line>    if !<a link="impl-shared.HaveMTE4Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE4Ext()">HaveMTE4Ext</a>() || is_instr then</line>
<line>        mtx = '0';</line>
<line>    else</line>
<line>        case regime of</line>
<line>            when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>                mtx = if address&lt;55&gt; == '1' then TCR_EL1.MTX1 else TCR_EL1.MTX0;</line>
<line>            when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>                if <a link="impl-shared.HaveVirtHostExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</a>() &amp;&amp; <a link="impl-shared.ELIsInHost.1" file="shared_pseudocode.xml" hover="function: boolean ELIsInHost(bits(2) el)">ELIsInHost</a>(el) then</line>
<line>                    mtx = if address&lt;55&gt; == '1' then TCR_EL2.MTX1 else TCR_EL2.MTX0;</line>
<line>                else</line>
<line>                    mtx = TCR_EL2.MTX;</line>
<line>            when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>                mtx = TCR_EL3.MTX;</line>
<line></line>
<line>    return mtx;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/EffectiveTBI" mylink="shared.functions.memory.EffectiveTBI" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EffectiveTBI()</line>
<line>// ==============</line>
<line>// Returns the effective TBI in the AArch64 stage 1 translation regime for "el".</line>
<line></line>
<line link="impl-shared.EffectiveTBI.3" hover="function: bit EffectiveTBI(bits(64) address, boolean IsInstr, bits(2) el)" conts="EffectiveTBI">bit <anchor link="impl-shared.EffectiveTBI.3" hover="function: bit EffectiveTBI(bits(64) address, boolean IsInstr, bits(2) el)">EffectiveTBI</anchor>(bits(64) address, boolean IsInstr, bits(2) el)</line>
<line>    bit tbi;</line>
<line>    bit tbid;</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(el);</line>
<line>    regime = <a link="impl-shared.S1TranslationRegime.1" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime(bits(2) el)">S1TranslationRegime</a>(el);</line>
<line>    assert(!<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(regime));</line>
<line></line>
<line>    case regime of</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            tbi = if address&lt;55&gt; == '1' then TCR_EL1.TBI1 else TCR_EL1.TBI0;</line>
<line>            if <a link="impl-aarch64.HavePACExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePACExt()">HavePACExt</a>() then</line>
<line>                tbid = if address&lt;55&gt; == '1' then TCR_EL1.TBID1 else TCR_EL1.TBID0;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            if <a link="impl-shared.HaveVirtHostExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</a>() &amp;&amp; <a link="impl-shared.ELIsInHost.1" file="shared_pseudocode.xml" hover="function: boolean ELIsInHost(bits(2) el)">ELIsInHost</a>(el) then</line>
<line>                tbi = if address&lt;55&gt; == '1' then TCR_EL2.TBI1 else TCR_EL2.TBI0;</line>
<line>                if <a link="impl-aarch64.HavePACExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePACExt()">HavePACExt</a>() then</line>
<line>                    tbid = if address&lt;55&gt; == '1' then TCR_EL2.TBID1 else TCR_EL2.TBID0;</line>
<line>            else</line>
<line>                tbi = TCR_EL2.TBI;</line>
<line>                if <a link="impl-aarch64.HavePACExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePACExt()">HavePACExt</a>() then tbid = TCR_EL2.TBID;</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            tbi = TCR_EL3.TBI;</line>
<line>            if <a link="impl-aarch64.HavePACExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePACExt()">HavePACExt</a>() then tbid = TCR_EL3.TBID;</line>
<line></line>
<line>    return (if tbi == '1' &amp;&amp; (!<a link="impl-aarch64.HavePACExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePACExt()">HavePACExt</a>() || tbid == '0' || !IsInstr) then '1' else '0');</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/EffectiveTCMA" mylink="shared.functions.memory.EffectiveTCMA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EffectiveTCMA()</line>
<line>// ===============</line>
<line>// Returns the effective TCMA of a virtual address in the stage 1 translation regime for "el".</line>
<line></line>
<line link="impl-shared.EffectiveTCMA.2" hover="function: bit EffectiveTCMA(bits(64) address, bits(2) el)" conts="EffectiveTCMA">bit <anchor link="impl-shared.EffectiveTCMA.2" hover="function: bit EffectiveTCMA(bits(64) address, bits(2) el)">EffectiveTCMA</anchor>(bits(64) address, bits(2) el)</line>
<line>    bit tcma;</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(el);</line>
<line>    regime = <a link="impl-shared.S1TranslationRegime.1" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime(bits(2) el)">S1TranslationRegime</a>(el);</line>
<line>    assert(!<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(regime));</line>
<line></line>
<line>    case regime of</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            tcma = if address&lt;55&gt; == '1' then TCR_EL1.TCMA1 else TCR_EL1.TCMA0;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            if <a link="impl-shared.HaveVirtHostExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</a>() &amp;&amp; <a link="impl-shared.ELIsInHost.1" file="shared_pseudocode.xml" hover="function: boolean ELIsInHost(bits(2) el)">ELIsInHost</a>(el) then</line>
<line>                tcma = if address&lt;55&gt; == '1' then TCR_EL2.TCMA1 else TCR_EL2.TCMA0;</line>
<line>            else</line>
<line>                tcma = TCR_EL2.TCMA;</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            tcma = TCR_EL3.TCMA;</line>
<line></line>
<line>    return tcma;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/ErrorState" mylink="shared.functions.memory.ErrorState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ErrorState</line>
<line>// ==========</line>
<line>// The allowed error states that can be returned by memory and used by the PE.</line>
<line></line>
<line link="ErrorState" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}" conts="ErrorState">enumeration <anchor link="ErrorState" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState</anchor> {<anchor link="ErrorState_UC" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UC</anchor>,            // Uncontainable</line>
<line link="ErrorState_UEU" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}" conts="ErrorState_UEU">                        <anchor link="ErrorState_UEU" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UEU</anchor>,           // Unrecoverable state</line>
<line link="ErrorState_UEO" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}" conts="ErrorState_UEO">                        <anchor link="ErrorState_UEO" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UEO</anchor>,           // Restartable state</line>
<line link="ErrorState_UER" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}" conts="ErrorState_UER">                        <anchor link="ErrorState_UER" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_UER</anchor>,           // Recoverable state</line>
<line link="ErrorState_CE" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}" conts="ErrorState_CE">                        <anchor link="ErrorState_CE" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_CE</anchor>,            // Corrected</line>
<line link="ErrorState_Uncategorized" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}" conts="ErrorState_Uncategorized">                        <anchor link="ErrorState_Uncategorized" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_Uncategorized</anchor>,</line>
<line link="ErrorState_IMPDEF" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}" conts="ErrorState_IMPDEF">                        <anchor link="ErrorState_IMPDEF" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState_IMPDEF</anchor>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/Fault" mylink="shared.functions.memory.Fault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Fault</line>
<line>// =====</line>
<line>// Fault types.</line>
<line></line>
<line link="Fault" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault">enumeration <anchor link="Fault" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault</anchor> {<anchor link="Fault_None" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</anchor>,</line>
<line link="Fault_AccessFlag" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_AccessFlag">                   <anchor link="Fault_AccessFlag" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AccessFlag</anchor>,</line>
<line link="Fault_Alignment" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_Alignment">                   <anchor link="Fault_Alignment" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Alignment</anchor>,</line>
<line link="Fault_Background" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_Background">                   <anchor link="Fault_Background" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Background</anchor>,</line>
<line link="Fault_Domain" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_Domain">                   <anchor link="Fault_Domain" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Domain</anchor>,</line>
<line link="Fault_Permission" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_Permission">                   <anchor link="Fault_Permission" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</anchor>,</line>
<line link="Fault_Translation" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_Translation">                   <anchor link="Fault_Translation" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Translation</anchor>,</line>
<line link="Fault_AddressSize" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_AddressSize">                   <anchor link="Fault_AddressSize" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AddressSize</anchor>,</line>
<line link="Fault_SyncExternal" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_SyncExternal">                   <anchor link="Fault_SyncExternal" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncExternal</anchor>,</line>
<line link="Fault_SyncExternalOnWalk" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_SyncExternalOnWalk">                   <anchor link="Fault_SyncExternalOnWalk" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncExternalOnWalk</anchor>,</line>
<line link="Fault_SyncParity" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_SyncParity">                   <anchor link="Fault_SyncParity" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncParity</anchor>,</line>
<line link="Fault_SyncParityOnWalk" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_SyncParityOnWalk">                   <anchor link="Fault_SyncParityOnWalk" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncParityOnWalk</anchor>,</line>
<line link="Fault_GPCFOnWalk" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_GPCFOnWalk">                   <anchor link="Fault_GPCFOnWalk" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_GPCFOnWalk</anchor>,</line>
<line link="Fault_GPCFOnOutput" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_GPCFOnOutput">                   <anchor link="Fault_GPCFOnOutput" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_GPCFOnOutput</anchor>,</line>
<line link="Fault_AsyncParity" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_AsyncParity">                   <anchor link="Fault_AsyncParity" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncParity</anchor>,</line>
<line link="Fault_AsyncExternal" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_AsyncExternal">                   <anchor link="Fault_AsyncExternal" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncExternal</anchor>,</line>
<line link="Fault_TagCheck" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_TagCheck">                   <anchor link="Fault_TagCheck" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_TagCheck</anchor>,</line>
<line link="Fault_Debug" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_Debug">                   <anchor link="Fault_Debug" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Debug</anchor>,</line>
<line link="Fault_TLBConflict" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_TLBConflict">                   <anchor link="Fault_TLBConflict" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_TLBConflict</anchor>,</line>
<line link="Fault_BranchTarget" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_BranchTarget">                   <anchor link="Fault_BranchTarget" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_BranchTarget</anchor>,</line>
<line link="Fault_HWUpdateAccessFlag" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_HWUpdateAccessFlag">                   <anchor link="Fault_HWUpdateAccessFlag" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_HWUpdateAccessFlag</anchor>,</line>
<line link="Fault_Lockdown" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_Lockdown">                   <anchor link="Fault_Lockdown" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Lockdown</anchor>,</line>
<line link="Fault_Exclusive" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_Exclusive">                   <anchor link="Fault_Exclusive" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Exclusive</anchor>,</line>
<line link="Fault_ICacheMaint" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}" conts="Fault_ICacheMaint">                   <anchor link="Fault_ICacheMaint" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_ICacheMaint</anchor>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/FaultRecord" mylink="shared.functions.memory.FaultRecord" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FaultRecord</line>
<line>// ===========</line>
<line>// Fields that relate only to Faults.</line>
<line></line>
<line link="FaultRecord" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )" conts="FaultRecord">type <anchor link="FaultRecord" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</anchor> is (</line>
<line>    <a link="Fault" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault</a>            statuscode,  // Fault Status</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> access,      // Details of the faulting access</line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a>      ipaddress,   // Intermediate physical address</line>
<line>    <a link="GPCFRecord" file="shared_pseudocode.xml" hover="type GPCFRecord is ( GPCF gpf, integer level )">GPCFRecord</a>       gpcf,        // Granule Protection Check Fault record</line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a>      paddress,    // Physical address</line>
<line>    boolean          gpcfs2walk,  // GPC for a stage 2 translation table walk</line>
<line>    boolean          s2fs1walk,   // Is on a Stage 1 translation table walk</line>
<line>    boolean          write,       // TRUE for a write, FALSE for a read</line>
<line>    boolean          s1tagnotdata,// TRUE for a fault due to tag not accessible at stage 1.</line>
<line>    boolean          tagaccess,   // TRUE for a fault due to NoTagAccess permission.</line>
<line>    integer          level,       // For translation, access flag and Permission faults</line>
<line>    bit              extflag,     // IMPLEMENTATION DEFINED syndrome for External aborts</line>
<line>    boolean          secondstage, // Is a Stage 2 abort</line>
<line>    boolean          assuredonly, // Stage 2 Permission fault due to AssuredOnly attribute</line>
<line>    boolean          toplevel,    // Stage 2 Permission fault due to TopLevel</line>
<line>    boolean          overlay,     // Fault due to overlay permissions</line>
<line>    boolean          dirtybit,    // Fault due to dirty state</line>
<line>    bits(4)          domain,      // Domain number, AArch32 only</line>
<line>    <a link="ErrorState" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState</a>       merrorstate, // Incoming error state from memory</line>
<line>    bits(4)          debugmoe     // Debug method of entry, from AArch32 only</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/FullAddress" mylink="shared.functions.memory.FullAddress" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FullAddress</line>
<line>// ===========</line>
<line>// Physical or Intermediate Physical Address type.</line>
<line>// Although AArch32 only has access to 40 bits of physical or intermediate physical address space,</line>
<line>// the full address type has 56 bits to allow interprocessing with AArch64.</line>
<line>// The maximum physical or intermediate physical address size is IMPLEMENTATION DEFINED,</line>
<line>// but never exceeds 56 bits.</line>
<line></line>
<line link="FullAddress" hover="type FullAddress is ( PASpace paspace, bits(56) address )" conts="FullAddress">type <anchor link="FullAddress" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</anchor> is (</line>
<line>    <a link="PASpace" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PASpace</a>  paspace,</line>
<line>    bits(56) address</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/GPCF" mylink="shared.functions.memory.GPCF" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GPCF</line>
<line>// ====</line>
<line>// Possible Granule Protection Check Fault reasons</line>
<line></line>
<line link="GPCF" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }" conts="GPCF">enumeration <anchor link="GPCF" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF</anchor> {</line>
<line link="GPCF_None" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }" conts="GPCF_None">    <anchor link="GPCF_None" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_None</anchor>,        // No fault</line>
<line link="GPCF_AddressSize" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }" conts="GPCF_AddressSize">    <anchor link="GPCF_AddressSize" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_AddressSize</anchor>, // GPT address size fault</line>
<line link="GPCF_Walk" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }" conts="GPCF_Walk">    <anchor link="GPCF_Walk" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_Walk</anchor>,        // GPT walk fault</line>
<line link="GPCF_EABT" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }" conts="GPCF_EABT">    <anchor link="GPCF_EABT" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_EABT</anchor>,        // Synchronous External abort on GPT fetch</line>
<line link="GPCF_Fail" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }" conts="GPCF_Fail">    <anchor link="GPCF_Fail" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_Fail</anchor>         // Granule protection fault</line>
<line>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/GPCFRecord" mylink="shared.functions.memory.GPCFRecord" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GPCFRecord</line>
<line>// ==========</line>
<line>// Full details of a Granule Protection Check Fault</line>
<line></line>
<line link="GPCFRecord" hover="type GPCFRecord is ( GPCF gpf, integer level )" conts="GPCFRecord">type <anchor link="GPCFRecord" hover="type GPCFRecord is ( GPCF gpf, integer level )">GPCFRecord</anchor> is (</line>
<line>    <a link="GPCF" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF</a>    gpf,</line>
<line>    integer level</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/Hint_Prefetch" mylink="shared.functions.memory.Hint_Prefetch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Hint_Prefetch()</line>
<line>// ===============</line>
<line>// Signals the memory system that memory accesses of type HINT to or from the specified address are</line>
<line>// likely in the near future. The memory system may take some action to speed up the memory</line>
<line>// accesses when they do occur, such as pre-loading the specified address into one or more</line>
<line>// caches as indicated by the innermost cache level target (0=L1, 1=L2, etc) and non-temporal hint</line>
<line>// stream. Any or all prefetch hints may be treated as a NOP. A prefetch hint must not cause a</line>
<line>// synchronous abort due to Alignment or Translation faults and the like. Its only effect on</line>
<line>// software-visible state should be on caches and TLBs associated with address, which must be</line>
<line>// accessible by reads, writes or execution, as defined in the translation regime of the current</line>
<line>// Exception level. It is guaranteed not to access Device memory.</line>
<line>// A Prefetch_EXEC hint must not result in an access that could not be performed by a speculative</line>
<line>// instruction fetch, therefore if all associated MMUs are disabled, then it cannot access any</line>
<line>// memory location that cannot be accessed by instruction fetches.</line>
<line></line>
<line link="impl-shared.Hint_Prefetch.4" hover="function: Hint_Prefetch(bits(64) address, PrefetchHint hint, integer target, boolean stream)" conts="Hint_Prefetch"><anchor link="impl-shared.Hint_Prefetch.4" hover="function: Hint_Prefetch(bits(64) address, PrefetchHint hint, integer target, boolean stream)">Hint_Prefetch</anchor>(bits(64) address, <a link="PrefetchHint" file="shared_pseudocode.xml" hover="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">PrefetchHint</a> hint, integer target, boolean stream);</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/Hint_RangePrefetch" mylink="shared.functions.memory.Hint_RangePrefetch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Hint_RangePrefetch()</line>
<line>// ====================</line>
<line>// Signals the memory system that data memory accesses from a specified range</line>
<line>// of addresses are likely to occur in the near future. The memory system can</line>
<line>// respond by taking actions that are expected to speed up the memory accesses</line>
<line>// when they do occur, such as preloading the locations within the specified</line>
<line>// address ranges into one or more caches.</line>
<line></line>
<line link="impl-shared.Hint_RangePrefetch.6" hover="function: Hint_RangePrefetch(bits(64) address, integer length, integer stride, integer count, integer reuse, bits(6) operation)" conts="Hint_RangePrefetch"><anchor link="impl-shared.Hint_RangePrefetch.6" hover="function: Hint_RangePrefetch(bits(64) address, integer length, integer stride, integer count, integer reuse, bits(6) operation)">Hint_RangePrefetch</anchor>(bits(64) address, integer length, integer stride,</line>
<line>                   integer count, integer reuse, bits(6) operation);</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/IsDataAccess" mylink="shared.functions.memory.IsDataAccess" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsDataAccess()</line>
<line>// ==============</line>
<line>// Return TRUE if access is to data memory.</line>
<line></line>
<line link="impl-shared.IsDataAccess.1" hover="function: boolean IsDataAccess(AccessType acctype)" conts="IsDataAccess">boolean <anchor link="impl-shared.IsDataAccess.1" hover="function: boolean IsDataAccess(AccessType acctype)">IsDataAccess</anchor>(<a link="AccessType" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType</a> acctype)</line>
<line>    return !(acctype IN {<a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a>,</line>
<line>                         <a link="AccessType_TTW" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_TTW</a>,</line>
<line>                         <a link="AccessType_DC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_DC</a>,</line>
<line>                         <a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a>,</line>
<line>                         <a link="AccessType_AT" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_AT</a>});</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/MBReqDomain" mylink="shared.functions.memory.MBReqDomain" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MBReqDomain</line>
<line>// ===========</line>
<line>// Memory barrier domain.</line>
<line></line>
<line link="MBReqDomain" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}" conts="MBReqDomain">enumeration <anchor link="MBReqDomain" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain</anchor>    {<anchor link="MBReqDomain_Nonshareable" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_Nonshareable</anchor>, <anchor link="MBReqDomain_InnerShareable" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_InnerShareable</anchor>,</line>
<line link="MBReqDomain_OuterShareable" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}" conts="MBReqDomain_OuterShareable">                            <anchor link="MBReqDomain_OuterShareable" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_OuterShareable</anchor>, <anchor link="MBReqDomain_FullSystem" hover="enumeration MBReqDomain    {MBReqDomain_Nonshareable, MBReqDomain_InnerShareable, MBReqDomain_OuterShareable, MBReqDomain_FullSystem}">MBReqDomain_FullSystem</anchor>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/MBReqTypes" mylink="shared.functions.memory.MBReqTypes" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MBReqTypes</line>
<line>// ==========</line>
<line>// Memory barrier read/write.</line>
<line></line>
<line link="MBReqTypes" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}" conts="MBReqTypes">enumeration <anchor link="MBReqTypes" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes</anchor>     {<anchor link="MBReqTypes_Reads" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_Reads</anchor>, <anchor link="MBReqTypes_Writes" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_Writes</anchor>, <anchor link="MBReqTypes_All" hover="enumeration MBReqTypes     {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All}">MBReqTypes_All</anchor>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/MPAM" mylink="shared.functions.memory.MPAM" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MPAM Types</line>
<line>// ==========</line>
<line></line>
<line link="PARTIDtype" hover="type PARTIDtype" conts="PARTIDtype">type <anchor link="PARTIDtype" hover="type PARTIDtype">PARTIDtype</anchor> = bits(16);</line>
<line></line>
<line link="PMGtype" hover="type PMGtype" conts="PMGtype">type <anchor link="PMGtype" hover="type PMGtype">PMGtype</anchor> = bits(8);</line>
<line></line>
<line link="PARTIDspaceType" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }" conts="PARTIDspaceType">enumeration <anchor link="PARTIDspaceType" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PARTIDspaceType</anchor> {</line>
<line link="PIdSpace_Secure" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }" conts="PIdSpace_Secure">    <anchor link="PIdSpace_Secure" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_Secure</anchor>,</line>
<line link="PIdSpace_Root" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }" conts="PIdSpace_Root">    <anchor link="PIdSpace_Root" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_Root</anchor>,</line>
<line link="PIdSpace_Realm" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }" conts="PIdSpace_Realm">    <anchor link="PIdSpace_Realm" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_Realm</anchor>,</line>
<line link="PIdSpace_NonSecure" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }" conts="PIdSpace_NonSecure">    <anchor link="PIdSpace_NonSecure" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_NonSecure</anchor></line>
<line>};</line>
<line></line>
<line link="MPAMinfo" hover="type MPAMinfo is ( PARTIDspaceType mpam_sp, PARTIDtype partid, PMGtype pmg )" conts="MPAMinfo">type <anchor link="MPAMinfo" hover="type MPAMinfo is ( PARTIDspaceType mpam_sp, PARTIDtype partid, PMGtype pmg )">MPAMinfo</anchor> is (</line>
<line>     <a link="PARTIDspaceType" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PARTIDspaceType</a> mpam_sp,</line>
<line>     <a link="PARTIDtype" file="shared_pseudocode.xml" hover="type PARTIDtype">PARTIDtype</a> partid,</line>
<line>     <a link="PMGtype" file="shared_pseudocode.xml" hover="type PMGtype">PMGtype</a> pmg</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/MemAtomicOp" mylink="shared.functions.memory.MemAtomicOp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemAtomicOp</line>
<line>// ===========</line>
<line>// Atomic data processing instruction types.</line>
<line></line>
<line link="MemAtomicOp" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }" conts="MemAtomicOp">enumeration <anchor link="MemAtomicOp" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp</anchor> {</line>
<line link="MemAtomicOp_GCSSS1" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }" conts="MemAtomicOp_GCSSS1">    <anchor link="MemAtomicOp_GCSSS1" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_GCSSS1</anchor>,</line>
<line link="MemAtomicOp_ADD" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }" conts="MemAtomicOp_ADD">    <anchor link="MemAtomicOp_ADD" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_ADD</anchor>,</line>
<line link="MemAtomicOp_BIC" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }" conts="MemAtomicOp_BIC">    <anchor link="MemAtomicOp_BIC" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_BIC</anchor>,</line>
<line link="MemAtomicOp_EOR" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }" conts="MemAtomicOp_EOR">    <anchor link="MemAtomicOp_EOR" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_EOR</anchor>,</line>
<line link="MemAtomicOp_ORR" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }" conts="MemAtomicOp_ORR">    <anchor link="MemAtomicOp_ORR" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_ORR</anchor>,</line>
<line link="MemAtomicOp_SMAX" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }" conts="MemAtomicOp_SMAX">    <anchor link="MemAtomicOp_SMAX" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_SMAX</anchor>,</line>
<line link="MemAtomicOp_SMIN" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }" conts="MemAtomicOp_SMIN">    <anchor link="MemAtomicOp_SMIN" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_SMIN</anchor>,</line>
<line link="MemAtomicOp_UMAX" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }" conts="MemAtomicOp_UMAX">    <anchor link="MemAtomicOp_UMAX" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_UMAX</anchor>,</line>
<line link="MemAtomicOp_UMIN" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }" conts="MemAtomicOp_UMIN">    <anchor link="MemAtomicOp_UMIN" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_UMIN</anchor>,</line>
<line link="MemAtomicOp_SWP" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }" conts="MemAtomicOp_SWP">    <anchor link="MemAtomicOp_SWP" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_SWP</anchor>,</line>
<line link="MemAtomicOp_CAS" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }" conts="MemAtomicOp_CAS">    <anchor link="MemAtomicOp_CAS" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_CAS</anchor></line>
<line>};</line>
<line></line>
<line link="CacheOp" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }" conts="CacheOp">enumeration <anchor link="CacheOp" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp</anchor> {</line>
<line link="CacheOp_Clean" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }" conts="CacheOp_Clean">    <anchor link="CacheOp_Clean" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_Clean</anchor>,</line>
<line link="CacheOp_Invalidate" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }" conts="CacheOp_Invalidate">    <anchor link="CacheOp_Invalidate" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_Invalidate</anchor>,</line>
<line link="CacheOp_CleanInvalidate" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }" conts="CacheOp_CleanInvalidate">    <anchor link="CacheOp_CleanInvalidate" hover="enumeration CacheOp { CacheOp_Clean, CacheOp_Invalidate, CacheOp_CleanInvalidate }">CacheOp_CleanInvalidate</anchor></line>
<line>};</line>
<line></line>
<line link="CacheOpScope" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }" conts="CacheOpScope">enumeration <anchor link="CacheOpScope" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope</anchor> {</line>
<line link="CacheOpScope_SetWay" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }" conts="CacheOpScope_SetWay">    <anchor link="CacheOpScope_SetWay" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_SetWay</anchor>,</line>
<line link="CacheOpScope_PoU" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }" conts="CacheOpScope_PoU">    <anchor link="CacheOpScope_PoU" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_PoU</anchor>,</line>
<line link="CacheOpScope_PoC" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }" conts="CacheOpScope_PoC">    <anchor link="CacheOpScope_PoC" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_PoC</anchor>,</line>
<line link="CacheOpScope_PoE" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }" conts="CacheOpScope_PoE">    <anchor link="CacheOpScope_PoE" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_PoE</anchor>,</line>
<line link="CacheOpScope_PoP" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }" conts="CacheOpScope_PoP">    <anchor link="CacheOpScope_PoP" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_PoP</anchor>,</line>
<line link="CacheOpScope_PoDP" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }" conts="CacheOpScope_PoDP">    <anchor link="CacheOpScope_PoDP" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_PoDP</anchor>,</line>
<line link="CacheOpScope_ALLU" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }" conts="CacheOpScope_ALLU">    <anchor link="CacheOpScope_ALLU" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_ALLU</anchor>,</line>
<line link="CacheOpScope_ALLUIS" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }" conts="CacheOpScope_ALLUIS">    <anchor link="CacheOpScope_ALLUIS" hover="enumeration CacheOpScope { CacheOpScope_SetWay, CacheOpScope_PoU, CacheOpScope_PoC, CacheOpScope_PoE, CacheOpScope_PoP, CacheOpScope_PoDP, CacheOpScope_ALLU, CacheOpScope_ALLUIS }">CacheOpScope_ALLUIS</anchor></line>
<line>};</line>
<line></line>
<line link="CacheType" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }" conts="CacheType">enumeration <anchor link="CacheType" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }">CacheType</anchor> {</line>
<line link="CacheType_Data" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }" conts="CacheType_Data">    <anchor link="CacheType_Data" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }">CacheType_Data</anchor>,</line>
<line link="CacheType_Tag" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }" conts="CacheType_Tag">    <anchor link="CacheType_Tag" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }">CacheType_Tag</anchor>,</line>
<line link="CacheType_Data_Tag" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }" conts="CacheType_Data_Tag">    <anchor link="CacheType_Data_Tag" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }">CacheType_Data_Tag</anchor>,</line>
<line link="CacheType_Instruction" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }" conts="CacheType_Instruction">    <anchor link="CacheType_Instruction" hover="enumeration CacheType { CacheType_Data, CacheType_Tag, CacheType_Data_Tag, CacheType_Instruction }">CacheType_Instruction</anchor></line>
<line>};</line>
<line></line>
<line link="CachePASpace" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }" conts="CachePASpace">enumeration <anchor link="CachePASpace" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }">CachePASpace</anchor> {</line>
<line link="CPAS_NonSecure" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }" conts="CPAS_NonSecure">    <anchor link="CPAS_NonSecure" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }">CPAS_NonSecure</anchor>,</line>
<line link="CPAS_Any" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }" conts="CPAS_Any">    <anchor link="CPAS_Any" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }">CPAS_Any</anchor>,               // Applicable only for DC *SW / IC IALLU* in Root state:</line>
<line>                            // match entries from any PA Space</line>
<line link="CPAS_RealmNonSecure" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }" conts="CPAS_RealmNonSecure">    <anchor link="CPAS_RealmNonSecure" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }">CPAS_RealmNonSecure</anchor>,    // Applicable only for DC *SW / IC IALLU* in Realm state:</line>
<line>                            // match entries from Realm or Non-Secure PAS</line>
<line link="CPAS_Realm" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }" conts="CPAS_Realm">    <anchor link="CPAS_Realm" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }">CPAS_Realm</anchor>,</line>
<line link="CPAS_Root" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }" conts="CPAS_Root">    <anchor link="CPAS_Root" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }">CPAS_Root</anchor>,</line>
<line link="CPAS_SecureNonSecure" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }" conts="CPAS_SecureNonSecure">    <anchor link="CPAS_SecureNonSecure" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }">CPAS_SecureNonSecure</anchor>,   // Applicable only for DC *SW / IC IALLU* in Secure state:</line>
<line>                            // match entries from Secure or Non-Secure PAS</line>
<line link="CPAS_Secure" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }" conts="CPAS_Secure">    <anchor link="CPAS_Secure" hover="enumeration CachePASpace { CPAS_NonSecure, CPAS_Any,  CPAS_RealmNonSecure,  CPAS_Realm, CPAS_Root, CPAS_SecureNonSecure,  CPAS_Secure }">CPAS_Secure</anchor></line>
<line>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/MemAttrHints" mylink="shared.functions.memory.MemAttrHints" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemAttrHints</line>
<line>// ============</line>
<line>// Attributes and hints for Normal memory.</line>
<line></line>
<line link="MemAttrHints" hover="type MemAttrHints is ( bits(2) attrs, bits(2) hints, boolean transient )" conts="MemAttrHints">type <anchor link="MemAttrHints" hover="type MemAttrHints is ( bits(2) attrs, bits(2) hints, boolean transient )">MemAttrHints</anchor> is (</line>
<line>    bits(2) attrs,  // See MemAttr_*, Cacheability attributes</line>
<line>    bits(2) hints,  // See MemHint_*, Allocation hints</line>
<line>    boolean transient</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/MemOp" mylink="shared.functions.memory.MemOp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemOp</line>
<line>// =====</line>
<line>// Memory access instruction types.</line>
<line></line>
<line link="MemOp" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}" conts="MemOp">enumeration <anchor link="MemOp" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</anchor> {<anchor link="MemOp_LOAD" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</anchor>, <anchor link="MemOp_STORE" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</anchor>, <anchor link="MemOp_PREFETCH" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_PREFETCH</anchor>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/MemType" mylink="shared.functions.memory.MemType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemType</line>
<line>// =======</line>
<line>// Basic memory types.</line>
<line></line>
<line link="MemType" hover="enumeration MemType {MemType_Normal, MemType_Device}" conts="MemType">enumeration <anchor link="MemType" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType</anchor> {<anchor link="MemType_Normal" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</anchor>, <anchor link="MemType_Device" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</anchor>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/Memory" mylink="shared.functions.memory.Memory" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Memory Tag type</line>
<line>// ===============</line>
<line></line>
<line link="MemTagType" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }" conts="MemTagType">enumeration <anchor link="MemTagType" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTagType</anchor> {</line>
<line link="MemTag_Untagged" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }" conts="MemTag_Untagged">    <anchor link="MemTag_Untagged" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_Untagged</anchor>,</line>
<line link="MemTag_AllocationTagged" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }" conts="MemTag_AllocationTagged">    <anchor link="MemTag_AllocationTagged" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_AllocationTagged</anchor>,</line>
<line link="MemTag_CanonicallyTagged" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }" conts="MemTag_CanonicallyTagged">    <anchor link="MemTag_CanonicallyTagged" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_CanonicallyTagged</anchor></line>
<line>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/MemoryAttributes" mylink="shared.functions.memory.MemoryAttributes" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MemoryAttributes</line>
<line>// ================</line>
<line>// Memory attributes descriptor</line>
<line></line>
<line link="MemoryAttributes" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )" conts="MemoryAttributes">type <anchor link="MemoryAttributes" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</anchor> is (</line>
<line>    <a link="MemType" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType</a>      memtype,</line>
<line>    <a link="DeviceType" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType</a>   device,       // For Device memory types</line>
<line>    <a link="MemAttrHints" file="shared_pseudocode.xml" hover="type MemAttrHints is ( bits(2) attrs, bits(2) hints, boolean transient )">MemAttrHints</a> inner,        // Inner hints and attributes</line>
<line>    <a link="MemAttrHints" file="shared_pseudocode.xml" hover="type MemAttrHints is ( bits(2) attrs, bits(2) hints, boolean transient )">MemAttrHints</a> outer,        // Outer hints and attributes</line>
<line>    <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> shareability, // Shareability attribute</line>
<line>    <a link="MemTagType" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTagType</a>   tags,         // MTE tag type for this memory.</line>
<line>    boolean      notagaccess,  // Allocation Tag access permission</line>
<line>    bit          xs            // XS attribute</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/NewAccDesc" mylink="shared.functions.memory.NewAccDesc" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// NewAccDesc()</line>
<line>// ============</line>
<line>// Create a new AccessDescriptor with initialised fields</line>
<line></line>
<line link="impl-shared.NewAccDesc.1" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)" conts="NewAccDesc">AccessDescriptor <anchor link="impl-shared.NewAccDesc.1" hover="function: AccessDescriptor NewAccDesc(AccessType acctype)">NewAccDesc</anchor>(<a link="AccessType" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType</a> acctype)</line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc;</line>
<line></line>
<line>    accdesc.acctype         = acctype;</line>
<line>    accdesc.el              = PSTATE.EL;</line>
<line>    accdesc.ss              = <a link="impl-shared.SecurityStateAtEL.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)">SecurityStateAtEL</a>(PSTATE.EL);</line>
<line>    accdesc.acqsc           = FALSE;</line>
<line>    accdesc.acqpc           = FALSE;</line>
<line>    accdesc.relsc           = FALSE;</line>
<line>    accdesc.limitedordered  = FALSE;</line>
<line>    accdesc.exclusive       = FALSE;</line>
<line>    accdesc.rcw             = FALSE;</line>
<line>    accdesc.rcws            = FALSE;</line>
<line>    accdesc.atomicop        = FALSE;</line>
<line>    accdesc.nontemporal     = FALSE;</line>
<line>    accdesc.read            = FALSE;</line>
<line>    accdesc.write           = FALSE;</line>
<line>    accdesc.pan             = FALSE;</line>
<line>    accdesc.nonfault        = FALSE;</line>
<line>    accdesc.firstfault      = FALSE;</line>
<line>    accdesc.first           = FALSE;</line>
<line>    accdesc.contiguous      = FALSE;</line>
<line>    accdesc.streamingsve    = FALSE;</line>
<line>    accdesc.ls64            = FALSE;</line>
<line>    accdesc.mops            = FALSE;</line>
<line>    accdesc.a32lsmd         = FALSE;</line>
<line>    accdesc.tagchecked      = FALSE;</line>
<line>    accdesc.tagaccess       = FALSE;</line>
<line>    accdesc.transactional   = FALSE;</line>
<line>    accdesc.mpam            = <a link="impl-shared.GenMPAMcurEL.1" file="shared_pseudocode.xml" hover="function: MPAMinfo GenMPAMcurEL(AccessType acctype)">GenMPAMcurEL</a>(acctype);</line>
<line></line>
<line>    return accdesc;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/PASpace" mylink="shared.functions.memory.PASpace" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PASpace</line>
<line>// =======</line>
<line>// Physical address spaces</line>
<line></line>
<line link="PASpace" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }" conts="PASpace">enumeration <anchor link="PASpace" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PASpace</anchor> {</line>
<line link="PAS_NonSecure" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }" conts="PAS_NonSecure">    <anchor link="PAS_NonSecure" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</anchor>,</line>
<line link="PAS_Secure" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }" conts="PAS_Secure">    <anchor link="PAS_Secure" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</anchor>,</line>
<line link="PAS_Root" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }" conts="PAS_Root">    <anchor link="PAS_Root" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Root</anchor>,</line>
<line link="PAS_Realm" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }" conts="PAS_Realm">    <anchor link="PAS_Realm" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</anchor></line>
<line>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/Permissions" mylink="shared.functions.memory.Permissions" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Permissions</line>
<line>// ===========</line>
<line>// Access Control bits in translation table descriptors</line>
<line></line>
<line link="Permissions" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )" conts="Permissions">type <anchor link="Permissions" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</anchor> is (</line>
<line>    bits(2) ap_table,   // Stage 1 hierarchical access permissions</line>
<line>    bit     xn_table,   // Stage 1 hierarchical execute-never for single EL regimes</line>
<line>    bit     pxn_table,  // Stage 1 hierarchical privileged execute-never</line>
<line>    bit     uxn_table,  // Stage 1 hierarchical unprivileged execute-never</line>
<line>    bits(3) ap,         // Stage 1 access permissions</line>
<line>    bit     xn,         // Stage 1 execute-never for single EL regimes</line>
<line>    bit     uxn,        // Stage 1 unprivileged execute-never</line>
<line>    bit     pxn,        // Stage 1 privileged execute-never</line>
<line>    bits(4) ppi,        // Stage 1 privileged indirect permissions</line>
<line>    bits(4) upi,        // Stage 1 unprivileged indirect permissions</line>
<line>    bit     ndirty,     // Stage 1 dirty state for indirect permissions scheme</line>
<line>    bits(4) s2pi,       // Stage 2 indirect permissions</line>
<line>    bit     s2dirty,    // Stage 2 dirty state</line>
<line>    bits(4) po_index,   // Stage 1 overlay permissions index</line>
<line>    bits(4) s2po_index, // Stage 2 overlay permissions index</line>
<line>    bits(2) s2ap,       // Stage 2 access permissions</line>
<line>    bit     s2tag_na,   // Stage 2 tag access</line>
<line>    bit     s2xnx,      // Stage 2 extended execute-never</line>
<line>    bit     s2xn        // Stage 2 execute-never</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/PhysMemRead" mylink="shared.functions.memory.PhysMemRead" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PhysMemRead()</line>
<line>// =============</line>
<line>// Returns the value read from memory, and a status.</line>
<line>// Returned value is UNKNOWN if an External abort occurred while reading the</line>
<line>// memory.</line>
<line>// Otherwise the PhysMemRetStatus statuscode is Fault_None.</line>
<line></line>
<line link="impl-shared.PhysMemRead.3" hover="function: (PhysMemRetStatus, bits(8*size)) PhysMemRead(AddressDescriptor desc, integer size, AccessDescriptor accdesc)" conts="PhysMemRead">(PhysMemRetStatus, bits(8*size)) <anchor link="impl-shared.PhysMemRead.3" hover="function: (PhysMemRetStatus, bits(8*size)) PhysMemRead(AddressDescriptor desc, integer size, AccessDescriptor accdesc)">PhysMemRead</anchor>(<a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> desc, integer size,</line>
<line>                                             <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc);</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/PhysMemRetStatus" mylink="shared.functions.memory.PhysMemRetStatus" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PhysMemRetStatus</line>
<line>// ================</line>
<line>// Fields that relate only to return values of PhysMem functions.</line>
<line></line>
<line link="PhysMemRetStatus" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )" conts="PhysMemRetStatus">type <anchor link="PhysMemRetStatus" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</anchor> is (</line>
<line>    <a link="Fault" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault</a>       statuscode,     // Fault Status</line>
<line>    bit         extflag,        // IMPLEMENTATION DEFINED syndrome for External aborts</line>
<line>    <a link="ErrorState" file="shared_pseudocode.xml" hover="enumeration ErrorState {ErrorState_UC, ErrorState_UEU, ErrorState_UEO, ErrorState_UER, ErrorState_CE, ErrorState_Uncategorized, ErrorState_IMPDEF}">ErrorState</a>  merrorstate,    // Optional error state returned on a physical memory access</line>
<line>    bits(64)    store64bstatus  // Status of 64B store</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/PhysMemWrite" mylink="shared.functions.memory.PhysMemWrite" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PhysMemWrite()</line>
<line>// ==============</line>
<line>// Writes the value to memory, and returns the status of the write.</line>
<line>// If there is an External abort on the write, the PhysMemRetStatus indicates this.</line>
<line>// Otherwise the statuscode of PhysMemRetStatus is Fault_None.</line>
<line></line>
<line link="impl-shared.PhysMemWrite.4" hover="function: PhysMemRetStatus PhysMemWrite(AddressDescriptor desc, integer size, AccessDescriptor accdesc, bits(8*size) value)" conts="PhysMemWrite">PhysMemRetStatus <anchor link="impl-shared.PhysMemWrite.4" hover="function: PhysMemRetStatus PhysMemWrite(AddressDescriptor desc, integer size, AccessDescriptor accdesc, bits(8*size) value)">PhysMemWrite</anchor>(<a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> desc, integer size, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc,</line>
<line>                              bits(8*size) value);</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/PrefetchHint" mylink="shared.functions.memory.PrefetchHint" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PrefetchHint</line>
<line>// ============</line>
<line>// Prefetch hint types.</line>
<line></line>
<line link="PrefetchHint" hover="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}" conts="PrefetchHint">enumeration <anchor link="PrefetchHint" hover="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">PrefetchHint</anchor> {<anchor link="Prefetch_READ" hover="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">Prefetch_READ</anchor>, <anchor link="Prefetch_WRITE" hover="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">Prefetch_WRITE</anchor>, <anchor link="Prefetch_EXEC" hover="enumeration PrefetchHint {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC}">Prefetch_EXEC</anchor>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/S1AccessControls" mylink="shared.functions.memory.S1AccessControls" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// S1AccessControls</line>
<line>// ================</line>
<line>// Effective access controls defined by stage 1 translation</line>
<line></line>
<line link="S1AccessControls" hover="type S1AccessControls is ( bit r, bit w, bit x, bit gcs, boolean overlay, bit or, bit ow, bit ox, bit wxn )" conts="S1AccessControls">type <anchor link="S1AccessControls" hover="type S1AccessControls is ( bit r, bit w, bit x, bit gcs, boolean overlay, bit or, bit ow, bit ox, bit wxn )">S1AccessControls</anchor> is (</line>
<line>    bit r,                 // Stage 1 base read permission</line>
<line>    bit w,                 // Stage 1 base write permission</line>
<line>    bit x,                 // Stage 1 base execute permission</line>
<line>    bit gcs,               // Stage 1 GCS permission</line>
<line>    boolean overlay,       // Stage 1 overlay feature enabled</line>
<line>    bit or,                // Stage 1 overlay read permission</line>
<line>    bit ow,                // Stage 1 overlay write permission</line>
<line>    bit ox,                // Stage 1 overlay execute permission</line>
<line>    bit wxn                // Stage 1 write permission implies execute-never</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/S2AccessControls" mylink="shared.functions.memory.S2AccessControls" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// S2AccessControls</line>
<line>// ================</line>
<line>// Effective access controls defined by stage 2 translation</line>
<line></line>
<line link="S2AccessControls" hover="type S2AccessControls is ( bit r, bit w, bit x, bit r_rcw, bit w_rcw, bit r_mmu, bit w_mmu, bit toplevel0, bit toplevel1, boolean overlay, bit or, bit ow, bit ox, bit or_rcw, bit ow_rcw, bit or_mmu, bit ow_mmu, )" conts="S2AccessControls">type <anchor link="S2AccessControls" hover="type S2AccessControls is ( bit r, bit w, bit x, bit r_rcw, bit w_rcw, bit r_mmu, bit w_mmu, bit toplevel0, bit toplevel1, boolean overlay, bit or, bit ow, bit ox, bit or_rcw, bit ow_rcw, bit or_mmu, bit ow_mmu, )">S2AccessControls</anchor> is (</line>
<line>    bit r,                 // Stage 2 read permission.</line>
<line>    bit w,                 // Stage 2 write permission.</line>
<line>    bit x,                 // Stage 2 execute permission.</line>
<line>    bit r_rcw,             // Stage 2 Read perms for RCW instruction.</line>
<line>    bit w_rcw,             // Stage 2 Write perms for RCW instruction.</line>
<line>    bit r_mmu,             // Stage 2 Read perms for TTW data.</line>
<line>    bit w_mmu,             // Stage 2 Write perms for TTW data.</line>
<line>    bit toplevel0,         // IPA as top level table for TTBR0_EL1.</line>
<line>    bit toplevel1,         // IPA as top level table for TTBR1_EL1.</line>
<line>    boolean overlay,       // Overlay enable</line>
<line>    bit or,                // Stage 2 overlay read permission.</line>
<line>    bit ow,                // Stage 2 overlay write permission.</line>
<line>    bit ox,                // Stage 2 overlay execute permission.</line>
<line>    bit or_rcw,            // Stage 2 overlay Read perms for RCW instruction.</line>
<line>    bit ow_rcw,            // Stage 2 overlay Write perms for RCW instruction.</line>
<line>    bit or_mmu,            // Stage 2 overlay Read perms for TTW data.</line>
<line>    bit ow_mmu,            // Stage 2 overlay Write perms for TTW data.</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/Shareability" mylink="shared.functions.memory.Shareability" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Shareability</line>
<line>// ============</line>
<line></line>
<line link="Shareability" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }" conts="Shareability">enumeration <anchor link="Shareability" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</anchor> {</line>
<line link="Shareability_NSH" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }" conts="Shareability_NSH">    <anchor link="Shareability_NSH" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</anchor>,</line>
<line link="Shareability_ISH" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }" conts="Shareability_ISH">    <anchor link="Shareability_ISH" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_ISH</anchor>,</line>
<line link="Shareability_OSH" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }" conts="Shareability_OSH">    <anchor link="Shareability_OSH" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</anchor></line>
<line>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/SpeculativeStoreBypassBarrierToPA" mylink="shared.functions.memory.SpeculativeStoreBypassBarrierToPA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SpeculativeStoreBypassBarrierToPA()</line>
<line>// ===================================</line>
<line></line>
<line link="impl-shared.SpeculativeStoreBypassBarrierToPA.0" hover="function: SpeculativeStoreBypassBarrierToPA()" conts="SpeculativeStoreBypassBarrierToPA"><anchor link="impl-shared.SpeculativeStoreBypassBarrierToPA.0" hover="function: SpeculativeStoreBypassBarrierToPA()">SpeculativeStoreBypassBarrierToPA</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/SpeculativeStoreBypassBarrierToVA" mylink="shared.functions.memory.SpeculativeStoreBypassBarrierToVA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SpeculativeStoreBypassBarrierToVA()</line>
<line>// ===================================</line>
<line></line>
<line link="impl-shared.SpeculativeStoreBypassBarrierToVA.0" hover="function: SpeculativeStoreBypassBarrierToVA()" conts="SpeculativeStoreBypassBarrierToVA"><anchor link="impl-shared.SpeculativeStoreBypassBarrierToVA.0" hover="function: SpeculativeStoreBypassBarrierToVA()">SpeculativeStoreBypassBarrierToVA</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/Tag" mylink="shared.functions.memory.Tag" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="LOG2_TAG_GRANULE" hover="constant integer LOG2_TAG_GRANULE = 4" conts="LOG2_TAG_GRANULE">constant integer <anchor link="LOG2_TAG_GRANULE" hover="constant integer LOG2_TAG_GRANULE = 4">LOG2_TAG_GRANULE</anchor> = 4;</line>
<line></line>
<line link="TAG_GRANULE" hover="constant integer TAG_GRANULE = 1 &lt;&lt; LOG2_TAG_GRANULE" conts="TAG_GRANULE">constant integer <anchor link="TAG_GRANULE" hover="constant integer TAG_GRANULE = 1 &lt;&lt; LOG2_TAG_GRANULE">TAG_GRANULE</anchor> = 1 &lt;&lt; <a link="LOG2_TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer LOG2_TAG_GRANULE = 4">LOG2_TAG_GRANULE</a>;</line>
</pstext>
    </ps>
    <ps name="shared/functions/memory/VARange" mylink="shared.functions.memory.VARange" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// VARange</line>
<line>// =======</line>
<line>// Virtual address ranges</line>
<line></line>
<line link="VARange" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }" conts="VARange">enumeration <anchor link="VARange" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange</anchor> {</line>
<line link="VARange_LOWER" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }" conts="VARange_LOWER">    <anchor link="VARange_LOWER" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_LOWER</anchor>,</line>
<line link="VARange_UPPER" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }" conts="VARange_UPPER">    <anchor link="VARange_UPPER" hover="enumeration VARange { VARange_LOWER, VARange_UPPER }">VARange_UPPER</anchor></line>
<line>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/mpam/AltPARTIDspace" mylink="shared.functions.mpam.AltPARTIDspace" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AltPARTIDspace()</line>
<line>// ================</line>
<line>// From the Security state, EL and ALTSP configuration, determine</line>
<line>// whether to primary space or the alt space is selected and which</line>
<line>// PARTID space is the alternative space. Return that alternative</line>
<line>// PARTID space if selected or the primary space if not.</line>
<line></line>
<line link="impl-shared.AltPARTIDspace.3" hover="function: PARTIDspaceType AltPARTIDspace(bits(2) el, SecurityState security, PARTIDspaceType primaryPIdSpace)" conts="AltPARTIDspace">PARTIDspaceType <anchor link="impl-shared.AltPARTIDspace.3" hover="function: PARTIDspaceType AltPARTIDspace(bits(2) el, SecurityState security, PARTIDspaceType primaryPIdSpace)">AltPARTIDspace</anchor>(bits(2) el, <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security,</line>
<line>                                <a link="PARTIDspaceType" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PARTIDspaceType</a> primaryPIdSpace)</line>
<line>    case security of</line>
<line>        when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a></line>
<line>            assert el != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line>            return primaryPIdSpace; // there is no ALTSP for Non_secure</line>
<line>        when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a></line>
<line>            assert el != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line>            if primaryPIdSpace == <a link="PIdSpace_NonSecure" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_NonSecure</a> then</line>
<line>                return primaryPIdSpace;</line>
<line>            return <a link="impl-shared.AltPIdSecure.2" file="shared_pseudocode.xml" hover="function: PARTIDspaceType AltPIdSecure(bits(2) el, PARTIDspaceType primaryPIdSpace)">AltPIdSecure</a>(el, primaryPIdSpace);</line>
<line>        when <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a></line>
<line>            assert el == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line>            if MPAM3_EL3.ALTSP_EL3 == '1' then</line>
<line>                if MPAM3_EL3.RT_ALTSP_NS == '1' then</line>
<line>                    return <a link="PIdSpace_NonSecure" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_NonSecure</a>;</line>
<line>                else</line>
<line>                    return <a link="PIdSpace_Secure" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_Secure</a>;</line>
<line>            else</line>
<line>                return primaryPIdSpace;</line>
<line>        when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a></line>
<line>            assert el != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line>            return <a link="impl-shared.AltPIdRealm.2" file="shared_pseudocode.xml" hover="function: PARTIDspaceType AltPIdRealm(bits(2) el, PARTIDspaceType primaryPIdSpace)">AltPIdRealm</a>(el, primaryPIdSpace);</line>
<line>        otherwise</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/mpam/AltPIdRealm" mylink="shared.functions.mpam.AltPIdRealm" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AltPIdRealm()</line>
<line>// =============</line>
<line>// Compute PARTID space as either the primary PARTID space or</line>
<line>// alternative PARTID space in the Realm Security state.</line>
<line>// Helper for AltPARTIDspace.</line>
<line></line>
<line link="impl-shared.AltPIdRealm.2" hover="function: PARTIDspaceType AltPIdRealm(bits(2) el, PARTIDspaceType primaryPIdSpace)" conts="AltPIdRealm">PARTIDspaceType <anchor link="impl-shared.AltPIdRealm.2" hover="function: PARTIDspaceType AltPIdRealm(bits(2) el, PARTIDspaceType primaryPIdSpace)">AltPIdRealm</anchor>(bits(2) el, <a link="PARTIDspaceType" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PARTIDspaceType</a> primaryPIdSpace)</line>
<line>    <a link="PARTIDspaceType" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PARTIDspaceType</a> PIdSpace = primaryPIdSpace;</line>
<line>    case el of</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>            if <a link="impl-shared.ELIsInHost.1" file="shared_pseudocode.xml" hover="function: boolean ELIsInHost(bits(2) el)">ELIsInHost</a>(<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>) then</line>
<line>                if !<a link="impl-shared.UsePrimarySpaceEL2.0" file="shared_pseudocode.xml" hover="function: boolean UsePrimarySpaceEL2()">UsePrimarySpaceEL2</a>() then</line>
<line>                    PIdSpace = <a link="PIdSpace_NonSecure" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_NonSecure</a>;</line>
<line>            elsif !<a link="impl-shared.UsePrimarySpaceEL10.0" file="shared_pseudocode.xml" hover="function: boolean UsePrimarySpaceEL10()">UsePrimarySpaceEL10</a>() then</line>
<line>                PIdSpace = <a link="PIdSpace_NonSecure" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_NonSecure</a>;</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            if !<a link="impl-shared.UsePrimarySpaceEL10.0" file="shared_pseudocode.xml" hover="function: boolean UsePrimarySpaceEL10()">UsePrimarySpaceEL10</a>() then</line>
<line>                PIdSpace = <a link="PIdSpace_NonSecure" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_NonSecure</a>;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            if !<a link="impl-shared.UsePrimarySpaceEL2.0" file="shared_pseudocode.xml" hover="function: boolean UsePrimarySpaceEL2()">UsePrimarySpaceEL2</a>() then</line>
<line>                PIdSpace = <a link="PIdSpace_NonSecure" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_NonSecure</a>;</line>
<line>        otherwise</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>    return PIdSpace;</line>
</pstext>
    </ps>
    <ps name="shared/functions/mpam/AltPIdSecure" mylink="shared.functions.mpam.AltPIdSecure" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AltPIdSecure()</line>
<line>// ==============</line>
<line>// Compute PARTID space as either the primary PARTID space or</line>
<line>// alternative PARTID space in the Secure Security state.</line>
<line>// Helper for AltPARTIDspace.</line>
<line></line>
<line link="impl-shared.AltPIdSecure.2" hover="function: PARTIDspaceType AltPIdSecure(bits(2) el, PARTIDspaceType primaryPIdSpace)" conts="AltPIdSecure">PARTIDspaceType <anchor link="impl-shared.AltPIdSecure.2" hover="function: PARTIDspaceType AltPIdSecure(bits(2) el, PARTIDspaceType primaryPIdSpace)">AltPIdSecure</anchor>(bits(2) el, <a link="PARTIDspaceType" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PARTIDspaceType</a> primaryPIdSpace)</line>
<line>    <a link="PARTIDspaceType" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PARTIDspaceType</a> PIdSpace = primaryPIdSpace;</line>
<line>    boolean el2en = <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>();</line>
<line>    case el of</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>            if el2en then</line>
<line>                if <a link="impl-shared.ELIsInHost.1" file="shared_pseudocode.xml" hover="function: boolean ELIsInHost(bits(2) el)">ELIsInHost</a>(<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>) then</line>
<line>                    if !<a link="impl-shared.UsePrimarySpaceEL2.0" file="shared_pseudocode.xml" hover="function: boolean UsePrimarySpaceEL2()">UsePrimarySpaceEL2</a>() then</line>
<line>                        PIdSpace = <a link="PIdSpace_NonSecure" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_NonSecure</a>;</line>
<line>                elsif !<a link="impl-shared.UsePrimarySpaceEL10.0" file="shared_pseudocode.xml" hover="function: boolean UsePrimarySpaceEL10()">UsePrimarySpaceEL10</a>() then</line>
<line>                    PIdSpace = <a link="PIdSpace_NonSecure" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_NonSecure</a>;</line>
<line>            elsif MPAM3_EL3.ALTSP_HEN == '0' &amp;&amp; MPAM3_EL3.ALTSP_HFC == '1' then</line>
<line>                PIdSpace = <a link="PIdSpace_NonSecure" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_NonSecure</a>;</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            if el2en then</line>
<line>                if !<a link="impl-shared.UsePrimarySpaceEL10.0" file="shared_pseudocode.xml" hover="function: boolean UsePrimarySpaceEL10()">UsePrimarySpaceEL10</a>() then</line>
<line>                    PIdSpace = <a link="PIdSpace_NonSecure" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_NonSecure</a>;</line>
<line>            elsif MPAM3_EL3.ALTSP_HEN == '0' &amp;&amp; MPAM3_EL3.ALTSP_HFC == '1' then</line>
<line>                PIdSpace = <a link="PIdSpace_NonSecure" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_NonSecure</a>;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            if !<a link="impl-shared.UsePrimarySpaceEL2.0" file="shared_pseudocode.xml" hover="function: boolean UsePrimarySpaceEL2()">UsePrimarySpaceEL2</a>() then</line>
<line>                PIdSpace = <a link="PIdSpace_NonSecure" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_NonSecure</a>;</line>
<line>        otherwise</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>    return PIdSpace;</line>
</pstext>
    </ps>
    <ps name="shared/functions/mpam/DefaultMPAMinfo" mylink="shared.functions.mpam.DefaultMPAMinfo" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DefaultMPAMinfo()</line>
<line>// =================</line>
<line>// Returns default MPAM info.  The partidspace argument sets</line>
<line>// the PARTID space of the default MPAM information returned.</line>
<line></line>
<line link="impl-shared.DefaultMPAMinfo.1" hover="function: MPAMinfo DefaultMPAMinfo(PARTIDspaceType partidspace)" conts="DefaultMPAMinfo">MPAMinfo <anchor link="impl-shared.DefaultMPAMinfo.1" hover="function: MPAMinfo DefaultMPAMinfo(PARTIDspaceType partidspace)">DefaultMPAMinfo</anchor>(<a link="PARTIDspaceType" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PARTIDspaceType</a> partidspace)</line>
<line>    <a link="MPAMinfo" file="shared_pseudocode.xml" hover="type MPAMinfo is ( PARTIDspaceType mpam_sp, PARTIDtype partid, PMGtype pmg )">MPAMinfo</a> DefaultInfo;</line>
<line>    DefaultInfo.mpam_sp = partidspace;</line>
<line>    DefaultInfo.partid  = <a link="DefaultPARTID" file="shared_pseudocode.xml" hover="constant PARTIDtype DefaultPARTID = 0&lt;15:0&gt;">DefaultPARTID</a>;</line>
<line>    DefaultInfo.pmg     = <a link="DefaultPMG" file="shared_pseudocode.xml" hover="constant PMGtype DefaultPMG = 0&lt;7:0&gt;">DefaultPMG</a>;</line>
<line>    return DefaultInfo;</line>
</pstext>
    </ps>
    <ps name="shared/functions/mpam/DefaultPARTID" mylink="shared.functions.mpam.DefaultPARTID" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="DefaultPARTID" hover="constant PARTIDtype DefaultPARTID = 0&lt;15:0&gt;" conts="DefaultPARTID">constant PARTIDtype <anchor link="DefaultPARTID" hover="constant PARTIDtype DefaultPARTID = 0&lt;15:0&gt;">DefaultPARTID</anchor> = 0&lt;15:0&gt;;</line>
</pstext>
    </ps>
    <ps name="shared/functions/mpam/DefaultPMG" mylink="shared.functions.mpam.DefaultPMG" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="DefaultPMG" hover="constant PMGtype DefaultPMG = 0&lt;7:0&gt;" conts="DefaultPMG">constant PMGtype    <anchor link="DefaultPMG" hover="constant PMGtype DefaultPMG = 0&lt;7:0&gt;">DefaultPMG</anchor> = 0&lt;7:0&gt;;</line>
</pstext>
    </ps>
    <ps name="shared/functions/mpam/GenMPAMatEL" mylink="shared.functions.mpam.GenMPAMatEL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GenMPAMatEL()</line>
<line>// =============</line>
<line>// Returns MPAMinfo for the specified EL.</line>
<line>// May be called if MPAM is not implemented (but in an version that supports</line>
<line>// MPAM), MPAM is disabled, or in AArch32.  In AArch32, convert the mode to</line>
<line>// EL if can and use that to drive MPAM information generation.  If mode</line>
<line>// cannot be converted, MPAM is not implemented, or MPAM is disabled return</line>
<line>// default MPAM information for the current security state.</line>
<line></line>
<line link="impl-shared.GenMPAMatEL.2" hover="function: MPAMinfo GenMPAMatEL(AccessType acctype, bits(2) el)" conts="GenMPAMatEL">MPAMinfo <anchor link="impl-shared.GenMPAMatEL.2" hover="function: MPAMinfo GenMPAMatEL(AccessType acctype, bits(2) el)">GenMPAMatEL</anchor>(<a link="AccessType" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType</a> acctype, bits(2) el)</line>
<line>    bits(2) mpamEL;</line>
<line>    boolean validEL = FALSE;</line>
<line>    <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security = <a link="impl-shared.SecurityStateAtEL.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)">SecurityStateAtEL</a>(el);</line>
<line>    boolean InD = FALSE;</line>
<line>    boolean InSM = FALSE;</line>
<line>    <a link="PARTIDspaceType" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PARTIDspaceType</a> pspace = <a link="impl-shared.PARTIDspaceFromSS.1" file="shared_pseudocode.xml" hover="function: PARTIDspaceType PARTIDspaceFromSS(SecurityState security)">PARTIDspaceFromSS</a>(security);</line>
<line>    if pspace == <a link="PIdSpace_NonSecure" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_NonSecure</a> &amp;&amp; !<a link="impl-shared.MPAMisEnabled.0" file="shared_pseudocode.xml" hover="function: boolean MPAMisEnabled()">MPAMisEnabled</a>() then</line>
<line>        return <a link="impl-shared.DefaultMPAMinfo.1" file="shared_pseudocode.xml" hover="function: MPAMinfo DefaultMPAMinfo(PARTIDspaceType partidspace)">DefaultMPAMinfo</a>(pspace);</line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        (validEL, mpamEL) = <a link="impl-shared.ELFromM32.1" file="shared_pseudocode.xml" hover="function: (boolean,bits(2)) ELFromM32(bits(5) mode)">ELFromM32</a>(PSTATE.M);</line>
<line>    else</line>
<line>        mpamEL = if acctype == <a link="AccessType_NV2" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_NV2</a> then <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> else el;</line>
<line>        validEL = TRUE;</line>
<line>    case acctype of</line>
<line>        when <a link="AccessType_IFETCH" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IFETCH</a>, <a link="AccessType_IC" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_IC</a></line>
<line>            InD = TRUE;</line>
<line>        when <a link="AccessType_SME" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_SME</a></line>
<line>            InSM = (boolean IMPLEMENTATION_DEFINED "Shared SMCU" ||</line>
<line>                    boolean IMPLEMENTATION_DEFINED "MPAMSM_EL1 label precedence");</line>
<line>        when <a link="AccessType_ASIMD" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_ASIMD</a></line>
<line>            InSM = (<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() &amp;&amp; PSTATE.SM == '1' &amp;&amp;</line>
<line>                    (boolean IMPLEMENTATION_DEFINED "Shared SMCU" ||</line>
<line>                    boolean IMPLEMENTATION_DEFINED "MPAMSM_EL1 label precedence"));</line>
<line>        when <a link="AccessType_SVE" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_SVE</a></line>
<line>            InSM = (<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() &amp;&amp; PSTATE.SM == '1' &amp;&amp;</line>
<line>                    (boolean IMPLEMENTATION_DEFINED "Shared SMCU" ||</line>
<line>                    boolean IMPLEMENTATION_DEFINED "MPAMSM_EL1 label precedence"));</line>
<line>        otherwise</line>
<line>            // Other access types are DATA accesses</line>
<line>            InD = FALSE;</line>
<line>    if !validEL then</line>
<line>        return <a link="impl-shared.DefaultMPAMinfo.1" file="shared_pseudocode.xml" hover="function: MPAMinfo DefaultMPAMinfo(PARTIDspaceType partidspace)">DefaultMPAMinfo</a>(pspace);</line>
<line>    elsif <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() &amp;&amp; MPAMIDR_EL1.HAS_ALTSP == '1' then</line>
<line>        // Substitute alternative PARTID space if selected</line>
<line>        pspace = <a link="impl-shared.AltPARTIDspace.3" file="shared_pseudocode.xml" hover="function: PARTIDspaceType AltPARTIDspace(bits(2) el, SecurityState security, PARTIDspaceType primaryPIdSpace)">AltPARTIDspace</a>(mpamEL, security, pspace);</line>
<line>    if <a link="impl-shared.HaveMPAMv0p1Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMPAMv0p1Ext()">HaveMPAMv0p1Ext</a>() &amp;&amp; MPAMIDR_EL1.HAS_FORCE_NS == '1' then</line>
<line>        if MPAM3_EL3.FORCE_NS == '1' &amp;&amp; security == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>            pspace = <a link="PIdSpace_NonSecure" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_NonSecure</a>;</line>
<line>    if (<a link="impl-shared.HaveMPAMv0p1Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMPAMv0p1Ext()">HaveMPAMv0p1Ext</a>() || <a link="impl-shared.HaveMPAMv1p1Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMPAMv1p1Ext()">HaveMPAMv1p1Ext</a>()) &amp;&amp; MPAMIDR_EL1.HAS_SDEFLT == '1' then</line>
<line>        if MPAM3_EL3.SDEFLT == '1' &amp;&amp; security == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>            return <a link="impl-shared.DefaultMPAMinfo.1" file="shared_pseudocode.xml" hover="function: MPAMinfo DefaultMPAMinfo(PARTIDspaceType partidspace)">DefaultMPAMinfo</a>(pspace);</line>
<line>    if !<a link="impl-shared.MPAMisEnabled.0" file="shared_pseudocode.xml" hover="function: boolean MPAMisEnabled()">MPAMisEnabled</a>() then</line>
<line>        return <a link="impl-shared.DefaultMPAMinfo.1" file="shared_pseudocode.xml" hover="function: MPAMinfo DefaultMPAMinfo(PARTIDspaceType partidspace)">DefaultMPAMinfo</a>(pspace);</line>
<line>    else</line>
<line>        return <a link="impl-shared.genMPAM.4" file="shared_pseudocode.xml" hover="function: MPAMinfo genMPAM(bits(2) el, boolean InD, boolean InSM, PARTIDspaceType pspace)">genMPAM</a>(mpamEL, InD, InSM, pspace);</line>
</pstext>
    </ps>
    <ps name="shared/functions/mpam/GenMPAMcurEL" mylink="shared.functions.mpam.GenMPAMcurEL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GenMPAMcurEL()</line>
<line>// ==============</line>
<line>// Returns MPAMinfo for the current EL and security state.</line>
<line>// May be called if MPAM is not implemented (but in an version that supports</line>
<line>// MPAM), MPAM is disabled, or in AArch32.  In AArch32, convert the mode to</line>
<line>// EL if can and use that to drive MPAM information generation.  If mode</line>
<line>// cannot be converted, MPAM is not implemented, or MPAM is disabled return</line>
<line>// default MPAM information for the current security state.</line>
<line></line>
<line link="impl-shared.GenMPAMcurEL.1" hover="function: MPAMinfo GenMPAMcurEL(AccessType acctype)" conts="GenMPAMcurEL">MPAMinfo <anchor link="impl-shared.GenMPAMcurEL.1" hover="function: MPAMinfo GenMPAMcurEL(AccessType acctype)">GenMPAMcurEL</anchor>(<a link="AccessType" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType</a> acctype)</line>
<line>    return <a link="impl-shared.GenMPAMatEL.2" file="shared_pseudocode.xml" hover="function: MPAMinfo GenMPAMatEL(AccessType acctype, bits(2) el)">GenMPAMatEL</a>(acctype, PSTATE.EL);</line>
</pstext>
    </ps>
    <ps name="shared/functions/mpam/MAP_vPARTID" mylink="shared.functions.mpam.MAP_vPARTID" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MAP_vPARTID()</line>
<line>// =============</line>
<line>// Performs conversion of virtual PARTID into physical PARTID</line>
<line>// Contains all of the error checking and implementation</line>
<line>// choices for the conversion.</line>
<line></line>
<line link="impl-shared.MAP_vPARTID.1" hover="function: (PARTIDtype, boolean) MAP_vPARTID(PARTIDtype vpartid)" conts="MAP_vPARTID">(PARTIDtype, boolean) <anchor link="impl-shared.MAP_vPARTID.1" hover="function: (PARTIDtype, boolean) MAP_vPARTID(PARTIDtype vpartid)">MAP_vPARTID</anchor>(<a link="PARTIDtype" file="shared_pseudocode.xml" hover="type PARTIDtype">PARTIDtype</a> vpartid)</line>
<line>    // should not ever be called if EL2 is not implemented</line>
<line>    // or is implemented but not enabled in the current</line>
<line>    // security state.</line>
<line>    <a link="PARTIDtype" file="shared_pseudocode.xml" hover="type PARTIDtype">PARTIDtype</a> ret;</line>
<line>    boolean err;</line>
<line>    integer virt    = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(vpartid);</line>
<line>    integer vpmrmax = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(MPAMIDR_EL1.VPMR_MAX);</line>
<line></line>
<line>    // vpartid_max is largest vpartid supported</line>
<line>    integer vpartid_max = (vpmrmax &lt;&lt; 2) + 3;</line>
<line></line>
<line>    // One of many ways to reduce vpartid to value less than vpartid_max.</line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(vpartid) &gt; vpartid_max then</line>
<line>        virt = virt MOD (vpartid_max+1);</line>
<line></line>
<line>    // Check for valid mapping entry.</line>
<line>    if MPAMVPMV_EL2&lt;virt&gt; == '1' then</line>
<line>        // vpartid has a valid mapping so access the map.</line>
<line>        ret = <a link="impl-shared.mapvpmw.1" file="shared_pseudocode.xml" hover="function: PARTIDtype mapvpmw(integer vpartid)">mapvpmw</a>(virt);</line>
<line>        err = FALSE;</line>
<line></line>
<line>    // Is the default virtual PARTID valid?</line>
<line>    elsif MPAMVPMV_EL2&lt;0&gt; == '1' then</line>
<line>        // Yes, so use default mapping for vpartid == 0.</line>
<line>        ret = MPAMVPM0_EL2&lt;0 +: 16&gt;;</line>
<line>        err = FALSE;</line>
<line></line>
<line>    // Neither is valid so use default physical PARTID.</line>
<line>    else</line>
<line>        ret = <a link="DefaultPARTID" file="shared_pseudocode.xml" hover="constant PARTIDtype DefaultPARTID = 0&lt;15:0&gt;">DefaultPARTID</a>;</line>
<line>        err = TRUE;</line>
<line></line>
<line>    // Check that the physical PARTID is in-range.</line>
<line>    // This physical PARTID came from a virtual mapping entry.</line>
<line>    integer partid_max = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(MPAMIDR_EL1.PARTID_MAX);</line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(ret) &gt; partid_max then</line>
<line>        // Out of range, so return default physical PARTID</line>
<line>        ret = <a link="DefaultPARTID" file="shared_pseudocode.xml" hover="constant PARTIDtype DefaultPARTID = 0&lt;15:0&gt;">DefaultPARTID</a>;</line>
<line>        err = TRUE;</line>
<line>    return (ret, err);</line>
</pstext>
    </ps>
    <ps name="shared/functions/mpam/MPAMisEnabled" mylink="shared.functions.mpam.MPAMisEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MPAMisEnabled()</line>
<line>// ===============</line>
<line>// Returns TRUE if MPAMisEnabled.</line>
<line></line>
<line link="impl-shared.MPAMisEnabled.0" hover="function: boolean MPAMisEnabled()" conts="MPAMisEnabled">boolean <anchor link="impl-shared.MPAMisEnabled.0" hover="function: boolean MPAMisEnabled()">MPAMisEnabled</anchor>()</line>
<line>    el = <a link="impl-shared.HighestEL.0" file="shared_pseudocode.xml" hover="function: bits(2) HighestEL()">HighestEL</a>();</line>
<line>    case el of</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> return MPAM3_EL3.MPAMEN == '1';</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> return MPAM2_EL2.MPAMEN == '1';</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> return MPAM1_EL1.MPAMEN == '1';</line>
</pstext>
    </ps>
    <ps name="shared/functions/mpam/MPAMisVirtual" mylink="shared.functions.mpam.MPAMisVirtual" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MPAMisVirtual()</line>
<line>// ===============</line>
<line>// Returns TRUE if MPAM is configured to be virtual at EL.</line>
<line></line>
<line link="impl-shared.MPAMisVirtual.1" hover="function: boolean MPAMisVirtual(bits(2) el)" conts="MPAMisVirtual">boolean <anchor link="impl-shared.MPAMisVirtual.1" hover="function: boolean MPAMisVirtual(bits(2) el)">MPAMisVirtual</anchor>(bits(2) el)</line>
<line>    return (MPAMIDR_EL1.HAS_HCR == '1' &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>            ((el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; MPAMHCR_EL2.EL0_VPMEN == '1' &amp;&amp;</line>
<line>               (HCR_EL2.E2H == '0' || HCR_EL2.TGE == '0')) ||</line>
<line>             (el == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; MPAMHCR_EL2.EL1_VPMEN == '1')));</line>
</pstext>
    </ps>
    <ps name="shared/functions/mpam/PARTIDspaceFromSS" mylink="shared.functions.mpam.PARTIDspaceFromSS" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PARTIDspaceFromSS()</line>
<line>// ===================</line>
<line>// Returns the primary PARTID space from the Security State.</line>
<line></line>
<line link="impl-shared.PARTIDspaceFromSS.1" hover="function: PARTIDspaceType PARTIDspaceFromSS(SecurityState security)" conts="PARTIDspaceFromSS">PARTIDspaceType <anchor link="impl-shared.PARTIDspaceFromSS.1" hover="function: PARTIDspaceType PARTIDspaceFromSS(SecurityState security)">PARTIDspaceFromSS</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> security)</line>
<line>    case security of</line>
<line>        when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a></line>
<line>            return <a link="PIdSpace_NonSecure" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_NonSecure</a>;</line>
<line>        when <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a></line>
<line>            return <a link="PIdSpace_Root" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_Root</a>;</line>
<line>        when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a></line>
<line>            return <a link="PIdSpace_Realm" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_Realm</a>;</line>
<line>        when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a></line>
<line>            return <a link="PIdSpace_Secure" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PIdSpace_Secure</a>;</line>
<line>        otherwise</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/mpam/UsePrimarySpaceEL10" mylink="shared.functions.mpam.UsePrimarySpaceEL10" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// UsePrimarySpaceEL10()</line>
<line>// =====================</line>
<line>// Checks whether Primary space is configured in the</line>
<line>// MPAM3_EL3 and MPAM2_EL2 ALTSP control bits that affect</line>
<line>// MPAM ALTSP use at EL1 and EL0.</line>
<line></line>
<line link="impl-shared.UsePrimarySpaceEL10.0" hover="function: boolean UsePrimarySpaceEL10()" conts="UsePrimarySpaceEL10">boolean <anchor link="impl-shared.UsePrimarySpaceEL10.0" hover="function: boolean UsePrimarySpaceEL10()">UsePrimarySpaceEL10</anchor>()</line>
<line>    if MPAM3_EL3.ALTSP_HEN == '0' then</line>
<line>        return MPAM3_EL3.ALTSP_HFC == '0';</line>
<line>    return !<a link="impl-shared.MPAMisEnabled.0" file="shared_pseudocode.xml" hover="function: boolean MPAMisEnabled()">MPAMisEnabled</a>() || !<a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() || MPAM2_EL2.ALTSP_HFC == '0';</line>
</pstext>
    </ps>
    <ps name="shared/functions/mpam/UsePrimarySpaceEL2" mylink="shared.functions.mpam.UsePrimarySpaceEL2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// UsePrimarySpaceEL2()</line>
<line>// ====================</line>
<line>// Checks whether Primary space is configured in the</line>
<line>// MPAM3_EL3 and MPAM2_EL2 ALTSP control bits that affect</line>
<line>// MPAM ALTSP use at EL2.</line>
<line></line>
<line link="impl-shared.UsePrimarySpaceEL2.0" hover="function: boolean UsePrimarySpaceEL2()" conts="UsePrimarySpaceEL2">boolean <anchor link="impl-shared.UsePrimarySpaceEL2.0" hover="function: boolean UsePrimarySpaceEL2()">UsePrimarySpaceEL2</anchor>()</line>
<line>    if MPAM3_EL3.ALTSP_HEN == '0' then</line>
<line>        return MPAM3_EL3.ALTSP_HFC == '0';</line>
<line>    return !<a link="impl-shared.MPAMisEnabled.0" file="shared_pseudocode.xml" hover="function: boolean MPAMisEnabled()">MPAMisEnabled</a>() || MPAM2_EL2.ALTSP_EL2 == '0';</line>
</pstext>
    </ps>
    <ps name="shared/functions/mpam/genMPAM" mylink="shared.functions.mpam.genMPAM" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// genMPAM()</line>
<line>// =========</line>
<line>// Returns MPAMinfo for exception level el.</line>
<line>// If InD is TRUE returns MPAM information using PARTID_I and PMG_I fields</line>
<line>// of MPAMel_ELx register and otherwise using PARTID_D and PMG_D fields.</line>
<line>// If InSM is TRUE returns MPAM information using PARTID_D and PMG_D fields</line>
<line>// of MPAMSM_EL1 register.</line>
<line>// Produces a PARTID in PARTID space pspace.</line>
<line></line>
<line link="impl-shared.genMPAM.4" hover="function: MPAMinfo genMPAM(bits(2) el, boolean InD, boolean InSM, PARTIDspaceType pspace)" conts="genMPAM">MPAMinfo <anchor link="impl-shared.genMPAM.4" hover="function: MPAMinfo genMPAM(bits(2) el, boolean InD, boolean InSM, PARTIDspaceType pspace)">genMPAM</anchor>(bits(2) el, boolean InD, boolean InSM, <a link="PARTIDspaceType" file="shared_pseudocode.xml" hover="enumeration PARTIDspaceType { PIdSpace_Secure, PIdSpace_Root, PIdSpace_Realm, PIdSpace_NonSecure }">PARTIDspaceType</a> pspace)</line>
<line>    <a link="MPAMinfo" file="shared_pseudocode.xml" hover="type MPAMinfo is ( PARTIDspaceType mpam_sp, PARTIDtype partid, PMGtype pmg )">MPAMinfo</a> returninfo;</line>
<line>    <a link="PARTIDtype" file="shared_pseudocode.xml" hover="type PARTIDtype">PARTIDtype</a> partidel;</line>
<line>    boolean perr;</line>
<line>    // gstplk is guest OS application locked by the EL2 hypervisor to</line>
<line>    // only use EL1 the virtual machine's PARTIDs.</line>
<line>    boolean gstplk = (el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp;</line>
<line>                      MPAMHCR_EL2.GSTAPP_PLK == '1' &amp;&amp;</line>
<line>                      HCR_EL2.TGE == '0');</line>
<line>    bits(2) eff_el = if gstplk then <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> else el;</line>
<line>    (partidel, perr) = <a link="impl-shared.genPARTID.3" file="shared_pseudocode.xml" hover="function: (PARTIDtype, boolean) genPARTID(bits(2) el, boolean InD, boolean InSM)">genPARTID</a>(eff_el, InD, InSM);</line>
<line>    <a link="PMGtype" file="shared_pseudocode.xml" hover="type PMGtype">PMGtype</a> groupel  = <a link="impl-shared.genPMG.4" file="shared_pseudocode.xml" hover="function: PMGtype genPMG(bits(2) el, boolean InD, boolean InSM, boolean partid_err)">genPMG</a>(eff_el, InD, InSM, perr);</line>
<line>    returninfo.mpam_sp = pspace;</line>
<line>    returninfo.partid  = partidel;</line>
<line>    returninfo.pmg     = groupel;</line>
<line>    return returninfo;</line>
</pstext>
    </ps>
    <ps name="shared/functions/mpam/genPARTID" mylink="shared.functions.mpam.genPARTID" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// genPARTID()</line>
<line>// ===========</line>
<line>// Returns physical PARTID and error boolean for exception level el.</line>
<line>// If InD is TRUE then PARTID is from MPAMel_ELx.PARTID_I and</line>
<line>// otherwise from MPAMel_ELx.PARTID_D.</line>
<line>// If InSM is TRUE then PARTID is from MPAMSM_EL1.PARTID_D.</line>
<line></line>
<line link="impl-shared.genPARTID.3" hover="function: (PARTIDtype, boolean) genPARTID(bits(2) el, boolean InD, boolean InSM)" conts="genPARTID">(PARTIDtype, boolean) <anchor link="impl-shared.genPARTID.3" hover="function: (PARTIDtype, boolean) genPARTID(bits(2) el, boolean InD, boolean InSM)">genPARTID</anchor>(bits(2) el, boolean InD, boolean InSM)</line>
<line>    <a link="PARTIDtype" file="shared_pseudocode.xml" hover="type PARTIDtype">PARTIDtype</a> partidel = <a link="impl-shared.getMPAM_PARTID.3" file="shared_pseudocode.xml" hover="function: PARTIDtype getMPAM_PARTID(bits(2) MPAMn, boolean InD, boolean InSM)">getMPAM_PARTID</a>(el, InD, InSM);</line>
<line>    <a link="PARTIDtype" file="shared_pseudocode.xml" hover="type PARTIDtype">PARTIDtype</a> partid_max = MPAMIDR_EL1.PARTID_MAX;</line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(partidel) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(partid_max) then</line>
<line>        return (<a link="DefaultPARTID" file="shared_pseudocode.xml" hover="constant PARTIDtype DefaultPARTID = 0&lt;15:0&gt;">DefaultPARTID</a>, TRUE);</line>
<line>    if <a link="impl-shared.MPAMisVirtual.1" file="shared_pseudocode.xml" hover="function: boolean MPAMisVirtual(bits(2) el)">MPAMisVirtual</a>(el) then</line>
<line>        return <a link="impl-shared.MAP_vPARTID.1" file="shared_pseudocode.xml" hover="function: (PARTIDtype, boolean) MAP_vPARTID(PARTIDtype vpartid)">MAP_vPARTID</a>(partidel);</line>
<line>    else</line>
<line>        return (partidel, FALSE);</line>
</pstext>
    </ps>
    <ps name="shared/functions/mpam/genPMG" mylink="shared.functions.mpam.genPMG" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// genPMG()</line>
<line>// ========</line>
<line>// Returns PMG for exception level el and I- or D-side (InD).</line>
<line>// If PARTID generation (genPARTID) encountered an error, genPMG() should be</line>
<line>// called with partid_err as TRUE.</line>
<line></line>
<line link="impl-shared.genPMG.4" hover="function: PMGtype genPMG(bits(2) el, boolean InD, boolean InSM, boolean partid_err)" conts="genPMG">PMGtype <anchor link="impl-shared.genPMG.4" hover="function: PMGtype genPMG(bits(2) el, boolean InD, boolean InSM, boolean partid_err)">genPMG</anchor>(bits(2) el, boolean InD, boolean InSM, boolean partid_err)</line>
<line>    integer pmg_max = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(MPAMIDR_EL1.PMG_MAX);</line>
<line>    // It is CONSTRAINED UNPREDICTABLE whether partid_err forces PMG to</line>
<line>    // use the default or if it uses the PMG from getMPAM_PMG.</line>
<line>    if partid_err then</line>
<line>        return <a link="DefaultPMG" file="shared_pseudocode.xml" hover="constant PMGtype DefaultPMG = 0&lt;7:0&gt;">DefaultPMG</a>;</line>
<line>    <a link="PMGtype" file="shared_pseudocode.xml" hover="type PMGtype">PMGtype</a> groupel = <a link="impl-shared.getMPAM_PMG.3" file="shared_pseudocode.xml" hover="function: PMGtype getMPAM_PMG(bits(2) MPAMn, boolean InD, boolean InSM)">getMPAM_PMG</a>(el, InD, InSM);</line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(groupel) &lt;= pmg_max then</line>
<line>        return groupel;</line>
<line>    return <a link="DefaultPMG" file="shared_pseudocode.xml" hover="constant PMGtype DefaultPMG = 0&lt;7:0&gt;">DefaultPMG</a>;</line>
</pstext>
    </ps>
    <ps name="shared/functions/mpam/getMPAM_PARTID" mylink="shared.functions.mpam.getMPAM_PARTID" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// getMPAM_PARTID()</line>
<line>// ================</line>
<line>// Returns a PARTID from one of the MPAMn_ELx or MPAMSM_EL1 registers.</line>
<line>// If InSM is TRUE, the MPAMSM_EL1 register is used. Otherwise,</line>
<line>// MPAMn selects the MPAMn_ELx register used.</line>
<line>// If InD is TRUE, selects the PARTID_I field of that</line>
<line>// register.  Otherwise, selects the PARTID_D field.</line>
<line></line>
<line link="impl-shared.getMPAM_PARTID.3" hover="function: PARTIDtype getMPAM_PARTID(bits(2) MPAMn, boolean InD, boolean InSM)" conts="getMPAM_PARTID">PARTIDtype <anchor link="impl-shared.getMPAM_PARTID.3" hover="function: PARTIDtype getMPAM_PARTID(bits(2) MPAMn, boolean InD, boolean InSM)">getMPAM_PARTID</anchor>(bits(2) MPAMn, boolean InD, boolean InSM)</line>
<line>    <a link="PARTIDtype" file="shared_pseudocode.xml" hover="type PARTIDtype">PARTIDtype</a> partid;</line>
<line>    boolean el2avail = <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>();</line>
<line></line>
<line>    if InSM then</line>
<line>        partid = MPAMSM_EL1.PARTID_D;</line>
<line>        return partid;</line>
<line></line>
<line>    if InD then</line>
<line>        case MPAMn of</line>
<line>            when '11' partid = MPAM3_EL3.PARTID_I;</line>
<line>            when '10' partid = if el2avail then MPAM2_EL2.PARTID_I else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>            when '01' partid = MPAM1_EL1.PARTID_I;</line>
<line>            when '00' partid = MPAM0_EL1.PARTID_I;</line>
<line>            otherwise partid = <a link="PARTIDtype" file="shared_pseudocode.xml" hover="type PARTIDtype">PARTIDtype</a> UNKNOWN;</line>
<line>    else</line>
<line>        case MPAMn of</line>
<line>            when '11' partid = MPAM3_EL3.PARTID_D;</line>
<line>            when '10' partid = if el2avail then MPAM2_EL2.PARTID_D else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);</line>
<line>            when '01' partid = MPAM1_EL1.PARTID_D;</line>
<line>            when '00' partid = MPAM0_EL1.PARTID_D;</line>
<line>            otherwise partid = <a link="PARTIDtype" file="shared_pseudocode.xml" hover="type PARTIDtype">PARTIDtype</a> UNKNOWN;</line>
<line>    return partid;</line>
</pstext>
    </ps>
    <ps name="shared/functions/mpam/getMPAM_PMG" mylink="shared.functions.mpam.getMPAM_PMG" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// getMPAM_PMG()</line>
<line>// =============</line>
<line>// Returns a PMG from one of the MPAMn_ELx or MPAMSM_EL1 registers.</line>
<line>// If InSM is TRUE, the MPAMSM_EL1 register is used. Otherwise,</line>
<line>// MPAMn selects the MPAMn_ELx register used.</line>
<line>// If InD is TRUE, selects the PMG_I field of that</line>
<line>// register.  Otherwise, selects the PMG_D field.</line>
<line></line>
<line link="impl-shared.getMPAM_PMG.3" hover="function: PMGtype getMPAM_PMG(bits(2) MPAMn, boolean InD, boolean InSM)" conts="getMPAM_PMG">PMGtype <anchor link="impl-shared.getMPAM_PMG.3" hover="function: PMGtype getMPAM_PMG(bits(2) MPAMn, boolean InD, boolean InSM)">getMPAM_PMG</anchor>(bits(2) MPAMn, boolean InD, boolean InSM)</line>
<line>    <a link="PMGtype" file="shared_pseudocode.xml" hover="type PMGtype">PMGtype</a> pmg;</line>
<line>    boolean el2avail = <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>();</line>
<line></line>
<line>    if InSM then</line>
<line>        pmg = MPAMSM_EL1.PMG_D;</line>
<line>        return pmg;</line>
<line></line>
<line>    if InD then</line>
<line>        case MPAMn of</line>
<line>            when '11' pmg = MPAM3_EL3.PMG_I;</line>
<line>            when '10' pmg = if el2avail then MPAM2_EL2.PMG_I else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8);</line>
<line>            when '01' pmg = MPAM1_EL1.PMG_I;</line>
<line>            when '00' pmg = MPAM0_EL1.PMG_I;</line>
<line>            otherwise pmg = <a link="PMGtype" file="shared_pseudocode.xml" hover="type PMGtype">PMGtype</a> UNKNOWN;</line>
<line>    else</line>
<line>        case MPAMn of</line>
<line>            when '11' pmg = MPAM3_EL3.PMG_D;</line>
<line>            when '10' pmg = if el2avail then MPAM2_EL2.PMG_D else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8);</line>
<line>            when '01' pmg = MPAM1_EL1.PMG_D;</line>
<line>            when '00' pmg = MPAM0_EL1.PMG_D;</line>
<line>            otherwise pmg = <a link="PMGtype" file="shared_pseudocode.xml" hover="type PMGtype">PMGtype</a> UNKNOWN;</line>
<line>    return pmg;</line>
</pstext>
    </ps>
    <ps name="shared/functions/mpam/mapvpmw" mylink="shared.functions.mpam.mapvpmw" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// mapvpmw()</line>
<line>// =========</line>
<line>// Map a virtual PARTID into a physical PARTID using</line>
<line>// the MPAMVPMn_EL2 registers.</line>
<line>// vpartid is now assumed in-range and valid (checked by caller)</line>
<line>// returns physical PARTID from mapping entry.</line>
<line></line>
<line link="impl-shared.mapvpmw.1" hover="function: PARTIDtype mapvpmw(integer vpartid)" conts="mapvpmw">PARTIDtype <anchor link="impl-shared.mapvpmw.1" hover="function: PARTIDtype mapvpmw(integer vpartid)">mapvpmw</anchor>(integer vpartid)</line>
<line>    bits(64) vpmw;</line>
<line>    integer  wd = vpartid DIV 4;</line>
<line>    case wd of</line>
<line>        when 0 vpmw = MPAMVPM0_EL2;</line>
<line>        when 1 vpmw = MPAMVPM1_EL2;</line>
<line>        when 2 vpmw = MPAMVPM2_EL2;</line>
<line>        when 3 vpmw = MPAMVPM3_EL2;</line>
<line>        when 4 vpmw = MPAMVPM4_EL2;</line>
<line>        when 5 vpmw = MPAMVPM5_EL2;</line>
<line>        when 6 vpmw = MPAMVPM6_EL2;</line>
<line>        when 7 vpmw = MPAMVPM7_EL2;</line>
<line>        otherwise vpmw = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>    // vpme_lsb selects LSB of field within register</line>
<line>    integer vpme_lsb = (vpartid MOD 4) * 16;</line>
<line>    return vpmw&lt;vpme_lsb +: 16&gt;;</line>
</pstext>
    </ps>
    <ps name="shared/functions/predictionrestrict/ASID" mylink="shared.functions.predictionrestrict.ASID" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ASID[]</line>
<line>// ======</line>
<line>// Effective ASID.</line>
<line></line>
<line link="impl-shared.ASID.read.0" hover="accessor: bits(16) ASID[]" conts="ASID">bits(16) <anchor link="impl-shared.ASID.read.0" hover="accessor: bits(16) ASID[]">ASID</anchor>[]</line>
<line>    if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; HCR_EL2.&lt;E2H, TGE&gt; == '11' then</line>
<line>        if TCR_EL2.A1 == '1' then</line>
<line>            return TTBR1_EL2.ASID;</line>
<line>        else</line>
<line>            return TTBR0_EL2.ASID;</line>
<line></line>
<line>    elsif !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>        if TCR_EL1.A1 == '1' then</line>
<line>            return TTBR1_EL1.ASID;</line>
<line>        else</line>
<line>            return TTBR0_EL1.ASID;</line>
<line></line>
<line>    else</line>
<line>        if TTBCR.EAE == '0' then</line>
<line>            return <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(CONTEXTIDR.ASID, 16);</line>
<line>        else</line>
<line>            if TTBCR.A1 == '1' then</line>
<line>                return <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(TTBR1.ASID, 16);</line>
<line>            else</line>
<line>                return <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(TTBR0.ASID, 16);</line>
</pstext>
    </ps>
    <ps name="shared/functions/predictionrestrict/ExecutionCntxt" mylink="shared.functions.predictionrestrict.ExecutionCntxt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExecutionCntxt</line>
<line>// ===============</line>
<line>// Context information for prediction restriction operation.</line>
<line></line>
<line link="ExecutionCntxt" hover="type ExecutionCntxt is ( boolean is_vmid_valid, boolean all_vmid, bits(16) vmid, boolean is_asid_valid, boolean all_asid, bits(16) asid, bits(2) target_el, SecurityState security, RestrictType restriction )" conts="ExecutionCntxt">type <anchor link="ExecutionCntxt" hover="type ExecutionCntxt is ( boolean is_vmid_valid, boolean all_vmid, bits(16) vmid, boolean is_asid_valid, boolean all_asid, bits(16) asid, bits(2) target_el, SecurityState security, RestrictType restriction )">ExecutionCntxt</anchor> is (</line>
<line>    boolean          is_vmid_valid, // is vmid valid for current context</line>
<line>    boolean          all_vmid,      // should the operation be applied for all vmids</line>
<line>    bits(16)         vmid,          // if all_vmid = FALSE, vmid to which operation is applied</line>
<line>    boolean          is_asid_valid, // is asid valid for current context</line>
<line>    boolean          all_asid,      // should the operation be applied for all asids</line>
<line>    bits(16)         asid,          // if all_asid = FALSE, ASID to which operation is applied</line>
<line>    bits(2)          target_el,     // target EL at which operation is performed</line>
<line>    <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a>    security,</line>
<line>    <a link="RestrictType" file="shared_pseudocode.xml" hover="enumeration RestrictType { RestrictType_DataValue, RestrictType_ControlFlow, RestrictType_CachePrefetch, RestrictType_Other }">RestrictType</a>     restriction    // type of restriction operation</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="shared/functions/predictionrestrict/RESTRICT_PREDICTIONS" mylink="shared.functions.predictionrestrict.RESTRICT_PREDICTIONS" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// RESTRICT_PREDICTIONS()</line>
<line>// ======================</line>
<line>// Clear all speculated values.</line>
<line></line>
<line link="impl-shared.RESTRICT_PREDICTIONS.1" hover="function: RESTRICT_PREDICTIONS(ExecutionCntxt c)" conts="RESTRICT_PREDICTIONS"><anchor link="impl-shared.RESTRICT_PREDICTIONS.1" hover="function: RESTRICT_PREDICTIONS(ExecutionCntxt c)">RESTRICT_PREDICTIONS</anchor>(<a link="ExecutionCntxt" file="shared_pseudocode.xml" hover="type ExecutionCntxt is ( boolean is_vmid_valid, boolean all_vmid, bits(16) vmid, boolean is_asid_valid, boolean all_asid, bits(16) asid, bits(2) target_el, SecurityState security, RestrictType restriction )">ExecutionCntxt</a> c)</line>
<line>    IMPLEMENTATION_DEFINED;</line>
</pstext>
    </ps>
    <ps name="shared/functions/predictionrestrict/RestrictType" mylink="shared.functions.predictionrestrict.RestrictType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// RestrictType</line>
<line>// ============</line>
<line>// Type of restriction on speculation.</line>
<line></line>
<line link="RestrictType" hover="enumeration RestrictType { RestrictType_DataValue, RestrictType_ControlFlow, RestrictType_CachePrefetch, RestrictType_Other }" conts="RestrictType">enumeration <anchor link="RestrictType" hover="enumeration RestrictType { RestrictType_DataValue, RestrictType_ControlFlow, RestrictType_CachePrefetch, RestrictType_Other }">RestrictType</anchor> {</line>
<line link="RestrictType_DataValue" hover="enumeration RestrictType { RestrictType_DataValue, RestrictType_ControlFlow, RestrictType_CachePrefetch, RestrictType_Other }" conts="RestrictType_DataValue">    <anchor link="RestrictType_DataValue" hover="enumeration RestrictType { RestrictType_DataValue, RestrictType_ControlFlow, RestrictType_CachePrefetch, RestrictType_Other }">RestrictType_DataValue</anchor>,</line>
<line link="RestrictType_ControlFlow" hover="enumeration RestrictType { RestrictType_DataValue, RestrictType_ControlFlow, RestrictType_CachePrefetch, RestrictType_Other }" conts="RestrictType_ControlFlow">    <anchor link="RestrictType_ControlFlow" hover="enumeration RestrictType { RestrictType_DataValue, RestrictType_ControlFlow, RestrictType_CachePrefetch, RestrictType_Other }">RestrictType_ControlFlow</anchor>,</line>
<line link="RestrictType_CachePrefetch" hover="enumeration RestrictType { RestrictType_DataValue, RestrictType_ControlFlow, RestrictType_CachePrefetch, RestrictType_Other }" conts="RestrictType_CachePrefetch">    <anchor link="RestrictType_CachePrefetch" hover="enumeration RestrictType { RestrictType_DataValue, RestrictType_ControlFlow, RestrictType_CachePrefetch, RestrictType_Other }">RestrictType_CachePrefetch</anchor>,</line>
<line link="RestrictType_Other" hover="enumeration RestrictType { RestrictType_DataValue, RestrictType_ControlFlow, RestrictType_CachePrefetch, RestrictType_Other }" conts="RestrictType_Other">    <anchor link="RestrictType_Other" hover="enumeration RestrictType { RestrictType_DataValue, RestrictType_ControlFlow, RestrictType_CachePrefetch, RestrictType_Other }">RestrictType_Other</anchor>              // Any other trained speculation mechanisms than those above</line>
<line>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/predictionrestrict/TargetSecurityState" mylink="shared.functions.predictionrestrict.TargetSecurityState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TargetSecurityState()</line>
<line>// =====================</line>
<line>// Decode the target security state for the prediction context.</line>
<line></line>
<line link="impl-shared.TargetSecurityState.2" hover="function: SecurityState TargetSecurityState(bit NS, bit NSE)" conts="TargetSecurityState">SecurityState <anchor link="impl-shared.TargetSecurityState.2" hover="function: SecurityState TargetSecurityState(bit NS, bit NSE)">TargetSecurityState</anchor>(bit NS, bit NSE)</line>
<line>    curr_ss =  <a link="impl-shared.SecurityStateAtEL.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)">SecurityStateAtEL</a>(PSTATE.EL);</line>
<line>    if curr_ss == <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> then</line>
<line>        return <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a>;</line>
<line>    elsif curr_ss == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> then</line>
<line>        case NS of</line>
<line>            when '0' return <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>;</line>
<line>            when '1' return <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a>;</line>
<line>    elsif <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then</line>
<line>        if curr_ss == <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a> then</line>
<line>            case NSE:NS of</line>
<line>                when '00' return <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>;</line>
<line>                when '01' return <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a>;</line>
<line>                when '11' return <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>;</line>
<line>                when '10' return <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>;</line>
<line>        elsif curr_ss == <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a> then</line>
<line>            return <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>;</line>
</pstext>
    </ps>
    <ps name="shared/functions/registers/BranchTo" mylink="shared.functions.registers.BranchTo" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BranchTo()</line>
<line>// ==========</line>
<line>// Set program counter to a new address, with a branch type.</line>
<line>// Parameter branch_conditional indicates whether the executed branch has a conditional encoding.</line>
<line>// In AArch64 state the address might include a tag in the top eight bits.</line>
<line></line>
<line link="impl-shared.BranchTo.3" hover="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)" conts="BranchTo"><anchor link="impl-shared.BranchTo.3" hover="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</anchor>(bits(N) target, <a link="BranchType" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType</a> branch_type, boolean branch_conditional)</line>
<line>    <a link="impl-shared.Hint_Branch.1" file="shared_pseudocode.xml" hover="function: Hint_Branch(BranchType hint)">Hint_Branch</a>(branch_type);</line>
<line>    if N == 32 then</line>
<line>        assert <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>();</line>
<line>        _PC = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(target, 64);</line>
<line>    else</line>
<line>        assert N == 64 &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>();</line>
<line>        bits(64) target_vaddress = <a link="AArch64.BranchAddr.2" file="shared_pseudocode.xml" hover="function: bits(64) AArch64.BranchAddr(bits(64) vaddress, bits(2) el)">AArch64.BranchAddr</a>(target&lt;63:0&gt;, PSTATE.EL);</line>
<line>        if (<a link="impl-shared.HaveBRBExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveBRBExt()">HaveBRBExt</a>() &amp;&amp;</line>
<line>            branch_type IN {<a link="BranchType_DIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</a>, <a link="BranchType_INDIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDIR</a>,</line>
<line>                            <a link="BranchType_DIRCALL" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIRCALL</a>, <a link="BranchType_INDCALL" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDCALL</a>,</line>
<line>                            <a link="BranchType_RET" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_RET</a>}) then</line>
<line>            <a link="impl-aarch64.BRBEBranch.3" file="shared_pseudocode.xml" hover="function: BRBEBranch(BranchType br_type, boolean cond, bits(64) target_address)">BRBEBranch</a>(branch_type, branch_conditional, target_vaddress);</line>
<line>        boolean branch_taken = TRUE;</line>
<line></line>
<line>        if <a link="impl-shared.HaveStatisticalProfiling.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfiling()">HaveStatisticalProfiling</a>() then</line>
<line>            <a link="impl-aarch64.SPEBranch.4" file="shared_pseudocode.xml" hover="function: SPEBranch(bits(N) target, BranchType branch_type, boolean conditional, boolean taken_flag)">SPEBranch</a>(target, branch_type, branch_conditional, branch_taken);</line>
<line></line>
<line>        _PC = target_vaddress;</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/functions/registers/BranchToAddr" mylink="shared.functions.registers.BranchToAddr" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BranchToAddr()</line>
<line>// ==============</line>
<line>// Set program counter to a new address, with a branch type.</line>
<line>// In AArch64 state the address does not include a tag in the top eight bits.</line>
<line></line>
<line link="impl-shared.BranchToAddr.2" hover="function: BranchToAddr(bits(N) target, BranchType branch_type)" conts="BranchToAddr"><anchor link="impl-shared.BranchToAddr.2" hover="function: BranchToAddr(bits(N) target, BranchType branch_type)">BranchToAddr</anchor>(bits(N) target, <a link="BranchType" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType</a> branch_type)</line>
<line>    <a link="impl-shared.Hint_Branch.1" file="shared_pseudocode.xml" hover="function: Hint_Branch(BranchType hint)">Hint_Branch</a>(branch_type);</line>
<line>    if N == 32 then</line>
<line>        assert <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>();</line>
<line>        _PC = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(target, 64);</line>
<line>    else</line>
<line>        assert N == 64 &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>();</line>
<line>        _PC = target&lt;63:0&gt;;</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/functions/registers/BranchType" mylink="shared.functions.registers.BranchType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BranchType</line>
<line>// ==========</line>
<line>// Information associated with a change in control flow.</line>
<line></line>
<line link="BranchType" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}" conts="BranchType">enumeration <anchor link="BranchType" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType</anchor> {</line>
<line link="BranchType_DIRCALL" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}" conts="BranchType_DIRCALL">    <anchor link="BranchType_DIRCALL" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIRCALL</anchor>,     // Direct Branch with link</line>
<line link="BranchType_INDCALL" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}" conts="BranchType_INDCALL">    <anchor link="BranchType_INDCALL" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDCALL</anchor>,     // Indirect Branch with link</line>
<line link="BranchType_ERET" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}" conts="BranchType_ERET">    <anchor link="BranchType_ERET" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_ERET</anchor>,        // Exception return (indirect)</line>
<line link="BranchType_DBGEXIT" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}" conts="BranchType_DBGEXIT">    <anchor link="BranchType_DBGEXIT" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DBGEXIT</anchor>,     // Exit from Debug state</line>
<line link="BranchType_RET" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}" conts="BranchType_RET">    <anchor link="BranchType_RET" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_RET</anchor>,         // Indirect branch with function return hint</line>
<line link="BranchType_DIR" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}" conts="BranchType_DIR">    <anchor link="BranchType_DIR" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</anchor>,         // Direct branch</line>
<line link="BranchType_INDIR" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}" conts="BranchType_INDIR">    <anchor link="BranchType_INDIR" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDIR</anchor>,       // Indirect branch</line>
<line link="BranchType_EXCEPTION" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}" conts="BranchType_EXCEPTION">    <anchor link="BranchType_EXCEPTION" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_EXCEPTION</anchor>,   // Exception entry</line>
<line link="BranchType_TMFAIL" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}" conts="BranchType_TMFAIL">    <anchor link="BranchType_TMFAIL" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_TMFAIL</anchor>,      // Transaction failure</line>
<line link="BranchType_RESET" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}" conts="BranchType_RESET">    <anchor link="BranchType_RESET" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_RESET</anchor>,       // Reset</line>
<line link="BranchType_UNKNOWN" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}" conts="BranchType_UNKNOWN">    <anchor link="BranchType_UNKNOWN" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_UNKNOWN</anchor>};   // Other</line>
</pstext>
    </ps>
    <ps name="shared/functions/registers/Hint_Branch" mylink="shared.functions.registers.Hint_Branch" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Hint_Branch()</line>
<line>// =============</line>
<line>// Report the hint passed to BranchTo() and BranchToAddr(), for consideration when processing</line>
<line>// the next instruction.</line>
<line></line>
<line link="impl-shared.Hint_Branch.1" hover="function: Hint_Branch(BranchType hint)" conts="Hint_Branch"><anchor link="impl-shared.Hint_Branch.1" hover="function: Hint_Branch(BranchType hint)">Hint_Branch</anchor>(<a link="BranchType" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType</a> hint);</line>
</pstext>
    </ps>
    <ps name="shared/functions/registers/NextInstrAddr" mylink="shared.functions.registers.NextInstrAddr" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// NextInstrAddr()</line>
<line>// ===============</line>
<line>// Return address of the sequentially next instruction.</line>
<line></line>
<line link="impl-shared.NextInstrAddr.1" hover="function: bits(N) NextInstrAddr(integer N)" conts="NextInstrAddr">bits(N) <anchor link="impl-shared.NextInstrAddr.1" hover="function: bits(N) NextInstrAddr(integer N)">NextInstrAddr</anchor>(integer N);</line>
</pstext>
    </ps>
    <ps name="shared/functions/registers/ResetExternalDebugRegisters" mylink="shared.functions.registers.ResetExternalDebugRegisters" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ResetExternalDebugRegisters()</line>
<line>// =============================</line>
<line>// Reset the External Debug registers in the Core power domain.</line>
<line></line>
<line link="impl-shared.ResetExternalDebugRegisters.1" hover="function: ResetExternalDebugRegisters(boolean cold_reset)" conts="ResetExternalDebugRegisters"><anchor link="impl-shared.ResetExternalDebugRegisters.1" hover="function: ResetExternalDebugRegisters(boolean cold_reset)">ResetExternalDebugRegisters</anchor>(boolean cold_reset);</line>
</pstext>
    </ps>
    <ps name="shared/functions/registers/ThisInstrAddr" mylink="shared.functions.registers.ThisInstrAddr" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ThisInstrAddr()</line>
<line>// ===============</line>
<line>// Return address of the current instruction.</line>
<line></line>
<line link="impl-shared.ThisInstrAddr.1" hover="function: bits(N) ThisInstrAddr(integer N)" conts="ThisInstrAddr">bits(N) <anchor link="impl-shared.ThisInstrAddr.1" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</anchor>(integer N)</line>
<line>    assert N == 64 || (N == 32 &amp;&amp; <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>());</line>
<line>    return _PC&lt;N-1:0&gt;;</line>
</pstext>
    </ps>
    <ps name="shared/functions/registers/_PC" mylink="shared.functions.registers._PC" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>bits(64) _PC;</line>
</pstext>
    </ps>
    <ps name="shared/functions/registers/_R" mylink="shared.functions.registers._R" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// _R[] - the general-purpose register file</line>
<line>// ========================================</line>
<line></line>
<line>array bits(64) _R[0..30];</line>
</pstext>
    </ps>
    <ps name="shared/functions/sysregisters/SPSR" mylink="shared.functions.sysregisters.SPSR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SPSR[] - non-assignment form</line>
<line>// ============================</line>
<line></line>
<line link="impl-shared.SPSR.read.0" hover="accessor: bits(N) SPSR[]" conts="SPSR">bits(N) <anchor link="impl-shared.SPSR.read.0" hover="accessor: bits(N) SPSR[]">SPSR</anchor>[]</line>
<line>    bits(N) result;</line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        assert N == 32;</line>
<line>        case PSTATE.M of</line>
<line>            when <a link="M32_FIQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_FIQ = '10001'">M32_FIQ</a>      result = SPSR_fiq&lt;N-1:0&gt;;</line>
<line>            when <a link="M32_IRQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_IRQ = '10010'">M32_IRQ</a>      result = SPSR_irq&lt;N-1:0&gt;;</line>
<line>            when <a link="M32_Svc" file="shared_pseudocode.xml" hover="constant bits(5) M32_Svc = '10011'">M32_Svc</a>      result = SPSR_svc&lt;N-1:0&gt;;</line>
<line>            when <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a>  result = SPSR_mon&lt;N-1:0&gt;;</line>
<line>            when <a link="M32_Abort" file="shared_pseudocode.xml" hover="constant bits(5) M32_Abort = '10111'">M32_Abort</a>    result = SPSR_abt&lt;N-1:0&gt;;</line>
<line>            when <a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a>      result = SPSR_hyp&lt;N-1:0&gt;;</line>
<line>            when <a link="M32_Undef" file="shared_pseudocode.xml" hover="constant bits(5) M32_Undef = '11011'">M32_Undef</a>    result = SPSR_und&lt;N-1:0&gt;;</line>
<line>            otherwise         <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>    else</line>
<line>        assert N == 64;</line>
<line>        case PSTATE.EL of</line>
<line>            when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>          result = SPSR_EL1&lt;N-1:0&gt;;</line>
<line>            when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>          result = SPSR_EL2&lt;N-1:0&gt;;</line>
<line>            when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>          result = SPSR_EL3&lt;N-1:0&gt;;</line>
<line>            otherwise         <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>    return result;</line>
<line></line>
<line>// SPSR[] - assignment form</line>
<line>// ========================</line>
<line></line>
<line link="impl-shared.SPSR.write.0" hover="accessor: SPSR[] = bits(N) value" conts="SPSR"><anchor link="impl-shared.SPSR.write.0" hover="accessor: SPSR[] = bits(N) value">SPSR</anchor>[] = bits(N) value</line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        assert N == 32;</line>
<line>        case PSTATE.M of</line>
<line>            when <a link="M32_FIQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_FIQ = '10001'">M32_FIQ</a>      SPSR_fiq&lt;N-1:0&gt; = value&lt;N-1:0&gt;;</line>
<line>            when <a link="M32_IRQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_IRQ = '10010'">M32_IRQ</a>      SPSR_irq&lt;N-1:0&gt; = value&lt;N-1:0&gt;;</line>
<line>            when <a link="M32_Svc" file="shared_pseudocode.xml" hover="constant bits(5) M32_Svc = '10011'">M32_Svc</a>      SPSR_svc&lt;N-1:0&gt; = value&lt;N-1:0&gt;;</line>
<line>            when <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a>  SPSR_mon&lt;N-1:0&gt; = value&lt;N-1:0&gt;;</line>
<line>            when <a link="M32_Abort" file="shared_pseudocode.xml" hover="constant bits(5) M32_Abort = '10111'">M32_Abort</a>    SPSR_abt&lt;N-1:0&gt; = value&lt;N-1:0&gt;;</line>
<line>            when <a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a>      SPSR_hyp&lt;N-1:0&gt; = value&lt;N-1:0&gt;;</line>
<line>            when <a link="M32_Undef" file="shared_pseudocode.xml" hover="constant bits(5) M32_Undef = '11011'">M32_Undef</a>    SPSR_und&lt;N-1:0&gt; = value&lt;N-1:0&gt;;</line>
<line>            otherwise         <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>    else</line>
<line>        assert N == 64;</line>
<line>        case PSTATE.EL of</line>
<line>            when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>          SPSR_EL1&lt;N-1:0&gt; = value&lt;N-1:0&gt;;</line>
<line>            when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>          SPSR_EL2&lt;N-1:0&gt; = value&lt;N-1:0&gt;;</line>
<line>            when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>          SPSR_EL3&lt;N-1:0&gt; = value&lt;N-1:0&gt;;</line>
<line>            otherwise         <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/AArch64.ChkFeat" mylink="shared.functions.system.AArch64.ChkFeat" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AArch64.ChkFeat()</line>
<line>// =================</line>
<line>// Indicates the status of some features</line>
<line></line>
<line link="AArch64.ChkFeat.1" hover="function: bits(64) AArch64.ChkFeat(bits(64) feat_select)" conts="AArch64.ChkFeat">bits(64) <anchor link="AArch64.ChkFeat.1" hover="function: bits(64) AArch64.ChkFeat(bits(64) feat_select)">AArch64.ChkFeat</anchor>(bits(64) feat_select)</line>
<line>    bits(64) feat_en = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>    feat_en[0] = if <a link="impl-shared.HaveGCS.0" file="shared_pseudocode.xml" hover="function: boolean HaveGCS()">HaveGCS</a>() &amp;&amp; <a link="impl-aarch64.GCSEnabled.1" file="shared_pseudocode.xml" hover="function: boolean GCSEnabled(bits(2) el)">GCSEnabled</a>(PSTATE.EL) then '1' else '0';</line>
<line>    return feat_select AND NOT(feat_en);</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/BranchTargetCheck" mylink="shared.functions.system.BranchTargetCheck" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BranchTargetCheck()</line>
<line>// ===================</line>
<line>// This function is executed checks if the current instruction is a valid target for a branch</line>
<line>// taken into, or inside, a guarded page. It is executed on every cycle once the current</line>
<line>// instruction has been decoded and the values of InGuardedPage and BTypeCompatible have been</line>
<line>// determined for the current instruction.</line>
<line></line>
<line link="impl-shared.BranchTargetCheck.0" hover="function: BranchTargetCheck()" conts="BranchTargetCheck"><anchor link="impl-shared.BranchTargetCheck.0" hover="function: BranchTargetCheck()">BranchTargetCheck</anchor>()</line>
<line>    assert <a link="impl-shared.HaveBTIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveBTIExt()">HaveBTIExt</a>() &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>();</line>
<line></line>
<line>    // The branch target check considers two state variables:</line>
<line>    // * InGuardedPage, which is evaluated during instruction fetch.</line>
<line>    // * BTypeCompatible, which is evaluated during instruction decode.</line>
<line>    if InGuardedPage &amp;&amp; PSTATE.BTYPE != '00' &amp;&amp; !BTypeCompatible &amp;&amp; !<a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() then</line>
<line>        bits(64) pc = <a link="impl-shared.ThisInstrAddr.1" file="shared_pseudocode.xml" hover="function: bits(N) ThisInstrAddr(integer N)">ThisInstrAddr</a>(64);</line>
<line>        <a link="AArch64.BranchTargetException.1" file="shared_pseudocode.xml" hover="function: AArch64.BranchTargetException(bits(52) vaddress)">AArch64.BranchTargetException</a>(pc&lt;51:0&gt;);</line>
<line></line>
<line>    boolean branch_instr = <a link="AArch64.ExecutingBROrBLROrRetInstr.0" file="shared_pseudocode.xml" hover="function: boolean AArch64.ExecutingBROrBLROrRetInstr()">AArch64.ExecutingBROrBLROrRetInstr</a>();</line>
<line>    boolean bti_instr    = <a link="AArch64.ExecutingBTIInstr.0" file="shared_pseudocode.xml" hover="function: boolean AArch64.ExecutingBTIInstr()">AArch64.ExecutingBTIInstr</a>();</line>
<line></line>
<line>    // PSTATE.BTYPE defaults to 00 for instructions that do not explictly set BTYPE.</line>
<line>    if !(branch_instr || bti_instr) then</line>
<line>        BTypeNext = '00';</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/ClearEventRegister" mylink="shared.functions.system.ClearEventRegister" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ClearEventRegister()</line>
<line>// ====================</line>
<line>// Clear the Event Register of this PE.</line>
<line></line>
<line link="impl-shared.ClearEventRegister.0" hover="function: ClearEventRegister()" conts="ClearEventRegister"><anchor link="impl-shared.ClearEventRegister.0" hover="function: ClearEventRegister()">ClearEventRegister</anchor>()</line>
<line>    EventRegister = '0';</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/ConditionHolds" mylink="shared.functions.system.ConditionHolds" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ConditionHolds()</line>
<line>// ================</line>
<line>// Return TRUE iff COND currently holds</line>
<line></line>
<line link="impl-shared.ConditionHolds.1" hover="function: boolean ConditionHolds(bits(4) cond)" conts="ConditionHolds">boolean <anchor link="impl-shared.ConditionHolds.1" hover="function: boolean ConditionHolds(bits(4) cond)">ConditionHolds</anchor>(bits(4) cond)</line>
<line>    // Evaluate base condition.</line>
<line>    boolean result;</line>
<line>    case cond&lt;3:1&gt; of</line>
<line>        when '000' result = (PSTATE.Z == '1');                          // EQ or NE</line>
<line>        when '001' result = (PSTATE.C == '1');                          // CS or CC</line>
<line>        when '010' result = (PSTATE.N == '1');                          // MI or PL</line>
<line>        when '011' result = (PSTATE.V == '1');                          // VS or VC</line>
<line>        when '100' result = (PSTATE.C == '1' &amp;&amp; PSTATE.Z == '0');       // HI or LS</line>
<line>        when '101' result = (PSTATE.N == PSTATE.V);                     // GE or LT</line>
<line>        when '110' result = (PSTATE.N == PSTATE.V &amp;&amp; PSTATE.Z == '0');  // GT or LE</line>
<line>        when '111' result = TRUE;                                       // AL</line>
<line></line>
<line>    // Condition flag values in the set '111x' indicate always true</line>
<line>    // Otherwise, invert condition if necessary.</line>
<line>    if cond&lt;0&gt; == '1' &amp;&amp; cond != '1111' then</line>
<line>        result = !result;</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/ConsumptionOfSpeculativeDataBarrier" mylink="shared.functions.system.ConsumptionOfSpeculativeDataBarrier" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ConsumptionOfSpeculativeDataBarrier()</line>
<line>// =====================================</line>
<line></line>
<line link="impl-shared.ConsumptionOfSpeculativeDataBarrier.0" hover="function: ConsumptionOfSpeculativeDataBarrier()" conts="ConsumptionOfSpeculativeDataBarrier"><anchor link="impl-shared.ConsumptionOfSpeculativeDataBarrier.0" hover="function: ConsumptionOfSpeculativeDataBarrier()">ConsumptionOfSpeculativeDataBarrier</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/CurrentInstrSet" mylink="shared.functions.system.CurrentInstrSet" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CurrentInstrSet()</line>
<line>// =================</line>
<line></line>
<line link="impl-shared.CurrentInstrSet.0" hover="function: InstrSet CurrentInstrSet()" conts="CurrentInstrSet">InstrSet <anchor link="impl-shared.CurrentInstrSet.0" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</anchor>()</line>
<line>    <a link="InstrSet" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet</a> result;</line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then</line>
<line>        result = if PSTATE.T == '0' then <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> else <a link="InstrSet_T32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_T32</a>;</line>
<line>        // PSTATE.J is RES0. Implementation of T32EE or Jazelle state not permitted.</line>
<line>    else</line>
<line>        result = <a link="InstrSet_A64" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A64</a>;</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/CurrentPL" mylink="shared.functions.system.CurrentPL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CurrentPL()</line>
<line>// ===========</line>
<line></line>
<line link="impl-shared.CurrentPL.0" hover="function: PrivilegeLevel CurrentPL()" conts="CurrentPL">PrivilegeLevel <anchor link="impl-shared.CurrentPL.0" hover="function: PrivilegeLevel CurrentPL()">CurrentPL</anchor>()</line>
<line>    return <a link="impl-shared.PLOfEL.1" file="shared_pseudocode.xml" hover="function: PrivilegeLevel PLOfEL(bits(2) el)">PLOfEL</a>(PSTATE.EL);</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/CurrentSecurityState" mylink="shared.functions.system.CurrentSecurityState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CurrentSecurityState()</line>
<line>// ======================</line>
<line>// Returns the effective security state at the exception level based off current settings.</line>
<line></line>
<line link="impl-shared.CurrentSecurityState.0" hover="function: SecurityState CurrentSecurityState()" conts="CurrentSecurityState">SecurityState <anchor link="impl-shared.CurrentSecurityState.0" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</anchor>()</line>
<line>    return <a link="impl-shared.SecurityStateAtEL.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)">SecurityStateAtEL</a>(PSTATE.EL);</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/DSBAlias" mylink="shared.functions.system.DSBAlias" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DSBAlias</line>
<line>// ========</line>
<line>// Aliases of DSB.</line>
<line></line>
<line link="DSBAlias" hover="enumeration DSBAlias {DSBAlias_SSBB, DSBAlias_PSSBB, DSBAlias_DSB}" conts="DSBAlias">enumeration <anchor link="DSBAlias" hover="enumeration DSBAlias {DSBAlias_SSBB, DSBAlias_PSSBB, DSBAlias_DSB}">DSBAlias</anchor> {<anchor link="DSBAlias_SSBB" hover="enumeration DSBAlias {DSBAlias_SSBB, DSBAlias_PSSBB, DSBAlias_DSB}">DSBAlias_SSBB</anchor>, <anchor link="DSBAlias_PSSBB" hover="enumeration DSBAlias {DSBAlias_SSBB, DSBAlias_PSSBB, DSBAlias_DSB}">DSBAlias_PSSBB</anchor>, <anchor link="DSBAlias_DSB" hover="enumeration DSBAlias {DSBAlias_SSBB, DSBAlias_PSSBB, DSBAlias_DSB}">DSBAlias_DSB</anchor>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/EL0" mylink="shared.functions.system.EL0" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="EL3" hover="constant bits(2) EL3 = '11'" conts="EL3">constant bits(2) <anchor link="EL3" hover="constant bits(2) EL3 = '11'">EL3</anchor> = '11';</line>
<line link="EL2" hover="constant bits(2) EL2 = '10'" conts="EL2">constant bits(2) <anchor link="EL2" hover="constant bits(2) EL2 = '10'">EL2</anchor> = '10';</line>
<line link="EL1" hover="constant bits(2) EL1 = '01'" conts="EL1">constant bits(2) <anchor link="EL1" hover="constant bits(2) EL1 = '01'">EL1</anchor> = '01';</line>
<line link="EL0" hover="constant bits(2) EL0 = '00'" conts="EL0">constant bits(2) <anchor link="EL0" hover="constant bits(2) EL0 = '00'">EL0</anchor> = '00';</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/EL2Enabled" mylink="shared.functions.system.EL2Enabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EL2Enabled()</line>
<line>// ============</line>
<line>// Returns TRUE if EL2 is present and executing</line>
<line>// - with the PE in Non-secure state when Non-secure EL2 is implemented, or</line>
<line>// - with the PE in Realm state when Realm EL2 is implemented, or</line>
<line>// - with the PE in Secure state when Secure EL2 is implemented and enabled, or</line>
<line>// - when EL3 is not implemented.</line>
<line></line>
<line link="impl-shared.EL2Enabled.0" hover="function: boolean EL2Enabled()" conts="EL2Enabled">boolean <anchor link="impl-shared.EL2Enabled.0" hover="function: boolean EL2Enabled()">EL2Enabled</anchor>()</line>
<line>    return <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; (!<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) || <a link="impl-shared.SCR_GEN.read.0" file="shared_pseudocode.xml" hover="accessor: SCRType SCR_GEN[]">SCR_GEN</a>[].NS == '1' || <a link="impl-shared.IsSecureEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsSecureEL2Enabled()">IsSecureEL2Enabled</a>());</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/EL3SDDUndef" mylink="shared.functions.system.EL3SDDUndef" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EL3SDDUndef()</line>
<line>// =============</line>
<line>// Returns TRUE if in Debug state and EDSCR.SDD is set.</line>
<line></line>
<line link="impl-shared.EL3SDDUndef.0" hover="function: boolean EL3SDDUndef()" conts="EL3SDDUndef">boolean <anchor link="impl-shared.EL3SDDUndef.0" hover="function: boolean EL3SDDUndef()">EL3SDDUndef</anchor>()</line>
<line>    return <a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() &amp;&amp; EDSCR.SDD == '1';</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/EL3SDDUndefPriority" mylink="shared.functions.system.EL3SDDUndefPriority" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EL3SDDUndefPriority()</line>
<line>// =====================</line>
<line>// Returns TRUE if in Debug state, EDSCR.SDD is set, and an EL3 trap by an</line>
<line>// EL3 control register has priority over other traps.</line>
<line>// The IMPLEMENTATION DEFINED priority may be different for each case.</line>
<line></line>
<line link="impl-shared.EL3SDDUndefPriority.0" hover="function: boolean EL3SDDUndefPriority()" conts="EL3SDDUndefPriority">boolean <anchor link="impl-shared.EL3SDDUndefPriority.0" hover="function: boolean EL3SDDUndefPriority()">EL3SDDUndefPriority</anchor>()</line>
<line>    return (<a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() &amp;&amp; EDSCR.SDD == '1' &amp;&amp;</line>
<line>            boolean IMPLEMENTATION_DEFINED "<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> trap priority when SDD == '1'");</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/ELFromM32" mylink="shared.functions.system.ELFromM32" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ELFromM32()</line>
<line>// ===========</line>
<line></line>
<line link="impl-shared.ELFromM32.1" hover="function: (boolean,bits(2)) ELFromM32(bits(5) mode)" conts="ELFromM32">(boolean,bits(2)) <anchor link="impl-shared.ELFromM32.1" hover="function: (boolean,bits(2)) ELFromM32(bits(5) mode)">ELFromM32</anchor>(bits(5) mode)</line>
<line>    // Convert an AArch32 mode encoding to an Exception level.</line>
<line>    // Returns (valid,EL):</line>
<line>    //   'valid' is TRUE if 'mode&lt;4:0&gt;' encodes a mode that is both valid for this implementation</line>
<line>    //           and the current value of SCR.NS/SCR_EL3.NS.</line>
<line>    //   'EL'    is the Exception level decoded from 'mode'.</line>
<line>    bits(2) el;</line>
<line>    boolean valid = !<a link="impl-aarch32.BadMode.1" file="shared_pseudocode.xml" hover="function: boolean BadMode(bits(5) mode)">BadMode</a>(mode);  // Check for modes that are not valid for this implementation</line>
<line>    bits(2) effective_nse_ns = <a link="impl-shared.EffectiveSCR_EL3_NSE.0" file="shared_pseudocode.xml" hover="function: bit EffectiveSCR_EL3_NSE()">EffectiveSCR_EL3_NSE</a>() : <a link="impl-shared.EffectiveSCR_EL3_NS.0" file="shared_pseudocode.xml" hover="function: bit EffectiveSCR_EL3_NS()">EffectiveSCR_EL3_NS</a>();</line>
<line></line>
<line>    case mode of</line>
<line>        when <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a></line>
<line>            el = <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line>        when <a link="M32_Hyp" file="shared_pseudocode.xml" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</a></line>
<line>            el = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>        when <a link="M32_FIQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_FIQ = '10001'">M32_FIQ</a>, <a link="M32_IRQ" file="shared_pseudocode.xml" hover="constant bits(5) M32_IRQ = '10010'">M32_IRQ</a>, <a link="M32_Svc" file="shared_pseudocode.xml" hover="constant bits(5) M32_Svc = '10011'">M32_Svc</a>, <a link="M32_Abort" file="shared_pseudocode.xml" hover="constant bits(5) M32_Abort = '10111'">M32_Abort</a>, <a link="M32_Undef" file="shared_pseudocode.xml" hover="constant bits(5) M32_Undef = '11011'">M32_Undef</a>, <a link="M32_System" file="shared_pseudocode.xml" hover="constant bits(5) M32_System = '11111'">M32_System</a></line>
<line>            // If EL3 is implemented and using AArch32, then these modes are EL3 modes in Secure</line>
<line>            // state, and EL1 modes in Non-secure state. If EL3 is not implemented or is using</line>
<line>            // AArch64, then these modes are EL1 modes.</line>
<line>            el = (if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; !<a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() &amp;&amp; SCR.NS == '0' then <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> else <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line>        when <a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a></line>
<line>            el = <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;</line>
<line>        otherwise</line>
<line>            valid = FALSE;           // Passed an illegal mode value</line>
<line></line>
<line>    if valid &amp;&amp; el == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> &amp;&amp; <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.SCR_GEN.read.0" file="shared_pseudocode.xml" hover="accessor: SCRType SCR_GEN[]">SCR_GEN</a>[].NS == '0' then</line>
<line>        valid = FALSE;               // EL2 only valid in Non-secure state in AArch32</line>
<line></line>
<line>    elsif valid &amp;&amp; <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() &amp;&amp; effective_nse_ns == '10' then</line>
<line>        valid = FALSE;               // Illegal Exception Return from EL3 if SCR_EL3.&lt;NSE,NS&gt;</line>
<line>                                     // selects a reserved encoding</line>
<line></line>
<line>    if !valid then el = bits(2) UNKNOWN;</line>
<line>    return (valid, el);</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/ELFromSPSR" mylink="shared.functions.system.ELFromSPSR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ELFromSPSR()</line>
<line>// ============</line>
<line></line>
<line>// Convert an SPSR value encoding to an Exception level.</line>
<line>// Returns (valid,EL):</line>
<line>//   'valid' is TRUE if 'spsr&lt;4:0&gt;' encodes a valid mode for the current state.</line>
<line>//   'EL'    is the Exception level decoded from 'spsr'.</line>
<line></line>
<line link="impl-shared.ELFromSPSR.1" hover="function: (boolean,bits(2)) ELFromSPSR(bits(N) spsr)" conts="ELFromSPSR">(boolean,bits(2)) <anchor link="impl-shared.ELFromSPSR.1" hover="function: (boolean,bits(2)) ELFromSPSR(bits(N) spsr)">ELFromSPSR</anchor>(bits(N) spsr)</line>
<line>    bits(2) el;</line>
<line>    boolean valid;</line>
<line>    bits(2) effective_nse_ns;</line>
<line>    if spsr&lt;4&gt; == '0' then      // AArch64 state</line>
<line>        el = spsr&lt;3:2&gt;;</line>
<line>        effective_nse_ns = <a link="impl-shared.EffectiveSCR_EL3_NSE.0" file="shared_pseudocode.xml" hover="function: bit EffectiveSCR_EL3_NSE()">EffectiveSCR_EL3_NSE</a>() : <a link="impl-shared.EffectiveSCR_EL3_NS.0" file="shared_pseudocode.xml" hover="function: bit EffectiveSCR_EL3_NS()">EffectiveSCR_EL3_NS</a>();</line>
<line>        if !<a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then</line>
<line>            valid = FALSE;      // No AArch64 support</line>
<line>        elsif !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(el) then</line>
<line>            valid = FALSE;      // Exception level not implemented</line>
<line>        elsif spsr&lt;1&gt; == '1' then</line>
<line>            valid = FALSE;      // M[1] must be 0</line>
<line>        elsif el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; spsr&lt;0&gt; == '1' then</line>
<line>            valid = FALSE;      // for EL0, M[0] must be 0</line>
<line>        elsif <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() &amp;&amp; el != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> &amp;&amp; effective_nse_ns == '10' then</line>
<line>            valid = FALSE;      // Only EL3 valid in Root state</line>
<line>        elsif el == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> &amp;&amp; <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; !<a link="impl-shared.IsSecureEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsSecureEL2Enabled()">IsSecureEL2Enabled</a>() &amp;&amp; SCR_EL3.NS == '0' then</line>
<line>            valid = FALSE;      // Unless Secure EL2 is enabled, EL2 valid only in Non-secure state</line>
<line>        else</line>
<line>            valid = TRUE;</line>
<line>    elsif <a link="impl-shared.HaveAArch32.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32()">HaveAArch32</a>() then    // AArch32 state</line>
<line>        (valid, el) = <a link="impl-shared.ELFromM32.1" file="shared_pseudocode.xml" hover="function: (boolean,bits(2)) ELFromM32(bits(5) mode)">ELFromM32</a>(spsr&lt;4:0&gt;);</line>
<line>    else</line>
<line>        valid = FALSE;</line>
<line></line>
<line>    if !valid then el = bits(2) UNKNOWN;</line>
<line>    return (valid,el);</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/ELIsInHost" mylink="shared.functions.system.ELIsInHost" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ELIsInHost()</line>
<line>// ============</line>
<line></line>
<line link="impl-shared.ELIsInHost.1" hover="function: boolean ELIsInHost(bits(2) el)" conts="ELIsInHost">boolean <anchor link="impl-shared.ELIsInHost.1" hover="function: boolean ELIsInHost(bits(2) el)">ELIsInHost</anchor>(bits(2) el)</line>
<line>    if !<a link="impl-shared.HaveVirtHostExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</a>() || <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>        return FALSE;</line>
<line>    case el of</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            return FALSE;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            return <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.E2H == '1';</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a></line>
<line>            return FALSE;</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>            return <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; HCR_EL2.&lt;E2H,TGE&gt; == '11';</line>
<line>        otherwise</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/ELStateUsingAArch32" mylink="shared.functions.system.ELStateUsingAArch32" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ELStateUsingAArch32()</line>
<line>// =====================</line>
<line></line>
<line link="impl-shared.ELStateUsingAArch32.2" hover="function: boolean ELStateUsingAArch32(bits(2) el, boolean secure)" conts="ELStateUsingAArch32">boolean <anchor link="impl-shared.ELStateUsingAArch32.2" hover="function: boolean ELStateUsingAArch32(bits(2) el, boolean secure)">ELStateUsingAArch32</anchor>(bits(2) el, boolean secure)</line>
<line>    // See ELStateUsingAArch32K() for description. Must only be called in circumstances where</line>
<line>    // result is valid (typically, that means 'el IN {EL1,EL2,EL3}').</line>
<line>    (known, aarch32) = <a link="impl-shared.ELStateUsingAArch32K.2" file="shared_pseudocode.xml" hover="function: (boolean,boolean) ELStateUsingAArch32K(bits(2) el, boolean secure)">ELStateUsingAArch32K</a>(el, secure);</line>
<line>    assert known;</line>
<line>    return aarch32;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/ELStateUsingAArch32K" mylink="shared.functions.system.ELStateUsingAArch32K" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ELStateUsingAArch32K()</line>
<line>// ======================</line>
<line></line>
<line link="impl-shared.ELStateUsingAArch32K.2" hover="function: (boolean,boolean) ELStateUsingAArch32K(bits(2) el, boolean secure)" conts="ELStateUsingAArch32K">(boolean,boolean) <anchor link="impl-shared.ELStateUsingAArch32K.2" hover="function: (boolean,boolean) ELStateUsingAArch32K(bits(2) el, boolean secure)">ELStateUsingAArch32K</anchor>(bits(2) el, boolean secure)</line>
<line>    // Returns (known, aarch32):</line>
<line>    //   'known'   is FALSE for EL0 if the current Exception level is not EL0 and EL1 is</line>
<line>    //             using AArch64, since it cannot determine the state of EL0; TRUE otherwise.</line>
<line>    //   'aarch32' is TRUE if the specified Exception level is using AArch32; FALSE otherwise.</line>
<line>    if !<a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(el) then</line>
<line>        return (TRUE, FALSE);   // Exception level is using AArch64</line>
<line>    elsif secure &amp;&amp; el == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>        return (TRUE, FALSE);   // Secure EL2 is using AArch64</line>
<line>    elsif !<a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then</line>
<line>        return (TRUE, TRUE);    // Highest Exception level, therefore all levels are using AArch32</line>
<line></line>
<line>    // Remainder of function deals with the interprocessing cases when highest</line>
<line>    // Exception level is using AArch64</line>
<line></line>
<line>    boolean aarch32 = boolean UNKNOWN;</line>
<line>    boolean known = TRUE;</line>
<line></line>
<line>    aarch32_below_el3 = (<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; (!secure || !<a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>() || SCR_EL3.EEL2 == '0') &amp;&amp;</line>
<line>                         SCR_EL3.RW == '0');</line>
<line>    aarch32_at_el1 = (aarch32_below_el3 ||</line>
<line>                      (<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; (!secure || (<a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>() &amp;&amp; SCR_EL3.EEL2 == '1')) &amp;&amp;</line>
<line>                       !(<a link="impl-shared.HaveVirtHostExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</a>() &amp;&amp; HCR_EL2.&lt;E2H,TGE&gt; == '11') &amp;&amp;</line>
<line>                       HCR_EL2.RW == '0'));</line>
<line>    if el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !aarch32_at_el1 then       // Only know if EL0 using AArch32 from PSTATE</line>
<line>        if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>            aarch32 = PSTATE.nRW == '1';       // EL0 controlled by PSTATE</line>
<line>        else</line>
<line>            known = FALSE;                     // EL0 state is UNKNOWN</line>
<line>    else</line>
<line>        aarch32 = (aarch32_below_el3 &amp;&amp; el != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) || (aarch32_at_el1 &amp;&amp; el IN {<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>,<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>});</line>
<line></line>
<line>    if !known then aarch32 = boolean UNKNOWN;</line>
<line>    return (known, aarch32);</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/ELUsingAArch32" mylink="shared.functions.system.ELUsingAArch32" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ELUsingAArch32()</line>
<line>// ================</line>
<line></line>
<line link="impl-shared.ELUsingAArch32.1" hover="function: boolean ELUsingAArch32(bits(2) el)" conts="ELUsingAArch32">boolean <anchor link="impl-shared.ELUsingAArch32.1" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</anchor>(bits(2) el)</line>
<line>    return <a link="impl-shared.ELStateUsingAArch32.2" file="shared_pseudocode.xml" hover="function: boolean ELStateUsingAArch32(bits(2) el, boolean secure)">ELStateUsingAArch32</a>(el, <a link="impl-shared.IsSecureBelowEL3.0" file="shared_pseudocode.xml" hover="function: boolean IsSecureBelowEL3()">IsSecureBelowEL3</a>());</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/ELUsingAArch32K" mylink="shared.functions.system.ELUsingAArch32K" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ELUsingAArch32K()</line>
<line>// =================</line>
<line></line>
<line link="impl-shared.ELUsingAArch32K.1" hover="function: (boolean,boolean) ELUsingAArch32K(bits(2) el)" conts="ELUsingAArch32K">(boolean,boolean) <anchor link="impl-shared.ELUsingAArch32K.1" hover="function: (boolean,boolean) ELUsingAArch32K(bits(2) el)">ELUsingAArch32K</anchor>(bits(2) el)</line>
<line>    return <a link="impl-shared.ELStateUsingAArch32K.2" file="shared_pseudocode.xml" hover="function: (boolean,boolean) ELStateUsingAArch32K(bits(2) el, boolean secure)">ELStateUsingAArch32K</a>(el, <a link="impl-shared.IsSecureBelowEL3.0" file="shared_pseudocode.xml" hover="function: boolean IsSecureBelowEL3()">IsSecureBelowEL3</a>());</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/EffectiveEA" mylink="shared.functions.system.EffectiveEA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EffectiveEA()</line>
<line>// =============</line>
<line>// Returns effective SCR_EL3.EA value</line>
<line></line>
<line link="impl-shared.EffectiveEA.0" hover="function: bit EffectiveEA()" conts="EffectiveEA">bit <anchor link="impl-shared.EffectiveEA.0" hover="function: bit EffectiveEA()">EffectiveEA</anchor>()</line>
<line>    if <a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>() &amp;&amp; EDSCR.SDD == '0' then</line>
<line>        return '0';</line>
<line>    else</line>
<line>        return if <a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then SCR_EL3.EA else SCR.EA;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/EffectiveSCR_EL3_NS" mylink="shared.functions.system.EffectiveSCR_EL3_NS" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EffectiveSCR_EL3_NS()</line>
<line>// =====================</line>
<line>// Return Effective SCR_EL3.NS value.</line>
<line></line>
<line link="impl-shared.EffectiveSCR_EL3_NS.0" hover="function: bit EffectiveSCR_EL3_NS()" conts="EffectiveSCR_EL3_NS">bit <anchor link="impl-shared.EffectiveSCR_EL3_NS.0" hover="function: bit EffectiveSCR_EL3_NS()">EffectiveSCR_EL3_NS</anchor>()</line>
<line>    if !<a link="impl-shared.HaveSecureState.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureState()">HaveSecureState</a>() then</line>
<line>        return '1';</line>
<line>    elsif !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        return '0';</line>
<line>    else</line>
<line>        return SCR_EL3.NS;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/EffectiveSCR_EL3_NSE" mylink="shared.functions.system.EffectiveSCR_EL3_NSE" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EffectiveSCR_EL3_NSE()</line>
<line>// ======================</line>
<line>// Return Effective SCR_EL3.NSE value.</line>
<line></line>
<line link="impl-shared.EffectiveSCR_EL3_NSE.0" hover="function: bit EffectiveSCR_EL3_NSE()" conts="EffectiveSCR_EL3_NSE">bit <anchor link="impl-shared.EffectiveSCR_EL3_NSE.0" hover="function: bit EffectiveSCR_EL3_NSE()">EffectiveSCR_EL3_NSE</anchor>()</line>
<line>    return if !<a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then '0' else SCR_EL3.NSE;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/EffectiveSCR_EL3_RW" mylink="shared.functions.system.EffectiveSCR_EL3_RW" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EffectiveSCR_EL3_RW()</line>
<line>// =====================</line>
<line>// Returns effective SCR_EL3.RW value</line>
<line></line>
<line link="impl-shared.EffectiveSCR_EL3_RW.0" hover="function: bit EffectiveSCR_EL3_RW()" conts="EffectiveSCR_EL3_RW">bit <anchor link="impl-shared.EffectiveSCR_EL3_RW.0" hover="function: bit EffectiveSCR_EL3_RW()">EffectiveSCR_EL3_RW</anchor>()</line>
<line>    if !<a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then</line>
<line>        return '0';</line>
<line>    if !<a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; !<a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>        return '1';</line>
<line>    if <a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then</line>
<line>        if !<a link="impl-shared.HaveAArch32EL.1" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; SCR_EL3.NS == '1' then</line>
<line>            return '1';</line>
<line>        if <a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>() &amp;&amp; SCR_EL3.EEL2 == '1' &amp;&amp; SCR_EL3.NS == '0' then</line>
<line>            return '1';</line>
<line>    return SCR_EL3.RW;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/EffectiveTGE" mylink="shared.functions.system.EffectiveTGE" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EffectiveTGE()</line>
<line>// ==============</line>
<line>// Returns effective TGE value</line>
<line></line>
<line link="impl-shared.EffectiveTGE.0" hover="function: bit EffectiveTGE()" conts="EffectiveTGE">bit <anchor link="impl-shared.EffectiveTGE.0" hover="function: bit EffectiveTGE()">EffectiveTGE</anchor>()</line>
<line>    if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() then</line>
<line>        return if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then HCR.TGE else HCR_EL2.TGE;</line>
<line>    else</line>
<line>        return '0';        // Effective value of TGE is zero</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/EndOfInstruction" mylink="shared.functions.system.EndOfInstruction" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EndOfInstruction()</line>
<line>// ==================</line>
<line>// Terminate processing of the current instruction.</line>
<line></line>
<line link="impl-shared.EndOfInstruction.0" hover="function: EndOfInstruction()" conts="EndOfInstruction"><anchor link="impl-shared.EndOfInstruction.0" hover="function: EndOfInstruction()">EndOfInstruction</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/EnterLowPowerState" mylink="shared.functions.system.EnterLowPowerState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EnterLowPowerState()</line>
<line>// ====================</line>
<line>// PE enters a low-power state.</line>
<line></line>
<line link="impl-shared.EnterLowPowerState.0" hover="function: EnterLowPowerState()" conts="EnterLowPowerState"><anchor link="impl-shared.EnterLowPowerState.0" hover="function: EnterLowPowerState()">EnterLowPowerState</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/EventRegister" mylink="shared.functions.system.EventRegister" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>bits(1) EventRegister;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/ExceptionalOccurrenceTargetState" mylink="shared.functions.system.ExceptionalOccurrenceTargetState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExceptionalOccurrenceTargetState</line>
<line>// ================================</line>
<line>// Enumeration to represent the target state of an Exceptional Occurrence.</line>
<line>// The Exceptional Occurrence can be either Exception or Debug State entry.</line>
<line></line>
<line link="ExceptionalOccurrenceTargetState" hover="enumeration ExceptionalOccurrenceTargetState { AArch32_NonDebugState, AArch64_NonDebugState, DebugState }" conts="ExceptionalOccurrenceTargetState">enumeration <anchor link="ExceptionalOccurrenceTargetState" hover="enumeration ExceptionalOccurrenceTargetState { AArch32_NonDebugState, AArch64_NonDebugState, DebugState }">ExceptionalOccurrenceTargetState</anchor> {</line>
<line link="AArch32_NonDebugState" hover="enumeration ExceptionalOccurrenceTargetState { AArch32_NonDebugState, AArch64_NonDebugState, DebugState }" conts="AArch32_NonDebugState">    <anchor link="AArch32_NonDebugState" hover="enumeration ExceptionalOccurrenceTargetState { AArch32_NonDebugState, AArch64_NonDebugState, DebugState }">AArch32_NonDebugState</anchor>,</line>
<line link="AArch64_NonDebugState" hover="enumeration ExceptionalOccurrenceTargetState { AArch32_NonDebugState, AArch64_NonDebugState, DebugState }" conts="AArch64_NonDebugState">    <anchor link="AArch64_NonDebugState" hover="enumeration ExceptionalOccurrenceTargetState { AArch32_NonDebugState, AArch64_NonDebugState, DebugState }">AArch64_NonDebugState</anchor>,</line>
<line link="DebugState" hover="enumeration ExceptionalOccurrenceTargetState { AArch32_NonDebugState, AArch64_NonDebugState, DebugState }" conts="DebugState">    <anchor link="DebugState" hover="enumeration ExceptionalOccurrenceTargetState { AArch32_NonDebugState, AArch64_NonDebugState, DebugState }">DebugState</anchor></line>
<line>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/FIQPending" mylink="shared.functions.system.FIQPending" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FIQPending()</line>
<line>// ============</line>
<line>// Returns a tuple indicating if there is any pending physical FIQ</line>
<line>// and if the pending FIQ has superpriority.</line>
<line></line>
<line link="impl-shared.FIQPending.0" hover="function: (boolean, boolean) FIQPending()" conts="FIQPending">(boolean, boolean) <anchor link="impl-shared.FIQPending.0" hover="function: (boolean, boolean) FIQPending()">FIQPending</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/GetAccumulatedFPExceptions" mylink="shared.functions.system.GetAccumulatedFPExceptions" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GetAccumulatedFPExceptions()</line>
<line>// ============================</line>
<line>// Returns FP exceptions accumulated by the PE.</line>
<line></line>
<line link="impl-shared.GetAccumulatedFPExceptions.0" hover="function: bits(8) GetAccumulatedFPExceptions()" conts="GetAccumulatedFPExceptions">bits(8) <anchor link="impl-shared.GetAccumulatedFPExceptions.0" hover="function: bits(8) GetAccumulatedFPExceptions()">GetAccumulatedFPExceptions</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/GetLoadStoreType" mylink="shared.functions.system.GetLoadStoreType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GetLoadStoreType()</line>
<line>// ==================</line>
<line>// Returns the Load/Store Type. Used when a Translation fault,</line>
<line>// Access flag fault, or Permission fault generates a Data Abort.</line>
<line></line>
<line link="impl-shared.GetLoadStoreType.0" hover="function: bits(2) GetLoadStoreType()" conts="GetLoadStoreType">bits(2) <anchor link="impl-shared.GetLoadStoreType.0" hover="function: bits(2) GetLoadStoreType()">GetLoadStoreType</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/GetPSRFromPSTATE" mylink="shared.functions.system.GetPSRFromPSTATE" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GetPSRFromPSTATE()</line>
<line>// ==================</line>
<line>// Return a PSR value which represents the current PSTATE</line>
<line></line>
<line link="impl-shared.GetPSRFromPSTATE.2" hover="function: bits(N) GetPSRFromPSTATE(ExceptionalOccurrenceTargetState targetELState, integer N)" conts="GetPSRFromPSTATE">bits(N) <anchor link="impl-shared.GetPSRFromPSTATE.2" hover="function: bits(N) GetPSRFromPSTATE(ExceptionalOccurrenceTargetState targetELState, integer N)">GetPSRFromPSTATE</anchor>(<a link="ExceptionalOccurrenceTargetState" file="shared_pseudocode.xml" hover="enumeration ExceptionalOccurrenceTargetState { AArch32_NonDebugState, AArch64_NonDebugState, DebugState }">ExceptionalOccurrenceTargetState</a> targetELState, integer N)</line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; targetELState == <a link="AArch32_NonDebugState" file="shared_pseudocode.xml" hover="enumeration ExceptionalOccurrenceTargetState { AArch32_NonDebugState, AArch64_NonDebugState, DebugState }">AArch32_NonDebugState</a> then</line>
<line>        assert N == 32;</line>
<line>    else</line>
<line>        assert N == 64;</line>
<line></line>
<line>    bits(N) spsr = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(N);</line>
<line>    spsr&lt;31:28&gt; = PSTATE.&lt;N,Z,C,V&gt;;</line>
<line>    if <a link="impl-shared.HavePANExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePANExt()">HavePANExt</a>() then spsr&lt;22&gt; = PSTATE.PAN;</line>
<line>    spsr&lt;20&gt;    = PSTATE.IL;</line>
<line>    if PSTATE.nRW == '1' then                           // AArch32 state</line>
<line>        spsr&lt;27&gt;    = PSTATE.Q;</line>
<line>        spsr&lt;26:25&gt; = PSTATE.IT&lt;1:0&gt;;</line>
<line>        if <a link="impl-shared.HaveSSBSExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveSSBSExt()">HaveSSBSExt</a>() then spsr&lt;23&gt; = PSTATE.SSBS;</line>
<line>        if <a link="impl-shared.HaveDITExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDITExt()">HaveDITExt</a>() then</line>
<line>            if targetELState == <a link="AArch32_NonDebugState" file="shared_pseudocode.xml" hover="enumeration ExceptionalOccurrenceTargetState { AArch32_NonDebugState, AArch64_NonDebugState, DebugState }">AArch32_NonDebugState</a> then</line>
<line>                spsr&lt;21&gt; = PSTATE.DIT;</line>
<line>            else                                        // AArch64_NonDebugState or DebugState</line>
<line>                spsr&lt;24&gt; = PSTATE.DIT;</line>
<line>        if targetELState IN {<a link="AArch64_NonDebugState" file="shared_pseudocode.xml" hover="enumeration ExceptionalOccurrenceTargetState { AArch32_NonDebugState, AArch64_NonDebugState, DebugState }">AArch64_NonDebugState</a>, <a link="DebugState" file="shared_pseudocode.xml" hover="enumeration ExceptionalOccurrenceTargetState { AArch32_NonDebugState, AArch64_NonDebugState, DebugState }">DebugState</a>} then</line>
<line>            spsr&lt;21&gt; = PSTATE.SS;</line>
<line>        spsr&lt;19:16&gt; = PSTATE.GE;</line>
<line>        spsr&lt;15:10&gt; = PSTATE.IT&lt;7:2&gt;;</line>
<line>        spsr&lt;9&gt;     = PSTATE.E;</line>
<line>        spsr&lt;8:6&gt;   = PSTATE.&lt;A,I,F&gt;;                   // No PSTATE.D in AArch32 state</line>
<line>        spsr&lt;5&gt;     = PSTATE.T;</line>
<line>        assert PSTATE.M&lt;4&gt; == PSTATE.nRW;               // bit [4] is the discriminator</line>
<line>        spsr&lt;4:0&gt;   = PSTATE.M;</line>
<line>    else                                                // AArch64 state</line>
<line>        if <a link="impl-shared.HaveMTEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEExt()">HaveMTEExt</a>() then spsr&lt;25&gt; = PSTATE.TCO;</line>
<line>        if <a link="impl-shared.HaveGCS.0" file="shared_pseudocode.xml" hover="function: boolean HaveGCS()">HaveGCS</a>() then spsr&lt;34&gt; = PSTATE.EXLOCK;</line>
<line>        if <a link="impl-shared.HaveDITExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDITExt()">HaveDITExt</a>() then spsr&lt;24&gt; = PSTATE.DIT;</line>
<line>        if <a link="impl-shared.HaveUAOExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveUAOExt()">HaveUAOExt</a>() then spsr&lt;23&gt; = PSTATE.UAO;</line>
<line>        spsr&lt;21&gt;    = PSTATE.SS;</line>
<line>        if <a link="impl-shared.HaveFeatNMI.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatNMI()">HaveFeatNMI</a>() then spsr&lt;13&gt; = PSTATE.ALLINT;</line>
<line>        if <a link="impl-shared.HaveSSBSExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveSSBSExt()">HaveSSBSExt</a>() then spsr&lt;12&gt; = PSTATE.SSBS;</line>
<line>        if <a link="impl-shared.HaveBTIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveBTIExt()">HaveBTIExt</a>() then spsr&lt;11:10&gt; = PSTATE.BTYPE;</line>
<line>        spsr&lt;9:6&gt;   = PSTATE.&lt;D,A,I,F&gt;;</line>
<line>        spsr&lt;4&gt;     = PSTATE.nRW;</line>
<line>        spsr&lt;3:2&gt;   = PSTATE.EL;</line>
<line>        spsr&lt;0&gt;     = PSTATE.SP;</line>
<line>    return spsr;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/HasArchVersion" mylink="shared.functions.system.HasArchVersion" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HasArchVersion()</line>
<line>// ================</line>
<line>// Returns TRUE if the implemented architecture includes the extensions defined in the specified</line>
<line>// architecture version.</line>
<line></line>
<line>boolean HasArchVersion(ArchVersion version)</line>
<line>    return Variant(version);</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/HaveAArch32" mylink="shared.functions.system.HaveAArch32" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveAArch32()</line>
<line>// =============</line>
<line>// Return TRUE if AArch32 state is supported at at least EL0.</line>
<line></line>
<line link="impl-shared.HaveAArch32.0" hover="function: boolean HaveAArch32()" conts="HaveAArch32">boolean <anchor link="impl-shared.HaveAArch32.0" hover="function: boolean HaveAArch32()">HaveAArch32</anchor>()</line>
<line>    return boolean IMPLEMENTATION_DEFINED "AArch32 state is supported at at least <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>";</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/HaveAArch32EL" mylink="shared.functions.system.HaveAArch32EL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveAArch32EL()</line>
<line>// ===============</line>
<line></line>
<line link="impl-shared.HaveAArch32EL.1" hover="function: boolean HaveAArch32EL(bits(2) el)" conts="HaveAArch32EL">boolean <anchor link="impl-shared.HaveAArch32EL.1" hover="function: boolean HaveAArch32EL(bits(2) el)">HaveAArch32EL</anchor>(bits(2) el)</line>
<line>    // Return TRUE if Exception level 'el' supports AArch32 in this implementation</line>
<line>    if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(el) then</line>
<line>        return FALSE;                    // The Exception level is not implemented</line>
<line>    elsif !<a link="impl-shared.HaveAArch32.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32()">HaveAArch32</a>() then</line>
<line>        return FALSE;                    // No Exception level can use AArch32</line>
<line>    elsif !<a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then</line>
<line>        return TRUE;                     // All Exception levels are using AArch32</line>
<line>    elsif el == <a link="impl-shared.HighestEL.0" file="shared_pseudocode.xml" hover="function: bits(2) HighestEL()">HighestEL</a>() then</line>
<line>        return FALSE;                    // The highest Exception level is using AArch64</line>
<line>    elsif el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        return TRUE;                     // EL0 must support using AArch32 if any AArch32</line>
<line>    return boolean IMPLEMENTATION_DEFINED;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/HaveAArch64" mylink="shared.functions.system.HaveAArch64" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveAArch64()</line>
<line>// =============</line>
<line>// Return TRUE if the highest Exception level is using AArch64 state.</line>
<line></line>
<line link="impl-shared.HaveAArch64.0" hover="function: boolean HaveAArch64()" conts="HaveAArch64">boolean <anchor link="impl-shared.HaveAArch64.0" hover="function: boolean HaveAArch64()">HaveAArch64</anchor>()</line>
<line>    return boolean IMPLEMENTATION_DEFINED "Highest EL using AArch64";</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/HaveEL" mylink="shared.functions.system.HaveEL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveEL()</line>
<line>// ========</line>
<line>// Return TRUE if Exception level 'el' is supported</line>
<line></line>
<line link="impl-shared.HaveEL.1" hover="function: boolean HaveEL(bits(2) el)" conts="HaveEL">boolean <anchor link="impl-shared.HaveEL.1" hover="function: boolean HaveEL(bits(2) el)">HaveEL</anchor>(bits(2) el)</line>
<line>    if el IN {<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>,<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>} then</line>
<line>        return TRUE;                             // EL1 and EL0 must exist</line>
<line>    return boolean IMPLEMENTATION_DEFINED;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/HaveELUsingSecurityState" mylink="shared.functions.system.HaveELUsingSecurityState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveELUsingSecurityState()</line>
<line>// ==========================</line>
<line>// Returns TRUE if Exception level 'el' with Security state 'secure' is supported,</line>
<line>// FALSE otherwise.</line>
<line></line>
<line link="impl-shared.HaveELUsingSecurityState.2" hover="function: boolean HaveELUsingSecurityState(bits(2) el, boolean secure)" conts="HaveELUsingSecurityState">boolean <anchor link="impl-shared.HaveELUsingSecurityState.2" hover="function: boolean HaveELUsingSecurityState(bits(2) el, boolean secure)">HaveELUsingSecurityState</anchor>(bits(2) el, boolean secure)</line>
<line></line>
<line>    case el of</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a></line>
<line>            assert secure;</line>
<line>            return <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a></line>
<line>            if secure then</line>
<line>                return <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; <a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>();</line>
<line>            else</line>
<line>                return <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>        otherwise</line>
<line>            return (<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) ||</line>
<line>                    (secure == boolean IMPLEMENTATION_DEFINED "Secure-only implementation"));</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/HaveFP16Ext" mylink="shared.functions.system.HaveFP16Ext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveFP16Ext()</line>
<line>// =============</line>
<line>// Return TRUE if FP16 extension is supported</line>
<line></line>
<line link="impl-shared.HaveFP16Ext.0" hover="function: boolean HaveFP16Ext()" conts="HaveFP16Ext">boolean <anchor link="impl-shared.HaveFP16Ext.0" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</anchor>()</line>
<line>    return IsFeatureImplemented(FEAT_FP16);</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/HaveSecureState" mylink="shared.functions.system.HaveSecureState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HaveSecureState()</line>
<line>// =================</line>
<line>// Return TRUE if Secure State is supported.</line>
<line></line>
<line link="impl-shared.HaveSecureState.0" hover="function: boolean HaveSecureState()" conts="HaveSecureState">boolean <anchor link="impl-shared.HaveSecureState.0" hover="function: boolean HaveSecureState()">HaveSecureState</anchor>()</line>
<line>    if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        return <a link="impl-shared.SecureOnlyImplementation.0" file="shared_pseudocode.xml" hover="function: boolean SecureOnlyImplementation()">SecureOnlyImplementation</a>();</line>
<line>    if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() &amp;&amp; !<a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>() then</line>
<line>        return FALSE;</line>
<line>    return TRUE;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/HighestEL" mylink="shared.functions.system.HighestEL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HighestEL()</line>
<line>// ===========</line>
<line>// Returns the highest implemented Exception level.</line>
<line></line>
<line link="impl-shared.HighestEL.0" hover="function: bits(2) HighestEL()" conts="HighestEL">bits(2) <anchor link="impl-shared.HighestEL.0" hover="function: bits(2) HighestEL()">HighestEL</anchor>()</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        return <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line>    elsif <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>        return <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>    else</line>
<line>        return <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/Hint_CLRBHB" mylink="shared.functions.system.Hint_CLRBHB" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Hint_CLRBHB()</line>
<line>// =============</line>
<line>// Provides a hint to clear the branch history for the current context.</line>
<line></line>
<line link="impl-shared.Hint_CLRBHB.0" hover="function: Hint_CLRBHB()" conts="Hint_CLRBHB"><anchor link="impl-shared.Hint_CLRBHB.0" hover="function: Hint_CLRBHB()">Hint_CLRBHB</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/Hint_DGH" mylink="shared.functions.system.Hint_DGH" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Hint_DGH()</line>
<line>// ==========</line>
<line>// Provides a hint to close any gathering occurring within the micro-architecture.</line>
<line></line>
<line link="impl-shared.Hint_DGH.0" hover="function: Hint_DGH()" conts="Hint_DGH"><anchor link="impl-shared.Hint_DGH.0" hover="function: Hint_DGH()">Hint_DGH</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/Hint_WFE" mylink="shared.functions.system.Hint_WFE" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Hint_WFE()</line>
<line>// ==========</line>
<line>// Provides a hint indicating that the PE can enter a low-power state</line>
<line>// and remain there until a wakeup event occurs or, for WFET,  a local</line>
<line>// timeout event is generated when the virtual timer value equals or</line>
<line>// exceeds the supplied threshold value.</line>
<line></line>
<line link="impl-shared.Hint_WFE.2" hover="function: Hint_WFE(integer localtimeout, WFxType wfxtype)" conts="Hint_WFE"><anchor link="impl-shared.Hint_WFE.2" hover="function: Hint_WFE(integer localtimeout, WFxType wfxtype)">Hint_WFE</anchor>(integer localtimeout, <a link="WFxType" file="shared_pseudocode.xml" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType</a> wfxtype)</line>
<line>    if <a link="impl-shared.IsEventRegisterSet.0" file="shared_pseudocode.xml" hover="function: boolean IsEventRegisterSet()">IsEventRegisterSet</a>() then</line>
<line>        <a link="impl-shared.ClearEventRegister.0" file="shared_pseudocode.xml" hover="function: ClearEventRegister()">ClearEventRegister</a>();</line>
<line>    elsif <a link="impl-shared.HaveFeatWFxT.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatWFxT()">HaveFeatWFxT</a>() &amp;&amp; <a link="impl-shared.LocalTimeoutEvent.1" file="shared_pseudocode.xml" hover="function: boolean LocalTimeoutEvent(integer localtimeout)">LocalTimeoutEvent</a>(localtimeout) then</line>
<line>        // No further operation if the local timeout has expired.</line>
<line>        <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
<line>    else</line>
<line>        bits(2) target_el;</line>
<line>        trap = FALSE;</line>
<line>        if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>            // Check for traps described by the OS which may be EL1 or EL2.</line>
<line>            if <a link="impl-shared.HaveTWEDExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTWEDExt()">HaveTWEDExt</a>() then</line>
<line>                sctlr     = <a link="impl-aarch64.SCTLR.read.0" file="shared_pseudocode.xml" hover="accessor: SCTLRType SCTLR[]">SCTLR</a>[];</line>
<line>                trap      = sctlr.nTWE == '0';</line>
<line>                target_el = <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>            else</line>
<line>                <a link="AArch64.CheckForWFxTrap.2" file="shared_pseudocode.xml" hover="function: AArch64.CheckForWFxTrap(bits(2) target_el, WFxType wfxtype)">AArch64.CheckForWFxTrap</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, wfxtype);</line>
<line>        if !trap &amp;&amp; PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>            // Check for traps described by the Hypervisor.</line>
<line>            if <a link="impl-shared.HaveTWEDExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTWEDExt()">HaveTWEDExt</a>() then</line>
<line>                trap      = HCR_EL2.TWE == '1';</line>
<line>                target_el = <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>            else</line>
<line>                <a link="AArch64.CheckForWFxTrap.2" file="shared_pseudocode.xml" hover="function: AArch64.CheckForWFxTrap(bits(2) target_el, WFxType wfxtype)">AArch64.CheckForWFxTrap</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, wfxtype);</line>
<line></line>
<line>        if !trap &amp;&amp; <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; PSTATE.EL != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then</line>
<line>            // Check for traps described by the Secure Monitor.</line>
<line>            if <a link="impl-shared.HaveTWEDExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTWEDExt()">HaveTWEDExt</a>() then</line>
<line>                trap      = SCR_EL3.TWE == '1';</line>
<line>                target_el = <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line>            else</line>
<line>                <a link="AArch64.CheckForWFxTrap.2" file="shared_pseudocode.xml" hover="function: AArch64.CheckForWFxTrap(bits(2) target_el, WFxType wfxtype)">AArch64.CheckForWFxTrap</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, wfxtype);</line>
<line></line>
<line>        if trap &amp;&amp; PSTATE.EL != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then</line>
<line>            // Determine if trap delay is enabled and delay amount</line>
<line>            (delay_enabled, delay) = <a link="impl-aarch64.WFETrapDelay.1" file="shared_pseudocode.xml" hover="function: (boolean, integer) WFETrapDelay(bits(2) target_el)">WFETrapDelay</a>(target_el);</line>
<line>            if !<a link="impl-aarch64.WaitForEventUntilDelay.2" file="shared_pseudocode.xml" hover="function: boolean WaitForEventUntilDelay(boolean delay_enabled, integer delay)">WaitForEventUntilDelay</a>(delay_enabled, delay) then</line>
<line>                // Event did not arrive before delay expired so trap WFE</line>
<line>                <a link="AArch64.WFxTrap.2" file="shared_pseudocode.xml" hover="function: AArch64.WFxTrap(WFxType wfxtype, bits(2) target_el)">AArch64.WFxTrap</a>(wfxtype, target_el);</line>
<line>        else</line>
<line>            <a link="impl-shared.WaitForEvent.1" file="shared_pseudocode.xml" hover="function: WaitForEvent(integer localtimeout)">WaitForEvent</a>(localtimeout);</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/Hint_WFI" mylink="shared.functions.system.Hint_WFI" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Hint_WFI()</line>
<line>// ==========</line>
<line>// Provides a hint indicating that the PE can enter a low-power state and</line>
<line>// remain there until a wakeup event occurs or, for WFIT, a local timeout</line>
<line>// event is generated when the virtual timer value equals or exceeds the</line>
<line>// supplied threshold value.</line>
<line></line>
<line link="impl-shared.Hint_WFI.2" hover="function: Hint_WFI(integer localtimeout, WFxType wfxtype)" conts="Hint_WFI"><anchor link="impl-shared.Hint_WFI.2" hover="function: Hint_WFI(integer localtimeout, WFxType wfxtype)">Hint_WFI</anchor>(integer localtimeout, <a link="WFxType" file="shared_pseudocode.xml" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType</a> wfxtype)</line>
<line>    if <a link="impl-shared.HaveTME.0" file="shared_pseudocode.xml" hover="function: boolean HaveTME()">HaveTME</a>() &amp;&amp; TSTATE.depth &gt; 0 then</line>
<line>        <a link="impl-aarch64.FailTransaction.2" file="shared_pseudocode.xml" hover="function: FailTransaction(TMFailure cause, boolean retry)">FailTransaction</a>(<a link="TMFailure_ERR" file="shared_pseudocode.xml" hover="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_ERR</a>, FALSE);</line>
<line></line>
<line>    if <a link="impl-shared.InterruptPending.0" file="shared_pseudocode.xml" hover="function: boolean InterruptPending()">InterruptPending</a>() || (<a link="impl-shared.HaveFeatWFxT.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatWFxT()">HaveFeatWFxT</a>() &amp;&amp; <a link="impl-shared.LocalTimeoutEvent.1" file="shared_pseudocode.xml" hover="function: boolean LocalTimeoutEvent(integer localtimeout)">LocalTimeoutEvent</a>(localtimeout)) then</line>
<line>        // No further operation if an interrupt is pending or the local timeout has expired.</line>
<line>        <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</line>
<line>    else</line>
<line>        if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>            // Check for traps described by the OS.</line>
<line>            <a link="AArch64.CheckForWFxTrap.2" file="shared_pseudocode.xml" hover="function: AArch64.CheckForWFxTrap(bits(2) target_el, WFxType wfxtype)">AArch64.CheckForWFxTrap</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>, wfxtype);</line>
<line>        if PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; !<a link="impl-shared.IsInHost.0" file="shared_pseudocode.xml" hover="function: boolean IsInHost()">IsInHost</a>() then</line>
<line>            // Check for traps described by the Hypervisor.</line>
<line>            <a link="AArch64.CheckForWFxTrap.2" file="shared_pseudocode.xml" hover="function: AArch64.CheckForWFxTrap(bits(2) target_el, WFxType wfxtype)">AArch64.CheckForWFxTrap</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>, wfxtype);</line>
<line>        if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; PSTATE.EL != <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then</line>
<line>            // Check for traps described by the Secure Monitor.</line>
<line>            <a link="AArch64.CheckForWFxTrap.2" file="shared_pseudocode.xml" hover="function: AArch64.CheckForWFxTrap(bits(2) target_el, WFxType wfxtype)">AArch64.CheckForWFxTrap</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>, wfxtype);</line>
<line>        <a link="impl-shared.WaitForInterrupt.1" file="shared_pseudocode.xml" hover="function: WaitForInterrupt(integer localtimeout)">WaitForInterrupt</a>(localtimeout);</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/Hint_Yield" mylink="shared.functions.system.Hint_Yield" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Hint_Yield()</line>
<line>// ============</line>
<line>// Provides a hint that the task performed by a thread is of low</line>
<line>// importance so that it could yield to improve overall performance.</line>
<line></line>
<line link="impl-shared.Hint_Yield.0" hover="function: Hint_Yield()" conts="Hint_Yield"><anchor link="impl-shared.Hint_Yield.0" hover="function: Hint_Yield()">Hint_Yield</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/IRQPending" mylink="shared.functions.system.IRQPending" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IRQPending()</line>
<line>// ============</line>
<line>// Returns a tuple indicating if there is any pending physical IRQ</line>
<line>// and if the pending IRQ has superpriority.</line>
<line></line>
<line link="impl-shared.IRQPending.0" hover="function: (boolean, boolean) IRQPending()" conts="IRQPending">(boolean, boolean) <anchor link="impl-shared.IRQPending.0" hover="function: (boolean, boolean) IRQPending()">IRQPending</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/IllegalExceptionReturn" mylink="shared.functions.system.IllegalExceptionReturn" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IllegalExceptionReturn()</line>
<line>// ========================</line>
<line></line>
<line link="impl-shared.IllegalExceptionReturn.1" hover="function: boolean IllegalExceptionReturn(bits(N) spsr)" conts="IllegalExceptionReturn">boolean <anchor link="impl-shared.IllegalExceptionReturn.1" hover="function: boolean IllegalExceptionReturn(bits(N) spsr)">IllegalExceptionReturn</anchor>(bits(N) spsr)</line>
<line></line>
<line>    // Check for illegal return:</line>
<line>    //   * To an unimplemented Exception level.</line>
<line>    //   * To EL2 in Secure state, when SecureEL2 is not enabled.</line>
<line>    //   * To EL0 using AArch64 state, with SPSR.M[0]==1.</line>
<line>    //   * To AArch64 state with SPSR.M[1]==1.</line>
<line>    //   * To AArch32 state with an illegal value of SPSR.M.</line>
<line>    (valid, target) = <a link="impl-shared.ELFromSPSR.1" file="shared_pseudocode.xml" hover="function: (boolean,bits(2)) ELFromSPSR(bits(N) spsr)">ELFromSPSR</a>(spsr);</line>
<line>    if !valid then return TRUE;</line>
<line></line>
<line>    // Check for return to higher Exception level</line>
<line>    if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(target) &gt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(PSTATE.EL) then return TRUE;</line>
<line></line>
<line>    spsr_mode_is_aarch32 = (spsr&lt;4&gt; == '1');</line>
<line></line>
<line>    // Check for illegal return:</line>
<line>    //   * To EL1, EL2 or EL3 with register width specified in the SPSR different from the</line>
<line>    //     Execution state used in the Exception level being returned to, as determined by</line>
<line>    //     the SCR_EL3.RW or HCR_EL2.RW bits, or as configured from reset.</line>
<line>    //   * To EL0 using AArch64 state when EL1 is using AArch32 state as determined by the</line>
<line>    //     SCR_EL3.RW or HCR_EL2.RW bits or as configured from reset.</line>
<line>    //   * To AArch64 state from AArch32 state (should be caught by above)</line>
<line>    (known, target_el_is_aarch32) = <a link="impl-shared.ELUsingAArch32K.1" file="shared_pseudocode.xml" hover="function: (boolean,boolean) ELUsingAArch32K(bits(2) el)">ELUsingAArch32K</a>(target);</line>
<line>    assert known || (target == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> &amp;&amp; !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>));</line>
<line>    if known &amp;&amp; spsr_mode_is_aarch32 != target_el_is_aarch32 then return TRUE;</line>
<line></line>
<line>    // Check for illegal return from AArch32 to AArch64</line>
<line>    if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; !spsr_mode_is_aarch32 then return TRUE;</line>
<line></line>
<line>    // Check for illegal return to EL1 when HCR.TGE is set and when either of</line>
<line>    // * SecureEL2 is enabled.</line>
<line>    // * SecureEL2 is not enabled and EL1 is in Non-secure state.</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; target == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> &amp;&amp; HCR_EL2.TGE == '1' then</line>
<line>        if (!<a link="impl-shared.IsSecureBelowEL3.0" file="shared_pseudocode.xml" hover="function: boolean IsSecureBelowEL3()">IsSecureBelowEL3</a>() || <a link="impl-shared.IsSecureEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsSecureEL2Enabled()">IsSecureEL2Enabled</a>()) then return TRUE;</line>
<line></line>
<line>    if (<a link="impl-shared.HaveGCS.0" file="shared_pseudocode.xml" hover="function: boolean HaveGCS()">HaveGCS</a>() &amp;&amp; PSTATE.EXLOCK == '0' &amp;&amp; PSTATE.EL == target &amp;&amp;</line>
<line>        <a link="impl-aarch64.GetCurrentEXLOCKEN.0" file="shared_pseudocode.xml" hover="function: boolean GetCurrentEXLOCKEN()">GetCurrentEXLOCKEN</a>() &amp;&amp; !<a link="impl-shared.Halted.0" file="shared_pseudocode.xml" hover="function: boolean Halted()">Halted</a>()) then</line>
<line>        return TRUE;</line>
<line></line>
<line>    return FALSE;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/InstrSet" mylink="shared.functions.system.InstrSet" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// InstrSet</line>
<line>// ========</line>
<line></line>
<line link="InstrSet" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}" conts="InstrSet">enumeration <anchor link="InstrSet" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet</anchor> {<anchor link="InstrSet_A64" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A64</anchor>, <anchor link="InstrSet_A32" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</anchor>, <anchor link="InstrSet_T32" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_T32</anchor>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/InstructionSynchronizationBarrier" mylink="shared.functions.system.InstructionSynchronizationBarrier" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// InstructionSynchronizationBarrier()</line>
<line>// ===================================</line>
<line link="impl-shared.InstructionSynchronizationBarrier.0" hover="function: InstructionSynchronizationBarrier()" conts="InstructionSynchronizationBarrier"><anchor link="impl-shared.InstructionSynchronizationBarrier.0" hover="function: InstructionSynchronizationBarrier()">InstructionSynchronizationBarrier</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/InterruptPending" mylink="shared.functions.system.InterruptPending" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// InterruptPending()</line>
<line>// ==================</line>
<line>// Returns TRUE if there are any pending physical or virtual</line>
<line>// interrupts, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.InterruptPending.0" hover="function: boolean InterruptPending()" conts="InterruptPending">boolean <anchor link="impl-shared.InterruptPending.0" hover="function: boolean InterruptPending()">InterruptPending</anchor>()</line>
<line>    boolean pending_virtual_interrupt = FALSE;</line>
<line>    (irq_pending, -) = <a link="impl-shared.IRQPending.0" file="shared_pseudocode.xml" hover="function: (boolean, boolean) IRQPending()">IRQPending</a>();</line>
<line>    (fiq_pending, -) = <a link="impl-shared.FIQPending.0" file="shared_pseudocode.xml" hover="function: (boolean, boolean) FIQPending()">FIQPending</a>();</line>
<line>    boolean pending_physical_interrupt = (irq_pending || fiq_pending ||</line>
<line>                                          <a link="impl-shared.IsPhysicalSErrorPending.0" file="shared_pseudocode.xml" hover="function: boolean IsPhysicalSErrorPending()">IsPhysicalSErrorPending</a>());</line>
<line></line>
<line>    if <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>() &amp;&amp; PSTATE.EL IN {<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>, <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>} &amp;&amp; HCR_EL2.TGE == '0' then</line>
<line>        boolean virq_pending = HCR_EL2.IMO == '1' &amp;&amp; (<a link="impl-shared.VirtualIRQPending.0" file="shared_pseudocode.xml" hover="function: boolean VirtualIRQPending()">VirtualIRQPending</a>() || HCR_EL2.VI == '1') ;</line>
<line>        boolean vfiq_pending = HCR_EL2.FMO == '1' &amp;&amp; (<a link="impl-shared.VirtualFIQPending.0" file="shared_pseudocode.xml" hover="function: boolean VirtualFIQPending()">VirtualFIQPending</a>() || HCR_EL2.VF == '1');</line>
<line>        boolean vsei_pending = HCR_EL2.AMO == '1' &amp;&amp; (<a link="impl-shared.IsVirtualSErrorPending.0" file="shared_pseudocode.xml" hover="function: boolean IsVirtualSErrorPending()">IsVirtualSErrorPending</a>() ||</line>
<line>                                                      HCR_EL2.VSE == '1');</line>
<line>        pending_virtual_interrupt = vsei_pending || virq_pending || vfiq_pending;</line>
<line></line>
<line>    return pending_physical_interrupt || pending_virtual_interrupt;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/IsASEInstruction" mylink="shared.functions.system.IsASEInstruction" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsASEInstruction()</line>
<line>// ==================</line>
<line>// Returns TRUE if the current instruction is an ASIMD or SVE vector instruction.</line>
<line></line>
<line link="impl-shared.IsASEInstruction.0" hover="function: boolean IsASEInstruction()" conts="IsASEInstruction">boolean <anchor link="impl-shared.IsASEInstruction.0" hover="function: boolean IsASEInstruction()">IsASEInstruction</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/IsCMOWControlledInstruction" mylink="shared.functions.system.IsCMOWControlledInstruction" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsCMOWControlledInstruction()</line>
<line>// =============================</line>
<line>// When using AArch64, returns TRUE if the current instruction is one of IC IVAU,</line>
<line>// DC CIVAC, DC CIGDVAC, or DC CIGVAC.</line>
<line>// When using AArch32, returns TRUE if the current instruction is ICIMVAU or DCCIMVAC.</line>
<line></line>
<line link="impl-shared.IsCMOWControlledInstruction.0" hover="function: boolean IsCMOWControlledInstruction()" conts="IsCMOWControlledInstruction">boolean <anchor link="impl-shared.IsCMOWControlledInstruction.0" hover="function: boolean IsCMOWControlledInstruction()">IsCMOWControlledInstruction</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/IsCurrentSecurityState" mylink="shared.functions.system.IsCurrentSecurityState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsCurrentSecurityState()</line>
<line>// ========================</line>
<line>// Returns TRUE if the current Security state matches</line>
<line>// the given Security state, and FALSE otherwise.</line>
<line></line>
<line link="impl-shared.IsCurrentSecurityState.1" hover="function: boolean IsCurrentSecurityState(SecurityState ss)" conts="IsCurrentSecurityState">boolean <anchor link="impl-shared.IsCurrentSecurityState.1" hover="function: boolean IsCurrentSecurityState(SecurityState ss)">IsCurrentSecurityState</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss)</line>
<line>    return <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() == ss;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/IsEventRegisterSet" mylink="shared.functions.system.IsEventRegisterSet" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsEventRegisterSet()</line>
<line>// ====================</line>
<line>// Return TRUE if the Event Register of this PE is set, and FALSE if it is clear.</line>
<line></line>
<line link="impl-shared.IsEventRegisterSet.0" hover="function: boolean IsEventRegisterSet()" conts="IsEventRegisterSet">boolean <anchor link="impl-shared.IsEventRegisterSet.0" hover="function: boolean IsEventRegisterSet()">IsEventRegisterSet</anchor>()</line>
<line>    return EventRegister == '1';</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/IsHighestEL" mylink="shared.functions.system.IsHighestEL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsHighestEL()</line>
<line>// =============</line>
<line>// Returns TRUE if given exception level is the highest exception level implemented</line>
<line></line>
<line link="impl-shared.IsHighestEL.1" hover="function: boolean IsHighestEL(bits(2) el)" conts="IsHighestEL">boolean <anchor link="impl-shared.IsHighestEL.1" hover="function: boolean IsHighestEL(bits(2) el)">IsHighestEL</anchor>(bits(2) el)</line>
<line>    return <a link="impl-shared.HighestEL.0" file="shared_pseudocode.xml" hover="function: bits(2) HighestEL()">HighestEL</a>() == el;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/IsInHost" mylink="shared.functions.system.IsInHost" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsInHost()</line>
<line>// ==========</line>
<line></line>
<line link="impl-shared.IsInHost.0" hover="function: boolean IsInHost()" conts="IsInHost">boolean <anchor link="impl-shared.IsInHost.0" hover="function: boolean IsInHost()">IsInHost</anchor>()</line>
<line>    return <a link="impl-shared.ELIsInHost.1" file="shared_pseudocode.xml" hover="function: boolean ELIsInHost(bits(2) el)">ELIsInHost</a>(PSTATE.EL);</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/IsSecure" mylink="shared.functions.system.IsSecure" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsSecure()</line>
<line>// ==========</line>
<line>// Returns TRUE if current Exception level is in Secure state.</line>
<line></line>
<line link="impl-shared.IsSecure.0" hover="function: boolean IsSecure()" conts="IsSecure">boolean <anchor link="impl-shared.IsSecure.0" hover="function: boolean IsSecure()">IsSecure</anchor>()</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; PSTATE.EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then</line>
<line>        return TRUE;</line>
<line>    elsif <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() &amp;&amp; PSTATE.M == <a link="M32_Monitor" file="shared_pseudocode.xml" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</a> then</line>
<line>        return TRUE;</line>
<line>    return <a link="impl-shared.IsSecureBelowEL3.0" file="shared_pseudocode.xml" hover="function: boolean IsSecureBelowEL3()">IsSecureBelowEL3</a>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/IsSecureBelowEL3" mylink="shared.functions.system.IsSecureBelowEL3" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsSecureBelowEL3()</line>
<line>// ==================</line>
<line>// Return TRUE if an Exception level below EL3 is in Secure state</line>
<line>// or would be following an exception return to that level.</line>
<line>//</line>
<line>// Differs from IsSecure in that it ignores the current EL or Mode</line>
<line>// in considering security state.</line>
<line>// That is, if at AArch64 EL3 or in AArch32 Monitor mode, whether an</line>
<line>// exception return would pass to Secure or Non-secure state.</line>
<line></line>
<line link="impl-shared.IsSecureBelowEL3.0" hover="function: boolean IsSecureBelowEL3()" conts="IsSecureBelowEL3">boolean <anchor link="impl-shared.IsSecureBelowEL3.0" hover="function: boolean IsSecureBelowEL3()">IsSecureBelowEL3</anchor>()</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        return <a link="impl-shared.SCR_GEN.read.0" file="shared_pseudocode.xml" hover="accessor: SCRType SCR_GEN[]">SCR_GEN</a>[].NS == '0';</line>
<line>    elsif <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; (!<a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>() || !<a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>()) then</line>
<line>        // If Secure EL2 is not an architecture option then we must be Non-secure.</line>
<line>        return FALSE;</line>
<line>    else</line>
<line>        // TRUE if processor is Secure or FALSE if Non-secure.</line>
<line>        return boolean IMPLEMENTATION_DEFINED "Secure-only implementation";</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/IsSecureEL2Enabled" mylink="shared.functions.system.IsSecureEL2Enabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsSecureEL2Enabled()</line>
<line>// ====================</line>
<line>// Returns TRUE if Secure EL2 is enabled, FALSE otherwise.</line>
<line></line>
<line link="impl-shared.IsSecureEL2Enabled.0" hover="function: boolean IsSecureEL2Enabled()" conts="IsSecureEL2Enabled">boolean <anchor link="impl-shared.IsSecureEL2Enabled.0" hover="function: boolean IsSecureEL2Enabled()">IsSecureEL2Enabled</anchor>()</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; <a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>() then</line>
<line>        if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>            if !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.EEL2 == '1' then</line>
<line>                return TRUE;</line>
<line>            else</line>
<line>                return FALSE;</line>
<line>        else</line>
<line>            return <a link="impl-shared.SecureOnlyImplementation.0" file="shared_pseudocode.xml" hover="function: boolean SecureOnlyImplementation()">SecureOnlyImplementation</a>();</line>
<line>    else</line>
<line>        return FALSE;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/LocalTimeoutEvent" mylink="shared.functions.system.LocalTimeoutEvent" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// LocalTimeoutEvent()</line>
<line>// ===================</line>
<line>// Returns TRUE if CNTVCT_EL0 equals or exceeds the localtimeout value.</line>
<line></line>
<line link="impl-shared.LocalTimeoutEvent.1" hover="function: boolean LocalTimeoutEvent(integer localtimeout)" conts="LocalTimeoutEvent">boolean <anchor link="impl-shared.LocalTimeoutEvent.1" hover="function: boolean LocalTimeoutEvent(integer localtimeout)">LocalTimeoutEvent</anchor>(integer localtimeout);</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/Mode_Bits" mylink="shared.functions.system.Mode_Bits" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="M32_User" hover="constant bits(5) M32_User = '10000'" conts="M32_User">constant bits(5) <anchor link="M32_User" hover="constant bits(5) M32_User = '10000'">M32_User</anchor>    = '10000';</line>
<line link="M32_FIQ" hover="constant bits(5) M32_FIQ = '10001'" conts="M32_FIQ">constant bits(5) <anchor link="M32_FIQ" hover="constant bits(5) M32_FIQ = '10001'">M32_FIQ</anchor>     = '10001';</line>
<line link="M32_IRQ" hover="constant bits(5) M32_IRQ = '10010'" conts="M32_IRQ">constant bits(5) <anchor link="M32_IRQ" hover="constant bits(5) M32_IRQ = '10010'">M32_IRQ</anchor>     = '10010';</line>
<line link="M32_Svc" hover="constant bits(5) M32_Svc = '10011'" conts="M32_Svc">constant bits(5) <anchor link="M32_Svc" hover="constant bits(5) M32_Svc = '10011'">M32_Svc</anchor>     = '10011';</line>
<line link="M32_Monitor" hover="constant bits(5) M32_Monitor = '10110'" conts="M32_Monitor">constant bits(5) <anchor link="M32_Monitor" hover="constant bits(5) M32_Monitor = '10110'">M32_Monitor</anchor> = '10110';</line>
<line link="M32_Abort" hover="constant bits(5) M32_Abort = '10111'" conts="M32_Abort">constant bits(5) <anchor link="M32_Abort" hover="constant bits(5) M32_Abort = '10111'">M32_Abort</anchor>   = '10111';</line>
<line link="M32_Hyp" hover="constant bits(5) M32_Hyp = '11010'" conts="M32_Hyp">constant bits(5) <anchor link="M32_Hyp" hover="constant bits(5) M32_Hyp = '11010'">M32_Hyp</anchor>     = '11010';</line>
<line link="M32_Undef" hover="constant bits(5) M32_Undef = '11011'" conts="M32_Undef">constant bits(5) <anchor link="M32_Undef" hover="constant bits(5) M32_Undef = '11011'">M32_Undef</anchor>   = '11011';</line>
<line link="M32_System" hover="constant bits(5) M32_System = '11111'" conts="M32_System">constant bits(5) <anchor link="M32_System" hover="constant bits(5) M32_System = '11111'">M32_System</anchor>  = '11111';</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/NonSecureOnlyImplementation" mylink="shared.functions.system.NonSecureOnlyImplementation" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// NonSecureOnlyImplementation()</line>
<line>// =============================</line>
<line>// Returns TRUE if the security state is always Non-secure for this implementation.</line>
<line></line>
<line link="impl-shared.NonSecureOnlyImplementation.0" hover="function: boolean NonSecureOnlyImplementation()" conts="NonSecureOnlyImplementation">boolean <anchor link="impl-shared.NonSecureOnlyImplementation.0" hover="function: boolean NonSecureOnlyImplementation()">NonSecureOnlyImplementation</anchor>()</line>
<line>    return boolean IMPLEMENTATION_DEFINED "Non-secure only implementation";</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/PLOfEL" mylink="shared.functions.system.PLOfEL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PLOfEL()</line>
<line>// ========</line>
<line></line>
<line link="impl-shared.PLOfEL.1" hover="function: PrivilegeLevel PLOfEL(bits(2) el)" conts="PLOfEL">PrivilegeLevel <anchor link="impl-shared.PLOfEL.1" hover="function: PrivilegeLevel PLOfEL(bits(2) el)">PLOfEL</anchor>(bits(2) el)</line>
<line>    case el of</line>
<line>        when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>  return if !<a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then <a link="PL1" file="shared_pseudocode.xml" hover="enumeration PrivilegeLevel {PL3, PL2, PL1, PL0}">PL1</a> else <a link="PL3" file="shared_pseudocode.xml" hover="enumeration PrivilegeLevel {PL3, PL2, PL1, PL0}">PL3</a>;</line>
<line>        when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>  return <a link="PL2" file="shared_pseudocode.xml" hover="enumeration PrivilegeLevel {PL3, PL2, PL1, PL0}">PL2</a>;</line>
<line>        when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>  return <a link="PL1" file="shared_pseudocode.xml" hover="enumeration PrivilegeLevel {PL3, PL2, PL1, PL0}">PL1</a>;</line>
<line>        when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>  return <a link="PL0" file="shared_pseudocode.xml" hover="enumeration PrivilegeLevel {PL3, PL2, PL1, PL0}">PL0</a>;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/PSTATE" mylink="shared.functions.system.PSTATE" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line><a link="ProcState" file="shared_pseudocode.xml" hover="type ProcState is ( bits (1) N, bits (1) Z, bits (1) C, bits (1) V, bits (1) D, bits (1) A, bits (1) I, bits (1) F, bits (1) EXLOCK, bits (1) PAN, bits (1) UAO, bits (1) DIT, bits (1) TCO, bits (1) PM, bits (1) PPEND, bits (2) BTYPE, bits (1) ZA, bits (1) SM, bits (1) ALLINT, bits (1) SS, bits (1) IL, bits (2) EL, bits (1) nRW, bits (1) SP, bits (1) Q, bits (4) GE, bits (1) SSBS, bits (8) IT, bits (1) J, bits (1) T, bits (1) E, bits (5) M )">ProcState</a> PSTATE;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/PhysicalCountInt" mylink="shared.functions.system.PhysicalCountInt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PhysicalCountInt()</line>
<line>// ==================</line>
<line>// Returns the integral part of physical count value of the System counter.</line>
<line></line>
<line link="impl-shared.PhysicalCountInt.0" hover="function: bits(64) PhysicalCountInt()" conts="PhysicalCountInt">bits(64) <anchor link="impl-shared.PhysicalCountInt.0" hover="function: bits(64) PhysicalCountInt()">PhysicalCountInt</anchor>()</line>
<line>    return PhysicalCount&lt;87:24&gt;;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/PrivilegeLevel" mylink="shared.functions.system.PrivilegeLevel" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PrivilegeLevel</line>
<line>// ==============</line>
<line>// Privilege Level abstraction.</line>
<line></line>
<line link="PrivilegeLevel" hover="enumeration PrivilegeLevel {PL3, PL2, PL1, PL0}" conts="PrivilegeLevel">enumeration <anchor link="PrivilegeLevel" hover="enumeration PrivilegeLevel {PL3, PL2, PL1, PL0}">PrivilegeLevel</anchor> {<anchor link="PL3" hover="enumeration PrivilegeLevel {PL3, PL2, PL1, PL0}">PL3</anchor>, <anchor link="PL2" hover="enumeration PrivilegeLevel {PL3, PL2, PL1, PL0}">PL2</anchor>, <anchor link="PL1" hover="enumeration PrivilegeLevel {PL3, PL2, PL1, PL0}">PL1</anchor>, <anchor link="PL0" hover="enumeration PrivilegeLevel {PL3, PL2, PL1, PL0}">PL0</anchor>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/ProcState" mylink="shared.functions.system.ProcState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ProcState</line>
<line>// =========</line>
<line>// Armv8 processor state bits.</line>
<line>// There is no significance to the field order.</line>
<line></line>
<line link="ProcState" hover="type ProcState is ( bits (1) N, bits (1) Z, bits (1) C, bits (1) V, bits (1) D, bits (1) A, bits (1) I, bits (1) F, bits (1) EXLOCK, bits (1) PAN, bits (1) UAO, bits (1) DIT, bits (1) TCO, bits (1) PM, bits (1) PPEND, bits (2) BTYPE, bits (1) ZA, bits (1) SM, bits (1) ALLINT, bits (1) SS, bits (1) IL, bits (2) EL, bits (1) nRW, bits (1) SP, bits (1) Q, bits (4) GE, bits (1) SSBS, bits (8) IT, bits (1) J, bits (1) T, bits (1) E, bits (5) M )" conts="ProcState">type <anchor link="ProcState" hover="type ProcState is ( bits (1) N, bits (1) Z, bits (1) C, bits (1) V, bits (1) D, bits (1) A, bits (1) I, bits (1) F, bits (1) EXLOCK, bits (1) PAN, bits (1) UAO, bits (1) DIT, bits (1) TCO, bits (1) PM, bits (1) PPEND, bits (2) BTYPE, bits (1) ZA, bits (1) SM, bits (1) ALLINT, bits (1) SS, bits (1) IL, bits (2) EL, bits (1) nRW, bits (1) SP, bits (1) Q, bits (4) GE, bits (1) SSBS, bits (8) IT, bits (1) J, bits (1) T, bits (1) E, bits (5) M )">ProcState</anchor> is (</line>
<line>    bits (1) N,        // Negative condition flag</line>
<line>    bits (1) Z,        // Zero condition flag</line>
<line>    bits (1) C,        // Carry condition flag</line>
<line>    bits (1) V,        // Overflow condition flag</line>
<line>    bits (1) D,        // Debug mask bit                     [AArch64 only]</line>
<line>    bits (1) A,        // SError interrupt mask bit</line>
<line>    bits (1) I,        // IRQ mask bit</line>
<line>    bits (1) F,        // FIQ mask bit</line>
<line>    bits (1) EXLOCK,   // Lock exception return state</line>
<line>    bits (1) PAN,      // Privileged Access Never Bit        [v8.1]</line>
<line>    bits (1) UAO,      // User Access Override               [v8.2]</line>
<line>    bits (1) DIT,      // Data Independent Timing            [v8.4]</line>
<line>    bits (1) TCO,      // Tag Check Override                 [v8.5, AArch64 only]</line>
<line>    bits (1) PM,       // PMU exception Mask</line>
<line>    bits (1) PPEND,     // synchronous PMU exception to be observed</line>
<line>    bits (2) BTYPE,    // Branch Type                        [v8.5]</line>
<line>    bits (1) ZA,       // Accumulation array enabled         [SME]</line>
<line>    bits (1) SM,       // Streaming SVE mode enabled         [SME]</line>
<line>    bits (1) ALLINT,   // Interrupt mask bit</line>
<line>    bits (1) SS,       // Software step bit</line>
<line>    bits (1) IL,       // Illegal Execution state bit</line>
<line>    bits (2) EL,       // Exception level</line>
<line>    bits (1) nRW,      // Execution state: 0=AArch64, 1=AArch32</line>
<line>    bits (1) SP,       // Stack pointer select: 0=SP0, 1=SPx [AArch64 only]</line>
<line>    bits (1) Q,        // Cumulative saturation flag         [AArch32 only]</line>
<line>    bits (4) GE,       // Greater than or Equal flags        [AArch32 only]</line>
<line>    bits (1) SSBS,     // Speculative Store Bypass Safe</line>
<line>    bits (8) IT,       // If-then bits, RES0 in CPSR         [AArch32 only]</line>
<line>    bits (1) J,        // J bit, RES0                        [AArch32 only, RES0 in SPSR and CPSR]</line>
<line>    bits (1) T,        // T32 bit, RES0 in CPSR              [AArch32 only]</line>
<line>    bits (1) E,        // Endianness bit                     [AArch32 only]</line>
<line>    bits (5) M         // Mode field                         [AArch32 only]</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/RestoredITBits" mylink="shared.functions.system.RestoredITBits" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// RestoredITBits()</line>
<line>// ================</line>
<line>// Get the value of PSTATE.IT to be restored on this exception return.</line>
<line></line>
<line link="impl-shared.RestoredITBits.1" hover="function: bits(8) RestoredITBits(bits(N) spsr)" conts="RestoredITBits">bits(8) <anchor link="impl-shared.RestoredITBits.1" hover="function: bits(8) RestoredITBits(bits(N) spsr)">RestoredITBits</anchor>(bits(N) spsr)</line>
<line>    it = spsr&lt;15:10,26:25&gt;;</line>
<line></line>
<line>    // When PSTATE.IL is set, it is CONSTRAINED UNPREDICTABLE whether the IT bits are each set</line>
<line>    // to zero or copied from the SPSR.</line>
<line>    if PSTATE.IL == '1' then</line>
<line>        if <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_ILZEROIT" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_ILZEROIT</a>) then return '00000000';</line>
<line>        else return it;</line>
<line></line>
<line>    // The IT bits are forced to zero when they are set to a reserved value.</line>
<line>    if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(it&lt;7:4&gt;) &amp;&amp; <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(it&lt;3:0&gt;) then</line>
<line>        return '00000000';</line>
<line></line>
<line>    // The IT bits are forced to zero when returning to A32 state, or when returning to an EL</line>
<line>    // with the ITD bit set to 1, and the IT bits are describing a multi-instruction block.</line>
<line>    itd = if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then HSCTLR.ITD else SCTLR.ITD;</line>
<line>    if (spsr&lt;5&gt; == '0' &amp;&amp; !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(it)) || (itd == '1' &amp;&amp; !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(it&lt;2:0&gt;)) then</line>
<line>        return '00000000';</line>
<line>    else</line>
<line>        return it;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/SCRType" mylink="shared.functions.system.SCRType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="SCRType" hover="type SCRType" conts="SCRType">type <anchor link="SCRType" hover="type SCRType">SCRType</anchor>;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/SCR_GEN" mylink="shared.functions.system.SCR_GEN" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SCR_GEN[]</line>
<line>// =========</line>
<line></line>
<line link="impl-shared.SCR_GEN.read.0" hover="accessor: SCRType SCR_GEN[]" conts="SCR_GEN">SCRType <anchor link="impl-shared.SCR_GEN.read.0" hover="accessor: SCRType SCR_GEN[]">SCR_GEN</anchor>[]</line>
<line>    // AArch32 secure &amp; AArch64 EL3 registers are not architecturally mapped</line>
<line>    assert <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>    bits(64) r;</line>
<line>    if !<a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then</line>
<line>        r = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(SCR, 64);</line>
<line>    else</line>
<line>        r = SCR_EL3;</line>
<line>    return r;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/SecureOnlyImplementation" mylink="shared.functions.system.SecureOnlyImplementation" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SecureOnlyImplementation()</line>
<line>// ==========================</line>
<line>// Returns TRUE if the security state is always Secure for this implementation.</line>
<line></line>
<line link="impl-shared.SecureOnlyImplementation.0" hover="function: boolean SecureOnlyImplementation()" conts="SecureOnlyImplementation">boolean <anchor link="impl-shared.SecureOnlyImplementation.0" hover="function: boolean SecureOnlyImplementation()">SecureOnlyImplementation</anchor>()</line>
<line>    return boolean IMPLEMENTATION_DEFINED "Secure-only implementation";</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/SecurityState" mylink="shared.functions.system.SecurityState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SecurityState</line>
<line>// =============</line>
<line>// The Security state of an execution context</line>
<line></line>
<line link="SecurityState" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }" conts="SecurityState">enumeration <anchor link="SecurityState" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</anchor> {</line>
<line link="SS_NonSecure" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }" conts="SS_NonSecure">    <anchor link="SS_NonSecure" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</anchor>,</line>
<line link="SS_Root" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }" conts="SS_Root">    <anchor link="SS_Root" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</anchor>,</line>
<line link="SS_Realm" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }" conts="SS_Realm">    <anchor link="SS_Realm" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</anchor>,</line>
<line link="SS_Secure" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }" conts="SS_Secure">    <anchor link="SS_Secure" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</anchor></line>
<line>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/SecurityStateAtEL" mylink="shared.functions.system.SecurityStateAtEL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SecurityStateAtEL()</line>
<line>// ===================</line>
<line>// Returns the effective security state at the exception level based off current settings.</line>
<line></line>
<line link="impl-shared.SecurityStateAtEL.1" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)" conts="SecurityStateAtEL">SecurityState <anchor link="impl-shared.SecurityStateAtEL.1" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)">SecurityStateAtEL</anchor>(bits(2) EL)</line>
<line>    if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then</line>
<line>        if EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then return <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a>;</line>
<line>        effective_nse_ns = SCR_EL3.NSE : <a link="impl-shared.EffectiveSCR_EL3_NS.0" file="shared_pseudocode.xml" hover="function: bit EffectiveSCR_EL3_NS()">EffectiveSCR_EL3_NS</a>();</line>
<line>        case effective_nse_ns of</line>
<line>            when '00' if <a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>() then return <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>; else <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>            when '01' return <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a>;</line>
<line>            when '11' return <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>;</line>
<line>            otherwise        <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        if <a link="impl-shared.SecureOnlyImplementation.0" file="shared_pseudocode.xml" hover="function: boolean SecureOnlyImplementation()">SecureOnlyImplementation</a>() then</line>
<line>            return <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>;</line>
<line>        else</line>
<line>            return <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a>;</line>
<line>    elsif EL == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then</line>
<line>        return <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>;</line>
<line>    else</line>
<line>        // For EL2 call only when EL2 is enabled in current security state</line>
<line>        assert(EL != <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> || <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>());</line>
<line>        if !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>            return if SCR_EL3.NS == '1' then <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> else <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>;</line>
<line>        else</line>
<line>            return if SCR.NS == '1' then <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> else <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/SendEvent" mylink="shared.functions.system.SendEvent" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SendEvent()</line>
<line>// ===========</line>
<line>// Signal an event to all PEs in a multiprocessor system to set their Event Registers.</line>
<line>// When a PE executes the SEV instruction, it causes this function to be executed.</line>
<line></line>
<line link="impl-shared.SendEvent.0" hover="function: SendEvent()" conts="SendEvent"><anchor link="impl-shared.SendEvent.0" hover="function: SendEvent()">SendEvent</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/SendEventLocal" mylink="shared.functions.system.SendEventLocal" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SendEventLocal()</line>
<line>// ================</line>
<line>// Set the local Event Register of this PE.</line>
<line>// When a PE executes the SEVL instruction, it causes this function to be executed.</line>
<line></line>
<line link="impl-shared.SendEventLocal.0" hover="function: SendEventLocal()" conts="SendEventLocal"><anchor link="impl-shared.SendEventLocal.0" hover="function: SendEventLocal()">SendEventLocal</anchor>()</line>
<line>    EventRegister = '1';</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/SetAccumulatedFPExceptions" mylink="shared.functions.system.SetAccumulatedFPExceptions" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SetAccumulatedFPExceptions()</line>
<line>// ============================</line>
<line>// Stores FP Exceptions accumulated by the PE.</line>
<line></line>
<line link="impl-shared.SetAccumulatedFPExceptions.1" hover="function: SetAccumulatedFPExceptions(bits(8) accumulated_exceptions)" conts="SetAccumulatedFPExceptions"><anchor link="impl-shared.SetAccumulatedFPExceptions.1" hover="function: SetAccumulatedFPExceptions(bits(8) accumulated_exceptions)">SetAccumulatedFPExceptions</anchor>(bits(8) accumulated_exceptions);</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/SetPSTATEFromPSR" mylink="shared.functions.system.SetPSTATEFromPSR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SetPSTATEFromPSR()</line>
<line>// ==================</line>
<line></line>
<line link="impl-shared.SetPSTATEFromPSR.1" hover="function: SetPSTATEFromPSR(bits(N) spsr)" conts="SetPSTATEFromPSR"><anchor link="impl-shared.SetPSTATEFromPSR.1" hover="function: SetPSTATEFromPSR(bits(N) spsr)">SetPSTATEFromPSR</anchor>(bits(N) spsr)</line>
<line>    boolean illegal_psr_state = <a link="impl-shared.IllegalExceptionReturn.1" file="shared_pseudocode.xml" hover="function: boolean IllegalExceptionReturn(bits(N) spsr)">IllegalExceptionReturn</a>(spsr);</line>
<line>    <a link="impl-shared.SetPSTATEFromPSR.2" file="shared_pseudocode.xml" hover="function: SetPSTATEFromPSR(bits(N) spsr_in, boolean illegal_psr_state)">SetPSTATEFromPSR</a>(spsr, illegal_psr_state);</line>
<line></line>
<line>// SetPSTATEFromPSR()</line>
<line>// ==================</line>
<line>// Set PSTATE based on a PSR value</line>
<line></line>
<line link="impl-shared.SetPSTATEFromPSR.2" hover="function: SetPSTATEFromPSR(bits(N) spsr_in, boolean illegal_psr_state)" conts="SetPSTATEFromPSR"><anchor link="impl-shared.SetPSTATEFromPSR.2" hover="function: SetPSTATEFromPSR(bits(N) spsr_in, boolean illegal_psr_state)">SetPSTATEFromPSR</anchor>(bits(N) spsr_in, boolean illegal_psr_state)</line>
<line>    bits(N) spsr = spsr_in;</line>
<line>    boolean from_aarch64 = !<a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>();</line>
<line>    PSTATE.SS = <a link="impl-shared.DebugExceptionReturnSS.1" file="shared_pseudocode.xml" hover="function: bit DebugExceptionReturnSS(bits(N) spsr)">DebugExceptionReturnSS</a>(spsr);</line>
<line></line>
<line>    ShouldAdvanceSS = FALSE;</line>
<line>    if illegal_psr_state then</line>
<line>        PSTATE.IL = '1';</line>
<line>        if <a link="impl-shared.HaveSSBSExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveSSBSExt()">HaveSSBSExt</a>() then PSTATE.SSBS = bit UNKNOWN;</line>
<line>        if <a link="impl-shared.HaveBTIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveBTIExt()">HaveBTIExt</a>() then PSTATE.BTYPE = bits(2) UNKNOWN;</line>
<line>        if <a link="impl-shared.HaveUAOExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveUAOExt()">HaveUAOExt</a>() then PSTATE.UAO = bit UNKNOWN;</line>
<line>        if <a link="impl-shared.HaveDITExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDITExt()">HaveDITExt</a>() then PSTATE.DIT = bit UNKNOWN;</line>
<line>        if <a link="impl-shared.HaveMTEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEExt()">HaveMTEExt</a>() then PSTATE.TCO = bit UNKNOWN;</line>
<line>    else</line>
<line>        // State that is reinstated only on a legal exception return</line>
<line>        PSTATE.IL = spsr&lt;20&gt;;</line>
<line>        if spsr&lt;4&gt; == '1' then                    // AArch32 state</line>
<line>            <a link="AArch32.WriteMode.1" file="shared_pseudocode.xml" hover="function: AArch32.WriteMode(bits(5) mode)">AArch32.WriteMode</a>(spsr&lt;4:0&gt;);         // Sets PSTATE.EL correctly</line>
<line>            if <a link="impl-shared.HaveSSBSExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveSSBSExt()">HaveSSBSExt</a>() then PSTATE.SSBS = spsr&lt;23&gt;;</line>
<line>        else                                      // AArch64 state</line>
<line>            PSTATE.nRW = '0';</line>
<line>            PSTATE.EL  = spsr&lt;3:2&gt;;</line>
<line>            PSTATE.SP  = spsr&lt;0&gt;;</line>
<line>            if <a link="impl-shared.HaveBTIExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveBTIExt()">HaveBTIExt</a>() then PSTATE.BTYPE = spsr&lt;11:10&gt;;</line>
<line>            if <a link="impl-shared.HaveSSBSExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveSSBSExt()">HaveSSBSExt</a>() then PSTATE.SSBS = spsr&lt;12&gt;;</line>
<line>            if <a link="impl-shared.HaveUAOExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveUAOExt()">HaveUAOExt</a>() then PSTATE.UAO = spsr&lt;23&gt;;</line>
<line>            if <a link="impl-shared.HaveDITExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDITExt()">HaveDITExt</a>() then PSTATE.DIT = spsr&lt;24&gt;;</line>
<line>            if <a link="impl-shared.HaveMTEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEExt()">HaveMTEExt</a>() then PSTATE.TCO = spsr&lt;25&gt;;</line>
<line>            if <a link="impl-shared.HaveGCS.0" file="shared_pseudocode.xml" hover="function: boolean HaveGCS()">HaveGCS</a>() then PSTATE.EXLOCK = spsr&lt;34&gt;;</line>
<line></line>
<line>    // If PSTATE.IL is set, it is CONSTRAINED UNPREDICTABLE whether the T bit is set to zero or</line>
<line>    // copied from SPSR.</line>
<line>    if PSTATE.IL == '1' &amp;&amp; PSTATE.nRW == '1' then</line>
<line>        if <a link="impl-shared.ConstrainUnpredictableBool.1" file="shared_pseudocode.xml" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</a>(<a link="Unpredictable_ILZEROT" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_ILZEROT</a>) then spsr&lt;5&gt; = '0';</line>
<line></line>
<line>    // State that is reinstated regardless of illegal exception return</line>
<line>    PSTATE.&lt;N,Z,C,V&gt; = spsr&lt;31:28&gt;;</line>
<line>    if <a link="impl-shared.HavePANExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePANExt()">HavePANExt</a>() then PSTATE.PAN = spsr&lt;22&gt;;</line>
<line>    if PSTATE.nRW == '1' then                     // AArch32 state</line>
<line>        PSTATE.Q         = spsr&lt;27&gt;;</line>
<line>        PSTATE.IT        = <a link="impl-shared.RestoredITBits.1" file="shared_pseudocode.xml" hover="function: bits(8) RestoredITBits(bits(N) spsr)">RestoredITBits</a>(spsr);</line>
<line>        ShouldAdvanceIT  = FALSE;</line>
<line>        if <a link="impl-shared.HaveDITExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveDITExt()">HaveDITExt</a>() then</line>
<line>            PSTATE.DIT = (if (<a link="impl-shared.Restarting.0" file="shared_pseudocode.xml" hover="function: boolean Restarting()">Restarting</a>() || from_aarch64) then spsr&lt;24&gt; else spsr&lt;21&gt;);</line>
<line>        PSTATE.GE        = spsr&lt;19:16&gt;;</line>
<line>        PSTATE.E         = spsr&lt;9&gt;;</line>
<line>        PSTATE.&lt;A,I,F&gt;   = spsr&lt;8:6&gt;;             // No PSTATE.D in AArch32 state</line>
<line>        PSTATE.T         = spsr&lt;5&gt;;               // PSTATE.J is RES0</line>
<line>    else                                          // AArch64 state</line>
<line>        if <a link="impl-shared.HaveFeatNMI.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatNMI()">HaveFeatNMI</a>() then PSTATE.ALLINT = spsr&lt;13&gt;;</line>
<line>        PSTATE.&lt;D,A,I,F&gt; = spsr&lt;9:6&gt;;             // No PSTATE.&lt;Q,IT,GE,E,T&gt; in AArch64 state</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/ShouldAdvanceIT" mylink="shared.functions.system.ShouldAdvanceIT" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>boolean ShouldAdvanceIT;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/ShouldAdvanceSS" mylink="shared.functions.system.ShouldAdvanceSS" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>boolean ShouldAdvanceSS;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/SpeculationBarrier" mylink="shared.functions.system.SpeculationBarrier" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SpeculationBarrier()</line>
<line>// ====================</line>
<line></line>
<line link="impl-shared.SpeculationBarrier.0" hover="function: SpeculationBarrier()" conts="SpeculationBarrier"><anchor link="impl-shared.SpeculationBarrier.0" hover="function: SpeculationBarrier()">SpeculationBarrier</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/SynchronizeContext" mylink="shared.functions.system.SynchronizeContext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SynchronizeContext()</line>
<line>// ====================</line>
<line></line>
<line link="impl-shared.SynchronizeContext.0" hover="function: SynchronizeContext()" conts="SynchronizeContext"><anchor link="impl-shared.SynchronizeContext.0" hover="function: SynchronizeContext()">SynchronizeContext</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/SynchronizeErrors" mylink="shared.functions.system.SynchronizeErrors" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SynchronizeErrors()</line>
<line>// ===================</line>
<line>// Implements the error synchronization event.</line>
<line></line>
<line link="impl-shared.SynchronizeErrors.0" hover="function: SynchronizeErrors()" conts="SynchronizeErrors"><anchor link="impl-shared.SynchronizeErrors.0" hover="function: SynchronizeErrors()">SynchronizeErrors</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/TakeUnmaskedPhysicalSErrorInterrupts" mylink="shared.functions.system.TakeUnmaskedPhysicalSErrorInterrupts" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TakeUnmaskedPhysicalSErrorInterrupts()</line>
<line>// ======================================</line>
<line>// Take any pending unmasked physical SError interrupt.</line>
<line></line>
<line link="impl-shared.TakeUnmaskedPhysicalSErrorInterrupts.1" hover="function: TakeUnmaskedPhysicalSErrorInterrupts(boolean iesb_req)" conts="TakeUnmaskedPhysicalSErrorInterrupts"><anchor link="impl-shared.TakeUnmaskedPhysicalSErrorInterrupts.1" hover="function: TakeUnmaskedPhysicalSErrorInterrupts(boolean iesb_req)">TakeUnmaskedPhysicalSErrorInterrupts</anchor>(boolean iesb_req);</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/TakeUnmaskedSErrorInterrupts" mylink="shared.functions.system.TakeUnmaskedSErrorInterrupts" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TakeUnmaskedSErrorInterrupts()</line>
<line>// ==============================</line>
<line>// Take any pending unmasked physical SError interrupt or unmasked virtual SError</line>
<line>// interrupt.</line>
<line></line>
<line link="impl-shared.TakeUnmaskedSErrorInterrupts.0" hover="function: TakeUnmaskedSErrorInterrupts()" conts="TakeUnmaskedSErrorInterrupts"><anchor link="impl-shared.TakeUnmaskedSErrorInterrupts.0" hover="function: TakeUnmaskedSErrorInterrupts()">TakeUnmaskedSErrorInterrupts</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/ThisInstr" mylink="shared.functions.system.ThisInstr" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ThisInstr()</line>
<line>// ===========</line>
<line></line>
<line link="impl-shared.ThisInstr.0" hover="function: bits(32) ThisInstr()" conts="ThisInstr">bits(32) <anchor link="impl-shared.ThisInstr.0" hover="function: bits(32) ThisInstr()">ThisInstr</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/ThisInstrLength" mylink="shared.functions.system.ThisInstrLength" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ThisInstrLength()</line>
<line>// =================</line>
<line></line>
<line link="impl-shared.ThisInstrLength.0" hover="function: integer ThisInstrLength()" conts="ThisInstrLength">integer <anchor link="impl-shared.ThisInstrLength.0" hover="function: integer ThisInstrLength()">ThisInstrLength</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/Unreachable" mylink="shared.functions.system.Unreachable" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Unreachable()</line>
<line>// =============</line>
<line></line>
<line link="impl-shared.Unreachable.0" hover="function: Unreachable()" conts="Unreachable"><anchor link="impl-shared.Unreachable.0" hover="function: Unreachable()">Unreachable</anchor>()</line>
<line>    assert FALSE;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/UsingAArch32" mylink="shared.functions.system.UsingAArch32" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// UsingAArch32()</line>
<line>// ==============</line>
<line>// Return TRUE if the current Exception level is using AArch32, FALSE if using AArch64.</line>
<line></line>
<line link="impl-shared.UsingAArch32.0" hover="function: boolean UsingAArch32()" conts="UsingAArch32">boolean <anchor link="impl-shared.UsingAArch32.0" hover="function: boolean UsingAArch32()">UsingAArch32</anchor>()</line>
<line>    boolean aarch32 = (PSTATE.nRW == '1');</line>
<line>    if !<a link="impl-shared.HaveAArch32.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32()">HaveAArch32</a>() then assert !aarch32;</line>
<line>    if !<a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then assert aarch32;</line>
<line>    return aarch32;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/ValidSecurityStateAtEL" mylink="shared.functions.system.ValidSecurityStateAtEL" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ValidSecurityStateAtEL()</line>
<line>// ========================</line>
<line>// Returns TRUE if the current settings and architecture choices for this</line>
<line>// implementation permit a valid Security state at the indicated EL.</line>
<line></line>
<line link="impl-shared.ValidSecurityStateAtEL.1" hover="function: boolean ValidSecurityStateAtEL(bits(2) el)" conts="ValidSecurityStateAtEL">boolean <anchor link="impl-shared.ValidSecurityStateAtEL.1" hover="function: boolean ValidSecurityStateAtEL(bits(2) el)">ValidSecurityStateAtEL</anchor>(bits(2) el)</line>
<line>    if !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(el) then</line>
<line>        return FALSE;</line>
<line></line>
<line>    if el == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then</line>
<line>        return TRUE;</line>
<line></line>
<line>    if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then</line>
<line>        bits(2) effective_nse_ns = SCR_EL3.NSE : <a link="impl-shared.EffectiveSCR_EL3_NS.0" file="shared_pseudocode.xml" hover="function: bit EffectiveSCR_EL3_NS()">EffectiveSCR_EL3_NS</a>();</line>
<line>        if effective_nse_ns == '10' then</line>
<line>            return FALSE;</line>
<line></line>
<line>    if el == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>        return <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>();</line>
<line></line>
<line>    return TRUE;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/VirtualFIQPending" mylink="shared.functions.system.VirtualFIQPending" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// VirtualFIQPending()</line>
<line>// ===================</line>
<line>// Returns TRUE if there is any pending virtual FIQ.</line>
<line></line>
<line link="impl-shared.VirtualFIQPending.0" hover="function: boolean VirtualFIQPending()" conts="VirtualFIQPending">boolean <anchor link="impl-shared.VirtualFIQPending.0" hover="function: boolean VirtualFIQPending()">VirtualFIQPending</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/VirtualIRQPending" mylink="shared.functions.system.VirtualIRQPending" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// VirtualIRQPending()</line>
<line>// ===================</line>
<line>// Returns TRUE if there is any pending virtual IRQ.</line>
<line></line>
<line link="impl-shared.VirtualIRQPending.0" hover="function: boolean VirtualIRQPending()" conts="VirtualIRQPending">boolean <anchor link="impl-shared.VirtualIRQPending.0" hover="function: boolean VirtualIRQPending()">VirtualIRQPending</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/WFxType" mylink="shared.functions.system.WFxType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// WFxType</line>
<line>// =======</line>
<line>// WFx instruction types.</line>
<line></line>
<line link="WFxType" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}" conts="WFxType">enumeration <anchor link="WFxType" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType</anchor> {<anchor link="WFxType_WFE" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFE</anchor>, <anchor link="WFxType_WFI" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFI</anchor>, <anchor link="WFxType_WFET" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFET</anchor>, <anchor link="WFxType_WFIT" hover="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFIT</anchor>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/WaitForEvent" mylink="shared.functions.system.WaitForEvent" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// WaitForEvent()</line>
<line>// ==============</line>
<line>// PE optionally suspends execution until one of the following occurs:</line>
<line>// - A WFE wakeup event.</line>
<line>// - A reset.</line>
<line>// - The implementation chooses to resume execution.</line>
<line>// - A Wait for Event with Timeout (WFET) is executing, and a local timeout event occurs</line>
<line>// It is IMPLEMENTATION DEFINED whether restarting execution after the period of</line>
<line>// suspension causes the Event Register to be cleared.</line>
<line></line>
<line link="impl-shared.WaitForEvent.1" hover="function: WaitForEvent(integer localtimeout)" conts="WaitForEvent"><anchor link="impl-shared.WaitForEvent.1" hover="function: WaitForEvent(integer localtimeout)">WaitForEvent</anchor>(integer localtimeout)</line>
<line>    if !(<a link="impl-shared.IsEventRegisterSet.0" file="shared_pseudocode.xml" hover="function: boolean IsEventRegisterSet()">IsEventRegisterSet</a>() || (<a link="impl-shared.HaveFeatWFxT.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatWFxT()">HaveFeatWFxT</a>() &amp;&amp; <a link="impl-shared.LocalTimeoutEvent.1" file="shared_pseudocode.xml" hover="function: boolean LocalTimeoutEvent(integer localtimeout)">LocalTimeoutEvent</a>(localtimeout))) then</line>
<line>        <a link="impl-shared.EnterLowPowerState.0" file="shared_pseudocode.xml" hover="function: EnterLowPowerState()">EnterLowPowerState</a>();</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/functions/system/WaitForInterrupt" mylink="shared.functions.system.WaitForInterrupt" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// WaitForInterrupt()</line>
<line>// ==================</line>
<line>// PE optionally suspends execution until one of the following occurs:</line>
<line>// - A WFI wakeup event.</line>
<line>// - A reset.</line>
<line>// - The implementation chooses to resume execution.</line>
<line>// - A Wait for Interrupt with Timeout (WFIT) is executing, and a local timeout event occurs.</line>
<line></line>
<line link="impl-shared.WaitForInterrupt.1" hover="function: WaitForInterrupt(integer localtimeout)" conts="WaitForInterrupt"><anchor link="impl-shared.WaitForInterrupt.1" hover="function: WaitForInterrupt(integer localtimeout)">WaitForInterrupt</anchor>(integer localtimeout)</line>
<line>    if !(<a link="impl-shared.HaveFeatWFxT.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatWFxT()">HaveFeatWFxT</a>() &amp;&amp; <a link="impl-shared.LocalTimeoutEvent.1" file="shared_pseudocode.xml" hover="function: boolean LocalTimeoutEvent(integer localtimeout)">LocalTimeoutEvent</a>(localtimeout)) then</line>
<line>        <a link="impl-shared.EnterLowPowerState.0" file="shared_pseudocode.xml" hover="function: EnterLowPowerState()">EnterLowPowerState</a>();</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/functions/unpredictable/ConstrainUnpredictable" mylink="shared.functions.unpredictable.ConstrainUnpredictable" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ConstrainUnpredictable()</line>
<line>// ========================</line>
<line>// Return the appropriate Constraint result to control the caller's behavior.</line>
<line>// The return value is IMPLEMENTATION DEFINED within a permitted list for each</line>
<line>// UNPREDICTABLE case.</line>
<line>// (The permitted list is determined by an assert or case statement at the call site.)</line>
<line></line>
<line link="impl-shared.ConstrainUnpredictable.1" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)" conts="ConstrainUnpredictable">Constraint <anchor link="impl-shared.ConstrainUnpredictable.1" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</anchor>(<a link="Unpredictable" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable</a> which);</line>
</pstext>
    </ps>
    <ps name="shared/functions/unpredictable/ConstrainUnpredictableBits" mylink="shared.functions.unpredictable.ConstrainUnpredictableBits" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ConstrainUnpredictableBits()</line>
<line>// ============================</line>
<line></line>
<line>// This is a variant of ConstrainUnpredictable for when the result can be Constraint_UNKNOWN.</line>
<line>// If the result is Constraint_UNKNOWN then the function also returns UNKNOWN value, but that</line>
<line>// value is always an allocated value; that is, one for which the behavior is not itself</line>
<line>// CONSTRAINED.</line>
<line></line>
<line link="impl-shared.ConstrainUnpredictableBits.2" hover="function: (Constraint,bits(width)) ConstrainUnpredictableBits(Unpredictable which, integer width)" conts="ConstrainUnpredictableBits">(Constraint,bits(width)) <anchor link="impl-shared.ConstrainUnpredictableBits.2" hover="function: (Constraint,bits(width)) ConstrainUnpredictableBits(Unpredictable which, integer width)">ConstrainUnpredictableBits</anchor>(<a link="Unpredictable" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable</a> which, integer width);</line>
</pstext>
    </ps>
    <ps name="shared/functions/unpredictable/ConstrainUnpredictableBool" mylink="shared.functions.unpredictable.ConstrainUnpredictableBool" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ConstrainUnpredictableBool()</line>
<line>// ============================</line>
<line>// This is a variant of the ConstrainUnpredictable function where the result is either</line>
<line>// Constraint_TRUE or Constraint_FALSE.</line>
<line></line>
<line link="impl-shared.ConstrainUnpredictableBool.1" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)" conts="ConstrainUnpredictableBool">boolean <anchor link="impl-shared.ConstrainUnpredictableBool.1" hover="function: boolean ConstrainUnpredictableBool(Unpredictable which)">ConstrainUnpredictableBool</anchor>(<a link="Unpredictable" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable</a> which);</line>
</pstext>
    </ps>
    <ps name="shared/functions/unpredictable/ConstrainUnpredictableInteger" mylink="shared.functions.unpredictable.ConstrainUnpredictableInteger" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ConstrainUnpredictableInteger()</line>
<line>// ===============================</line>
<line>// This is a variant of ConstrainUnpredictable for when the result can be Constraint_UNKNOWN.</line>
<line>// If the result is Constraint_UNKNOWN then the function also returns an UNKNOWN</line>
<line>// value in the range low to high, inclusive.</line>
<line></line>
<line link="impl-shared.ConstrainUnpredictableInteger.3" hover="function: (Constraint,integer) ConstrainUnpredictableInteger(integer low, integer high, Unpredictable which)" conts="ConstrainUnpredictableInteger">(Constraint,integer) <anchor link="impl-shared.ConstrainUnpredictableInteger.3" hover="function: (Constraint,integer) ConstrainUnpredictableInteger(integer low, integer high, Unpredictable which)">ConstrainUnpredictableInteger</anchor>(integer low, integer high,</line>
<line>                                                   <a link="Unpredictable" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable</a> which);</line>
</pstext>
    </ps>
    <ps name="shared/functions/unpredictable/ConstrainUnpredictableProcedure" mylink="shared.functions.unpredictable.ConstrainUnpredictableProcedure" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ConstrainUnpredictableProcedure()</line>
<line>// =================================</line>
<line>// This is a variant of ConstrainUnpredictable that implements a Constrained</line>
<line>// Unpredictable behavior for a given Unpredictable situation.</line>
<line>// The behavior is within permitted behaviors for a given Unpredictable situation,</line>
<line>// these are documented in the textual part of the architecture specification.</line>
<line>//</line>
<line>// This function is expected to be refined in an IMPLEMENTATION DEFINED manner.</line>
<line>// The details of possible outcomes may not be present in the code and must be interpreted</line>
<line>// for each use with respect to the CONSTRAINED UNPREDICTABLE specifications</line>
<line>// for the specific area.</line>
<line></line>
<line link="impl-shared.ConstrainUnpredictableProcedure.1" hover="function: ConstrainUnpredictableProcedure(Unpredictable which)" conts="ConstrainUnpredictableProcedure"><anchor link="impl-shared.ConstrainUnpredictableProcedure.1" hover="function: ConstrainUnpredictableProcedure(Unpredictable which)">ConstrainUnpredictableProcedure</anchor>(<a link="Unpredictable" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable</a> which);</line>
</pstext>
    </ps>
    <ps name="shared/functions/unpredictable/Constraint" mylink="shared.functions.unpredictable.Constraint" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Constraint</line>
<line>// ==========</line>
<line>// List of Constrained Unpredictable behaviors.</line>
<line></line>
<line link="Constraint" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint">enumeration <anchor link="Constraint" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint</anchor>    {// General</line>
<line link="Constraint_NONE" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_NONE">                           <anchor link="Constraint_NONE" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NONE</anchor>,              // Instruction executes with</line>
<line>                                                         // no change or side-effect</line>
<line>                                                         // to its described behavior</line>
<line link="Constraint_UNKNOWN" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_UNKNOWN">                           <anchor link="Constraint_UNKNOWN" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNKNOWN</anchor>,           // Destination register</line>
<line>                                                         // has UNKNOWN value</line>
<line link="Constraint_UNDEF" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_UNDEF">                           <anchor link="Constraint_UNDEF" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNDEF</anchor>,             // Instruction is UNDEFINED</line>
<line link="Constraint_UNDEFEL0" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_UNDEFEL0">                           <anchor link="Constraint_UNDEFEL0" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNDEFEL0</anchor>,          // Instruction is UNDEFINED at EL0 only</line>
<line link="Constraint_NOP" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_NOP">                           <anchor link="Constraint_NOP" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NOP</anchor>,               // Instruction executes as NOP</line>
<line link="Constraint_TRUE" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_TRUE">                           <anchor link="Constraint_TRUE" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_TRUE</anchor>,</line>
<line link="Constraint_FALSE" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_FALSE">                           <anchor link="Constraint_FALSE" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_FALSE</anchor>,</line>
<line link="Constraint_DISABLED" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_DISABLED">                           <anchor link="Constraint_DISABLED" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_DISABLED</anchor>,</line>
<line link="Constraint_UNCOND" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_UNCOND">                           <anchor link="Constraint_UNCOND" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_UNCOND</anchor>,            // Instruction executes unconditionally</line>
<line link="Constraint_COND" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_COND">                           <anchor link="Constraint_COND" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_COND</anchor>,              // Instruction executes conditionally</line>
<line link="Constraint_ADDITIONAL_DECODE" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_ADDITIONAL_DECODE">                           <anchor link="Constraint_ADDITIONAL_DECODE" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_ADDITIONAL_DECODE</anchor>, // Instruction executes</line>
<line>                                                         // with additional decode</line>
<line>                           // Load-store</line>
<line link="Constraint_WBSUPPRESS" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_WBSUPPRESS">                           <anchor link="Constraint_WBSUPPRESS" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_WBSUPPRESS</anchor>,</line>
<line link="Constraint_FAULT" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_FAULT">                           <anchor link="Constraint_FAULT" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_FAULT</anchor>,</line>
<line link="Constraint_LIMITED_ATOMICITY" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_LIMITED_ATOMICITY">                           <anchor link="Constraint_LIMITED_ATOMICITY" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_LIMITED_ATOMICITY</anchor>, // Accesses are not</line>
<line>                                                         // single-copy atomic</line>
<line>                                                         // above the byte level</line>
<line link="Constraint_NVNV1_00" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_NVNV1_00">                           <anchor link="Constraint_NVNV1_00" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NVNV1_00</anchor>,</line>
<line link="Constraint_NVNV1_01" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_NVNV1_01">                           <anchor link="Constraint_NVNV1_01" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NVNV1_01</anchor>,</line>
<line link="Constraint_NVNV1_11" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_NVNV1_11">                           <anchor link="Constraint_NVNV1_11" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NVNV1_11</anchor>,</line>
<line link="Constraint_EL1TIMESTAMP" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_EL1TIMESTAMP">                           <anchor link="Constraint_EL1TIMESTAMP" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_EL1TIMESTAMP</anchor>,      // Constrain to Virtual Timestamp</line>
<line link="Constraint_EL2TIMESTAMP" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_EL2TIMESTAMP">                           <anchor link="Constraint_EL2TIMESTAMP" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_EL2TIMESTAMP</anchor>,      // Constrain to Virtual Timestamp</line>
<line link="Constraint_OSH" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_OSH">                           <anchor link="Constraint_OSH" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_OSH</anchor>,               // Constrain to Outer Shareable</line>
<line link="Constraint_ISH" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_ISH">                           <anchor link="Constraint_ISH" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_ISH</anchor>,               // Constrain to Inner Shareable</line>
<line link="Constraint_NSH" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_NSH">                           <anchor link="Constraint_NSH" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NSH</anchor>,               // Constrain to Nonshareable</line>
<line></line>
<line link="Constraint_NC" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_NC">                           <anchor link="Constraint_NC" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NC</anchor>,                // Constrain to Noncacheable</line>
<line link="Constraint_WT" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_WT">                           <anchor link="Constraint_WT" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_WT</anchor>,                // Constrain to Writethrough</line>
<line link="Constraint_WB" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_WB">                           <anchor link="Constraint_WB" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_WB</anchor>,                // Constrain to Writeback</line>
<line></line>
<line>                           // IPA too large</line>
<line link="Constraint_FORCE" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_FORCE">                           <anchor link="Constraint_FORCE" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_FORCE</anchor>, <anchor link="Constraint_FORCENOSLCHECK" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_FORCENOSLCHECK</anchor>,</line>
<line>                           // An unallocated System register value maps onto an allocated value</line>
<line link="Constraint_MAPTOALLOCATED" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_MAPTOALLOCATED">                           <anchor link="Constraint_MAPTOALLOCATED" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_MAPTOALLOCATED</anchor>,</line>
<line>                           // PMSCR_PCT reserved values select Virtual timestamp</line>
<line link="Constraint_PMSCR_PCT_VIRT" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }" conts="Constraint_PMSCR_PCT_VIRT">                           <anchor link="Constraint_PMSCR_PCT_VIRT" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_PMSCR_PCT_VIRT</anchor></line>
<line>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/unpredictable/Unpredictable" mylink="shared.functions.unpredictable.Unpredictable" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Unpredictable</line>
<line>// =============</line>
<line>// List of Constrained Unpredictable situations.</line>
<line></line>
<line link="Unpredictable" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable">enumeration <anchor link="Unpredictable" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable</anchor> {</line>
<line>                           // VMSR on MVFR</line>
<line link="Unpredictable_VMSR" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_VMSR">                           <anchor link="Unpredictable_VMSR" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_VMSR</anchor>,</line>
<line>                           // Writeback/transfer register overlap (load)</line>
<line link="Unpredictable_WBOVERLAPLD" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_WBOVERLAPLD">                           <anchor link="Unpredictable_WBOVERLAPLD" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_WBOVERLAPLD</anchor>,</line>
<line>                           // Writeback/transfer register overlap (store)</line>
<line link="Unpredictable_WBOVERLAPST" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_WBOVERLAPST">                           <anchor link="Unpredictable_WBOVERLAPST" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_WBOVERLAPST</anchor>,</line>
<line>                           // Load Pair transfer register overlap</line>
<line link="Unpredictable_LDPOVERLAP" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_LDPOVERLAP">                           <anchor link="Unpredictable_LDPOVERLAP" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_LDPOVERLAP</anchor>,</line>
<line>                           // Store-exclusive base/status register overlap</line>
<line link="Unpredictable_BASEOVERLAP" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_BASEOVERLAP">                           <anchor link="Unpredictable_BASEOVERLAP" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BASEOVERLAP</anchor>,</line>
<line>                           // Store-exclusive data/status register overlap</line>
<line link="Unpredictable_DATAOVERLAP" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_DATAOVERLAP">                           <anchor link="Unpredictable_DATAOVERLAP" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_DATAOVERLAP</anchor>,</line>
<line>                           // Load-store alignment checks</line>
<line link="Unpredictable_DEVPAGE2" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_DEVPAGE2">                           <anchor link="Unpredictable_DEVPAGE2" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_DEVPAGE2</anchor>,</line>
<line>                           // Instruction fetch from Device memory</line>
<line link="Unpredictable_INSTRDEVICE" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_INSTRDEVICE">                           <anchor link="Unpredictable_INSTRDEVICE" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_INSTRDEVICE</anchor>,</line>
<line>                           // Reserved CPACR value</line>
<line link="Unpredictable_RESCPACR" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_RESCPACR">                           <anchor link="Unpredictable_RESCPACR" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESCPACR</anchor>,</line>
<line>                           // Reserved MAIR value</line>
<line link="Unpredictable_RESMAIR" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_RESMAIR">                           <anchor link="Unpredictable_RESMAIR" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESMAIR</anchor>,</line>
<line>                           // Effect of SCTLR_ELx.C on Tagged attribute</line>
<line link="Unpredictable_S1CTAGGED" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_S1CTAGGED">                           <anchor link="Unpredictable_S1CTAGGED" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_S1CTAGGED</anchor>,</line>
<line>                           // Reserved Stage 2 MemAttr value</line>
<line link="Unpredictable_S2RESMEMATTR" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_S2RESMEMATTR">                           <anchor link="Unpredictable_S2RESMEMATTR" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_S2RESMEMATTR</anchor>,</line>
<line>                           // Reserved TEX:C:B value</line>
<line link="Unpredictable_RESTEXCB" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_RESTEXCB">                           <anchor link="Unpredictable_RESTEXCB" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESTEXCB</anchor>,</line>
<line>                           // Reserved PRRR value</line>
<line link="Unpredictable_RESPRRR" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_RESPRRR">                           <anchor link="Unpredictable_RESPRRR" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESPRRR</anchor>,</line>
<line>                           // Reserved DACR field</line>
<line link="Unpredictable_RESDACR" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_RESDACR">                           <anchor link="Unpredictable_RESDACR" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESDACR</anchor>,</line>
<line>                           // Reserved VTCR.S value</line>
<line link="Unpredictable_RESVTCRS" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_RESVTCRS">                           <anchor link="Unpredictable_RESVTCRS" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESVTCRS</anchor>,</line>
<line>                           // Reserved TCR.TnSZ value</line>
<line link="Unpredictable_RESTnSZ" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_RESTnSZ">                           <anchor link="Unpredictable_RESTnSZ" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESTnSZ</anchor>,</line>
<line>                           // Reserved SCTLR_ELx.TCF value</line>
<line link="Unpredictable_RESTCF" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_RESTCF">                           <anchor link="Unpredictable_RESTCF" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESTCF</anchor>,</line>
<line>                           // Tag stored to Device memory</line>
<line link="Unpredictable_DEVICETAGSTORE" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_DEVICETAGSTORE">                           <anchor link="Unpredictable_DEVICETAGSTORE" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_DEVICETAGSTORE</anchor>,</line>
<line>                           // Out-of-range TCR.TnSZ value</line>
<line link="Unpredictable_OORTnSZ" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_OORTnSZ">                           <anchor link="Unpredictable_OORTnSZ" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_OORTnSZ</anchor>,</line>
<line>                           // IPA size exceeds PA size</line>
<line link="Unpredictable_LARGEIPA" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_LARGEIPA">                           <anchor link="Unpredictable_LARGEIPA" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_LARGEIPA</anchor>,</line>
<line>                           // Syndrome for a known-passing conditional A32 instruction</line>
<line link="Unpredictable_ESRCONDPASS" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_ESRCONDPASS">                           <anchor link="Unpredictable_ESRCONDPASS" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_ESRCONDPASS</anchor>,</line>
<line>                           // Illegal State exception: zero PSTATE.IT</line>
<line link="Unpredictable_ILZEROIT" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_ILZEROIT">                           <anchor link="Unpredictable_ILZEROIT" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_ILZEROIT</anchor>,</line>
<line>                           // Illegal State exception: zero PSTATE.T</line>
<line link="Unpredictable_ILZEROT" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_ILZEROT">                           <anchor link="Unpredictable_ILZEROT" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_ILZEROT</anchor>,</line>
<line>                           // Debug: prioritization of Vector Catch</line>
<line link="Unpredictable_BPVECTORCATCHPRI" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_BPVECTORCATCHPRI">                           <anchor link="Unpredictable_BPVECTORCATCHPRI" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BPVECTORCATCHPRI</anchor>,</line>
<line>                           // Debug Vector Catch: match on 2nd halfword</line>
<line link="Unpredictable_VCMATCHHALF" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_VCMATCHHALF">                           <anchor link="Unpredictable_VCMATCHHALF" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_VCMATCHHALF</anchor>,</line>
<line>                           // Debug Vector Catch: match on Data Abort</line>
<line>                           // or Prefetch abort</line>
<line link="Unpredictable_VCMATCHDAPA" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_VCMATCHDAPA">                           <anchor link="Unpredictable_VCMATCHDAPA" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_VCMATCHDAPA</anchor>,</line>
<line>                           // Debug watchpoints: non-zero MASK and non-ones BAS</line>
<line link="Unpredictable_WPMASKANDBAS" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_WPMASKANDBAS">                           <anchor link="Unpredictable_WPMASKANDBAS" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_WPMASKANDBAS</anchor>,</line>
<line>                           // Debug watchpoints: non-contiguous BAS</line>
<line link="Unpredictable_WPBASCONTIGUOUS" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_WPBASCONTIGUOUS">                           <anchor link="Unpredictable_WPBASCONTIGUOUS" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_WPBASCONTIGUOUS</anchor>,</line>
<line>                           // Debug watchpoints: reserved MASK</line>
<line link="Unpredictable_RESWPMASK" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_RESWPMASK">                           <anchor link="Unpredictable_RESWPMASK" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESWPMASK</anchor>,</line>
<line>                           // Debug watchpoints: non-zero MASKed bits of address</line>
<line link="Unpredictable_WPMASKEDBITS" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_WPMASKEDBITS">                           <anchor link="Unpredictable_WPMASKEDBITS" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_WPMASKEDBITS</anchor>,</line>
<line>                           // Debug breakpoints and watchpoints: reserved control bits</line>
<line link="Unpredictable_RESBPWPCTRL" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_RESBPWPCTRL">                           <anchor link="Unpredictable_RESBPWPCTRL" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESBPWPCTRL</anchor>,</line>
<line>                           // Debug breakpoints: not implemented</line>
<line link="Unpredictable_BPNOTIMPL" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_BPNOTIMPL">                           <anchor link="Unpredictable_BPNOTIMPL" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BPNOTIMPL</anchor>,</line>
<line>                           // Debug breakpoints: reserved type</line>
<line link="Unpredictable_RESBPTYPE" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_RESBPTYPE">                           <anchor link="Unpredictable_RESBPTYPE" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESBPTYPE</anchor>,</line>
<line>                           // Debug breakpoints: not-context-aware breakpoint</line>
<line link="Unpredictable_BPNOTCTXCMP" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_BPNOTCTXCMP">                           <anchor link="Unpredictable_BPNOTCTXCMP" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BPNOTCTXCMP</anchor>,</line>
<line>                           // Debug breakpoints: match on 2nd halfword of instruction</line>
<line link="Unpredictable_BPMATCHHALF" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_BPMATCHHALF">                           <anchor link="Unpredictable_BPMATCHHALF" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BPMATCHHALF</anchor>,</line>
<line>                           // Debug breakpoints: mismatch on 2nd halfword of instruction</line>
<line link="Unpredictable_BPMISMATCHHALF" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_BPMISMATCHHALF">                           <anchor link="Unpredictable_BPMISMATCHHALF" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BPMISMATCHHALF</anchor>,</line>
<line>                           // Debug: restart to a misaligned AArch32 PC value</line>
<line link="Unpredictable_RESTARTALIGNPC" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_RESTARTALIGNPC">                           <anchor link="Unpredictable_RESTARTALIGNPC" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESTARTALIGNPC</anchor>,</line>
<line>                           // Debug: restart to a not-zero-extended AArch32 PC value</line>
<line link="Unpredictable_RESTARTZEROUPPERPC" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_RESTARTZEROUPPERPC">                           <anchor link="Unpredictable_RESTARTZEROUPPERPC" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESTARTZEROUPPERPC</anchor>,</line>
<line>                           // Zero top 32 bits of X registers in AArch32 state</line>
<line link="Unpredictable_ZEROUPPER" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_ZEROUPPER">                           <anchor link="Unpredictable_ZEROUPPER" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_ZEROUPPER</anchor>,</line>
<line>                           // Zero top 32 bits of PC on illegal return to</line>
<line>                           // AArch32 state</line>
<line link="Unpredictable_ERETZEROUPPERPC" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_ERETZEROUPPERPC">                           <anchor link="Unpredictable_ERETZEROUPPERPC" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_ERETZEROUPPERPC</anchor>,</line>
<line>                           // Force address to be aligned when interworking</line>
<line>                           // branch to A32 state</line>
<line link="Unpredictable_A32FORCEALIGNPC" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_A32FORCEALIGNPC">                           <anchor link="Unpredictable_A32FORCEALIGNPC" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_A32FORCEALIGNPC</anchor>,</line>
<line>                           // SMC disabled</line>
<line link="Unpredictable_SMD" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_SMD">                           <anchor link="Unpredictable_SMD" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_SMD</anchor>,</line>
<line>                           // FF speculation</line>
<line link="Unpredictable_NONFAULT" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_NONFAULT">                           <anchor link="Unpredictable_NONFAULT" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_NONFAULT</anchor>,</line>
<line>                           // Zero top bits of Z registers in EL change</line>
<line link="Unpredictable_SVEZEROUPPER" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_SVEZEROUPPER">                           <anchor link="Unpredictable_SVEZEROUPPER" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_SVEZEROUPPER</anchor>,</line>
<line>                           // Load mem data in NF loads</line>
<line link="Unpredictable_SVELDNFDATA" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_SVELDNFDATA">                           <anchor link="Unpredictable_SVELDNFDATA" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_SVELDNFDATA</anchor>,</line>
<line>                           // Write zeros in NF loads</line>
<line link="Unpredictable_SVELDNFZERO" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_SVELDNFZERO">                           <anchor link="Unpredictable_SVELDNFZERO" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_SVELDNFZERO</anchor>,</line>
<line>                           // SP alignment fault when predicate is all zero</line>
<line link="Unpredictable_CHECKSPNONEACTIVE" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_CHECKSPNONEACTIVE">                           <anchor link="Unpredictable_CHECKSPNONEACTIVE" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_CHECKSPNONEACTIVE</anchor>,</line>
<line>                           // Zero top bits of ZA registers in EL change</line>
<line link="Unpredictable_SMEZEROUPPER" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_SMEZEROUPPER">                           <anchor link="Unpredictable_SMEZEROUPPER" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_SMEZEROUPPER</anchor>,</line>
<line>                           // HCR_EL2.&lt;NV,NV1&gt; == '01'</line>
<line link="Unpredictable_NVNV1" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_NVNV1">                           <anchor link="Unpredictable_NVNV1" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_NVNV1</anchor>,</line>
<line>                           // Reserved shareability encoding</line>
<line link="Unpredictable_Shareability" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_Shareability">                           <anchor link="Unpredictable_Shareability" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_Shareability</anchor>,</line>
<line>                           // Access Flag Update by HW</line>
<line link="Unpredictable_AFUPDATE" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_AFUPDATE">                           <anchor link="Unpredictable_AFUPDATE" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_AFUPDATE</anchor>,</line>
<line>                           // Dirty Bit State Update by HW</line>
<line link="Unpredictable_DBUPDATE" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_DBUPDATE">                           <anchor link="Unpredictable_DBUPDATE" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_DBUPDATE</anchor>,</line>
<line>                           // Consider SCTLR[].IESB in Debug state</line>
<line link="Unpredictable_IESBinDebug" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_IESBinDebug">                           <anchor link="Unpredictable_IESBinDebug" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_IESBinDebug</anchor>,</line>
<line>                           // Bad settings for PMSFCR_EL1/PMSEVFR_EL1/PMSLATFR_EL1</line>
<line link="Unpredictable_BADPMSFCR" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_BADPMSFCR">                           <anchor link="Unpredictable_BADPMSFCR" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BADPMSFCR</anchor>,</line>
<line>                           // Zero saved BType value in SPSR_ELx/DPSR_EL0</line>
<line link="Unpredictable_ZEROBTYPE" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_ZEROBTYPE">                           <anchor link="Unpredictable_ZEROBTYPE" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_ZEROBTYPE</anchor>,</line>
<line>                           // Timestamp constrained to virtual or physical</line>
<line link="Unpredictable_EL2TIMESTAMP" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_EL2TIMESTAMP">                           <anchor link="Unpredictable_EL2TIMESTAMP" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_EL2TIMESTAMP</anchor>,</line>
<line link="Unpredictable_EL1TIMESTAMP" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_EL1TIMESTAMP">                           <anchor link="Unpredictable_EL1TIMESTAMP" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_EL1TIMESTAMP</anchor>,</line>
<line>                            // Reserved MDCR_EL3.&lt;NSTBE,NSTB&gt; or MDCR_EL3.&lt;NSPBE,NSPB&gt; value</line>
<line link="Unpredictable_RESERVEDNSxB" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_RESERVEDNSxB">                            <anchor link="Unpredictable_RESERVEDNSxB" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESERVEDNSxB</anchor>,</line>
<line>                           // WFET or WFIT instruction in Debug state</line>
<line link="Unpredictable_WFxTDEBUG" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_WFxTDEBUG">                           <anchor link="Unpredictable_WFxTDEBUG" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_WFxTDEBUG</anchor>,</line>
<line>                           // Address does not support LS64 instructions</line>
<line link="Unpredictable_LS64UNSUPPORTED" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_LS64UNSUPPORTED">                           <anchor link="Unpredictable_LS64UNSUPPORTED" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_LS64UNSUPPORTED</anchor>,</line>
<line>                           // Misaligned exclusives, atomics, acquire/release</line>
<line>                           // to region that is not Normal Cacheable WB</line>
<line link="Unpredictable_MISALIGNEDATOMIC" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_MISALIGNEDATOMIC">                           <anchor link="Unpredictable_MISALIGNEDATOMIC" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_MISALIGNEDATOMIC</anchor>,</line>
<line>                           // Clearing DCC/ITR sticky flags when instruction is in flight</line>
<line link="Unpredictable_CLEARERRITEZERO" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_CLEARERRITEZERO">                           <anchor link="Unpredictable_CLEARERRITEZERO" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_CLEARERRITEZERO</anchor>,</line>
<line>                           // ALUEXCEPTIONRETURN when in user/system mode in</line>
<line>                           // A32 instructions</line>
<line link="Unpredictable_ALUEXCEPTIONRETURN" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_ALUEXCEPTIONRETURN">                           <anchor link="Unpredictable_ALUEXCEPTIONRETURN" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_ALUEXCEPTIONRETURN</anchor>,</line>
<line>                           // Trap to register in debug state are ignored</line>
<line link="Unpredictable_IGNORETRAPINDEBUG" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_IGNORETRAPINDEBUG">                           <anchor link="Unpredictable_IGNORETRAPINDEBUG" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_IGNORETRAPINDEBUG</anchor>,</line>
<line>                           // Compare DBGBVR.RESS for BP/WP</line>
<line link="Unpredictable_DBGxVR_RESS" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_DBGxVR_RESS">                           <anchor link="Unpredictable_DBGxVR_RESS" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_DBGxVR_RESS</anchor>,</line>
<line>                           // Inaccessible event counter</line>
<line link="Unpredictable_PMUEVENTCOUNTER" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_PMUEVENTCOUNTER">                           <anchor link="Unpredictable_PMUEVENTCOUNTER" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_PMUEVENTCOUNTER</anchor>,</line>
<line>                           // Reserved PMSCR.PCT behavior.</line>
<line link="Unpredictable_PMSCR_PCT" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_PMSCR_PCT">                           <anchor link="Unpredictable_PMSCR_PCT" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_PMSCR_PCT</anchor>,</line>
<line>                           // MDCR_EL2.HPMN or HDCR.HPMN is larger than PMCR.N or</line>
<line>                           // FEAT_HPMN0 is not implemented and HPMN is 0.</line>
<line link="Unpredictable_CounterReservedForEL2" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_CounterReservedForEL2">                           <anchor link="Unpredictable_CounterReservedForEL2" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_CounterReservedForEL2</anchor>,</line>
<line>                           // Generate BRB_FILTRATE event on BRB injection</line>
<line link="Unpredictable_BRBFILTRATE" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_BRBFILTRATE">                           <anchor link="Unpredictable_BRBFILTRATE" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_BRBFILTRATE</anchor>,</line>
<line>                          // Operands for CPY*/SET* instructions overlap or</line>
<line>                          // use 0b11111 as a register specifier</line>
<line link="Unpredictable_MOPSOVERLAP31" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_MOPSOVERLAP31">                          <anchor link="Unpredictable_MOPSOVERLAP31" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_MOPSOVERLAP31</anchor>,</line>
<line>                          // Store-only Tag checking on a failed Atomic Compare and Swap</line>
<line link="Unpredictable_STOREONLYTAGCHECKEDCAS" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_STOREONLYTAGCHECKEDCAS">                          <anchor link="Unpredictable_STOREONLYTAGCHECKEDCAS" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_STOREONLYTAGCHECKEDCAS</anchor>,</line>
<line>                           // Reserved PMEVTYPER&lt;n&gt;_EL0.TC value</line>
<line link="Unpredictable_RESTC" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }" conts="Unpredictable_RESTC">                           <anchor link="Unpredictable_RESTC" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESTC</anchor></line>
<line>};</line>
</pstext>
    </ps>
    <ps name="shared/functions/vector/AdvSIMDExpandImm" mylink="shared.functions.vector.AdvSIMDExpandImm" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AdvSIMDExpandImm()</line>
<line>// ==================</line>
<line></line>
<line link="impl-shared.AdvSIMDExpandImm.3" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)" conts="AdvSIMDExpandImm">bits(64) <anchor link="impl-shared.AdvSIMDExpandImm.3" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</anchor>(bit op, bits(4) cmode, bits(8) imm8)</line>
<line>    bits(64) imm64;</line>
<line>    case cmode&lt;3:1&gt; of</line>
<line>        when '000'</line>
<line>            imm64 = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(24):imm8, 2);</line>
<line>        when '001'</line>
<line>            imm64 = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16):imm8:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8), 2);</line>
<line>        when '010'</line>
<line>            imm64 = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8):imm8:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16), 2);</line>
<line>        when '011'</line>
<line>            imm64 = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(imm8:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(24), 2);</line>
<line>        when '100'</line>
<line>            imm64 = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8):imm8, 4);</line>
<line>        when '101'</line>
<line>            imm64 = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(imm8:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8), 4);</line>
<line>        when '110'</line>
<line>            if cmode&lt;0&gt; == '0' then</line>
<line>                imm64 = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16):imm8:<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(8), 2);</line>
<line>            else</line>
<line>                imm64 = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8):imm8:<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(16), 2);</line>
<line>        when '111'</line>
<line>            if cmode&lt;0&gt; == '0' &amp;&amp; op == '0' then</line>
<line>                imm64 = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(imm8, 8);</line>
<line>            if cmode&lt;0&gt; == '0' &amp;&amp; op == '1' then</line>
<line>                imm8a = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(imm8&lt;7&gt;, 8); imm8b = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(imm8&lt;6&gt;, 8);</line>
<line>                imm8c = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(imm8&lt;5&gt;, 8); imm8d = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(imm8&lt;4&gt;, 8);</line>
<line>                imm8e = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(imm8&lt;3&gt;, 8); imm8f = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(imm8&lt;2&gt;, 8);</line>
<line>                imm8g = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(imm8&lt;1&gt;, 8); imm8h = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(imm8&lt;0&gt;, 8);</line>
<line>                imm64 = imm8a:imm8b:imm8c:imm8d:imm8e:imm8f:imm8g:imm8h;</line>
<line>            if cmode&lt;0&gt; == '1' &amp;&amp; op == '0' then</line>
<line>                imm32 = imm8&lt;7&gt;:NOT(imm8&lt;6&gt;):<a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(imm8&lt;6&gt;,5):imm8&lt;5:0&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(19);</line>
<line>                imm64 = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(imm32, 2);</line>
<line>            if cmode&lt;0&gt; == '1' &amp;&amp; op == '1' then</line>
<line>                if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then ReservedEncoding();</line>
<line>                imm64 = imm8&lt;7&gt;:NOT(imm8&lt;6&gt;):<a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(imm8&lt;6&gt;,8):imm8&lt;5:0&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(48);</line>
<line></line>
<line>    return imm64;</line>
</pstext>
    </ps>
    <ps name="shared/functions/vector/MatMulAdd" mylink="shared.functions.vector.MatMulAdd" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// MatMulAdd()</line>
<line>// ===========</line>
<line>//</line>
<line>// Signed or unsigned 8-bit integer matrix multiply and add to 32-bit integer matrix</line>
<line>// result[2, 2] = addend[2, 2] + (op1[2, 8] * op2[8, 2])</line>
<line></line>
<line link="impl-shared.MatMulAdd.5" hover="function: bits(N) MatMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, boolean op1_unsigned, boolean op2_unsigned)" conts="MatMulAdd">bits(N) <anchor link="impl-shared.MatMulAdd.5" hover="function: bits(N) MatMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, boolean op1_unsigned, boolean op2_unsigned)">MatMulAdd</anchor>(bits(N) addend, bits(N) op1, bits(N) op2, boolean op1_unsigned,</line>
<line>                  boolean op2_unsigned)</line>
<line>    assert N == 128;</line>
<line></line>
<line>    bits(N)  result;</line>
<line>    bits(32) sum;</line>
<line>    integer  prod;</line>
<line></line>
<line>    for i = 0 to 1</line>
<line>        for j = 0 to 1</line>
<line>            sum = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[addend, 2*i + j, 32];</line>
<line>            for k = 0 to 7</line>
<line>                prod = (<a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[op1, 8*i + k, 8], op1_unsigned) *</line>
<line>                        <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[op2, 8*j + k, 8], op2_unsigned));</line>
<line>                sum  = sum + prod;</line>
<line>            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*i + j, 32] = sum;</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/vector/PolynomialMult" mylink="shared.functions.vector.PolynomialMult" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PolynomialMult()</line>
<line>// ================</line>
<line></line>
<line link="impl-shared.PolynomialMult.2" hover="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)" conts="PolynomialMult">bits(M+N) <anchor link="impl-shared.PolynomialMult.2" hover="function: bits(M+N) PolynomialMult(bits(M) op1, bits(N) op2)">PolynomialMult</anchor>(bits(M) op1, bits(N) op2)</line>
<line>    result = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(M+N);</line>
<line>    extended_op2 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(op2, M+N);</line>
<line>    for i=0 to M-1</line>
<line>        if op1&lt;i&gt; == '1' then</line>
<line>            result = result EOR <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(extended_op2, i);</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/vector/SatQ" mylink="shared.functions.vector.SatQ" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SatQ()</line>
<line>// ======</line>
<line></line>
<line link="impl-shared.SatQ.3" hover="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)" conts="SatQ">(bits(N), boolean) <anchor link="impl-shared.SatQ.3" hover="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</anchor>(integer i, integer N, boolean unsigned)</line>
<line>    (result, sat) = if unsigned then <a link="impl-shared.UnsignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</a>(i, N) else <a link="impl-shared.SignedSatQ.2" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</a>(i, N);</line>
<line>    return (result, sat);</line>
</pstext>
    </ps>
    <ps name="shared/functions/vector/SignedSatQ" mylink="shared.functions.vector.SignedSatQ" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SignedSatQ()</line>
<line>// ============</line>
<line></line>
<line link="impl-shared.SignedSatQ.2" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)" conts="SignedSatQ">(bits(N), boolean) <anchor link="impl-shared.SignedSatQ.2" hover="function: (bits(N), boolean) SignedSatQ(integer i, integer N)">SignedSatQ</anchor>(integer i, integer N)</line>
<line>    integer result;</line>
<line>    boolean saturated;</line>
<line>    if i &gt; 2^(N-1) - 1 then</line>
<line>        result = 2^(N-1) - 1;  saturated = TRUE;</line>
<line>    elsif i &lt; -(2^(N-1)) then</line>
<line>        result = -(2^(N-1));  saturated = TRUE;</line>
<line>    else</line>
<line>        result = i;  saturated = FALSE;</line>
<line>    return (result&lt;N-1:0&gt;, saturated);</line>
</pstext>
    </ps>
    <ps name="shared/functions/vector/UnsignedRSqrtEstimate" mylink="shared.functions.vector.UnsignedRSqrtEstimate" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// UnsignedRSqrtEstimate()</line>
<line>// =======================</line>
<line></line>
<line link="impl-shared.UnsignedRSqrtEstimate.1" hover="function: bits(N) UnsignedRSqrtEstimate(bits(N) operand)" conts="UnsignedRSqrtEstimate">bits(N) <anchor link="impl-shared.UnsignedRSqrtEstimate.1" hover="function: bits(N) UnsignedRSqrtEstimate(bits(N) operand)">UnsignedRSqrtEstimate</anchor>(bits(N) operand)</line>
<line>    assert N == 32;</line>
<line>    bits(N) result;</line>
<line>    if operand&lt;N-1:N-2&gt; == '00' then  // Operands &lt;= 0x3FFFFFFF produce 0xFFFFFFFF</line>
<line>        result = <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(N);</line>
<line>    else</line>
<line>        // input is in the range 0x40000000 .. 0xffffffff representing [0.25 .. 1.0)</line>
<line>        // estimate is in the range 256 .. 511 representing [1.0 .. 2.0)</line>
<line>        increasedprecision = FALSE;</line>
<line>        estimate = <a link="impl-shared.RecipSqrtEstimate.2" file="shared_pseudocode.xml" hover="function: integer RecipSqrtEstimate(integer a_in, boolean increasedprecision)">RecipSqrtEstimate</a>(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(operand&lt;31:23&gt;), increasedprecision);</line>
<line>        // result is in the range 0x80000000 .. 0xff800000 representing [1.0 .. 2.0)</line>
<line>        result = estimate&lt;8:0&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(N-9);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/vector/UnsignedRecipEstimate" mylink="shared.functions.vector.UnsignedRecipEstimate" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// UnsignedRecipEstimate()</line>
<line>// =======================</line>
<line></line>
<line link="impl-shared.UnsignedRecipEstimate.1" hover="function: bits(N) UnsignedRecipEstimate(bits(N) operand)" conts="UnsignedRecipEstimate">bits(N) <anchor link="impl-shared.UnsignedRecipEstimate.1" hover="function: bits(N) UnsignedRecipEstimate(bits(N) operand)">UnsignedRecipEstimate</anchor>(bits(N) operand)</line>
<line>    assert N == 32;</line>
<line>    bits(N) result;</line>
<line>    if operand&lt;N-1&gt; == '0' then  // Operands &lt;= 0x7FFFFFFF produce 0xFFFFFFFF</line>
<line>        result = <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(N);</line>
<line>    else</line>
<line>        // input is in the range 0x80000000 .. 0xffffffff representing [0.5 .. 1.0)</line>
<line></line>
<line>        // estimate is in the range 256 to 511 representing [1.0 .. 2.0)</line>
<line>        increasedprecision = FALSE;</line>
<line>        estimate = <a link="impl-shared.RecipEstimate.2" file="shared_pseudocode.xml" hover="function: integer RecipEstimate(integer a_in, boolean increasedprecision)">RecipEstimate</a>(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(operand&lt;31:23&gt;), increasedprecision);</line>
<line></line>
<line>        // result is in the range 0x80000000 .. 0xff800000 representing [1.0 .. 2.0)</line>
<line>        result = estimate&lt;8:0&gt; : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(N-9);</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/functions/vector/UnsignedSatQ" mylink="shared.functions.vector.UnsignedSatQ" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// UnsignedSatQ()</line>
<line>// ==============</line>
<line></line>
<line link="impl-shared.UnsignedSatQ.2" hover="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)" conts="UnsignedSatQ">(bits(N), boolean) <anchor link="impl-shared.UnsignedSatQ.2" hover="function: (bits(N), boolean) UnsignedSatQ(integer i, integer N)">UnsignedSatQ</anchor>(integer i, integer N)</line>
<line>    integer result;</line>
<line>    boolean saturated;</line>
<line>    if i &gt; 2^N - 1 then</line>
<line>        result = 2^N - 1;  saturated = TRUE;</line>
<line>    elsif i &lt; 0 then</line>
<line>        result = 0;  saturated = TRUE;</line>
<line>    else</line>
<line>        result = i;  saturated = FALSE;</line>
<line>    return (result&lt;N-1:0&gt;, saturated);</line>
</pstext>
    </ps>
    <ps name="shared/trace/Common/DebugMemWrite" mylink="shared.trace.Common.DebugMemWrite" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DebugMemWrite()</line>
<line>// ===============</line>
<line>// Write data to memory one byte at a time. Starting at the passed virtual address.</line>
<line>// Used by SPE.</line>
<line></line>
<line link="impl-shared.DebugMemWrite.4" hover="function: (PhysMemRetStatus, AddressDescriptor) DebugMemWrite(bits(64) vaddress, AccessDescriptor accdesc, boolean aligned, bits(8) data)" conts="DebugMemWrite">(PhysMemRetStatus, AddressDescriptor) <anchor link="impl-shared.DebugMemWrite.4" hover="function: (PhysMemRetStatus, AddressDescriptor) DebugMemWrite(bits(64) vaddress, AccessDescriptor accdesc, boolean aligned, bits(8) data)">DebugMemWrite</anchor>(bits(64) vaddress, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc,</line>
<line>                                                    boolean aligned, bits(8) data)</line>
<line></line>
<line>    <a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> memstatus = <a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> UNKNOWN;</line>
<line></line>
<line>    // Translate virtual address</line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> addrdesc;</line>
<line>    integer size = 1;</line>
<line>    addrdesc = <a link="AArch64.TranslateAddress.4" file="shared_pseudocode.xml" hover="function: AddressDescriptor AArch64.TranslateAddress(bits(64) va, AccessDescriptor accdesc, boolean aligned, integer size)">AArch64.TranslateAddress</a>(vaddress, accdesc, aligned, size);</line>
<line></line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(addrdesc) then</line>
<line>        return (memstatus, addrdesc);</line>
<line></line>
<line>    memstatus = <a link="impl-shared.PhysMemWrite.4" file="shared_pseudocode.xml" hover="function: PhysMemRetStatus PhysMemWrite(AddressDescriptor desc, integer size, AccessDescriptor accdesc, bits(8*size) value)">PhysMemWrite</a>(addrdesc, 1, accdesc, data);</line>
<line></line>
<line>    return (memstatus, addrdesc);</line>
</pstext>
    </ps>
    <ps name="shared/trace/Common/DebugWriteExternalAbort" mylink="shared.trace.Common.DebugWriteExternalAbort" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DebugWriteExternalAbort()</line>
<line>// =========================</line>
<line>// Populate the syndrome register for an External abort caused by a call of DebugMemWrite().</line>
<line></line>
<line link="impl-shared.DebugWriteExternalAbort.3" hover="function: DebugWriteExternalAbort(PhysMemRetStatus memstatus, AddressDescriptor addrdesc, bits(64) start_vaddr)" conts="DebugWriteExternalAbort"><anchor link="impl-shared.DebugWriteExternalAbort.3" hover="function: DebugWriteExternalAbort(PhysMemRetStatus memstatus, AddressDescriptor addrdesc, bits(64) start_vaddr)">DebugWriteExternalAbort</anchor>(<a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> memstatus, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> addrdesc,</line>
<line>                        bits(64) start_vaddr)</line>
<line></line>
<line>    boolean iswrite = TRUE;</line>
<line></line>
<line>    boolean handle_as_SError = FALSE;</line>
<line>    boolean async_external_abort = FALSE;</line>
<line>    bits(64) syndrome;</line>
<line>    case addrdesc.fault.access.acctype of</line>
<line>        when <a link="AccessType_SPE" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_SPE</a></line>
<line>            handle_as_SError = boolean IMPLEMENTATION_DEFINED "SPE SyncExternal as SError";</line>
<line>            async_external_abort = boolean IMPLEMENTATION_DEFINED "SPE async External abort";</line>
<line>            syndrome = PMBSR_EL1&lt;63:0&gt;;</line>
<line>        otherwise</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    boolean ttw_abort;</line>
<line>    ttw_abort = addrdesc.fault.statuscode IN {<a link="Fault_SyncExternalOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncExternalOnWalk</a>,</line>
<line>                                              <a link="Fault_SyncParityOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncParityOnWalk</a>};</line>
<line>    <a link="Fault" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault</a> statuscode = if ttw_abort then addrdesc.fault.statuscode else memstatus.statuscode;</line>
<line>    bit extflag = if ttw_abort then addrdesc.fault.extflag else memstatus.extflag;</line>
<line>    if (statuscode IN {<a link="Fault_AsyncExternal" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncExternal</a>, <a link="Fault_AsyncParity" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncParity</a>} || handle_as_SError) then</line>
<line>        // ASYNC Fault -&gt; SError or SYNC Fault handled as SError</line>
<line>        <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = <a link="impl-shared.NoFault.0" file="shared_pseudocode.xml" hover="function: FaultRecord NoFault()">NoFault</a>();</line>
<line>        boolean parity = statuscode IN {<a link="Fault_SyncParity" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncParity</a>, <a link="Fault_AsyncParity" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncParity</a>,</line>
<line>                                        <a link="Fault_SyncParityOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_SyncParityOnWalk</a>};</line>
<line>        fault.statuscode = if parity then <a link="Fault_AsyncParity" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncParity</a> else <a link="Fault_AsyncExternal" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_AsyncExternal</a>;</line>
<line>        if <a link="impl-shared.HaveRASExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveRASExt()">HaveRASExt</a>() then</line>
<line>            fault.merrorstate = memstatus.merrorstate;</line>
<line>        fault.extflag = extflag;</line>
<line>        fault.access.acctype = addrdesc.fault.access.acctype;</line>
<line>        <a link="impl-shared.PendSErrorInterrupt.1" file="shared_pseudocode.xml" hover="function: PendSErrorInterrupt(FaultRecord fault)">PendSErrorInterrupt</a>(fault);</line>
<line>    else</line>
<line>        // SYNC Fault, not handled by SError</line>
<line>        // Generate Buffer Management Event</line>
<line>        // EA bit</line>
<line>        syndrome&lt;18&gt; = '1';</line>
<line></line>
<line>        // DL bit for SPE</line>
<line>        if addrdesc.fault.access.acctype == <a link="AccessType_SPE" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_SPE</a> &amp;&amp; (async_external_abort ||</line>
<line>            (start_vaddr != addrdesc.vaddress)) then</line>
<line>            syndrome&lt;19&gt; = '1';</line>
<line></line>
<line>        // Do not change following values if previous Buffer Management Event</line>
<line>        // has not been handled.</line>
<line>        // S bit</line>
<line>        if <a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(syndrome&lt;17&gt;) then</line>
<line>            syndrome&lt;17&gt; = '1';</line>
<line></line>
<line>            // EC bits</line>
<line>            bits(6) ec;</line>
<line>            if (<a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() &amp;&amp; addrdesc.fault.gpcf.gpf != <a link="GPCF_None" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_None</a> &amp;&amp;</line>
<line>                addrdesc.fault.gpcf.gpf != <a link="GPCF_Fail" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_Fail</a>) then</line>
<line>                ec = '011110';</line>
<line>            else</line>
<line>                ec = if addrdesc.fault.secondstage then '100101' else '100100';</line>
<line>            syndrome&lt;31:26&gt; = ec;</line>
<line></line>
<line>            // MSS bits</line>
<line>            if async_external_abort then</line>
<line>                syndrome&lt;15:0&gt; = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(10) : '010001';</line>
<line>            else</line>
<line>                syndrome&lt;15:0&gt; = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(10) : <a link="impl-shared.EncodeLDFSC.2" file="shared_pseudocode.xml" hover="function: bits(6) EncodeLDFSC(Fault statuscode, integer level)">EncodeLDFSC</a>(statuscode, addrdesc.fault.level);</line>
<line></line>
<line>        case addrdesc.fault.access.acctype of</line>
<line>            when <a link="AccessType_SPE" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_SPE</a></line>
<line>                PMBSR_EL1&lt;63:0&gt; = syndrome;</line>
<line>            otherwise</line>
<line>                <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
</pstext>
    </ps>
    <ps name="shared/trace/Common/DebugWriteFault" mylink="shared.trace.Common.DebugWriteFault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DebugWriteFault()</line>
<line>// =================</line>
<line>// Populate the syndrome register for a Translation fault caused by a call of DebugMemWrite().</line>
<line></line>
<line link="impl-shared.DebugWriteFault.2" hover="function: DebugWriteFault(bits(64) vaddress, FaultRecord fault)" conts="DebugWriteFault"><anchor link="impl-shared.DebugWriteFault.2" hover="function: DebugWriteFault(bits(64) vaddress, FaultRecord fault)">DebugWriteFault</anchor>(bits(64) vaddress, <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    bits(64) syndrome;</line>
<line>    case fault.access.acctype of</line>
<line>        when <a link="AccessType_SPE" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_SPE</a></line>
<line>            syndrome = PMBSR_EL1&lt;63:0&gt;;</line>
<line>        otherwise</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    // MSS</line>
<line>    syndrome&lt;15:0&gt; = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(10) : <a link="impl-shared.EncodeLDFSC.2" file="shared_pseudocode.xml" hover="function: bits(6) EncodeLDFSC(Fault statuscode, integer level)">EncodeLDFSC</a>(fault.statuscode, fault.level);</line>
<line></line>
<line>    // MSS2</line>
<line>    syndrome&lt;55:32&gt; = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(24);</line>
<line></line>
<line>    // EC bits</line>
<line>    bits(6) ec;</line>
<line>    if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() &amp;&amp; fault.gpcf.gpf != <a link="GPCF_None" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_None</a> &amp;&amp; fault.gpcf.gpf != <a link="GPCF_Fail" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_Fail</a> then</line>
<line>        ec = '011110';</line>
<line>    else</line>
<line>        ec = if fault.secondstage then '100101' else '100100';</line>
<line>    syndrome&lt;31:26&gt; = ec;</line>
<line></line>
<line>    // S bit</line>
<line>    syndrome&lt;17&gt; = '1';</line>
<line></line>
<line>    if fault.statuscode == <a link="Fault_Permission" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Permission</a> then</line>
<line>        // assuredonly bit</line>
<line>        syndrome&lt;39&gt; = if fault.assuredonly then '1' else '0';</line>
<line>        // overlay bit</line>
<line>        syndrome&lt;38&gt; = if fault.overlay then '1' else '0';</line>
<line>        // dirtybit</line>
<line>        syndrome&lt;37&gt; = if fault.dirtybit then '1' else '0';</line>
<line></line>
<line>    case fault.access.acctype of</line>
<line>        when <a link="AccessType_SPE" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_SPE</a></line>
<line>            PMBSR_EL1&lt;63:0&gt; = syndrome;</line>
<line>        otherwise</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    // Buffer Write Pointer already points to the address that generated the fault.</line>
<line>    // Writing to memory never started so no data loss. DL is unchanged.</line>
<line></line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/trace/Common/GetTimestamp" mylink="shared.trace.Common.GetTimestamp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GetTimestamp()</line>
<line>// ==============</line>
<line>// Returns the Timestamp depending on the type</line>
<line></line>
<line link="impl-shared.GetTimestamp.1" hover="function: bits(64) GetTimestamp(TimeStamp timeStampType)" conts="GetTimestamp">bits(64) <anchor link="impl-shared.GetTimestamp.1" hover="function: bits(64) GetTimestamp(TimeStamp timeStampType)">GetTimestamp</anchor>(<a link="TimeStamp" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp</a> timeStampType)</line>
<line>    case timeStampType of</line>
<line>        when <a link="TimeStamp_Physical" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_Physical</a></line>
<line>            return <a link="impl-shared.PhysicalCountInt.0" file="shared_pseudocode.xml" hover="function: bits(64) PhysicalCountInt()">PhysicalCountInt</a>();</line>
<line>        when <a link="TimeStamp_Virtual" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_Virtual</a></line>
<line>            return <a link="impl-shared.PhysicalCountInt.0" file="shared_pseudocode.xml" hover="function: bits(64) PhysicalCountInt()">PhysicalCountInt</a>() - CNTVOFF_EL2;</line>
<line>        when <a link="TimeStamp_OffsetPhysical" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_OffsetPhysical</a></line>
<line>            bits(64) physoff = if <a link="impl-shared.PhysicalOffsetIsValid.0" file="shared_pseudocode.xml" hover="function: boolean PhysicalOffsetIsValid()">PhysicalOffsetIsValid</a>() then CNTPOFF_EL2 else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>            return <a link="impl-shared.PhysicalCountInt.0" file="shared_pseudocode.xml" hover="function: bits(64) PhysicalCountInt()">PhysicalCountInt</a>() - physoff;</line>
<line>        when <a link="TimeStamp_None" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_None</a></line>
<line>            return <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);</line>
<line>        when <a link="TimeStamp_CoreSight" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_CoreSight</a></line>
<line>            return bits(64) IMPLEMENTATION_DEFINED "CoreSight timestamp";</line>
<line>        otherwise</line>
<line>            <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
</pstext>
    </ps>
    <ps name="shared/trace/Common/PhysicalOffsetIsValid" mylink="shared.trace.Common.PhysicalOffsetIsValid" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PhysicalOffsetIsValid()</line>
<line>// =======================</line>
<line>// Returns whether the Physical offset for the timestamp is valid</line>
<line></line>
<line link="impl-shared.PhysicalOffsetIsValid.0" hover="function: boolean PhysicalOffsetIsValid()" conts="PhysicalOffsetIsValid">boolean <anchor link="impl-shared.PhysicalOffsetIsValid.0" hover="function: boolean PhysicalOffsetIsValid()">PhysicalOffsetIsValid</anchor>()</line>
<line>    if !<a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then</line>
<line>        return FALSE;</line>
<line>    elsif !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) || !<a link="impl-shared.HaveECVExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveECVExt()">HaveECVExt</a>() then</line>
<line>        return FALSE;</line>
<line>    elsif <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.NS == '1' &amp;&amp; <a link="impl-shared.EffectiveSCR_EL3_RW.0" file="shared_pseudocode.xml" hover="function: bit EffectiveSCR_EL3_RW()">EffectiveSCR_EL3_RW</a>() == '0' then</line>
<line>        return FALSE;</line>
<line>    elsif <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR_EL3.ECVEn == '0' then</line>
<line>        return FALSE;</line>
<line>    elsif CNTHCTL_EL2.ECV == '0' then</line>
<line>        return FALSE;</line>
<line>    else</line>
<line>        return TRUE;</line>
</pstext>
    </ps>
    <ps name="shared/trace/TraceBranch/BranchNotTaken" mylink="shared.trace.TraceBranch.BranchNotTaken" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// BranchNotTaken()</line>
<line>// ================</line>
<line>// Called when a branch is not taken.</line>
<line></line>
<line link="impl-shared.BranchNotTaken.2" hover="function: BranchNotTaken(BranchType branchtype, boolean branch_conditional)" conts="BranchNotTaken"><anchor link="impl-shared.BranchNotTaken.2" hover="function: BranchNotTaken(BranchType branchtype, boolean branch_conditional)">BranchNotTaken</anchor>(<a link="BranchType" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType</a> branchtype, boolean branch_conditional)</line>
<line>    boolean branchtaken = FALSE;</line>
<line>    if <a link="impl-shared.HaveStatisticalProfiling.0" file="shared_pseudocode.xml" hover="function: boolean HaveStatisticalProfiling()">HaveStatisticalProfiling</a>() then</line>
<line>        <a link="impl-aarch64.SPEBranch.4" file="shared_pseudocode.xml" hover="function: SPEBranch(bits(N) target, BranchType branch_type, boolean conditional, boolean taken_flag)">SPEBranch</a>(bits(64) UNKNOWN, branchtype, branch_conditional, branchtaken);</line>
<line>    return;</line>
</pstext>
    </ps>
    <ps name="shared/trace/TraceBuffer/TraceBufferEnabled" mylink="shared.trace.TraceBuffer.TraceBufferEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TraceBufferEnabled()</line>
<line>// ====================</line>
<line></line>
<line link="impl-shared.TraceBufferEnabled.0" hover="function: boolean TraceBufferEnabled()" conts="TraceBufferEnabled">boolean <anchor link="impl-shared.TraceBufferEnabled.0" hover="function: boolean TraceBufferEnabled()">TraceBufferEnabled</anchor>()</line>
<line>    if !<a link="impl-shared.HaveTraceBufferExtension.0" file="shared_pseudocode.xml" hover="function: boolean HaveTraceBufferExtension()">HaveTraceBufferExtension</a>() || TRBLIMITR_EL1.E == '0' then</line>
<line>        return FALSE;</line>
<line>    if !<a link="impl-shared.SelfHostedTraceEnabled.0" file="shared_pseudocode.xml" hover="function: boolean SelfHostedTraceEnabled()">SelfHostedTraceEnabled</a>() then</line>
<line>        return FALSE;</line>
<line>    (-, el) = <a link="impl-shared.TraceBufferOwner.0" file="shared_pseudocode.xml" hover="function: (SecurityState, bits(2)) TraceBufferOwner()">TraceBufferOwner</a>();</line>
<line>    return !<a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(el);</line>
</pstext>
    </ps>
    <ps name="shared/trace/TraceBuffer/TraceBufferOwner" mylink="shared.trace.TraceBuffer.TraceBufferOwner" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TraceBufferOwner()</line>
<line>// ==================</line>
<line>// Return the owning Security state and Exception level. Must only be called</line>
<line>// when SelfHostedTraceEnabled() is TRUE.</line>
<line></line>
<line link="impl-shared.TraceBufferOwner.0" hover="function: (SecurityState, bits(2)) TraceBufferOwner()" conts="TraceBufferOwner">(SecurityState, bits(2)) <anchor link="impl-shared.TraceBufferOwner.0" hover="function: (SecurityState, bits(2)) TraceBufferOwner()">TraceBufferOwner</anchor>()</line>
<line>    assert <a link="impl-shared.HaveTraceBufferExtension.0" file="shared_pseudocode.xml" hover="function: boolean HaveTraceBufferExtension()">HaveTraceBufferExtension</a>() &amp;&amp; <a link="impl-shared.SelfHostedTraceEnabled.0" file="shared_pseudocode.xml" hover="function: boolean SelfHostedTraceEnabled()">SelfHostedTraceEnabled</a>();</line>
<line></line>
<line>    <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> owning_ss;</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        bits(3) state_bits;</line>
<line>        if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then</line>
<line>            state_bits = MDCR_EL3.&lt;NSTBE,NSTB&gt;;</line>
<line>            if (state_bits IN {'10x'} ||</line>
<line>                (!<a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>() &amp;&amp; state_bits IN {'00x'})) then</line>
<line>                // Reserved value</line>
<line>                (-, state_bits) = <a link="impl-shared.ConstrainUnpredictableBits.2" file="shared_pseudocode.xml" hover="function: (Constraint,bits(width)) ConstrainUnpredictableBits(Unpredictable which, integer width)">ConstrainUnpredictableBits</a>(<a link="Unpredictable_RESERVEDNSxB" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESERVEDNSxB</a>, 3);</line>
<line>        else</line>
<line>            state_bits = '0' : MDCR_EL3.NSTB;</line>
<line></line>
<line>        case state_bits of</line>
<line>            when '00x' owning_ss = <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>;</line>
<line>            when '01x' owning_ss = <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a>;</line>
<line>            when '11x' owning_ss = <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>;</line>
<line>    else</line>
<line>        owning_ss = if <a link="impl-shared.SecureOnlyImplementation.0" file="shared_pseudocode.xml" hover="function: boolean SecureOnlyImplementation()">SecureOnlyImplementation</a>() then <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> else <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a>;</line>
<line>    bits(2) owning_el;</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) &amp;&amp; (owning_ss != <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> || <a link="impl-shared.IsSecureEL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean IsSecureEL2Enabled()">IsSecureEL2Enabled</a>()) then</line>
<line>        owning_el = if MDCR_EL2.E2TB == '00' then <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> else <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>    else</line>
<line>        owning_el = <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line>    return (owning_ss, owning_el);</line>
</pstext>
    </ps>
    <ps name="shared/trace/TraceBuffer/TraceBufferRunning" mylink="shared.trace.TraceBuffer.TraceBufferRunning" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TraceBufferRunning()</line>
<line>// ====================</line>
<line></line>
<line link="impl-shared.TraceBufferRunning.0" hover="function: boolean TraceBufferRunning()" conts="TraceBufferRunning">boolean <anchor link="impl-shared.TraceBufferRunning.0" hover="function: boolean TraceBufferRunning()">TraceBufferRunning</anchor>()</line>
<line>    return <a link="impl-shared.TraceBufferEnabled.0" file="shared_pseudocode.xml" hover="function: boolean TraceBufferEnabled()">TraceBufferEnabled</a>() &amp;&amp; TRBSR_EL1.S == '0';</line>
</pstext>
    </ps>
    <ps name="shared/trace/TraceInstrumentationAllowed/TraceInstrumentationAllowed" mylink="shared.trace.TraceInstrumentationAllowed.TraceInstrumentationAllowed" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TraceInstrumentationAllowed()</line>
<line>// =============================</line>
<line>// Returns TRUE if Instrumentation Trace is allowed</line>
<line>// in the given Exception level and Security state.</line>
<line></line>
<line link="impl-shared.TraceInstrumentationAllowed.2" hover="function: boolean TraceInstrumentationAllowed(SecurityState ss, bits(2) el)" conts="TraceInstrumentationAllowed">boolean <anchor link="impl-shared.TraceInstrumentationAllowed.2" hover="function: boolean TraceInstrumentationAllowed(SecurityState ss, bits(2) el)">TraceInstrumentationAllowed</anchor>(<a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss, bits(2) el)</line>
<line>    if !IsFeatureImplemented(FEAT_ITE) then return FALSE;</line>
<line>    if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(el) then return FALSE;</line>
<line></line>
<line>    if <a link="impl-shared.TraceAllowed.1" file="shared_pseudocode.xml" hover="function: boolean TraceAllowed(bits(2) el)">TraceAllowed</a>(el) then</line>
<line>        bit ite_bit;</line>
<line>        case el of</line>
<line>            when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> ite_bit = '0';</line>
<line>            when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> ite_bit = TRCITECR_EL2.E2E;</line>
<line>            when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> ite_bit = TRCITECR_EL1.E1E;</line>
<line>            when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>                if <a link="impl-shared.EffectiveTGE.0" file="shared_pseudocode.xml" hover="function: bit EffectiveTGE()">EffectiveTGE</a>() == '1' then</line>
<line>                    ite_bit = TRCITECR_EL2.E0HE;</line>
<line>                else</line>
<line>                    ite_bit = TRCITECR_EL1.E0E;</line>
<line></line>
<line>        if <a link="impl-shared.SelfHostedTraceEnabled.0" file="shared_pseudocode.xml" hover="function: boolean SelfHostedTraceEnabled()">SelfHostedTraceEnabled</a>() then</line>
<line>            return ite_bit == '1';</line>
<line>        else</line>
<line>            bit el_bit;</line>
<line>            bit ss_bit;</line>
<line>            case el of</line>
<line>                when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> el_bit = TRCITEEDCR.E0;</line>
<line>                when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> el_bit = TRCITEEDCR.E1;</line>
<line>                when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> el_bit = TRCITEEDCR.E2;</line>
<line>                when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> el_bit = TRCITEEDCR.E3;</line>
<line>            case ss of</line>
<line>                when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a>     ss_bit = TRCITEEDCR.RL;</line>
<line>                when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>    ss_bit = TRCITEEDCR.S;</line>
<line>                when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a> ss_bit = TRCITEEDCR.NS;</line>
<line>                otherwise ss_bit = '1';</line>
<line></line>
<line>            boolean ed_allowed = ss_bit == '1' &amp;&amp; el_bit == '1';</line>
<line></line>
<line>            if TRCCONFIGR.ITO == '1' then</line>
<line>                return ed_allowed;</line>
<line>            else</line>
<line>                return ed_allowed &amp;&amp; ite_bit == '1';</line>
<line>    else</line>
<line>        return FALSE;</line>
</pstext>
    </ps>
    <ps name="shared/trace/selfhosted/EffectiveE0HTRE" mylink="shared.trace.selfhosted.EffectiveE0HTRE" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EffectiveE0HTRE()</line>
<line>// =================</line>
<line>// Returns effective E0HTRE value</line>
<line></line>
<line link="impl-shared.EffectiveE0HTRE.0" hover="function: bit EffectiveE0HTRE()" conts="EffectiveE0HTRE">bit <anchor link="impl-shared.EffectiveE0HTRE.0" hover="function: bit EffectiveE0HTRE()">EffectiveE0HTRE</anchor>()</line>
<line>    return if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then HTRFCR.E0HTRE else TRFCR_EL2.E0HTRE;</line>
</pstext>
    </ps>
    <ps name="shared/trace/selfhosted/EffectiveE0TRE" mylink="shared.trace.selfhosted.EffectiveE0TRE" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EffectiveE0TRE()</line>
<line>// ================</line>
<line>// Returns effective E0TRE value</line>
<line></line>
<line link="impl-shared.EffectiveE0TRE.0" hover="function: bit EffectiveE0TRE()" conts="EffectiveE0TRE">bit <anchor link="impl-shared.EffectiveE0TRE.0" hover="function: bit EffectiveE0TRE()">EffectiveE0TRE</anchor>()</line>
<line>    return if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>) then TRFCR.E0TRE else TRFCR_EL1.E0TRE;</line>
</pstext>
    </ps>
    <ps name="shared/trace/selfhosted/EffectiveE1TRE" mylink="shared.trace.selfhosted.EffectiveE1TRE" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EffectiveE1TRE()</line>
<line>// ================</line>
<line>// Returns effective E1TRE value</line>
<line></line>
<line link="impl-shared.EffectiveE1TRE.0" hover="function: bit EffectiveE1TRE()" conts="EffectiveE1TRE">bit <anchor link="impl-shared.EffectiveE1TRE.0" hover="function: bit EffectiveE1TRE()">EffectiveE1TRE</anchor>()</line>
<line>    return if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then TRFCR.E1TRE else TRFCR_EL1.E1TRE;</line>
</pstext>
    </ps>
    <ps name="shared/trace/selfhosted/EffectiveE2TRE" mylink="shared.trace.selfhosted.EffectiveE2TRE" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EffectiveE2TRE()</line>
<line>// ================</line>
<line>// Returns effective E2TRE value</line>
<line></line>
<line link="impl-shared.EffectiveE2TRE.0" hover="function: bit EffectiveE2TRE()" conts="EffectiveE2TRE">bit <anchor link="impl-shared.EffectiveE2TRE.0" hover="function: bit EffectiveE2TRE()">EffectiveE2TRE</anchor>()</line>
<line>    return if <a link="impl-shared.UsingAArch32.0" file="shared_pseudocode.xml" hover="function: boolean UsingAArch32()">UsingAArch32</a>() then HTRFCR.E2TRE else TRFCR_EL2.E2TRE;</line>
</pstext>
    </ps>
    <ps name="shared/trace/selfhosted/SelfHostedTraceEnabled" mylink="shared.trace.selfhosted.SelfHostedTraceEnabled" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SelfHostedTraceEnabled()</line>
<line>// ========================</line>
<line>// Returns TRUE if Self-hosted Trace is enabled.</line>
<line></line>
<line link="impl-shared.SelfHostedTraceEnabled.0" hover="function: boolean SelfHostedTraceEnabled()" conts="SelfHostedTraceEnabled">boolean <anchor link="impl-shared.SelfHostedTraceEnabled.0" hover="function: boolean SelfHostedTraceEnabled()">SelfHostedTraceEnabled</anchor>()</line>
<line>    bit secure_trace_enable = '0';</line>
<line>    if !(<a link="impl-shared.HaveTraceExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTraceExt()">HaveTraceExt</a>() &amp;&amp; <a link="impl-shared.HaveSelfHostedTrace.0" file="shared_pseudocode.xml" hover="function: boolean HaveSelfHostedTrace()">HaveSelfHostedTrace</a>()) then return FALSE;</line>
<line>    if EDSCR.TFO == '0' then return TRUE;</line>
<line>    if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then</line>
<line>        secure_trace_enable = if <a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>() then MDCR_EL3.STE else '0';</line>
<line>        return ((secure_trace_enable == '1' &amp;&amp; !<a link="impl-shared.ExternalSecureNoninvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalSecureNoninvasiveDebugEnabled()">ExternalSecureNoninvasiveDebugEnabled</a>()) ||</line>
<line>                (MDCR_EL3.RLTE == '1' &amp;&amp; !<a link="impl-shared.ExternalRealmNoninvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalRealmNoninvasiveDebugEnabled()">ExternalRealmNoninvasiveDebugEnabled</a>()));</line>
<line>    if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>        secure_trace_enable = if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then SDCR.STE else MDCR_EL3.STE;</line>
<line>    else</line>
<line>        secure_trace_enable = if <a link="impl-shared.SecureOnlyImplementation.0" file="shared_pseudocode.xml" hover="function: boolean SecureOnlyImplementation()">SecureOnlyImplementation</a>() then '1' else '0';</line>
<line></line>
<line>    if secure_trace_enable == '1' &amp;&amp; !<a link="impl-shared.ExternalSecureNoninvasiveDebugEnabled.0" file="shared_pseudocode.xml" hover="function: boolean ExternalSecureNoninvasiveDebugEnabled()">ExternalSecureNoninvasiveDebugEnabled</a>() then</line>
<line>        return TRUE;</line>
<line></line>
<line>    return FALSE;</line>
</pstext>
    </ps>
    <ps name="shared/trace/selfhosted/TraceAllowed" mylink="shared.trace.selfhosted.TraceAllowed" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TraceAllowed()</line>
<line>// ==============</line>
<line>// Returns TRUE if Self-hosted Trace is allowed in the given Exception level.</line>
<line></line>
<line link="impl-shared.TraceAllowed.1" hover="function: boolean TraceAllowed(bits(2) el)" conts="TraceAllowed">boolean <anchor link="impl-shared.TraceAllowed.1" hover="function: boolean TraceAllowed(bits(2) el)">TraceAllowed</anchor>(bits(2) el)</line>
<line>    if !<a link="impl-shared.HaveTraceExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveTraceExt()">HaveTraceExt</a>() then return FALSE;</line>
<line>    if <a link="impl-shared.SelfHostedTraceEnabled.0" file="shared_pseudocode.xml" hover="function: boolean SelfHostedTraceEnabled()">SelfHostedTraceEnabled</a>() then</line>
<line>        boolean trace_allowed;</line>
<line>        ss = <a link="impl-shared.SecurityStateAtEL.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)">SecurityStateAtEL</a>(el);</line>
<line>        // Detect scenarios where tracing in this Security state is never allowed.</line>
<line>        case ss of</line>
<line>            when <a link="SS_NonSecure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_NonSecure</a></line>
<line>                trace_allowed = TRUE;</line>
<line>            when <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a></line>
<line>                bit trace_bit;</line>
<line>                if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>                    trace_bit = if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then SDCR.STE else MDCR_EL3.STE;</line>
<line>                else</line>
<line>                    trace_bit = '1';</line>
<line>                trace_allowed = trace_bit == '1';</line>
<line>            when <a link="SS_Realm" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Realm</a></line>
<line>                trace_allowed = MDCR_EL3.RLTE == '1';</line>
<line>            when <a link="SS_Root" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Root</a></line>
<line>                trace_allowed = FALSE;</line>
<line></line>
<line>        // Tracing is prohibited if the trace buffer owning security state is not the</line>
<line>        // current Security state or the owning Exception level is a lower Exception level.</line>
<line>        if <a link="impl-shared.HaveTraceBufferExtension.0" file="shared_pseudocode.xml" hover="function: boolean HaveTraceBufferExtension()">HaveTraceBufferExtension</a>() &amp;&amp; <a link="impl-shared.TraceBufferEnabled.0" file="shared_pseudocode.xml" hover="function: boolean TraceBufferEnabled()">TraceBufferEnabled</a>() then</line>
<line>            (owning_ss, owning_el) = <a link="impl-shared.TraceBufferOwner.0" file="shared_pseudocode.xml" hover="function: (SecurityState, bits(2)) TraceBufferOwner()">TraceBufferOwner</a>();</line>
<line>            if (ss != owning_ss || <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(owning_el) &lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(el) ||</line>
<line>                (<a link="impl-shared.EffectiveTGE.0" file="shared_pseudocode.xml" hover="function: bit EffectiveTGE()">EffectiveTGE</a>() == '1' &amp;&amp; owning_el == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>)) then</line>
<line>                trace_allowed = FALSE;</line>
<line></line>
<line>        bit TRE_bit;</line>
<line>        case el of</line>
<line>            when <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>  TRE_bit = if !<a link="impl-shared.HaveAArch64.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch64()">HaveAArch64</a>() then TRFCR.E1TRE else '0';</line>
<line>            when <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>  TRE_bit = <a link="impl-shared.EffectiveE2TRE.0" file="shared_pseudocode.xml" hover="function: bit EffectiveE2TRE()">EffectiveE2TRE</a>();</line>
<line>            when <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>  TRE_bit = <a link="impl-shared.EffectiveE1TRE.0" file="shared_pseudocode.xml" hover="function: bit EffectiveE1TRE()">EffectiveE1TRE</a>();</line>
<line>            when <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a></line>
<line>                if <a link="impl-shared.EffectiveTGE.0" file="shared_pseudocode.xml" hover="function: bit EffectiveTGE()">EffectiveTGE</a>() == '1' then</line>
<line>                    TRE_bit = <a link="impl-shared.EffectiveE0HTRE.0" file="shared_pseudocode.xml" hover="function: bit EffectiveE0HTRE()">EffectiveE0HTRE</a>();</line>
<line>                else</line>
<line>                    TRE_bit = <a link="impl-shared.EffectiveE0TRE.0" file="shared_pseudocode.xml" hover="function: bit EffectiveE0TRE()">EffectiveE0TRE</a>();</line>
<line></line>
<line>        return trace_allowed &amp;&amp; TRE_bit == '1';</line>
<line>    else</line>
<line>        return <a link="impl-shared.ExternalNoninvasiveDebugAllowed.1" file="shared_pseudocode.xml" hover="function: boolean ExternalNoninvasiveDebugAllowed(bits(2) el)">ExternalNoninvasiveDebugAllowed</a>(el);</line>
</pstext>
    </ps>
    <ps name="shared/trace/selfhosted/TraceContextIDR2" mylink="shared.trace.selfhosted.TraceContextIDR2" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TraceContextIDR2()</line>
<line>// ==================</line>
<line></line>
<line link="impl-shared.TraceContextIDR2.0" hover="function: boolean TraceContextIDR2()" conts="TraceContextIDR2">boolean <anchor link="impl-shared.TraceContextIDR2.0" hover="function: boolean TraceContextIDR2()">TraceContextIDR2</anchor>()</line>
<line>    if !<a link="impl-shared.TraceAllowed.1" file="shared_pseudocode.xml" hover="function: boolean TraceAllowed(bits(2) el)">TraceAllowed</a>(PSTATE.EL)|| !<a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then return FALSE;</line>
<line>    return (!<a link="impl-shared.SelfHostedTraceEnabled.0" file="shared_pseudocode.xml" hover="function: boolean SelfHostedTraceEnabled()">SelfHostedTraceEnabled</a>() || TRFCR_EL2.CX == '1');</line>
</pstext>
    </ps>
    <ps name="shared/trace/selfhosted/TraceSynchronizationBarrier" mylink="shared.trace.selfhosted.TraceSynchronizationBarrier" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TraceSynchronizationBarrier()</line>
<line>// =============================</line>
<line>// Memory barrier instruction that preserves the relative order of memory accesses to System</line>
<line>// registers due to trace operations and other memory accesses to the same registers</line>
<line></line>
<line link="impl-shared.TraceSynchronizationBarrier.0" hover="function: TraceSynchronizationBarrier()" conts="TraceSynchronizationBarrier"><anchor link="impl-shared.TraceSynchronizationBarrier.0" hover="function: TraceSynchronizationBarrier()">TraceSynchronizationBarrier</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/trace/selfhosted/TraceTimeStamp" mylink="shared.trace.selfhosted.TraceTimeStamp" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TraceTimeStamp()</line>
<line>// ================</line>
<line></line>
<line link="impl-shared.TraceTimeStamp.0" hover="function: TimeStamp TraceTimeStamp()" conts="TraceTimeStamp">TimeStamp <anchor link="impl-shared.TraceTimeStamp.0" hover="function: TimeStamp TraceTimeStamp()">TraceTimeStamp</anchor>()</line>
<line>    if <a link="impl-shared.SelfHostedTraceEnabled.0" file="shared_pseudocode.xml" hover="function: boolean SelfHostedTraceEnabled()">SelfHostedTraceEnabled</a>() then</line>
<line>        if <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then</line>
<line>            TS_el2 = TRFCR_EL2.TS;</line>
<line>            if !<a link="impl-shared.HaveECVExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveECVExt()">HaveECVExt</a>() &amp;&amp; TS_el2 == '10' then</line>
<line>                // Reserved value</line>
<line>                (-, TS_el2) = <a link="impl-shared.ConstrainUnpredictableBits.2" file="shared_pseudocode.xml" hover="function: (Constraint,bits(width)) ConstrainUnpredictableBits(Unpredictable which, integer width)">ConstrainUnpredictableBits</a>(<a link="Unpredictable_EL2TIMESTAMP" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_EL2TIMESTAMP</a>, 2);</line>
<line></line>
<line>            case TS_el2 of</line>
<line>                when '00'</line>
<line>                    // Falls out to check TRFCR_EL1.TS</line>
<line>                when '01'</line>
<line>                    return <a link="TimeStamp_Virtual" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_Virtual</a>;</line>
<line>                when '10'</line>
<line>                    assert <a link="impl-shared.HaveECVExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveECVExt()">HaveECVExt</a>();  // Otherwise ConstrainUnpredictableBits removes this case</line>
<line>                    return <a link="TimeStamp_OffsetPhysical" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_OffsetPhysical</a>;</line>
<line>                when '11'</line>
<line>                    return <a link="TimeStamp_Physical" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_Physical</a>;</line>
<line></line>
<line>        TS_el1 = TRFCR_EL1.TS;</line>
<line>        if TS_el1 == '00' || (!<a link="impl-shared.HaveECVExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveECVExt()">HaveECVExt</a>() &amp;&amp; TS_el1 == '10') then</line>
<line>            // Reserved value</line>
<line>            (-, TS_el1) = <a link="impl-shared.ConstrainUnpredictableBits.2" file="shared_pseudocode.xml" hover="function: (Constraint,bits(width)) ConstrainUnpredictableBits(Unpredictable which, integer width)">ConstrainUnpredictableBits</a>(<a link="Unpredictable_EL1TIMESTAMP" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_EL1TIMESTAMP</a>, 2);</line>
<line></line>
<line>        case TS_el1 of</line>
<line>            when '01'</line>
<line>                return <a link="TimeStamp_Virtual" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_Virtual</a>;</line>
<line>            when '10'</line>
<line>                assert <a link="impl-shared.HaveECVExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveECVExt()">HaveECVExt</a>();</line>
<line>                return <a link="TimeStamp_OffsetPhysical" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_OffsetPhysical</a>;</line>
<line>            when '11'</line>
<line>                return <a link="TimeStamp_Physical" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_Physical</a>;</line>
<line>            otherwise</line>
<line>                <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();         // ConstrainUnpredictableBits removes this case</line>
<line>    else</line>
<line>        return <a link="TimeStamp_CoreSight" file="shared_pseudocode.xml" hover="enumeration TimeStamp { TimeStamp_None, TimeStamp_CoreSight, TimeStamp_Physical, TimeStamp_OffsetPhysical, TimeStamp_Virtual  }">TimeStamp_CoreSight</a>;</line>
</pstext>
    </ps>
    <ps name="shared/trace/system/IsTraceCorePowered" mylink="shared.trace.system.IsTraceCorePowered" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// IsTraceCorePowered()</line>
<line>// ====================</line>
<line>// Returns TRUE if the Trace Core Power Domain is powered up</line>
<line></line>
<line link="impl-shared.IsTraceCorePowered.0" hover="function: boolean IsTraceCorePowered()" conts="IsTraceCorePowered">boolean <anchor link="impl-shared.IsTraceCorePowered.0" hover="function: boolean IsTraceCorePowered()">IsTraceCorePowered</anchor>();</line>
</pstext>
    </ps>
    <ps name="shared/translation/at" mylink="shared.translation.at" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="TranslationStage" hover="enumeration TranslationStage { TranslationStage_1, TranslationStage_12 }" conts="TranslationStage">enumeration <anchor link="TranslationStage" hover="enumeration TranslationStage { TranslationStage_1, TranslationStage_12 }">TranslationStage</anchor> {</line>
<line link="TranslationStage_1" hover="enumeration TranslationStage { TranslationStage_1, TranslationStage_12 }" conts="TranslationStage_1">    <anchor link="TranslationStage_1" hover="enumeration TranslationStage { TranslationStage_1, TranslationStage_12 }">TranslationStage_1</anchor>,</line>
<line link="TranslationStage_12" hover="enumeration TranslationStage { TranslationStage_1, TranslationStage_12 }" conts="TranslationStage_12">    <anchor link="TranslationStage_12" hover="enumeration TranslationStage { TranslationStage_1, TranslationStage_12 }">TranslationStage_12</anchor></line>
<line>};</line>
<line></line>
<line link="ATAccess" hover="enumeration ATAccess { ATAccess_Read, ATAccess_Write, ATAccess_ReadPAN, ATAccess_WritePAN }" conts="ATAccess">enumeration <anchor link="ATAccess" hover="enumeration ATAccess { ATAccess_Read, ATAccess_Write, ATAccess_ReadPAN, ATAccess_WritePAN }">ATAccess</anchor> {</line>
<line link="ATAccess_Read" hover="enumeration ATAccess { ATAccess_Read, ATAccess_Write, ATAccess_ReadPAN, ATAccess_WritePAN }" conts="ATAccess_Read">    <anchor link="ATAccess_Read" hover="enumeration ATAccess { ATAccess_Read, ATAccess_Write, ATAccess_ReadPAN, ATAccess_WritePAN }">ATAccess_Read</anchor>,</line>
<line link="ATAccess_Write" hover="enumeration ATAccess { ATAccess_Read, ATAccess_Write, ATAccess_ReadPAN, ATAccess_WritePAN }" conts="ATAccess_Write">    <anchor link="ATAccess_Write" hover="enumeration ATAccess { ATAccess_Read, ATAccess_Write, ATAccess_ReadPAN, ATAccess_WritePAN }">ATAccess_Write</anchor>,</line>
<line link="ATAccess_ReadPAN" hover="enumeration ATAccess { ATAccess_Read, ATAccess_Write, ATAccess_ReadPAN, ATAccess_WritePAN }" conts="ATAccess_ReadPAN">    <anchor link="ATAccess_ReadPAN" hover="enumeration ATAccess { ATAccess_Read, ATAccess_Write, ATAccess_ReadPAN, ATAccess_WritePAN }">ATAccess_ReadPAN</anchor>,</line>
<line link="ATAccess_WritePAN" hover="enumeration ATAccess { ATAccess_Read, ATAccess_Write, ATAccess_ReadPAN, ATAccess_WritePAN }" conts="ATAccess_WritePAN">    <anchor link="ATAccess_WritePAN" hover="enumeration ATAccess { ATAccess_Read, ATAccess_Write, ATAccess_ReadPAN, ATAccess_WritePAN }">ATAccess_WritePAN</anchor></line>
<line>};</line>
</pstext>
    </ps>
    <ps name="shared/translation/at/EncodePARAttrs" mylink="shared.translation.at.EncodePARAttrs" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EncodePARAttrs()</line>
<line>// ================</line>
<line>// Convert orthogonal attributes and hints to 64-bit PAR ATTR field.</line>
<line></line>
<line link="impl-shared.EncodePARAttrs.1" hover="function: bits(8) EncodePARAttrs(MemoryAttributes memattrs)" conts="EncodePARAttrs">bits(8) <anchor link="impl-shared.EncodePARAttrs.1" hover="function: bits(8) EncodePARAttrs(MemoryAttributes memattrs)">EncodePARAttrs</anchor>(<a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs)</line>
<line>    bits(8) result;</line>
<line></line>
<line>    if <a link="impl-shared.HaveMTEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEExt()">HaveMTEExt</a>() &amp;&amp; memattrs.tags == <a link="MemTag_AllocationTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_AllocationTagged</a> then</line>
<line>        if <a link="impl-shared.HaveMTEPermExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEPermExt()">HaveMTEPermExt</a>() &amp;&amp; memattrs.notagaccess then</line>
<line>            result&lt;7:0&gt; = '11100000';</line>
<line>        else</line>
<line>            result&lt;7:0&gt; = '11110000';</line>
<line>        return result;</line>
<line></line>
<line>    if memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> then</line>
<line>        result&lt;7:4&gt; = '0000';</line>
<line>        case memattrs.device of</line>
<line>            when <a link="DeviceType_nGnRnE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGnRnE</a> result&lt;3:0&gt; = '0000';</line>
<line>            when <a link="DeviceType_nGnRE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGnRE</a>  result&lt;3:0&gt; = '0100';</line>
<line>            when <a link="DeviceType_nGRE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGRE</a>   result&lt;3:0&gt; = '1000';</line>
<line>            when <a link="DeviceType_GRE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_GRE</a>    result&lt;3:0&gt; = '1100';</line>
<line>            otherwise              <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>        result&lt;0&gt; = NOT memattrs.xs;</line>
<line>    else</line>
<line>        if memattrs.xs == '0' then</line>
<line>            if (memattrs.outer.attrs == <a link="MemAttr_WT" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WT = '10'">MemAttr_WT</a> &amp;&amp; memattrs.inner.attrs == <a link="MemAttr_WT" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WT = '10'">MemAttr_WT</a> &amp;&amp;</line>
<line>                    !memattrs.outer.transient &amp;&amp; memattrs.outer.hints == <a link="MemHint_RA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RA = '10'">MemHint_RA</a>) then</line>
<line>                return '10100000';</line>
<line>            elsif memattrs.outer.attrs == <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a> &amp;&amp; memattrs.inner.attrs == <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a> then</line>
<line>                return '01000000';</line>
<line></line>
<line>        if memattrs.outer.attrs == <a link="MemAttr_WT" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WT = '10'">MemAttr_WT</a> then</line>
<line>            result&lt;7:6&gt; = if memattrs.outer.transient then '00' else '10';</line>
<line>            result&lt;5:4&gt; = memattrs.outer.hints;</line>
<line>        elsif memattrs.outer.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a> then</line>
<line>            result&lt;7:6&gt; = if memattrs.outer.transient then '01' else '11';</line>
<line>            result&lt;5:4&gt; = memattrs.outer.hints;</line>
<line>        else // MemAttr_NC</line>
<line>            result&lt;7:4&gt; = '0100';</line>
<line></line>
<line>        if memattrs.inner.attrs == <a link="MemAttr_WT" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WT = '10'">MemAttr_WT</a> then</line>
<line>            result&lt;3:2&gt; = if memattrs.inner.transient then '00' else '10';</line>
<line>            result&lt;1:0&gt; = memattrs.inner.hints;</line>
<line>        elsif memattrs.inner.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a> then</line>
<line>            result&lt;3:2&gt; = if memattrs.inner.transient then '01' else '11';</line>
<line>            result&lt;1:0&gt; = memattrs.inner.hints;</line>
<line>        else // MemAttr_NC</line>
<line>            result&lt;3:0&gt; = '0100';</line>
<line></line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/translation/at/PAREncodeShareability" mylink="shared.translation.at.PAREncodeShareability" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PAREncodeShareability()</line>
<line>// =======================</line>
<line>// Derive 64-bit PAR SH field.</line>
<line></line>
<line link="impl-shared.PAREncodeShareability.1" hover="function: bits(2) PAREncodeShareability(MemoryAttributes memattrs)" conts="PAREncodeShareability">bits(2) <anchor link="impl-shared.PAREncodeShareability.1" hover="function: bits(2) PAREncodeShareability(MemoryAttributes memattrs)">PAREncodeShareability</anchor>(<a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs)</line>
<line>    if (memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> ||</line>
<line>            (memattrs.inner.attrs == <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a> &amp;&amp;</line>
<line>             memattrs.outer.attrs == <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a>)) then</line>
<line>        // Force Outer-Shareable on Device and Normal Non-Cacheable memory</line>
<line>        return '10';</line>
<line></line>
<line>    case memattrs.shareability of</line>
<line>        when <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a> return '00';</line>
<line>        when <a link="Shareability_ISH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_ISH</a> return '11';</line>
<line>        when <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a> return '10';</line>
</pstext>
    </ps>
    <ps name="shared/translation/at/ReportedPARAttrs" mylink="shared.translation.at.ReportedPARAttrs" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ReportedPARAttrs()</line>
<line>// ==================</line>
<line>// The value returned in this field can be the resulting attribute, as determined by any permitted</line>
<line>// implementation choices and any applicable configuration bits, instead of the value that appears</line>
<line>// in the translation table descriptor.</line>
<line></line>
<line link="impl-shared.ReportedPARAttrs.1" hover="function: bits(8) ReportedPARAttrs(bits(8) parattrs)" conts="ReportedPARAttrs">bits(8) <anchor link="impl-shared.ReportedPARAttrs.1" hover="function: bits(8) ReportedPARAttrs(bits(8) parattrs)">ReportedPARAttrs</anchor>(bits(8) parattrs);</line>
</pstext>
    </ps>
    <ps name="shared/translation/at/ReportedPARShareability" mylink="shared.translation.at.ReportedPARShareability" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ReportedPARShareability()</line>
<line>// =========================</line>
<line>// The value returned in SH field can be the resulting attribute, as determined by any</line>
<line>// permitted implementation choices and any applicable configuration bits, instead of</line>
<line>// the value that appears in the translation table descriptor.</line>
<line></line>
<line link="impl-shared.ReportedPARShareability.1" hover="function: bits(2) ReportedPARShareability(bits(2) sh)" conts="ReportedPARShareability">bits(2) <anchor link="impl-shared.ReportedPARShareability.1" hover="function: bits(2) ReportedPARShareability(bits(2) sh)">ReportedPARShareability</anchor>(bits(2) sh);</line>
</pstext>
    </ps>
    <ps name="shared/translation/attrs/DecodeDevice" mylink="shared.translation.attrs.DecodeDevice" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DecodeDevice()</line>
<line>// ==============</line>
<line>// Decode output Device type</line>
<line></line>
<line link="impl-shared.DecodeDevice.1" hover="function: DeviceType DecodeDevice(bits(2) device)" conts="DecodeDevice">DeviceType <anchor link="impl-shared.DecodeDevice.1" hover="function: DeviceType DecodeDevice(bits(2) device)">DecodeDevice</anchor>(bits(2) device)</line>
<line>    case device of</line>
<line>        when '00'   return <a link="DeviceType_nGnRnE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGnRnE</a>;</line>
<line>        when '01'   return <a link="DeviceType_nGnRE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGnRE</a>;</line>
<line>        when '10'   return <a link="DeviceType_nGRE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGRE</a>;</line>
<line>        when '11'   return <a link="DeviceType_GRE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_GRE</a>;</line>
</pstext>
    </ps>
    <ps name="shared/translation/attrs/DecodeLDFAttr" mylink="shared.translation.attrs.DecodeLDFAttr" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DecodeLDFAttr()</line>
<line>// ===============</line>
<line>// Decode memory attributes using LDF (Long Descriptor Format) mapping</line>
<line></line>
<line link="impl-shared.DecodeLDFAttr.1" hover="function: MemAttrHints DecodeLDFAttr(bits(4) attr)" conts="DecodeLDFAttr">MemAttrHints <anchor link="impl-shared.DecodeLDFAttr.1" hover="function: MemAttrHints DecodeLDFAttr(bits(4) attr)">DecodeLDFAttr</anchor>(bits(4) attr)</line>
<line>    <a link="MemAttrHints" file="shared_pseudocode.xml" hover="type MemAttrHints is ( bits(2) attrs, bits(2) hints, boolean transient )">MemAttrHints</a> ldfattr;</line>
<line></line>
<line>    if    attr IN {'x0xx'} then ldfattr.attrs = <a link="MemAttr_WT" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WT = '10'">MemAttr_WT</a>; // Write-through</line>
<line>    elsif attr == '0100' then ldfattr.attrs = <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a>;   // Non-cacheable</line>
<line>    elsif attr IN {'x1xx'} then ldfattr.attrs = <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>; // Write-back</line>
<line>    else                      <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    // Allocation hints are applicable only to cacheable memory.</line>
<line>    if ldfattr.attrs != <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a> then</line>
<line>        case attr&lt;1:0&gt; of</line>
<line>            when '00' ldfattr.hints = <a link="MemHint_No" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_No = '00'">MemHint_No</a>;  // No allocation hints</line>
<line>            when '01' ldfattr.hints = <a link="MemHint_WA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_WA = '01'">MemHint_WA</a>;  // Write-allocate</line>
<line>            when '10' ldfattr.hints = <a link="MemHint_RA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RA = '10'">MemHint_RA</a>;  // Read-allocate</line>
<line>            when '11' ldfattr.hints = <a link="MemHint_RWA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RWA = '11'">MemHint_RWA</a>; // Read/Write allocate</line>
<line></line>
<line>    // The Transient hint applies only to cacheable memory with some allocation hints.</line>
<line>    if ldfattr.attrs != <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a> &amp;&amp; ldfattr.hints != <a link="MemHint_No" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_No = '00'">MemHint_No</a> then</line>
<line>        ldfattr.transient = attr&lt;3&gt; == '0';</line>
<line></line>
<line>    return ldfattr;</line>
</pstext>
    </ps>
    <ps name="shared/translation/attrs/DecodeSDFAttr" mylink="shared.translation.attrs.DecodeSDFAttr" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DecodeSDFAttr()</line>
<line>// ===============</line>
<line>// Decode memory attributes using SDF (Short Descriptor Format) mapping</line>
<line></line>
<line link="impl-shared.DecodeSDFAttr.1" hover="function: MemAttrHints DecodeSDFAttr(bits(2) rgn)" conts="DecodeSDFAttr">MemAttrHints <anchor link="impl-shared.DecodeSDFAttr.1" hover="function: MemAttrHints DecodeSDFAttr(bits(2) rgn)">DecodeSDFAttr</anchor>(bits(2) rgn)</line>
<line>    <a link="MemAttrHints" file="shared_pseudocode.xml" hover="type MemAttrHints is ( bits(2) attrs, bits(2) hints, boolean transient )">MemAttrHints</a> sdfattr;</line>
<line></line>
<line>    case rgn of</line>
<line>        when '00'                   // Non-cacheable (no allocate)</line>
<line>            sdfattr.attrs = <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a>;</line>
<line>        when '01'                   // Write-back, Read and Write allocate</line>
<line>            sdfattr.attrs = <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>;</line>
<line>            sdfattr.hints = <a link="MemHint_RWA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RWA = '11'">MemHint_RWA</a>;</line>
<line>        when '10'                   // Write-through, Read allocate</line>
<line>            sdfattr.attrs = <a link="MemAttr_WT" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WT = '10'">MemAttr_WT</a>;</line>
<line>            sdfattr.hints = <a link="MemHint_RA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RA = '10'">MemHint_RA</a>;</line>
<line>        when '11'                   // Write-back, Read allocate</line>
<line>            sdfattr.attrs = <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>;</line>
<line>            sdfattr.hints = <a link="MemHint_RA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RA = '10'">MemHint_RA</a>;</line>
<line></line>
<line>    sdfattr.transient = FALSE;</line>
<line></line>
<line>    return sdfattr;</line>
</pstext>
    </ps>
    <ps name="shared/translation/attrs/DecodeShareability" mylink="shared.translation.attrs.DecodeShareability" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DecodeShareability()</line>
<line>// ====================</line>
<line>// Decode shareability of target memory region</line>
<line></line>
<line link="impl-shared.DecodeShareability.1" hover="function: Shareability DecodeShareability(bits(2) sh)" conts="DecodeShareability">Shareability <anchor link="impl-shared.DecodeShareability.1" hover="function: Shareability DecodeShareability(bits(2) sh)">DecodeShareability</anchor>(bits(2) sh)</line>
<line>    case sh of</line>
<line>        when '10' return <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a>;</line>
<line>        when '11' return <a link="Shareability_ISH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_ISH</a>;</line>
<line>        when '00' return <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a>;</line>
<line>        otherwise</line>
<line>            case <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_Shareability" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_Shareability</a>) of</line>
<line>                when <a link="Constraint_OSH" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_OSH</a> return <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a>;</line>
<line>                when <a link="Constraint_ISH" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_ISH</a> return <a link="Shareability_ISH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_ISH</a>;</line>
<line>                when <a link="Constraint_NSH" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NSH</a> return <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a>;</line>
</pstext>
    </ps>
    <ps name="shared/translation/attrs/EffectiveShareability" mylink="shared.translation.attrs.EffectiveShareability" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// EffectiveShareability()</line>
<line>// =======================</line>
<line>// Force Outer Shareability on Device and Normal iNCoNC memory</line>
<line></line>
<line link="impl-shared.EffectiveShareability.1" hover="function: Shareability EffectiveShareability(MemoryAttributes memattrs)" conts="EffectiveShareability">Shareability <anchor link="impl-shared.EffectiveShareability.1" hover="function: Shareability EffectiveShareability(MemoryAttributes memattrs)">EffectiveShareability</anchor>(<a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs)</line>
<line>    if (memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> ||</line>
<line>            (memattrs.inner.attrs == <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a> &amp;&amp;</line>
<line>             memattrs.outer.attrs == <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a>)) then</line>
<line>        return <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a>;</line>
<line>    else</line>
<line>        return memattrs.shareability;</line>
</pstext>
    </ps>
    <ps name="shared/translation/attrs/NormalNCMemAttr" mylink="shared.translation.attrs.NormalNCMemAttr" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// NormalNCMemAttr()</line>
<line>// =================</line>
<line>// Normal Non-cacheable memory attributes</line>
<line></line>
<line link="impl-shared.NormalNCMemAttr.0" hover="function: MemoryAttributes NormalNCMemAttr()" conts="NormalNCMemAttr">MemoryAttributes <anchor link="impl-shared.NormalNCMemAttr.0" hover="function: MemoryAttributes NormalNCMemAttr()">NormalNCMemAttr</anchor>()</line>
<line>    <a link="MemAttrHints" file="shared_pseudocode.xml" hover="type MemAttrHints is ( bits(2) attrs, bits(2) hints, boolean transient )">MemAttrHints</a> non_cacheable;</line>
<line>    non_cacheable.attrs = <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a>;</line>
<line></line>
<line>    <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> nc_memattrs;</line>
<line>    nc_memattrs.memtype      = <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>;</line>
<line>    nc_memattrs.outer        = non_cacheable;</line>
<line>    nc_memattrs.inner        = non_cacheable;</line>
<line>    nc_memattrs.shareability = <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a>;</line>
<line>    nc_memattrs.tags         = <a link="MemTag_Untagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_Untagged</a>;</line>
<line>    nc_memattrs.notagaccess  = FALSE;</line>
<line></line>
<line>    return nc_memattrs;</line>
</pstext>
    </ps>
    <ps name="shared/translation/attrs/S1ConstrainUnpredictableRESMAIR" mylink="shared.translation.attrs.S1ConstrainUnpredictableRESMAIR" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// S1ConstrainUnpredictableRESMAIR()</line>
<line>// =================================</line>
<line>// Determine whether a reserved value occupies MAIR_ELx.AttrN</line>
<line></line>
<line link="impl-shared.S1ConstrainUnpredictableRESMAIR.2" hover="function: boolean S1ConstrainUnpredictableRESMAIR(bits(8) attr, boolean s1aarch64)" conts="S1ConstrainUnpredictableRESMAIR">boolean <anchor link="impl-shared.S1ConstrainUnpredictableRESMAIR.2" hover="function: boolean S1ConstrainUnpredictableRESMAIR(bits(8) attr, boolean s1aarch64)">S1ConstrainUnpredictableRESMAIR</anchor>(bits(8) attr, boolean s1aarch64)</line>
<line>    case attr of</line>
<line>        when '0000xx01' return !(s1aarch64 &amp;&amp; <a link="impl-shared.HaveFeatXS.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatXS()">HaveFeatXS</a>());</line>
<line>        when '0000xxxx' return attr&lt;1:0&gt; != '00';</line>
<line>        when '01000000' return !(s1aarch64 &amp;&amp; <a link="impl-shared.HaveFeatXS.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatXS()">HaveFeatXS</a>());</line>
<line>        when '10100000' return !(s1aarch64 &amp;&amp; <a link="impl-shared.HaveFeatXS.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatXS()">HaveFeatXS</a>());</line>
<line>        when '11110000' return !(s1aarch64 &amp;&amp; <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>());</line>
<line>        when 'xxxx0000' return TRUE;</line>
<line>        otherwise       return FALSE;</line>
</pstext>
    </ps>
    <ps name="shared/translation/attrs/S1DecodeMemAttrs" mylink="shared.translation.attrs.S1DecodeMemAttrs" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// S1DecodeMemAttrs()</line>
<line>// ==================</line>
<line>// Decode MAIR-format memory attributes assigned in stage 1</line>
<line></line>
<line><a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> S1DecodeMemAttrs(bits(8) attr_in, bits(2) sh, boolean s1aarch64,</line>
<line>                                  S1TTWParams walkparams)</line>
<line>    bits(8) attr = attr_in;</line>
<line>    if <a link="impl-shared.S1ConstrainUnpredictableRESMAIR.2" file="shared_pseudocode.xml" hover="function: boolean S1ConstrainUnpredictableRESMAIR(bits(8) attr, boolean s1aarch64)">S1ConstrainUnpredictableRESMAIR</a>(attr, s1aarch64) then</line>
<line>        (-, attr) = <a link="impl-shared.ConstrainUnpredictableBits.2" file="shared_pseudocode.xml" hover="function: (Constraint,bits(width)) ConstrainUnpredictableBits(Unpredictable which, integer width)">ConstrainUnpredictableBits</a>(<a link="Unpredictable_RESMAIR" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_RESMAIR</a>, 8);</line>
<line></line>
<line>    <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs;</line>
<line>    case attr of</line>
<line>        when '0000xxxx' // Device memory</line>
<line>            memattrs.memtype = <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a>;</line>
<line>            memattrs.device  = <a link="impl-shared.DecodeDevice.1" file="shared_pseudocode.xml" hover="function: DeviceType DecodeDevice(bits(2) device)">DecodeDevice</a>(attr&lt;3:2&gt;);</line>
<line>            memattrs.xs      = if s1aarch64 then NOT attr&lt;0&gt; else '1';</line>
<line>        when '01000000'</line>
<line>            assert s1aarch64 &amp;&amp; <a link="impl-shared.HaveFeatXS.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatXS()">HaveFeatXS</a>();</line>
<line>            memattrs.memtype = <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>;</line>
<line>            memattrs.outer.attrs = <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a>;</line>
<line>            memattrs.inner.attrs = <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a>;</line>
<line>            memattrs.xs          = '0';</line>
<line></line>
<line>        when '10100000'</line>
<line>            assert s1aarch64 &amp;&amp; <a link="impl-shared.HaveFeatXS.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatXS()">HaveFeatXS</a>();</line>
<line>            memattrs.memtype = <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>;</line>
<line>            memattrs.outer.attrs     = <a link="MemAttr_WT" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WT = '10'">MemAttr_WT</a>;</line>
<line>            memattrs.outer.hints     = <a link="MemHint_RA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RA = '10'">MemHint_RA</a>;</line>
<line>            memattrs.outer.transient = FALSE;</line>
<line>            memattrs.inner.attrs     = <a link="MemAttr_WT" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WT = '10'">MemAttr_WT</a>;</line>
<line>            memattrs.inner.hints     = <a link="MemHint_RA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RA = '10'">MemHint_RA</a>;</line>
<line>            memattrs.inner.transient = FALSE;</line>
<line>            memattrs.xs              = '0';</line>
<line>        when '11110000' // Tagged memory</line>
<line>            assert s1aarch64 &amp;&amp; <a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>();</line>
<line>            memattrs.memtype = <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>;</line>
<line>            memattrs.outer.attrs     = <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>;</line>
<line>            memattrs.outer.hints     = <a link="MemHint_RWA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RWA = '11'">MemHint_RWA</a>;</line>
<line>            memattrs.outer.transient = FALSE;</line>
<line>            memattrs.inner.attrs     = <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>;</line>
<line>            memattrs.inner.hints     = <a link="MemHint_RWA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RWA = '11'">MemHint_RWA</a>;</line>
<line>            memattrs.inner.transient = FALSE;</line>
<line>            memattrs.xs              = '0';</line>
<line>        otherwise</line>
<line>            memattrs.memtype = <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>;</line>
<line>            memattrs.outer   = <a link="impl-shared.DecodeLDFAttr.1" file="shared_pseudocode.xml" hover="function: MemAttrHints DecodeLDFAttr(bits(4) attr)">DecodeLDFAttr</a>(attr&lt;7:4&gt;);</line>
<line>            memattrs.inner   = <a link="impl-shared.DecodeLDFAttr.1" file="shared_pseudocode.xml" hover="function: MemAttrHints DecodeLDFAttr(bits(4) attr)">DecodeLDFAttr</a>(attr&lt;3:0&gt;);</line>
<line></line>
<line>            if (memattrs.inner.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a> &amp;&amp;</line>
<line>                    memattrs.outer.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>) then</line>
<line>                memattrs.xs = '0';</line>
<line>            else</line>
<line>                memattrs.xs = '1';</line>
<line></line>
<line>    if s1aarch64 &amp;&amp; attr IN {'11110000'} then</line>
<line>        memattrs.tags = <a link="MemTag_AllocationTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_AllocationTagged</a>;</line>
<line>    elsif s1aarch64 &amp;&amp; walkparams.mtx == '1' then</line>
<line>        memattrs.tags = <a link="MemTag_CanonicallyTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_CanonicallyTagged</a>;</line>
<line>    else</line>
<line>        memattrs.tags = <a link="MemTag_Untagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_Untagged</a>;</line>
<line></line>
<line>    memattrs.notagaccess = FALSE;</line>
<line></line>
<line>    memattrs.shareability = <a link="impl-shared.DecodeShareability.1" file="shared_pseudocode.xml" hover="function: Shareability DecodeShareability(bits(2) sh)">DecodeShareability</a>(sh);</line>
<line></line>
<line>    return memattrs;</line>
</pstext>
    </ps>
    <ps name="shared/translation/attrs/S2CombineS1AttrHints" mylink="shared.translation.attrs.S2CombineS1AttrHints" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// S2CombineS1AttrHints()</line>
<line>// ======================</line>
<line>// Determine resultant Normal memory cacheability and allocation hints from</line>
<line>// combining stage 1 Normal memory attributes and stage 2 cacheability attributes.</line>
<line></line>
<line link="impl-shared.S2CombineS1AttrHints.2" hover="function: MemAttrHints S2CombineS1AttrHints(MemAttrHints s1_attrhints, MemAttrHints s2_attrhints)" conts="S2CombineS1AttrHints">MemAttrHints <anchor link="impl-shared.S2CombineS1AttrHints.2" hover="function: MemAttrHints S2CombineS1AttrHints(MemAttrHints s1_attrhints, MemAttrHints s2_attrhints)">S2CombineS1AttrHints</anchor>(<a link="MemAttrHints" file="shared_pseudocode.xml" hover="type MemAttrHints is ( bits(2) attrs, bits(2) hints, boolean transient )">MemAttrHints</a> s1_attrhints, <a link="MemAttrHints" file="shared_pseudocode.xml" hover="type MemAttrHints is ( bits(2) attrs, bits(2) hints, boolean transient )">MemAttrHints</a> s2_attrhints)</line>
<line>    <a link="MemAttrHints" file="shared_pseudocode.xml" hover="type MemAttrHints is ( bits(2) attrs, bits(2) hints, boolean transient )">MemAttrHints</a> attrhints;</line>
<line></line>
<line>    if s1_attrhints.attrs == <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a> || s2_attrhints.attrs == <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a> then</line>
<line>        attrhints.attrs = <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a>;</line>
<line>    elsif s1_attrhints.attrs == <a link="MemAttr_WT" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WT = '10'">MemAttr_WT</a> || s2_attrhints.attrs == <a link="MemAttr_WT" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WT = '10'">MemAttr_WT</a> then</line>
<line>        attrhints.attrs = <a link="MemAttr_WT" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WT = '10'">MemAttr_WT</a>;</line>
<line>    else</line>
<line>        attrhints.attrs = <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>;</line>
<line></line>
<line>    // Stage 2 does not assign any allocation hints</line>
<line>    // Instead, they are inherited from stage 1</line>
<line>    if attrhints.attrs != <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a> then</line>
<line>        attrhints.hints     = s1_attrhints.hints;</line>
<line>        attrhints.transient = s1_attrhints.transient;</line>
<line></line>
<line>    return attrhints;</line>
</pstext>
    </ps>
    <ps name="shared/translation/attrs/S2CombineS1Device" mylink="shared.translation.attrs.S2CombineS1Device" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// S2CombineS1Device()</line>
<line>// ===================</line>
<line>// Determine resultant Device type from combining output memory attributes</line>
<line>// in stage 1 and Device attributes in stage 2</line>
<line></line>
<line link="impl-shared.S2CombineS1Device.2" hover="function: DeviceType S2CombineS1Device(DeviceType s1_device, DeviceType s2_device)" conts="S2CombineS1Device">DeviceType <anchor link="impl-shared.S2CombineS1Device.2" hover="function: DeviceType S2CombineS1Device(DeviceType s1_device, DeviceType s2_device)">S2CombineS1Device</anchor>(<a link="DeviceType" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType</a> s1_device, <a link="DeviceType" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType</a> s2_device)</line>
<line>    if s1_device == <a link="DeviceType_nGnRnE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGnRnE</a> || s2_device == <a link="DeviceType_nGnRnE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGnRnE</a> then</line>
<line>        return <a link="DeviceType_nGnRnE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGnRnE</a>;</line>
<line>    elsif s1_device == <a link="DeviceType_nGnRE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGnRE</a> || s2_device == <a link="DeviceType_nGnRE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGnRE</a> then</line>
<line>        return <a link="DeviceType_nGnRE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGnRE</a>;</line>
<line>    elsif s1_device == <a link="DeviceType_nGRE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGRE</a> || s2_device == <a link="DeviceType_nGRE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGRE</a> then</line>
<line>        return <a link="DeviceType_nGRE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_nGRE</a>;</line>
<line>    else</line>
<line>        return <a link="DeviceType_GRE" file="shared_pseudocode.xml" hover="enumeration DeviceType {DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE}">DeviceType_GRE</a>;</line>
</pstext>
    </ps>
    <ps name="shared/translation/attrs/S2CombineS1MemAttrs" mylink="shared.translation.attrs.S2CombineS1MemAttrs" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// S2CombineS1MemAttrs()</line>
<line>// =====================</line>
<line>// Combine stage 2 with stage 1 memory attributes</line>
<line></line>
<line link="impl-shared.S2CombineS1MemAttrs.3" hover="function: MemoryAttributes S2CombineS1MemAttrs(MemoryAttributes s1_memattrs, MemoryAttributes s2_memattrs, boolean s2aarch64)" conts="S2CombineS1MemAttrs">MemoryAttributes <anchor link="impl-shared.S2CombineS1MemAttrs.3" hover="function: MemoryAttributes S2CombineS1MemAttrs(MemoryAttributes s1_memattrs, MemoryAttributes s2_memattrs, boolean s2aarch64)">S2CombineS1MemAttrs</anchor>(<a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> s1_memattrs, <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> s2_memattrs,</line>
<line>                                     boolean s2aarch64)</line>
<line>    <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs;</line>
<line></line>
<line>    if s1_memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> &amp;&amp; s2_memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> then</line>
<line>        memattrs.memtype = <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a>;</line>
<line>        memattrs.device  = <a link="impl-shared.S2CombineS1Device.2" file="shared_pseudocode.xml" hover="function: DeviceType S2CombineS1Device(DeviceType s1_device, DeviceType s2_device)">S2CombineS1Device</a>(s1_memattrs.device, s2_memattrs.device);</line>
<line>    elsif s1_memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> then    // S2 Normal, S1 Device</line>
<line>        memattrs = s1_memattrs;</line>
<line>    elsif s2_memattrs.memtype == <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a> then    // S2 Device, S1 Normal</line>
<line>        memattrs = s2_memattrs;</line>
<line>    else                                                // S2 Normal, S1 Normal</line>
<line>        memattrs.memtype = <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>;</line>
<line>        memattrs.inner   = <a link="impl-shared.S2CombineS1AttrHints.2" file="shared_pseudocode.xml" hover="function: MemAttrHints S2CombineS1AttrHints(MemAttrHints s1_attrhints, MemAttrHints s2_attrhints)">S2CombineS1AttrHints</a>(s1_memattrs.inner, s2_memattrs.inner);</line>
<line>        memattrs.outer   = <a link="impl-shared.S2CombineS1AttrHints.2" file="shared_pseudocode.xml" hover="function: MemAttrHints S2CombineS1AttrHints(MemAttrHints s1_attrhints, MemAttrHints s2_attrhints)">S2CombineS1AttrHints</a>(s1_memattrs.outer, s2_memattrs.outer);</line>
<line></line>
<line>    memattrs.tags = <a link="impl-shared.S2MemTagType.2" file="shared_pseudocode.xml" hover="function: MemTagType S2MemTagType(MemoryAttributes s2_memattrs, MemTagType s1_tagtype)">S2MemTagType</a>(memattrs, s1_memattrs.tags);</line>
<line></line>
<line>    if !<a link="impl-shared.HaveMTEPermExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEPermExt()">HaveMTEPermExt</a>() then</line>
<line>        memattrs.notagaccess = FALSE;</line>
<line>    else</line>
<line>        memattrs.notagaccess = (s2_memattrs.notagaccess &amp;&amp;</line>
<line>                               s1_memattrs.tags == <a link="MemTag_AllocationTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_AllocationTagged</a>);</line>
<line>    memattrs.shareability = <a link="impl-shared.S2CombineS1Shareability.2" file="shared_pseudocode.xml" hover="function: Shareability S2CombineS1Shareability(Shareability s1_shareability, Shareability s2_shareability)">S2CombineS1Shareability</a>(s1_memattrs.shareability,</line>
<line>                                                    s2_memattrs.shareability);</line>
<line></line>
<line>    if (memattrs.memtype == <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a> &amp;&amp;</line>
<line>            memattrs.inner.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a> &amp;&amp;</line>
<line>            memattrs.outer.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>) then</line>
<line>        memattrs.xs = '0';</line>
<line>    elsif s2aarch64 then</line>
<line>        memattrs.xs = s2_memattrs.xs AND s1_memattrs.xs;</line>
<line>    else</line>
<line>        memattrs.xs = s1_memattrs.xs;</line>
<line></line>
<line>    memattrs.shareability = <a link="impl-shared.EffectiveShareability.1" file="shared_pseudocode.xml" hover="function: Shareability EffectiveShareability(MemoryAttributes memattrs)">EffectiveShareability</a>(memattrs);</line>
<line>    return memattrs;</line>
</pstext>
    </ps>
    <ps name="shared/translation/attrs/S2CombineS1Shareability" mylink="shared.translation.attrs.S2CombineS1Shareability" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// S2CombineS1Shareability()</line>
<line>// =========================</line>
<line>// Combine stage 2 shareability with stage 1</line>
<line></line>
<line link="impl-shared.S2CombineS1Shareability.2" hover="function: Shareability S2CombineS1Shareability(Shareability s1_shareability, Shareability s2_shareability)" conts="S2CombineS1Shareability">Shareability <anchor link="impl-shared.S2CombineS1Shareability.2" hover="function: Shareability S2CombineS1Shareability(Shareability s1_shareability, Shareability s2_shareability)">S2CombineS1Shareability</anchor>(<a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> s1_shareability,</line>
<line>                                     <a link="Shareability" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability</a> s2_shareability)</line>
<line></line>
<line>    if (s1_shareability == <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a> ||</line>
<line>            s2_shareability == <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a>) then</line>
<line>        return <a link="Shareability_OSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_OSH</a>;</line>
<line>    elsif (s1_shareability == <a link="Shareability_ISH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_ISH</a> ||</line>
<line>            s2_shareability == <a link="Shareability_ISH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_ISH</a>) then</line>
<line>        return <a link="Shareability_ISH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_ISH</a>;</line>
<line>    else</line>
<line>        return <a link="Shareability_NSH" file="shared_pseudocode.xml" hover="enumeration Shareability { Shareability_NSH, Shareability_ISH, Shareability_OSH }">Shareability_NSH</a>;</line>
</pstext>
    </ps>
    <ps name="shared/translation/attrs/S2DecodeCacheability" mylink="shared.translation.attrs.S2DecodeCacheability" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// S2DecodeCacheability()</line>
<line>// ======================</line>
<line>// Determine the stage 2 cacheability for Normal memory</line>
<line></line>
<line link="impl-shared.S2DecodeCacheability.1" hover="function: MemAttrHints S2DecodeCacheability(bits(2) attr)" conts="S2DecodeCacheability">MemAttrHints <anchor link="impl-shared.S2DecodeCacheability.1" hover="function: MemAttrHints S2DecodeCacheability(bits(2) attr)">S2DecodeCacheability</anchor>(bits(2) attr)</line>
<line>    <a link="MemAttrHints" file="shared_pseudocode.xml" hover="type MemAttrHints is ( bits(2) attrs, bits(2) hints, boolean transient )">MemAttrHints</a> s2attr;</line>
<line></line>
<line>    case attr of</line>
<line>        when '01' s2attr.attrs = <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a>;  // Non-cacheable</line>
<line>        when '10' s2attr.attrs = <a link="MemAttr_WT" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WT = '10'">MemAttr_WT</a>;  // Write-through</line>
<line>        when '11' s2attr.attrs = <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>;  // Write-back</line>
<line>        otherwise // Constrained unpredictable</line>
<line>            case <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_S2RESMEMATTR" file="shared_pseudocode.xml" hover="enumeration Unpredictable {  Unpredictable_VMSR,  Unpredictable_WBOVERLAPLD,  Unpredictable_WBOVERLAPST,  Unpredictable_LDPOVERLAP,  Unpredictable_BASEOVERLAP,  Unpredictable_DATAOVERLAP,  Unpredictable_DEVPAGE2,  Unpredictable_INSTRDEVICE,  Unpredictable_RESCPACR,  Unpredictable_RESMAIR,  Unpredictable_S1CTAGGED,  Unpredictable_S2RESMEMATTR,  Unpredictable_RESTEXCB,  Unpredictable_RESPRRR,  Unpredictable_RESDACR,  Unpredictable_RESVTCRS,  Unpredictable_RESTnSZ,  Unpredictable_RESTCF,  Unpredictable_DEVICETAGSTORE,  Unpredictable_OORTnSZ,  Unpredictable_LARGEIPA,  Unpredictable_ESRCONDPASS,  Unpredictable_ILZEROIT,  Unpredictable_ILZEROT,  Unpredictable_BPVECTORCATCHPRI,  Unpredictable_VCMATCHHALF,   Unpredictable_VCMATCHDAPA,  Unpredictable_WPMASKANDBAS,  Unpredictable_WPBASCONTIGUOUS,  Unpredictable_RESWPMASK,  Unpredictable_WPMASKEDBITS,  Unpredictable_RESBPWPCTRL,  Unpredictable_BPNOTIMPL,  Unpredictable_RESBPTYPE,  Unpredictable_BPNOTCTXCMP,  Unpredictable_BPMATCHHALF,  Unpredictable_BPMISMATCHHALF,  Unpredictable_RESTARTALIGNPC,  Unpredictable_RESTARTZEROUPPERPC,  Unpredictable_ZEROUPPER,   Unpredictable_ERETZEROUPPERPC,   Unpredictable_A32FORCEALIGNPC,  Unpredictable_SMD,  Unpredictable_NONFAULT,  Unpredictable_SVEZEROUPPER,  Unpredictable_SVELDNFDATA,  Unpredictable_SVELDNFZERO,  Unpredictable_CHECKSPNONEACTIVE,  Unpredictable_SMEZEROUPPER,  Unpredictable_NVNV1,  Unpredictable_Shareability,  Unpredictable_AFUPDATE,  Unpredictable_DBUPDATE,  Unpredictable_IESBinDebug,  Unpredictable_BADPMSFCR,  Unpredictable_ZEROBTYPE,  Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP,  Unpredictable_RESERVEDNSxB,  Unpredictable_WFxTDEBUG,  Unpredictable_LS64UNSUPPORTED,   Unpredictable_MISALIGNEDATOMIC,  Unpredictable_CLEARERRITEZERO,   Unpredictable_ALUEXCEPTIONRETURN,  Unpredictable_IGNORETRAPINDEBUG,  Unpredictable_DBGxVR_RESS,  Unpredictable_PMUEVENTCOUNTER,  Unpredictable_PMSCR_PCT,   Unpredictable_CounterReservedForEL2,  Unpredictable_BRBFILTRATE,   Unpredictable_MOPSOVERLAP31,  Unpredictable_STOREONLYTAGCHECKEDCAS,  Unpredictable_RESTC }">Unpredictable_S2RESMEMATTR</a>) of</line>
<line>                when <a link="Constraint_NC" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_NC</a> s2attr.attrs = <a link="MemAttr_NC" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_NC = '00'">MemAttr_NC</a>;</line>
<line>                when <a link="Constraint_WT" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_WT</a> s2attr.attrs = <a link="MemAttr_WT" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WT = '10'">MemAttr_WT</a>;</line>
<line>                when <a link="Constraint_WB" file="shared_pseudocode.xml" hover="enumeration Constraint    { Constraint_NONE,   Constraint_UNKNOWN,  Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE,   Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY,   Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH,  Constraint_NC, Constraint_WT, Constraint_WB,   Constraint_FORCE, Constraint_FORCENOSLCHECK,  Constraint_MAPTOALLOCATED,  Constraint_PMSCR_PCT_VIRT }">Constraint_WB</a> s2attr.attrs = <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>;</line>
<line></line>
<line>    // Stage 2 does not assign hints or the transient property</line>
<line>    // They are inherited from stage 1 if the result of the combination allows it</line>
<line>    s2attr.hints     = bits(2) UNKNOWN;</line>
<line>    s2attr.transient = boolean UNKNOWN;</line>
<line></line>
<line>    return s2attr;</line>
</pstext>
    </ps>
    <ps name="shared/translation/attrs/S2DecodeMemAttrs" mylink="shared.translation.attrs.S2DecodeMemAttrs" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// S2DecodeMemAttrs()</line>
<line>// ==================</line>
<line>// Decode stage 2 memory attributes</line>
<line></line>
<line link="impl-shared.S2DecodeMemAttrs.3" hover="function: MemoryAttributes S2DecodeMemAttrs(bits(4) attr, bits(2) sh, boolean s2aarch64)" conts="S2DecodeMemAttrs">MemoryAttributes <anchor link="impl-shared.S2DecodeMemAttrs.3" hover="function: MemoryAttributes S2DecodeMemAttrs(bits(4) attr, bits(2) sh, boolean s2aarch64)">S2DecodeMemAttrs</anchor>(bits(4) attr, bits(2) sh, boolean s2aarch64)</line>
<line>    <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs;</line>
<line></line>
<line>    case attr of</line>
<line>        when '00xx' // Device memory</line>
<line>            memattrs.memtype      = <a link="MemType_Device" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Device</a>;</line>
<line>            memattrs.device       = <a link="impl-shared.DecodeDevice.1" file="shared_pseudocode.xml" hover="function: DeviceType DecodeDevice(bits(2) device)">DecodeDevice</a>(attr&lt;1:0&gt;);</line>
<line>        when '0100' // Normal, Inner+Outer WB cacheable NoTagAccess memory</line>
<line>            if s2aarch64 &amp;&amp; <a link="impl-shared.HaveMTEPermExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEPermExt()">HaveMTEPermExt</a>() then</line>
<line>                memattrs.memtype      = <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>;</line>
<line>                memattrs.outer        = <a link="impl-shared.S2DecodeCacheability.1" file="shared_pseudocode.xml" hover="function: MemAttrHints S2DecodeCacheability(bits(2) attr)">S2DecodeCacheability</a>('11'); // Write-back</line>
<line>                memattrs.inner        = <a link="impl-shared.S2DecodeCacheability.1" file="shared_pseudocode.xml" hover="function: MemAttrHints S2DecodeCacheability(bits(2) attr)">S2DecodeCacheability</a>('11'); // Write-back</line>
<line>            else</line>
<line>                memattrs.memtype      = <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>;</line>
<line>                memattrs.outer        = <a link="impl-shared.S2DecodeCacheability.1" file="shared_pseudocode.xml" hover="function: MemAttrHints S2DecodeCacheability(bits(2) attr)">S2DecodeCacheability</a>(attr&lt;3:2&gt;);</line>
<line>                memattrs.inner        = <a link="impl-shared.S2DecodeCacheability.1" file="shared_pseudocode.xml" hover="function: MemAttrHints S2DecodeCacheability(bits(2) attr)">S2DecodeCacheability</a>(attr&lt;1:0&gt;);</line>
<line>        otherwise   // Normal memory</line>
<line>            memattrs.memtype      = <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>;</line>
<line>            memattrs.outer        = <a link="impl-shared.S2DecodeCacheability.1" file="shared_pseudocode.xml" hover="function: MemAttrHints S2DecodeCacheability(bits(2) attr)">S2DecodeCacheability</a>(attr&lt;3:2&gt;);</line>
<line>            memattrs.inner        = <a link="impl-shared.S2DecodeCacheability.1" file="shared_pseudocode.xml" hover="function: MemAttrHints S2DecodeCacheability(bits(2) attr)">S2DecodeCacheability</a>(attr&lt;1:0&gt;);</line>
<line></line>
<line>    memattrs.shareability = <a link="impl-shared.DecodeShareability.1" file="shared_pseudocode.xml" hover="function: Shareability DecodeShareability(bits(2) sh)">DecodeShareability</a>(sh);</line>
<line></line>
<line>    if s2aarch64 &amp;&amp; <a link="impl-shared.HaveMTEPermExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEPermExt()">HaveMTEPermExt</a>() then</line>
<line>        memattrs.notagaccess = attr == '0100';</line>
<line>    else</line>
<line>        memattrs.notagaccess = FALSE;</line>
<line></line>
<line>    return memattrs;</line>
</pstext>
    </ps>
    <ps name="shared/translation/attrs/S2MemTagType" mylink="shared.translation.attrs.S2MemTagType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// S2MemTagType()</line>
<line>// ==============</line>
<line>// Determine whether the combined output memory attributes of stage 1 and</line>
<line>// stage 2 indicate tagged memory</line>
<line></line>
<line link="impl-shared.S2MemTagType.2" hover="function: MemTagType S2MemTagType(MemoryAttributes s2_memattrs, MemTagType s1_tagtype)" conts="S2MemTagType">MemTagType <anchor link="impl-shared.S2MemTagType.2" hover="function: MemTagType S2MemTagType(MemoryAttributes s2_memattrs, MemTagType s1_tagtype)">S2MemTagType</anchor>(<a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> s2_memattrs, <a link="MemTagType" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTagType</a> s1_tagtype)</line>
<line></line>
<line>    if !<a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() then</line>
<line>        return <a link="MemTag_Untagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_Untagged</a>;</line>
<line></line>
<line>    if ((s1_tagtype == <a link="MemTag_AllocationTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_AllocationTagged</a>)  &amp;&amp;</line>
<line>        (s2_memattrs.memtype == <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>)  &amp;&amp;</line>
<line>        (s2_memattrs.inner.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>)  &amp;&amp;</line>
<line>        (s2_memattrs.inner.hints == <a link="MemHint_RWA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RWA = '11'">MemHint_RWA</a>) &amp;&amp;</line>
<line>        (!s2_memattrs.inner.transient)           &amp;&amp;</line>
<line>        (s2_memattrs.outer.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>)  &amp;&amp;</line>
<line>        (s2_memattrs.outer.hints == <a link="MemHint_RWA" file="shared_pseudocode.xml" hover="constant bits(2) MemHint_RWA = '11'">MemHint_RWA</a>) &amp;&amp;</line>
<line>        (!s2_memattrs.outer.transient)) then</line>
<line>        return <a link="MemTag_AllocationTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_AllocationTagged</a>;</line>
<line></line>
<line>    // Return what stage 1 asked for if we can, otherwise Untagged.</line>
<line>    if s1_tagtype != <a link="MemTag_AllocationTagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_AllocationTagged</a> then</line>
<line>        return s1_tagtype;</line>
<line></line>
<line>    return <a link="MemTag_Untagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_Untagged</a>;</line>
</pstext>
    </ps>
    <ps name="shared/translation/attrs/WalkMemAttrs" mylink="shared.translation.attrs.WalkMemAttrs" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// WalkMemAttrs()</line>
<line>// ==============</line>
<line>// Retrieve memory attributes of translation table walk</line>
<line></line>
<line link="impl-shared.WalkMemAttrs.3" hover="function: MemoryAttributes WalkMemAttrs(bits(2) sh, bits(2) irgn, bits(2) orgn)" conts="WalkMemAttrs">MemoryAttributes <anchor link="impl-shared.WalkMemAttrs.3" hover="function: MemoryAttributes WalkMemAttrs(bits(2) sh, bits(2) irgn, bits(2) orgn)">WalkMemAttrs</anchor>(bits(2) sh, bits(2) irgn, bits(2) orgn)</line>
<line>    <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> walkmemattrs;</line>
<line></line>
<line>    walkmemattrs.memtype      = <a link="MemType_Normal" file="shared_pseudocode.xml" hover="enumeration MemType {MemType_Normal, MemType_Device}">MemType_Normal</a>;</line>
<line>    walkmemattrs.shareability = <a link="impl-shared.DecodeShareability.1" file="shared_pseudocode.xml" hover="function: Shareability DecodeShareability(bits(2) sh)">DecodeShareability</a>(sh);</line>
<line>    walkmemattrs.inner        = <a link="impl-shared.DecodeSDFAttr.1" file="shared_pseudocode.xml" hover="function: MemAttrHints DecodeSDFAttr(bits(2) rgn)">DecodeSDFAttr</a>(irgn);</line>
<line>    walkmemattrs.outer        = <a link="impl-shared.DecodeSDFAttr.1" file="shared_pseudocode.xml" hover="function: MemAttrHints DecodeSDFAttr(bits(2) rgn)">DecodeSDFAttr</a>(orgn);</line>
<line>    walkmemattrs.tags         = <a link="MemTag_Untagged" file="shared_pseudocode.xml" hover="enumeration MemTagType { MemTag_Untagged, MemTag_AllocationTagged, MemTag_CanonicallyTagged }">MemTag_Untagged</a>;</line>
<line>    if (walkmemattrs.inner.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a> &amp;&amp;</line>
<line>            walkmemattrs.outer.attrs == <a link="MemAttr_WB" file="shared_pseudocode.xml" hover="constant bits(2) MemAttr_WB = '11'">MemAttr_WB</a>) then</line>
<line>        walkmemattrs.xs = '0';</line>
<line>    else</line>
<line>        walkmemattrs.xs = '1';</line>
<line>    walkmemattrs.notagaccess = FALSE;</line>
<line></line>
<line>    return walkmemattrs;</line>
</pstext>
    </ps>
    <ps name="shared/translation/faults/AlignmentFault" mylink="shared.translation.faults.AlignmentFault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AlignmentFault()</line>
<line>// ================</line>
<line>// Return a fault record indicating an Alignment fault not due to memory type has occured</line>
<line>// for a specific access</line>
<line></line>
<line link="impl-shared.AlignmentFault.1" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)" conts="AlignmentFault">FaultRecord <anchor link="impl-shared.AlignmentFault.1" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</anchor>(<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault;</line>
<line></line>
<line>    fault.statuscode  = <a link="Fault_Alignment" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Alignment</a>;</line>
<line>    fault.access      = accdesc;</line>
<line>    fault.secondstage = FALSE;</line>
<line>    fault.s2fs1walk   = FALSE;</line>
<line>    fault.write       = !accdesc.read &amp;&amp; accdesc.write;</line>
<line>    fault.gpcfs2walk  = FALSE;</line>
<line>    fault.gpcf        = <a link="impl-shared.GPCNoFault.0" file="shared_pseudocode.xml" hover="function: GPCFRecord GPCNoFault()">GPCNoFault</a>();</line>
<line></line>
<line>    return fault;</line>
</pstext>
    </ps>
    <ps name="shared/translation/faults/ExclusiveFault" mylink="shared.translation.faults.ExclusiveFault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ExclusiveFault()</line>
<line>// ================</line>
<line>// Return a fault record indicating an Exclusive fault for a specific access</line>
<line></line>
<line link="impl-shared.ExclusiveFault.1" hover="function: FaultRecord ExclusiveFault(AccessDescriptor accdesc)" conts="ExclusiveFault">FaultRecord <anchor link="impl-shared.ExclusiveFault.1" hover="function: FaultRecord ExclusiveFault(AccessDescriptor accdesc)">ExclusiveFault</anchor>(<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault;</line>
<line></line>
<line>    fault.statuscode  = <a link="Fault_Exclusive" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_Exclusive</a>;</line>
<line>    fault.access      = accdesc;</line>
<line>    fault.secondstage = FALSE;</line>
<line>    fault.s2fs1walk   = FALSE;</line>
<line>    fault.write       = !accdesc.read &amp;&amp; accdesc.write;</line>
<line>    fault.gpcfs2walk  = FALSE;</line>
<line>    fault.gpcf        = <a link="impl-shared.GPCNoFault.0" file="shared_pseudocode.xml" hover="function: GPCFRecord GPCNoFault()">GPCNoFault</a>();</line>
<line></line>
<line>    return fault;</line>
</pstext>
    </ps>
    <ps name="shared/translation/faults/NoFault" mylink="shared.translation.faults.NoFault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// NoFault()</line>
<line>// =========</line>
<line>// Return a clear fault record indicating no faults have occured</line>
<line></line>
<line link="impl-shared.NoFault.0" hover="function: FaultRecord NoFault()" conts="NoFault">FaultRecord <anchor link="impl-shared.NoFault.0" hover="function: FaultRecord NoFault()">NoFault</anchor>()</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault;</line>
<line></line>
<line>    fault.statuscode  = <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a>;</line>
<line>    fault.access      = <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> UNKNOWN;</line>
<line>    fault.secondstage = FALSE;</line>
<line>    fault.s2fs1walk   = FALSE;</line>
<line>    fault.dirtybit    = FALSE;</line>
<line>    fault.overlay     = FALSE;</line>
<line>    fault.toplevel    = FALSE;</line>
<line>    fault.assuredonly = FALSE;</line>
<line>    fault.s1tagnotdata = FALSE;</line>
<line>    fault.tagaccess   = FALSE;</line>
<line>    fault.gpcfs2walk  = FALSE;</line>
<line>    fault.gpcf        = <a link="impl-shared.GPCNoFault.0" file="shared_pseudocode.xml" hover="function: GPCFRecord GPCNoFault()">GPCNoFault</a>();</line>
<line></line>
<line>    return fault;</line>
<line></line>
<line>// NoFault()</line>
<line>// =========</line>
<line>// Return a clear fault record indicating no faults have occured for a specific access</line>
<line></line>
<line link="impl-shared.NoFault.1" hover="function: FaultRecord NoFault(AccessDescriptor accdesc)" conts="NoFault">FaultRecord <anchor link="impl-shared.NoFault.1" hover="function: FaultRecord NoFault(AccessDescriptor accdesc)">NoFault</anchor>(<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault;</line>
<line></line>
<line>    fault.statuscode  = <a link="Fault_None" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_None</a>;</line>
<line>    fault.access      = accdesc;</line>
<line>    fault.secondstage = FALSE;</line>
<line>    fault.s2fs1walk   = FALSE;</line>
<line>    fault.dirtybit    = FALSE;</line>
<line>    fault.overlay     = FALSE;</line>
<line>    fault.toplevel    = FALSE;</line>
<line>    fault.assuredonly = FALSE;</line>
<line>    fault.s1tagnotdata = FALSE;</line>
<line>    fault.tagaccess   = FALSE;</line>
<line>    fault.write       = !accdesc.read &amp;&amp; accdesc.write;</line>
<line>    fault.gpcfs2walk  = FALSE;</line>
<line>    fault.gpcf        = <a link="impl-shared.GPCNoFault.0" file="shared_pseudocode.xml" hover="function: GPCFRecord GPCNoFault()">GPCNoFault</a>();</line>
<line></line>
<line>    return fault;</line>
</pstext>
    </ps>
    <ps name="shared/translation/gpc/AbovePPS" mylink="shared.translation.gpc.AbovePPS" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// AbovePPS()</line>
<line>// ==========</line>
<line>// Returns TRUE if an address exceeds the range configured in GPCCR_EL3.PPS.</line>
<line></line>
<line link="impl-shared.AbovePPS.1" hover="function: boolean AbovePPS(bits(56) address)" conts="AbovePPS">boolean <anchor link="impl-shared.AbovePPS.1" hover="function: boolean AbovePPS(bits(56) address)">AbovePPS</anchor>(bits(56) address)</line>
<line>    pps = <a link="impl-shared.DecodePPS.0" file="shared_pseudocode.xml" hover="function: integer DecodePPS()">DecodePPS</a>();</line>
<line>    if pps &gt;= 56 then</line>
<line>        return FALSE;</line>
<line></line>
<line>    return !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(address&lt;55:pps&gt;);</line>
</pstext>
    </ps>
    <ps name="shared/translation/gpc/DecodeGPTBlock" mylink="shared.translation.gpc.DecodeGPTBlock" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DecodeGPTBlock()</line>
<line>// ================</line>
<line>// Validate and decode a GPT Block descriptor</line>
<line></line>
<line link="impl-shared.DecodeGPTBlock.2" hover="function: (GPCF, GPTEntry) DecodeGPTBlock(PGSe pgs, bits(64) entry)" conts="DecodeGPTBlock">(GPCF, GPTEntry) <anchor link="impl-shared.DecodeGPTBlock.2" hover="function: (GPCF, GPTEntry) DecodeGPTBlock(PGSe pgs, bits(64) entry)">DecodeGPTBlock</anchor>(<a link="PGSe" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGSe</a> pgs, bits(64) entry)</line>
<line>    assert entry&lt;3:0&gt; == <a link="GPT_Block" file="shared_pseudocode.xml" hover="constant bits(4) GPT_Block = '0001'">GPT_Block</a>;</line>
<line>    <a link="GPTEntry" file="shared_pseudocode.xml" hover="type GPTEntry is ( bits(4) gpi, integer size, integer contig_size, integer level, bits(56) pa )">GPTEntry</a> result;</line>
<line></line>
<line>    if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(entry&lt;63:8&gt;) then</line>
<line>        return (<a link="GPCF_Walk" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_Walk</a>, <a link="GPTEntry" file="shared_pseudocode.xml" hover="type GPTEntry is ( bits(4) gpi, integer size, integer contig_size, integer level, bits(56) pa )">GPTEntry</a> UNKNOWN);</line>
<line></line>
<line>    if !<a link="impl-shared.GPIValid.1" file="shared_pseudocode.xml" hover="function: boolean GPIValid(bits(4) gpi)">GPIValid</a>(entry&lt;7:4&gt;) then</line>
<line>        return (<a link="GPCF_Walk" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_Walk</a>, <a link="GPTEntry" file="shared_pseudocode.xml" hover="type GPTEntry is ( bits(4) gpi, integer size, integer contig_size, integer level, bits(56) pa )">GPTEntry</a> UNKNOWN);</line>
<line></line>
<line>    result.gpi   = entry&lt;7:4&gt;;</line>
<line>    result.level = 0;</line>
<line></line>
<line>    // GPT information from a level 0 GPT Block descriptor is permitted</line>
<line>    // to be cached in a TLB as though the Block is a contiguous region</line>
<line>    // of granules each of the size configured in GPCCR_EL3.PGS.</line>
<line>    case pgs of</line>
<line>        when <a link="PGS_4KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_4KB</a>  result.size = <a link="GPTRange_4KB" file="shared_pseudocode.xml" hover="constant integer GPTRange_4KB = 12">GPTRange_4KB</a>;</line>
<line>        when <a link="PGS_16KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_16KB</a> result.size = <a link="GPTRange_16KB" file="shared_pseudocode.xml" hover="constant integer GPTRange_16KB = 14">GPTRange_16KB</a>;</line>
<line>        when <a link="PGS_64KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_64KB</a> result.size = <a link="GPTRange_64KB" file="shared_pseudocode.xml" hover="constant integer GPTRange_64KB = 16">GPTRange_64KB</a>;</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>    result.contig_size = <a link="impl-shared.GPTL0Size.0" file="shared_pseudocode.xml" hover="function: integer GPTL0Size()">GPTL0Size</a>();</line>
<line></line>
<line>    return (<a link="GPCF_None" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_None</a>, result);</line>
</pstext>
    </ps>
    <ps name="shared/translation/gpc/DecodeGPTContiguous" mylink="shared.translation.gpc.DecodeGPTContiguous" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DecodeGPTContiguous()</line>
<line>// =====================</line>
<line>// Validate and decode a GPT Contiguous descriptor</line>
<line></line>
<line link="impl-shared.DecodeGPTContiguous.2" hover="function: (GPCF, GPTEntry) DecodeGPTContiguous(PGSe pgs, bits(64) entry)" conts="DecodeGPTContiguous">(GPCF, GPTEntry) <anchor link="impl-shared.DecodeGPTContiguous.2" hover="function: (GPCF, GPTEntry) DecodeGPTContiguous(PGSe pgs, bits(64) entry)">DecodeGPTContiguous</anchor>(<a link="PGSe" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGSe</a> pgs, bits(64) entry)</line>
<line>    assert entry&lt;3:0&gt; == <a link="GPT_Contig" file="shared_pseudocode.xml" hover="constant bits(4) GPT_Contig = '0001'">GPT_Contig</a>;</line>
<line>    <a link="GPTEntry" file="shared_pseudocode.xml" hover="type GPTEntry is ( bits(4) gpi, integer size, integer contig_size, integer level, bits(56) pa )">GPTEntry</a> result;</line>
<line></line>
<line>    if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(entry&lt;63:10&gt;) then</line>
<line>        return (<a link="GPCF_Walk" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_Walk</a>, result);</line>
<line></line>
<line>    result.gpi = entry&lt;7:4&gt;;</line>
<line>    if !<a link="impl-shared.GPIValid.1" file="shared_pseudocode.xml" hover="function: boolean GPIValid(bits(4) gpi)">GPIValid</a>(result.gpi) then</line>
<line>        return (<a link="GPCF_Walk" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_Walk</a>, result);</line>
<line></line>
<line>    case pgs of</line>
<line>        when <a link="PGS_4KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_4KB</a>  result.size = <a link="GPTRange_4KB" file="shared_pseudocode.xml" hover="constant integer GPTRange_4KB = 12">GPTRange_4KB</a>;</line>
<line>        when <a link="PGS_16KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_16KB</a> result.size = <a link="GPTRange_16KB" file="shared_pseudocode.xml" hover="constant integer GPTRange_16KB = 14">GPTRange_16KB</a>;</line>
<line>        when <a link="PGS_64KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_64KB</a> result.size = <a link="GPTRange_64KB" file="shared_pseudocode.xml" hover="constant integer GPTRange_64KB = 16">GPTRange_64KB</a>;</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    case entry&lt;9:8&gt; of</line>
<line>        when '01' result.contig_size = <a link="GPTRange_2MB" file="shared_pseudocode.xml" hover="constant integer GPTRange_2MB = 21">GPTRange_2MB</a>;</line>
<line>        when '10' result.contig_size = <a link="GPTRange_32MB" file="shared_pseudocode.xml" hover="constant integer GPTRange_32MB = 25">GPTRange_32MB</a>;</line>
<line>        when '11' result.contig_size = <a link="GPTRange_512MB" file="shared_pseudocode.xml" hover="constant integer GPTRange_512MB = 29">GPTRange_512MB</a>;</line>
<line>        otherwise return (<a link="GPCF_Walk" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_Walk</a>, <a link="GPTEntry" file="shared_pseudocode.xml" hover="type GPTEntry is ( bits(4) gpi, integer size, integer contig_size, integer level, bits(56) pa )">GPTEntry</a> UNKNOWN);</line>
<line></line>
<line>    result.level = 1;</line>
<line></line>
<line>    return (<a link="GPCF_None" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_None</a>, result);</line>
</pstext>
    </ps>
    <ps name="shared/translation/gpc/DecodeGPTGranules" mylink="shared.translation.gpc.DecodeGPTGranules" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DecodeGPTGranules()</line>
<line>// ===================</line>
<line>// Validate and decode a GPT Granules descriptor</line>
<line></line>
<line link="impl-shared.DecodeGPTGranules.3" hover="function: (GPCF, GPTEntry) DecodeGPTGranules(PGSe pgs, integer index, bits(64) entry)" conts="DecodeGPTGranules">(GPCF, GPTEntry) <anchor link="impl-shared.DecodeGPTGranules.3" hover="function: (GPCF, GPTEntry) DecodeGPTGranules(PGSe pgs, integer index, bits(64) entry)">DecodeGPTGranules</anchor>(<a link="PGSe" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGSe</a> pgs, integer index, bits(64) entry)</line>
<line>    <a link="GPTEntry" file="shared_pseudocode.xml" hover="type GPTEntry is ( bits(4) gpi, integer size, integer contig_size, integer level, bits(56) pa )">GPTEntry</a> result;</line>
<line></line>
<line>    for i = 0 to 15</line>
<line>        if !<a link="impl-shared.GPIValid.1" file="shared_pseudocode.xml" hover="function: boolean GPIValid(bits(4) gpi)">GPIValid</a>(entry&lt;i*4 +:4&gt;) then</line>
<line>            return (<a link="GPCF_Walk" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_Walk</a>, result);</line>
<line></line>
<line>    result.gpi = entry&lt;index*4 +:4&gt;;</line>
<line></line>
<line>    case pgs of</line>
<line>        when <a link="PGS_4KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_4KB</a>  result.size = <a link="GPTRange_4KB" file="shared_pseudocode.xml" hover="constant integer GPTRange_4KB = 12">GPTRange_4KB</a>;</line>
<line>        when <a link="PGS_16KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_16KB</a> result.size = <a link="GPTRange_16KB" file="shared_pseudocode.xml" hover="constant integer GPTRange_16KB = 14">GPTRange_16KB</a>;</line>
<line>        when <a link="PGS_64KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_64KB</a> result.size = <a link="GPTRange_64KB" file="shared_pseudocode.xml" hover="constant integer GPTRange_64KB = 16">GPTRange_64KB</a>;</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    result.contig_size = result.size; // No contiguity</line>
<line>    result.level = 1;</line>
<line></line>
<line>    return (<a link="GPCF_None" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_None</a>, result);</line>
</pstext>
    </ps>
    <ps name="shared/translation/gpc/DecodeGPTTable" mylink="shared.translation.gpc.DecodeGPTTable" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DecodeGPTTable()</line>
<line>// ================</line>
<line>// Validate and decode a GPT Table descriptor</line>
<line></line>
<line link="impl-shared.DecodeGPTTable.2" hover="function: (GPCF, GPTTable) DecodeGPTTable(PGSe pgs, bits(64) entry)" conts="DecodeGPTTable">(GPCF, GPTTable) <anchor link="impl-shared.DecodeGPTTable.2" hover="function: (GPCF, GPTTable) DecodeGPTTable(PGSe pgs, bits(64) entry)">DecodeGPTTable</anchor>(<a link="PGSe" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGSe</a> pgs, bits(64) entry)</line>
<line>    assert entry&lt;3:0&gt; == <a link="GPT_Table" file="shared_pseudocode.xml" hover="constant bits(4) GPT_Table = '0011'">GPT_Table</a>;</line>
<line>    <a link="GPTTable" file="shared_pseudocode.xml" hover="type GPTTable is ( bits(56) address )">GPTTable</a> result;</line>
<line></line>
<line>    if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(entry&lt;63:52,11:4&gt;) then</line>
<line>        return (<a link="GPCF_Walk" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_Walk</a>, <a link="GPTTable" file="shared_pseudocode.xml" hover="type GPTTable is ( bits(56) address )">GPTTable</a> UNKNOWN);</line>
<line></line>
<line>    l0sz = <a link="impl-shared.GPTL0Size.0" file="shared_pseudocode.xml" hover="function: integer GPTL0Size()">GPTL0Size</a>();</line>
<line>    integer p;</line>
<line>    case pgs of</line>
<line>        when <a link="PGS_4KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_4KB</a>  p = 12;</line>
<line>        when <a link="PGS_16KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_16KB</a> p = 14;</line>
<line>        when <a link="PGS_64KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_64KB</a> p = 16;</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    if !<a link="impl-shared.IsZero.1" file="shared_pseudocode.xml" hover="function: boolean IsZero(bits(N) x)">IsZero</a>(entry&lt;(l0sz-p)-2:12&gt;) then</line>
<line>        return (<a link="GPCF_Walk" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_Walk</a>, <a link="GPTTable" file="shared_pseudocode.xml" hover="type GPTTable is ( bits(56) address )">GPTTable</a> UNKNOWN);</line>
<line></line>
<line>    case pgs of</line>
<line>        when <a link="PGS_4KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_4KB</a>  result.address = entry&lt;55:17&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(17);</line>
<line>        when <a link="PGS_16KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_16KB</a> result.address = entry&lt;55:15&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(15);</line>
<line>        when <a link="PGS_64KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_64KB</a> result.address = entry&lt;55:13&gt;:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(13);</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line></line>
<line>    // The address must be within the range covered by the GPT</line>
<line>    if <a link="impl-shared.AbovePPS.1" file="shared_pseudocode.xml" hover="function: boolean AbovePPS(bits(56) address)">AbovePPS</a>(result.address) then</line>
<line>        return (<a link="GPCF_AddressSize" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_AddressSize</a>, <a link="GPTTable" file="shared_pseudocode.xml" hover="type GPTTable is ( bits(56) address )">GPTTable</a> UNKNOWN);</line>
<line></line>
<line>    return (<a link="GPCF_None" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_None</a>, result);</line>
</pstext>
    </ps>
    <ps name="shared/translation/gpc/DecodePGS" mylink="shared.translation.gpc.DecodePGS" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DecodePGS()</line>
<line>// ===========</line>
<line></line>
<line link="impl-shared.DecodePGS.1" hover="function: PGSe DecodePGS(bits(2) pgs)" conts="DecodePGS">PGSe <anchor link="impl-shared.DecodePGS.1" hover="function: PGSe DecodePGS(bits(2) pgs)">DecodePGS</anchor>(bits(2) pgs)</line>
<line>    case pgs of</line>
<line>        when '00' return <a link="PGS_4KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_4KB</a>;</line>
<line>        when '10' return <a link="PGS_16KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_16KB</a>;</line>
<line>        when '01' return <a link="PGS_64KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_64KB</a>;</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
</pstext>
    </ps>
    <ps name="shared/translation/gpc/DecodePPS" mylink="shared.translation.gpc.DecodePPS" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DecodePPS()</line>
<line>// ===========</line>
<line>// Size of region protected by the GPT, in bits.</line>
<line></line>
<line link="impl-shared.DecodePPS.0" hover="function: integer DecodePPS()" conts="DecodePPS">integer <anchor link="impl-shared.DecodePPS.0" hover="function: integer DecodePPS()">DecodePPS</anchor>()</line>
<line>    case GPCCR_EL3.PPS of</line>
<line>        when '000' return 32;</line>
<line>        when '001' return 36;</line>
<line>        when '010' return 40;</line>
<line>        when '011' return 42;</line>
<line>        when '100' return 44;</line>
<line>        when '101' return 48;</line>
<line>        when '110' return 52;</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
</pstext>
    </ps>
    <ps name="shared/translation/gpc/GPCFault" mylink="shared.translation.gpc.GPCFault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GPCFault()</line>
<line>// ==========</line>
<line>// Constructs and returns a GPCF</line>
<line></line>
<line link="impl-shared.GPCFault.2" hover="function: GPCFRecord GPCFault(GPCF gpf, integer level)" conts="GPCFault">GPCFRecord <anchor link="impl-shared.GPCFault.2" hover="function: GPCFRecord GPCFault(GPCF gpf, integer level)">GPCFault</anchor>(<a link="GPCF" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF</a> gpf, integer level)</line>
<line>    <a link="GPCFRecord" file="shared_pseudocode.xml" hover="type GPCFRecord is ( GPCF gpf, integer level )">GPCFRecord</a> fault;</line>
<line>    fault.gpf   = gpf;</line>
<line>    fault.level = level;</line>
<line>    return fault;</line>
</pstext>
    </ps>
    <ps name="shared/translation/gpc/GPCNoFault" mylink="shared.translation.gpc.GPCNoFault" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GPCNoFault()</line>
<line>// ============</line>
<line>// Returns the default properties of a GPCF that does not represent a fault</line>
<line></line>
<line link="impl-shared.GPCNoFault.0" hover="function: GPCFRecord GPCNoFault()" conts="GPCNoFault">GPCFRecord <anchor link="impl-shared.GPCNoFault.0" hover="function: GPCFRecord GPCNoFault()">GPCNoFault</anchor>()</line>
<line>    <a link="GPCFRecord" file="shared_pseudocode.xml" hover="type GPCFRecord is ( GPCF gpf, integer level )">GPCFRecord</a> result;</line>
<line>    result.gpf = <a link="GPCF_None" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_None</a>;</line>
<line>    return result;</line>
</pstext>
    </ps>
    <ps name="shared/translation/gpc/GPCRegistersConsistent" mylink="shared.translation.gpc.GPCRegistersConsistent" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GPCRegistersConsistent()</line>
<line>// ========================</line>
<line>// Returns whether the GPT registers are configured correctly.</line>
<line>// This returns false if any fields select a Reserved value.</line>
<line></line>
<line link="impl-shared.GPCRegistersConsistent.0" hover="function: boolean GPCRegistersConsistent()" conts="GPCRegistersConsistent">boolean <anchor link="impl-shared.GPCRegistersConsistent.0" hover="function: boolean GPCRegistersConsistent()">GPCRegistersConsistent</anchor>()</line>
<line></line>
<line>    // Check for Reserved register values</line>
<line>    if GPCCR_EL3.PPS == '111' || <a link="impl-shared.DecodePPS.0" file="shared_pseudocode.xml" hover="function: integer DecodePPS()">DecodePPS</a>() &gt; <a link="AArch64.PAMax.0" file="shared_pseudocode.xml" hover="function: integer AArch64.PAMax()">AArch64.PAMax</a>() then</line>
<line>        return FALSE;</line>
<line>    if GPCCR_EL3.PGS == '11' then</line>
<line>        return FALSE;</line>
<line>    if GPCCR_EL3.SH == '01' then</line>
<line>        return FALSE;</line>
<line></line>
<line>    // Inner and Outer Non-cacheable requires Outer Shareable</line>
<line>    if GPCCR_EL3.&lt;ORGN, IRGN&gt; == '0000' &amp;&amp; GPCCR_EL3.SH != '10' then</line>
<line>        return FALSE;</line>
<line></line>
<line>    return TRUE;</line>
</pstext>
    </ps>
    <ps name="shared/translation/gpc/GPICheck" mylink="shared.translation.gpc.GPICheck" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GPICheck()</line>
<line>// ==========</line>
<line>// Returns whether an access to a given physical address space is permitted</line>
<line>// given the configured GPI value.</line>
<line>// paspace: Physical address space of the access</line>
<line>// gpi: Value read from GPT for the access</line>
<line></line>
<line link="impl-shared.GPICheck.2" hover="function: boolean GPICheck(PASpace paspace, bits(4) gpi)" conts="GPICheck">boolean <anchor link="impl-shared.GPICheck.2" hover="function: boolean GPICheck(PASpace paspace, bits(4) gpi)">GPICheck</anchor>(<a link="PASpace" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PASpace</a> paspace, bits(4) gpi)</line>
<line></line>
<line>    case gpi of</line>
<line>        when <a link="GPT_NoAccess" file="shared_pseudocode.xml" hover="constant bits(4) GPT_NoAccess = '0000'">GPT_NoAccess</a>  return FALSE;</line>
<line>        when <a link="GPT_Secure" file="shared_pseudocode.xml" hover="constant bits(4) GPT_Secure = '1000'">GPT_Secure</a>    assert <a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>();return paspace == <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a>;</line>
<line>        when <a link="GPT_NonSecure" file="shared_pseudocode.xml" hover="constant bits(4) GPT_NonSecure = '1001'">GPT_NonSecure</a> return paspace == <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line>        when <a link="GPT_Root" file="shared_pseudocode.xml" hover="constant bits(4) GPT_Root = '1010'">GPT_Root</a>      return paspace == <a link="PAS_Root" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Root</a>;</line>
<line>        when <a link="GPT_Realm" file="shared_pseudocode.xml" hover="constant bits(4) GPT_Realm = '1011'">GPT_Realm</a>     return paspace == <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a>;</line>
<line>        when <a link="GPT_Any" file="shared_pseudocode.xml" hover="constant bits(4) GPT_Any = '1111'">GPT_Any</a>       return TRUE;</line>
<line>        otherwise          <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
</pstext>
    </ps>
    <ps name="shared/translation/gpc/GPIIndex" mylink="shared.translation.gpc.GPIIndex" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GPIIndex()</line>
<line>// ==========</line>
<line></line>
<line link="impl-shared.GPIIndex.1" hover="function: integer GPIIndex(bits(56) pa)" conts="GPIIndex">integer <anchor link="impl-shared.GPIIndex.1" hover="function: integer GPIIndex(bits(56) pa)">GPIIndex</anchor>(bits(56) pa)</line>
<line>    case <a link="impl-shared.DecodePGS.1" file="shared_pseudocode.xml" hover="function: PGSe DecodePGS(bits(2) pgs)">DecodePGS</a>(GPCCR_EL3.PGS) of</line>
<line>        when <a link="PGS_4KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_4KB</a>  return <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(pa&lt;15:12&gt;);</line>
<line>        when <a link="PGS_16KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_16KB</a> return <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(pa&lt;17:14&gt;);</line>
<line>        when <a link="PGS_64KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_64KB</a> return <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(pa&lt;19:16&gt;);</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
</pstext>
    </ps>
    <ps name="shared/translation/gpc/GPIValid" mylink="shared.translation.gpc.GPIValid" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GPIValid()</line>
<line>// ==========</line>
<line>// Returns whether a given value is a valid encoding for a GPI value</line>
<line></line>
<line link="impl-shared.GPIValid.1" hover="function: boolean GPIValid(bits(4) gpi)" conts="GPIValid">boolean <anchor link="impl-shared.GPIValid.1" hover="function: boolean GPIValid(bits(4) gpi)">GPIValid</anchor>(bits(4) gpi)</line>
<line>    if gpi == <a link="GPT_Secure" file="shared_pseudocode.xml" hover="constant bits(4) GPT_Secure = '1000'">GPT_Secure</a> then</line>
<line>        return <a link="impl-shared.HaveSecureEL2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSecureEL2Ext()">HaveSecureEL2Ext</a>();</line>
<line></line>
<line>    return gpi IN {<a link="GPT_NoAccess" file="shared_pseudocode.xml" hover="constant bits(4) GPT_NoAccess = '0000'">GPT_NoAccess</a>,</line>
<line>                   <a link="GPT_NonSecure" file="shared_pseudocode.xml" hover="constant bits(4) GPT_NonSecure = '1001'">GPT_NonSecure</a>,</line>
<line>                   <a link="GPT_Root" file="shared_pseudocode.xml" hover="constant bits(4) GPT_Root = '1010'">GPT_Root</a>,</line>
<line>                   <a link="GPT_Realm" file="shared_pseudocode.xml" hover="constant bits(4) GPT_Realm = '1011'">GPT_Realm</a>,</line>
<line>                   <a link="GPT_Any" file="shared_pseudocode.xml" hover="constant bits(4) GPT_Any = '1111'">GPT_Any</a>};</line>
</pstext>
    </ps>
    <ps name="shared/translation/gpc/GPTL0Size" mylink="shared.translation.gpc.GPTL0Size" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GPTL0Size()</line>
<line>// ===========</line>
<line>// Returns number of bits covered by a level 0 GPT entry</line>
<line></line>
<line link="impl-shared.GPTL0Size.0" hover="function: integer GPTL0Size()" conts="GPTL0Size">integer <anchor link="impl-shared.GPTL0Size.0" hover="function: integer GPTL0Size()">GPTL0Size</anchor>()</line>
<line>    case GPCCR_EL3.L0GPTSZ of</line>
<line>        when '0000' return <a link="GPTRange_1GB" file="shared_pseudocode.xml" hover="constant integer GPTRange_1GB = 30">GPTRange_1GB</a>;</line>
<line>        when '0100' return <a link="GPTRange_16GB" file="shared_pseudocode.xml" hover="constant integer GPTRange_16GB = 34">GPTRange_16GB</a>;</line>
<line>        when '0110' return <a link="GPTRange_64GB" file="shared_pseudocode.xml" hover="constant integer GPTRange_64GB = 36">GPTRange_64GB</a>;</line>
<line>        when '1001' return <a link="GPTRange_512GB" file="shared_pseudocode.xml" hover="constant integer GPTRange_512GB = 39">GPTRange_512GB</a>;</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
<line>    return 30;</line>
</pstext>
    </ps>
    <ps name="shared/translation/gpc/GPTLevel0Index" mylink="shared.translation.gpc.GPTLevel0Index" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GPTLevel0Index()</line>
<line>// ================</line>
<line>// Compute the level 0 index based on input PA.</line>
<line></line>
<line link="impl-shared.GPTLevel0Index.1" hover="function: integer GPTLevel0Index(bits(56) pa)" conts="GPTLevel0Index">integer <anchor link="impl-shared.GPTLevel0Index.1" hover="function: integer GPTLevel0Index(bits(56) pa)">GPTLevel0Index</anchor>(bits(56) pa)</line>
<line>    // Input address and index bounds</line>
<line>    pps = <a link="impl-shared.DecodePPS.0" file="shared_pseudocode.xml" hover="function: integer DecodePPS()">DecodePPS</a>();</line>
<line>    l0sz = <a link="impl-shared.GPTL0Size.0" file="shared_pseudocode.xml" hover="function: integer GPTL0Size()">GPTL0Size</a>();</line>
<line>    if pps &lt;= l0sz then</line>
<line>        return 0;</line>
<line></line>
<line>    return <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(pa&lt;pps-1:l0sz&gt;);</line>
</pstext>
    </ps>
    <ps name="shared/translation/gpc/GPTLevel1Index" mylink="shared.translation.gpc.GPTLevel1Index" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GPTLevel1Index()</line>
<line>// ================</line>
<line>// Compute the level 1 index based on input PA.</line>
<line></line>
<line link="impl-shared.GPTLevel1Index.1" hover="function: integer GPTLevel1Index(bits(56) pa)" conts="GPTLevel1Index">integer <anchor link="impl-shared.GPTLevel1Index.1" hover="function: integer GPTLevel1Index(bits(56) pa)">GPTLevel1Index</anchor>(bits(56) pa)</line>
<line>    // Input address and index bounds</line>
<line>    l0sz = <a link="impl-shared.GPTL0Size.0" file="shared_pseudocode.xml" hover="function: integer GPTL0Size()">GPTL0Size</a>();</line>
<line>    case <a link="impl-shared.DecodePGS.1" file="shared_pseudocode.xml" hover="function: PGSe DecodePGS(bits(2) pgs)">DecodePGS</a>(GPCCR_EL3.PGS) of</line>
<line>        when <a link="PGS_4KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_4KB</a>  return <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(pa&lt;l0sz-1:16&gt;);</line>
<line>        when <a link="PGS_16KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_16KB</a> return <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(pa&lt;l0sz-1:18&gt;);</line>
<line>        when <a link="PGS_64KB" file="shared_pseudocode.xml" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_64KB</a> return <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(pa&lt;l0sz-1:20&gt;);</line>
<line>        otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
</pstext>
    </ps>
    <ps name="shared/translation/gpc/GPTWalk" mylink="shared.translation.gpc.GPTWalk" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GPTWalk()</line>
<line>// =========</line>
<line>// Get the GPT entry for a given physical address, pa</line>
<line></line>
<line link="impl-shared.GPTWalk.2" hover="function: (GPCFRecord, GPTEntry) GPTWalk(bits(56) pa, AccessDescriptor accdesc)" conts="GPTWalk">(GPCFRecord, GPTEntry) <anchor link="impl-shared.GPTWalk.2" hover="function: (GPCFRecord, GPTEntry) GPTWalk(bits(56) pa, AccessDescriptor accdesc)">GPTWalk</anchor>(bits(56) pa, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line></line>
<line>    // GPT base address</line>
<line>    bits(56) base;</line>
<line>    pgs = <a link="impl-shared.DecodePGS.1" file="shared_pseudocode.xml" hover="function: PGSe DecodePGS(bits(2) pgs)">DecodePGS</a>(GPCCR_EL3.PGS);</line>
<line></line>
<line>    // The level 0 GPT base address is aligned to the greater of:</line>
<line>    // * the size of the level 0 GPT, determined by GPCCR_EL3.{PPS, L0GPTSZ}.</line>
<line>    // * 4KB</line>
<line>    base = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(GPTBR_EL3.BADDR:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12), 56);</line>
<line>    pps = <a link="impl-shared.DecodePPS.0" file="shared_pseudocode.xml" hover="function: integer DecodePPS()">DecodePPS</a>();</line>
<line>    l0sz = <a link="impl-shared.GPTL0Size.0" file="shared_pseudocode.xml" hover="function: integer GPTL0Size()">GPTL0Size</a>();</line>
<line>    integer alignment = <a link="impl-shared.Max.2" file="shared_pseudocode.xml" hover="function: integer Max(integer a, integer b)">Max</a>((pps - l0sz) + 3, 12);</line>
<line>    base = base AND NOT <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(alignment), 56);</line>
<line></line>
<line>    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> gptaccdesc = <a link="impl-shared.CreateAccDescGPTW.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescGPTW(AccessDescriptor accdesc_in)">CreateAccDescGPTW</a>(accdesc);</line>
<line></line>
<line>    // Access attributes and address for GPT fetches</line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> gptaddrdesc;</line>
<line>    gptaddrdesc.memattrs = <a link="impl-shared.WalkMemAttrs.3" file="shared_pseudocode.xml" hover="function: MemoryAttributes WalkMemAttrs(bits(2) sh, bits(2) irgn, bits(2) orgn)">WalkMemAttrs</a>(GPCCR_EL3.SH, GPCCR_EL3.ORGN, GPCCR_EL3.IRGN);</line>
<line>    gptaddrdesc.fault    = <a link="impl-shared.NoFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord NoFault(AccessDescriptor accdesc)">NoFault</a>(gptaccdesc);</line>
<line></line>
<line>    // Address of level 0 GPT entry</line>
<line>    gptaddrdesc.paddress.paspace = <a link="PAS_Root" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Root</a>;</line>
<line>    gptaddrdesc.paddress.address = base + <a link="impl-shared.GPTLevel0Index.1" file="shared_pseudocode.xml" hover="function: integer GPTLevel0Index(bits(56) pa)">GPTLevel0Index</a>(pa) * 8;</line>
<line></line>
<line>    // Fetch L0GPT entry</line>
<line>    bits(64) level_0_entry;</line>
<line>    <a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> memstatus;</line>
<line>    (memstatus, level_0_entry) = <a link="impl-shared.PhysMemRead.3" file="shared_pseudocode.xml" hover="function: (PhysMemRetStatus, bits(8*size)) PhysMemRead(AddressDescriptor desc, integer size, AccessDescriptor accdesc)">PhysMemRead</a>(gptaddrdesc, 8, gptaccdesc);</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>        return (<a link="impl-shared.GPCFault.2" file="shared_pseudocode.xml" hover="function: GPCFRecord GPCFault(GPCF gpf, integer level)">GPCFault</a>(<a link="GPCF_EABT" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_EABT</a>, 0), <a link="GPTEntry" file="shared_pseudocode.xml" hover="type GPTEntry is ( bits(4) gpi, integer size, integer contig_size, integer level, bits(56) pa )">GPTEntry</a> UNKNOWN);</line>
<line></line>
<line>    <a link="GPTEntry" file="shared_pseudocode.xml" hover="type GPTEntry is ( bits(4) gpi, integer size, integer contig_size, integer level, bits(56) pa )">GPTEntry</a> result;</line>
<line>    <a link="GPTTable" file="shared_pseudocode.xml" hover="type GPTTable is ( bits(56) address )">GPTTable</a> table;</line>
<line>    <a link="GPCF" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF</a> gpf;</line>
<line>    case level_0_entry&lt;3:0&gt; of</line>
<line>        when <a link="GPT_Block" file="shared_pseudocode.xml" hover="constant bits(4) GPT_Block = '0001'">GPT_Block</a></line>
<line>            // Decode the GPI value and return that</line>
<line>            (gpf, result) = <a link="impl-shared.DecodeGPTBlock.2" file="shared_pseudocode.xml" hover="function: (GPCF, GPTEntry) DecodeGPTBlock(PGSe pgs, bits(64) entry)">DecodeGPTBlock</a>(pgs, level_0_entry);</line>
<line>            result.pa = pa;</line>
<line>            return (<a link="impl-shared.GPCFault.2" file="shared_pseudocode.xml" hover="function: GPCFRecord GPCFault(GPCF gpf, integer level)">GPCFault</a>(gpf, 0), result);</line>
<line>        when <a link="GPT_Table" file="shared_pseudocode.xml" hover="constant bits(4) GPT_Table = '0011'">GPT_Table</a></line>
<line>            // Decode the table entry and continue walking</line>
<line>            (gpf, table) = <a link="impl-shared.DecodeGPTTable.2" file="shared_pseudocode.xml" hover="function: (GPCF, GPTTable) DecodeGPTTable(PGSe pgs, bits(64) entry)">DecodeGPTTable</a>(pgs, level_0_entry);</line>
<line>            if gpf != <a link="GPCF_None" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_None</a> then</line>
<line>                return (<a link="impl-shared.GPCFault.2" file="shared_pseudocode.xml" hover="function: GPCFRecord GPCFault(GPCF gpf, integer level)">GPCFault</a>(gpf, 0), <a link="GPTEntry" file="shared_pseudocode.xml" hover="type GPTEntry is ( bits(4) gpi, integer size, integer contig_size, integer level, bits(56) pa )">GPTEntry</a> UNKNOWN);</line>
<line>        otherwise</line>
<line>            // GPF - invalid encoding</line>
<line>            return (<a link="impl-shared.GPCFault.2" file="shared_pseudocode.xml" hover="function: GPCFRecord GPCFault(GPCF gpf, integer level)">GPCFault</a>(<a link="GPCF_Walk" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_Walk</a>, 0), <a link="GPTEntry" file="shared_pseudocode.xml" hover="type GPTEntry is ( bits(4) gpi, integer size, integer contig_size, integer level, bits(56) pa )">GPTEntry</a> UNKNOWN);</line>
<line></line>
<line>    // Must be a GPT Table entry</line>
<line>    assert level_0_entry&lt;3:0&gt; == <a link="GPT_Table" file="shared_pseudocode.xml" hover="constant bits(4) GPT_Table = '0011'">GPT_Table</a>;</line>
<line></line>
<line>    // Address of level 1 GPT entry</line>
<line>    offset = <a link="impl-shared.GPTLevel1Index.1" file="shared_pseudocode.xml" hover="function: integer GPTLevel1Index(bits(56) pa)">GPTLevel1Index</a>(pa) * 8;</line>
<line>    gptaddrdesc.paddress.address = table.address + offset;</line>
<line></line>
<line>    // Fetch L1GPT entry</line>
<line>    bits(64) level_1_entry;</line>
<line>    (memstatus, level_1_entry) = <a link="impl-shared.PhysMemRead.3" file="shared_pseudocode.xml" hover="function: (PhysMemRetStatus, bits(8*size)) PhysMemRead(AddressDescriptor desc, integer size, AccessDescriptor accdesc)">PhysMemRead</a>(gptaddrdesc, 8, gptaccdesc);</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>        return (<a link="impl-shared.GPCFault.2" file="shared_pseudocode.xml" hover="function: GPCFRecord GPCFault(GPCF gpf, integer level)">GPCFault</a>(<a link="GPCF_EABT" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_EABT</a>, 1), <a link="GPTEntry" file="shared_pseudocode.xml" hover="type GPTEntry is ( bits(4) gpi, integer size, integer contig_size, integer level, bits(56) pa )">GPTEntry</a> UNKNOWN);</line>
<line></line>
<line>    case level_1_entry&lt;3:0&gt; of</line>
<line>        when <a link="GPT_Contig" file="shared_pseudocode.xml" hover="constant bits(4) GPT_Contig = '0001'">GPT_Contig</a></line>
<line>            (gpf, result) = <a link="impl-shared.DecodeGPTContiguous.2" file="shared_pseudocode.xml" hover="function: (GPCF, GPTEntry) DecodeGPTContiguous(PGSe pgs, bits(64) entry)">DecodeGPTContiguous</a>(pgs, level_1_entry);</line>
<line>        otherwise</line>
<line>            gpi_index = <a link="impl-shared.GPIIndex.1" file="shared_pseudocode.xml" hover="function: integer GPIIndex(bits(56) pa)">GPIIndex</a>(pa);</line>
<line>            (gpf, result) = <a link="impl-shared.DecodeGPTGranules.3" file="shared_pseudocode.xml" hover="function: (GPCF, GPTEntry) DecodeGPTGranules(PGSe pgs, integer index, bits(64) entry)">DecodeGPTGranules</a>(pgs, gpi_index, level_1_entry);</line>
<line></line>
<line>    if gpf != <a link="GPCF_None" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_None</a> then</line>
<line>        return (<a link="impl-shared.GPCFault.2" file="shared_pseudocode.xml" hover="function: GPCFRecord GPCFault(GPCF gpf, integer level)">GPCFault</a>(gpf, 1), <a link="GPTEntry" file="shared_pseudocode.xml" hover="type GPTEntry is ( bits(4) gpi, integer size, integer contig_size, integer level, bits(56) pa )">GPTEntry</a> UNKNOWN);</line>
<line></line>
<line>    result.pa = pa;</line>
<line>    return (<a link="impl-shared.GPCNoFault.0" file="shared_pseudocode.xml" hover="function: GPCFRecord GPCNoFault()">GPCNoFault</a>(), result);</line>
</pstext>
    </ps>
    <ps name="shared/translation/gpc/GranuleProtectionCheck" mylink="shared.translation.gpc.GranuleProtectionCheck" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// GranuleProtectionCheck()</line>
<line>// ========================</line>
<line>// Returns whether a given access is permitted, according to the</line>
<line>// granule protection check.</line>
<line>// addrdesc and accdesc describe the access to be checked.</line>
<line></line>
<line link="impl-shared.GranuleProtectionCheck.2" hover="function: GPCFRecord GranuleProtectionCheck(AddressDescriptor addrdesc, AccessDescriptor accdesc)" conts="GranuleProtectionCheck">GPCFRecord <anchor link="impl-shared.GranuleProtectionCheck.2" hover="function: GPCFRecord GranuleProtectionCheck(AddressDescriptor addrdesc, AccessDescriptor accdesc)">GranuleProtectionCheck</anchor>(<a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> addrdesc, <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc)</line>
<line></line>
<line>    assert <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>();</line>
<line>    // The address to be checked</line>
<line>    address = addrdesc.paddress;</line>
<line></line>
<line>    // Bypass mode - all accesses pass</line>
<line>    if GPCCR_EL3.GPC == '0' then</line>
<line>        return <a link="impl-shared.GPCNoFault.0" file="shared_pseudocode.xml" hover="function: GPCFRecord GPCNoFault()">GPCNoFault</a>();</line>
<line></line>
<line>    // Configuration consistency check</line>
<line>    if !<a link="impl-shared.GPCRegistersConsistent.0" file="shared_pseudocode.xml" hover="function: boolean GPCRegistersConsistent()">GPCRegistersConsistent</a>() then</line>
<line>        return <a link="impl-shared.GPCFault.2" file="shared_pseudocode.xml" hover="function: GPCFRecord GPCFault(GPCF gpf, integer level)">GPCFault</a>(<a link="GPCF_Walk" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_Walk</a>, 0);</line>
<line></line>
<line>    // Input address size check</line>
<line>    if <a link="impl-shared.AbovePPS.1" file="shared_pseudocode.xml" hover="function: boolean AbovePPS(bits(56) address)">AbovePPS</a>(address.address) then</line>
<line>        if address.paspace == <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a> then</line>
<line>            return <a link="impl-shared.GPCNoFault.0" file="shared_pseudocode.xml" hover="function: GPCFRecord GPCNoFault()">GPCNoFault</a>();</line>
<line>        else</line>
<line>            return <a link="impl-shared.GPCFault.2" file="shared_pseudocode.xml" hover="function: GPCFRecord GPCFault(GPCF gpf, integer level)">GPCFault</a>(<a link="GPCF_Fail" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_Fail</a>, 0);</line>
<line></line>
<line>    // GPT base address size check</line>
<line>    bits(56) gpt_base = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(GPTBR_EL3.BADDR:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12), 56);</line>
<line>    if <a link="impl-shared.AbovePPS.1" file="shared_pseudocode.xml" hover="function: boolean AbovePPS(bits(56) address)">AbovePPS</a>(gpt_base) then</line>
<line>        return <a link="impl-shared.GPCFault.2" file="shared_pseudocode.xml" hover="function: GPCFRecord GPCFault(GPCF gpf, integer level)">GPCFault</a>(<a link="GPCF_AddressSize" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_AddressSize</a>, 0);</line>
<line></line>
<line>    // GPT lookup</line>
<line>    (gpcf, gpt_entry) = <a link="impl-shared.GPTWalk.2" file="shared_pseudocode.xml" hover="function: (GPCFRecord, GPTEntry) GPTWalk(bits(56) pa, AccessDescriptor accdesc)">GPTWalk</a>(address.address, accdesc);</line>
<line>    if gpcf.gpf != <a link="GPCF_None" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_None</a> then</line>
<line>        return gpcf;</line>
<line></line>
<line>    // Check input physical address space against GPI</line>
<line>    permitted = <a link="impl-shared.GPICheck.2" file="shared_pseudocode.xml" hover="function: boolean GPICheck(PASpace paspace, bits(4) gpi)">GPICheck</a>(address.paspace, gpt_entry.gpi);</line>
<line></line>
<line>    if !permitted then</line>
<line>        gpcf = <a link="impl-shared.GPCFault.2" file="shared_pseudocode.xml" hover="function: GPCFRecord GPCFault(GPCF gpf, integer level)">GPCFault</a>(<a link="GPCF_Fail" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_Fail</a>, gpt_entry.level);</line>
<line>        return gpcf;</line>
<line></line>
<line>    // Check passed</line>
<line></line>
<line>    return <a link="impl-shared.GPCNoFault.0" file="shared_pseudocode.xml" hover="function: GPCFRecord GPCNoFault()">GPCNoFault</a>();</line>
</pstext>
    </ps>
    <ps name="shared/translation/gpc/PGS" mylink="shared.translation.gpc.PGS" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// PGS</line>
<line>// ===</line>
<line>// Physical granule size</line>
<line></line>
<line link="PGSe" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }" conts="PGSe">enumeration <anchor link="PGSe" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGSe</anchor> {</line>
<line link="PGS_4KB" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }" conts="PGS_4KB">    <anchor link="PGS_4KB" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_4KB</anchor>,</line>
<line link="PGS_16KB" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }" conts="PGS_16KB">    <anchor link="PGS_16KB" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_16KB</anchor>,</line>
<line link="PGS_64KB" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }" conts="PGS_64KB">    <anchor link="PGS_64KB" hover="enumeration PGSe { PGS_4KB, PGS_16KB, PGS_64KB }">PGS_64KB</anchor></line>
<line>};</line>
</pstext>
    </ps>
    <ps name="shared/translation/gpc/Table" mylink="shared.translation.gpc.Table" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="GPT_NoAccess" hover="constant bits(4) GPT_NoAccess = '0000'" conts="GPT_NoAccess">constant bits(4) <anchor link="GPT_NoAccess" hover="constant bits(4) GPT_NoAccess = '0000'">GPT_NoAccess</anchor>  = '0000';</line>
<line link="GPT_Table" hover="constant bits(4) GPT_Table = '0011'" conts="GPT_Table">constant bits(4) <anchor link="GPT_Table" hover="constant bits(4) GPT_Table = '0011'">GPT_Table</anchor>     = '0011';</line>
<line link="GPT_Block" hover="constant bits(4) GPT_Block = '0001'" conts="GPT_Block">constant bits(4) <anchor link="GPT_Block" hover="constant bits(4) GPT_Block = '0001'">GPT_Block</anchor>     = '0001';</line>
<line link="GPT_Contig" hover="constant bits(4) GPT_Contig = '0001'" conts="GPT_Contig">constant bits(4) <anchor link="GPT_Contig" hover="constant bits(4) GPT_Contig = '0001'">GPT_Contig</anchor>    = '0001';</line>
<line link="GPT_Secure" hover="constant bits(4) GPT_Secure = '1000'" conts="GPT_Secure">constant bits(4) <anchor link="GPT_Secure" hover="constant bits(4) GPT_Secure = '1000'">GPT_Secure</anchor>    = '1000';</line>
<line link="GPT_NonSecure" hover="constant bits(4) GPT_NonSecure = '1001'" conts="GPT_NonSecure">constant bits(4) <anchor link="GPT_NonSecure" hover="constant bits(4) GPT_NonSecure = '1001'">GPT_NonSecure</anchor> = '1001';</line>
<line link="GPT_Root" hover="constant bits(4) GPT_Root = '1010'" conts="GPT_Root">constant bits(4) <anchor link="GPT_Root" hover="constant bits(4) GPT_Root = '1010'">GPT_Root</anchor>      = '1010';</line>
<line link="GPT_Realm" hover="constant bits(4) GPT_Realm = '1011'" conts="GPT_Realm">constant bits(4) <anchor link="GPT_Realm" hover="constant bits(4) GPT_Realm = '1011'">GPT_Realm</anchor>     = '1011';</line>
<line link="GPT_Any" hover="constant bits(4) GPT_Any = '1111'" conts="GPT_Any">constant bits(4) <anchor link="GPT_Any" hover="constant bits(4) GPT_Any = '1111'">GPT_Any</anchor>       = '1111';</line>
<line link="GPTRange_4KB" hover="constant integer GPTRange_4KB = 12" conts="GPTRange_4KB">constant integer <anchor link="GPTRange_4KB" hover="constant integer GPTRange_4KB = 12">GPTRange_4KB</anchor>   = 12;</line>
<line link="GPTRange_16KB" hover="constant integer GPTRange_16KB = 14" conts="GPTRange_16KB">constant integer <anchor link="GPTRange_16KB" hover="constant integer GPTRange_16KB = 14">GPTRange_16KB</anchor>  = 14;</line>
<line link="GPTRange_64KB" hover="constant integer GPTRange_64KB = 16" conts="GPTRange_64KB">constant integer <anchor link="GPTRange_64KB" hover="constant integer GPTRange_64KB = 16">GPTRange_64KB</anchor>  = 16;</line>
<line link="GPTRange_2MB" hover="constant integer GPTRange_2MB = 21" conts="GPTRange_2MB">constant integer <anchor link="GPTRange_2MB" hover="constant integer GPTRange_2MB = 21">GPTRange_2MB</anchor>   = 21;</line>
<line link="GPTRange_32MB" hover="constant integer GPTRange_32MB = 25" conts="GPTRange_32MB">constant integer <anchor link="GPTRange_32MB" hover="constant integer GPTRange_32MB = 25">GPTRange_32MB</anchor>  = 25;</line>
<line link="GPTRange_512MB" hover="constant integer GPTRange_512MB = 29" conts="GPTRange_512MB">constant integer <anchor link="GPTRange_512MB" hover="constant integer GPTRange_512MB = 29">GPTRange_512MB</anchor> = 29;</line>
<line link="GPTRange_1GB" hover="constant integer GPTRange_1GB = 30" conts="GPTRange_1GB">constant integer <anchor link="GPTRange_1GB" hover="constant integer GPTRange_1GB = 30">GPTRange_1GB</anchor>   = 30;</line>
<line link="GPTRange_16GB" hover="constant integer GPTRange_16GB = 34" conts="GPTRange_16GB">constant integer <anchor link="GPTRange_16GB" hover="constant integer GPTRange_16GB = 34">GPTRange_16GB</anchor>  = 34;</line>
<line link="GPTRange_64GB" hover="constant integer GPTRange_64GB = 36" conts="GPTRange_64GB">constant integer <anchor link="GPTRange_64GB" hover="constant integer GPTRange_64GB = 36">GPTRange_64GB</anchor>  = 36;</line>
<line link="GPTRange_512GB" hover="constant integer GPTRange_512GB = 39" conts="GPTRange_512GB">constant integer <anchor link="GPTRange_512GB" hover="constant integer GPTRange_512GB = 39">GPTRange_512GB</anchor> = 39;</line>
<line></line>
<line link="GPTTable" hover="type GPTTable is ( bits(56) address )" conts="GPTTable">type <anchor link="GPTTable" hover="type GPTTable is ( bits(56) address )">GPTTable</anchor> is (</line>
<line>    bits(56) address        // Base address of next table</line>
<line>)</line>
<line></line>
<line link="GPTEntry" hover="type GPTEntry is ( bits(4) gpi, integer size, integer contig_size, integer level, bits(56) pa )" conts="GPTEntry">type <anchor link="GPTEntry" hover="type GPTEntry is ( bits(4) gpi, integer size, integer contig_size, integer level, bits(56) pa )">GPTEntry</anchor> is (</line>
<line>    bits(4)  gpi,           // GPI value for this region</line>
<line>    integer  size,          // Region size</line>
<line>    integer  contig_size,   // Contiguous region size</line>
<line>    integer  level,         // Level of GPT lookup</line>
<line>    bits(56) pa             // PA uniquely identifying the GPT entry</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="shared/translation/translation/S1TranslationRegime" mylink="shared.translation.translation.S1TranslationRegime" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// S1TranslationRegime()</line>
<line>// =====================</line>
<line>// Stage 1 translation regime for the given Exception level</line>
<line></line>
<line link="impl-shared.S1TranslationRegime.1" hover="function: bits(2) S1TranslationRegime(bits(2) el)" conts="S1TranslationRegime">bits(2) <anchor link="impl-shared.S1TranslationRegime.1" hover="function: bits(2) S1TranslationRegime(bits(2) el)">S1TranslationRegime</anchor>(bits(2) el)</line>
<line>    if el != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        return el;</line>
<line>    elsif <a link="impl-shared.HaveEL.1" file="shared_pseudocode.xml" hover="function: boolean HaveEL(bits(2) el)">HaveEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) &amp;&amp; SCR.NS == '0' then</line>
<line>        return <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>;</line>
<line>    elsif <a link="impl-shared.HaveVirtHostExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveVirtHostExt()">HaveVirtHostExt</a>() &amp;&amp; <a link="impl-shared.ELIsInHost.1" file="shared_pseudocode.xml" hover="function: boolean ELIsInHost(bits(2) el)">ELIsInHost</a>(el) then</line>
<line>        return <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>;</line>
<line>    else</line>
<line>        return <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>;</line>
<line></line>
<line>// S1TranslationRegime()</line>
<line>// =====================</line>
<line>// Returns the Exception level controlling the current Stage 1 translation regime. For the most</line>
<line>// part this is unused in code because the System register accessors (SCTLR[], etc.) implicitly</line>
<line>// return the correct value.</line>
<line></line>
<line link="impl-shared.S1TranslationRegime.0" hover="function: bits(2) S1TranslationRegime()" conts="S1TranslationRegime">bits(2) <anchor link="impl-shared.S1TranslationRegime.0" hover="function: bits(2) S1TranslationRegime()">S1TranslationRegime</anchor>()</line>
<line>    return <a link="impl-shared.S1TranslationRegime.1" file="shared_pseudocode.xml" hover="function: bits(2) S1TranslationRegime(bits(2) el)">S1TranslationRegime</a>(PSTATE.EL);</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/AddressDescriptor" mylink="shared.translation.vmsa.AddressDescriptor" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="FINAL_LEVEL" hover="constant integer FINAL_LEVEL = 3" conts="FINAL_LEVEL">constant integer <anchor link="FINAL_LEVEL" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</anchor> = 3;</line>
<line></line>
<line>// AddressDescriptor</line>
<line>// =================</line>
<line>// Descriptor used to access the underlying memory array.</line>
<line></line>
<line link="AddressDescriptor" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )" conts="AddressDescriptor">type <anchor link="AddressDescriptor" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</anchor> is (</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a>      fault,      // fault.statuscode indicates whether the address is valid</line>
<line>    <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs,</line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a>      paddress,</line>
<line>    boolean          s1assured,  // Stage 1 Assured Translation Property</line>
<line>    boolean          s2fs1mro,   // Stage 2 MRO permission for Satge 1</line>
<line>    bits(16)         mecid,      // FEAT_MEC: Memory Encryption Context ID</line>
<line>    bits(64)         vaddress</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/ContiguousSize" mylink="shared.translation.vmsa.ContiguousSize" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// ContiguousSize()</line>
<line>// ================</line>
<line>// Return the number of entries log 2 marking a contiguous output range</line>
<line></line>
<line link="impl-shared.ContiguousSize.3" hover="function: integer ContiguousSize(bit d128, TGx tgx, integer level)" conts="ContiguousSize">integer <anchor link="impl-shared.ContiguousSize.3" hover="function: integer ContiguousSize(bit d128, TGx tgx, integer level)">ContiguousSize</anchor>(bit d128, <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tgx, integer level)</line>
<line>    if d128 == '1' then</line>
<line>        return 4;</line>
<line>    else</line>
<line>        case tgx of</line>
<line>            when <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a></line>
<line>                assert level != 0;</line>
<line>                return 4;</line>
<line>            when <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a></line>
<line>                assert level IN {2, 3};</line>
<line>                return if level == 2 then 5 else 7;</line>
<line>            when <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a></line>
<line>                assert level != 1;</line>
<line>                return 5;</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/CreateAddressDescriptor" mylink="shared.translation.vmsa.CreateAddressDescriptor" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateAddressDescriptor()</line>
<line>// =========================</line>
<line>// Set internal members for address descriptor type to valid values</line>
<line></line>
<line link="impl-shared.CreateAddressDescriptor.3" hover="function: AddressDescriptor CreateAddressDescriptor(bits(64) va, FullAddress pa, MemoryAttributes memattrs)" conts="CreateAddressDescriptor">AddressDescriptor <anchor link="impl-shared.CreateAddressDescriptor.3" hover="function: AddressDescriptor CreateAddressDescriptor(bits(64) va, FullAddress pa, MemoryAttributes memattrs)">CreateAddressDescriptor</anchor>(bits(64) va, <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> pa,</line>
<line>                                          <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a> memattrs)</line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> addrdesc;</line>
<line></line>
<line>    addrdesc.paddress = pa;</line>
<line>    addrdesc.vaddress = va;</line>
<line>    addrdesc.memattrs = memattrs;</line>
<line>    addrdesc.fault    = <a link="impl-shared.NoFault.0" file="shared_pseudocode.xml" hover="function: FaultRecord NoFault()">NoFault</a>();</line>
<line>    addrdesc.s1assured = FALSE;</line>
<line></line>
<line>    return addrdesc;</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/CreateFaultyAddressDescriptor" mylink="shared.translation.vmsa.CreateFaultyAddressDescriptor" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// CreateFaultyAddressDescriptor()</line>
<line>// ===============================</line>
<line>// Set internal members for address descriptor type with values indicating error</line>
<line></line>
<line link="impl-shared.CreateFaultyAddressDescriptor.2" hover="function: AddressDescriptor CreateFaultyAddressDescriptor(bits(64) va, FaultRecord fault)" conts="CreateFaultyAddressDescriptor">AddressDescriptor <anchor link="impl-shared.CreateFaultyAddressDescriptor.2" hover="function: AddressDescriptor CreateFaultyAddressDescriptor(bits(64) va, FaultRecord fault)">CreateFaultyAddressDescriptor</anchor>(bits(64) va, <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault)</line>
<line>    <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> addrdesc;</line>
<line></line>
<line>    addrdesc.vaddress = va;</line>
<line>    addrdesc.fault    = fault;</line>
<line></line>
<line>    return addrdesc;</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/DecodePASpace" mylink="shared.translation.vmsa.DecodePASpace" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DecodePASpace()</line>
<line>// ===============</line>
<line>// Decode the target PA Space</line>
<line></line>
<line link="impl-shared.DecodePASpace.2" hover="function: PASpace DecodePASpace (bit nse, bit ns)" conts="DecodePASpace">PASpace <anchor link="impl-shared.DecodePASpace.2" hover="function: PASpace DecodePASpace (bit nse, bit ns)">DecodePASpace</anchor> (bit nse, bit ns)</line>
<line>    case nse:ns of</line>
<line>        when '00'   return <a link="PAS_Secure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Secure</a>;</line>
<line>        when '01'   return <a link="PAS_NonSecure" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_NonSecure</a>;</line>
<line>        when '10'   return <a link="PAS_Root" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Root</a>;</line>
<line>        when '11'   return <a link="PAS_Realm" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PAS_Realm</a>;</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/DescriptorType" mylink="shared.translation.vmsa.DescriptorType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// DescriptorType</line>
<line>// ==============</line>
<line>// Translation table descriptor formats</line>
<line></line>
<line link="DescriptorType" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }" conts="DescriptorType">enumeration <anchor link="DescriptorType" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType</anchor> {</line>
<line link="DescriptorType_Table" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }" conts="DescriptorType_Table">    <anchor link="DescriptorType_Table" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Table</anchor>,</line>
<line link="DescriptorType_Leaf" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }" conts="DescriptorType_Leaf">    <anchor link="DescriptorType_Leaf" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Leaf</anchor>,</line>
<line link="DescriptorType_Invalid" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }" conts="DescriptorType_Invalid">    <anchor link="DescriptorType_Invalid" hover="enumeration DescriptorType { DescriptorType_Table, DescriptorType_Leaf, DescriptorType_Invalid }">DescriptorType_Invalid</anchor></line>
<line>};</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/Domains" mylink="shared.translation.vmsa.Domains" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line link="Domain_NoAccess" hover="constant bits(2) Domain_NoAccess = '00'" conts="Domain_NoAccess">constant bits(2) <anchor link="Domain_NoAccess" hover="constant bits(2) Domain_NoAccess = '00'">Domain_NoAccess</anchor> = '00';</line>
<line link="Domain_Client" hover="constant bits(2) Domain_Client = '01'" conts="Domain_Client">constant bits(2) <anchor link="Domain_Client" hover="constant bits(2) Domain_Client = '01'">Domain_Client</anchor>   = '01';</line>
<line link="Domain_Manager" hover="constant bits(2) Domain_Manager = '11'" conts="Domain_Manager">constant bits(2) <anchor link="Domain_Manager" hover="constant bits(2) Domain_Manager = '11'">Domain_Manager</anchor>  = '11';</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/FetchDescriptor" mylink="shared.translation.vmsa.FetchDescriptor" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// FetchDescriptor()</line>
<line>// =================</line>
<line>// Fetch a translation table descriptor</line>
<line></line>
<line link="impl-shared.FetchDescriptor.5" hover="function: (FaultRecord, bits(N)) FetchDescriptor(bit ee, AddressDescriptor walkaddress, AccessDescriptor walkaccess, FaultRecord fault_in, integer N)" conts="FetchDescriptor">(FaultRecord, bits(N)) <anchor link="impl-shared.FetchDescriptor.5" hover="function: (FaultRecord, bits(N)) FetchDescriptor(bit ee, AddressDescriptor walkaddress, AccessDescriptor walkaccess, FaultRecord fault_in, integer N)">FetchDescriptor</anchor>(bit ee, <a link="AddressDescriptor" file="shared_pseudocode.xml" hover="type AddressDescriptor is ( FaultRecord fault, MemoryAttributes memattrs, FullAddress paddress, boolean s1assured, boolean s2fs1mro, bits(16) mecid, bits(64) vaddress )">AddressDescriptor</a> walkaddress,</line>
<line>                                       <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> walkaccess, <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault_in,</line>
<line>                                       integer N)</line>
<line>    // 32-bit descriptors for AArch32 Short-descriptor format</line>
<line>    // 64-bit descriptors for AArch64 or AArch32 Long-descriptor format</line>
<line>    // 128-bit descriptors for AArch64 when FEAT_D128 is set and {V}TCR_ELx.d128 is set</line>
<line>    assert N == 32 || N == 64 || N == 128;</line>
<line>    bits(N) descriptor;</line>
<line>    <a link="FaultRecord" file="shared_pseudocode.xml" hover="type FaultRecord is ( Fault statuscode, AccessDescriptor access, FullAddress ipaddress, GPCFRecord gpcf, FullAddress paddress, boolean gpcfs2walk, boolean s2fs1walk, boolean write, boolean s1tagnotdata, boolean tagaccess, integer level, bit extflag, boolean secondstage, boolean assuredonly, boolean toplevel, boolean overlay, boolean dirtybit, bits(4) domain, ErrorState merrorstate, bits(4) debugmoe )">FaultRecord</a> fault = fault_in;</line>
<line></line>
<line>    if <a link="impl-shared.HaveRME.0" file="shared_pseudocode.xml" hover="function: boolean HaveRME()">HaveRME</a>() then</line>
<line>        fault.gpcf = <a link="impl-shared.GranuleProtectionCheck.2" file="shared_pseudocode.xml" hover="function: GPCFRecord GranuleProtectionCheck(AddressDescriptor addrdesc, AccessDescriptor accdesc)">GranuleProtectionCheck</a>(walkaddress, walkaccess);</line>
<line>        if fault.gpcf.gpf != <a link="GPCF_None" file="shared_pseudocode.xml" hover="enumeration GPCF { GPCF_None, GPCF_AddressSize, GPCF_Walk, GPCF_EABT, GPCF_Fail }">GPCF_None</a> then</line>
<line>            fault.statuscode = <a link="Fault_GPCFOnWalk" file="shared_pseudocode.xml" hover="enumeration Fault {Fault_None, Fault_AccessFlag, Fault_Alignment, Fault_Background, Fault_Domain, Fault_Permission, Fault_Translation, Fault_AddressSize, Fault_SyncExternal, Fault_SyncExternalOnWalk, Fault_SyncParity, Fault_SyncParityOnWalk, Fault_GPCFOnWalk, Fault_GPCFOnOutput, Fault_AsyncParity, Fault_AsyncExternal, Fault_TagCheck, Fault_Debug, Fault_TLBConflict, Fault_BranchTarget, Fault_HWUpdateAccessFlag, Fault_Lockdown, Fault_Exclusive, Fault_ICacheMaint}">Fault_GPCFOnWalk</a>;</line>
<line>            fault.paddress   = walkaddress.paddress;</line>
<line>            fault.gpcfs2walk = fault.secondstage;</line>
<line>            return (fault, bits(N) UNKNOWN);</line>
<line></line>
<line>    <a link="PhysMemRetStatus" file="shared_pseudocode.xml" hover="type PhysMemRetStatus is ( Fault statuscode, bit extflag, ErrorState merrorstate, bits(64) store64bstatus )">PhysMemRetStatus</a> memstatus;</line>
<line>    (memstatus, descriptor) = <a link="impl-shared.PhysMemRead.3" file="shared_pseudocode.xml" hover="function: (PhysMemRetStatus, bits(8*size)) PhysMemRead(AddressDescriptor desc, integer size, AccessDescriptor accdesc)">PhysMemRead</a>(walkaddress, N DIV 8, walkaccess);</line>
<line>    if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(memstatus) then</line>
<line>        boolean iswrite = FALSE;</line>
<line>        fault = <a link="impl-shared.HandleExternalTTWAbort.6" file="shared_pseudocode.xml" hover="function: FaultRecord HandleExternalTTWAbort(PhysMemRetStatus memretstatus, boolean iswrite, AddressDescriptor memaddrdesc, AccessDescriptor accdesc, integer size, FaultRecord input_fault)">HandleExternalTTWAbort</a>(memstatus, iswrite, walkaddress,</line>
<line>                                       walkaccess, N DIV 8, fault);</line>
<line>        if <a link="impl-shared.IsFault.1" file="shared_pseudocode.xml" hover="function: boolean IsFault(AddressDescriptor addrdesc)">IsFault</a>(fault.statuscode) then</line>
<line>            return (fault, bits(N) UNKNOWN);</line>
<line></line>
<line>    if ee == '1' then</line>
<line>        descriptor = <a link="impl-shared.BigEndianReverse.1" file="shared_pseudocode.xml" hover="function: bits(width) BigEndianReverse (bits(width) value)">BigEndianReverse</a>(descriptor);</line>
<line></line>
<line>    return (fault, descriptor);</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/HasUnprivileged" mylink="shared.translation.vmsa.HasUnprivileged" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// HasUnprivileged()</line>
<line>// =================</line>
<line>// Returns whether a translation regime serves EL0 as well as a higher EL</line>
<line></line>
<line link="impl-shared.HasUnprivileged.1" hover="function: boolean HasUnprivileged(Regime regime)" conts="HasUnprivileged">boolean <anchor link="impl-shared.HasUnprivileged.1" hover="function: boolean HasUnprivileged(Regime regime)">HasUnprivileged</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime)</line>
<line>    return (regime IN {</line>
<line>        <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a>,</line>
<line>        <a link="Regime_EL30" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL30</a>,</line>
<line>        <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a></line>
<line>    });</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/Regime" mylink="shared.translation.vmsa.Regime" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// Regime</line>
<line>// ======</line>
<line>// Translation regimes</line>
<line></line>
<line link="Regime" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }" conts="Regime">enumeration <anchor link="Regime" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</anchor> {</line>
<line link="Regime_EL3" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }" conts="Regime_EL3">    <anchor link="Regime_EL3" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL3</anchor>,            // EL3</line>
<line link="Regime_EL30" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }" conts="Regime_EL30">    <anchor link="Regime_EL30" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL30</anchor>,           // EL3&amp;0 (PL1&amp;0 when EL3 is AArch32)</line>
<line link="Regime_EL2" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }" conts="Regime_EL2">    <anchor link="Regime_EL2" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</anchor>,            // EL2</line>
<line link="Regime_EL20" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }" conts="Regime_EL20">    <anchor link="Regime_EL20" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</anchor>,           // EL2&amp;0</line>
<line link="Regime_EL10" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }" conts="Regime_EL10">    <anchor link="Regime_EL10" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</anchor>            // EL1&amp;0</line>
<line>};</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/RegimeUsingAArch32" mylink="shared.translation.vmsa.RegimeUsingAArch32" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// RegimeUsingAArch32()</line>
<line>// ====================</line>
<line>// Determine if the EL controlling the regime executes in AArch32 state</line>
<line></line>
<line link="impl-shared.RegimeUsingAArch32.1" hover="function: boolean RegimeUsingAArch32(Regime regime)" conts="RegimeUsingAArch32">boolean <anchor link="impl-shared.RegimeUsingAArch32.1" hover="function: boolean RegimeUsingAArch32(Regime regime)">RegimeUsingAArch32</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime)</line>
<line>    case regime of</line>
<line>        when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> return <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
<line>        when <a link="Regime_EL30" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL30</a> return TRUE;</line>
<line>        when <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a> return FALSE;</line>
<line>        when <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>  return <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>        when <a link="Regime_EL3" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL3</a>  return FALSE;</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/S1TTWParams" mylink="shared.translation.vmsa.S1TTWParams" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// S1TTWParams</line>
<line>// ===========</line>
<line>// Register fields corresponding to stage 1 translation</line>
<line>// For A32-VMSA, if noted, they correspond to A32-LPAE (Long descriptor format)</line>
<line></line>
<line>type S1TTWParams is (</line>
<line>// A64-VMSA exclusive parameters</line>
<line>    bit         ha,         // TCR_ELx.HA</line>
<line>    bit         hd,         // TCR_ELx.HD</line>
<line>    bit         tbi,        // TCR_ELx.TBI{x}</line>
<line>    bit         tbid,       // TCR_ELx.TBID{x}</line>
<line>    bit         nfd,        // TCR_EL1.NFDx or TCR_EL2.NFDx when HCR_EL2.E2H == '1'</line>
<line>    bit         e0pd,       // TCR_EL1.E0PDx or TCR_EL2.E0PDx when HCR_EL2.E2H == '1'</line>
<line>    bit         d128,       // TCR_ELx.D128</line>
<line>    bit         aie,         // (TCR2_ELx/TCR_EL3).AIE</line>
<line>    MAIRType    mair2,       // MAIR2_ELx</line>
<line>    bit         ds,         // TCR_ELx.DS</line>
<line>    bits(3)     ps,         // TCR_ELx.{I}PS</line>
<line>    bits(6)     txsz,       // TCR_ELx.TxSZ</line>
<line>    bit         epan,       // SCTLR_EL1.EPAN or SCTLR_EL2.EPAN when HCR_EL2.E2H == '1'</line>
<line>    bit         dct,        // HCR_EL2.DCT</line>
<line>    bit         nv1,        // HCR_EL2.NV1</line>
<line>    bit         cmow,       // SCTLR_EL1.CMOW or SCTLR_EL2.CMOW when HCR_EL2.E2H == '1'</line>
<line>    bit         pnch,       // TCR{2}_ELx.PnCH</line>
<line>    bit         disch,      // TCR{2}_ELx.DisCH</line>
<line>    bit         haft,       // TCR{2}_ELx.HAFT</line>
<line>    bit         mtx,        // TCR_ELx.MTX{y}</line>
<line>    bits(2)     skl,        // TCR_ELx.SKL</line>
<line>    bit         pie,        // TCR2_ELx.PIE or TCR_EL3.PIE</line>
<line>    S1PIRType   pir,        // PIR_ELx</line>
<line>    S1PIRType   pire0,      // PIRE0_EL1 or PIRE0_EL2 when HCR_EL2.E2H == '1'</line>
<line>    bit         emec,       // SCTLR2_EL2.EMEC or SCTLR2_EL3.EMEC</line>
<line>    bit         amec,       // TCR2_EL2.AMEC0 or TCR2_EL2.AMEC1 when HCR_EL2.E2H == '1'</line>
<line></line>
<line>// A32-VMSA exclusive parameters</line>
<line>    bits(3)     t0sz,       // TTBCR.T0SZ</line>
<line>    bits(3)     t1sz,       // TTBCR.T1SZ</line>
<line>    bit         uwxn,       // SCTLR.UWXN</line>
<line></line>
<line>// Parameters common to both A64-VMSA &amp; A32-VMSA (A64/A32)</line>
<line>    <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a>         tgx,        // TCR_ELx.TGx      / Always TGx_4KB</line>
<line>    bits(2)     irgn,       // TCR_ELx.IRGNx    / TTBCR.IRGNx or HTCR.IRGN0</line>
<line>    bits(2)     orgn,       // TCR_ELx.ORGNx    / TTBCR.ORGNx or HTCR.ORGN0</line>
<line>    bits(2)     sh,         // TCR_ELx.SHx      / TTBCR.SHx or HTCR.SH0</line>
<line>    bit         hpd,        // TCR_ELx.HPD{x}   / TTBCR2.HPDx or HTCR.HPD</line>
<line>    bit         ee,         // SCTLR_ELx.EE     / SCTLR.EE or HSCTLR.EE</line>
<line>    bit         wxn,        // SCTLR_ELx.WXN    / SCTLR.WXN or HSCTLR.WXN</line>
<line>    bit         ntlsmd,     // SCTLR_ELx.nTLSMD / SCTLR.nTLSMD or HSCTLR.nTLSMD</line>
<line>    bit         dc,         // HCR_EL2.DC       / HCR.DC</line>
<line>    bit         sif,        // SCR_EL3.SIF      / SCR.SIF</line>
<line>    MAIRType    mair        // MAIR_ELx         / MAIR1:MAIR0 or HMAIR1:HMAIR0</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/S2TTWParams" mylink="shared.translation.vmsa.S2TTWParams" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// S2TTWParams</line>
<line>// ===========</line>
<line>// Register fields corresponding to stage 2 translation.</line>
<line></line>
<line>type S2TTWParams is (</line>
<line>// A64-VMSA exclusive parameters</line>
<line>    bit         ha,         // VTCR_EL2.HA</line>
<line>    bit         hd,         // VTCR_EL2.HD</line>
<line>    bit         sl2,        // V{S}TCR_EL2.SL2</line>
<line>    bit         ds,         // VTCR_EL2.DS</line>
<line>    bit         d128,       // VTCR_ELx.D128</line>
<line>    bit         sw,         // VSTCR_EL2.SW</line>
<line>    bit         nsw,        // VTCR_EL2.NSW</line>
<line>    bit         sa,         // VSTCR_EL2.SA</line>
<line>    bit         nsa,        // VTCR_EL2.NSA</line>
<line>    bits(3)     ps,         // VTCR_EL2.PS</line>
<line>    bits(6)     txsz,       // V{S}TCR_EL2.T0SZ</line>
<line>    bit         fwb,        // HCR_EL2.PTW</line>
<line>    bit         cmow,       // HCRX_EL2.CMOW</line>
<line>    bits(2)     skl,        // VTCR_EL2.SKL</line>
<line>    bit         s2pie,      // VTCR_EL2.S2PIE</line>
<line>    S2PIRType   s2pir,      // S2PIR_EL2</line>
<line>    bit         tl0,        // VTCR_EL2.TL0</line>
<line>    bit         tl1,        // VTCR_EL2.TL1</line>
<line>    bit         assuredonly,// VTCR_EL2.AssuredOnly</line>
<line>    bit         haft,       // VTCR_EL2.HAFT</line>
<line>    bit         emec,       // SCTLR2_EL2.EMEC</line>
<line></line>
<line>// A32-VMSA exclusive parameters</line>
<line>    bit         s,          // VTCR.S</line>
<line>    bits(4)     t0sz,       // VTCR.T0SZ</line>
<line></line>
<line>// Parameters common to both A64-VMSA &amp; A32-VMSA if implemented (A64/A32)</line>
<line>    <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a>         tgx,        // V{S}TCR_EL2.TG0  / Always TGx_4KB</line>
<line>    bits(2)     sl0,        // V{S}TCR_EL2.SL0  / VTCR.SL0</line>
<line>    bits(2)     irgn,       // VTCR_EL2.IRGN0   / VTCR.IRGN0</line>
<line>    bits(2)     orgn,       // VTCR_EL2.ORGN0   / VTCR.ORGN0</line>
<line>    bits(2)     sh,         // VTCR_EL2.SH0     / VTCR.SH0</line>
<line>    bit         ee,         // SCTLR_EL2.EE     / HSCTLR.EE</line>
<line>    bit         ptw,        // HCR_EL2.PTW      / HCR.PTW</line>
<line>    bit         vm          // HCR_EL2.VM       / HCR.VM</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/SDFType" mylink="shared.translation.vmsa.SDFType" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SDFType</line>
<line>// =======</line>
<line>// Short-descriptor format type</line>
<line></line>
<line link="SDFType" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }" conts="SDFType">enumeration <anchor link="SDFType" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType</anchor> {</line>
<line link="SDFType_Table" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }" conts="SDFType_Table">    <anchor link="SDFType_Table" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_Table</anchor>,</line>
<line link="SDFType_Invalid" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }" conts="SDFType_Invalid">    <anchor link="SDFType_Invalid" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_Invalid</anchor>,</line>
<line link="SDFType_Supersection" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }" conts="SDFType_Supersection">    <anchor link="SDFType_Supersection" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_Supersection</anchor>,</line>
<line link="SDFType_Section" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }" conts="SDFType_Section">    <anchor link="SDFType_Section" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_Section</anchor>,</line>
<line link="SDFType_LargePage" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }" conts="SDFType_LargePage">    <anchor link="SDFType_LargePage" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_LargePage</anchor>,</line>
<line link="SDFType_SmallPage" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }" conts="SDFType_SmallPage">    <anchor link="SDFType_SmallPage" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType_SmallPage</anchor></line>
<line>};</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/SecurityStateForRegime" mylink="shared.translation.vmsa.SecurityStateForRegime" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// SecurityStateForRegime()</line>
<line>// ========================</line>
<line>// Return the Security State of the given translation regime</line>
<line></line>
<line link="impl-shared.SecurityStateForRegime.1" hover="function: SecurityState SecurityStateForRegime(Regime regime)" conts="SecurityStateForRegime">SecurityState <anchor link="impl-shared.SecurityStateForRegime.1" hover="function: SecurityState SecurityStateForRegime(Regime regime)">SecurityStateForRegime</anchor>(<a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a> regime)</line>
<line>    case regime of</line>
<line>        when <a link="Regime_EL3" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL3</a>     return <a link="impl-shared.SecurityStateAtEL.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)">SecurityStateAtEL</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>);</line>
<line>        when <a link="Regime_EL30" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL30</a>    return <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a>; // A32 EL3 is always Secure</line>
<line>        when <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>     return <a link="impl-shared.SecurityStateAtEL.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)">SecurityStateAtEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>        when <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a>    return <a link="impl-shared.SecurityStateAtEL.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)">SecurityStateAtEL</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>);</line>
<line>        when <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a>    return <a link="impl-shared.SecurityStateAtEL.1" file="shared_pseudocode.xml" hover="function: SecurityState SecurityStateAtEL(bits(2) EL)">SecurityStateAtEL</a>(<a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a>);</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/StageOA" mylink="shared.translation.vmsa.StageOA" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// StageOA()</line>
<line>// =========</line>
<line>// Given the final walk state (a page or block descriptor), map the untranslated</line>
<line>// input address bits to the output address</line>
<line></line>
<line link="impl-shared.StageOA.4" hover="function: FullAddress StageOA(bits(64) ia, bit d128, TGx tgx, TTWState walkstate)" conts="StageOA">FullAddress <anchor link="impl-shared.StageOA.4" hover="function: FullAddress StageOA(bits(64) ia, bit d128, TGx tgx, TTWState walkstate)">StageOA</anchor>(bits(64) ia, bit d128, <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tgx, <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a> walkstate)</line>
<line>    // Output Address</line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a> oa;</line>
<line>    integer csize;</line>
<line></line>
<line>    tsize = <a link="impl-shared.TranslationSize.3" file="shared_pseudocode.xml" hover="function: integer TranslationSize(bit d128, TGx tgx, integer level)">TranslationSize</a>(d128, tgx, walkstate.level);</line>
<line>    if walkstate.contiguous == '1' then</line>
<line>        csize = <a link="impl-shared.ContiguousSize.3" file="shared_pseudocode.xml" hover="function: integer ContiguousSize(bit d128, TGx tgx, integer level)">ContiguousSize</a>(d128, tgx, walkstate.level);</line>
<line>    else</line>
<line>        csize = 0;</line>
<line></line>
<line>    ia_msb = tsize + csize;</line>
<line>    oa.paspace = walkstate.baseaddress.paspace;</line>
<line>    oa.address = walkstate.baseaddress.address&lt;55:ia_msb&gt;:ia&lt;ia_msb-1:0&gt;;</line>
<line></line>
<line>    return oa;</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/TGx" mylink="shared.translation.vmsa.TGx" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TGx</line>
<line>// ===</line>
<line>// Translation granules sizes</line>
<line></line>
<line link="TGx" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }" conts="TGx">enumeration <anchor link="TGx" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</anchor> {</line>
<line link="TGx_4KB" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }" conts="TGx_4KB">    <anchor link="TGx_4KB" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</anchor>,</line>
<line link="TGx_16KB" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }" conts="TGx_16KB">    <anchor link="TGx_16KB" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</anchor>,</line>
<line link="TGx_64KB" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }" conts="TGx_64KB">    <anchor link="TGx_64KB" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</anchor></line>
<line>};</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/TGxGranuleBits" mylink="shared.translation.vmsa.TGxGranuleBits" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TGxGranuleBits()</line>
<line>// ================</line>
<line>// Retrieve the address size, in bits, of a granule</line>
<line></line>
<line link="impl-shared.TGxGranuleBits.1" hover="function: integer TGxGranuleBits(TGx tgx)" conts="TGxGranuleBits">integer <anchor link="impl-shared.TGxGranuleBits.1" hover="function: integer TGxGranuleBits(TGx tgx)">TGxGranuleBits</anchor>(<a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tgx)</line>
<line>    case tgx of</line>
<line>        when <a link="TGx_4KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_4KB</a>  return 12;</line>
<line>        when <a link="TGx_16KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_16KB</a> return 14;</line>
<line>        when <a link="TGx_64KB" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx_64KB</a> return 16;</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/TLBContext" mylink="shared.translation.vmsa.TLBContext" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TLBContext</line>
<line>// ==========</line>
<line>// Translation context compared on TLB lookups and invalidations, promoting a TLB hit on match</line>
<line></line>
<line link="TLBContext" hover="type TLBContext is ( SecurityState ss, Regime regime, bits(16) vmid, bits(16) asid, bit nG, PASpace ipaspace, boolean includes_s1, boolean includes_s2, boolean includes_gpt, bits(64) ia, TGx tg, bit cnp, integer level, boolean isd128, bit xs )" conts="TLBContext">type <anchor link="TLBContext" hover="type TLBContext is ( SecurityState ss, Regime regime, bits(16) vmid, bits(16) asid, bit nG, PASpace ipaspace, boolean includes_s1, boolean includes_s2, boolean includes_gpt, bits(64) ia, TGx tg, bit cnp, integer level, boolean isd128, bit xs )">TLBContext</anchor> is (</line>
<line>    <a link="SecurityState" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SecurityState</a> ss,</line>
<line>    <a link="Regime" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime</a>        regime,</line>
<line>    bits(16)      vmid,</line>
<line>    bits(16)      asid,</line>
<line>    bit           nG,</line>
<line>    <a link="PASpace" file="shared_pseudocode.xml" hover="enumeration PASpace { PAS_NonSecure, PAS_Secure, PAS_Root, PAS_Realm }">PASpace</a>       ipaspace, // Used in stage 2 lookups &amp; invalidations only</line>
<line>    boolean       includes_s1,</line>
<line>    boolean       includes_s2,</line>
<line>    boolean       includes_gpt,</line>
<line>    bits(64)      ia,       // Input Address</line>
<line>    <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a>           tg,</line>
<line>    bit           cnp,</line>
<line>    integer       level,    // Assist TLBI level hints (FEAT_TTL)</line>
<line>    boolean       isd128,</line>
<line>    bit           xs        // XS attribute (FEAT_XS)</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/TLBRecord" mylink="shared.translation.vmsa.TLBRecord" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TLBRecord</line>
<line>// =========</line>
<line>// Translation output as a TLB payload</line>
<line></line>
<line link="TLBRecord" hover="type TLBRecord is ( TLBContext context, TTWState walkstate, integer blocksize, integer contigsize, bits(128) s1descriptor, bits(128) s2descriptor )" conts="TLBRecord">type <anchor link="TLBRecord" hover="type TLBRecord is ( TLBContext context, TTWState walkstate, integer blocksize, integer contigsize, bits(128) s1descriptor, bits(128) s2descriptor )">TLBRecord</anchor> is (</line>
<line>    <a link="TLBContext" file="shared_pseudocode.xml" hover="type TLBContext is ( SecurityState ss, Regime regime, bits(16) vmid, bits(16) asid, bit nG, PASpace ipaspace, boolean includes_s1, boolean includes_s2, boolean includes_gpt, bits(64) ia, TGx tg, bit cnp, integer level, boolean isd128, bit xs )">TLBContext</a>  context,</line>
<line>    <a link="TTWState" file="shared_pseudocode.xml" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</a>    walkstate,</line>
<line>    integer     blocksize,    // Number of bits directly mapped from IA to OA</line>
<line>    integer     contigsize,   // Number of entries log 2 marking a contiguous output range</line>
<line>    bits(128)   s1descriptor, // Stage 1 leaf descriptor in memory (valid if the TLB caches stage 1)</line>
<line>    bits(128)   s2descriptor  // Stage 2 leaf descriptor in memory (valid if the TLB caches stage 2)</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/TTWState" mylink="shared.translation.vmsa.TTWState" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TTWState</line>
<line>// ========</line>
<line>// Translation table walk state</line>
<line></line>
<line link="TTWState" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )" conts="TTWState">type <anchor link="TTWState" hover="type TTWState is ( boolean istable, integer level, FullAddress baseaddress, bit contiguous, boolean s1assured, bit s2assuredonly, bit disch, bit nG, bit guardedpage, SDFType sdftype, bits(4) domain, MemoryAttributes memattrs, Permissions permissions )">TTWState</anchor> is (</line>
<line>    boolean             istable,</line>
<line>    integer             level,</line>
<line>    <a link="FullAddress" file="shared_pseudocode.xml" hover="type FullAddress is ( PASpace paspace, bits(56) address )">FullAddress</a>         baseaddress,</line>
<line>    bit                 contiguous,</line>
<line>    boolean             s1assured,      // Stage 1 Assured Translation Property</line>
<line>    bit                 s2assuredonly,  // Stage 2 AssuredOnly attribute</line>
<line>    bit                 disch,          // Stage 1 Disable Contiguous Hint</line>
<line>    bit                 nG,</line>
<line>    bit                 guardedpage,</line>
<line>    <a link="SDFType" file="shared_pseudocode.xml" hover="enumeration SDFType { SDFType_Table, SDFType_Invalid, SDFType_Supersection, SDFType_Section, SDFType_LargePage, SDFType_SmallPage }">SDFType</a>             sdftype,    // AArch32 Short-descriptor format walk only</line>
<line>    bits(4)             domain,     // AArch32 Short-descriptor format walk only</line>
<line>    <a link="MemoryAttributes" file="shared_pseudocode.xml" hover="type MemoryAttributes is ( MemType memtype, DeviceType device, MemAttrHints inner, MemAttrHints outer, Shareability shareability, MemTagType tags, boolean notagaccess, bit xs )">MemoryAttributes</a>    memattrs,</line>
<line>    <a link="Permissions" file="shared_pseudocode.xml" hover="type Permissions is ( bits(2) ap_table, bit xn_table, bit pxn_table, bit uxn_table, bits(3) ap, bit xn, bit uxn, bit pxn, bits(4) ppi, bits(4) upi, bit ndirty, bits(4) s2pi, bit s2dirty, bits(4) po_index, bits(4) s2po_index, bits(2) s2ap, bit s2tag_na, bit s2xnx, bit s2xn )">Permissions</a>         permissions</line>
<line>)</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/TranslationRegime" mylink="shared.translation.vmsa.TranslationRegime" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TranslationRegime()</line>
<line>// ===================</line>
<line>// Select the translation regime given the target EL and PE state</line>
<line></line>
<line link="impl-shared.TranslationRegime.1" hover="function: Regime TranslationRegime(bits(2) el)" conts="TranslationRegime">Regime <anchor link="impl-shared.TranslationRegime.1" hover="function: Regime TranslationRegime(bits(2) el)">TranslationRegime</anchor>(bits(2) el)</line>
<line>    if el == <a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a> then</line>
<line>        return if <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then <a link="Regime_EL30" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL30</a> else <a link="Regime_EL3" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL3</a>;</line>
<line>    elsif el == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then</line>
<line>        return if <a link="impl-shared.ELIsInHost.1" file="shared_pseudocode.xml" hover="function: boolean ELIsInHost(bits(2) el)">ELIsInHost</a>(<a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a>) then <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a> else <a link="Regime_EL2" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL2</a>;</line>
<line>    elsif el == <a link="EL1" file="shared_pseudocode.xml" hover="constant bits(2) EL1 = '01'">EL1</a> then</line>
<line>        return <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a>;</line>
<line>    elsif el == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then</line>
<line>        if <a link="impl-shared.CurrentSecurityState.0" file="shared_pseudocode.xml" hover="function: SecurityState CurrentSecurityState()">CurrentSecurityState</a>() == <a link="SS_Secure" file="shared_pseudocode.xml" hover="enumeration SecurityState { SS_NonSecure, SS_Root, SS_Realm, SS_Secure }">SS_Secure</a> &amp;&amp; <a link="impl-shared.ELUsingAArch32.1" file="shared_pseudocode.xml" hover="function: boolean ELUsingAArch32(bits(2) el)">ELUsingAArch32</a>(<a link="EL3" file="shared_pseudocode.xml" hover="constant bits(2) EL3 = '11'">EL3</a>) then</line>
<line>            return <a link="Regime_EL30" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL30</a>;</line>
<line>        elsif <a link="impl-shared.ELIsInHost.1" file="shared_pseudocode.xml" hover="function: boolean ELIsInHost(bits(2) el)">ELIsInHost</a>(<a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>) then</line>
<line>            return <a link="Regime_EL20" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL20</a>;</line>
<line>        else</line>
<line>            return <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a>;</line>
<line>    else</line>
<line>        <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>();</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/TranslationSize" mylink="shared.translation.vmsa.TranslationSize" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// TranslationSize()</line>
<line>// =================</line>
<line>// Compute the number of bits directly mapped from the input address</line>
<line>// to the output address</line>
<line></line>
<line link="impl-shared.TranslationSize.3" hover="function: integer TranslationSize(bit d128, TGx tgx, integer level)" conts="TranslationSize">integer <anchor link="impl-shared.TranslationSize.3" hover="function: integer TranslationSize(bit d128, TGx tgx, integer level)">TranslationSize</anchor>(bit d128, <a link="TGx" file="shared_pseudocode.xml" hover="enumeration TGx { TGx_4KB, TGx_16KB, TGx_64KB }">TGx</a> tgx, integer level)</line>
<line>    granulebits = <a link="impl-shared.TGxGranuleBits.1" file="shared_pseudocode.xml" hover="function: integer TGxGranuleBits(TGx tgx)">TGxGranuleBits</a>(tgx);</line>
<line>    descsizelog2 = if d128 == '1' then 4 else 3;</line>
<line>    blockbits   = (<a link="FINAL_LEVEL" file="shared_pseudocode.xml" hover="constant integer FINAL_LEVEL = 3">FINAL_LEVEL</a> - level) * (granulebits - descsizelog2);</line>
<line></line>
<line>    return granulebits + blockbits;</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/UseASID" mylink="shared.translation.vmsa.UseASID" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// UseASID()</line>
<line>// =========</line>
<line>// Determine whether the translation context for the access requires ASID or is a global entry</line>
<line></line>
<line link="impl-shared.UseASID.1" hover="function: boolean UseASID(TLBContext access)" conts="UseASID">boolean <anchor link="impl-shared.UseASID.1" hover="function: boolean UseASID(TLBContext access)">UseASID</anchor>(<a link="TLBContext" file="shared_pseudocode.xml" hover="type TLBContext is ( SecurityState ss, Regime regime, bits(16) vmid, bits(16) asid, bit nG, PASpace ipaspace, boolean includes_s1, boolean includes_s2, boolean includes_gpt, bits(64) ia, TGx tg, bit cnp, integer level, boolean isd128, bit xs )">TLBContext</a> access)</line>
<line>    return <a link="impl-shared.HasUnprivileged.1" file="shared_pseudocode.xml" hover="function: boolean HasUnprivileged(Regime regime)">HasUnprivileged</a>(access.regime);</line>
</pstext>
    </ps>
    <ps name="shared/translation/vmsa/UseVMID" mylink="shared.translation.vmsa.UseVMID" enclabels="" sections="1" secttype="Library">
      <pstext mayhavelinks="1" section="Functions" rep_section="functions"><line>// UseVMID()</line>
<line>// =========</line>
<line>// Determine whether the translation context for the access requires VMID to match a TLB entry</line>
<line></line>
<line link="impl-shared.UseVMID.1" hover="function: boolean UseVMID(TLBContext access)" conts="UseVMID">boolean <anchor link="impl-shared.UseVMID.1" hover="function: boolean UseVMID(TLBContext access)">UseVMID</anchor>(<a link="TLBContext" file="shared_pseudocode.xml" hover="type TLBContext is ( SecurityState ss, Regime regime, bits(16) vmid, bits(16) asid, bit nG, PASpace ipaspace, boolean includes_s1, boolean includes_s2, boolean includes_gpt, bits(64) ia, TGx tg, bit cnp, integer level, boolean isd128, bit xs )">TLBContext</a> access)</line>
<line>    return access.regime == <a link="Regime_EL10" file="shared_pseudocode.xml" hover="enumeration Regime { Regime_EL3, Regime_EL30, Regime_EL2, Regime_EL20, Regime_EL10 }">Regime_EL10</a> &amp;&amp; <a link="impl-shared.EL2Enabled.0" file="shared_pseudocode.xml" hover="function: boolean EL2Enabled()">EL2Enabled</a>();</line>
</pstext>
    </ps>
  </ps_section>
</instructionsection>
</file>
  </sect1>
<file type="constraint_text_mappings" file="constraint_text_mappings.xml">

<!-- Map constraint IDs on to humanly-readable text. This is used by the XSL
     that handles the CONSTRAINED UNPREDICTABLE behaviour of instructions. -->

<!-- Copyright (c) 2016-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and
     distributed in accordance with the terms of the agreement entered
     into by Arm and the party that Arm delivered this document to. -->

<constraint_text_mappings>
  <constraint_text_mapping>
    <constraint_id>Constraint_NONE</constraint_id>
    <constraint_text>The instruction executes as described, with no change to its behavior and no additional side effects.</constraint_text>
  </constraint_text_mapping>
  <constraint_text_mapping>
    <constraint_id>Constraint_UNKNOWN</constraint_id>
    <constraint_text>The value in the destination register is <arm-defined-word>unknown</arm-defined-word>.</constraint_text>
  </constraint_text_mapping>
  <constraint_text_mapping>
    <constraint_id>Constraint_UNDEF</constraint_id>
    <constraint_text>The instruction is <arm-defined-word>undefined</arm-defined-word>.</constraint_text>
  </constraint_text_mapping>
  <constraint_text_mapping>
    <constraint_id>Constraint_NOP</constraint_id>
    <constraint_text>The instruction executes as <instruction>NOP</instruction>.</constraint_text>
  </constraint_text_mapping>
  <constraint_text_mapping>
    <constraint_id>Constraint_UNCOND</constraint_id>
    <constraint_text>The instruction executes unconditionally.</constraint_text>
  </constraint_text_mapping>
  <constraint_text_mapping>
    <constraint_id>Constraint_COND</constraint_id>
    <constraint_text>The instruction executes conditionally.</constraint_text>
  </constraint_text_mapping>
  <constraint_text_mapping>
    <constraint_id>Constraint_WBSUPPRESS</constraint_id>
    <constraint_text>The instruction executes without writeback of the base address.</constraint_text>
  </constraint_text_mapping>
  <constraint_text_mapping>
    <constraint_id>Constraint_ADDITIONAL_DECODE</constraint_id>
    <constraint_text>The instruction executes with the additional decode: $pseudocode.</constraint_text>
  </constraint_text_mapping>
  <constraint_text_mapping>
    <constraint_id>Constraint_EXECUTES_AS_IF</constraint_id>
    <constraint_text>The instruction executes as if $pseudocode.</constraint_text>
  </constraint_text_mapping>
  <constraint_text_mapping>
    <constraint_id>Constraint_LDUNKNOWN</constraint_id>
    <constraint_text>The load instruction executes but the destination register takes an <arm-defined-word>unknown</arm-defined-word> value.</constraint_text>
  </constraint_text_mapping>
  <constraint_text_mapping>
    <constraint_id>Constraint_STUNKNOWN</constraint_id>
    <constraint_text>The store instruction executes but the value stored is <arm-defined-word>unknown</arm-defined-word>.</constraint_text>
  </constraint_text_mapping>
  <constraint_text_mapping>
    <constraint_id>Constraint_BASEUNKNOWN</constraint_id>
    <constraint_text>The store instruction executes but the value stored for the base register is <arm-defined-word>unknown</arm-defined-word>.</constraint_text>
  </constraint_text_mapping>
</constraint_text_mappings>
</file>
</allinstrs>
